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library verilog;
use verilog.vl_types.all;
entity losd_store_pipe_arbiter is
port(
oLDST_REQ : out vl_logic;
iLDST_BUSY : in vl_logic;
oLDST_ORDER : out vl_logic_vector(1 downto 0);
oLDST_MASK : out vl_logic_vector(3 downto 0);
oLDST_RW : out vl_logic;
oLDST_TID : out vl_logic_vector(13 downto 0);
oLDST_MMUMOD : out vl_logic_vector(1 downto 0);
oLDST_PDT : out vl_logic_vector(31 downto 0);
oLDST_ADDR : out vl_logic_vector(31 downto 0);
oLDST_DATA : out vl_logic_vector(31 downto 0);
iLDST_VALID : in vl_logic;
iLDST_PAGEFAULT : in vl_logic;
iLDST_MMU_FLAGS : in vl_logic_vector(13 downto 0);
iLDST_DATA : in vl_logic_vector(31 downto 0);
iUSE_SEL : in vl_logic;
iEXE_REQ : in vl_logic;
oEXE_BUSY : out vl_logic;
iEXE_ORDER : in vl_logic_vector(1 downto 0);
iEXE_MASK : in vl_logic_vector(3 downto 0);
iEXE_RW : in vl_logic;
iEXE_TID : in vl_logic_vector(13 downto 0);
iEXE_MMUMOD : in vl_logic_vector(1 downto 0);
iEXE_PDT : in vl_logic_vector(31 downto 0);
iEXE_ADDR : in vl_logic_vector(31 downto 0);
iEXE_DATA : in vl_logic_vector(31 downto 0);
oEXE_REQ : out vl_logic;
oEXE_PAGEFAULT : out vl_logic;
oEXE_MMU_FLAGS : out vl_logic_vector(13 downto 0);
oEXE_DATA : out vl_logic_vector(31 downto 0);
iEXCEPT_REQ : in vl_logic;
oEXCEPT_BUSY : out vl_logic;
iEXCEPT_ORDER : in vl_logic_vector(1 downto 0);
iEXCEPT_RW : in vl_logic;
iEXCEPT_TID : in vl_logic_vector(13 downto 0);
iEXCEPT_MMUMOD : in vl_logic_vector(1 downto 0);
iEXCEPT_PDT : in vl_logic_vector(31 downto 0);
iEXCEPT_ADDR : in vl_logic_vector(31 downto 0);
iEXCEPT_DATA : in vl_logic_vector(31 downto 0);
oEXCEPT_REQ : out vl_logic;
oEXCEPT_DATA : out vl_logic_vector(31 downto 0)
);
end losd_store_pipe_arbiter;
|
-- Copyright (c) 2017 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-- Title : 1R1W RF primarily for Xilinx Series 7 devices
-------------------------------------------------------------------------------
-- File : s7_rf_1wr_1rd.vhdl
-- Author : Lasse Lehtonen <lasse.lehtonen@phnet.fi>
-- Company : Tampere University
-- Created : 2017
-- Last update: 2018-06-09
-- Platform : Xilinx Series 7
-------------------------------------------------------------------------------
-- Description: Register file with one read and one write port.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017 1.0 lasse Initial version
-- 2018-06-09 1.1 tervoa Cleanup for HDB
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.tce_util.all;
entity s7_rf_1wr_1rd is
generic (
width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_rd_in : in std_logic;
data_rd_out : out std_logic_vector(width_g-1 downto 0);
addr_rd_in : in std_logic_vector(bit_width(depth_g)-1 downto 0);
load_wr_in : in std_logic;
data_wr_in : in std_logic_vector(width_g-1 downto 0);
addr_wr_in : in std_logic_vector(bit_width(depth_g)-1 downto 0)
);
end entity s7_rf_1wr_1rd;
architecture rtl of s7_rf_1wr_1rd is
type reg_type is array (0 to depth_g-1) of std_logic_vector(width_g-1 downto 0);
signal reg_r : reg_type;
begin
main_sp : process (clk)
begin
if clk'event and clk = '1' then
if load_wr_in = '1' then
reg_r(to_integer(unsigned(addr_wr_in))) <= data_wr_in;
end if;
end if;
end process main_sp;
data_rd_out <= reg_r(to_integer(unsigned(addr_rd_in)));
end architecture rtl;
|
-- Copyright (c) 2017 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--
-------------------------------------------------------------------------------
-- Title : 1R1W RF primarily for Xilinx Series 7 devices
-------------------------------------------------------------------------------
-- File : s7_rf_1wr_1rd.vhdl
-- Author : Lasse Lehtonen <lasse.lehtonen@phnet.fi>
-- Company : Tampere University
-- Created : 2017
-- Last update: 2018-06-09
-- Platform : Xilinx Series 7
-------------------------------------------------------------------------------
-- Description: Register file with one read and one write port.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017 1.0 lasse Initial version
-- 2018-06-09 1.1 tervoa Cleanup for HDB
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.tce_util.all;
entity s7_rf_1wr_1rd is
generic (
width_g : integer;
depth_g : integer);
port (
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_rd_in : in std_logic;
data_rd_out : out std_logic_vector(width_g-1 downto 0);
addr_rd_in : in std_logic_vector(bit_width(depth_g)-1 downto 0);
load_wr_in : in std_logic;
data_wr_in : in std_logic_vector(width_g-1 downto 0);
addr_wr_in : in std_logic_vector(bit_width(depth_g)-1 downto 0)
);
end entity s7_rf_1wr_1rd;
architecture rtl of s7_rf_1wr_1rd is
type reg_type is array (0 to depth_g-1) of std_logic_vector(width_g-1 downto 0);
signal reg_r : reg_type;
begin
main_sp : process (clk)
begin
if clk'event and clk = '1' then
if load_wr_in = '1' then
reg_r(to_integer(unsigned(addr_wr_in))) <= data_wr_in;
end if;
end if;
end process main_sp;
data_rd_out <= reg_r(to_integer(unsigned(addr_rd_in)));
end architecture rtl;
|
--------------------------------------------------------------------------------
--! @file fifo2shiftreg.vhd
--! @brief Writes data into FIFO, then this module pushes them out
--! through serial bus (SPI). DIN is captured simultaneously.
--! @author Yuan Mei
--!
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY fifo2shiftreg IS
GENERIC (
DATA_WIDTH : positive := 32; -- parallel data width
CLK_DIV_WIDTH : positive := 16;
DELAY_AFTER_SYNCn : natural := 0; -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL : std_logic := '0'; -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE : std_logic := '1'; -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE : std_logic := '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
);
PORT (
CLK : IN std_logic; -- clock
RESET : IN std_logic; -- reset
-- input data interface
WR_CLK : IN std_logic; -- FIFO write clock
DINFIFO : IN std_logic_vector(15 DOWNTO 0);
WR_EN : IN std_logic;
WR_PULSE : IN std_logic; -- one pulse writes one word, regardless of pulse duration
FULL : OUT std_logic;
-- captured data
BUSY : OUT std_logic;
DATAOUT : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
-- serial interface
CLK_DIV : IN std_logic_vector(CLK_DIV_WIDTH-1 DOWNTO 0); -- SCLK freq is CLK / 2**(CLK_DIV)
SCLK : OUT std_logic;
DOUT : OUT std_logic;
SYNCn : OUT std_logic;
DIN : IN std_logic
);
END fifo2shiftreg;
ARCHITECTURE Behavioral OF fifo2shiftreg IS
COMPONENT shiftreg_drive
GENERIC (
DATA_WIDTH : positive := 32; -- parallel data width
CLK_DIV_WIDTH : positive := 16;
DELAY_AFTER_SYNCn : natural := 0; -- number of SCLK cycles' wait after falling edge OF SYNCn
SCLK_IDLE_LEVEL : std_logic := '0'; -- High or Low for SCLK when not switching
DOUT_DRIVE_EDGE : std_logic := '1'; -- 1/0 rising/falling edge of SCLK drives new DOUT bit
DIN_CAPTURE_EDGE : std_logic := '0' -- 1/0 rising/falling edge of SCLK captures new DIN bit
);
PORT (
CLK : IN std_logic; -- clock
RESET : IN std_logic; -- reset
-- internal data interface
CLK_DIV : IN std_logic_vector(CLK_DIV_WIDTH-1 DOWNTO 0); -- SCLK freq is CLK / 2**(CLK_DIV)
DATAIN : IN std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
START : IN std_logic;
BUSY : OUT std_logic;
DATAOUT : OUT std_logic_vector(DATA_WIDTH-1 DOWNTO 0);
-- external serial interface
SCLK : OUT std_logic;
DOUT : OUT std_logic;
SYNCn : OUT std_logic;
DIN : IN std_logic
);
END COMPONENT;
--
COMPONENT edge_sync
GENERIC (
EDGE : std_logic := '1' -- '1' : rising edge, '0' falling edge
);
PORT (
RESET : IN std_logic;
CLK : IN std_logic;
EI : IN std_logic;
SO : OUT std_logic
);
END COMPONENT;
--
COMPONENT fifo16to32
PORT (
RST : IN std_logic;
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
DIN : IN std_logic_vector(15 DOWNTO 0);
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DOUT : OUT std_logic_vector(31 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic
);
END COMPONENT;
--
SIGNAL sd_start : std_logic;
SIGNAL sd_busy : std_logic;
--
SIGNAL fifo_dout : std_logic_vector(31 DOWNTO 0);
SIGNAL fifo_wr_en : std_logic;
SIGNAL fifo_rd_en : std_logic;
SIGNAL fifo_empty : std_logic;
--
SIGNAL es_so : std_logic;
BEGIN
sd : shiftreg_drive
GENERIC MAP (
DATA_WIDTH => DATA_WIDTH,
CLK_DIV_WIDTH => CLK_DIV_WIDTH,
DELAY_AFTER_SYNCn => DELAY_AFTER_SYNCn,
SCLK_IDLE_LEVEL => SCLK_IDLE_LEVEL,
DOUT_DRIVE_EDGE => DOUT_DRIVE_EDGE,
DIN_CAPTURE_EDGE => DIN_CAPTURE_EDGE
)
PORT MAP (
CLK => CLK,
RESET => RESET,
-- internal data interface
CLK_DIV => CLK_DIV,
DATAIN => fifo_dout(DATA_WIDTH-1 DOWNTO 0),
START => sd_start,
BUSY => sd_busy,
DATAOUT => DATAOUT,
-- external serial interface
SCLK => SCLK,
DOUT => DOUT,
SYNCn => SYNCn,
DIN => DIN
);
BUSY <= sd_busy;
fifo : fifo16to32
PORT MAP (
RST => RESET,
WR_CLK => WR_CLK,
RD_CLK => CLK,
DIN => DINFIFO,
WR_EN => fifo_wr_en,
RD_EN => fifo_rd_en,
DOUT => fifo_dout,
FULL => FULL,
EMPTY => fifo_empty
);
sd_start <= NOT fifo_empty;
-- rising edge of busy
rd_es : edge_sync
GENERIC MAP (
EDGE => '1' -- '1' : rising edge, '0' falling edge
)
PORT MAP (
RESET => RESET,
CLK => CLK,
EI => sd_busy,
SO => fifo_rd_en
);
wr_es : edge_sync
GENERIC MAP (
EDGE => '1' -- '1' : rising edge, '0' falling edge
)
PORT MAP (
RESET => RESET,
CLK => CLK,
EI => WR_PULSE,
SO => es_so
);
fifo_wr_en <= es_so OR WR_EN;
END Behavioral;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.arriaii_atom_pack.all;
package arriaii_components is
--
-- arriaii_lcell_comb
--
COMPONENT arriaii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "arriaii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- arriaii_routing_wire
--
COMPONENT arriaii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- arriaii_lvds_transmitter
--
COMPONENT arriaii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "arriaii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- arriaii_rublock
--
COMPONENT arriaii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "arriaii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaii_oscillator
--
COMPONENT arriaii_oscillator
generic
(
lpm_type: string := "arriaii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
END COMPONENT;
--
-- arriaii_ram_block
--
COMPONENT arriaii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "arriaii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_ff
--
COMPONENT arriaii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "arriaii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- arriaii_clkselect
--
COMPONENT arriaii_clkselect
generic (
lpm_type : STRING := "arriaii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- arriaii_clkena
--
COMPONENT arriaii_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "arriaii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- arriaii_mlab_cell
--
COMPONENT arriaii_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "arriaii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_io_ibuf
--
COMPONENT arriaii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "arriaii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- arriaii_io_obuf
--
COMPONENT arriaii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "arriaii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaii_ddio_in
--
COMPONENT arriaii_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "arriaii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_ddio_oe
--
COMPONENT arriaii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "arriaii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_ddio_out
--
COMPONENT arriaii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "arriaii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_dll
--
COMPONENT arriaii_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "arriaii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- arriaii_dll_offset_ctrl
--
COMPONENT arriaii_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "arriaii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_dqs_enable
--
COMPONENT arriaii_dqs_enable
GENERIC (
lpm_type : string := "arriaii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- arriaii_mac_mult
--
COMPONENT arriaii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_mac_out
--
COMPONENT arriaii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "arriaii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_io_pad
--
COMPONENT arriaii_io_pad
GENERIC (
lpm_type : string := "arriaii_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- arriaii_pll
--
COMPONENT arriaii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "arriaii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "PiranhaIII";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- arriaii_asmiblock
--
COMPONENT arriaii_asmiblock
generic (
lpm_type : string := "arriaii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- arriaii_lvds_receiver
--
COMPONENT arriaii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := 2;
x_on_bitslip : string := "on";
lpm_type : string := "arriaii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- arriaii_pseudo_diff_out
--
COMPONENT arriaii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "arriaii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- arriaii_dqs_delay_chain
--
COMPONENT arriaii_dqs_delay_chain
GENERIC (
lpm_type : STRING := "arriaii_dqs_delay_chain";
delay_buffer_mode : STRING := "low";
dqs_ctrl_latches_enable : STRING := "false";
dqs_input_frequency : string := "unused" ;
dqs_offsetctrl_enable : STRING := "false";
dqs_phase_shift : INTEGER := 0;
phase_setting : INTEGER := 0;
sim_buffer_delay_increment : INTEGER := 10;
sim_high_buffer_intrinsic_delay : INTEGER := 175;
sim_low_buffer_intrinsic_delay : INTEGER := 350;
test_enable : STRING := "false";
test_select : INTEGER := 0 ;
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
dqsin : IN STD_LOGIC := '0';
dqsupdateen : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0):= (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_dqs_enable_ctrl
--
COMPONENT arriaii_dqs_enable_ctrl
GENERIC (
lpm_type : STRING := "arriaii_dqs_enable_ctrl";
delay_dqs_enable_by_half_cycle : STRING := "false" ;
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN STD_LOGIC := '0';
dqsenablein : IN STD_LOGIC := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaii_jtag
--
COMPONENT arriaii_jtag
generic (
lpm_type : string := "arriaii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- arriaii_crcblock
--
COMPONENT arriaii_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "arriaii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- arriaii_controller
--
COMPONENT arriaii_controller
generic (
lpm_type : string := "arriaii_controller"
);
port (
nceout : out std_logic
);
END COMPONENT;
--
-- arriaii_termination_logic
--
COMPONENT arriaii_termination_logic
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationselect : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_termination_logic"
);
PORT (
terminationclock : IN STD_LOGIC := '0';
terminationdata : IN STD_LOGIC := '0';
terminationselect : IN STD_LOGIC := '0';
terminationcontrol : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
--
-- arriaii_termination
--
COMPONENT arriaii_termination
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_scanshiftmux : VitalDelayType01 := DefpropDelay01;
tipd_scaninmux : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclock : VitalDelayType01 := DefpropDelay01;
tipd_scanclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationuserclear : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_rup : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaii_termination";
runtime_control : STRING := "false"
);
PORT (
rdn : IN STD_LOGIC := '0';
rup : IN STD_LOGIC := '0';
scanclock : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC := '0';
scaninmux : IN STD_LOGIC := '0';
scanshiftmux : IN STD_LOGIC := '0';
terminationuserclear : IN STD_LOGIC := '0';
terminationuserclock : IN STD_LOGIC := '0';
comparatorprobe : OUT STD_LOGIC;
scanout : OUT STD_LOGIC;
terminationclockout : OUT STD_LOGIC;
terminationcontrolprobe : OUT STD_LOGIC;
terminationdataout : OUT STD_LOGIC;
terminationdone : OUT STD_LOGIC;
terminationselectout : OUT STD_LOGIC
);
END COMPONENT;
end arriaii_components;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity controller is
end entity controller;
-- code from book
architecture instrumented of controller is
shared variable operation_count : natural := 0;
-- . . .
begin
-- . . .
end architecture instrumented;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity controller is
end entity controller;
-- code from book
architecture instrumented of controller is
shared variable operation_count : natural := 0;
-- . . .
begin
-- . . .
end architecture instrumented;
-- end code from book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity controller is
end entity controller;
-- code from book
architecture instrumented of controller is
shared variable operation_count : natural := 0;
-- . . .
begin
-- . . .
end architecture instrumented;
-- end code from book
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ac_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-e.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_ac_e-e.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ac_e
--
entity inst_ac_e is
-- Generics:
-- No Generated Generics for Entity inst_ac_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ac_e
end inst_ac_e;
--
-- End of Generated Entity inst_ac_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Memory mapped 16550 UART
-- Acutally, it's won't even be a proper 8250, it should at least support
-- 9600 baud 8N1 with Tx, Rx, data_available, tx_ready memory-mapped
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
entity uart16550 is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE;
-- pins
tx : out std_logic;
rx : in std_logic
);
end uart16550;
architecture behav of uart16550 is
constant reading : std_logic := '0';
constant writing : std_logic := '1';
begin
dout <= HI_Z;
process(clk)
begin
if rising_edge(clk) and size /= "00" then
-- A 16550 UART spans 7 registers
dout <= NEG_ONE;
case addr(2 downto 0) is
when "000" => -- union { Tx, Rx, baud_lo }
null;
when "001" => -- union { baud_hi, int_enable }
null;
when "010" => -- union { int_status, fifo_ctrl }
null;
when "011" => -- struct LINE_CTRL { set baud, config }
null;
when "100" => -- struct MODEM_CTRL
null;
when "101" => -- struct LINE_STATUS { tx_empty, data_available }
null;
when "110" => -- struct MODEM_STATUS
null;
when others => trap <= TRAP_SEGFAULT;
end case;
end if;
end process;
end;
--
--struct uart16550 {
-- union {
-- writeonly uint8_t tx;
-- readonly uint8_t rx;
-- uint8_t baud_div_lo;
-- UART_PAD
-- };
-- union {
-- uint8_t int_enable;
-- uint8_t baud_div_hi;
-- UART_PAD
-- };
--
-- union {
-- uint8_t int_status;
-- uint8_t fifo_ctrl;
-- UART_PAD
-- };
--
-- writeonly struct {
-- union {
-- uint8_t set_baud : 1;
-- uint8_t : 2;
-- uint8_t config : 5;
-- UART_PAD
-- };
-- } line_ctrl;
--
-- writeonly union {uint8_t modem_ctrl; UART_PAD};
--
-- readonly union {struct {
-- uint8_t : 2;
-- uint8_t tx_empty : 1;
-- uint8_t : 4;
-- uint8_t data_available : 1;
-- }; UART_PAD } line_status;
--
-- readonly union{uint8_t modem_status; UART_PAD};
--};
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk17_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(2 downto 0)
);
end dk17_rnd;
architecture behaviour of dk17_rnd is
constant s10000000: std_logic_vector(2 downto 0) := "101";
constant s01000000: std_logic_vector(2 downto 0) := "010";
constant s00100000: std_logic_vector(2 downto 0) := "011";
constant s00010000: std_logic_vector(2 downto 0) := "110";
constant s00001000: std_logic_vector(2 downto 0) := "111";
constant s00000100: std_logic_vector(2 downto 0) := "001";
constant s00000010: std_logic_vector(2 downto 0) := "000";
constant s00000001: std_logic_vector(2 downto 0) := "100";
signal current_state, next_state: std_logic_vector(2 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "---"; output <= "---";
case current_state is
when s10000000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s00010000; output <= "010";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s00001000; output <= "010";
end if;
when s01000000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00000100; output <= "000";
end if;
when s00100000 =>
if std_match(input, "00") then next_state <= s10000000; output <= "001";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s01000000; output <= "001";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00010000 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "101";
elsif std_match(input, "10") then next_state <= s00010000; output <= "010";
elsif std_match(input, "11") then next_state <= s00001000; output <= "101";
end if;
when s00001000 =>
if std_match(input, "00") then next_state <= s00100000; output <= "000";
elsif std_match(input, "01") then next_state <= s00010000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000100 =>
if std_match(input, "00") then next_state <= s00000010; output <= "000";
elsif std_match(input, "01") then next_state <= s00000001; output <= "000";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when s00000010 =>
if std_match(input, "00") then next_state <= s00010000; output <= "010";
elsif std_match(input, "01") then next_state <= s10000000; output <= "101";
elsif std_match(input, "10") then next_state <= s00001000; output <= "010";
elsif std_match(input, "11") then next_state <= s01000000; output <= "101";
end if;
when s00000001 =>
if std_match(input, "00") then next_state <= s00010000; output <= "100";
elsif std_match(input, "01") then next_state <= s00001000; output <= "100";
elsif std_match(input, "10") then next_state <= s00100000; output <= "010";
elsif std_match(input, "11") then next_state <= s00100000; output <= "100";
end if;
when others => next_state <= "---"; output <= "---";
end case;
end process;
end behaviour;
|
-- generated with romgen v3.0 by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ipl_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(12 downto 0);
data : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of ipl_rom is
type ROM_ARRAY is array(0 to 8191) of std_logic_vector(7 downto 0);
constant ROM : ROM_ARRAY := (
x"F3",x"ED",x"56",x"C3",x"80",x"00",x"FF",x"FF", -- 0x0000
x"ED",x"4D",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008
x"ED",x"4D",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0010
x"ED",x"4D",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0018
x"ED",x"4D",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020
x"ED",x"4D",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0028
x"ED",x"4D",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0030
x"ED",x"4D",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0038
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0040
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0048
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0050
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0058
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"ED",x"45", -- 0x0060
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0068
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0070
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0078
x"31",x"FF",x"7F",x"CD",x"67",x"1E",x"CD",x"48", -- 0x0080
x"02",x"C3",x"00",x"01",x"FF",x"FF",x"FF",x"FF", -- 0x0088
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0090
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0098
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00A0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00A8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00B0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00B8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00C8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00D8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00E8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00F0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x00F8
x"76",x"18",x"FD",x"21",x"03",x"00",x"39",x"4E", -- 0x0100
x"23",x"46",x"C5",x"CD",x"8F",x"1C",x"F1",x"CB", -- 0x0108
x"3C",x"CB",x"1D",x"55",x"3E",x"10",x"92",x"57", -- 0x0110
x"21",x"02",x"00",x"39",x"7E",x"F5",x"33",x"D5", -- 0x0118
x"33",x"CD",x"44",x"1A",x"F1",x"21",x"03",x"00", -- 0x0120
x"39",x"4E",x"23",x"46",x"C5",x"CD",x"31",x"1B", -- 0x0128
x"F1",x"C9",x"28",x"20",x"20",x"20",x"20",x"20", -- 0x0130
x"20",x"20",x"20",x"4D",x"53",x"58",x"31",x"46", -- 0x0138
x"50",x"47",x"41",x"20",x"4C",x"4F",x"41",x"44", -- 0x0140
x"45",x"52",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0148
x"20",x"20",x"20",x"00",x"3E",x"FF",x"D3",x"9E", -- 0x0150
x"21",x"01",x"0F",x"E5",x"3E",x"06",x"F5",x"33", -- 0x0158
x"CD",x"D5",x"19",x"F1",x"33",x"C1",x"E1",x"E5", -- 0x0160
x"C5",x"E5",x"3E",x"0C",x"F5",x"33",x"CD",x"03", -- 0x0168
x"01",x"F1",x"33",x"18",x"FE",x"11",x"03",x"40", -- 0x0170
x"21",x"02",x"00",x"39",x"01",x"02",x"00",x"ED", -- 0x0178
x"B0",x"21",x"04",x"00",x"39",x"3A",x"03",x"40", -- 0x0180
x"96",x"3A",x"04",x"40",x"23",x"9E",x"D0",x"2A", -- 0x0188
x"50",x"44",x"3A",x"03",x"40",x"77",x"23",x"FD", -- 0x0190
x"21",x"03",x"40",x"FD",x"7E",x"01",x"77",x"E5", -- 0x0198
x"D5",x"C5",x"21",x"00",x"80",x"11",x"01",x"80", -- 0x01A0
x"01",x"FF",x"3F",x"3E",x"00",x"77",x"ED",x"B0", -- 0x01A8
x"C1",x"D1",x"E1",x"21",x"03",x"40",x"34",x"20", -- 0x01B0
x"C8",x"21",x"04",x"40",x"34",x"18",x"C2",x"11", -- 0x01B8
x"03",x"40",x"21",x"02",x"00",x"39",x"01",x"02", -- 0x01C0
x"00",x"ED",x"B0",x"21",x"04",x"00",x"39",x"3A", -- 0x01C8
x"03",x"40",x"96",x"3A",x"04",x"40",x"23",x"9E", -- 0x01D0
x"D0",x"2A",x"50",x"44",x"3A",x"03",x"40",x"77", -- 0x01D8
x"23",x"3A",x"04",x"40",x"77",x"21",x"00",x"80", -- 0x01E0
x"22",x"00",x"40",x"21",x"02",x"40",x"36",x"00", -- 0x01E8
x"11",x"05",x"40",x"2A",x"00",x"40",x"E5",x"D5", -- 0x01F0
x"CD",x"11",x"14",x"F1",x"F1",x"7C",x"B5",x"20", -- 0x01F8
x"08",x"21",x"34",x"02",x"E5",x"CD",x"54",x"01", -- 0x0200
x"F1",x"21",x"00",x"40",x"7E",x"C6",x"00",x"77", -- 0x0208
x"23",x"7E",x"CE",x"02",x"77",x"21",x"02",x"40", -- 0x0210
x"34",x"3A",x"02",x"40",x"D6",x"20",x"38",x"D0", -- 0x0218
x"3E",x"2E",x"F5",x"33",x"CD",x"BA",x"1A",x"33", -- 0x0220
x"21",x"03",x"40",x"34",x"20",x"9D",x"21",x"04", -- 0x0228
x"40",x"34",x"18",x"97",x"45",x"72",x"72",x"6F", -- 0x0230
x"72",x"20",x"72",x"65",x"61",x"64",x"69",x"6E", -- 0x0238
x"67",x"20",x"66",x"69",x"6C",x"65",x"21",x"00", -- 0x0240
x"21",x"C9",x"FD",x"39",x"F9",x"01",x"00",x"00", -- 0x0248
x"21",x"22",x"02",x"39",x"AF",x"77",x"23",x"77", -- 0x0250
x"21",x"20",x"02",x"39",x"AF",x"77",x"23",x"77", -- 0x0258
x"21",x"27",x"02",x"39",x"AF",x"77",x"23",x"77", -- 0x0260
x"21",x"08",x"02",x"39",x"AF",x"77",x"23",x"77", -- 0x0268
x"21",x"1E",x"02",x"39",x"AF",x"77",x"23",x"77", -- 0x0270
x"21",x"29",x"02",x"39",x"AF",x"77",x"23",x"77", -- 0x0278
x"21",x"06",x"02",x"39",x"36",x"02",x"23",x"36", -- 0x0280
x"00",x"21",x"2E",x"02",x"39",x"AF",x"77",x"23", -- 0x0288
x"77",x"3A",x"32",x"01",x"D3",x"40",x"3E",x"12", -- 0x0290
x"D3",x"48",x"3E",x"01",x"D3",x"49",x"C5",x"CD", -- 0x0298
x"46",x"19",x"21",x"01",x"0F",x"E5",x"3E",x"04", -- 0x02A0
x"F5",x"33",x"CD",x"D5",x"19",x"F1",x"33",x"C1", -- 0x02A8
x"21",x"33",x"01",x"C5",x"E5",x"CD",x"31",x"1B", -- 0x02B0
x"F1",x"C1",x"3E",x"00",x"D3",x"48",x"DB",x"49", -- 0x02B8
x"FD",x"21",x"2B",x"02",x"FD",x"39",x"FD",x"77", -- 0x02C0
x"00",x"3E",x"01",x"D3",x"48",x"21",x"02",x"40", -- 0x02C8
x"36",x"00",x"21",x"0A",x"02",x"39",x"FD",x"21", -- 0x02D0
x"34",x"02",x"FD",x"39",x"FD",x"75",x"00",x"FD", -- 0x02D8
x"74",x"01",x"21",x"34",x"02",x"39",x"3A",x"02", -- 0x02E0
x"40",x"86",x"5F",x"3E",x"00",x"23",x"8E",x"57", -- 0x02E8
x"DB",x"49",x"12",x"21",x"34",x"02",x"39",x"3A", -- 0x02F0
x"02",x"40",x"86",x"5F",x"3E",x"00",x"23",x"8E", -- 0x02F8
x"57",x"1A",x"B7",x"28",x"0B",x"21",x"02",x"40", -- 0x0300
x"34",x"3A",x"02",x"40",x"D6",x"14",x"38",x"D2", -- 0x0308
x"3E",x"02",x"D3",x"48",x"DB",x"49",x"FD",x"21", -- 0x0310
x"26",x"02",x"FD",x"39",x"FD",x"77",x"00",x"3E", -- 0x0318
x"03",x"D3",x"48",x"DB",x"49",x"FD",x"21",x"25", -- 0x0320
x"02",x"FD",x"39",x"FD",x"77",x"00",x"3E",x"04", -- 0x0328
x"D3",x"48",x"DB",x"49",x"E6",x"01",x"FD",x"21", -- 0x0330
x"24",x"02",x"FD",x"39",x"FD",x"77",x"00",x"C5", -- 0x0338
x"21",x"00",x"03",x"E5",x"CD",x"44",x"1A",x"F1", -- 0x0340
x"C1",x"21",x"AF",x"09",x"C5",x"E5",x"CD",x"31", -- 0x0348
x"1B",x"F1",x"21",x"2D",x"02",x"39",x"7E",x"F5", -- 0x0350
x"33",x"CD",x"2A",x"1C",x"33",x"C1",x"21",x"B8", -- 0x0358
x"09",x"C5",x"E5",x"CD",x"31",x"1B",x"F1",x"C1", -- 0x0360
x"21",x"34",x"02",x"39",x"7E",x"23",x"66",x"6F", -- 0x0368
x"C5",x"E5",x"CD",x"31",x"1B",x"F1",x"C1",x"21", -- 0x0370
x"BC",x"09",x"C5",x"E5",x"CD",x"31",x"1B",x"F1", -- 0x0378
x"C1",x"21",x"26",x"02",x"39",x"7E",x"07",x"07", -- 0x0380
x"07",x"07",x"E6",x"0F",x"C5",x"F5",x"33",x"CD", -- 0x0388
x"2A",x"1C",x"33",x"3E",x"2E",x"F5",x"33",x"CD", -- 0x0390
x"BA",x"1A",x"33",x"C1",x"21",x"26",x"02",x"39", -- 0x0398
x"7E",x"E6",x"0F",x"C5",x"F5",x"33",x"CD",x"2A", -- 0x03A0
x"1C",x"33",x"C1",x"21",x"C7",x"09",x"C5",x"E5", -- 0x03A8
x"CD",x"31",x"1B",x"F1",x"CD",x"4A",x"0C",x"7D", -- 0x03B0
x"C1",x"B7",x"20",x"0A",x"21",x"CA",x"09",x"C5", -- 0x03B8
x"E5",x"CD",x"54",x"01",x"F1",x"C1",x"21",x"E2", -- 0x03C0
x"09",x"C5",x"E5",x"CD",x"31",x"1B",x"F1",x"CD", -- 0x03C8
x"55",x"0C",x"7D",x"C1",x"B7",x"20",x"0A",x"21", -- 0x03D0
x"F9",x"09",x"C5",x"E5",x"CD",x"54",x"01",x"F1", -- 0x03D8
x"C1",x"C5",x"CD",x"AE",x"10",x"C1",x"7C",x"B5", -- 0x03E0
x"20",x"0A",x"21",x"1A",x"0A",x"C5",x"E5",x"CD", -- 0x03E8
x"54",x"01",x"F1",x"C1",x"21",x"2C",x"0A",x"C5", -- 0x03F0
x"E5",x"CD",x"31",x"1B",x"F1",x"2A",x"3A",x"44", -- 0x03F8
x"E5",x"CD",x"26",x"15",x"F1",x"C1",x"7C",x"B5", -- 0x0400
x"20",x"0A",x"21",x"46",x"0A",x"C5",x"E5",x"CD", -- 0x0408
x"54",x"01",x"F1",x"C1",x"11",x"05",x"40",x"C5", -- 0x0410
x"2A",x"3C",x"44",x"E5",x"D5",x"CD",x"B8",x"13", -- 0x0418
x"F1",x"F1",x"C1",x"7C",x"B5",x"20",x"0A",x"21", -- 0x0420
x"66",x"0A",x"C5",x"E5",x"CD",x"54",x"01",x"F1", -- 0x0428
x"C1",x"21",x"06",x"00",x"39",x"FD",x"21",x"34", -- 0x0430
x"02",x"FD",x"39",x"FD",x"75",x"00",x"FD",x"74", -- 0x0438
x"01",x"FD",x"5E",x"00",x"FD",x"56",x"01",x"21", -- 0x0440
x"05",x"40",x"C5",x"D5",x"E5",x"CD",x"11",x"14", -- 0x0448
x"F1",x"F1",x"C1",x"7C",x"B5",x"20",x"0A",x"21", -- 0x0450
x"7D",x"0A",x"C5",x"E5",x"CD",x"54",x"01",x"F1", -- 0x0458
x"C1",x"21",x"34",x"02",x"39",x"7E",x"23",x"66", -- 0x0460
x"6F",x"7E",x"D6",x"31",x"20",x"04",x"3E",x"01", -- 0x0468
x"18",x"02",x"3E",x"00",x"FD",x"21",x"03",x"00", -- 0x0470
x"FD",x"39",x"FD",x"77",x"00",x"21",x"34",x"02", -- 0x0478
x"39",x"7E",x"23",x"66",x"6F",x"23",x"7E",x"D6", -- 0x0480
x"31",x"20",x"04",x"3E",x"02",x"18",x"02",x"3E", -- 0x0488
x"00",x"FD",x"21",x"04",x"00",x"FD",x"39",x"FD", -- 0x0490
x"77",x"00",x"21",x"34",x"02",x"39",x"7E",x"23", -- 0x0498
x"66",x"6F",x"23",x"23",x"7E",x"FD",x"21",x"05", -- 0x04A0
x"00",x"FD",x"39",x"FD",x"77",x"00",x"FD",x"7E", -- 0x04A8
x"00",x"D6",x"45",x"28",x"26",x"FD",x"7E",x"00", -- 0x04B0
x"D6",x"42",x"28",x"1F",x"FD",x"7E",x"00",x"D6", -- 0x04B8
x"46",x"28",x"18",x"FD",x"7E",x"00",x"D6",x"53", -- 0x04C0
x"28",x"11",x"FD",x"7E",x"00",x"D6",x"4A",x"28", -- 0x04C8
x"0A",x"21",x"98",x"0A",x"C5",x"E5",x"CD",x"54", -- 0x04D0
x"01",x"F1",x"C1",x"21",x"34",x"02",x"39",x"7E", -- 0x04D8
x"23",x"66",x"6F",x"23",x"23",x"23",x"7E",x"D6", -- 0x04E0
x"50",x"20",x"04",x"1E",x"08",x"18",x"02",x"1E", -- 0x04E8
x"00",x"21",x"34",x"02",x"39",x"7E",x"23",x"66", -- 0x04F0
x"6F",x"23",x"23",x"23",x"23",x"7E",x"D6",x"31", -- 0x04F8
x"20",x"04",x"3E",x"01",x"18",x"02",x"3E",x"00", -- 0x0500
x"FD",x"21",x"02",x"00",x"FD",x"39",x"FD",x"77", -- 0x0508
x"00",x"21",x"34",x"02",x"39",x"7E",x"23",x"66", -- 0x0510
x"6F",x"23",x"23",x"23",x"23",x"23",x"7E",x"D6", -- 0x0518
x"31",x"20",x"04",x"16",x"04",x"18",x"02",x"16", -- 0x0520
x"00",x"3E",x"10",x"D3",x"48",x"7B",x"B2",x"21", -- 0x0528
x"04",x"00",x"39",x"B6",x"21",x"03",x"00",x"39", -- 0x0530
x"B6",x"D3",x"49",x"21",x"25",x"02",x"39",x"7E", -- 0x0538
x"E6",x"07",x"6F",x"B7",x"20",x"3C",x"01",x"08", -- 0x0540
x"00",x"21",x"22",x"02",x"39",x"36",x"0E",x"23", -- 0x0548
x"36",x"00",x"21",x"20",x"02",x"39",x"36",x"0F", -- 0x0550
x"23",x"36",x"00",x"21",x"1E",x"02",x"39",x"36", -- 0x0558
x"1E",x"23",x"36",x"00",x"21",x"06",x"02",x"39", -- 0x0560
x"36",x"02",x"23",x"36",x"00",x"21",x"27",x"02", -- 0x0568
x"39",x"36",x"10",x"23",x"36",x"00",x"21",x"08", -- 0x0570
x"02",x"39",x"36",x"1C",x"23",x"36",x"00",x"C3", -- 0x0578
x"0C",x"06",x"7D",x"D6",x"02",x"20",x"3B",x"01", -- 0x0580
x"40",x"00",x"21",x"22",x"02",x"39",x"36",x"60", -- 0x0588
x"23",x"36",x"00",x"21",x"20",x"02",x"39",x"36", -- 0x0590
x"7F",x"23",x"36",x"00",x"21",x"06",x"02",x"39", -- 0x0598
x"36",x"04",x"23",x"36",x"00",x"21",x"29",x"02", -- 0x05A0
x"39",x"36",x"08",x"23",x"36",x"00",x"21",x"27", -- 0x05A8
x"02",x"39",x"36",x"20",x"23",x"36",x"00",x"21", -- 0x05B0
x"08",x"02",x"39",x"36",x"40",x"23",x"36",x"00", -- 0x05B8
x"18",x"4A",x"7D",x"D6",x"04",x"20",x"3B",x"01", -- 0x05C0
x"00",x"01",x"21",x"22",x"02",x"39",x"36",x"1F", -- 0x05C8
x"23",x"36",x"01",x"21",x"20",x"02",x"39",x"36", -- 0x05D0
x"FF",x"23",x"36",x"01",x"21",x"06",x"02",x"39", -- 0x05D8
x"36",x"04",x"23",x"36",x"00",x"21",x"29",x"02", -- 0x05E0
x"39",x"36",x"08",x"23",x"36",x"00",x"21",x"27", -- 0x05E8
x"02",x"39",x"36",x"40",x"23",x"36",x"00",x"21", -- 0x05F0
x"08",x"02",x"39",x"36",x"60",x"23",x"36",x"00", -- 0x05F8
x"18",x"0A",x"21",x"A8",x"0A",x"C5",x"E5",x"CD", -- 0x0600
x"54",x"01",x"F1",x"C1",x"21",x"BB",x"0A",x"C5", -- 0x0608
x"E5",x"CD",x"31",x"1B",x"F1",x"C1",x"21",x"03", -- 0x0610
x"00",x"39",x"7E",x"3D",x"20",x"04",x"3E",x"01", -- 0x0618
x"18",x"01",x"AF",x"FD",x"21",x"36",x"02",x"FD", -- 0x0620
x"39",x"FD",x"77",x"00",x"21",x"2C",x"02",x"39", -- 0x0628
x"FD",x"21",x"29",x"02",x"FD",x"39",x"FD",x"7E", -- 0x0630
x"00",x"C6",x"08",x"77",x"FD",x"7E",x"01",x"CE", -- 0x0638
x"00",x"23",x"77",x"21",x"36",x"02",x"39",x"7E", -- 0x0640
x"B7",x"20",x"17",x"C5",x"21",x"2E",x"02",x"39", -- 0x0648
x"4E",x"23",x"46",x"C5",x"21",x"2D",x"02",x"39", -- 0x0650
x"4E",x"23",x"46",x"C5",x"CD",x"75",x"01",x"F1", -- 0x0658
x"F1",x"C1",x"21",x"22",x"02",x"39",x"7E",x"23", -- 0x0660
x"66",x"6F",x"E5",x"C5",x"CD",x"75",x"01",x"F1", -- 0x0668
x"F1",x"21",x"08",x"02",x"39",x"4E",x"23",x"46", -- 0x0670
x"C5",x"21",x"29",x"02",x"39",x"4E",x"23",x"46", -- 0x0678
x"C5",x"CD",x"75",x"01",x"F1",x"21",x"CD",x"0A", -- 0x0680
x"E3",x"CD",x"31",x"1B",x"F1",x"21",x"25",x"02", -- 0x0688
x"39",x"7E",x"E6",x"80",x"D6",x"80",x"20",x"68", -- 0x0690
x"21",x"D2",x"0A",x"E5",x"CD",x"31",x"1B",x"F1", -- 0x0698
x"11",x"05",x"40",x"2A",x"42",x"44",x"E5",x"D5", -- 0x06A0
x"CD",x"B8",x"13",x"F1",x"F1",x"4D",x"7C",x"B1", -- 0x06A8
x"20",x"08",x"21",x"E9",x"0A",x"E5",x"CD",x"54", -- 0x06B0
x"01",x"F1",x"2A",x"06",x"40",x"ED",x"5B",x"08", -- 0x06B8
x"40",x"7D",x"B7",x"20",x"0A",x"B4",x"20",x"07", -- 0x06C0
x"1D",x"20",x"04",x"7A",x"B7",x"28",x"08",x"21", -- 0x06C8
x"01",x"0B",x"E5",x"CD",x"54",x"01",x"F1",x"21", -- 0x06D0
x"06",x"02",x"39",x"FD",x"21",x"1E",x"02",x"FD", -- 0x06D8
x"39",x"FD",x"7E",x"00",x"86",x"5F",x"FD",x"7E", -- 0x06E0
x"01",x"23",x"8E",x"57",x"D5",x"FD",x"6E",x"00", -- 0x06E8
x"FD",x"66",x"01",x"E5",x"CD",x"BF",x"01",x"F1", -- 0x06F0
x"21",x"CD",x"0A",x"E3",x"CD",x"31",x"1B",x"F1", -- 0x06F8
x"21",x"36",x"02",x"39",x"7E",x"B7",x"CA",x"B4", -- 0x0700
x"07",x"21",x"24",x"02",x"39",x"7E",x"B7",x"20", -- 0x0708
x"1A",x"3A",x"3E",x"44",x"FD",x"21",x"00",x"00", -- 0x0710
x"FD",x"39",x"FD",x"77",x"00",x"3A",x"3F",x"44", -- 0x0718
x"FD",x"21",x"00",x"00",x"FD",x"39",x"FD",x"77", -- 0x0720
x"01",x"18",x"18",x"3A",x"40",x"44",x"FD",x"21", -- 0x0728
x"00",x"00",x"FD",x"39",x"FD",x"77",x"00",x"3A", -- 0x0730
x"41",x"44",x"FD",x"21",x"00",x"00",x"FD",x"39", -- 0x0738
x"FD",x"77",x"01",x"21",x"1A",x"0B",x"E5",x"CD", -- 0x0740
x"31",x"1B",x"F1",x"E1",x"E5",x"E5",x"21",x"05", -- 0x0748
x"40",x"E5",x"CD",x"B8",x"13",x"F1",x"F1",x"4D", -- 0x0750
x"7C",x"B1",x"20",x"08",x"21",x"2C",x"0B",x"E5", -- 0x0758
x"CD",x"54",x"01",x"F1",x"11",x"06",x"40",x"21", -- 0x0760
x"30",x"02",x"39",x"EB",x"01",x"04",x"00",x"ED", -- 0x0768
x"B0",x"FD",x"21",x"30",x"02",x"FD",x"39",x"FD", -- 0x0770
x"7E",x"00",x"B7",x"20",x"13",x"FD",x"7E",x"01", -- 0x0778
x"B7",x"20",x"0D",x"FD",x"7E",x"02",x"D6",x"02", -- 0x0780
x"20",x"06",x"FD",x"7E",x"03",x"B7",x"28",x"08", -- 0x0788
x"21",x"43",x"0B",x"E5",x"CD",x"54",x"01",x"F1", -- 0x0790
x"21",x"2C",x"02",x"39",x"4E",x"23",x"46",x"C5", -- 0x0798
x"21",x"2B",x"02",x"39",x"4E",x"23",x"46",x"C5", -- 0x07A0
x"CD",x"BF",x"01",x"F1",x"21",x"CD",x"0A",x"E3", -- 0x07A8
x"CD",x"31",x"1B",x"F1",x"21",x"05",x"00",x"39", -- 0x07B0
x"7E",x"FE",x"42",x"28",x"26",x"FE",x"45",x"28", -- 0x07B8
x"0E",x"FE",x"46",x"28",x"32",x"FE",x"4A",x"28", -- 0x07C0
x"56",x"D6",x"53",x"28",x"3E",x"18",x"62",x"21", -- 0x07C8
x"44",x"44",x"7E",x"FD",x"21",x"2E",x"02",x"FD", -- 0x07D0
x"39",x"FD",x"77",x"00",x"23",x"7E",x"FD",x"77", -- 0x07D8
x"01",x"18",x"4E",x"21",x"46",x"44",x"7E",x"FD", -- 0x07E0
x"21",x"2E",x"02",x"FD",x"39",x"FD",x"77",x"00", -- 0x07E8
x"23",x"7E",x"FD",x"77",x"01",x"18",x"3A",x"21", -- 0x07F0
x"48",x"44",x"7E",x"FD",x"21",x"2E",x"02",x"FD", -- 0x07F8
x"39",x"FD",x"77",x"00",x"23",x"7E",x"FD",x"77", -- 0x0800
x"01",x"18",x"26",x"21",x"4A",x"44",x"7E",x"FD", -- 0x0808
x"21",x"2E",x"02",x"FD",x"39",x"FD",x"77",x"00", -- 0x0810
x"23",x"7E",x"FD",x"77",x"01",x"18",x"12",x"21", -- 0x0818
x"4C",x"44",x"7E",x"FD",x"21",x"2E",x"02",x"FD", -- 0x0820
x"39",x"FD",x"77",x"00",x"23",x"7E",x"FD",x"77", -- 0x0828
x"01",x"21",x"64",x"0B",x"E5",x"CD",x"31",x"1B", -- 0x0830
x"F1",x"21",x"05",x"40",x"FD",x"21",x"2E",x"02", -- 0x0838
x"FD",x"39",x"FD",x"4E",x"00",x"FD",x"46",x"01", -- 0x0840
x"C5",x"E5",x"CD",x"B8",x"13",x"F1",x"F1",x"7C", -- 0x0848
x"B5",x"20",x"08",x"21",x"75",x"0B",x"E5",x"CD", -- 0x0850
x"54",x"01",x"F1",x"2A",x"06",x"40",x"ED",x"5B", -- 0x0858
x"08",x"40",x"7D",x"D6",x"A4",x"20",x"0B",x"7C", -- 0x0860
x"D6",x"03",x"20",x"06",x"B3",x"20",x"03",x"B2", -- 0x0868
x"28",x"08",x"21",x"8C",x"0B",x"E5",x"CD",x"54", -- 0x0870
x"01",x"F1",x"3E",x"0D",x"D3",x"48",x"3E",x"00", -- 0x0878
x"D3",x"49",x"3E",x"0E",x"D3",x"48",x"3E",x"00", -- 0x0880
x"D3",x"49",x"3E",x"0F",x"D3",x"48",x"21",x"34", -- 0x0888
x"02",x"39",x"7E",x"23",x"66",x"6F",x"11",x"05", -- 0x0890
x"40",x"E5",x"D5",x"CD",x"11",x"14",x"F1",x"F1", -- 0x0898
x"7C",x"B5",x"20",x"08",x"21",x"AB",x"0B",x"E5", -- 0x08A0
x"CD",x"54",x"01",x"F1",x"11",x"00",x"00",x"21", -- 0x08A8
x"34",x"02",x"39",x"7E",x"23",x"66",x"6F",x"19", -- 0x08B0
x"7E",x"D3",x"49",x"13",x"7A",x"D6",x"02",x"38", -- 0x08B8
x"EE",x"3E",x"2E",x"F5",x"33",x"CD",x"BA",x"1A", -- 0x08C0
x"33",x"21",x"34",x"02",x"39",x"7E",x"23",x"66", -- 0x08C8
x"6F",x"11",x"05",x"40",x"E5",x"D5",x"CD",x"11", -- 0x08D0
x"14",x"F1",x"F1",x"7C",x"B5",x"20",x"08",x"21", -- 0x08D8
x"AB",x"0B",x"E5",x"CD",x"54",x"01",x"F1",x"3E", -- 0x08E0
x"2E",x"F5",x"33",x"CD",x"BA",x"1A",x"33",x"2A", -- 0x08E8
x"50",x"44",x"FD",x"21",x"1E",x"02",x"FD",x"39", -- 0x08F0
x"FD",x"7E",x"00",x"77",x"23",x"FD",x"7E",x"01", -- 0x08F8
x"77",x"FD",x"21",x"00",x"80",x"ED",x"5B",x"4E", -- 0x0900
x"44",x"FD",x"19",x"FD",x"22",x"00",x"40",x"11", -- 0x0908
x"00",x"00",x"ED",x"4B",x"00",x"40",x"21",x"30", -- 0x0910
x"02",x"39",x"FD",x"21",x"34",x"02",x"FD",x"39", -- 0x0918
x"FD",x"7E",x"00",x"83",x"77",x"FD",x"7E",x"01", -- 0x0920
x"8A",x"23",x"77",x"21",x"30",x"02",x"39",x"7E", -- 0x0928
x"23",x"66",x"6F",x"7E",x"02",x"21",x"00",x"40", -- 0x0930
x"34",x"20",x"04",x"21",x"01",x"40",x"34",x"13", -- 0x0938
x"7B",x"D6",x"A4",x"7A",x"DE",x"01",x"38",x"CA", -- 0x0940
x"21",x"CD",x"0A",x"E5",x"CD",x"31",x"1B",x"F1", -- 0x0948
x"3E",x"FF",x"D3",x"9E",x"21",x"01",x"0F",x"E5", -- 0x0950
x"3E",x"0C",x"F5",x"33",x"CD",x"D5",x"19",x"33", -- 0x0958
x"21",x"C6",x"0B",x"E3",x"CD",x"31",x"1B",x"F1", -- 0x0960
x"2A",x"50",x"44",x"FD",x"21",x"20",x"02",x"FD", -- 0x0968
x"39",x"FD",x"7E",x"00",x"77",x"23",x"FD",x"7E", -- 0x0970
x"01",x"77",x"3E",x"12",x"D3",x"48",x"FD",x"21", -- 0x0978
x"02",x"00",x"FD",x"39",x"FD",x"7E",x"00",x"D3", -- 0x0980
x"49",x"21",x"00",x"FF",x"36",x"3E",x"2E",x"01", -- 0x0988
x"36",x"F0",x"2E",x"02",x"36",x"D3",x"2E",x"03", -- 0x0990
x"36",x"A8",x"2E",x"04",x"36",x"C3",x"2E",x"05", -- 0x0998
x"36",x"00",x"2E",x"06",x"36",x"00",x"C3",x"00", -- 0x09A0
x"FF",x"21",x"37",x"02",x"39",x"F9",x"C9",x"48", -- 0x09A8
x"57",x"20",x"49",x"44",x"20",x"3D",x"20",x"00", -- 0x09B0
x"20",x"2D",x"20",x"00",x"0A",x"0A",x"56",x"65", -- 0x09B8
x"72",x"73",x"69",x"6F",x"6E",x"20",x"00",x"0A", -- 0x09C0
x"0A",x"00",x"4E",x"6F",x"20",x"53",x"44",x"20", -- 0x09C8
x"63",x"61",x"72",x"64",x"20",x"69",x"6E",x"20", -- 0x09D0
x"74",x"68",x"65",x"20",x"73",x"6C",x"6F",x"74", -- 0x09D8
x"21",x"00",x"49",x"6E",x"69",x"74",x"69",x"61", -- 0x09E0
x"6C",x"69",x"7A",x"69",x"6E",x"67",x"20",x"53", -- 0x09E8
x"44",x"20",x"43",x"61",x"72",x"64",x"3A",x"20", -- 0x09F0
x"00",x"45",x"72",x"72",x"6F",x"72",x"20",x"6F", -- 0x09F8
x"6E",x"20",x"53",x"44",x"20",x"63",x"61",x"72", -- 0x0A00
x"64",x"20",x"69",x"6E",x"69",x"74",x"69",x"61", -- 0x0A08
x"6C",x"69",x"7A",x"61",x"74",x"69",x"6F",x"6E", -- 0x0A10
x"21",x"00",x"46",x"41",x"54",x"20",x"46",x"53", -- 0x0A18
x"20",x"6E",x"6F",x"74",x"20",x"66",x"6F",x"75", -- 0x0A20
x"6E",x"64",x"21",x"00",x"4F",x"4B",x"0A",x"0A", -- 0x0A28
x"4C",x"6F",x"61",x"64",x"69",x"6E",x"67",x"20", -- 0x0A30
x"63",x"6F",x"6E",x"66",x"69",x"67",x"20",x"66", -- 0x0A38
x"69",x"6C",x"65",x"3A",x"20",x"00",x"27",x"4D", -- 0x0A40
x"53",x"58",x"31",x"46",x"50",x"47",x"41",x"27", -- 0x0A48
x"20",x"64",x"69",x"72",x"65",x"63",x"74",x"6F", -- 0x0A50
x"72",x"79",x"20",x"6E",x"6F",x"74",x"20",x"66", -- 0x0A58
x"6F",x"75",x"6E",x"64",x"21",x"00",x"43",x"6F", -- 0x0A60
x"6E",x"66",x"69",x"67",x"20",x"66",x"69",x"6C", -- 0x0A68
x"65",x"20",x"6E",x"6F",x"74",x"20",x"66",x"6F", -- 0x0A70
x"75",x"6E",x"64",x"21",x"00",x"45",x"72",x"72", -- 0x0A78
x"6F",x"72",x"20",x"72",x"65",x"61",x"64",x"69", -- 0x0A80
x"6E",x"67",x"20",x"43",x"6F",x"6E",x"66",x"69", -- 0x0A88
x"67",x"20",x"66",x"69",x"6C",x"65",x"21",x"00", -- 0x0A90
x"49",x"6E",x"76",x"61",x"6C",x"69",x"64",x"20", -- 0x0A98
x"6B",x"65",x"79",x"6D",x"61",x"70",x"21",x"00", -- 0x0AA0
x"4D",x"65",x"6D",x"6F",x"72",x"79",x"20",x"73", -- 0x0AA8
x"69",x"7A",x"65",x"20",x"65",x"72",x"72",x"6F", -- 0x0AB0
x"72",x"21",x"00",x"4F",x"4B",x"0A",x"0A",x"5A", -- 0x0AB8
x"65",x"72",x"6F",x"69",x"6E",x"67",x"20",x"52", -- 0x0AC0
x"41",x"4D",x"3A",x"20",x"00",x"20",x"4F",x"4B", -- 0x0AC8
x"0A",x"00",x"0A",x"4C",x"6F",x"61",x"64",x"69", -- 0x0AD0
x"6E",x"67",x"20",x"4D",x"53",x"58",x"52",x"4F", -- 0x0AD8
x"4D",x"53",x"2E",x"52",x"4F",x"4D",x"3A",x"20", -- 0x0AE0
x"00",x"4D",x"53",x"58",x"52",x"4F",x"4D",x"53", -- 0x0AE8
x"20",x"66",x"69",x"6C",x"65",x"20",x"6E",x"6F", -- 0x0AF0
x"74",x"20",x"66",x"6F",x"75",x"6E",x"64",x"21", -- 0x0AF8
x"00",x"4D",x"53",x"58",x"52",x"4F",x"4D",x"53", -- 0x0B00
x"20",x"66",x"69",x"6C",x"65",x"20",x"73",x"69", -- 0x0B08
x"7A",x"65",x"20",x"77",x"72",x"6F",x"6E",x"67", -- 0x0B10
x"21",x"00",x"0A",x"4C",x"6F",x"61",x"64",x"69", -- 0x0B18
x"6E",x"67",x"20",x"4E",x"45",x"58",x"54",x"4F", -- 0x0B20
x"52",x"3A",x"20",x"00",x"4E",x"45",x"58",x"54", -- 0x0B28
x"4F",x"52",x"20",x"66",x"69",x"6C",x"65",x"20", -- 0x0B30
x"6E",x"6F",x"74",x"20",x"66",x"6F",x"75",x"6E", -- 0x0B38
x"64",x"21",x"00",x"4E",x"45",x"58",x"54",x"4F", -- 0x0B40
x"52",x"20",x"66",x"69",x"6C",x"65",x"20",x"73", -- 0x0B48
x"69",x"7A",x"65",x"20",x"6D",x"75",x"73",x"74", -- 0x0B50
x"20",x"62",x"65",x"20",x"31",x"33",x"31",x"30", -- 0x0B58
x"37",x"32",x"21",x"00",x"0A",x"4C",x"6F",x"61", -- 0x0B60
x"64",x"69",x"6E",x"67",x"20",x"4B",x"65",x"79", -- 0x0B68
x"6D",x"61",x"70",x"20",x"00",x"4B",x"65",x"79", -- 0x0B70
x"6D",x"61",x"70",x"20",x"66",x"69",x"6C",x"65", -- 0x0B78
x"20",x"6E",x"6F",x"74",x"20",x"66",x"6F",x"75", -- 0x0B80
x"6E",x"64",x"21",x"00",x"4B",x"65",x"79",x"6D", -- 0x0B88
x"61",x"70",x"20",x"66",x"69",x"6C",x"65",x"20", -- 0x0B90
x"73",x"69",x"7A",x"65",x"20",x"6D",x"75",x"73", -- 0x0B98
x"74",x"20",x"62",x"65",x"20",x"39",x"33",x"32", -- 0x0BA0
x"42",x"21",x"00",x"45",x"72",x"72",x"6F",x"72", -- 0x0BA8
x"20",x"72",x"65",x"61",x"64",x"69",x"6E",x"67", -- 0x0BB0
x"20",x"4B",x"65",x"79",x"6D",x"61",x"70",x"20", -- 0x0BB8
x"66",x"69",x"6C",x"65",x"21",x"00",x"0A",x"42", -- 0x0BC0
x"6F",x"6F",x"74",x"69",x"6E",x"67",x"2E",x"2E", -- 0x0BC8
x"2E",x"00",x"4D",x"53",x"58",x"31",x"46",x"50", -- 0x0BD0
x"47",x"41",x"20",x"20",x"20",x"00",x"43",x"4F", -- 0x0BD8
x"4E",x"46",x"49",x"47",x"20",x"20",x"54",x"58", -- 0x0BE0
x"54",x"00",x"4E",x"45",x"58",x"54",x"4F",x"52", -- 0x0BE8
x"20",x"20",x"52",x"4F",x"4D",x"00",x"4E",x"45", -- 0x0BF0
x"58",x"54",x"4F",x"52",x"48",x"20",x"52",x"4F", -- 0x0BF8
x"4D",x"00",x"4D",x"53",x"58",x"52",x"4F",x"4D", -- 0x0C00
x"53",x"20",x"52",x"4F",x"4D",x"00",x"45",x"4E", -- 0x0C08
x"20",x"20",x"20",x"20",x"20",x"20",x"4B",x"4D", -- 0x0C10
x"50",x"00",x"50",x"54",x"42",x"52",x"20",x"20", -- 0x0C18
x"20",x"20",x"4B",x"4D",x"50",x"00",x"46",x"52", -- 0x0C20
x"20",x"20",x"20",x"20",x"20",x"20",x"4B",x"4D", -- 0x0C28
x"50",x"00",x"53",x"50",x"41",x"20",x"20",x"20", -- 0x0C30
x"20",x"20",x"4B",x"4D",x"50",x"00",x"4A",x"50", -- 0x0C38
x"20",x"20",x"20",x"20",x"20",x"20",x"4B",x"4D", -- 0x0C40
x"50",x"00",x"DB",x"9E",x"2E",x"01",x"E6",x"02", -- 0x0C48
x"28",x"02",x"2E",x"00",x"C9",x"DB",x"9E",x"E6", -- 0x0C50
x"02",x"20",x"48",x"3E",x"FF",x"D3",x"9E",x"06", -- 0x0C58
x"0A",x"3E",x"FF",x"D3",x"9F",x"10",x"FA",x"3E", -- 0x0C60
x"FE",x"D3",x"9E",x"06",x"10",x"3E",x"40",x"11", -- 0x0C68
x"00",x"00",x"C5",x"CD",x"43",x"0D",x"C1",x"D2", -- 0x0C70
x"83",x"0C",x"10",x"F1",x"2E",x"00",x"3E",x"FF", -- 0x0C78
x"D3",x"9E",x"C9",x"3E",x"48",x"11",x"AA",x"01", -- 0x0C80
x"CD",x"50",x"0D",x"21",x"27",x"0D",x"38",x"03", -- 0x0C88
x"21",x"35",x"0D",x"01",x"78",x"00",x"C5",x"CD", -- 0x0C90
x"AA",x"0C",x"C1",x"D2",x"AB",x"0C",x"10",x"F6", -- 0x0C98
x"0D",x"20",x"F3",x"2E",x"00",x"3E",x"FF",x"D3", -- 0x0CA0
x"9E",x"C9",x"E9",x"3E",x"7A",x"11",x"00",x"00", -- 0x0CA8
x"CD",x"50",x"0D",x"DA",x"A3",x"0C",x"78",x"E6", -- 0x0CB0
x"40",x"32",x"12",x"40",x"CC",x"CE",x"0C",x"3E", -- 0x0CB8
x"FF",x"D3",x"9E",x"3A",x"12",x"40",x"2E",x"03", -- 0x0CC0
x"FE",x"40",x"C8",x"2E",x"02",x"C9",x"3E",x"50", -- 0x0CC8
x"01",x"00",x"00",x"11",x"00",x"02",x"C3",x"2E", -- 0x0CD0
x"0D",x"FD",x"21",x"00",x"00",x"FD",x"39",x"FD", -- 0x0CD8
x"5E",x"02",x"FD",x"56",x"03",x"FD",x"4E",x"04", -- 0x0CE0
x"FD",x"46",x"05",x"FD",x"6E",x"06",x"FD",x"66", -- 0x0CE8
x"07",x"3E",x"FE",x"D3",x"9E",x"3A",x"12",x"40", -- 0x0CF0
x"B7",x"CC",x"1B",x"0D",x"3E",x"51",x"CD",x"2E", -- 0x0CF8
x"0D",x"30",x"03",x"2E",x"00",x"C9",x"CD",x"90", -- 0x0D00
x"0D",x"38",x"F8",x"01",x"9F",x"00",x"ED",x"B2", -- 0x0D08
x"ED",x"B2",x"00",x"DB",x"9F",x"00",x"DB",x"9F", -- 0x0D10
x"2E",x"01",x"C9",x"41",x"4A",x"53",x"1E",x"00", -- 0x0D18
x"CB",x"22",x"CB",x"11",x"CB",x"10",x"C9",x"3E", -- 0x0D20
x"41",x"01",x"00",x"00",x"50",x"59",x"CD",x"69", -- 0x0D28
x"0D",x"B7",x"C8",x"37",x"C9",x"3E",x"77",x"CD", -- 0x0D30
x"29",x"0D",x"3E",x"69",x"01",x"00",x"40",x"51", -- 0x0D38
x"59",x"18",x"EB",x"01",x"00",x"00",x"CD",x"69", -- 0x0D40
x"0D",x"47",x"E6",x"FE",x"78",x"20",x"E4",x"C9", -- 0x0D48
x"CD",x"43",x"0D",x"D8",x"F5",x"CD",x"9E",x"0D", -- 0x0D50
x"67",x"CD",x"9E",x"0D",x"6F",x"CD",x"9E",x"0D", -- 0x0D58
x"57",x"CD",x"9E",x"0D",x"5F",x"44",x"4D",x"F1", -- 0x0D60
x"C9",x"D3",x"9F",x"F5",x"78",x"00",x"D3",x"9F", -- 0x0D68
x"79",x"00",x"D3",x"9F",x"7A",x"00",x"D3",x"9F", -- 0x0D70
x"7B",x"00",x"D3",x"9F",x"F1",x"FE",x"40",x"06", -- 0x0D78
x"95",x"28",x"08",x"FE",x"48",x"06",x"87",x"28", -- 0x0D80
x"02",x"06",x"FF",x"78",x"D3",x"9F",x"18",x"0E", -- 0x0D88
x"06",x"0A",x"C5",x"CD",x"9E",x"0D",x"C1",x"FE", -- 0x0D90
x"FE",x"C8",x"10",x"F6",x"37",x"C9",x"01",x"64", -- 0x0D98
x"00",x"DB",x"9F",x"FE",x"FF",x"C0",x"10",x"F9", -- 0x0DA0
x"0D",x"20",x"F6",x"C9",x"C1",x"E1",x"E5",x"C5", -- 0x0DA8
x"4E",x"23",x"46",x"23",x"5E",x"23",x"56",x"69", -- 0x0DB0
x"60",x"C9",x"C1",x"E1",x"E5",x"C5",x"4E",x"23", -- 0x0DB8
x"66",x"69",x"C9",x"F5",x"F5",x"21",x"06",x"00", -- 0x0DC0
x"39",x"4E",x"23",x"46",x"21",x"08",x"00",x"39", -- 0x0DC8
x"7E",x"FD",x"21",x"00",x"00",x"FD",x"39",x"FD", -- 0x0DD0
x"77",x"00",x"21",x"09",x"00",x"39",x"7E",x"FD", -- 0x0DD8
x"21",x"00",x"00",x"FD",x"39",x"FD",x"77",x"01", -- 0x0DE0
x"11",x"00",x"00",x"21",x"0A",x"00",x"39",x"7B", -- 0x0DE8
x"96",x"7A",x"23",x"9E",x"E2",x"F9",x"0D",x"EE", -- 0x0DF0
x"80",x"F2",x"39",x"0E",x"0A",x"FD",x"21",x"02", -- 0x0DF8
x"00",x"FD",x"39",x"FD",x"77",x"00",x"03",x"E1", -- 0x0E00
x"E5",x"7E",x"FD",x"21",x"03",x"00",x"FD",x"39", -- 0x0E08
x"FD",x"77",x"00",x"FD",x"21",x"00",x"00",x"FD", -- 0x0E10
x"39",x"FD",x"34",x"00",x"20",x"03",x"FD",x"34", -- 0x0E18
x"01",x"21",x"02",x"00",x"39",x"7E",x"FD",x"21", -- 0x0E20
x"03",x"00",x"FD",x"39",x"FD",x"96",x"00",x"28", -- 0x0E28
x"05",x"21",x"00",x"00",x"18",x"06",x"13",x"18", -- 0x0E30
x"B2",x"21",x"01",x"00",x"F1",x"F1",x"C9",x"ED", -- 0x0E38
x"4B",x"14",x"40",x"ED",x"5B",x"16",x"40",x"21", -- 0x0E40
x"02",x"00",x"39",x"7E",x"81",x"77",x"23",x"7E", -- 0x0E48
x"88",x"77",x"23",x"7E",x"8B",x"77",x"23",x"7E", -- 0x0E50
x"8A",x"77",x"ED",x"4B",x"20",x"40",x"ED",x"5B", -- 0x0E58
x"22",x"40",x"FD",x"21",x"02",x"00",x"FD",x"39", -- 0x0E60
x"FD",x"7E",x"00",x"91",x"20",x"16",x"FD",x"7E", -- 0x0E68
x"01",x"90",x"20",x"10",x"FD",x"7E",x"02",x"93", -- 0x0E70
x"20",x"0A",x"FD",x"7E",x"03",x"92",x"20",x"04", -- 0x0E78
x"21",x"01",x"00",x"C9",x"21",x"36",x"40",x"E5", -- 0x0E80
x"FD",x"21",x"04",x"00",x"FD",x"39",x"FD",x"6E", -- 0x0E88
x"02",x"FD",x"66",x"03",x"E5",x"FD",x"6E",x"00", -- 0x0E90
x"FD",x"66",x"01",x"E5",x"CD",x"D9",x"0C",x"F1", -- 0x0E98
x"F1",x"F1",x"7D",x"B7",x"28",x"10",x"11",x"20", -- 0x0EA0
x"40",x"21",x"02",x"00",x"39",x"01",x"04",x"00", -- 0x0EA8
x"ED",x"B0",x"21",x"01",x"00",x"C9",x"21",x"00", -- 0x0EB0
x"00",x"C9",x"F5",x"F5",x"F5",x"F5",x"11",x"18", -- 0x0EB8
x"40",x"21",x"04",x"00",x"39",x"EB",x"01",x"04", -- 0x0EC0
x"00",x"ED",x"B0",x"21",x"00",x"00",x"39",x"FD", -- 0x0EC8
x"21",x"0A",x"00",x"FD",x"39",x"FD",x"7E",x"00", -- 0x0ED0
x"C6",x"FE",x"77",x"FD",x"7E",x"01",x"CE",x"FF", -- 0x0ED8
x"23",x"77",x"FD",x"7E",x"02",x"CE",x"FF",x"23", -- 0x0EE0
x"77",x"FD",x"7E",x"03",x"CE",x"FF",x"23",x"77", -- 0x0EE8
x"21",x"13",x"40",x"4E",x"06",x"00",x"11",x"00", -- 0x0EF0
x"00",x"D5",x"C5",x"FD",x"21",x"04",x"00",x"FD", -- 0x0EF8
x"39",x"FD",x"6E",x"02",x"FD",x"66",x"03",x"E5", -- 0x0F00
x"FD",x"6E",x"00",x"FD",x"66",x"01",x"E5",x"CD", -- 0x0F08
x"D1",x"1C",x"F1",x"F1",x"F1",x"F1",x"4D",x"44", -- 0x0F10
x"FD",x"21",x"04",x"00",x"FD",x"39",x"FD",x"7E", -- 0x0F18
x"00",x"81",x"4F",x"FD",x"7E",x"01",x"88",x"47", -- 0x0F20
x"FD",x"7E",x"02",x"8B",x"5F",x"FD",x"7E",x"03", -- 0x0F28
x"8A",x"57",x"69",x"60",x"F1",x"F1",x"F1",x"F1", -- 0x0F30
x"C9",x"F5",x"FD",x"21",x"04",x"00",x"FD",x"39", -- 0x0F38
x"FD",x"5E",x"00",x"FD",x"56",x"01",x"FD",x"6E", -- 0x0F40
x"02",x"FD",x"66",x"03",x"F1",x"06",x"08",x"CB", -- 0x0F48
x"3C",x"CB",x"1D",x"CB",x"1A",x"CB",x"1B",x"10", -- 0x0F50
x"F6",x"E5",x"D5",x"CD",x"3F",x"0E",x"F1",x"F1", -- 0x0F58
x"4D",x"7C",x"B1",x"20",x"06",x"21",x"00",x"00", -- 0x0F60
x"5D",x"54",x"C9",x"01",x"36",x"40",x"FD",x"21", -- 0x0F68
x"02",x"00",x"FD",x"39",x"FD",x"6E",x"00",x"26", -- 0x0F70
x"00",x"11",x"00",x"00",x"29",x"CB",x"13",x"CB", -- 0x0F78
x"12",x"09",x"E5",x"CD",x"BA",x"0D",x"F1",x"11", -- 0x0F80
x"00",x"00",x"C9",x"FD",x"21",x"02",x"00",x"FD", -- 0x0F88
x"39",x"FD",x"7E",x"00",x"E6",x"F8",x"4F",x"FD", -- 0x0F90
x"46",x"01",x"11",x"00",x"00",x"79",x"D6",x"F8", -- 0x0F98
x"20",x"0E",x"04",x"20",x"0B",x"7B",x"B7",x"20", -- 0x0FA0
x"07",x"B2",x"20",x"04",x"3E",x"01",x"18",x"01", -- 0x0FA8
x"AF",x"6F",x"17",x"9F",x"67",x"C9",x"F5",x"F5", -- 0x0FB0
x"F5",x"F5",x"3A",x"46",x"42",x"33",x"F5",x"33", -- 0x0FB8
x"21",x"4C",x"42",x"E5",x"CD",x"BA",x"0D",x"F1", -- 0x0FC0
x"FD",x"21",x"01",x"00",x"FD",x"39",x"FD",x"75", -- 0x0FC8
x"00",x"FD",x"74",x"01",x"21",x"00",x"00",x"22", -- 0x0FD0
x"24",x"40",x"22",x"26",x"40",x"ED",x"4B",x"14", -- 0x0FD8
x"40",x"ED",x"5B",x"16",x"40",x"ED",x"43",x"28", -- 0x0FE0
x"40",x"ED",x"53",x"2A",x"40",x"21",x"00",x"00", -- 0x0FE8
x"39",x"7E",x"FD",x"21",x"07",x"00",x"FD",x"39", -- 0x0FF0
x"FD",x"77",x"00",x"21",x"07",x"00",x"39",x"7E", -- 0x0FF8
x"B7",x"28",x"44",x"11",x"28",x"40",x"21",x"03", -- 0x1000
x"00",x"39",x"EB",x"01",x"04",x"00",x"ED",x"B0", -- 0x1008
x"21",x"01",x"00",x"39",x"4E",x"23",x"46",x"11", -- 0x1010
x"00",x"00",x"FD",x"21",x"03",x"00",x"FD",x"39", -- 0x1018
x"FD",x"7E",x"00",x"81",x"4F",x"FD",x"7E",x"01", -- 0x1020
x"88",x"47",x"FD",x"7E",x"02",x"8B",x"5F",x"FD", -- 0x1028
x"7E",x"03",x"8A",x"57",x"ED",x"43",x"28",x"40", -- 0x1030
x"ED",x"53",x"2A",x"40",x"FD",x"21",x"07",x"00", -- 0x1038
x"FD",x"39",x"FD",x"35",x"00",x"18",x"B4",x"21", -- 0x1040
x"47",x"42",x"E5",x"CD",x"BA",x"0D",x"F1",x"EB", -- 0x1048
x"06",x"04",x"CB",x"3A",x"CB",x"1B",x"10",x"FA", -- 0x1050
x"ED",x"53",x"2C",x"40",x"D5",x"11",x"28",x"40", -- 0x1058
x"21",x"05",x"00",x"39",x"EB",x"01",x"04",x"00", -- 0x1060
x"ED",x"B0",x"D1",x"01",x"00",x"00",x"FD",x"21", -- 0x1068
x"03",x"00",x"FD",x"39",x"FD",x"7E",x"00",x"83", -- 0x1070
x"5F",x"FD",x"7E",x"01",x"8A",x"57",x"FD",x"7E", -- 0x1078
x"02",x"89",x"4F",x"FD",x"7E",x"03",x"88",x"47", -- 0x1080
x"ED",x"53",x"18",x"40",x"ED",x"43",x"1A",x"40", -- 0x1088
x"21",x"00",x"00",x"22",x"2E",x"40",x"22",x"30", -- 0x1090
x"40",x"ED",x"4B",x"28",x"40",x"ED",x"5B",x"2A", -- 0x1098
x"40",x"ED",x"43",x"32",x"40",x"ED",x"53",x"34", -- 0x10A0
x"40",x"F1",x"F1",x"F1",x"F1",x"C9",x"F5",x"F5", -- 0x10A8
x"21",x"36",x"42",x"E5",x"21",x"00",x"00",x"E5", -- 0x10B0
x"21",x"00",x"00",x"E5",x"CD",x"D9",x"0C",x"F1", -- 0x10B8
x"F1",x"F1",x"7D",x"B7",x"20",x"06",x"21",x"00", -- 0x10C0
x"00",x"C3",x"A6",x"11",x"3A",x"34",x"44",x"D6", -- 0x10C8
x"55",x"20",x"07",x"3A",x"35",x"44",x"D6",x"AA", -- 0x10D0
x"28",x"06",x"21",x"00",x"00",x"C3",x"A6",x"11", -- 0x10D8
x"3A",x"F8",x"43",x"FE",x"04",x"28",x"04",x"D6", -- 0x10E0
x"06",x"20",x"04",x"0E",x"01",x"18",x"10",x"3A", -- 0x10E8
x"6F",x"42",x"D6",x"31",x"20",x"03",x"4F",x"18", -- 0x10F0
x"06",x"21",x"00",x"00",x"C3",x"A6",x"11",x"79", -- 0x10F8
x"B7",x"28",x"1C",x"21",x"FC",x"43",x"E5",x"CD", -- 0x1100
x"AC",x"0D",x"F1",x"FD",x"21",x"00",x"00",x"FD", -- 0x1108
x"39",x"FD",x"75",x"00",x"FD",x"74",x"01",x"FD", -- 0x1110
x"73",x"02",x"FD",x"72",x"03",x"18",x"13",x"AF", -- 0x1118
x"FD",x"21",x"00",x"00",x"FD",x"39",x"FD",x"77", -- 0x1120
x"00",x"FD",x"77",x"01",x"FD",x"77",x"02",x"FD", -- 0x1128
x"77",x"03",x"21",x"36",x"42",x"E5",x"FD",x"21", -- 0x1130
x"02",x"00",x"FD",x"39",x"FD",x"6E",x"02",x"FD", -- 0x1138
x"66",x"03",x"E5",x"FD",x"6E",x"00",x"FD",x"66", -- 0x1140
x"01",x"E5",x"CD",x"D9",x"0C",x"F1",x"F1",x"F1", -- 0x1148
x"7D",x"B7",x"20",x"05",x"21",x"00",x"00",x"18", -- 0x1150
x"4D",x"3A",x"41",x"42",x"B7",x"20",x"07",x"3A", -- 0x1158
x"42",x"42",x"D6",x"02",x"28",x"05",x"21",x"00", -- 0x1160
x"00",x"18",x"3B",x"3A",x"43",x"42",x"32",x"13", -- 0x1168
x"40",x"21",x"44",x"42",x"E5",x"CD",x"BA",x"0D", -- 0x1170
x"F1",x"4D",x"44",x"11",x"00",x"00",x"FD",x"21", -- 0x1178
x"00",x"00",x"FD",x"39",x"FD",x"7E",x"00",x"81", -- 0x1180
x"4F",x"FD",x"7E",x"01",x"88",x"47",x"FD",x"7E", -- 0x1188
x"02",x"8B",x"5F",x"FD",x"7E",x"03",x"8A",x"57", -- 0x1190
x"ED",x"43",x"14",x"40",x"ED",x"53",x"16",x"40", -- 0x1198
x"CD",x"B6",x"0F",x"21",x"01",x"00",x"F1",x"F1", -- 0x11A0
x"C9",x"21",x"EA",x"FF",x"39",x"F9",x"11",x"32", -- 0x11A8
x"40",x"21",x"05",x"00",x"39",x"EB",x"01",x"04", -- 0x11B0
x"00",x"ED",x"B0",x"2A",x"2C",x"40",x"FD",x"21", -- 0x11B8
x"0B",x"00",x"FD",x"39",x"FD",x"75",x"00",x"21", -- 0x11C0
x"0B",x"00",x"39",x"7E",x"B7",x"CA",x"AC",x"13", -- 0x11C8
x"21",x"36",x"42",x"E5",x"FD",x"21",x"07",x"00", -- 0x11D0
x"FD",x"39",x"FD",x"6E",x"02",x"FD",x"66",x"03", -- 0x11D8
x"E5",x"FD",x"6E",x"00",x"FD",x"66",x"01",x"E5", -- 0x11E0
x"CD",x"D9",x"0C",x"F1",x"F1",x"F1",x"7D",x"B7", -- 0x11E8
x"20",x"06",x"21",x"00",x"00",x"C3",x"AF",x"13", -- 0x11F0
x"FD",x"21",x"00",x"00",x"FD",x"39",x"FD",x"36", -- 0x11F8
x"00",x"36",x"FD",x"36",x"01",x"42",x"FD",x"7E", -- 0x1200
x"00",x"FD",x"21",x"14",x"00",x"FD",x"39",x"FD", -- 0x1208
x"77",x"00",x"21",x"01",x"00",x"39",x"7E",x"FD", -- 0x1210
x"21",x"14",x"00",x"FD",x"39",x"FD",x"77",x"01", -- 0x1218
x"FD",x"21",x"02",x"00",x"FD",x"39",x"FD",x"36", -- 0x1220
x"00",x"00",x"21",x"14",x"00",x"39",x"7E",x"23", -- 0x1228
x"66",x"6F",x"7E",x"FE",x"E5",x"CA",x"4E",x"13", -- 0x1230
x"B7",x"CA",x"4E",x"13",x"21",x"0B",x"00",x"E5", -- 0x1238
x"21",x"1C",x"00",x"39",x"4E",x"23",x"46",x"C5", -- 0x1240
x"21",x"18",x"00",x"39",x"4E",x"23",x"46",x"C5", -- 0x1248
x"CD",x"C3",x"0D",x"F1",x"F1",x"F1",x"7C",x"B5", -- 0x1250
x"CA",x"4E",x"13",x"21",x"18",x"00",x"39",x"7E", -- 0x1258
x"FD",x"21",x"03",x"00",x"FD",x"39",x"FD",x"77", -- 0x1260
x"00",x"21",x"19",x"00",x"39",x"7E",x"FD",x"21", -- 0x1268
x"03",x"00",x"FD",x"39",x"FD",x"77",x"01",x"E1", -- 0x1270
x"E5",x"11",x"0B",x"00",x"19",x"4E",x"FD",x"6E", -- 0x1278
x"00",x"FD",x"66",x"01",x"71",x"21",x"09",x"00", -- 0x1280
x"39",x"FD",x"7E",x"00",x"C6",x"01",x"77",x"FD", -- 0x1288
x"7E",x"01",x"CE",x"00",x"23",x"77",x"FD",x"21", -- 0x1290
x"00",x"00",x"FD",x"39",x"FD",x"7E",x"00",x"C6", -- 0x1298
x"1C",x"4F",x"FD",x"7E",x"01",x"CE",x"00",x"47", -- 0x12A0
x"C5",x"CD",x"AC",x"0D",x"F1",x"FD",x"21",x"10", -- 0x12A8
x"00",x"FD",x"39",x"FD",x"72",x"03",x"FD",x"73", -- 0x12B0
x"02",x"FD",x"74",x"01",x"FD",x"75",x"00",x"21", -- 0x12B8
x"09",x"00",x"39",x"5E",x"23",x"56",x"21",x"10", -- 0x12C0
x"00",x"39",x"01",x"04",x"00",x"ED",x"B0",x"21", -- 0x12C8
x"10",x"00",x"39",x"FD",x"21",x"03",x"00",x"FD", -- 0x12D0
x"39",x"FD",x"7E",x"00",x"C6",x"05",x"77",x"FD", -- 0x12D8
x"7E",x"01",x"CE",x"00",x"23",x"77",x"21",x"09", -- 0x12E0
x"00",x"39",x"FD",x"21",x"00",x"00",x"FD",x"39", -- 0x12E8
x"FD",x"7E",x"00",x"C6",x"1A",x"77",x"FD",x"7E", -- 0x12F0
x"01",x"CE",x"00",x"23",x"77",x"21",x"09",x"00", -- 0x12F8
x"39",x"4E",x"23",x"46",x"C5",x"CD",x"BA",x"0D", -- 0x1300
x"F1",x"FD",x"21",x"09",x"00",x"FD",x"39",x"FD", -- 0x1308
x"74",x"01",x"FD",x"75",x"00",x"21",x"09",x"00", -- 0x1310
x"39",x"7E",x"FD",x"21",x"0C",x"00",x"FD",x"39", -- 0x1318
x"FD",x"77",x"00",x"21",x"0A",x"00",x"39",x"7E", -- 0x1320
x"FD",x"21",x"0C",x"00",x"FD",x"39",x"FD",x"77", -- 0x1328
x"01",x"FD",x"36",x"02",x"00",x"FD",x"36",x"03", -- 0x1330
x"00",x"21",x"10",x"00",x"39",x"5E",x"23",x"56", -- 0x1338
x"21",x"0C",x"00",x"39",x"01",x"04",x"00",x"ED", -- 0x1340
x"B0",x"21",x"01",x"00",x"18",x"61",x"21",x"14", -- 0x1348
x"00",x"39",x"7E",x"C6",x"20",x"77",x"23",x"7E", -- 0x1350
x"CE",x"00",x"77",x"21",x"14",x"00",x"39",x"7E", -- 0x1358
x"FD",x"21",x"00",x"00",x"FD",x"39",x"FD",x"77", -- 0x1360
x"00",x"21",x"15",x"00",x"39",x"7E",x"FD",x"21", -- 0x1368
x"00",x"00",x"FD",x"39",x"FD",x"77",x"01",x"FD", -- 0x1370
x"21",x"02",x"00",x"FD",x"39",x"FD",x"34",x"00", -- 0x1378
x"FD",x"7E",x"00",x"D6",x"10",x"DA",x"2A",x"12", -- 0x1380
x"FD",x"21",x"05",x"00",x"FD",x"39",x"FD",x"34", -- 0x1388
x"00",x"20",x"0D",x"FD",x"34",x"01",x"20",x"08", -- 0x1390
x"FD",x"34",x"02",x"20",x"03",x"FD",x"34",x"03", -- 0x1398
x"FD",x"21",x"0B",x"00",x"FD",x"39",x"FD",x"35", -- 0x13A0
x"00",x"C3",x"C7",x"11",x"21",x"00",x"00",x"FD", -- 0x13A8
x"21",x"16",x"00",x"FD",x"39",x"FD",x"F9",x"C9", -- 0x13B0
x"F5",x"21",x"06",x"00",x"39",x"4E",x"23",x"46", -- 0x13B8
x"C5",x"21",x"06",x"00",x"39",x"4E",x"23",x"46", -- 0x13C0
x"C5",x"CD",x"A9",x"11",x"F1",x"F1",x"7C",x"B5", -- 0x13C8
x"20",x"05",x"21",x"00",x"00",x"18",x"38",x"21", -- 0x13D0
x"04",x"00",x"39",x"4E",x"23",x"46",x"0A",x"E6", -- 0x13D8
x"18",x"28",x"05",x"21",x"00",x"00",x"18",x"27", -- 0x13E0
x"21",x"09",x"00",x"09",x"E3",x"69",x"60",x"11", -- 0x13E8
x"05",x"00",x"19",x"4E",x"23",x"46",x"23",x"5E", -- 0x13F0
x"23",x"56",x"D5",x"C5",x"CD",x"BA",x"0E",x"F1", -- 0x13F8
x"F1",x"4D",x"44",x"E1",x"E5",x"71",x"23",x"70", -- 0x1400
x"23",x"73",x"23",x"72",x"21",x"01",x"00",x"F1", -- 0x1408
x"C9",x"F5",x"F5",x"F5",x"F5",x"21",x"0A",x"00", -- 0x1410
x"39",x"4E",x"23",x"46",x"21",x"09",x"00",x"09", -- 0x1418
x"E3",x"C5",x"21",x"02",x"00",x"39",x"5E",x"23", -- 0x1420
x"56",x"21",x"04",x"00",x"39",x"EB",x"01",x"04", -- 0x1428
x"00",x"ED",x"B0",x"C1",x"21",x"05",x"00",x"09", -- 0x1430
x"FD",x"21",x"06",x"00",x"FD",x"39",x"FD",x"75", -- 0x1438
x"00",x"FD",x"74",x"01",x"FD",x"6E",x"00",x"FD", -- 0x1440
x"66",x"01",x"4E",x"23",x"46",x"23",x"5E",x"23", -- 0x1448
x"56",x"0C",x"20",x"07",x"04",x"20",x"04",x"1C", -- 0x1450
x"20",x"01",x"14",x"D5",x"C5",x"CD",x"BA",x"0E", -- 0x1458
x"F1",x"F1",x"4D",x"44",x"FD",x"21",x"02",x"00", -- 0x1460
x"FD",x"39",x"FD",x"7E",x"00",x"91",x"20",x"6A", -- 0x1468
x"FD",x"7E",x"01",x"90",x"20",x"64",x"FD",x"7E", -- 0x1470
x"02",x"93",x"20",x"5E",x"FD",x"7E",x"03",x"92", -- 0x1478
x"20",x"58",x"21",x"06",x"00",x"39",x"7E",x"23", -- 0x1480
x"66",x"6F",x"4E",x"23",x"46",x"23",x"5E",x"23", -- 0x1488
x"56",x"D5",x"C5",x"CD",x"39",x"0F",x"F1",x"F1", -- 0x1490
x"4D",x"44",x"21",x"06",x"00",x"39",x"7E",x"23", -- 0x1498
x"66",x"6F",x"71",x"23",x"70",x"23",x"73",x"23", -- 0x14A0
x"72",x"D5",x"C5",x"CD",x"8B",x"0F",x"F1",x"F1", -- 0x14A8
x"7C",x"B5",x"28",x"05",x"21",x"FF",x"FF",x"18", -- 0x14B0
x"68",x"21",x"06",x"00",x"39",x"7E",x"23",x"66", -- 0x14B8
x"6F",x"4E",x"23",x"46",x"23",x"5E",x"23",x"56", -- 0x14C0
x"D5",x"C5",x"CD",x"BA",x"0E",x"F1",x"F1",x"4D", -- 0x14C8
x"44",x"E1",x"E5",x"71",x"23",x"70",x"23",x"73", -- 0x14D0
x"23",x"72",x"E1",x"E5",x"4E",x"23",x"46",x"23", -- 0x14D8
x"5E",x"23",x"56",x"79",x"21",x"02",x"00",x"39", -- 0x14E0
x"C6",x"01",x"77",x"78",x"CE",x"00",x"23",x"77", -- 0x14E8
x"7B",x"CE",x"00",x"23",x"77",x"7A",x"CE",x"00", -- 0x14F0
x"23",x"77",x"D5",x"C5",x"21",x"04",x"00",x"39", -- 0x14F8
x"5E",x"23",x"56",x"21",x"06",x"00",x"39",x"01", -- 0x1500
x"04",x"00",x"ED",x"B0",x"C1",x"D1",x"21",x"0C", -- 0x1508
x"00",x"39",x"7E",x"23",x"66",x"6F",x"E5",x"D5", -- 0x1510
x"C5",x"CD",x"D9",x"0C",x"F1",x"F1",x"F1",x"26", -- 0x1518
x"00",x"F1",x"F1",x"F1",x"F1",x"C9",x"21",x"ED", -- 0x1520
x"FF",x"39",x"F9",x"21",x"00",x"00",x"39",x"EB", -- 0x1528
x"FD",x"21",x"11",x"00",x"FD",x"39",x"FD",x"73", -- 0x1530
x"00",x"FD",x"72",x"01",x"D5",x"21",x"17",x"00", -- 0x1538
x"39",x"4E",x"23",x"46",x"C5",x"21",x"15",x"00", -- 0x1540
x"39",x"4E",x"23",x"46",x"C5",x"CD",x"A9",x"11", -- 0x1548
x"F1",x"F1",x"D1",x"7C",x"B5",x"20",x"05",x"21", -- 0x1550
x"00",x"00",x"18",x"42",x"1A",x"CB",x"67",x"20", -- 0x1558
x"05",x"21",x"00",x"00",x"18",x"38",x"13",x"13", -- 0x1560
x"13",x"13",x"13",x"D5",x"21",x"0F",x"00",x"39", -- 0x1568
x"EB",x"01",x"04",x"00",x"ED",x"B0",x"11",x"2E", -- 0x1570
x"40",x"21",x"0F",x"00",x"39",x"01",x"04",x"00", -- 0x1578
x"ED",x"B0",x"E1",x"4E",x"23",x"46",x"23",x"5E", -- 0x1580
x"23",x"56",x"D5",x"C5",x"CD",x"BA",x"0E",x"F1", -- 0x1588
x"F1",x"4D",x"44",x"ED",x"43",x"32",x"40",x"ED", -- 0x1590
x"53",x"34",x"40",x"21",x"01",x"00",x"FD",x"21", -- 0x1598
x"13",x"00",x"FD",x"39",x"FD",x"F9",x"C9",x"21", -- 0x15A0
x"03",x"00",x"39",x"7E",x"D3",x"99",x"21",x"02", -- 0x15A8
x"00",x"39",x"7E",x"E6",x"07",x"CB",x"FF",x"D3", -- 0x15B0
x"99",x"C9",x"28",x"00",x"00",x"00",x"00",x"00", -- 0x15B8
x"00",x"00",x"00",x"00",x"10",x"10",x"10",x"10", -- 0x15C0
x"00",x"10",x"00",x"00",x"24",x"24",x"00",x"00", -- 0x15C8
x"00",x"00",x"00",x"00",x"24",x"7E",x"24",x"24", -- 0x15D0
x"7E",x"24",x"00",x"00",x"08",x"3E",x"28",x"3E", -- 0x15D8
x"0A",x"3E",x"08",x"00",x"62",x"64",x"08",x"10", -- 0x15E0
x"26",x"46",x"00",x"00",x"10",x"28",x"10",x"2A", -- 0x15E8
x"44",x"3A",x"00",x"00",x"08",x"10",x"00",x"00", -- 0x15F0
x"00",x"00",x"00",x"00",x"04",x"08",x"08",x"08", -- 0x15F8
x"08",x"04",x"00",x"00",x"20",x"10",x"10",x"10", -- 0x1600
x"10",x"20",x"00",x"00",x"00",x"14",x"08",x"3E", -- 0x1608
x"08",x"14",x"00",x"00",x"00",x"08",x"08",x"3E", -- 0x1610
x"08",x"08",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1618
x"08",x"08",x"10",x"00",x"00",x"00",x"00",x"3E", -- 0x1620
x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x1628
x"18",x"18",x"00",x"00",x"00",x"02",x"04",x"08", -- 0x1630
x"10",x"20",x"00",x"00",x"3C",x"46",x"4A",x"52", -- 0x1638
x"62",x"3C",x"00",x"00",x"18",x"28",x"08",x"08", -- 0x1640
x"08",x"3E",x"00",x"00",x"3C",x"42",x"02",x"3C", -- 0x1648
x"40",x"7E",x"00",x"00",x"3C",x"42",x"0C",x"02", -- 0x1650
x"42",x"3C",x"00",x"00",x"08",x"18",x"28",x"48", -- 0x1658
x"7E",x"08",x"00",x"00",x"7E",x"40",x"7C",x"02", -- 0x1660
x"42",x"3C",x"00",x"00",x"3C",x"40",x"7C",x"42", -- 0x1668
x"42",x"3C",x"00",x"00",x"7E",x"02",x"04",x"08", -- 0x1670
x"10",x"10",x"00",x"00",x"3C",x"42",x"3C",x"42", -- 0x1678
x"42",x"3C",x"00",x"00",x"3C",x"42",x"42",x"3E", -- 0x1680
x"02",x"3C",x"00",x"00",x"00",x"00",x"10",x"00", -- 0x1688
x"00",x"10",x"00",x"00",x"00",x"10",x"00",x"00", -- 0x1690
x"10",x"10",x"20",x"00",x"00",x"04",x"08",x"10", -- 0x1698
x"08",x"04",x"00",x"00",x"00",x"00",x"3E",x"00", -- 0x16A0
x"3E",x"00",x"00",x"00",x"00",x"20",x"10",x"08", -- 0x16A8
x"10",x"20",x"00",x"00",x"3C",x"42",x"04",x"08", -- 0x16B0
x"00",x"08",x"00",x"00",x"3C",x"4A",x"56",x"5E", -- 0x16B8
x"40",x"3C",x"00",x"00",x"3C",x"42",x"42",x"7E", -- 0x16C0
x"42",x"42",x"00",x"00",x"7C",x"42",x"7C",x"42", -- 0x16C8
x"42",x"7C",x"00",x"00",x"3C",x"42",x"40",x"40", -- 0x16D0
x"42",x"3C",x"00",x"00",x"78",x"44",x"42",x"42", -- 0x16D8
x"44",x"78",x"00",x"00",x"7E",x"40",x"7C",x"40", -- 0x16E0
x"40",x"7E",x"00",x"00",x"7E",x"40",x"7C",x"40", -- 0x16E8
x"40",x"40",x"00",x"00",x"3C",x"42",x"40",x"4E", -- 0x16F0
x"42",x"3C",x"00",x"00",x"42",x"42",x"7E",x"42", -- 0x16F8
x"42",x"42",x"00",x"00",x"3E",x"08",x"08",x"08", -- 0x1700
x"08",x"3E",x"00",x"00",x"02",x"02",x"02",x"42", -- 0x1708
x"42",x"3C",x"00",x"00",x"44",x"48",x"70",x"48", -- 0x1710
x"44",x"42",x"00",x"00",x"40",x"40",x"40",x"40", -- 0x1718
x"40",x"7E",x"00",x"00",x"42",x"66",x"5A",x"42", -- 0x1720
x"42",x"42",x"00",x"00",x"42",x"62",x"52",x"4A", -- 0x1728
x"46",x"42",x"00",x"00",x"3C",x"42",x"42",x"42", -- 0x1730
x"42",x"3C",x"00",x"00",x"7C",x"42",x"42",x"7C", -- 0x1738
x"40",x"40",x"00",x"00",x"3C",x"42",x"42",x"52", -- 0x1740
x"4A",x"3C",x"00",x"00",x"7C",x"42",x"42",x"7C", -- 0x1748
x"44",x"42",x"00",x"00",x"3C",x"40",x"3C",x"02", -- 0x1750
x"42",x"3C",x"00",x"00",x"FE",x"10",x"10",x"10", -- 0x1758
x"10",x"10",x"00",x"00",x"42",x"42",x"42",x"42", -- 0x1760
x"42",x"3C",x"00",x"00",x"42",x"42",x"42",x"42", -- 0x1768
x"24",x"18",x"00",x"00",x"42",x"42",x"42",x"42", -- 0x1770
x"5A",x"24",x"00",x"00",x"42",x"24",x"18",x"18", -- 0x1778
x"24",x"42",x"00",x"00",x"82",x"44",x"28",x"10", -- 0x1780
x"10",x"10",x"00",x"00",x"7E",x"04",x"08",x"10", -- 0x1788
x"20",x"7E",x"00",x"00",x"0E",x"08",x"08",x"08", -- 0x1790
x"08",x"0E",x"00",x"00",x"00",x"40",x"20",x"10", -- 0x1798
x"08",x"04",x"00",x"00",x"70",x"10",x"10",x"10", -- 0x17A0
x"10",x"70",x"00",x"00",x"10",x"38",x"54",x"10", -- 0x17A8
x"10",x"10",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x17B0
x"00",x"00",x"FF",x"00",x"1C",x"22",x"78",x"20", -- 0x17B8
x"20",x"7E",x"00",x"00",x"00",x"38",x"04",x"3C", -- 0x17C0
x"44",x"3C",x"00",x"00",x"20",x"20",x"3C",x"22", -- 0x17C8
x"22",x"3C",x"00",x"00",x"00",x"1C",x"20",x"20", -- 0x17D0
x"20",x"1C",x"00",x"00",x"04",x"04",x"3C",x"44", -- 0x17D8
x"44",x"3C",x"00",x"00",x"00",x"38",x"44",x"78", -- 0x17E0
x"40",x"3C",x"00",x"00",x"0C",x"10",x"18",x"10", -- 0x17E8
x"10",x"10",x"00",x"00",x"00",x"3C",x"44",x"44", -- 0x17F0
x"3C",x"04",x"38",x"00",x"40",x"40",x"78",x"44", -- 0x17F8
x"44",x"44",x"00",x"00",x"10",x"00",x"30",x"10", -- 0x1800
x"10",x"38",x"00",x"00",x"04",x"00",x"04",x"04", -- 0x1808
x"04",x"24",x"18",x"00",x"20",x"28",x"30",x"30", -- 0x1810
x"28",x"24",x"00",x"00",x"10",x"10",x"10",x"10", -- 0x1818
x"10",x"0C",x"00",x"00",x"00",x"68",x"54",x"54", -- 0x1820
x"54",x"54",x"00",x"00",x"00",x"78",x"44",x"44", -- 0x1828
x"44",x"44",x"00",x"00",x"00",x"38",x"44",x"44", -- 0x1830
x"44",x"38",x"00",x"00",x"00",x"78",x"44",x"44", -- 0x1838
x"78",x"40",x"40",x"00",x"00",x"3C",x"44",x"44", -- 0x1840
x"3C",x"04",x"06",x"00",x"00",x"1C",x"20",x"20", -- 0x1848
x"20",x"20",x"00",x"00",x"00",x"38",x"40",x"38", -- 0x1850
x"04",x"78",x"00",x"00",x"10",x"38",x"10",x"10", -- 0x1858
x"10",x"0C",x"00",x"00",x"00",x"44",x"44",x"44", -- 0x1860
x"44",x"38",x"00",x"00",x"00",x"44",x"44",x"28", -- 0x1868
x"28",x"10",x"00",x"00",x"00",x"44",x"54",x"54", -- 0x1870
x"54",x"28",x"00",x"00",x"00",x"44",x"28",x"10", -- 0x1878
x"28",x"44",x"00",x"00",x"00",x"44",x"44",x"44", -- 0x1880
x"3C",x"04",x"38",x"00",x"00",x"7C",x"08",x"10", -- 0x1888
x"20",x"7C",x"00",x"00",x"0E",x"08",x"30",x"08", -- 0x1890
x"08",x"0E",x"00",x"00",x"08",x"08",x"08",x"08", -- 0x1898
x"08",x"08",x"00",x"00",x"70",x"10",x"0C",x"10", -- 0x18A0
x"10",x"70",x"00",x"00",x"14",x"28",x"00",x"00", -- 0x18A8
x"00",x"00",x"00",x"3C",x"42",x"99",x"A1",x"A1", -- 0x18B0
x"99",x"42",x"3C",x"00",x"C0",x"02",x"2C",x"00", -- 0x18B8
x"00",x"00",x"F7",x"FD",x"21",x"02",x"00",x"FD", -- 0x18C0
x"39",x"FD",x"7E",x"00",x"D3",x"99",x"FD",x"7E", -- 0x18C8
x"01",x"E6",x"3F",x"4F",x"06",x"00",x"21",x"04", -- 0x18D0
x"00",x"39",x"7E",x"E6",x"01",x"0F",x"0F",x"E6", -- 0x18D8
x"C0",x"5F",x"16",x"00",x"79",x"B3",x"4F",x"78", -- 0x18E0
x"B2",x"79",x"D3",x"99",x"C9",x"3E",x"01",x"F5", -- 0x18E8
x"33",x"21",x"05",x"00",x"39",x"4E",x"23",x"46", -- 0x18F0
x"C5",x"CD",x"C3",x"18",x"F1",x"33",x"01",x"00", -- 0x18F8
x"00",x"21",x"06",x"00",x"39",x"79",x"96",x"78", -- 0x1900
x"23",x"9E",x"D0",x"21",x"02",x"00",x"39",x"7E", -- 0x1908
x"23",x"66",x"6F",x"09",x"7E",x"D3",x"98",x"1E", -- 0x1910
x"0A",x"53",x"15",x"7A",x"5F",x"B7",x"20",x"F9", -- 0x1918
x"03",x"18",x"DE",x"FD",x"21",x"36",x"44",x"FD", -- 0x1920
x"34",x"00",x"3E",x"1F",x"FD",x"96",x"00",x"D0", -- 0x1928
x"FD",x"36",x"00",x"00",x"FD",x"21",x"37",x"44", -- 0x1930
x"FD",x"34",x"00",x"3E",x"17",x"FD",x"96",x"00", -- 0x1938
x"D0",x"FD",x"36",x"00",x"17",x"C9",x"01",x"BB", -- 0x1940
x"18",x"16",x"00",x"6A",x"26",x"00",x"09",x"66", -- 0x1948
x"C5",x"D5",x"E5",x"33",x"D5",x"33",x"CD",x"A7", -- 0x1950
x"15",x"F1",x"D1",x"C1",x"14",x"7A",x"D6",x"08", -- 0x1958
x"38",x"E9",x"3E",x"01",x"F5",x"33",x"21",x"00", -- 0x1960
x"00",x"E5",x"CD",x"C3",x"18",x"F1",x"33",x"01", -- 0x1968
x"00",x"00",x"3E",x"00",x"D3",x"98",x"03",x"78", -- 0x1970
x"D6",x"01",x"38",x"F6",x"21",x"00",x"03",x"E5", -- 0x1978
x"26",x"01",x"E5",x"21",x"BB",x"15",x"E5",x"CD", -- 0x1980
x"ED",x"18",x"F1",x"F1",x"26",x"01",x"E3",x"33", -- 0x1988
x"21",x"00",x"04",x"E5",x"CD",x"C3",x"18",x"F1", -- 0x1990
x"33",x"01",x"00",x"00",x"3E",x"00",x"D3",x"98", -- 0x1998
x"03",x"78",x"D6",x"04",x"38",x"F6",x"21",x"37", -- 0x19A0
x"44",x"36",x"00",x"21",x"36",x"44",x"36",x"00", -- 0x19A8
x"21",x"38",x"44",x"36",x"0F",x"21",x"39",x"44", -- 0x19B0
x"36",x"07",x"3E",x"01",x"F5",x"33",x"21",x"00", -- 0x19B8
x"08",x"E5",x"CD",x"C3",x"18",x"F1",x"33",x"01", -- 0x19C0
x"00",x"00",x"3E",x"20",x"D3",x"98",x"03",x"78", -- 0x19C8
x"D6",x"03",x"38",x"F6",x"C9",x"21",x"04",x"00", -- 0x19D0
x"39",x"7E",x"E6",x"0F",x"07",x"07",x"07",x"07", -- 0x19D8
x"E6",x"F0",x"47",x"21",x"03",x"00",x"39",x"7E", -- 0x19E0
x"E6",x"0F",x"B0",x"4F",x"21",x"02",x"00",x"39", -- 0x19E8
x"7E",x"E6",x"0F",x"B0",x"47",x"C5",x"C5",x"33", -- 0x19F0
x"3E",x"07",x"F5",x"33",x"CD",x"A7",x"15",x"26", -- 0x19F8
x"01",x"E3",x"33",x"21",x"00",x"0B",x"E5",x"CD", -- 0x1A00
x"C3",x"18",x"F1",x"33",x"C1",x"06",x"00",x"79", -- 0x1A08
x"D3",x"98",x"04",x"78",x"D6",x"20",x"38",x"F7", -- 0x1A10
x"21",x"04",x"00",x"39",x"7E",x"32",x"38",x"44", -- 0x1A18
x"21",x"03",x"00",x"39",x"7E",x"32",x"39",x"44", -- 0x1A20
x"C9",x"3E",x"01",x"F5",x"33",x"21",x"00",x"08", -- 0x1A28
x"E5",x"CD",x"C3",x"18",x"F1",x"33",x"01",x"00", -- 0x1A30
x"00",x"3E",x"20",x"D3",x"98",x"03",x"78",x"D6", -- 0x1A38
x"03",x"38",x"F6",x"C9",x"21",x"02",x"00",x"39", -- 0x1A40
x"7E",x"E6",x"1F",x"32",x"36",x"44",x"21",x"03", -- 0x1A48
x"00",x"39",x"7E",x"FD",x"21",x"37",x"44",x"FD", -- 0x1A50
x"77",x"00",x"3E",x"17",x"FD",x"96",x"00",x"D0", -- 0x1A58
x"FD",x"36",x"00",x"17",x"C9",x"21",x"02",x"00", -- 0x1A60
x"39",x"7E",x"E6",x"1F",x"32",x"36",x"44",x"21", -- 0x1A68
x"03",x"00",x"39",x"7E",x"FD",x"21",x"37",x"44", -- 0x1A70
x"FD",x"77",x"00",x"3E",x"17",x"FD",x"96",x"00", -- 0x1A78
x"30",x"04",x"FD",x"36",x"00",x"17",x"FD",x"21", -- 0x1A80
x"37",x"44",x"FD",x"6E",x"00",x"26",x"00",x"29", -- 0x1A88
x"29",x"29",x"29",x"29",x"01",x"00",x"08",x"09", -- 0x1A90
x"4D",x"44",x"FD",x"21",x"36",x"44",x"FD",x"6E", -- 0x1A98
x"00",x"26",x"00",x"09",x"4D",x"44",x"3E",x"01", -- 0x1AA0
x"F5",x"33",x"C5",x"CD",x"C3",x"18",x"F1",x"33", -- 0x1AA8
x"21",x"04",x"00",x"39",x"7E",x"D3",x"98",x"C3", -- 0x1AB0
x"23",x"19",x"21",x"02",x"00",x"39",x"7E",x"D6", -- 0x1AB8
x"0A",x"20",x"13",x"21",x"36",x"44",x"36",x"00", -- 0x1AC0
x"FD",x"21",x"37",x"44",x"FD",x"7E",x"00",x"D6", -- 0x1AC8
x"17",x"D0",x"FD",x"34",x"00",x"C9",x"21",x"02", -- 0x1AD0
x"00",x"39",x"7E",x"F5",x"33",x"3A",x"37",x"44", -- 0x1AD8
x"F5",x"33",x"3A",x"36",x"44",x"F5",x"33",x"CD", -- 0x1AE0
x"65",x"1A",x"F1",x"33",x"C9",x"21",x"36",x"44", -- 0x1AE8
x"4E",x"06",x"00",x"21",x"00",x"0B",x"09",x"4D", -- 0x1AF0
x"44",x"21",x"03",x"00",x"39",x"7E",x"E6",x"0F", -- 0x1AF8
x"07",x"07",x"07",x"07",x"E6",x"F0",x"21",x"39", -- 0x1B00
x"44",x"B6",x"5F",x"D5",x"3E",x"01",x"F5",x"33", -- 0x1B08
x"C5",x"CD",x"C3",x"18",x"F1",x"33",x"D1",x"7B", -- 0x1B10
x"D3",x"98",x"21",x"02",x"00",x"39",x"7E",x"F5", -- 0x1B18
x"33",x"3A",x"37",x"44",x"F5",x"33",x"3A",x"36", -- 0x1B20
x"44",x"F5",x"33",x"CD",x"65",x"1A",x"F1",x"33", -- 0x1B28
x"C9",x"C1",x"E1",x"E5",x"C5",x"46",x"E5",x"C5", -- 0x1B30
x"33",x"CD",x"BA",x"1A",x"33",x"E1",x"23",x"7E", -- 0x1B38
x"B7",x"20",x"F2",x"C9",x"21",x"02",x"00",x"39", -- 0x1B40
x"4E",x"0D",x"69",x"26",x"00",x"29",x"29",x"F5", -- 0x1B48
x"FD",x"21",x"05",x"00",x"FD",x"39",x"FD",x"5E", -- 0x1B50
x"00",x"FD",x"56",x"01",x"F1",x"2C",x"18",x"04", -- 0x1B58
x"CB",x"3A",x"CB",x"1B",x"2D",x"20",x"F9",x"7B", -- 0x1B60
x"E6",x"0F",x"E6",x"0F",x"5F",x"43",x"3E",x"09", -- 0x1B68
x"93",x"30",x"0E",x"78",x"C6",x"37",x"47",x"C5", -- 0x1B70
x"C5",x"33",x"CD",x"BA",x"1A",x"33",x"C1",x"18", -- 0x1B78
x"0C",x"78",x"C6",x"30",x"47",x"C5",x"C5",x"33", -- 0x1B80
x"CD",x"BA",x"1A",x"33",x"C1",x"0D",x"18",x"BA", -- 0x1B88
x"21",x"02",x"00",x"39",x"4E",x"06",x"00",x"C5", -- 0x1B90
x"3E",x"02",x"F5",x"33",x"CD",x"44",x"1B",x"F1", -- 0x1B98
x"33",x"C9",x"C1",x"E1",x"E5",x"C5",x"E5",x"3E", -- 0x1BA0
x"04",x"F5",x"33",x"CD",x"44",x"1B",x"F1",x"33", -- 0x1BA8
x"C9",x"3B",x"FD",x"21",x"00",x"00",x"FD",x"39", -- 0x1BB0
x"FD",x"36",x"00",x"00",x"FD",x"21",x"03",x"00", -- 0x1BB8
x"FD",x"39",x"FD",x"7E",x"01",x"FD",x"B6",x"00", -- 0x1BC0
x"28",x"5E",x"FD",x"6E",x"00",x"FD",x"66",x"01", -- 0x1BC8
x"E5",x"21",x"07",x"00",x"39",x"4E",x"23",x"46", -- 0x1BD0
x"C5",x"CD",x"4E",x"1C",x"F1",x"F1",x"01",x"0A", -- 0x1BD8
x"00",x"C5",x"E5",x"CD",x"AA",x"1C",x"F1",x"F1", -- 0x1BE0
x"7D",x"4F",x"B7",x"20",x"08",x"21",x"00",x"00", -- 0x1BE8
x"39",x"7E",x"B7",x"28",x"14",x"79",x"C6",x"30", -- 0x1BF0
x"47",x"C5",x"33",x"CD",x"BA",x"1A",x"33",x"FD", -- 0x1BF8
x"21",x"00",x"00",x"FD",x"39",x"FD",x"36",x"00", -- 0x1C00
x"01",x"21",x"0A",x"00",x"E5",x"21",x"05",x"00", -- 0x1C08
x"39",x"4E",x"23",x"46",x"C5",x"CD",x"4E",x"1C", -- 0x1C10
x"F1",x"F1",x"FD",x"21",x"03",x"00",x"FD",x"39", -- 0x1C18
x"FD",x"75",x"00",x"FD",x"74",x"01",x"18",x"94", -- 0x1C20
x"33",x"C9",x"21",x"02",x"00",x"39",x"4E",x"06", -- 0x1C28
x"00",x"C5",x"21",x"64",x"00",x"E5",x"CD",x"B1", -- 0x1C30
x"1B",x"F1",x"F1",x"C9",x"21",x"02",x"00",x"39", -- 0x1C38
x"4E",x"06",x"00",x"C5",x"21",x"10",x"27",x"E5", -- 0x1C40
x"CD",x"B1",x"1B",x"F1",x"F1",x"C9",x"F1",x"E1", -- 0x1C48
x"D1",x"D5",x"E5",x"F5",x"18",x"0A",x"21",x"03", -- 0x1C50
x"00",x"39",x"5E",x"2B",x"6E",x"26",x"00",x"54", -- 0x1C58
x"7B",x"E6",x"80",x"B2",x"20",x"10",x"06",x"10", -- 0x1C60
x"ED",x"6A",x"17",x"93",x"30",x"01",x"83",x"3F", -- 0x1C68
x"ED",x"6A",x"10",x"F6",x"5F",x"C9",x"06",x"09", -- 0x1C70
x"7D",x"6C",x"26",x"00",x"CB",x"1D",x"ED",x"6A", -- 0x1C78
x"ED",x"52",x"30",x"01",x"19",x"3F",x"17",x"10", -- 0x1C80
x"F5",x"CB",x"10",x"50",x"5F",x"EB",x"C9",x"C1", -- 0x1C88
x"E1",x"E5",x"C5",x"AF",x"47",x"4F",x"ED",x"B1", -- 0x1C90
x"21",x"FF",x"FF",x"ED",x"42",x"C9",x"21",x"03", -- 0x1C98
x"00",x"39",x"5E",x"2B",x"6E",x"CD",x"5D",x"1C", -- 0x1CA0
x"EB",x"C9",x"F1",x"E1",x"D1",x"D5",x"E5",x"F5", -- 0x1CA8
x"CD",x"60",x"1C",x"EB",x"C9",x"F1",x"E1",x"D1", -- 0x1CB0
x"D5",x"E5",x"F5",x"44",x"4D",x"AF",x"6F",x"B0", -- 0x1CB8
x"06",x"10",x"20",x"04",x"06",x"08",x"79",x"29", -- 0x1CC0
x"CB",x"11",x"17",x"30",x"01",x"19",x"10",x"F7", -- 0x1CC8
x"C9",x"DD",x"E5",x"DD",x"21",x"00",x"00",x"DD", -- 0x1CD0
x"39",x"21",x"FA",x"FF",x"39",x"F9",x"21",x"0A", -- 0x1CD8
x"00",x"39",x"4D",x"44",x"23",x"23",x"DD",x"75", -- 0x1CE0
x"FE",x"DD",x"74",x"FF",x"69",x"60",x"23",x"23", -- 0x1CE8
x"5E",x"23",x"56",x"21",x"0E",x"00",x"39",x"DD", -- 0x1CF0
x"75",x"FC",x"DD",x"74",x"FD",x"DD",x"6E",x"FC", -- 0x1CF8
x"DD",x"66",x"FD",x"7E",x"23",x"66",x"6F",x"C5", -- 0x1D00
x"E5",x"D5",x"CD",x"B5",x"1C",x"F1",x"F1",x"55", -- 0x1D08
x"5C",x"C1",x"DD",x"6E",x"FE",x"DD",x"66",x"FF", -- 0x1D10
x"72",x"23",x"73",x"69",x"60",x"23",x"23",x"DD", -- 0x1D18
x"75",x"FE",x"DD",x"74",x"FF",x"69",x"60",x"23", -- 0x1D20
x"23",x"7E",x"DD",x"77",x"FA",x"23",x"7E",x"DD", -- 0x1D28
x"77",x"FB",x"D1",x"E1",x"E5",x"D5",x"23",x"23", -- 0x1D30
x"5E",x"23",x"56",x"69",x"60",x"7E",x"23",x"66", -- 0x1D38
x"6F",x"C5",x"E5",x"D5",x"CD",x"B5",x"1C",x"F1", -- 0x1D40
x"F1",x"C1",x"DD",x"7E",x"FA",x"85",x"57",x"DD", -- 0x1D48
x"7E",x"FB",x"8C",x"5F",x"DD",x"6E",x"FE",x"DD", -- 0x1D50
x"66",x"FF",x"72",x"23",x"73",x"69",x"60",x"23", -- 0x1D58
x"23",x"E3",x"69",x"60",x"23",x"23",x"5E",x"23", -- 0x1D60
x"56",x"69",x"60",x"23",x"7E",x"DD",x"77",x"FE", -- 0x1D68
x"DD",x"6E",x"FC",x"DD",x"66",x"FD",x"23",x"66", -- 0x1D70
x"D5",x"C5",x"DD",x"5E",x"FE",x"2E",x"00",x"55", -- 0x1D78
x"06",x"08",x"29",x"30",x"01",x"19",x"10",x"FA", -- 0x1D80
x"C1",x"D1",x"19",x"EB",x"E1",x"E5",x"73",x"23", -- 0x1D88
x"72",x"D1",x"E1",x"E5",x"D5",x"5E",x"69",x"60", -- 0x1D90
x"23",x"66",x"C5",x"2E",x"00",x"55",x"06",x"08", -- 0x1D98
x"29",x"30",x"01",x"19",x"10",x"FA",x"C1",x"EB", -- 0x1DA0
x"DD",x"6E",x"FC",x"DD",x"66",x"FD",x"23",x"E5", -- 0x1DA8
x"FD",x"E1",x"69",x"60",x"7E",x"DD",x"77",x"FA", -- 0x1DB0
x"DD",x"6E",x"FC",x"DD",x"66",x"FD",x"23",x"7E", -- 0x1DB8
x"D5",x"C5",x"5F",x"DD",x"66",x"FA",x"2E",x"00", -- 0x1DC0
x"55",x"06",x"08",x"29",x"30",x"01",x"19",x"10", -- 0x1DC8
x"FA",x"C1",x"D1",x"FD",x"75",x"00",x"FD",x"74", -- 0x1DD0
x"01",x"DD",x"6E",x"FC",x"DD",x"66",x"FD",x"23", -- 0x1DD8
x"23",x"23",x"E3",x"DD",x"6E",x"FC",x"DD",x"66", -- 0x1DE0
x"FD",x"23",x"E5",x"FD",x"E1",x"DD",x"6E",x"FC", -- 0x1DE8
x"DD",x"66",x"FD",x"23",x"7E",x"23",x"66",x"6F", -- 0x1DF0
x"19",x"FD",x"75",x"00",x"FD",x"74",x"01",x"BF", -- 0x1DF8
x"ED",x"52",x"3E",x"00",x"17",x"E1",x"E5",x"77", -- 0x1E00
x"59",x"50",x"0A",x"4F",x"DD",x"6E",x"FC",x"DD", -- 0x1E08
x"66",x"FD",x"66",x"D5",x"59",x"2E",x"00",x"55", -- 0x1E10
x"06",x"08",x"29",x"30",x"01",x"19",x"10",x"FA", -- 0x1E18
x"D1",x"4D",x"44",x"79",x"12",x"13",x"78",x"12", -- 0x1E20
x"C1",x"E1",x"E5",x"C5",x"36",x"00",x"DD",x"7E", -- 0x1E28
x"04",x"DD",x"86",x"08",x"6F",x"DD",x"7E",x"05", -- 0x1E30
x"DD",x"8E",x"09",x"67",x"DD",x"7E",x"06",x"DD", -- 0x1E38
x"8E",x"0A",x"5F",x"DD",x"7E",x"07",x"DD",x"8E", -- 0x1E40
x"0B",x"57",x"DD",x"F9",x"DD",x"E1",x"C9",x"D2", -- 0x1E48
x"0B",x"DE",x"0B",x"EA",x"0B",x"F6",x"0B",x"02", -- 0x1E50
x"0C",x"0E",x"0C",x"1A",x"0C",x"26",x"0C",x"32", -- 0x1E58
x"0C",x"3E",x"0C",x"A5",x"0D",x"FE",x"3F",x"01", -- 0x1E60
x"18",x"00",x"78",x"B1",x"28",x"08",x"11",x"3A", -- 0x1E68
x"44",x"21",x"4F",x"1E",x"ED",x"B0",x"C9",x"FF", -- 0x1E70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1E98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1ED0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1ED8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1EF8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F00
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F08
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F10
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F18
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F20
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F28
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F30
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F38
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F40
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F48
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F50
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F58
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F60
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F68
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F70
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F78
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F80
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F88
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F90
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1F98
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FA0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FA8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FB0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FB8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FC0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FC8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FD0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FD8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FE0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FE8
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x1FF0
x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF" -- 0x1FF8
);
begin
process(clk)
begin
if rising_edge(clk) then
data <= ROM(to_integer(unsigned(addr)));
end if;
end process;
end RTL;
|
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity GrayIncReg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity GrayIncReg;
architecture MyHDL of GrayIncReg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= (others => '0');
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(gray_inc_1_bincnt, 9);
for i in 0 to 8-1 loop
graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
GRAYINCREG_REG_1: process (clock) is
begin
if rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAYINCREG_REG_1;
end architecture MyHDL;
|
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity GrayIncReg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity GrayIncReg;
architecture MyHDL of GrayIncReg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= (others => '0');
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(gray_inc_1_bincnt, 9);
for i in 0 to 8-1 loop
graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
GRAYINCREG_REG_1: process (clock) is
begin
if rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAYINCREG_REG_1;
end architecture MyHDL;
|
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity GrayIncReg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity GrayIncReg;
architecture MyHDL of GrayIncReg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= (others => '0');
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(gray_inc_1_bincnt, 9);
for i in 0 to 8-1 loop
graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
GRAYINCREG_REG_1: process (clock) is
begin
if rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAYINCREG_REG_1;
end architecture MyHDL;
|
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity GrayIncReg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity GrayIncReg;
architecture MyHDL of GrayIncReg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= (others => '0');
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(gray_inc_1_bincnt, 9);
for i in 0 to 8-1 loop
graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
GRAYINCREG_REG_1: process (clock) is
begin
if rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAYINCREG_REG_1;
end architecture MyHDL;
|
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity GrayIncReg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity GrayIncReg;
architecture MyHDL of GrayIncReg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= (others => '0');
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(gray_inc_1_bincnt, 9);
for i in 0 to 8-1 loop
graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
GRAYINCREG_REG_1: process (clock) is
begin
if rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAYINCREG_REG_1;
end architecture MyHDL;
|
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity GrayIncReg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity GrayIncReg;
architecture MyHDL of GrayIncReg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= (others => '0');
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(gray_inc_1_bincnt, 9);
for i in 0 to 8-1 loop
graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
GRAYINCREG_REG_1: process (clock) is
begin
if rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAYINCREG_REG_1;
end architecture MyHDL;
|
-- File: GrayIncReg.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Dec 21 15:02:38 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity GrayIncReg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity GrayIncReg;
architecture MyHDL of GrayIncReg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= (others => '0');
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC;
GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC: process (gray_inc_1_bincnt) is
variable Bext: unsigned(8 downto 0);
begin
Bext := to_unsigned(0, 9);
Bext := resize(gray_inc_1_bincnt, 9);
for i in 0 to 8-1 loop
graycnt_comb(i) <= (Bext((i + 1)) xor Bext(i));
end loop;
end process GRAYINCREG_GRAY_INC_1_BIN2GRAY_1_LOGIC;
GRAYINCREG_REG_1: process (clock) is
begin
if rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAYINCREG_REG_1;
end architecture MyHDL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------
-- synthesis translate_off
library ims;
use ims.coprocessor.all;
-- synthesis translate_on
-------------------------------------------------------------------------
ENTITY Q16_8_DoubleMini is
PORT (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
ARCHITECTURE rtl of Q16_8_DoubleMini IS
BEGIN
-------------------------------------------------------------------------
-- synthesis translate_off
PROCESS
BEGIN
WAIT FOR 1 ns;
printmsg("(IMS) Q16_8_DoubleMini : ALLOCATION OK !");
WAIT;
END PROCESS;
-- synthesis translate_on
-------------------------------------------------------------------------
-------------------------------------------------------------------------
PROCESS (INPUT_1, INPUT_2)
VARIABLE OP1 : SIGNED(15 downto 0);
VARIABLE MIN1 : SIGNED(15 downto 0);
VARIABLE MIN2 : SIGNED(15 downto 0);
BEGIN
--
-- ON RECUPERE NOS OPERANDES
--
OP1 := SIGNED(INPUT_1(15 downto 0));
MIN1 := SIGNED(INPUT_2(31 downto 16));
MIN2 := SIGNED(INPUT_2(15 downto 0));
--
-- ON CALCULE LA VALEUR ABSOLUE DE L'ENTREE
--
OP1 := abs( OP1 );
--
-- ON CALCULE LE MIN QUI VA BIEN
--
IF OP1 < MIN1 THEN
MIN2 := MIN1;
MIN1 := OP1;
ELSIF OP1 < MIN2 THEN
MIN2 := OP1;
END IF;
OUTPUT_1 <= STD_LOGIC_VECTOR(MIN1) & STD_LOGIC_VECTOR(MIN2);
END PROCESS;
-------------------------------------------------------------------------
END;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_low_1/bg_low_stub.vhdl
-- Design : bg_low
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_low is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_low;
architecture stub of bg_low is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[10:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_low_1/bg_low_stub.vhdl
-- Design : bg_low
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bg_low is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end bg_low;
architecture stub of bg_low is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[10:0],dina[11:0],douta[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_5,Vivado 2016.4";
begin
end;
|
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_589 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_589;
architecture augh of mul_589 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_589 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_589;
architecture augh of mul_589 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
-------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 11-May-13, 26-May-13
-------------------------------------------------------------------------------
-- Total # of FFs: DW
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity rom is
port(clk : in std_logic;
-- ROM bus signals
bus_in : in t_bus2ros;
bus_out : out t_ros2bus
);
end rom;
architecture rtl of rom is
type t_rom is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
constant rom_table : t_rom := (
---------------------------------------------------------------------------
-- program code -----------------------------------------------------------
---------------------------------------------------------------------------
-- addr Opcode Rdest Rsrc1 Rsrc2 description
---------------------------------------------------------------------------
-- auto generated by asmtovhd from floppy.asm
0 => OPC(setih) & reg(0) & std_logic_vector(to_unsigned(0,DW/2)), --
1 => OPC(setih) & reg(1) & std_logic_vector(to_unsigned(0,DW/2)), --
2 => OPC(setih) & reg(2) & std_logic_vector(to_unsigned(0,DW/2)), --
3 => OPC(setih) & reg(3) & std_logic_vector(to_unsigned(0,DW/2)), --
4 => OPC(setih) & reg(4) & std_logic_vector(to_unsigned(16#FF#,DW/2)), --
5 => OPC(setil) & reg(4) & std_logic_vector(to_unsigned(16#FF#,DW/2)), --
6 => OPC(setih) & reg(5) & std_logic_vector(to_unsigned(0,DW/2)), --
7 => OPC(setih) & reg(6) & std_logic_vector(to_unsigned(0,DW/2)), --
8 => OPC(setih) & reg(7) & std_logic_vector(to_unsigned(0,DW/2)), --
9 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(16#84#,DW/2)), --
10 => OPC(ld) & reg(1) & reg(0) & "---" & "--", --
11 => OPC(add) & reg(1) & reg(1) & reg(3) & "--", --
12 => OPC(bne) & "---" & std_logic_vector(to_signed(-3,DW/2)), --
13 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#86#,DW/2)), --
14 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(69,DW/2)), --
15 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
16 => OPC(add) & reg(6) & reg(5) & reg(3) & "--", --
17 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(16#80#,DW/2)), --
18 => OPC(ld) & reg(5) & reg(0) & "---" & "--", --
19 => OPC(add) & reg(0) & reg(3) & reg(4) & "--", --
20 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
21 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(1,DW/2)), --
22 => OPC(andi) & reg(1) & reg(1) & reg(5) & "--", --
23 => OPC(bne) & "---" & std_logic_vector(to_signed(+2,DW/2)), --
24 => OPC(add) & reg(0) & reg(3) & reg(3) & "--", --
25 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#82#,DW/2)), --
26 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
27 => OPC(add) & reg(0) & reg(3) & reg(4) & "--", --
28 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
29 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(2,DW/2)), --
30 => OPC(andi) & reg(1) & reg(1) & reg(5) & "--", --
31 => OPC(bne) & "---" & std_logic_vector(to_signed(+2,DW/2)), --
32 => OPC(add) & reg(0) & reg(3) & reg(3) & "--", --
33 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#83#,DW/2)), --
34 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
35 => OPC(xori) & reg(0) & reg(6) & reg(4) & "--", --
36 => OPC(andi) & reg(0) & reg(0) & reg(5) & "--", --
37 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
38 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(16#10#,DW/2)), --
39 => OPC(andi) & reg(0) & reg(0) & reg(1) & "--", --
40 => OPC(xori) & reg(0) & reg(0) & reg(1) & "--", --
41 => OPC(bne) & "---" & std_logic_vector(to_signed(+6,DW/2)), --
42 => OPC(add) & reg(2) & reg(3) & reg(3) & "--", --
43 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#86#,DW/2)), --
44 => OPC(ld) & reg(0) & reg(2) & "---" & "--", --
45 => OPC(addil) & reg(0) & std_logic_vector(to_unsigned(1,DW/2)), --
46 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
47 => OPC(xori) & reg(0) & reg(6) & reg(4) & "--", --
48 => OPC(andi) & reg(0) & reg(0) & reg(5) & "--", --
49 => OPC(add) & reg(1) & reg(3) & reg(3) & "--", --
50 => OPC(setil) & reg(1) & std_logic_vector(to_unsigned(16#20#,DW/2)), --
51 => OPC(andi) & reg(0) & reg(0) & reg(1) & "--", --
52 => OPC(xori) & reg(0) & reg(0) & reg(1) & "--", --
53 => OPC(bne) & "---" & std_logic_vector(to_signed(+6,DW/2)), --
54 => OPC(add) & reg(2) & reg(3) & reg(3) & "--", --
55 => OPC(setil) & reg(2) & std_logic_vector(to_unsigned(16#86#,DW/2)), --
56 => OPC(ld) & reg(0) & reg(2) & "---" & "--", --
57 => OPC(addil) & reg(0) & std_logic_vector(to_signed(-1,DW/2)), --
58 => OPC(st) & reg(0) & reg(2) & "---" & "--", --
59 => OPC(add) & reg(7) & reg(3) & reg(5) & "--", --
60 => OPC(setil) & reg(0) & std_logic_vector(to_unsigned(16#81#,DW/2)), --
61 => OPC(st) & reg(7) & reg(0) & "---" & "--", --
62 => OPC(jmp) & "---" & std_logic_vector(to_unsigned(16,DW/2)), --
63 => OPC(nop) & "---" & "---" & "---" & "--", --
others => (others => '1')
);
begin
-----------------------------------------------------------------------------
-- sequential process: ROM table with registerd output
-----------------------------------------------------------------------------
P_rom: process(clk)
begin
if rising_edge(clk) then
bus_out.data <= rom_table(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package types is
-- Declare types
subtype voltage is std_logic_vector(3 downto 0);
type voltage_vector is array (natural range <>) of voltage;
-- Declare constants
constant zero : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(0,4));
constant Vth : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(3,4));
constant Vth_neg : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(-3,4));
constant Vr: STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(2,4));
constant Vr_neg : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(-2,4));
constant Vw : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(4,4));
constant Vw_neg : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(-4,4));
constant Vn : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(7,4));
constant Vn_neg : STD_LOGIC_VECTOR(3 downto 0) := std_logic_vector(to_signed(-7,4));
-- Declare functions
function verify_voltage (v: voltage) return boolean;
end types;
package body types is
function verify_voltage (v: voltage) return boolean is
begin
case v is
when "0000" => return true;
when "0001" => return true;
when "0010" => return true;
when "0011" => return true;
when "0100" => return true;
when "0101" => return true;
when "0110" => return true;
when "0111" => return true;
when "1000" => return true;
when "1001" => return true;
when "1010" => return true;
when "1011" => return true;
when "1100" => return true;
when "1101" => return true;
when "1110" => return true;
when "1111" => return true;
when others => return false;
end case;
end verify_voltage;
end types;
package variables is
shared variable switchUpCnt : integer := 0;
shared variable switchDownCnt : integer := 0;
end variables;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 8bit input
entity EPROC_IN8 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN8;
architecture Behavioral of EPROC_IN8 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
EPROC_IN8_direct_inst: entity work.EPROC_IN8_direct
port map(
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN8_DEC8b10b_inst: entity work.EPROC_IN8_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 20:51:06 01/31/2010
-- Design Name: SPI
-- Module Name: tb_SPIFrqDiv
-- Description: VHDL Test Bench for module: SPIFrqDiv
--
-- Revision:
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_SPIFrqDiv is
end tb_SPIFrqDiv;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:57:31 07/13/2014
-- Design Name:
-- Module Name: counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
port(
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
d_out : out byte;
x : out std_logic -- boolean indicating if the tenth round is reached (d_out = 'A')
);
end counter;
architecture Behavioral of counter is
signal reg_D, reg_Q : byte;
begin
mux_3_1 : process(y, reg_Q)
begin
case y is
when "00" => reg_D <= (others => '0');
when "01" => reg_D <= reg_Q + 1;
when others => reg_D <= reg_Q;
end case;
end process mux_3_1;
reg : process (reset, clk, reg_D)
begin
if reset = '1' then
reg_Q <= (others => '0');
elsif rising_edge(clk) then
reg_Q <= reg_D;
end if;
end process reg;
comp : process (reg_Q)
begin
if reg_Q = x"0A" then
x <= '1';
else
x <= '0';
end if;
end process comp;
d_out <= reg_Q;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: dpr_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 8
-- C_READ_DEPTH_A : 8
-- C_ADDRA_WIDTH : 3
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 8
-- C_READ_DEPTH_B : 8
-- C_ADDRB_WIDTH : 3
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY dpr_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END dpr_prod;
ARCHITECTURE xilinx OF dpr_prod IS
COMPONENT dpr_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : dpr_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package adder_types is
subtype word is integer;
end package adder_types;
use work.adder_types.all;
-- end not in book
entity adder is
port ( a : in word;
b : in word;
sum : out word );
end entity adder;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package adder_types is
subtype word is integer;
end package adder_types;
use work.adder_types.all;
-- end not in book
entity adder is
port ( a : in word;
b : in word;
sum : out word );
end entity adder;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package adder_types is
subtype word is integer;
end package adder_types;
use work.adder_types.all;
-- end not in book
entity adder is
port ( a : in word;
b : in word;
sum : out word );
end entity adder;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 11:02:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-a.vhd,v 1.1 2007/03/03 11:17:34 wig Exp $
-- $Date: 2007/03/03 11:17:34 $
-- $Log: inst_t_e-rtl-a.vhd,v $
-- Revision 1.1 2007/03/03 11:17:34 wig
-- Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_t_e
--
architecture rtl of inst_t_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_a_e -- a instance
-- No Generated Generics
port (
-- Generated Port for Entity inst_a_e
p_mix_signal_aa_ba_go : out std_ulogic;
p_mix_signal_bb_ab_gi : in std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end component;
-- ---------
component inst_b_e -- Change parent to verilog
-- No Generated Generics
port (
-- Generated Port for Entity inst_b_e
p_mix_signal_aa_ba_gi : in std_ulogic;
p_mix_signal_bb_ab_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_b_e
);
end component;
-- ---------
--
-- Generated Signal List
--
signal signal_aa_ba : std_ulogic;
signal s_int_signal_bb_ab : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
signal_bb_ab <= s_int_signal_bb_ab; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a_i
inst_a_i: inst_a_e -- a instance
port map (
p_mix_signal_aa_ba_go => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_gi => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_a_i
-- Generated Instance Port Map for inst_b_i
inst_b_i: inst_b_e -- Change parent to verilog
port map (
p_mix_signal_aa_ba_gi => signal_aa_ba, -- signal test aa to ba
p_mix_signal_bb_ab_go => s_int_signal_bb_ab -- vector test bb to ab
);
-- End of Generated Instance Port Map for inst_b_i
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weight_hid_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weight_hid_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END weight_hid_exdes;
ARCHITECTURE xilinx OF weight_hid_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT weight_hid IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : weight_hid
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc670.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:58 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00670ent IS
END c03s04b01x00p23n01i00670ent;
ARCHITECTURE c03s04b01x00p23n01i00670arch OF c03s04b01x00p23n01i00670ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ('0', '1', 'X');
type FT is file of SWITCH_LEVEL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.48";
-- Declare a variable.
constant CON : SWITCH_LEVEL := '1';
variable VAR : SWITCH_LEVEL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00670 - The output file will tested by test file s010404.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00670arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc670.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:58 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00670ent IS
END c03s04b01x00p23n01i00670ent;
ARCHITECTURE c03s04b01x00p23n01i00670arch OF c03s04b01x00p23n01i00670ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ('0', '1', 'X');
type FT is file of SWITCH_LEVEL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.48";
-- Declare a variable.
constant CON : SWITCH_LEVEL := '1';
variable VAR : SWITCH_LEVEL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00670 - The output file will tested by test file s010404.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00670arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc670.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:58 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00670ent IS
END c03s04b01x00p23n01i00670ent;
ARCHITECTURE c03s04b01x00p23n01i00670arch OF c03s04b01x00p23n01i00670ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ('0', '1', 'X');
type FT is file of SWITCH_LEVEL;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.48";
-- Declare a variable.
constant CON : SWITCH_LEVEL := '1';
variable VAR : SWITCH_LEVEL := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00670 - The output file will tested by test file s010404.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00670arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: core_clock_mux
-- File: core_clock_mux.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: Clock muxes for LEONx ASIC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.clkmux;
use techmap.gencomp.has_clkmux;
entity core_clock_mux is
generic(
tech : integer;
scantest : integer range 0 to 1 := 0
);
port(
clksel : in std_logic_vector(1 downto 0);
testen : in std_logic;
clkin : in std_logic;
clk1x : in std_logic;
clk2x : in std_logic;
clk4x : in std_logic;
clkout : out std_ulogic
);
end entity;
architecture rtl of core_clock_mux is
signal sel1x,sel2x,sel4x : std_logic;
signal lclkm1o,lclkm2o : std_logic;
signal selbypass,seltest : std_logic;
begin
-- Select testclk or not
seltest <= '1' when (testen = '1' and scantest = 1) else '0';
-- Bypass PLL
selbypass <= '1' when (clksel = "00" or seltest = '1') else '0';
-- Select PLL clock if not test or bypassed
sel1x <= '1' when (clksel(1 downto 0) = "01" and selbypass = '0' and seltest = '0') else '0';
sel2x <= '1' when (clksel(1 downto 0) = "10" and selbypass = '0' and seltest = '0') else '0';
sel4x <= '1' when (clksel(1 downto 0) = "11" and selbypass = '0' and seltest = '0') else '0';
-- Select output clock from PLL (or bypass PLL)
lpllclkm1 : clkmux generic map (tech => tech) port map (clkin ,clk1x,sel1x,lclkm1o);
lpllclkm2 : clkmux generic map (tech => tech) port map (lclkm1o,clk2x,sel2x,lclkm2o);
lpllclkm4 : clkmux generic map (tech => tech) port map (lclkm2o,clk4x,sel4x,clkout );
end architecture;
|
-------------------------------------------------------------------------------
--
-- Title : dmem
-- Design : Mips
-- Author : Eduardo Sanchez
-- Company : Famaf
--
-------------------------------------------------------------------------------
--
-- File : dmem.vhd
--
-------------------------------------------------------------------------------
--
-- Description : Archivo con el diseño de la memoria RAM del procesador MIPS.
-- Para mantener un diseño corto, la memoria solo contiene 64 palabras de
-- 32 bits c/u (aunque podria direccionar mas memoria)
-- dump: si esta señal esta activa (1), se copia le contenido de la memoria
-- en el archivo de salida DUMP (para su posterior revision).
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_SIGNED.all;
use ieee.numeric_std.all;
--library WORK;
--use WORK.components.all;
entity dmem is -- data memory
port(clk, we: in STD_LOGIC;
a, wd: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0);
dump: in STD_LOGIC
);
end;
architecture behave of dmem is
constant MEMORY_DUMP_FILE: string := "output.dump";
constant MAX_BOUND: Integer := 64;
type ramtype is array (MAX_BOUND-1 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
signal mem: ramtype;
procedure memDump is
file dumpfile : text open write_mode is MEMORY_DUMP_FILE;
variable dumpline : line;
variable i: natural := 0;
begin
write(dumpline, string'("Memoria RAM de Mips:"));
writeline(dumpfile,dumpline);
write(dumpline, string'("Address Data"));
writeline(dumpfile,dumpline);
while i <= MAX_BOUND-1 loop
write(dumpline, i);
write(dumpline, string'(" "));
write(dumpline, conv_integer(mem(i)));
writeline(dumpfile,dumpline);
i:=i+1;
end loop;
end procedure memDump;
begin
process(clk, a, mem)
--edit
variable pos_a : integer;
begin
if clk'event and clk = '1' and we = '1' then
mem(to_integer(unsigned(a(7 downto 2)))) <= wd;
end if;
if a = x"00000000" then rd <= x"00000000";
else
pos_a := to_integer(unsigned(a(7 downto 2)));
rd <= mem(pos_a); -- word aligned
end if;
end process;
process(dump)
begin
if dump = '1' then
memDump;
end if;
end process;
end;
|
-------------------------------------------------------------------------------
--
-- Title : dmem
-- Design : Mips
-- Author : Eduardo Sanchez
-- Company : Famaf
--
-------------------------------------------------------------------------------
--
-- File : dmem.vhd
--
-------------------------------------------------------------------------------
--
-- Description : Archivo con el diseño de la memoria RAM del procesador MIPS.
-- Para mantener un diseño corto, la memoria solo contiene 64 palabras de
-- 32 bits c/u (aunque podria direccionar mas memoria)
-- dump: si esta señal esta activa (1), se copia le contenido de la memoria
-- en el archivo de salida DUMP (para su posterior revision).
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_SIGNED.all;
use ieee.numeric_std.all;
--library WORK;
--use WORK.components.all;
entity dmem is -- data memory
port(clk, we: in STD_LOGIC;
a, wd: in STD_LOGIC_VECTOR(31 downto 0);
rd: out STD_LOGIC_VECTOR(31 downto 0);
dump: in STD_LOGIC
);
end;
architecture behave of dmem is
constant MEMORY_DUMP_FILE: string := "output.dump";
constant MAX_BOUND: Integer := 64;
type ramtype is array (MAX_BOUND-1 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
signal mem: ramtype;
procedure memDump is
file dumpfile : text open write_mode is MEMORY_DUMP_FILE;
variable dumpline : line;
variable i: natural := 0;
begin
write(dumpline, string'("Memoria RAM de Mips:"));
writeline(dumpfile,dumpline);
write(dumpline, string'("Address Data"));
writeline(dumpfile,dumpline);
while i <= MAX_BOUND-1 loop
write(dumpline, i);
write(dumpline, string'(" "));
write(dumpline, conv_integer(mem(i)));
writeline(dumpfile,dumpline);
i:=i+1;
end loop;
end procedure memDump;
begin
process(clk, a, mem)
--edit
variable pos_a : integer;
begin
if clk'event and clk = '1' and we = '1' then
mem(to_integer(unsigned(a(7 downto 2)))) <= wd;
end if;
if a = x"00000000" then rd <= x"00000000";
else
pos_a := to_integer(unsigned(a(7 downto 2)));
rd <= mem(pos_a); -- word aligned
end if;
end process;
process(dump)
begin
if dump = '1' then
memDump;
end if;
end process;
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 28 11:48:21 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => Q(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 2) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(1 downto 0) => B"00",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => din(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 4),
DOBDO(3 downto 0) => dout(3 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
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INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => Q(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => \gc0.count_d1_reg[11]\(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 6) => B"00000000000000000000000000",
DIADI(5 downto 0) => din(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78\,
DOBDO(5 downto 0) => dout(5 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ram_full_fb_i_reg,
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => ram_full_fb_i_reg,
WEA(2) => ram_full_fb_i_reg,
WEA(1) => ram_full_fb_i_reg,
WEA(0) => ram_full_fb_i_reg,
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_comb : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0055000000FFC0C0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => wr_rst_busy,
I4 => \out\,
I5 => E(0),
O => ram_full_comb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg_0(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp0,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \gcc0.gc0.count_d1_reg[10]\,
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal carrynet_4 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => comp1,
CO(0) => carrynet_4,
CYINIT => '0',
DI(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"00",
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1 downto 0) => v1_reg(5 downto 4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^d\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
D(11 downto 0) <= \^d\(11 downto 0);
\gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(3),
O => \gc0.count[0]_i_2_n_0\
);
\gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(2),
O => \gc0.count[0]_i_3_n_0\
);
\gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(1),
O => \gc0.count[0]_i_4_n_0\
);
\gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^d\(0),
O => \gc0.count[0]_i_5_n_0\
);
\gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(7),
O => \gc0.count[4]_i_2_n_0\
);
\gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(6),
O => \gc0.count[4]_i_3_n_0\
);
\gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(5),
O => \gc0.count[4]_i_4_n_0\
);
\gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(4),
O => \gc0.count[4]_i_5_n_0\
);
\gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(11),
O => \gc0.count[8]_i_2_n_0\
);
\gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(10),
O => \gc0.count[8]_i_3_n_0\
);
\gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(9),
O => \gc0.count[8]_i_4_n_0\
);
\gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^d\(8),
O => \gc0.count[8]_i_5_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(0),
Q => Q(0)
);
\gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(10),
Q => Q(10)
);
\gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(11),
Q => Q(11)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(1),
Q => Q(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(2),
Q => Q(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(3),
Q => Q(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(4),
Q => Q(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(5),
Q => Q(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(6),
Q => Q(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(7),
Q => Q(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(8),
Q => Q(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \^d\(9),
Q => Q(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
D => \gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => \^d\(0)
);
\gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gc0.count_reg[0]_i_1_n_4\,
O(2) => \gc0.count_reg[0]_i_1_n_5\,
O(1) => \gc0.count_reg[0]_i_1_n_6\,
O(0) => \gc0.count_reg[0]_i_1_n_7\,
S(3) => \gc0.count[0]_i_2_n_0\,
S(2) => \gc0.count[0]_i_3_n_0\,
S(1) => \gc0.count[0]_i_4_n_0\,
S(0) => \gc0.count[0]_i_5_n_0\
);
\gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_5\,
Q => \^d\(10)
);
\gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_4\,
Q => \^d\(11)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_6\,
Q => \^d\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_5\,
Q => \^d\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[0]_i_1_n_4\,
Q => \^d\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_7\,
Q => \^d\(4)
);
\gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[4]_i_1_n_4\,
O(2) => \gc0.count_reg[4]_i_1_n_5\,
O(1) => \gc0.count_reg[4]_i_1_n_6\,
O(0) => \gc0.count_reg[4]_i_1_n_7\,
S(3) => \gc0.count[4]_i_2_n_0\,
S(2) => \gc0.count[4]_i_3_n_0\,
S(1) => \gc0.count[4]_i_4_n_0\,
S(0) => \gc0.count[4]_i_5_n_0\
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_6\,
Q => \^d\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_5\,
Q => \^d\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[4]_i_1_n_4\,
Q => \^d\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_7\,
Q => \^d\(8)
);
\gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gc0.count_reg[8]_i_1_n_4\,
O(2) => \gc0.count_reg[8]_i_1_n_5\,
O(1) => \gc0.count_reg[8]_i_1_n_6\,
O(0) => \gc0.count_reg[8]_i_1_n_7\,
S(3) => \gc0.count[8]_i_2_n_0\,
S(2) => \gc0.count[8]_i_3_n_0\,
S(1) => \gc0.count[8]_i_4_n_0\,
S(0) => \gc0.count[8]_i_5_n_0\
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_empty_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
D => \gc0.count_reg[8]_i_1_n_6\,
Q => \^d\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gcc0.gc0.count[0]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[0]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[4]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_2_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_3_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_4_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count[8]_i_5_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[0]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \gcc0.gc0.count_reg[8]_i_1_n_7\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
Q(11 downto 0) <= \^q\(11 downto 0);
\gcc0.gc0.count[0]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(3),
O => \gcc0.gc0.count[0]_i_2_n_0\
);
\gcc0.gc0.count[0]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(2),
O => \gcc0.gc0.count[0]_i_3_n_0\
);
\gcc0.gc0.count[0]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(1),
O => \gcc0.gc0.count[0]_i_4_n_0\
);
\gcc0.gc0.count[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(7),
O => \gcc0.gc0.count[4]_i_2_n_0\
);
\gcc0.gc0.count[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(6),
O => \gcc0.gc0.count[4]_i_3_n_0\
);
\gcc0.gc0.count[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(5),
O => \gcc0.gc0.count[4]_i_4_n_0\
);
\gcc0.gc0.count[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(4),
O => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(11),
O => \gcc0.gc0.count[8]_i_2_n_0\
);
\gcc0.gc0.count[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(10),
O => \gcc0.gc0.count[8]_i_3_n_0\
);
\gcc0.gc0.count[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(9),
O => \gcc0.gc0.count[8]_i_4_n_0\
);
\gcc0.gc0.count[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => p_12_out(8),
O => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(0),
Q => \^q\(0)
);
\gcc0.gc0.count_d1_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(10),
Q => \^q\(10)
);
\gcc0.gc0.count_d1_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(11),
Q => \^q\(11)
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(1),
Q => \^q\(1)
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(2),
Q => \^q\(2)
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(3),
Q => \^q\(3)
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(4),
Q => \^q\(4)
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(5),
Q => \^q\(5)
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(6),
Q => \^q\(6)
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(7),
Q => \^q\(7)
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(8),
Q => \^q\(8)
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => p_12_out(9),
Q => \^q\(9)
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
D => \gcc0.gc0.count_reg[0]_i_1_n_7\,
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => p_12_out(0)
);
\gcc0.gc0.count_reg[0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[0]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[0]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \gcc0.gc0.count_reg[0]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[0]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[0]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[0]_i_1_n_7\,
S(3) => \gcc0.gc0.count[0]_i_2_n_0\,
S(2) => \gcc0.gc0.count[0]_i_3_n_0\,
S(1) => \gcc0.gc0.count[0]_i_4_n_0\,
S(0) => \gcc0.gc0.count[0]_i_5_n_0\
);
\gcc0.gc0.count_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_5\,
Q => p_12_out(10)
);
\gcc0.gc0.count_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_4\,
Q => p_12_out(11)
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_6\,
Q => p_12_out(1)
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_5\,
Q => p_12_out(2)
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[0]_i_1_n_4\,
Q => p_12_out(3)
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_7\,
Q => p_12_out(4)
);
\gcc0.gc0.count_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[0]_i_1_n_0\,
CO(3) => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(2) => \gcc0.gc0.count_reg[4]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[4]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[4]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[4]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[4]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[4]_i_1_n_7\,
S(3) => \gcc0.gc0.count[4]_i_2_n_0\,
S(2) => \gcc0.gc0.count[4]_i_3_n_0\,
S(1) => \gcc0.gc0.count[4]_i_4_n_0\,
S(0) => \gcc0.gc0.count[4]_i_5_n_0\
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_6\,
Q => p_12_out(5)
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_5\,
Q => p_12_out(6)
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[4]_i_1_n_4\,
Q => p_12_out(7)
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_7\,
Q => p_12_out(8)
);
\gcc0.gc0.count_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gcc0.gc0.count_reg[4]_i_1_n_0\,
CO(3) => \NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gcc0.gc0.count_reg[8]_i_1_n_1\,
CO(1) => \gcc0.gc0.count_reg[8]_i_1_n_2\,
CO(0) => \gcc0.gc0.count_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \gcc0.gc0.count_reg[8]_i_1_n_4\,
O(2) => \gcc0.gc0.count_reg[8]_i_1_n_5\,
O(1) => \gcc0.gc0.count_reg[8]_i_1_n_6\,
O(0) => \gcc0.gc0.count_reg[8]_i_1_n_7\,
S(3) => \gcc0.gc0.count[8]_i_2_n_0\,
S(2) => \gcc0.gc0.count[8]_i_3_n_0\,
S(1) => \gcc0.gc0.count[8]_i_4_n_0\,
S(0) => \gcc0.gc0.count[8]_i_5_n_0\
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => ram_full_fb_i_reg,
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \gcc0.gc0.count_reg[8]_i_1_n_6\,
Q => p_12_out(9)
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => D(0),
I2 => \^q\(1),
I3 => D(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[11]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[11]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => D(2),
I2 => \^q\(3),
I3 => D(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[11]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[11]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => D(4),
I2 => \^q\(5),
I3 => D(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[11]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[11]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => D(6),
I2 => \^q\(7),
I3 => D(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[11]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[11]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => D(8),
I2 => \^q\(9),
I3 => D(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[11]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[11]\(9),
O => ram_empty_i_reg_3
);
\gmux.gm[5].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_0(5)
);
\gmux.gm[5].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => D(10),
I2 => \^q\(11),
I3 => D(11),
O => v1_reg(5)
);
\gmux.gm[5].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => p_12_out(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => v1_reg_1(5)
);
\gmux.gm[5].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(10),
I1 => \gc0.count_d1_reg[11]\(10),
I2 => \^q\(11),
I3 => \gc0.count_d1_reg[11]\(11),
O => ram_empty_i_reg_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
port (
dout : out STD_LOGIC_VECTOR ( 8 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(8 downto 0),
dout(8 downto 0) => dout(8 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(5 downto 0),
dout(5 downto 0) => dout(5 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
\gc0.count_d1_reg[11]\ : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
v1_reg(5 downto 0) => v1_reg(5 downto 0)
);
\gc0.count_d1[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => \gc0.count_d1_reg[11]\
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[0]\(1) <= rd_rst_reg(2);
\gc0.count_reg[0]\(0) <= rd_rst_reg(0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(0) <= wr_rst_reg(1);
wr_rst_busy <= rst_d3;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
clk => clk,
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
clk => clk,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
clk => clk,
in0(0) => rd_rst_asreg,
\out\ => p_7_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
clk => clk,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss is
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_comb : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => \gcc0.gc0.count_d1_reg[11]\
);
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
E(0) => E(0),
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_full_comb => ram_full_comb,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp1 => comp1,
v1_reg_0(5 downto 0) => v1_reg_0(5 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '1',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(3 downto 0) => din(3 downto 0),
dout(3 downto 0) => dout(3 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(12 downto 4),
dout(8 downto 0) => dout(12 downto 4),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(21 downto 13),
dout(8 downto 0) => dout(21 downto 13),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(30 downto 22),
dout(8 downto 0) => dout(30 downto 22),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[4].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(39 downto 31),
dout(8 downto 0) => dout(39 downto 31),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[5].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(48 downto 40),
dout(8 downto 0) => dout(48 downto 40),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[6].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(8 downto 0) => din(57 downto 49),
dout(8 downto 0) => dout(57 downto 49),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[7].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(5 downto 0) => din(63 downto 58),
dout(5 downto 0) => dout(63 downto 58),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[10]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\grss.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
port map (
clk => clk,
empty => empty,
\gc0.count_d1_reg[11]\ => \^e\(0),
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[10]\ => \gcc0.gc0.count_d1_reg[10]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
wr_en => wr_en
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
ram_empty_fb_i_reg => \^e\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[11]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
ram_empty_i_reg_4 : out STD_LOGIC;
clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC;
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
wr_rst_busy : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gcc0.gc0.count_d1_reg[11]\ : STD_LOGIC;
begin
\gcc0.gc0.count_d1_reg[11]\ <= \^gcc0.gc0.count_d1_reg[11]\;
\gwss.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
port map (
E(0) => E(0),
clk => clk,
full => full,
\gcc0.gc0.count_d1_reg[11]\ => \^gcc0.gc0.count_d1_reg[11]\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \grstd1.grst_full.grst_f.rst_d2_reg\,
\out\ => \out\,
v1_reg(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_0(5 downto 0) => \c1/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
D(11 downto 0) => D(11 downto 0),
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
ram_empty_i_reg_4 => ram_empty_i_reg_4,
ram_full_fb_i_reg => \^gcc0.gc0.count_d1_reg[11]\,
v1_reg(5 downto 0) => v1_reg(5 downto 0),
v1_reg_0(5 downto 0) => \c0/v1_reg\(5 downto 0),
v1_reg_1(5 downto 0) => \c1/v1_reg\(5 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gc0.count_d1_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
Q(11 downto 0) => Q(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => \gc0.count_d1_reg[11]\(11 downto 0),
\out\(0) => \out\(0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.rd_n_14\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_23\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_24\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_25\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_26\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal \^wr_rst_busy\ : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 to 1 );
begin
wr_rst_busy <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_0_out(11 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[10]\ => \gntv_or_sync_fifo.gl0.wr_n_26\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_23\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_24\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_25\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => rd_rst_i(2),
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
D(11 downto 0) => rd_pntr_plus1(11 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_14\,
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
full => full,
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\gcc0.gc0.count_d1_reg[11]\ => \gntv_or_sync_fifo.gl0.wr_n_2\,
\grstd1.grst_full.grst_f.rst_d2_reg\ => rst_full_ff_i,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => wr_rst_i(1),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_22\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_23\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_24\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_25\,
ram_empty_i_reg_4 => \gntv_or_sync_fifo.gl0.wr_n_26\,
v1_reg(5 downto 0) => \grss.rsts/c2/v1_reg\(5 downto 0),
wr_en => wr_en,
wr_rst_busy => \^wr_rst_busy\
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
Q(11 downto 0) => p_11_out(11 downto 0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[11]\(11 downto 0) => p_0_out(11 downto 0),
\out\(0) => rd_rst_i(0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_2\,
tmp_ram_rd_en => tmp_ram_rd_en
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
clk => clk,
\gc0.count_reg[0]\(1) => rd_rst_i(2),
\gc0.count_reg[0]\(0) => rd_rst_i(0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(0) => wr_rst_i(1),
ram_empty_fb_i_reg => p_2_out,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_rst_busy => \^wr_rst_busy\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
wr_rst_busy : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 11 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 11 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(11) <= \<const0>\;
data_count(10) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(11) <= \<const0>\;
rd_data_count(10) <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(11) <= \<const0>\;
wr_data_count(10) <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "4kx9";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 4094;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 4093;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 4096;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 12;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 12;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 4096;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 12;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(11 downto 0) => NLW_U0_data_count_UNCONNECTED(11 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(11 downto 0) => B"000000000000",
prog_empty_thresh_assert(11 downto 0) => B"000000000000",
prog_empty_thresh_negate(11 downto 0) => B"000000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(11 downto 0) => B"000000000000",
prog_full_thresh_assert(11 downto 0) => B"000000000000",
prog_full_thresh_negate(11 downto 0) => B"000000000000",
rd_clk => '0',
rd_data_count(11 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(11 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(11 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(11 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6704)
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`protect end_protected
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:53 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[1:0][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[3:2][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[5:4][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[23:22][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[25:24][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[27:26][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[29:28][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:30][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[7:6][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[9:8][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[11:10][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[13:12][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:14][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[17:16][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[19:18][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
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DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[21:20][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[10].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(21 downto 20),
dinb(1 downto 0) => dinb(21 downto 20),
douta(1 downto 0) => douta(21 downto 20),
doutb(1 downto 0) => doutb(21 downto 20),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[11].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(23 downto 22),
dinb(1 downto 0) => dinb(23 downto 22),
douta(1 downto 0) => douta(23 downto 22),
doutb(1 downto 0) => doutb(23 downto 22),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[12].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(25 downto 24),
dinb(1 downto 0) => dinb(25 downto 24),
douta(1 downto 0) => douta(25 downto 24),
doutb(1 downto 0) => doutb(25 downto 24),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[13].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(27 downto 26),
dinb(1 downto 0) => dinb(27 downto 26),
douta(1 downto 0) => douta(27 downto 26),
doutb(1 downto 0) => doutb(27 downto 26),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[14].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(29 downto 28),
dinb(1 downto 0) => dinb(29 downto 28),
douta(1 downto 0) => douta(29 downto 28),
doutb(1 downto 0) => doutb(29 downto 28),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[15].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(31 downto 30),
dinb(1 downto 0) => dinb(31 downto 30),
douta(1 downto 0) => douta(31 downto 30),
doutb(1 downto 0) => doutb(31 downto 30),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(3 downto 2),
dinb(1 downto 0) => dinb(3 downto 2),
douta(1 downto 0) => douta(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(5 downto 4),
dinb(1 downto 0) => dinb(5 downto 4),
douta(1 downto 0) => douta(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(7 downto 6),
dinb(1 downto 0) => dinb(7 downto 6),
douta(1 downto 0) => douta(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(9 downto 8),
dinb(1 downto 0) => dinb(9 downto 8),
douta(1 downto 0) => douta(9 downto 8),
doutb(1 downto 0) => doutb(9 downto 8),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[5].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(11 downto 10),
dinb(1 downto 0) => dinb(11 downto 10),
douta(1 downto 0) => douta(11 downto 10),
doutb(1 downto 0) => doutb(11 downto 10),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[6].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(13 downto 12),
dinb(1 downto 0) => dinb(13 downto 12),
douta(1 downto 0) => douta(13 downto 12),
doutb(1 downto 0) => doutb(13 downto 12),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[7].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(15 downto 14),
dinb(1 downto 0) => dinb(15 downto 14),
douta(1 downto 0) => douta(15 downto 14),
doutb(1 downto 0) => doutb(15 downto 14),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[8].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(17 downto 16),
dinb(1 downto 0) => dinb(17 downto 16),
douta(1 downto 0) => douta(17 downto 16),
doutb(1 downto 0) => doutb(17 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[9].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(19 downto 18),
dinb(1 downto 0) => dinb(19 downto 18),
douta(1 downto 0) => douta(19 downto 18),
doutb(1 downto 0) => doutb(19 downto 18),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
port map (
addra(13 downto 0) => addra(15 downto 2),
addrb(13 downto 0) => addrb(15 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlbcam
-- File: mmutlbcam.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlbcam is
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end mmutlbcam;
architecture rtl of mmutlbcam is
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
type tlbcam_rtype is record
btag : tlbcam_reg;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : tlbcam_rtype := (btag => tlbcam_reg_none);
signal r,c : tlbcam_rtype;
begin
p0: process (rst, r, tlbcami)
variable v : tlbcam_rtype;
variable hm, hf : std_logic;
variable h_i1, h_i2, h_i3, h_c : std_logic;
variable h_l2, h_l3 : std_logic;
variable h_su_cnt : std_logic;
variable blvl : std_logic_vector(1 downto 0);
variable bet : std_logic_vector(1 downto 0);
variable bsu : std_logic;
variable blvl_decode : std_logic_vector(3 downto 0);
variable bet_decode : std_logic_vector(3 downto 0);
variable ref, modified : std_logic;
variable tlbcamo_pteout : std_logic_vector(31 downto 0);
variable tlbcamo_LVL : std_logic_vector(1 downto 0);
variable tlbcamo_NEEDSYNC : std_logic;
variable tlbcamo_WBNEEDSYNC : std_logic;
variable vaddr_r : std_logic_vector(31 downto 12);
variable vaddr_i : std_logic_vector(31 downto 12);
variable pagesize : integer range 0 to 3;
begin
v := r;
--#init
h_i1 := '0'; h_i2 := '0'; h_i3 := '0'; h_c := '0';
hm := '0'; pagesize := 0;
hf := r.btag.VALID;
blvl := r.btag.LVL;
bet := r.btag.ET;
bsu := r.btag.SU;
bet_decode := decode(bet);
blvl_decode := decode(blvl);
ref := r.btag.R;
modified := r.btag.M;
tlbcamo_pteout := (others => '0');
tlbcamo_lvl := (others => '0');
vaddr_r := r.btag.I1 & r.btag.I2 & r.btag.I3;
vaddr_i := tlbcami.tagin.I1 & tlbcami.tagin.I2 & tlbcami.tagin.I3;
-- prepare tag comparision
pagesize := MMU_getpagesize(mmupgsz,tlbcami.mmctrl);
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
if (vaddr_r(P8K_VA_I1_U downto P8K_VA_I1_D) = vaddr_i(P8K_VA_I1_U downto P8K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P8K_VA_I2_U downto P8K_VA_I2_D) = vaddr_i(P8K_VA_I2_U downto P8K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P8K_VA_I3_U downto P8K_VA_I3_D) = vaddr_i(P8K_VA_I3_U downto P8K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
if (vaddr_r(P16K_VA_I1_U downto P16K_VA_I1_D) = vaddr_i(P16K_VA_I1_U downto P16K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P16K_VA_I2_U downto P16K_VA_I2_D) = vaddr_i(P16K_VA_I2_U downto P16K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P16K_VA_I3_U downto P16K_VA_I3_D) = vaddr_i(P16K_VA_I3_U downto P16K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
if (vaddr_r(P32K_VA_I1_U downto P32K_VA_I1_D) = vaddr_i(P32K_VA_I1_U downto P32K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P32K_VA_I2_U downto P32K_VA_I2_D) = vaddr_i(P32K_VA_I2_U downto P32K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P32K_VA_I3_U downto P32K_VA_I3_D) = vaddr_i(P32K_VA_I3_U downto P32K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when others => -- standard 4k tag comparision [ 8 6 6 ]
if (r.btag.I1 = tlbcami.tagin.I1) then h_i1 := '1'; else h_i1 := '0'; end if;
if (r.btag.I2 = tlbcami.tagin.I2) then h_i2 := '1'; else h_i2 := '0'; end if;
if (r.btag.I3 = tlbcami.tagin.I3) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
end case;
-- #level 2 hit (segment)
h_l2 := h_i1 and h_i2 ;
-- #level 3 hit (page)
h_l3 := h_i1 and h_i2 and h_i3;
-- # context + su
h_su_cnt := h_c or bsu;
--# translation (match) op
case blvl is
when LVL_PAGE => hm := h_l3 and h_c and r.btag.VALID;
when LVL_SEGMENT => hm := h_l2 and h_c and r.btag.VALID;
when LVL_REGION => hm := h_i1 and h_c and r.btag.VALID;
when LVL_CTX => hm := h_c and r.btag.VALID;
when others => hm := 'X';
end case;
--# translation: update ref/mod bit
tlbcamo_NEEDSYNC := '0';
if (tlbcami.trans_op and hm ) = '1' then
v.btag.R := '1';
v.btag.M := r.btag.M or tlbcami.tagin.M;
tlbcamo_NEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
tlbcamo_WBNEEDSYNC := '0';
if ( hm ) = '1' then
tlbcamo_WBNEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
--# flush operation
-- tlbcam only stores PTEs, tlb does not store PTDs
case tlbcami.tagin.TYP is
when FPTY_PAGE => -- page
hf := hf and h_su_cnt and h_l3 and (blvl_decode(0)); -- only level 3 (page)
when FPTY_SEGMENT => -- segment
hf := hf and h_su_cnt and h_l2 and (blvl_decode(0) or blvl_decode(1)); -- only level 2+3 (segment,page)
when FPTY_REGION => -- region
hf := hf and h_su_cnt and h_i1 and (not blvl_decode(3)); -- only level 1+2+3 (region,segment,page)
when FPTY_CTX => -- context
hf := hf and (h_c and (not bsu));
when FPTY_N => -- entire
when others =>
hf := '0';
end case;
--# flush: invalidate on flush hit
--if (tlbcami.flush_op and hf ) = '1' then
if (tlbcami.flush_op ) = '1' then
v.btag.VALID := '0';
end if;
--# write op
if ( tlbcami.write_op = '1' ) then
v.btag := tlbcami.tagwrite;
end if;
--# reset
if ((not RESET_ALL) and (rst = '0')) or (tlbcami.mmuen = '0') then
v.btag.VALID := RRES.btag.VALID;
end if;
tlbcamo_pteout(PTE_PPN_U downto PTE_PPN_D) := r.btag.PPN;
tlbcamo_pteout(PTE_C) := r.btag.C;
tlbcamo_pteout(PTE_M) := r.btag.M;
tlbcamo_pteout(PTE_R) := r.btag.R;
tlbcamo_pteout(PTE_ACC_U downto PTE_ACC_D) := r.btag.ACC;
tlbcamo_pteout(PT_ET_U downto PT_ET_D) := r.btag.ET;
tlbcamo_LVL(1 downto 0) := r.btag.LVL;
--# drive signals
tlbcamo.pteout <= tlbcamo_pteout;
tlbcamo.LVL <= tlbcamo_LVL;
--tlbcamo.hit <= (tlbcami.trans_op and hm) or (tlbcami.flush_op and hf);
tlbcamo.hit <= (hm) or (tlbcami.flush_op and hf);
tlbcamo.ctx <= r.btag.CTX; -- for diagnostic only
tlbcamo.valid <= r.btag.VALID; -- for diagnostic only
tlbcamo.vaddr <= r.btag.I1 & r.btag.I2 & r.btag.I3 & "000000000000"; -- for diagnostic only
tlbcamo.NEEDSYNC <= tlbcamo_NEEDSYNC;
tlbcamo.WBNEEDSYNC <= tlbcamo_WBNEEDSYNC;
c <= v;
end process p0;
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end rtl;
|
------------------------------------------------------
-- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM --
-- --
-- Packages for HY5PS121621F.vhd --
-- --
-- HHHH HHHH --
-- HHHH HHHH --
-- ,O0O. ,O0 .HH ,O0 .HH --
-- (O000O)(000 )H(000 )H Hynix --
-- `O0O' `O0 'HH `O0 'HH --
-- HHHH HHHH Semiconductor --
-- HHHH HHHH --
------------------------------------------------------
---------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.stdlib.all;
--USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.STD_LOGIC_UNSIGNED.all;
---------------------------------------------------------------------------------------------------
package HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
constant NUM_OF_MROPCODE : integer := 13;
constant NUM_OF_ROW_ADD : integer := 13;
constant NUM_OF_COL_ADD : integer := 10;
constant NUM_OF_BANK_ADD : integer := 2;
constant WORD_SIZE : integer := 16;
constant NUM_OF_ROWS : integer := 2**NUM_OF_ROW_ADD;
constant NUM_OF_COLS : integer := 2**NUM_OF_COL_ADD;
constant NUM_OF_BANKS : integer := 2**NUM_OF_BANK_ADD;
constant NUM_OF_BUFFERS : integer := 3;
type PART_NUM_TYPE is (B400, B533, B667, B800);
type PART_NUM is array (B400 to B800) of time;
constant tCKmin : PART_NUM := (B400 => 5 ns, B533 => 3.75 ns, B667 => 3 ns, B800 => 2.5 ns);
constant tCKmax : PART_NUM := (B400 => 8 ns, B533 => 8 ns, B667 => 8 ns, B800 => 8 ns);
constant tWR : PART_NUM := (B400 => 15 ns, B533 => 15 ns, B667 => 15 ns, B800 => 15 ns);
constant tDS : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tDH : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tIS : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tIH : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tWTR : PART_NUM := (B400 => 10 ns, B533 => 7.5 ns, B667 => 7.5 ns, B800 => 7.5 ns);
constant tRASmax : PART_NUM := (B400 => 70000 ns, B533 => 70000 ns, B667 => 70000 ns, B800 => 70000 ns);
constant tRRD : time := 10 ns;
constant tREF : time := 64 ms;
constant tRFC : time := 75 ns;
constant tRTP : time := 7.5 ns;
constant tXSNR : time := tRFC + 10 ns;
constant tXP : integer := 2;
constant tCKE : integer := 3;
constant tXARD : integer := 2;
constant tXARDS : integer := 2;
constant tXSRD : integer := 200;
constant tPUS : time := 200 us;
type STATE_TYPE is (
PWRDN,
PWRUP,
SLFREF,
IDLE,
RACT,
READ,
WRITE);
type COMMAND_TYPE is (
DSEL,
NOP,
MRS,
EMRS1,
EMRS2,
EMRS3,
ACT,
RD,
RDAP,
WR,
WRAP,
PCG,
PCGA,
AREF,
SREF,
SREX,
PDEN,
PDEX,
ERROR,
ILLEGAL);
type BURST_MODE_TYPE is (
SEQUENTIAL,
INTERLEAVE);
type OCD_DRIVE_MODE_TYPE is (
CAL_EXIT,
DRIVE1,
DRIVE0,
ADJUST,
CAL_DEFAULT);
subtype CL_TYPE is integer range 0 to 6;
subtype BL_TYPE is integer range 4 to 8;
subtype TWR_TYPE is integer range 2 to 6;
type DLL_RST is (
RST,
NORST);
type MODE_REGISTER is
record
CAS_LATENCY : CL_TYPE;
BURST_MODE : BURST_MODE_TYPE;
BURST_LENGTH : BL_TYPE;
DLL_STATE : DLL_RST;
SAPD : std_logic;
TWR : TWR_TYPE;
end record;
type EMR_TYPE is
record
DLL_EN : std_logic;
AL : CL_TYPE;
QOFF : std_logic;
DQSB_ENB : std_logic;
RDQS_EN : std_logic;
OCD_PGM : OCD_DRIVE_MODE_TYPE;
end record;
type EMR2_TYPE is
record
SREF_HOT : std_logic;
end record;
type REF_CHECK is array (0 to (NUM_OF_BANKS - 1), 0 to (NUM_OF_ROWS - 1)) of time;
type COL_ADDR_TYPE is array (0 to 3) of std_logic_vector((NUM_OF_COL_ADD - 1) downto 0);
type DATA_BUFFER_TYPE is array (0 to 6) of std_logic_vector(8 downto 0);
subtype COL_DATA_TYPE is integer range 0 to 65535;
type SA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type ROW_DATA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type RAM_PNTR is ACCESS ROW_DATA_TYPE;
type SA_ARRAY_TYPE is array (0 to (NUM_OF_BANKS - 1)) of SA_TYPE;
type MEM_CELL_TYPE is array (0 to (NUM_OF_ROWS - 1)) of RAM_PNTR;
subtype DATA_TYPE is std_logic_vector ((WORD_SIZE - 1) downto 0);
type BUFFER_TYPE is array (0 to NUM_OF_BUFFERS - 1, 0 to 3) of DATA_TYPE;
type ADD_PIPE_TYPE is array (0 to 12) of std_logic_vector((NUM_OF_COL_ADD + NUM_OF_BANK_ADD - 1) downto 0);
type CKE_TYPE is array (integer range -1 to 0) of std_logic;
subtype MROPCODE_TYPE is std_logic_vector ((NUM_OF_MROPCODE - 1) downto 0);
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE);
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER);
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE);
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE);
function REMAINDER (
val0 : in integer;
val1 : in integer) return integer;
function XOR_FUNC (
val0 : in std_logic_vector;
val1 : in std_logic_vector) return std_logic_vector;
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic;
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT;
end HY5PS121621F_PACK; ------------------------------------------------------HY5DU121622T Package
---------------------------------------------------------------------------------------------------
package body HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE) Is
begin
case CKE (-1) is
when '1' =>
case CKE (0) is
when '0' =>
if (BankState = "0000") then
if (CSB = '0' and RASB = '0' and CASB = '0' and WEB = '1') then
COMMAND := SREF;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
when '1' =>
if (CSB = '1') then
COMMAND := DSEL;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
COMMAND := NOP;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') then
if (A10 = '0') then
COMMAND := RD;
else
COMMAND := RDAP;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') then
if (A10 = '0') then
COMMAND := WR;
else
COMMAND := WRAP;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then
COMMAND := ACT;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') then
if (A10 = '0') then
COMMAND := PCG;
else
COMMAND := PCGA;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then
COMMAND := AREF;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then
if (BankState = "0000") then
if (Bank_Add = "00") then
COMMAND := MRS;
elsif (Bank_Add = "01") then
COMMAND := EMRS1;
elsif (Bank_Add = "10") then
COMMAND := EMRS2;
elsif (Bank_Add = "11") then
COMMAND := EMRS3;
end if;
else
COMMAND := ILLEGAL;
end if;
end if;
when others =>
COMMAND := ERROR;
end case;
when '0' =>
case CKE (0) is
when '0' =>
COMMAND := NOP;
when '1' =>
if (State = PWRUP) then
COMMAND := NOP;
elsif (CSB = '1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
else
COMMAND := ERROR;
end if;
when others =>
COMMAND := ERROR;
end case;
when others =>
COMMAND := ERROR;
end case;
end COMMAND_DECODE;
------------------------------------------------------------------------------------------------
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER) is
begin
if (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 2;
elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 3;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 4;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 5;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Cas_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(3) = '0' then
MR.BURST_MODE := SEQUENTIAL;
elsif MROPCODE(3) = '1' then
MR.BURST_MODE := INTERLEAVE;
end if;
if MROPCODE(8) = '0' then
MR.DLL_STATE := NORST;
elsif MROPCODE(8) = '1' then
MR.DLL_STATE := RST;
end if;
if MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '0' then
MR.BURST_LENGTH := 4;
elsif MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '1' then
MR.BURST_LENGTH := 8;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Burst_Length Encountered!"
severity ERROR;
end if;
if MROPCODE(12) = '0' then
MR.SAPD := '0';
elsif MROPCODE(12) = '1' then
MR.SAPD := '1';
end if;
if MROPCODE(11) = '0' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 2;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '0' then
MR.TWR := 3;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '1' then
MR.TWR := 4;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '0' then
MR.TWR := 5;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Write Recovery Value Encountered!"
severity ERROR;
end if;
end MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE) is
begin
if (MROPCODE(0) = '0') then
EMR.DLL_EN := '1';
elsif (MROPCODE(0) = '1') then
EMR.DLL_EN := '0';
end if;
if (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 0;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 1;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '0')then
EMR.AL := 2;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '1')then
EMR.AL := 3;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 4;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 5;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid Additive_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(12) = '0' then
EMR.QOFF := '0';
elsif MROPCODE(12) = '1' then
EMR.QOFF := '1';
end if;
if MROPCODE(10) = '0' then
EMR.DQSB_ENB := '0';
elsif MROPCODE(10) = '1' then
EMR.DQSB_ENB := '1';
end if;
if MROPCODE(11) = '0' then
EMR.RDQS_EN := '0';
elsif MROPCODE(11) = '1' then
EMR.RDQS_EN := '1';
end if;
if MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := CAL_EXIT;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '1' then
EMR.OCD_PGM := DRIVE1;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '1' and MROPCODE(7) = '0' then
EMR.OCD_PGM := DRIVE0;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := ADJUST;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '1' and MROPCODE(7) = '1' then
EMR.OCD_PGM := CAL_DEFAULT;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid OCD Calibration Program Encountered!"
severity ERROR;
end if;
end EXT_MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE) is
begin
if (MROPCODE(7) = '0') then
EMR.SREF_HOT := '0';
elsif (MROPCODE(7) = '1') then
EMR.SREF_HOT := '1';
end if;
end EXT_MODE_REGISTER_SET2;
------------------------------------------------------------------------------------------------
function REMAINDER (val0 : in integer; val1 : in integer) return integer is
variable Result : integer;
begin
Result := val0;
loop
exit when Result < val1;
Result := Result - val1;
end loop;
return Result;
end REMAINDER;
------------------------------------------------------------------------------------------------
function XOR_FUNC (val0 : in std_logic_vector; val1 : in std_logic_vector) return std_logic_vector is
variable Result : std_logic_vector(2 downto 0);
variable j : integer := 0;
begin
for i in val0'RANGE LOOP
if (val0(i) /= val1(i)) then
Result(i) := '1';
else
Result(i) := '0';
end if;
j := j + 1;
end loop;
return Result((j - 1) downto 0);
end XOR_FUNC;
------------------------------------------------------------------------------------------------
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic is
variable r : std_logic;
begin
case c is
when '0' => r := '0';
when 'L' => r := 'L';
when '1' => r := '1';
when 'H' => r := 'H';
when 'W' => r := 'W';
when 'Z' => r := 'Z';
when 'U' => r := 'U';
when '-' => r := '-';
when others => r := 'X';
end case;
return r;
end CHAR_TO_STD_LOGIC;
------------------------------------------------------------------------------------------------
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT is
variable Result: BIT;
begin
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' | 'W' | 'Z' | 'U' | '-' =>
Result := '0';
end case;
return Result;
end STD_LOGIC_TO_BIT;
------------------------------------------------------------------------------------------------
end HY5PS121621F_PACK;
|
------------------------------------------------------
-- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM --
-- --
-- Packages for HY5PS121621F.vhd --
-- --
-- HHHH HHHH --
-- HHHH HHHH --
-- ,O0O. ,O0 .HH ,O0 .HH --
-- (O000O)(000 )H(000 )H Hynix --
-- `O0O' `O0 'HH `O0 'HH --
-- HHHH HHHH Semiconductor --
-- HHHH HHHH --
------------------------------------------------------
---------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.stdlib.all;
--USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.STD_LOGIC_UNSIGNED.all;
---------------------------------------------------------------------------------------------------
package HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
constant NUM_OF_MROPCODE : integer := 13;
constant NUM_OF_ROW_ADD : integer := 13;
constant NUM_OF_COL_ADD : integer := 10;
constant NUM_OF_BANK_ADD : integer := 2;
constant WORD_SIZE : integer := 16;
constant NUM_OF_ROWS : integer := 2**NUM_OF_ROW_ADD;
constant NUM_OF_COLS : integer := 2**NUM_OF_COL_ADD;
constant NUM_OF_BANKS : integer := 2**NUM_OF_BANK_ADD;
constant NUM_OF_BUFFERS : integer := 3;
type PART_NUM_TYPE is (B400, B533, B667, B800);
type PART_NUM is array (B400 to B800) of time;
constant tCKmin : PART_NUM := (B400 => 5 ns, B533 => 3.75 ns, B667 => 3 ns, B800 => 2.5 ns);
constant tCKmax : PART_NUM := (B400 => 8 ns, B533 => 8 ns, B667 => 8 ns, B800 => 8 ns);
constant tWR : PART_NUM := (B400 => 15 ns, B533 => 15 ns, B667 => 15 ns, B800 => 15 ns);
constant tDS : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tDH : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tIS : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tIH : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tWTR : PART_NUM := (B400 => 10 ns, B533 => 7.5 ns, B667 => 7.5 ns, B800 => 7.5 ns);
constant tRASmax : PART_NUM := (B400 => 70000 ns, B533 => 70000 ns, B667 => 70000 ns, B800 => 70000 ns);
constant tRRD : time := 10 ns;
constant tREF : time := 64 ms;
constant tRFC : time := 75 ns;
constant tRTP : time := 7.5 ns;
constant tXSNR : time := tRFC + 10 ns;
constant tXP : integer := 2;
constant tCKE : integer := 3;
constant tXARD : integer := 2;
constant tXARDS : integer := 2;
constant tXSRD : integer := 200;
constant tPUS : time := 200 us;
type STATE_TYPE is (
PWRDN,
PWRUP,
SLFREF,
IDLE,
RACT,
READ,
WRITE);
type COMMAND_TYPE is (
DSEL,
NOP,
MRS,
EMRS1,
EMRS2,
EMRS3,
ACT,
RD,
RDAP,
WR,
WRAP,
PCG,
PCGA,
AREF,
SREF,
SREX,
PDEN,
PDEX,
ERROR,
ILLEGAL);
type BURST_MODE_TYPE is (
SEQUENTIAL,
INTERLEAVE);
type OCD_DRIVE_MODE_TYPE is (
CAL_EXIT,
DRIVE1,
DRIVE0,
ADJUST,
CAL_DEFAULT);
subtype CL_TYPE is integer range 0 to 6;
subtype BL_TYPE is integer range 4 to 8;
subtype TWR_TYPE is integer range 2 to 6;
type DLL_RST is (
RST,
NORST);
type MODE_REGISTER is
record
CAS_LATENCY : CL_TYPE;
BURST_MODE : BURST_MODE_TYPE;
BURST_LENGTH : BL_TYPE;
DLL_STATE : DLL_RST;
SAPD : std_logic;
TWR : TWR_TYPE;
end record;
type EMR_TYPE is
record
DLL_EN : std_logic;
AL : CL_TYPE;
QOFF : std_logic;
DQSB_ENB : std_logic;
RDQS_EN : std_logic;
OCD_PGM : OCD_DRIVE_MODE_TYPE;
end record;
type EMR2_TYPE is
record
SREF_HOT : std_logic;
end record;
type REF_CHECK is array (0 to (NUM_OF_BANKS - 1), 0 to (NUM_OF_ROWS - 1)) of time;
type COL_ADDR_TYPE is array (0 to 3) of std_logic_vector((NUM_OF_COL_ADD - 1) downto 0);
type DATA_BUFFER_TYPE is array (0 to 6) of std_logic_vector(8 downto 0);
subtype COL_DATA_TYPE is integer range 0 to 65535;
type SA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type ROW_DATA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type RAM_PNTR is ACCESS ROW_DATA_TYPE;
type SA_ARRAY_TYPE is array (0 to (NUM_OF_BANKS - 1)) of SA_TYPE;
type MEM_CELL_TYPE is array (0 to (NUM_OF_ROWS - 1)) of RAM_PNTR;
subtype DATA_TYPE is std_logic_vector ((WORD_SIZE - 1) downto 0);
type BUFFER_TYPE is array (0 to NUM_OF_BUFFERS - 1, 0 to 3) of DATA_TYPE;
type ADD_PIPE_TYPE is array (0 to 12) of std_logic_vector((NUM_OF_COL_ADD + NUM_OF_BANK_ADD - 1) downto 0);
type CKE_TYPE is array (integer range -1 to 0) of std_logic;
subtype MROPCODE_TYPE is std_logic_vector ((NUM_OF_MROPCODE - 1) downto 0);
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE);
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER);
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE);
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE);
function REMAINDER (
val0 : in integer;
val1 : in integer) return integer;
function XOR_FUNC (
val0 : in std_logic_vector;
val1 : in std_logic_vector) return std_logic_vector;
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic;
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT;
end HY5PS121621F_PACK; ------------------------------------------------------HY5DU121622T Package
---------------------------------------------------------------------------------------------------
package body HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE) Is
begin
case CKE (-1) is
when '1' =>
case CKE (0) is
when '0' =>
if (BankState = "0000") then
if (CSB = '0' and RASB = '0' and CASB = '0' and WEB = '1') then
COMMAND := SREF;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
when '1' =>
if (CSB = '1') then
COMMAND := DSEL;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
COMMAND := NOP;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') then
if (A10 = '0') then
COMMAND := RD;
else
COMMAND := RDAP;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') then
if (A10 = '0') then
COMMAND := WR;
else
COMMAND := WRAP;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then
COMMAND := ACT;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') then
if (A10 = '0') then
COMMAND := PCG;
else
COMMAND := PCGA;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then
COMMAND := AREF;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then
if (BankState = "0000") then
if (Bank_Add = "00") then
COMMAND := MRS;
elsif (Bank_Add = "01") then
COMMAND := EMRS1;
elsif (Bank_Add = "10") then
COMMAND := EMRS2;
elsif (Bank_Add = "11") then
COMMAND := EMRS3;
end if;
else
COMMAND := ILLEGAL;
end if;
end if;
when others =>
COMMAND := ERROR;
end case;
when '0' =>
case CKE (0) is
when '0' =>
COMMAND := NOP;
when '1' =>
if (State = PWRUP) then
COMMAND := NOP;
elsif (CSB = '1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
else
COMMAND := ERROR;
end if;
when others =>
COMMAND := ERROR;
end case;
when others =>
COMMAND := ERROR;
end case;
end COMMAND_DECODE;
------------------------------------------------------------------------------------------------
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER) is
begin
if (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 2;
elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 3;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 4;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 5;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Cas_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(3) = '0' then
MR.BURST_MODE := SEQUENTIAL;
elsif MROPCODE(3) = '1' then
MR.BURST_MODE := INTERLEAVE;
end if;
if MROPCODE(8) = '0' then
MR.DLL_STATE := NORST;
elsif MROPCODE(8) = '1' then
MR.DLL_STATE := RST;
end if;
if MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '0' then
MR.BURST_LENGTH := 4;
elsif MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '1' then
MR.BURST_LENGTH := 8;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Burst_Length Encountered!"
severity ERROR;
end if;
if MROPCODE(12) = '0' then
MR.SAPD := '0';
elsif MROPCODE(12) = '1' then
MR.SAPD := '1';
end if;
if MROPCODE(11) = '0' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 2;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '0' then
MR.TWR := 3;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '1' then
MR.TWR := 4;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '0' then
MR.TWR := 5;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Write Recovery Value Encountered!"
severity ERROR;
end if;
end MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE) is
begin
if (MROPCODE(0) = '0') then
EMR.DLL_EN := '1';
elsif (MROPCODE(0) = '1') then
EMR.DLL_EN := '0';
end if;
if (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 0;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 1;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '0')then
EMR.AL := 2;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '1')then
EMR.AL := 3;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 4;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 5;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid Additive_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(12) = '0' then
EMR.QOFF := '0';
elsif MROPCODE(12) = '1' then
EMR.QOFF := '1';
end if;
if MROPCODE(10) = '0' then
EMR.DQSB_ENB := '0';
elsif MROPCODE(10) = '1' then
EMR.DQSB_ENB := '1';
end if;
if MROPCODE(11) = '0' then
EMR.RDQS_EN := '0';
elsif MROPCODE(11) = '1' then
EMR.RDQS_EN := '1';
end if;
if MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := CAL_EXIT;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '1' then
EMR.OCD_PGM := DRIVE1;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '1' and MROPCODE(7) = '0' then
EMR.OCD_PGM := DRIVE0;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := ADJUST;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '1' and MROPCODE(7) = '1' then
EMR.OCD_PGM := CAL_DEFAULT;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid OCD Calibration Program Encountered!"
severity ERROR;
end if;
end EXT_MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE) is
begin
if (MROPCODE(7) = '0') then
EMR.SREF_HOT := '0';
elsif (MROPCODE(7) = '1') then
EMR.SREF_HOT := '1';
end if;
end EXT_MODE_REGISTER_SET2;
------------------------------------------------------------------------------------------------
function REMAINDER (val0 : in integer; val1 : in integer) return integer is
variable Result : integer;
begin
Result := val0;
loop
exit when Result < val1;
Result := Result - val1;
end loop;
return Result;
end REMAINDER;
------------------------------------------------------------------------------------------------
function XOR_FUNC (val0 : in std_logic_vector; val1 : in std_logic_vector) return std_logic_vector is
variable Result : std_logic_vector(2 downto 0);
variable j : integer := 0;
begin
for i in val0'RANGE LOOP
if (val0(i) /= val1(i)) then
Result(i) := '1';
else
Result(i) := '0';
end if;
j := j + 1;
end loop;
return Result((j - 1) downto 0);
end XOR_FUNC;
------------------------------------------------------------------------------------------------
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic is
variable r : std_logic;
begin
case c is
when '0' => r := '0';
when 'L' => r := 'L';
when '1' => r := '1';
when 'H' => r := 'H';
when 'W' => r := 'W';
when 'Z' => r := 'Z';
when 'U' => r := 'U';
when '-' => r := '-';
when others => r := 'X';
end case;
return r;
end CHAR_TO_STD_LOGIC;
------------------------------------------------------------------------------------------------
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT is
variable Result: BIT;
begin
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' | 'W' | 'Z' | 'U' | '-' =>
Result := '0';
end case;
return Result;
end STD_LOGIC_TO_BIT;
------------------------------------------------------------------------------------------------
end HY5PS121621F_PACK;
|
------------------------------------------------------
-- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM --
-- --
-- Packages for HY5PS121621F.vhd --
-- --
-- HHHH HHHH --
-- HHHH HHHH --
-- ,O0O. ,O0 .HH ,O0 .HH --
-- (O000O)(000 )H(000 )H Hynix --
-- `O0O' `O0 'HH `O0 'HH --
-- HHHH HHHH Semiconductor --
-- HHHH HHHH --
------------------------------------------------------
---------------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
library grlib;
use grlib.stdlib.all;
--USE IEEE.STD_LOGIC_ARITH.all;
--USE IEEE.STD_LOGIC_UNSIGNED.all;
---------------------------------------------------------------------------------------------------
package HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
constant NUM_OF_MROPCODE : integer := 13;
constant NUM_OF_ROW_ADD : integer := 13;
constant NUM_OF_COL_ADD : integer := 10;
constant NUM_OF_BANK_ADD : integer := 2;
constant WORD_SIZE : integer := 16;
constant NUM_OF_ROWS : integer := 2**NUM_OF_ROW_ADD;
constant NUM_OF_COLS : integer := 2**NUM_OF_COL_ADD;
constant NUM_OF_BANKS : integer := 2**NUM_OF_BANK_ADD;
constant NUM_OF_BUFFERS : integer := 3;
type PART_NUM_TYPE is (B400, B533, B667, B800);
type PART_NUM is array (B400 to B800) of time;
constant tCKmin : PART_NUM := (B400 => 5 ns, B533 => 3.75 ns, B667 => 3 ns, B800 => 2.5 ns);
constant tCKmax : PART_NUM := (B400 => 8 ns, B533 => 8 ns, B667 => 8 ns, B800 => 8 ns);
constant tWR : PART_NUM := (B400 => 15 ns, B533 => 15 ns, B667 => 15 ns, B800 => 15 ns);
constant tDS : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tDH : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns);
constant tIS : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tIH : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns);
constant tWTR : PART_NUM := (B400 => 10 ns, B533 => 7.5 ns, B667 => 7.5 ns, B800 => 7.5 ns);
constant tRASmax : PART_NUM := (B400 => 70000 ns, B533 => 70000 ns, B667 => 70000 ns, B800 => 70000 ns);
constant tRRD : time := 10 ns;
constant tREF : time := 64 ms;
constant tRFC : time := 75 ns;
constant tRTP : time := 7.5 ns;
constant tXSNR : time := tRFC + 10 ns;
constant tXP : integer := 2;
constant tCKE : integer := 3;
constant tXARD : integer := 2;
constant tXARDS : integer := 2;
constant tXSRD : integer := 200;
constant tPUS : time := 200 us;
type STATE_TYPE is (
PWRDN,
PWRUP,
SLFREF,
IDLE,
RACT,
READ,
WRITE);
type COMMAND_TYPE is (
DSEL,
NOP,
MRS,
EMRS1,
EMRS2,
EMRS3,
ACT,
RD,
RDAP,
WR,
WRAP,
PCG,
PCGA,
AREF,
SREF,
SREX,
PDEN,
PDEX,
ERROR,
ILLEGAL);
type BURST_MODE_TYPE is (
SEQUENTIAL,
INTERLEAVE);
type OCD_DRIVE_MODE_TYPE is (
CAL_EXIT,
DRIVE1,
DRIVE0,
ADJUST,
CAL_DEFAULT);
subtype CL_TYPE is integer range 0 to 6;
subtype BL_TYPE is integer range 4 to 8;
subtype TWR_TYPE is integer range 2 to 6;
type DLL_RST is (
RST,
NORST);
type MODE_REGISTER is
record
CAS_LATENCY : CL_TYPE;
BURST_MODE : BURST_MODE_TYPE;
BURST_LENGTH : BL_TYPE;
DLL_STATE : DLL_RST;
SAPD : std_logic;
TWR : TWR_TYPE;
end record;
type EMR_TYPE is
record
DLL_EN : std_logic;
AL : CL_TYPE;
QOFF : std_logic;
DQSB_ENB : std_logic;
RDQS_EN : std_logic;
OCD_PGM : OCD_DRIVE_MODE_TYPE;
end record;
type EMR2_TYPE is
record
SREF_HOT : std_logic;
end record;
type REF_CHECK is array (0 to (NUM_OF_BANKS - 1), 0 to (NUM_OF_ROWS - 1)) of time;
type COL_ADDR_TYPE is array (0 to 3) of std_logic_vector((NUM_OF_COL_ADD - 1) downto 0);
type DATA_BUFFER_TYPE is array (0 to 6) of std_logic_vector(8 downto 0);
subtype COL_DATA_TYPE is integer range 0 to 65535;
type SA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type ROW_DATA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE;
type RAM_PNTR is ACCESS ROW_DATA_TYPE;
type SA_ARRAY_TYPE is array (0 to (NUM_OF_BANKS - 1)) of SA_TYPE;
type MEM_CELL_TYPE is array (0 to (NUM_OF_ROWS - 1)) of RAM_PNTR;
subtype DATA_TYPE is std_logic_vector ((WORD_SIZE - 1) downto 0);
type BUFFER_TYPE is array (0 to NUM_OF_BUFFERS - 1, 0 to 3) of DATA_TYPE;
type ADD_PIPE_TYPE is array (0 to 12) of std_logic_vector((NUM_OF_COL_ADD + NUM_OF_BANK_ADD - 1) downto 0);
type CKE_TYPE is array (integer range -1 to 0) of std_logic;
subtype MROPCODE_TYPE is std_logic_vector ((NUM_OF_MROPCODE - 1) downto 0);
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE);
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER);
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE);
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE);
function REMAINDER (
val0 : in integer;
val1 : in integer) return integer;
function XOR_FUNC (
val0 : in std_logic_vector;
val1 : in std_logic_vector) return std_logic_vector;
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic;
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT;
end HY5PS121621F_PACK; ------------------------------------------------------HY5DU121622T Package
---------------------------------------------------------------------------------------------------
package body HY5PS121621F_PACK is
---------------------------------------------------------------------------------------------------
procedure COMMAND_DECODE (
variable
CSB,
RASB,
CASB,
WEB,
A10 : in std_logic;
variable
Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0);
variable
CKE : in CKE_TYPE;
variable
COMMAND : out COMMAND_TYPE;
variable
BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0);
variable
State : in STATE_TYPE) Is
begin
case CKE (-1) is
when '1' =>
case CKE (0) is
when '0' =>
if (BankState = "0000") then
if (CSB = '0' and RASB = '0' and CASB = '0' and WEB = '1') then
COMMAND := SREF;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then
COMMAND := PDEN;
else
COMMAND := ILLEGAL;
end if;
when '1' =>
if (CSB = '1') then
COMMAND := DSEL;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
COMMAND := NOP;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') then
if (A10 = '0') then
COMMAND := RD;
else
COMMAND := RDAP;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') then
if (A10 = '0') then
COMMAND := WR;
else
COMMAND := WRAP;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then
COMMAND := ACT;
elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') then
if (A10 = '0') then
COMMAND := PCG;
else
COMMAND := PCGA;
end if;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then
COMMAND := AREF;
elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then
if (BankState = "0000") then
if (Bank_Add = "00") then
COMMAND := MRS;
elsif (Bank_Add = "01") then
COMMAND := EMRS1;
elsif (Bank_Add = "10") then
COMMAND := EMRS2;
elsif (Bank_Add = "11") then
COMMAND := EMRS3;
end if;
else
COMMAND := ILLEGAL;
end if;
end if;
when others =>
COMMAND := ERROR;
end case;
when '0' =>
case CKE (0) is
when '0' =>
COMMAND := NOP;
when '1' =>
if (State = PWRUP) then
COMMAND := NOP;
elsif (CSB = '1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then
if (State = SLFREF) then
COMMAND := SREX;
elsif (State = PWRDN) then
COMMAND := PDEX;
end if;
else
COMMAND := ERROR;
end if;
when others =>
COMMAND := ERROR;
end case;
when others =>
COMMAND := ERROR;
end case;
end COMMAND_DECODE;
------------------------------------------------------------------------------------------------
procedure MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
MR : out MODE_REGISTER) is
begin
if (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 2;
elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 3;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 4;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '1')then
MR.CAS_LATENCY := 5;
elsif (MROPCODE(6) = '1' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then
MR.CAS_LATENCY := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Cas_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(3) = '0' then
MR.BURST_MODE := SEQUENTIAL;
elsif MROPCODE(3) = '1' then
MR.BURST_MODE := INTERLEAVE;
end if;
if MROPCODE(8) = '0' then
MR.DLL_STATE := NORST;
elsif MROPCODE(8) = '1' then
MR.DLL_STATE := RST;
end if;
if MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '0' then
MR.BURST_LENGTH := 4;
elsif MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '1' then
MR.BURST_LENGTH := 8;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Burst_Length Encountered!"
severity ERROR;
end if;
if MROPCODE(12) = '0' then
MR.SAPD := '0';
elsif MROPCODE(12) = '1' then
MR.SAPD := '1';
end if;
if MROPCODE(11) = '0' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 2;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '0' then
MR.TWR := 3;
elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '1' then
MR.TWR := 4;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '0' then
MR.TWR := 5;
elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then
MR.TWR := 6;
else
assert false report
"ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Write Recovery Value Encountered!"
severity ERROR;
end if;
end MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR_TYPE) is
begin
if (MROPCODE(0) = '0') then
EMR.DLL_EN := '1';
elsif (MROPCODE(0) = '1') then
EMR.DLL_EN := '0';
end if;
if (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 0;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 1;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '0')then
EMR.AL := 2;
elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '1')then
EMR.AL := 3;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then
EMR.AL := 4;
elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then
EMR.AL := 5;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid Additive_Latency Encountered!"
severity WARNING;
end if;
if MROPCODE(12) = '0' then
EMR.QOFF := '0';
elsif MROPCODE(12) = '1' then
EMR.QOFF := '1';
end if;
if MROPCODE(10) = '0' then
EMR.DQSB_ENB := '0';
elsif MROPCODE(10) = '1' then
EMR.DQSB_ENB := '1';
end if;
if MROPCODE(11) = '0' then
EMR.RDQS_EN := '0';
elsif MROPCODE(11) = '1' then
EMR.RDQS_EN := '1';
end if;
if MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := CAL_EXIT;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '1' then
EMR.OCD_PGM := DRIVE1;
elsif MROPCODE(9) = '0' and MROPCODE(8) = '1' and MROPCODE(7) = '0' then
EMR.OCD_PGM := DRIVE0;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then
EMR.OCD_PGM := ADJUST;
elsif MROPCODE(9) = '1' and MROPCODE(8) = '1' and MROPCODE(7) = '1' then
EMR.OCD_PGM := CAL_DEFAULT;
else
assert false report
"ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid OCD Calibration Program Encountered!"
severity ERROR;
end if;
end EXT_MODE_REGISTER_SET;
------------------------------------------------------------------------------------------------
procedure EXT_MODE_REGISTER_SET2 (
MROPCODE : in MROPCODE_TYPE;
EMR : out EMR2_TYPE) is
begin
if (MROPCODE(7) = '0') then
EMR.SREF_HOT := '0';
elsif (MROPCODE(7) = '1') then
EMR.SREF_HOT := '1';
end if;
end EXT_MODE_REGISTER_SET2;
------------------------------------------------------------------------------------------------
function REMAINDER (val0 : in integer; val1 : in integer) return integer is
variable Result : integer;
begin
Result := val0;
loop
exit when Result < val1;
Result := Result - val1;
end loop;
return Result;
end REMAINDER;
------------------------------------------------------------------------------------------------
function XOR_FUNC (val0 : in std_logic_vector; val1 : in std_logic_vector) return std_logic_vector is
variable Result : std_logic_vector(2 downto 0);
variable j : integer := 0;
begin
for i in val0'RANGE LOOP
if (val0(i) /= val1(i)) then
Result(i) := '1';
else
Result(i) := '0';
end if;
j := j + 1;
end loop;
return Result((j - 1) downto 0);
end XOR_FUNC;
------------------------------------------------------------------------------------------------
function CHAR_TO_STD_LOGIC (
c : in character)
return std_logic is
variable r : std_logic;
begin
case c is
when '0' => r := '0';
when 'L' => r := 'L';
when '1' => r := '1';
when 'H' => r := 'H';
when 'W' => r := 'W';
when 'Z' => r := 'Z';
when 'U' => r := 'U';
when '-' => r := '-';
when others => r := 'X';
end case;
return r;
end CHAR_TO_STD_LOGIC;
------------------------------------------------------------------------------------------------
function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT is
variable Result: BIT;
begin
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' | 'W' | 'Z' | 'U' | '-' =>
Result := '0';
end case;
return Result;
end STD_LOGIC_TO_BIT;
------------------------------------------------------------------------------------------------
end HY5PS121621F_PACK;
|
-- NEED RESULT: ARCH00563: Aliasing - composite static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00563
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.4 (1)
-- 4.3.4 (2)
-- 4.3.4 (12)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00563)
-- ENT00563_Test_Bench(ARCH00563_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00563 of E00000 is
constant co_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
constant co_st_string_1 : st_string
:= c_st_string_1 ;
constant co_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
constant co_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
constant co_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
constant co_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
signal si_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
signal si_st_string_1 : st_string
:= c_st_string_1 ;
signal si_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
signal si_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
signal si_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
signal si_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
alias as_st_bit_vector_1 : st_bit_vector
is si_st_bit_vector_1 ;
alias as_st_string_1 : st_string
is si_st_string_1 ;
alias as_st_rec1_1 : st_rec1
is si_st_rec1_1 ;
alias as_st_rec2_1 : st_rec2
is si_st_rec2_1 ;
alias as_st_rec3_1 : st_rec3
is si_st_rec3_1 ;
alias as_st_arr1_1 : st_arr1
is si_st_arr1_1 ;
type test is (initial, intermediate, final) ;
signal synch : test := initial ;
signal s_correct1 : boolean ;
signal s_correct2 : boolean ;
begin
process
variable correct : boolean := true ;
begin
if synch = initial then
correct := correct and as_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and as_st_string_1 = c_st_string_1 ;
correct := correct and as_st_rec1_1 = c_st_rec1_1 ;
correct := correct and as_st_rec2_1 = c_st_rec2_1 ;
correct := correct and as_st_rec3_1 = c_st_rec3_1 ;
correct := correct and as_st_arr1_1 = c_st_arr1_1 ;
si_st_bit_vector_1 <= c_st_bit_vector_2 ;
si_st_string_1 <= c_st_string_2 ;
si_st_rec1_1 <= c_st_rec1_2 ;
si_st_rec2_1 <= c_st_rec2_2 ;
si_st_rec3_1 <= c_st_rec3_2 ;
si_st_arr1_1 <= c_st_arr1_2 ;
synch <= intermediate ;
as_st_bit_vector_1 <= transport c_st_bit_vector_1 after 1 ns ;
as_st_string_1 <= transport c_st_string_1 after 1 ns ;
as_st_rec1_1 <= transport c_st_rec1_1 after 1 ns ;
as_st_rec2_1 <= transport c_st_rec2_1 after 1 ns ;
as_st_rec3_1 <= transport c_st_rec3_1 after 1 ns ;
as_st_arr1_1 <= transport c_st_arr1_1 after 1 ns ;
synch <= transport final after 1 ns ;
s_correct1 <= correct ;
end if ;
wait ;
end process ;
process (synch)
procedure p1 is
variable correct : boolean ;
variable va_st_bit_vector_1 : st_bit_vector
:= c_st_bit_vector_1 ;
variable va_st_string_1 : st_string
:= c_st_string_1 ;
variable va_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
variable va_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
variable va_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
variable va_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
alias ac_st_bit_vector_1 : st_bit_vector
is co_st_bit_vector_1 ;
alias ac_st_string_1 : st_string
is co_st_string_1 ;
alias ac_st_rec1_1 : st_rec1
is co_st_rec1_1 ;
alias ac_st_rec2_1 : st_rec2
is co_st_rec2_1 ;
alias ac_st_rec3_1 : st_rec3
is co_st_rec3_1 ;
alias ac_st_arr1_1 : st_arr1
is co_st_arr1_1 ;
alias av_st_bit_vector_1 : st_bit_vector
is va_st_bit_vector_1 ;
alias av_st_string_1 : st_string
is va_st_string_1 ;
alias av_st_rec1_1 : st_rec1
is va_st_rec1_1 ;
alias av_st_rec2_1 : st_rec2
is va_st_rec2_1 ;
alias av_st_rec3_1 : st_rec3
is va_st_rec3_1 ;
alias av_st_arr1_1 : st_arr1
is va_st_arr1_1 ;
begin
correct := s_correct1 ;
if synch = intermediate then
-- test that variables denote same object
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and av_st_string_1 = c_st_string_1 ;
correct := correct and av_st_rec1_1 = c_st_rec1_1 ;
correct := correct and av_st_rec2_1 = c_st_rec2_1 ;
correct := correct and av_st_rec3_1 = c_st_rec3_1 ;
correct := correct and av_st_arr1_1 = c_st_arr1_1 ;
va_st_bit_vector_1 := c_st_bit_vector_2 ;
va_st_string_1 := c_st_string_2 ;
va_st_rec1_1 := c_st_rec1_2 ;
va_st_rec2_1 := c_st_rec2_2 ;
va_st_rec3_1 := c_st_rec3_2 ;
va_st_arr1_1 := c_st_arr1_2 ;
correct := correct and av_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and av_st_string_1 = c_st_string_2 ;
correct := correct and av_st_rec1_1 = c_st_rec1_2 ;
correct := correct and av_st_rec2_1 = c_st_rec2_2 ;
correct := correct and av_st_rec3_1 = c_st_rec3_2 ;
correct := correct and av_st_arr1_1 = c_st_arr1_2 ;
av_st_bit_vector_1 := c_st_bit_vector_1 ;
av_st_string_1 := c_st_string_1 ;
av_st_rec1_1 := c_st_rec1_1 ;
av_st_rec2_1 := c_st_rec2_1 ;
av_st_rec3_1 := c_st_rec3_1 ;
av_st_arr1_1 := c_st_arr1_1 ;
correct := correct and va_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and va_st_string_1 = c_st_string_1 ;
correct := correct and va_st_rec1_1 = c_st_rec1_1 ;
correct := correct and va_st_rec2_1 = c_st_rec2_1 ;
correct := correct and va_st_rec3_1 = c_st_rec3_1 ;
correct := correct and va_st_arr1_1 = c_st_arr1_1 ;
-- test that signals denote same object
correct := correct and as_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and as_st_string_1 = c_st_string_2 ;
correct := correct and as_st_rec1_1 = c_st_rec1_2 ;
correct := correct and as_st_rec2_1 = c_st_rec2_2 ;
correct := correct and as_st_rec3_1 = c_st_rec3_2 ;
correct := correct and as_st_arr1_1 = c_st_arr1_2 ;
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_2 ;
correct := correct and si_st_string_1 = c_st_string_2 ;
correct := correct and si_st_rec1_1 = c_st_rec1_2 ;
correct := correct and si_st_rec2_1 = c_st_rec2_2 ;
correct := correct and si_st_rec3_1 = c_st_rec3_2 ;
correct := correct and si_st_arr1_1 = c_st_arr1_2 ;
-- test that constants denote same object
correct := correct and ac_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and ac_st_string_1 = c_st_string_1 ;
correct := correct and ac_st_rec1_1 = c_st_rec1_1 ;
correct := correct and ac_st_rec2_1 = c_st_rec2_1 ;
correct := correct and ac_st_rec3_1 = c_st_rec3_1 ;
correct := correct and ac_st_arr1_1 = c_st_arr1_1 ;
s_correct2 <= correct ;
end if ;
end p1 ;
begin
p1 ;
end process ;
--
process (synch)
variable correct : boolean ;
begin
if synch = final then
correct := s_correct2 ;
correct := correct and si_st_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and si_st_string_1 = c_st_string_1 ;
correct := correct and si_st_rec1_1 = c_st_rec1_1 ;
correct := correct and si_st_rec2_1 = c_st_rec2_1 ;
correct := correct and si_st_rec3_1 = c_st_rec3_1 ;
correct := correct and si_st_arr1_1 = c_st_arr1_1 ;
test_report ( "ARCH00563" ,
"Aliasing - composite static subtypes" ,
correct) ;
end if ;
end process ;
end ARCH00563 ;
--
entity ENT00563_Test_Bench is
end ENT00563_Test_Bench ;
--
architecture ARCH00563_Test_Bench of ENT00563_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00563 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00563_Test_Bench ;
|
-----------------------------------------------------------------------
-- UART transmitter block. It sends the data to the GPS at the baud rate
-- defined. The data are sent following the Skytraq binary protocol.
-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gps_pkg.all;
entity gps_transmitter is
port(
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
start_flag : in std_logic;
done : out std_logic;
done_send : out std_logic;
count_bd : in unsigned(15 downto 0);
count_max : in unsigned(15 downto 0);
rst_count_bd : out std_logic;
TXD : out std_logic;
bytes : in unsigned(7 downto 0);
data_in : in std_logic_vector(7 downto 0)
);
end GPS_transmitter;
architecture RTL of gps_transmitter is
signal number_of_bits : unsigned(3 downto 0);
signal data_out_s : std_logic_vector(7 downto 0);
signal gngga : std_logic_vector(55 downto 0);
signal g_flag : std_logic;
signal data_to_send : std_logic_vector(7 downto 0);
signal count_bytes : unsigned(7 downto 0);
signal count_wait : unsigned(15 downto 0);
signal TXD_r : std_logic;
type type_state is (idle, start, data, wait_st, stop);
signal state : type_state;
begin
process(clk,reset,enable)
begin
if reset='0' then
rst_count_bd <='0';
number_of_bits <= x"0";
TXD_r <= '1';
state <= idle;
elsif clk'event and clk='1'then
if enable='1' then
case(state) is
----- Starting a communication
when(idle) =>
done <= '0';
done_send <= '0';
TXD_r <= '1';
if start_flag='1' then
state <= start;
data_to_send <= data_in;
rst_count_bd <= '1';
end if;
----- Writing start bit
when(start) =>
rst_count_bd <= '0';
data_to_send <= data_in;
done <= '0';
TXD_r <= '0';
if count_bd=count_max then
state <= data;
number_of_bits <= x"0";
end if;
----- Writing the 8 bits of data (LSB first)
when(data) =>
TXD_r <= data_to_send(0);
if count_bd=count_max then
data_to_send <= '0' & data_to_send(7 downto 1);
if number_of_bits= x"7" then
state <= stop;
else
number_of_bits <= number_of_bits +1;
end if;
end if;
----- Write stop bit
when(stop) =>
TXD_r <= '1';
if count_bd=count_max then
done <= '1';
number_of_bits <= x"0";
count_bytes <= count_bytes +1;
if count_bytes=bytes-1 then
if count_max=COUNT_BD_RATE_MAX then
count_wait <= x"0000";
else
count_wait <= x"7000";
end if;
state <= wait_st;
else
state <= start;
end if;
end if;
----- Full sequence sended, waiting before sending a new one
when wait_st =>
TXD_r <= '1';
if count_bd=count_max then
count_wait <= count_wait +1;
elsif count_wait=x"FFFF" then
state <= idle;
count_bytes <= x"00";
done_send <= '1';
end if;
when others =>
TXD_r <= '1';
state <= idle;
end case;
else
rst_count_bd <='0';
number_of_bits <= x"0";
TXD_r <= '1';
state <= idle;
end if;
end if;
end process;
TXD <= TXD_r;
end RTL;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:31:20 11/17/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282/My_Adder_tb_948282.vhd
-- Project Name: Mips32_948282
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_Adder_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_Adder_tb_948282 IS
END My_Adder_tb_948282;
ARCHITECTURE behavior OF My_Adder_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_Adder_948282
PORT(
A_element : IN std_logic;
B_element : IN std_logic;
CarryIn : IN std_logic;
CarryOut : OUT std_logic;
Result : OUT std_logic
);
END COMPONENT;
--Inputs
signal A_element : std_logic := '0';
signal B_element : std_logic := '0';
signal CarryIn : std_logic := '0';
--Outputs
signal CarryOut : std_logic;
signal Result : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_Adder_948282 PORT MAP (
A_element => A_element,
B_element => B_element,
CarryIn => CarryIn,
CarryOut => CarryOut,
Result => Result
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
A_element<='1';
B_element<='0';
CarryIn<='0';
wait for 100 ns;
A_element<='1';
B_element<='1';
CarryIn<='1';
wait for 100 ns;
wait;
end process;
END;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - ramp.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Ramp filter / envelope
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity ramp is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
incr2 : in signed(31 downto 0);
rmp : out signed(31 downto 0)
);
end ramp;
architecture Behavioral of ramp is
type states is (s_increasing, s_decreasing, s_exit);
signal state : states;
signal s_one : signed (31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal s_zero : signed (31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
begin
rmp <= x;
CALC_RAMP : process (clk, x, incr, rst)
begin
if rst = '1' then
x <= to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
state <= s_increasing;
else
if rising_edge(clk) then
if ce = '1' then
case state is
when s_increasing =>
x <= x + incr;
if x > s_one then
state <= s_decreasing;
end if;
when s_decreasing =>
x <= x - incr2;
if x < s_zero then
state <= s_exit;
end if;
when s_exit =>
--
end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atactrl
-- File: atactrl.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ata.all;
use gaisler.misc.all; --2007-1-16
use gaisler.ata_inf.all;
library opencores;
use opencores.occomp.all;
entity atactrl_dma is
generic (
tech : integer := 0;
fdepth : integer := 8;
mhindex : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
cfo : out cf_out_type;
-- ATA signals
ddin : in std_logic_vector(15 downto 0);
iordy : in std_logic;
intrq : in std_logic;
ata_resetn : out std_logic;
ddout : out std_logic_vector(15 downto 0);
ddoe : out std_logic;
da : out std_logic_vector(2 downto 0);
cs0n : out std_logic;
cs1n : out std_logic;
diorn : out std_logic;
diown : out std_logic;
dmack : out std_logic;
dmarq : in std_logic
);
end;
architecture rtl of atactrl_dma is
-- Device ID
constant DeviceId : integer := 2;
constant RevisionNo : integer := 0;
constant VERSION : integer := 0;
component atahost_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
-- DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
-- DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
-- DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0);
-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
fr_BM : in bm_to_slv_type;
to_BM : out slv_to_bm_type
-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
);
end component atahost_amba_slave;
component atahost_ahbmst is
generic(fdepth : integer := 8);
Port(clk : in std_logic;
rst : in std_logic;
i : in bmi_type;
o : out bmo_type
);
end component atahost_ahbmst;
-- asynchronous reset signal
signal arst_signal : std_logic;
-- primary address decoder
-- signal PIOsel,s_bmen : std_logic; -- controller select, IDE devices select
signal PIOsel : std_logic; -- controller select, IDE devices select
-- control signal
signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic;
-- compatible mode timing
signal s_PIO_cmdport_T1, s_PIO_cmdport_T2, s_PIO_cmdport_T4, s_PIO_cmdport_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_cmdport_IORDYen : std_logic;
-- data port0 timing
signal s_PIO_dport0_T1, s_PIO_dport0_T2, s_PIO_dport0_T4, s_PIO_dport0_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport0_IORDYen : std_logic;
-- data port1 timing
signal s_PIO_dport1_T1, s_PIO_dport1_T2, s_PIO_dport1_T4, s_PIO_dport1_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport1_IORDYen : std_logic;
signal PIOack : std_logic;
signal PIOq : std_logic_vector(15 downto 0);
signal PIOa : std_logic_vector(3 downto 0):="0000";
signal PIOd : std_logic_vector(15 downto 0) := X"0000";
signal PIOwe : std_logic;
signal irq : std_logic; -- ATA bus IRQ signal
signal reset : std_logic;
signal gnd,vcc : std_logic;
signal gnd32 : std_logic_vector(31 downto 0);
--**********************SIGNAL DECLARATION*****by Erik Jagre 2006-10-04*******
signal s_PIOtip : std_logic:='0'; -- PIO transfer in progress
signal s_PIOpp_full : std_logic:='0'; -- PIO Write PingPong full
-- DMA registers
signal s_DMA_dev0_Td,
s_DMA_dev0_Tm,
s_DMA_dev0_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device0
signal s_DMA_dev1_Td,
s_DMA_dev1_Tm,
s_DMA_dev1_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device1
signal s_DMActrl_DMAen,
s_DMActrl_dir,
s_DMActrl_Bytesw,
s_DMActrl_BeLeC0,
s_DMActrl_BeLeC1 : std_logic:='0'; -- DMA settings
-- signal s_DMAsel : std_logic:='0'; -- DMA controller select
-- signal s_DMAack : std_logic:='0'; -- DMA controller acknowledge
-- signal s_DMAq : std_logic_vector(31 downto 0); -- DMA data out
-- signal s_DMAtip : std_logic:='0'; -- DMA transfer in progress
signal s_DMA_dmarq : std_logic:='0'; -- Synchronized ATA DMARQ line
-- signal s_DMATxFull : std_logic:='0'; -- DMA transmit buffer full
-- signal s_DMARxEmpty : std_logic:='0'; -- DMA receive buffer empty
-- signal s_DMA_req : std_logic:='0'; -- DMA request to external DMA engine
-- signal s_DMA_ack : std_logic:='0'; -- DMA acknowledge from external DMA engine
signal s_IDEctrl_ppen : std_logic; --:='0';
signal datemp : std_logic_vector(2 downto 0):="000";
-- signal s_mst_bm : ahb_dma_out_type;
-- signal s_bm_mst : ahb_dma_in_type;
-- signal s_slv_bm : slv_to_bm_type := SLV_TO_BM_RESET_VECTOR;
-- signal s_bm_slv : bm_to_slv_type := BM_TO_SLV_RESET_VECTOR;
-- signal s_bm_ctr : bm_to_ctrl_type;
-- signal s_ctr_bm : ctrl_to_bm_type;
signal s_bmi : bmi_type;
signal s_bmo : bmo_type;
signal s_d : std_logic_vector(31 downto 0);
signal s_we, s_irq : std_logic;
constant DMA_mode0_Tm : natural := 4; -- 50ns
constant DMA_mode0_Td : natural := 21; -- 215ns
constant DMA_mode0_Teoc : natural := 21; -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
constant SECTOR_LENGTH : integer := 16;
-- signal PIOa_temp : std_logic_vector(7 downto 0);
--**********************END SIGNAL DECLARATION********************************
begin
gnd <= '0';vcc <= '1'; gnd32 <= zero32;
-- generate asynchronous reset level
arst_signal <= arst;-- xor ARST_LVL;
reset <= not rst;
da<=datemp;
--PIOa_temp <= unsigned(PIOa);
--dmack <= vcc; -- Disable DMA
-- Generate CompactFlash signals
--cfo.power connected to bit 31 of the control register
cfo.atasel <= gnd;
cfo.we <= vcc;
cfo.csel <= gnd;
cfo.da <= (others => gnd);
--s_bmi.fr_mst<=s_mst_bm; s_bmi.fr_slv<=s_slv_bm; s_bmi.fr_ctr<=s_ctr_bm;
--s_bmo.to_mst<=s_bm_mst; s_bmo.to_slv<=s_slv_bm; s_bmo.to_ctr<=s_bm_ctr;
with s_bmi.fr_slv.en select
s_d(15 downto 0)<=s_bmo.d(15 downto 0) when '1',
PIOd when others;
with s_bmi.fr_slv.en select
s_d(31 downto 16)<=s_bmo.d(31 downto 16) when '1',
(others=>'0') when others;
with s_bmi.fr_slv.en select
s_we<=s_bmo.we when '1',
PIOwe when others;
with s_bmi.fr_slv.en select --for guaranteeing coherent memory before irq
s_irq<=irq and (not s_bmo.to_mst.start) when '1',
irq when others;
s_bmi.fr_ctr.irq<=irq;
slv: atahost_amba_slave
generic map(
hindex => hindex,
haddr => haddr,
hmask => hmask,
pirq => pirq,
DeviceID => DeviceID,
RevisionNo => RevisionNo,
-- PIO mode 0 settings
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
-- Multiword DMA mode 0 settings
-- OCIDEC-1 does not support DMA, set registers to zero
DMA_mode0_Tm => 0,
DMA_mode0_Td => 0,
DMA_mode0_Teoc => 0
)
port map(
arst => arst_signal,
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
cf_power => cfo.power, -- power switch for compactflash
-- PIO control input
-- PIOtip is only asserted during a PIO transfer (No shit! ;)
-- Since it is impossible to read the status register and access the PIO registers at the same time
-- this bit is useless (besides using-up resources)
PIOtip => gnd,
PIOack => PIOack,
PIOq => PIOq,
PIOsel => PIOsel,
PIOpp_full => gnd, -- OCIDEC-1 does not support PIO-write PingPong, negate signal
irq => s_irq,
PIOa => PIOa,
PIOd => PIOd,
PIOwe => PIOwe,
-- DMA control inputs (negate all of them)
DMAtip => s_bmi.fr_ctr.tip, --Erik Jagre 2006-11-13
-- DMAack => gnd,
DMARxEmpty => s_bmi.fr_ctr.rx_empty, --Erik Jagre 2006-11-13
DMATxFull => s_bmi.fr_ctr.fifo_rdy, --Erik Jagre 2006-11-13
DMA_dmarq => s_DMA_dmarq, --Erik Jagre 2006-11-13
-- DMAq => gnd32,
-- outputs
-- control register outputs
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
-- CMD port timing registers
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
-- data-port0 timing registers
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
-- data-port1 timing registers
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
-- Bus master edits by Erik Jagre 2006-10-04 ---------------start--
DMActrl_Bytesw=> s_DMActrl_Bytesw,
DMActrl_BeLeC0=> s_DMActrl_BeLeC0,
DMActrl_BeLeC1=> s_DMActrl_BeLeC1,
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
fr_BM =>s_bmo.to_slv,
to_BM =>s_bmi.fr_slv
-- Bus master edits by Erik Jagre 2006-10-04 ------------------end-------
);
ctr: atahost_controller
generic map(
fdepth => fdepth,
tech => tech,
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map(
clk => clk,
nReset => arst_signal,
rst => reset,
irq => irq,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_rst => IDEctrl_rst,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
a => PIOa,
d => s_d,
we => s_we,
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
PIOsel => PIOsel,
PIOack => PIOack,
PIOq => PIOq,
PIOtip => s_PIOtip,
PIOpp_full => s_PIOpp_full,
--DMA
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMActrl_Bytesw => s_DMActrl_Bytesw,
DMActrl_BeLeC0 => s_DMActrl_BeLeC0,
DMActrl_BeLeC1 => s_DMActrl_BeLeC1,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
DMAsel => s_bmo.to_ctr.sel,
DMAack => s_bmi.fr_ctr.ack,
DMAq => s_bmi.fr_ctr.q,
DMAtip_out => s_bmi.fr_ctr.tip,
DMA_dmarq => s_DMA_dmarq,
force_rdy => s_bmo.to_ctr.force_rdy,
fifo_rdy => s_bmi.fr_ctr.fifo_rdy,
DMARxEmpty => s_bmi.fr_ctr.rx_empty,
DMARxFull => s_bmi.fr_ctr.rx_full,
DMA_req => s_bmi.fr_ctr.req,
DMA_ack => s_bmo.to_ctr.ack,
BM_en => s_bmi.fr_slv.en, -- Bus mater enabled, for DMA reset Erik Jagre 2006-10-24
--ATA
RESETn => ata_resetn,
DDi => ddin,
DDo => ddout,
DDoe => ddoe,
DA => datemp,
CS0n => cs0n,
CS1n => cs1n,
DIORn => diorn,
DIOWn => diown,
IORDY => iordy,
INTRQ => intrq,
DMARQ => dmarq,
DMACKn => dmack
);
mst : ahbmst
generic map(
hindex => mhindex,
hirq => 0,
venid => VENDOR_GAISLER,
devid => GAISLER_ATACTRL,
version => 0,
chprot => 3,
incaddr => 4)
port map (
rst => rst,
clk => clk,
dmai => s_bmo.to_mst,
dmao => s_bmi.fr_mst,
ahbi => ahbmi,
ahbo => ahbmo
);
bm : atahost_ahbmst
generic map(fdepth=>fdepth)
port map(
clk => clk,
rst => rst,
i => s_bmi,
o => s_bmo
);
-- pragma translate_off
bootmsg : report_version
generic map ("atactrl" & tost(hindex) &
": ATA controller rev " & tost(VERSION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: atactrl
-- File: atactrl.vhd
-- Author: Nils-Johan Wessman, Gaisler Research
-- Description: ATA controller
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ata.all;
use gaisler.misc.all; --2007-1-16
use gaisler.ata_inf.all;
library opencores;
use opencores.occomp.all;
entity atactrl_dma is
generic (
tech : integer := 0;
fdepth : integer := 8;
mhindex : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
TWIDTH : natural := 8; -- counter width
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
cfo : out cf_out_type;
-- ATA signals
ddin : in std_logic_vector(15 downto 0);
iordy : in std_logic;
intrq : in std_logic;
ata_resetn : out std_logic;
ddout : out std_logic_vector(15 downto 0);
ddoe : out std_logic;
da : out std_logic_vector(2 downto 0);
cs0n : out std_logic;
cs1n : out std_logic;
diorn : out std_logic;
diown : out std_logic;
dmack : out std_logic;
dmarq : in std_logic
);
end;
architecture rtl of atactrl_dma is
-- Device ID
constant DeviceId : integer := 2;
constant RevisionNo : integer := 0;
constant VERSION : integer := 0;
component atahost_amba_slave is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#ff0#;
pirq : integer := 0;
DeviceID : integer := 0;
RevisionNo : integer := 0;
-- PIO mode 0 settings (@100MHz clock)
PIO_mode0_T1 : natural := 6; -- 70ns
PIO_mode0_T2 : natural := 28; -- 290ns
PIO_mode0_T4 : natural := 2; -- 30ns
PIO_mode0_Teoc : natural := 23; -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
-- Multiword DMA mode 0 settings (@100MHz clock)
DMA_mode0_Tm : natural := 4; -- 50ns
DMA_mode0_Td : natural := 21; -- 215ns
DMA_mode0_Teoc : natural := 21 -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
);
port (
rst : in std_ulogic;
arst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
cf_power: out std_logic;
-- ata controller signals
-- PIO control input
PIOsel : out std_logic;
PIOtip, -- PIO transfer in progress
PIOack : in std_logic; -- PIO acknowledge signal
PIOq : in std_logic_vector(15 downto 0); -- PIO data input
PIOpp_full : in std_logic; -- PIO write-ping-pong buffers full
irq : in std_logic; -- interrupt signal input
PIOa : out std_logic_vector(3 downto 0);
PIOd : out std_logic_vector(15 downto 0);
PIOwe : out std_logic;
-- DMA control inputs
-- DMAsel : out std_logic;
DMAtip, -- DMA transfer in progress
-- DMAack, -- DMA transfer acknowledge
DMARxEmpty, -- DMA receive buffer empty
DMATxFull, -- DMA transmit buffer full
DMA_dmarq : in std_logic; -- wishbone DMA request
-- DMAq : in std_logic_vector(31 downto 0);
-- outputs
-- control register outputs
IDEctrl_rst,
IDEctrl_IDEen,
IDEctrl_FATR1,
IDEctrl_FATR0,
IDEctrl_ppen,
DMActrl_DMAen,
DMActrl_dir,
DMActrl_Bytesw, --Jagre 2006-12-04
DMActrl_BeLeC0,
DMActrl_BeLeC1 : out std_logic;
-- CMD port timing registers
PIO_cmdport_T1,
PIO_cmdport_T2,
PIO_cmdport_T4,
PIO_cmdport_Teoc : out std_logic_vector(7 downto 0);
PIO_cmdport_IORDYen : out std_logic;
-- data-port0 timing registers
PIO_dport0_T1,
PIO_dport0_T2,
PIO_dport0_T4,
PIO_dport0_Teoc : out std_logic_vector(7 downto 0);
PIO_dport0_IORDYen : out std_logic;
-- data-port1 timing registers
PIO_dport1_T1,
PIO_dport1_T2,
PIO_dport1_T4,
PIO_dport1_Teoc : out std_logic_vector(7 downto 0);
PIO_dport1_IORDYen : out std_logic;
-- DMA device0 timing registers
DMA_dev0_Tm,
DMA_dev0_Td,
DMA_dev0_Teoc : out std_logic_vector(7 downto 0);
-- DMA device1 timing registers
DMA_dev1_Tm,
DMA_dev1_Td,
DMA_dev1_Teoc : out std_logic_vector(7 downto 0);
-- Bus master edits by Erik Jagre 2006-10-03 ------------------start-----
fr_BM : in bm_to_slv_type;
to_BM : out slv_to_bm_type
-- Bus master edits by Erik Jagre 2006-10-03 ------------------end-------
);
end component atahost_amba_slave;
component atahost_ahbmst is
generic(fdepth : integer := 8);
Port(clk : in std_logic;
rst : in std_logic;
i : in bmi_type;
o : out bmo_type
);
end component atahost_ahbmst;
-- asynchronous reset signal
signal arst_signal : std_logic;
-- primary address decoder
-- signal PIOsel,s_bmen : std_logic; -- controller select, IDE devices select
signal PIOsel : std_logic; -- controller select, IDE devices select
-- control signal
signal IDEctrl_rst, IDEctrl_IDEen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic;
-- compatible mode timing
signal s_PIO_cmdport_T1, s_PIO_cmdport_T2, s_PIO_cmdport_T4, s_PIO_cmdport_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_cmdport_IORDYen : std_logic;
-- data port0 timing
signal s_PIO_dport0_T1, s_PIO_dport0_T2, s_PIO_dport0_T4, s_PIO_dport0_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport0_IORDYen : std_logic;
-- data port1 timing
signal s_PIO_dport1_T1, s_PIO_dport1_T2, s_PIO_dport1_T4, s_PIO_dport1_Teoc : std_logic_vector(7 downto 0);
signal s_PIO_dport1_IORDYen : std_logic;
signal PIOack : std_logic;
signal PIOq : std_logic_vector(15 downto 0);
signal PIOa : std_logic_vector(3 downto 0):="0000";
signal PIOd : std_logic_vector(15 downto 0) := X"0000";
signal PIOwe : std_logic;
signal irq : std_logic; -- ATA bus IRQ signal
signal reset : std_logic;
signal gnd,vcc : std_logic;
signal gnd32 : std_logic_vector(31 downto 0);
--**********************SIGNAL DECLARATION*****by Erik Jagre 2006-10-04*******
signal s_PIOtip : std_logic:='0'; -- PIO transfer in progress
signal s_PIOpp_full : std_logic:='0'; -- PIO Write PingPong full
-- DMA registers
signal s_DMA_dev0_Td,
s_DMA_dev0_Tm,
s_DMA_dev0_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device0
signal s_DMA_dev1_Td,
s_DMA_dev1_Tm,
s_DMA_dev1_Teoc : std_logic_vector(7 downto 0):= X"03"; -- DMA timing settings for device1
signal s_DMActrl_DMAen,
s_DMActrl_dir,
s_DMActrl_Bytesw,
s_DMActrl_BeLeC0,
s_DMActrl_BeLeC1 : std_logic:='0'; -- DMA settings
-- signal s_DMAsel : std_logic:='0'; -- DMA controller select
-- signal s_DMAack : std_logic:='0'; -- DMA controller acknowledge
-- signal s_DMAq : std_logic_vector(31 downto 0); -- DMA data out
-- signal s_DMAtip : std_logic:='0'; -- DMA transfer in progress
signal s_DMA_dmarq : std_logic:='0'; -- Synchronized ATA DMARQ line
-- signal s_DMATxFull : std_logic:='0'; -- DMA transmit buffer full
-- signal s_DMARxEmpty : std_logic:='0'; -- DMA receive buffer empty
-- signal s_DMA_req : std_logic:='0'; -- DMA request to external DMA engine
-- signal s_DMA_ack : std_logic:='0'; -- DMA acknowledge from external DMA engine
signal s_IDEctrl_ppen : std_logic; --:='0';
signal datemp : std_logic_vector(2 downto 0):="000";
-- signal s_mst_bm : ahb_dma_out_type;
-- signal s_bm_mst : ahb_dma_in_type;
-- signal s_slv_bm : slv_to_bm_type := SLV_TO_BM_RESET_VECTOR;
-- signal s_bm_slv : bm_to_slv_type := BM_TO_SLV_RESET_VECTOR;
-- signal s_bm_ctr : bm_to_ctrl_type;
-- signal s_ctr_bm : ctrl_to_bm_type;
signal s_bmi : bmi_type;
signal s_bmo : bmo_type;
signal s_d : std_logic_vector(31 downto 0);
signal s_we, s_irq : std_logic;
constant DMA_mode0_Tm : natural := 4; -- 50ns
constant DMA_mode0_Td : natural := 21; -- 215ns
constant DMA_mode0_Teoc : natural := 21; -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215
constant SECTOR_LENGTH : integer := 16;
-- signal PIOa_temp : std_logic_vector(7 downto 0);
--**********************END SIGNAL DECLARATION********************************
begin
gnd <= '0';vcc <= '1'; gnd32 <= zero32;
-- generate asynchronous reset level
arst_signal <= arst;-- xor ARST_LVL;
reset <= not rst;
da<=datemp;
--PIOa_temp <= unsigned(PIOa);
--dmack <= vcc; -- Disable DMA
-- Generate CompactFlash signals
--cfo.power connected to bit 31 of the control register
cfo.atasel <= gnd;
cfo.we <= vcc;
cfo.csel <= gnd;
cfo.da <= (others => gnd);
--s_bmi.fr_mst<=s_mst_bm; s_bmi.fr_slv<=s_slv_bm; s_bmi.fr_ctr<=s_ctr_bm;
--s_bmo.to_mst<=s_bm_mst; s_bmo.to_slv<=s_slv_bm; s_bmo.to_ctr<=s_bm_ctr;
with s_bmi.fr_slv.en select
s_d(15 downto 0)<=s_bmo.d(15 downto 0) when '1',
PIOd when others;
with s_bmi.fr_slv.en select
s_d(31 downto 16)<=s_bmo.d(31 downto 16) when '1',
(others=>'0') when others;
with s_bmi.fr_slv.en select
s_we<=s_bmo.we when '1',
PIOwe when others;
with s_bmi.fr_slv.en select --for guaranteeing coherent memory before irq
s_irq<=irq and (not s_bmo.to_mst.start) when '1',
irq when others;
s_bmi.fr_ctr.irq<=irq;
slv: atahost_amba_slave
generic map(
hindex => hindex,
haddr => haddr,
hmask => hmask,
pirq => pirq,
DeviceID => DeviceID,
RevisionNo => RevisionNo,
-- PIO mode 0 settings
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
-- Multiword DMA mode 0 settings
-- OCIDEC-1 does not support DMA, set registers to zero
DMA_mode0_Tm => 0,
DMA_mode0_Td => 0,
DMA_mode0_Teoc => 0
)
port map(
arst => arst_signal,
rst => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso,
cf_power => cfo.power, -- power switch for compactflash
-- PIO control input
-- PIOtip is only asserted during a PIO transfer (No shit! ;)
-- Since it is impossible to read the status register and access the PIO registers at the same time
-- this bit is useless (besides using-up resources)
PIOtip => gnd,
PIOack => PIOack,
PIOq => PIOq,
PIOsel => PIOsel,
PIOpp_full => gnd, -- OCIDEC-1 does not support PIO-write PingPong, negate signal
irq => s_irq,
PIOa => PIOa,
PIOd => PIOd,
PIOwe => PIOwe,
-- DMA control inputs (negate all of them)
DMAtip => s_bmi.fr_ctr.tip, --Erik Jagre 2006-11-13
-- DMAack => gnd,
DMARxEmpty => s_bmi.fr_ctr.rx_empty, --Erik Jagre 2006-11-13
DMATxFull => s_bmi.fr_ctr.fifo_rdy, --Erik Jagre 2006-11-13
DMA_dmarq => s_DMA_dmarq, --Erik Jagre 2006-11-13
-- DMAq => gnd32,
-- outputs
-- control register outputs
IDEctrl_rst => IDEctrl_rst,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
-- CMD port timing registers
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
-- data-port0 timing registers
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
-- data-port1 timing registers
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
-- Bus master edits by Erik Jagre 2006-10-04 ---------------start--
DMActrl_Bytesw=> s_DMActrl_Bytesw,
DMActrl_BeLeC0=> s_DMActrl_BeLeC0,
DMActrl_BeLeC1=> s_DMActrl_BeLeC1,
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
fr_BM =>s_bmo.to_slv,
to_BM =>s_bmi.fr_slv
-- Bus master edits by Erik Jagre 2006-10-04 ------------------end-------
);
ctr: atahost_controller
generic map(
fdepth => fdepth,
tech => tech,
TWIDTH => TWIDTH,
PIO_mode0_T1 => PIO_mode0_T1,
PIO_mode0_T2 => PIO_mode0_T2,
PIO_mode0_T4 => PIO_mode0_T4,
PIO_mode0_Teoc => PIO_mode0_Teoc,
DMA_mode0_Tm => DMA_mode0_Tm,
DMA_mode0_Td => DMA_mode0_Td,
DMA_mode0_Teoc => DMA_mode0_Teoc
)
port map(
clk => clk,
nReset => arst_signal,
rst => reset,
irq => irq,
IDEctrl_IDEen => IDEctrl_IDEen,
IDEctrl_rst => IDEctrl_rst,
IDEctrl_ppen => s_IDEctrl_ppen,
IDEctrl_FATR0 => IDEctrl_FATR0,
IDEctrl_FATR1 => IDEctrl_FATR1,
a => PIOa,
d => s_d,
we => s_we,
PIO_cmdport_T1 => s_PIO_cmdport_T1,
PIO_cmdport_T2 => s_PIO_cmdport_T2,
PIO_cmdport_T4 => s_PIO_cmdport_T4,
PIO_cmdport_Teoc => s_PIO_cmdport_Teoc,
PIO_cmdport_IORDYen => s_PIO_cmdport_IORDYen,
PIO_dport0_T1 => s_PIO_dport0_T1,
PIO_dport0_T2 => s_PIO_dport0_T2,
PIO_dport0_T4 => s_PIO_dport0_T4,
PIO_dport0_Teoc => s_PIO_dport0_Teoc,
PIO_dport0_IORDYen => s_PIO_dport0_IORDYen,
PIO_dport1_T1 => s_PIO_dport1_T1,
PIO_dport1_T2 => s_PIO_dport1_T2,
PIO_dport1_T4 => s_PIO_dport1_T4,
PIO_dport1_Teoc => s_PIO_dport1_Teoc,
PIO_dport1_IORDYen => s_PIO_dport1_IORDYen,
PIOsel => PIOsel,
PIOack => PIOack,
PIOq => PIOq,
PIOtip => s_PIOtip,
PIOpp_full => s_PIOpp_full,
--DMA
DMActrl_DMAen => s_DMActrl_DMAen,
DMActrl_dir => s_DMActrl_dir,
DMActrl_Bytesw => s_DMActrl_Bytesw,
DMActrl_BeLeC0 => s_DMActrl_BeLeC0,
DMActrl_BeLeC1 => s_DMActrl_BeLeC1,
DMA_dev0_Td => s_DMA_dev0_Td,
DMA_dev0_Tm => s_DMA_dev0_Tm,
DMA_dev0_Teoc => s_DMA_dev0_Teoc,
DMA_dev1_Td => s_DMA_dev1_Td,
DMA_dev1_Tm => s_DMA_dev1_Tm,
DMA_dev1_Teoc => s_DMA_dev1_Teoc,
DMAsel => s_bmo.to_ctr.sel,
DMAack => s_bmi.fr_ctr.ack,
DMAq => s_bmi.fr_ctr.q,
DMAtip_out => s_bmi.fr_ctr.tip,
DMA_dmarq => s_DMA_dmarq,
force_rdy => s_bmo.to_ctr.force_rdy,
fifo_rdy => s_bmi.fr_ctr.fifo_rdy,
DMARxEmpty => s_bmi.fr_ctr.rx_empty,
DMARxFull => s_bmi.fr_ctr.rx_full,
DMA_req => s_bmi.fr_ctr.req,
DMA_ack => s_bmo.to_ctr.ack,
BM_en => s_bmi.fr_slv.en, -- Bus mater enabled, for DMA reset Erik Jagre 2006-10-24
--ATA
RESETn => ata_resetn,
DDi => ddin,
DDo => ddout,
DDoe => ddoe,
DA => datemp,
CS0n => cs0n,
CS1n => cs1n,
DIORn => diorn,
DIOWn => diown,
IORDY => iordy,
INTRQ => intrq,
DMARQ => dmarq,
DMACKn => dmack
);
mst : ahbmst
generic map(
hindex => mhindex,
hirq => 0,
venid => VENDOR_GAISLER,
devid => GAISLER_ATACTRL,
version => 0,
chprot => 3,
incaddr => 4)
port map (
rst => rst,
clk => clk,
dmai => s_bmo.to_mst,
dmao => s_bmi.fr_mst,
ahbi => ahbmi,
ahbo => ahbmo
);
bm : atahost_ahbmst
generic map(fdepth=>fdepth)
port map(
clk => clk,
rst => rst,
i => s_bmi,
o => s_bmo
);
-- pragma translate_off
bootmsg : report_version
generic map ("atactrl" & tost(hindex) &
": ATA controller rev " & tost(VERSION) & ", irq " & tost(pirq));
-- pragma translate_on
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Reset_Altera
--
-- Description:
-- ------------------------------------
-- This is a clock-domain-crossing circuit for reset signals optimized for
-- Altera FPGAs. It infers 2 flip flops with asynchronous preset and notifies
-- Quartus II, that these flip flops are synchronizer flip flops. If you need
-- a platform independent version of this synchronizer, please use
-- 'PoC.misc.sync.sync_Reset', which internally instantiates this module if
-- a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for reset signals.
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Reset_Altera is
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC; -- Data to be synchronized
Output : out STD_LOGIC -- synchronised data
);
end entity;
architecture rtl of sync_Reset_Altera is
attribute altera_attribute : STRING;
attribute preserve : BOOLEAN;
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := '1';
signal Data_sync : STD_LOGIC := '1';
-- Apply a SDC constraint to meta stable flip flop
--attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to *|sync_Reset_Altera:*|Data_meta """;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute altera_attribute of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
-- preserve both registers (no optimization, shift register extraction, ...)
attribute preserve of Data_meta : signal is TRUE;
attribute preserve of Data_sync : signal is TRUE;
begin
Data_async <= '0';
process(Clock)
begin
if (Input = '1') then
Data_meta <= '1';
Data_sync <= '1';
elsif rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output <= Data_sync;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: sync_Reset_Altera
--
-- Description:
-- ------------------------------------
-- This is a clock-domain-crossing circuit for reset signals optimized for
-- Altera FPGAs. It infers 2 flip flops with asynchronous preset and notifies
-- Quartus II, that these flip flops are synchronizer flip flops. If you need
-- a platform independent version of this synchronizer, please use
-- 'PoC.misc.sync.sync_Reset', which internally instantiates this module if
-- a Altera FPGA is detected.
--
-- ATTENTION:
-- Use this synchronizer only for reset signals.
--
-- CONSTRAINTS:
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sync_Reset_Altera is
port (
Clock : in STD_LOGIC; -- Clock to be synchronized to
Input : in STD_LOGIC; -- Data to be synchronized
Output : out STD_LOGIC -- synchronised data
);
end entity;
architecture rtl of sync_Reset_Altera is
attribute altera_attribute : STRING;
attribute preserve : BOOLEAN;
signal Data_async : STD_LOGIC;
signal Data_meta : STD_LOGIC := '1';
signal Data_sync : STD_LOGIC := '1';
-- Apply a SDC constraint to meta stable flip flop
--attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to *|sync_Reset_Altera:*|Data_meta """;
-- Notity the synthesizer / timing analysator to identity a synchronizer circuit
attribute altera_attribute of Data_meta : signal is "-name SYNCHRONIZER_IDENTIFICATION ""FORCED IF ASYNCHRONOUS""";
-- preserve both registers (no optimization, shift register extraction, ...)
attribute preserve of Data_meta : signal is TRUE;
attribute preserve of Data_sync : signal is TRUE;
begin
Data_async <= '0';
process(Clock)
begin
if (Input = '1') then
Data_meta <= '1';
Data_sync <= '1';
elsif rising_edge(Clock) then
Data_meta <= Data_async;
Data_sync <= Data_meta;
end if;
end process;
Output <= Data_sync;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library STD;
use IEEE.NUMERIC_STD.ALL;
entity DSPn is
port(
CLK : in std_logic;
CE : in std_logic;
RST_N : in std_logic;
ENABLE : in std_logic;
A0 : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CS_N : in std_logic;
RD_N : in std_logic;
WR_N : in std_logic;
DP_ADDR : in std_logic_vector(11 downto 0);
DP_SEL : in std_logic;
VER : in std_logic_vector(2 downto 0);--00-DSP1B, 01-DSP2, 10-DSP3, 11-DSP4
BRK_OUT : out std_logic;
DBG_REG : in std_logic_vector(7 downto 0);
DBG_DAT_IN : in std_logic_vector(7 downto 0);
DBG_DAT_OUT : out std_logic_vector(7 downto 0);
DBG_DAT_WR : in std_logic
);
end DSPn;
architecture rtl of DSPn is
constant ACC_A : integer range 0 to 1 := 0;
constant ACC_B : integer range 0 to 1 := 1;
constant FLAG_OV0 : integer range 0 to 5 := 0;
constant FLAG_OV1 : integer range 0 to 5 := 1;
constant FLAG_Z : integer range 0 to 5 := 2;
constant FLAG_C : integer range 0 to 5 := 3;
constant FLAG_S0 : integer range 0 to 5 := 4;
constant FLAG_S1 : integer range 0 to 5 := 5;
constant INSTR_OP: std_logic_vector(1 downto 0) := "00";
constant INSTR_RT: std_logic_vector(1 downto 0) := "01";
constant INSTR_JP: std_logic_vector(1 downto 0) := "10";
constant INSTR_LD: std_logic_vector(1 downto 0) := "11";
-- IO Registers
signal DR : std_logic_vector(15 downto 0);
signal SR : std_logic_vector(15 downto 0);
signal DP : std_logic_vector(10 downto 0);
signal RP : std_logic_vector(10 downto 0);
signal PC : std_logic_vector(10 downto 0);
type StackRam_t is array (0 to 7) of std_logic_vector(10 downto 0);
signal STACK_RAM : StackRam_t;
signal SP : unsigned(2 downto 0);
signal K, L, M, N : std_logic_vector(15 downto 0);
signal P, Q : std_logic_vector(15 downto 0);
type Acc_t is array (0 to 1) of std_logic_vector(15 downto 0);
signal ACC : Acc_t;
type Flags_t is array (0 to 1) of std_logic_vector(5 downto 0);
signal FLAGS : Flags_t;
signal TR, TRB : std_logic_vector(15 downto 0);
signal SI, SO : std_logic_vector(15 downto 0);
signal SGN : std_logic_vector(15 downto 0);
signal RQM : std_logic;
signal DRS, DRC : std_logic;
signal USF0, USF1 : std_logic;
signal P0, P1 : std_logic;
signal EI, DMA : std_logic;
signal OP_DST : std_logic_vector(3 downto 0);
signal OP_SRC : std_logic_vector(3 downto 0);
signal OP_RP : std_logic;
signal OP_DPH : std_logic_vector(3 downto 0);
signal OP_DPL : std_logic_vector(1 downto 0);
signal OP_A : unsigned(0 downto 0);
signal OP_ALU : std_logic_vector(3 downto 0);
signal OP_P : std_logic_vector(1 downto 0);
signal OP_ID : std_logic_vector(15 downto 0);
signal OP_NA : std_logic_vector(10 downto 0);
signal OP_BRCH : std_logic_vector(8 downto 0);
signal OP_INSTR : std_logic_vector(1 downto 0);
signal IDB : std_logic_vector(15 downto 0);
signal ALU_R : std_logic_vector(15 downto 0);
signal PROG_ROM_ADDR : std_logic_vector(12 downto 0);
signal PROG_ROM_Q : std_logic_vector(23 downto 0);
signal DATA_ROM_ADDR : std_logic_vector(12 downto 0);
signal DATA_ROM_Q : std_logic_vector(15 downto 0);
signal DATA_RAM_ADDR_A, DATA_RAM_ADDR_B : std_logic_vector(10 downto 0);
signal DATA_RAM_Q_A, DATA_RAM_Q_B : std_logic_vector(15 downto 0);
signal DATA_RAM_WE : std_logic;
signal EN : std_logic;
signal RD_Nr, WR_Nr : std_logic_vector(2 downto 0);
signal PORT_ACTIVE : std_logic;
--debug
signal DBG_RUN_LAST : std_logic;
signal DBG_DAT_WRr : std_logic;
signal DBG_BRK_ADDR : std_logic_vector(10 downto 0) := (others => '1');
signal DBG_CTRL : std_logic_vector(7 downto 0) := (others => '0');
component dp16k_wrapper_8bit
generic (
addr_width : natural := 11
);
port (
clock : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
data_a : in STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
enable_a : in STD_LOGIC := '1';
wren_a : in STD_LOGIC := '0';
q_a : out STD_LOGIC_VECTOR (7 DOWNTO 0);
cs_a : in std_logic := '1';
address_b : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0) := (others => '0');
data_b : in STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0');
enable_b : in STD_LOGIC := '1';
wren_b : in STD_LOGIC := '0';
q_b : out STD_LOGIC_VECTOR (7 DOWNTO 0);
cs_b : in std_logic := '1'
);
end component;
component sprom_verilog is
generic (
addr_width : integer := 8;
data_width : integer := 8;
length : integer := 8;
hex_file : string := ""
);
port
(
clock : in STD_LOGIC;
address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0)
);
end component;
begin
EN <= ENABLE and CE;
OP_INSTR <= PROG_ROM_Q(23 downto 22);
OP_P <= PROG_ROM_Q(21 downto 20);
OP_ALU <= PROG_ROM_Q(19 downto 16);
OP_A <= unsigned(PROG_ROM_Q(15 downto 15));
OP_DPL <= PROG_ROM_Q(14 downto 13);
OP_DPH <= PROG_ROM_Q(12 downto 9);
OP_RP <= PROG_ROM_Q(8);
OP_SRC <= PROG_ROM_Q(7 downto 4);
OP_DST <= PROG_ROM_Q(3 downto 0);
OP_ID <= PROG_ROM_Q(21 downto 6) when OP_INSTR = INSTR_LD else IDB;
OP_NA <= PROG_ROM_Q(12 downto 2);
OP_BRCH <= PROG_ROM_Q(21 downto 13);
SGN <= x"8000" xor (0 to 15 => FLAGS(ACC_A)(FLAG_S1));
SR <= RQM & USF1 & USF0 & DRS & DMA & DRC & "00" & EI & "00000" & P1 & P0;
SI <= (others => '0');
IDB <= TRB when OP_SRC = x"0" else
ACC(ACC_A) when OP_SRC = x"1" else
ACC(ACC_B) when OP_SRC = x"2" else
TR when OP_SRC = x"3" else
"00000" & DP when OP_SRC = x"4" and VER(2) = '1' else
"00000" & RP when OP_SRC = x"5" and VER(2) = '1' else
x"00" & DP(7 downto 0) when OP_SRC = x"4" else
"000000" & RP(9 downto 0) when OP_SRC = x"5" else
DATA_ROM_Q when OP_SRC = x"6" else
SGN when OP_SRC = x"7" else
DR when OP_SRC = x"8" else
DR when OP_SRC = x"9" else
SR when OP_SRC = x"A" else
SI when OP_SRC = x"B" else
SI when OP_SRC = x"C" else
K when OP_SRC = x"D" else
L when OP_SRC = x"E" else
DATA_RAM_Q_A when OP_SRC = x"F" else
x"0000";
--ALU
Q <= ACC(to_integer(OP_A));
P <= x"0001" when OP_ALU(3 downto 1) = "100" else
DATA_RAM_Q_A when OP_P = "00" else
IDB when OP_P = "01" else
M when OP_P = "10" else
N;
process( OP_ALU, P, Q, ALU_R, FLAGS, OP_A)
variable FC : std_logic;
variable CARRY : unsigned(15 downto 0);
begin
FC := FLAGS(to_integer(not OP_A))(FLAG_C);
CARRY := (0 => FC, others => '0');
case OP_ALU is
when x"1" =>
ALU_R <= Q or P;
when x"2" =>
ALU_R <= Q and P;
when x"3" =>
ALU_R <= Q xor P;
when x"4" =>
ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P));
when x"5" =>
ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P));
when x"6" =>
ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P) - CARRY);
when x"7" =>
ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P) + CARRY);
when x"8" =>
ALU_R <= std_logic_vector(unsigned(Q) - unsigned(P));
when x"9" =>
ALU_R <= std_logic_vector(unsigned(Q) + unsigned(P));
when x"A" =>
ALU_R <= not Q;
when x"B" =>
ALU_R <= Q(15) & Q(15 downto 1);
when x"C" =>
ALU_R <= Q(14 downto 0) & FC;
when x"D" =>
ALU_R <= Q(13 downto 0) & "11";
when x"E" =>
ALU_R <= Q(11 downto 0) & "1111";
when x"F" =>
ALU_R <= Q(7 downto 0) & Q(15 downto 8);
when others =>
ALU_R <= Q;
end case;
end process;
--Flags
process(CLK, RST_N)
variable OV0 : std_logic;
begin
if RST_N = '0' then
FLAGS <= (others => (others => '0'));
elsif rising_edge(CLK) then
if EN = '1' then
if (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) and OP_ALU /= x"0" then
FLAGS(to_integer(OP_A))(FLAG_S0) <= ALU_R(15);
if ALU_R = x"0000" then
FLAGS(to_integer(OP_A))(FLAG_Z) <= '1';
else
FLAGS(to_integer(OP_A))(FLAG_Z) <= '0';
end if;
case OP_ALU is
when x"1" | x"2" | x"3" | x"A" | x"D" | x"E" | x"F" =>
FLAGS(to_integer(OP_A))(FLAG_C) <= '0';
when x"4" | x"6" | x"8" =>
if ALU_R > Q then
FLAGS(to_integer(OP_A))(FLAG_C) <= '1';
else
FLAGS(to_integer(OP_A))(FLAG_C) <= '0';
end if;
when x"5" | x"7" | x"9" =>
if ALU_R < Q then
FLAGS(to_integer(OP_A))(FLAG_C) <= '1';
else
FLAGS(to_integer(OP_A))(FLAG_C) <= '0';
end if;
when x"B" =>
FLAGS(to_integer(OP_A))(FLAG_C) <= Q(0);
when x"C" =>
FLAGS(to_integer(OP_A))(FLAG_C) <= Q(15);
when others => null;
end case;
OV0 := (Q(15) xor ALU_R(15)) and ((Q(15) xor P(15)) xor OP_ALU(0));
case OP_ALU is
when x"1" | x"2" | x"3" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" =>
FLAGS(to_integer(OP_A))(FLAG_OV0) <= '0';
FLAGS(to_integer(OP_A))(FLAG_OV1) <= '0';
when x"4" | x"5" | x"6" | x"7" | x"8" | x"9" =>
FLAGS(to_integer(OP_A))(FLAG_OV0) <= OV0;
if OV0 = '1' then
FLAGS(to_integer(OP_A))(FLAG_S1) <= FLAGS(to_integer(OP_A))(FLAG_OV1) xor (not ALU_R(15));
FLAGS(to_integer(OP_A))(FLAG_OV1) <= not FLAGS(to_integer(OP_A))(FLAG_OV1);
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
--Multiplier
process(K, L)
variable TEMP : signed(30 downto 0);
begin
TEMP := resize((signed(K) * signed(L)),TEMP'length);
M <= std_logic_vector(TEMP(30 downto 15));
N <= std_logic_vector(TEMP(14 downto 0)) & "0";
end process;
--Registers
process(CLK, RST_N)
variable DAT : std_logic_vector(15 downto 0);
begin
if RST_N = '0' then
ACC <= (others => (others => '0'));
TR <= (others => '0');
DP <= (others => '0');
RP <= (others => '1');
DRC <= '0';
USF1 <= '0';
USF0 <= '0';
DMA <= '0';
EI <= '0';
P1 <= '0';
P0 <= '0';
TRB <= (others => '0');
SO <= (others => '0');
K <= (others => '0');
L <= (others => '0');
elsif rising_edge(CLK) then
if EN = '1' then
if (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) then
if OP_ALU /= x"0" then
ACC(to_integer(OP_A)) <= ALU_R;
end if;
case OP_DPL is
when "01" =>
DP(3 downto 0) <= std_logic_vector(unsigned(DP(3 downto 0)) + 1);
when "10" =>
DP(3 downto 0) <= std_logic_vector(unsigned(DP(3 downto 0)) - 1);
when "11" =>
DP(3 downto 0) <= (others => '0');
when others => null;
end case;
DP(7 downto 4) <= DP(7 downto 4) xor OP_DPH;
if OP_RP = '1' then
RP <= std_logic_vector(unsigned(RP) - 1);
end if;
end if;
if OP_INSTR /= INSTR_JP then
case OP_DST is
when x"1" =>
ACC(ACC_A) <= OP_ID;
when x"2" =>
ACC(ACC_B) <= OP_ID;
when x"3" =>
TR <= OP_ID;
when x"4" =>
DP <= OP_ID(10 downto 0);
when x"5" =>
RP <= OP_ID(10 downto 0);
when x"7" =>
USF1 <= OP_ID(14);
USF0 <= OP_ID(13);
DMA <= OP_ID(11);
DRC <= OP_ID(10);
EI <= OP_ID(7);
P1 <= OP_ID(1);
P0 <= OP_ID(0);
when x"8" =>
SO <= OP_ID;
when x"9" =>
SO <= OP_ID;
when x"A" =>
K <= OP_ID;
when x"B" =>
K <= OP_ID;
L <= DATA_ROM_Q;
when x"C" =>
K <= DATA_RAM_Q_B;
L <= OP_ID;
when x"D" =>
L <= OP_ID;
when x"E" =>
TRB <= OP_ID;
when others => null;
end case;
end if;
end if;
end if;
end process;
process(CLK, RST_N)
variable NEXT_SP : unsigned(2 downto 0);
variable NEXT_PC : std_logic_vector(10 downto 0);
variable COND : std_logic;
begin
if RST_N = '0' then
STACK_RAM <= (others => (others => '0'));
SP <= (others => '0');
PC <= (others => '0');
elsif rising_edge(CLK) then
if EN = '1' then
NEXT_PC := std_logic_vector(unsigned(PC) + 1);
if OP_INSTR = INSTR_RT then
NEXT_SP := SP - 1;
PC <= STACK_RAM(to_integer((NEXT_SP(2) and VER(2))&NEXT_SP(1 downto 0)));
SP <= NEXT_SP;
elsif OP_INSTR = INSTR_JP then
case OP_BRCH(5 downto 2) is
when "0000" =>
COND := FLAGS(ACC_A)(FLAG_C) xor (not OP_BRCH(1));
when "0001" =>
COND := FLAGS(ACC_B)(FLAG_C) xor (not OP_BRCH(1));
when "0010" =>
COND := FLAGS(ACC_A)(FLAG_Z) xor (not OP_BRCH(1));
when "0011" =>
COND := FLAGS(ACC_B)(FLAG_Z) xor (not OP_BRCH(1));
when "0100" =>
COND := FLAGS(ACC_A)(FLAG_OV0) xor (not OP_BRCH(1));
when "0101" =>
COND := FLAGS(ACC_B)(FLAG_OV0) xor (not OP_BRCH(1));
when "0110" =>
COND := FLAGS(ACC_A)(FLAG_OV1) xor (not OP_BRCH(1));
when "0111" =>
COND := FLAGS(ACC_B)(FLAG_OV1) xor (not OP_BRCH(1));
when "1000" =>
COND := FLAGS(ACC_A)(FLAG_S0) xor (not OP_BRCH(1));
when "1001" =>
COND := FLAGS(ACC_B)(FLAG_S0) xor (not OP_BRCH(1));
when "1010" =>
COND := FLAGS(ACC_A)(FLAG_S1) xor (not OP_BRCH(1));
when "1011" =>
COND := FLAGS(ACC_B)(FLAG_S1) xor (not OP_BRCH(1));
when "1100" =>
if (DP(3 downto 0) = (0 to 3 => OP_BRCH(1)) and OP_BRCH(0) = '0') or
(DP(3 downto 0) /= (0 to 3 => OP_BRCH(1)) and OP_BRCH(0) = '1') then
COND := '1';
else
COND := '0';
end if;
when "1111" =>
COND := RQM xor (not OP_BRCH(1));
when others =>
COND := '0';
end case;
if OP_BRCH = "000000000" then
PC <= SO(10 downto 0);
elsif OP_BRCH(8 downto 6) = "010" and COND = '1' then
PC <= OP_NA;
elsif OP_BRCH(8 downto 7) = "10" and OP_BRCH(5 downto 0) = "000000" then
PC <= OP_NA;
if OP_BRCH(6) = '1' then
STACK_RAM(to_integer((SP(2) and VER(2))&SP(1 downto 0))) <= NEXT_PC;
SP <= SP + 1;
end if;
else
PC <= NEXT_PC;
end if;
else
PC <= NEXT_PC;
end if;
end if;
end if;
end process;
PROG_ROM_ADDR <= std_logic_vector(unsigned(PC) + ("0"&x"000")) when VER="000" else
std_logic_vector(unsigned(PC) + ("0"&x"500")) when VER="001" else
std_logic_vector(unsigned(PC) + ("0"&x"C00")) when VER="010" else
std_logic_vector(unsigned(PC) + ("1"&x"254")) when VER="011" else
std_logic_vector(unsigned(PC) + ("1"&x"954"));
PROG_ROM : sprom_verilog generic map(13, 24, 7018, "../src/chip/DSP/dsp1b23410_p.hex")
port map(
clock => CLK,
address => PROG_ROM_ADDR,
q => PROG_ROM_Q
);
DATA_ROM_ADDR <= VER(2 downto 1) & (VER(0) or (RP(10) and VER(2))) & RP(9 downto 0);
DATA_ROM : sprom_verilog generic map(13, 16, 6144, "../src/chip/DSP/dsp1b23410_d.hex")
port map(
clock => CLK,
address => DATA_ROM_ADDR,
q => DATA_ROM_Q
);
DATA_RAM_ADDR_A <= "000" & DP(7 downto 0) when VER(2)='0' else DP;
DATA_RAM_ADDR_B <= DP_ADDR(11 downto 1) when DP_SEL = '1' and (WR_N = '0' or RD_N = '0') else DATA_RAM_ADDR_A or x"40";
DATA_RAM_WE <= '1' when OP_INSTR /= INSTR_JP and OP_DST = x"F" and EN = '1' else '0';
DATA_RAML : dp16k_wrapper_8bit generic map(11)
port map(
clock => CLK,
address_a => DATA_RAM_ADDR_A,
data_a => OP_ID(7 downto 0),
wren_a => DATA_RAM_WE,
q_a => DATA_RAM_Q_A(7 downto 0),
address_b => DATA_RAM_ADDR_B,
data_b => DI,
wren_b => not WR_N and DP_SEL and not DP_ADDR(0),
q_b => DATA_RAM_Q_B(7 downto 0)
);
DATA_RAMH : dp16k_wrapper_8bit generic map(11)
port map(
clock => CLK,
address_a => DATA_RAM_ADDR_A,
data_a => OP_ID(15 downto 8),
wren_a => DATA_RAM_WE,
q_a => DATA_RAM_Q_A(15 downto 8),
address_b => DATA_RAM_ADDR_B,
data_b => DI,
wren_b => not WR_N and DP_SEL and DP_ADDR(0),
q_b => DATA_RAM_Q_B(15 downto 8)
);
--I/O Ports
process(CLK, RST_N)
begin
if RST_N = '0' then
DRS <= '0';
RQM <= '0';
DR <= (others => '0');
WR_Nr <= (others => '1');
RD_Nr <= (others => '1');
PORT_ACTIVE <= '0';
elsif rising_edge(CLK) then
if ENABLE = '1' then
WR_Nr <= WR_Nr(1 downto 0) & WR_N;
RD_Nr <= RD_Nr(1 downto 0) & RD_N;
if WR_Nr = "110" and CS_N = '0' and A0 = '0' then
if DRC = '0' then
if DRS = '0' then
DR(7 downto 0) <= DI;
else
DR(15 downto 8) <= DI;
end if;
else
DR(7 downto 0) <= DI;
end if;
PORT_ACTIVE <= '1';
elsif RD_Nr = "110" and CS_N = '0' and A0 = '0' then
PORT_ACTIVE <= '1';
end if;
if (WR_Nr = "001" or RD_Nr = "001") and PORT_ACTIVE = '1' then
if DRC = '0' then
if DRS = '0' then
DRS <= '1';
else
RQM <= '0';
DRS <= '0';
end if;
else
RQM <= '0';
end if;
PORT_ACTIVE <= '0';
elsif EN = '1' then
if OP_INSTR /= INSTR_JP and OP_DST = x"6" then
DR <= OP_ID;
RQM <= '1';
elsif (OP_INSTR = INSTR_OP or OP_INSTR = INSTR_RT) and OP_SRC = x"8" then
RQM <= '1';
end if;
end if;
end if;
end if;
end process;
process( A0, SR, DR, DRC, DRS, DP_SEL, DP_ADDR, DATA_RAM_Q_B )
begin
if DP_SEL = '1' then
if DP_ADDR(0) = '0' then
DO <= DATA_RAM_Q_B(7 downto 0);
else
DO <= DATA_RAM_Q_B(15 downto 8);
end if;
elsif A0 = '1' then
DO <= SR(15 downto 8);
else
if DRC = '0' then
if DRS = '0' then
DO <= DR(7 downto 0);
else
DO <= DR(15 downto 8);
end if;
else
DO <= DR(7 downto 0);
end if;
end if;
end process;
--Debug
process(CLK, RST_N)
begin
if RST_N = '0' then
BRK_OUT <= '0';
DBG_RUN_LAST <= '0';
elsif rising_edge(CLK) then
if EN = '1' then
BRK_OUT <= '0';
if DBG_CTRL(0) = '1' then --step
BRK_OUT <= '1';
elsif DBG_CTRL(2) = '1' and DBG_BRK_ADDR = PC then --opcode address break
BRK_OUT <= '1';
end if;
end if;
DBG_RUN_LAST <= DBG_CTRL(7);
if DBG_CTRL(7) = '1' and DBG_RUN_LAST = '0' then
BRK_OUT <= '0';
end if;
end if;
end process;
process( RST_N, CLK, DBG_REG, ACC, FLAGS, PC, RP, DP, TR, TRB, K, L, M, N, DR, SR, SP, IDB )
begin
case DBG_REG is
when x"00" => DBG_DAT_OUT <= ACC(ACC_A)(7 downto 0);
when x"01" => DBG_DAT_OUT <= ACC(ACC_A)(15 downto 8);
when x"02" => DBG_DAT_OUT <= ACC(ACC_B)(7 downto 0);
when x"03" => DBG_DAT_OUT <= ACC(ACC_B)(15 downto 8);
when x"04" => DBG_DAT_OUT <= "00"&FLAGS(ACC_A);
when x"05" => DBG_DAT_OUT <= "00"&FLAGS(ACC_B);
when x"06" => DBG_DAT_OUT <= PC(7 downto 0);
when x"07" => DBG_DAT_OUT <= "00000"&PC(10 downto 8);
when x"08" => DBG_DAT_OUT <= RP(7 downto 0);
when x"09" => DBG_DAT_OUT <= "000000"&RP(9 downto 8);
when x"0A" => DBG_DAT_OUT <= DP(7 downto 0);
when x"0B" => DBG_DAT_OUT <= TR(7 downto 0);
when x"0C" => DBG_DAT_OUT <= TR(15 downto 8);
when x"0D" => DBG_DAT_OUT <= TRB(7 downto 0);
when x"0E" => DBG_DAT_OUT <= TRB(15 downto 8);
when x"0F" => DBG_DAT_OUT <= K(7 downto 0);
when x"10" => DBG_DAT_OUT <= K(15 downto 8);
when x"11" => DBG_DAT_OUT <= L(7 downto 0);
when x"12" => DBG_DAT_OUT <= L(15 downto 8);
when x"13" => DBG_DAT_OUT <= M(7 downto 0);
when x"14" => DBG_DAT_OUT <= M(15 downto 8);
when x"15" => DBG_DAT_OUT <= N(7 downto 0);
when x"16" => DBG_DAT_OUT <= N(15 downto 8);
when x"17" => DBG_DAT_OUT <= DR(7 downto 0);
when x"18" => DBG_DAT_OUT <= DR(15 downto 8);
when x"19" => DBG_DAT_OUT <= SR(7 downto 0);
when x"1A" => DBG_DAT_OUT <= SR(15 downto 8);
when x"1B" => DBG_DAT_OUT <= "00000" & std_logic_vector(SP);
when x"1C" => DBG_DAT_OUT <= IDB(7 downto 0);
when x"1D" => DBG_DAT_OUT <= IDB(15 downto 8);
when others => DBG_DAT_OUT <= x"00";
end case;
if RST_N = '0' then
DBG_DAT_WRr <= '0';
elsif rising_edge(CLK) then
DBG_DAT_WRr <= DBG_DAT_WR;
if DBG_DAT_WR = '1' and DBG_DAT_WRr = '0' then
case DBG_REG is
when x"80" => DBG_BRK_ADDR(7 downto 0) <= DBG_DAT_IN;
when x"81" => DBG_BRK_ADDR(10 downto 8) <= DBG_DAT_IN(2 downto 0);
when x"82" => null;
when x"83" => DBG_CTRL <= DBG_DAT_IN;
when others => null;
end case;
end if;
end if;
end process;
end rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_debounce is
end tb_debounce;
architecture behav of tb_debounce is
signal clk : std_logic := '0';
signal io_i : std_logic := '0';
signal io_o : std_logic := '0';
signal noise : std_logic := '0';
signal fixed : std_logic := '0';
signal toggling : std_logic := '0';
signal riseedge : std_logic := '0';
signal falledge: std_logic := '0';
begin
process
begin
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
VARIABLE seed1: positive := 1;
VARIABLE seed2: positive := 1;
VARIABLE rand: real;
VARIABLE t_rand: time;
begin
noise <= not noise;
UNIFORM(seed1, seed2, rand);
t_rand := (rand*100.0)*1 ns;
wait for t_rand;
end process;
process
begin
wait for 1400 ns;
toggling <= '1';
wait for 600 ns;
toggling <= '0';
fixed <= '1';
wait for 2000 ns;
toggling <= '1';
fixed <= '0';
wait for 1000 ns;
toggling <= '0';
wait for 3000 ns;
assert false report "done" severity failure;
wait;
end process;
io_i <= noise when toggling = '1' else
fixed;
debounce : entity work.debounce
generic map(
CNT => 15 -- 1500000 = 30 ms at 50 MHz; hier 300ns
)
port map(
clk_50 => clk,
input => io_i,
output => io_o,
riseedge => riseedge,
falledge => falledge
);
end behav;
|
package fifo_pkg is
signal wr_en : std_logic;
signal rd_en : std_logic;
constant c_constant : integer;
alias alias1 : subtype_indicator is name;
alias alias1 is name;
signal wr_en : std_logic;
signal rd_en : std_logic;
constant c_constant : integer;
alias alias1 : subtype_indicator is name;
alias alias1 is name;
end package;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity DrinksFSM is
port( C : in std_logic;
V : in std_logic;
reset : in std_logic;
clk : in std_logic;
drink : out std_logic);
end DrinksFSM;
architecture Behavioral of DrinksFSM is
type Tstate is (S0,S1,S2,S3,S4,S5);
signal pState, nState : Tstate;
begin
clk_proc: process(clk, reset)
begin
if(reset = '1') then
pState <= S0;
elsif(rising_edge(clk)) then
pState <= nState;
end if;
end process;
comb_process: process(pState, C, V)
begin
drink <= '0';
case pState is
when S0 =>
if(C='1') then
nState <= S3;
elsif(V='1') then
nState <= S1;
else
nState <= S0;
end if;
when S1 =>
if(C='1') then
nState <= S4;
elsif(V='1') then
nState <= S2;
else
nState <= S1;
end if;
when S2 =>
if(C='1') then
nState <= S5;
elsif(V='1') then
nState <= S3;
else
nState <= S2;
end if;
when S3 =>
if(C='1') then
nState <= S5;
elsif(V='1') then
nState <= S4;
else
nState <= S3;
end if;
when S4 =>
if(C='1' or V='1') then
nState <= S5;
else
nState <= S4;
end if;
when S5 =>
drink <= '1';
when others =>
nState <= S0;
end case;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.id_pkg.all;
use work.encode_pkg.all;
use work.test_config.all;
entity pipeline_tb is
end entity pipeline_tb;
architecture testbench of pipeline_tb is
signal clk : std_logic := '0';
signal rst_n : std_logic := '1';
-- inputs
signal insn_in : word := (others => '0');
signal insn_addr : word := (others => '0');
signal insn_valid : std_logic := '0';
-- shift registers to simulate delays in accessing memory
constant c_data_in_delay : integer := 4; -- number of delay cycles for memory reads
type data_in_sr_t is array (0 to c_data_in_delay - 1) of std_logic_vector(31 downto 0); --word;
type data_in_valid_sr_t is array (0 to c_data_in_delay - 1) of std_logic;
signal data_in : data_in_sr_t := (others => (others => '0'));
signal data_in_valid : data_in_valid_sr_t := (others => '0');
signal data_valid : std_logic;
-- outputs
signal data_write_en : std_logic;
signal data_read_en : std_logic;
signal data_addr : word;
signal data_out : word;
-- simulation specific
signal done : boolean := false;
constant clk_period : time := 10 ns; -- 100 MHz
file memfile : text open write_mode is "sim/memio.vec";
-- data memory
type ram_t is array(0 to 100) of word;
signal ram : ram_t := (0 => X"80008081",
others => (others => '0'));
begin
instruction_memory : entity work.dpram(rtl)
generic map (g_data_width => 32,
g_addr_width => 8,
g_init => true,
g_init_file => pipeline_tb_test_vector_input_filename)
port map (clk => clk,
addr_a => insn_addr(7 downto 0),
data_a => (others => '0'),
we_a => '0',
q_a => insn_in,
addr_b => (others => '0'),
data_b => (others => '0'),
we_b => '0',
q_b => open);
-- create a clock
clk <= '0' when done else (not clk) after clk_period / 2;
-- purpose: data memory
ram_proc : process (clk, rst_n) is
variable addr : integer;
variable valid : std_logic;
begin
if rst_n = '0' then
reset_shift_regs : for i in data_in'range loop
data_in(i) <= (others => '0');
data_in_valid(i) <= '0';
end loop reset_shift_regs;
elsif rising_edge(clk) then
-- default values
data_in_valid(0) <= '0';
data_in(0) <= (others => '0');
-- create shift registers
shift_regs : for i in 1 to data_in'high loop
data_in(i) <= data_in(i - 1);
data_in_valid(i) <= data_in_valid(i - 1);
end loop shift_regs;
if ((data_in_valid(data_in_valid'high) = '0')
and (data_in_valid(data_in_valid'high - 1) = '1')) then
valid := '1';
else
valid := '0';
end if;
data_valid <= valid;
-- writes/reads
addr := to_integer(unsigned(data_addr));
if data_write_en = '1' then
ram(addr) <= data_out;
elsif data_read_en = '1' then
data_in(0) <= ram(addr);
data_in_valid(0) <= '1';
end if;
end if;
end process ram_proc;
---------------------------------------------------
-- print memory bus transactions
---------------------------------------------------
log_memio_proc : process (data_write_en, data_read_en, data_valid, clk) is
variable l : line;
begin -- process log_memio_proc
if data_write_en = '1' and clk = '0' then
write(l, string'("W "));
write(l, hstr(data_addr));
write(l, string'(", "));
write(l, hstr(data_out));
writeline(memfile, l);
end if;
if (data_valid = '1' and clk = '0') then
write(l, string'("R "));
write(l, hstr(data_addr));
write(l, string'(", "));
write(l, hstr(data_in(data_in'high)));
writeline(memfile, l);
end if;
end process log_memio_proc;
-- instantiate the unit under test
uut : entity work.pipeline(Behavioral)
generic map (
g_initial_pc => (others => '0'),
g_for_sim => true)
port map (
clk => clk,
rst_n => rst_n,
insn_in => insn_in,
insn_addr => insn_addr,
insn_valid => insn_valid,
data_in => data_in(data_in'high),
data_out => data_out,
data_addr => data_addr,
data_write_en => data_write_en,
data_read_en => data_read_en,
data_in_valid => data_valid);
-- purpose: Provide stimulus to test the pipeline
stimulus_proc : process is
variable i : natural := 0;
begin -- process stimulus_proc
-- reset sequence
println ("Beginning simulation");
-- fill up the instruction memory
rst_n <= '0';
wait for clk_period * 2;
rst_n <= '1';
-- begin stimulus
wait for clk_period;
insn_valid <= '1';
-- run for a bit.
wait for clk_period * 35;
-- finished with simulation
----------------------------------------------------------------
println("Simulation complete");
----------------------------------------------------------------
done <= true;
wait;
end process stimulus_proc;
end architecture testbench;
|
entity test is
type t is protected end protected;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1226.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p29n01i01226ent IS
END c08s01b00x00p29n01i01226ent;
ARCHITECTURE c08s01b00x00p29n01i01226arch OF c08s01b00x00p29n01i01226ent IS
BEGIN
TESTING: PROCESS
function test_1 (a:integer; b:boolean) return integer is
variable c : integer := 1;
begin
wait for 100 ns;
return c;
end;
variable k : integer := 0;
variable y : boolean := false;
variable i : integer;
BEGIN
i := test_1 (a=>k, b=>y);
assert FALSE
report "***FAILED TEST: c08s01b00x00p29n01i01226 - Wait not allowed in a function subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p29n01i01226arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1226.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p29n01i01226ent IS
END c08s01b00x00p29n01i01226ent;
ARCHITECTURE c08s01b00x00p29n01i01226arch OF c08s01b00x00p29n01i01226ent IS
BEGIN
TESTING: PROCESS
function test_1 (a:integer; b:boolean) return integer is
variable c : integer := 1;
begin
wait for 100 ns;
return c;
end;
variable k : integer := 0;
variable y : boolean := false;
variable i : integer;
BEGIN
i := test_1 (a=>k, b=>y);
assert FALSE
report "***FAILED TEST: c08s01b00x00p29n01i01226 - Wait not allowed in a function subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p29n01i01226arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1226.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p29n01i01226ent IS
END c08s01b00x00p29n01i01226ent;
ARCHITECTURE c08s01b00x00p29n01i01226arch OF c08s01b00x00p29n01i01226ent IS
BEGIN
TESTING: PROCESS
function test_1 (a:integer; b:boolean) return integer is
variable c : integer := 1;
begin
wait for 100 ns;
return c;
end;
variable k : integer := 0;
variable y : boolean := false;
variable i : integer;
BEGIN
i := test_1 (a=>k, b=>y);
assert FALSE
report "***FAILED TEST: c08s01b00x00p29n01i01226 - Wait not allowed in a function subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p29n01i01226arch;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Find_Correct_Errors_N_v3
-- Module Name: Tb_Find_Correct_Errors_N_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Testbench for polynomial_syndrome_computing_n circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_pipelines :
--
-- Number of pipelines used in the circuit to test the support elements and
-- correct the message. Each pipeline needs at least 2 memory ram to store
-- intermediate results.
--
-- pipeline_size :
--
-- The number of stages of the pipeline. More stages means more values of sigma
-- are tested at once.
--
-- size_pipeline_size :
--
-- The number of bits necessary to store the size of the pipeline.
-- This is ceil(log2(pipeline_size))
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- length_support_elements :
--
-- The number of support elements. This parameter depends of the Goppa code used.
--
-- size_support_elements :
--
-- The size of the memory that holds all support elements. This parameter
-- depends of the Goppa code used.
-- This is ceil(log2(length_support_elements))
--
-- x_memory_file :
--
-- File that holds the values to be evaluated on the polynomial. Support elements L.
--
-- sigma_memory_file :
--
-- File that holds polynomial sigma coefficients.
--
-- resp_memory_file :
--
-- File that holds all evaluations of support L on polynomial sigma.
-- This file holds the output of the circuit,
-- it is needed to detect if polynomial evaluator circuit worked properly.
--
-- dump_acc_memory_file :
--
-- File that will hold the output of all support L evaluations on polynomial sigma,
-- that were done by the circuit.
--
-- codeword_memory_file :
--
-- File that holds the ciphertext that will be corrected according to the polynomial
-- sigma roots that were found.
--
-- message_memory_file :
--
-- File that holds the ciphertext already corrected.
-- This file is necessary to detect
-- if the ciphertext correction was performed correctly by the circuit.
--
-- dump_codeword_memory_file :
--
-- File that will hold the ciphertext corrected by the circuit.
--
-- dump_error_memory_file :
--
-- File that will hold the errors found on the ciphertext by the circuit.
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- polynomial_syndrome_computing_n Rev 1.0
-- ram Rev 1.0
-- ram_bank Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_find_correct_errors_n_v3 is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 6;
-- sigma_degree : integer := 4;
-- size_sigma_degree : integer := 2;
-- length_support_elements: integer := 52;
-- size_support_elements : integer := 6;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_52_28_4_6.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_52_28_4_6.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_52_28_4_6.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_pipelines : integer := 4;
-- pipeline_size : integer := 2;
-- size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 27;
-- size_sigma_degree : integer := 5;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1751_27_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1751_27_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1751_27_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1751_27_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 11;
-- sigma_degree : integer := 50;
-- size_sigma_degree : integer := 6;
-- length_support_elements: integer := 2048;
-- size_support_elements : integer := 11;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_2048_1498_50_11.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_2048_1498_50_11.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_2048_1498_50_11.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_2048_1498_50_11.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 7;
-- size_pipeline_size : integer := 3;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 66;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3307;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_goppa_3307_2515_66_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_goppa_3307_2515_66_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_goppa_3307_2515_66_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_goppa_3307_2515_66_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_pipelines : integer := 1;
pipeline_size : integer := 33;
size_pipeline_size : integer := 6;
gf_2_m : integer range 1 to 20 := 12;
sigma_degree : integer := 32;
size_sigma_degree : integer := 6;
length_support_elements: integer := 2528;
size_support_elements : integer := 12;
x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12_1.dat";
sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2528_2144_32_12_1.dat";
resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2528_2144_32_12_1.dat";
dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2528_2144_32_12_1.dat";
codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12_1.dat";
message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12_1.dat";
dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2528_2144_32_12_1.dat";
dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2528_2144_32_12_1.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 2816;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_2816_2048_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_2816_2048_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 65;
-- size_pipeline_size : integer := 7;
-- gf_2_m : integer range 1 to 20 := 12;
-- sigma_degree : integer := 64;
-- size_sigma_degree : integer := 7;
-- length_support_elements: integer := 3328;
-- size_support_elements : integer := 12;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_3328_2560_64_12.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_3328_2560_64_12.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_pipelines : integer := 1;
-- pipeline_size : integer := 129;
-- size_pipeline_size : integer := 8;
-- gf_2_m : integer range 1 to 20 := 13;
-- sigma_degree : integer := 128;
-- size_sigma_degree : integer := 8;
-- length_support_elements: integer := 7296;
-- size_support_elements : integer := 13;
-- x_memory_file : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- sigma_memory_file : string := "mceliece/data_tests/sigma_qdgoppa_7296_5632_128_13.dat";
-- resp_memory_file : string := "mceliece/data_tests/sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- dump_acc_memory_file : string := "mceliece/data_tests/dump_sigma(L)_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- message_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- dump_codeword_memory_file : string := "mceliece/data_tests/dump_ciphertext_qdgoppa_7296_5632_128_13.dat";
-- dump_error_memory_file : string := "mceliece/data_tests/dump_error_qdgoppa_7296_5632_128_13.dat"
);
end tb_find_correct_errors_n_v3;
architecture Behavioral of tb_find_correct_errors_n_v3 is
component ram
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component polynomial_syndrome_computing_n
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
number_of_errors : integer;
size_number_of_errors : integer;
number_of_support_elements : integer;
size_number_of_support_elements : integer
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_h : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
mode_polynomial_syndrome : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
computation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_support_elements - 1) downto 0);
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal value_x : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_h : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal mode_polynomial_syndrome : STD_LOGIC;
signal computation_finalized : STD_LOGIC;
signal address_value_polynomial : STD_LOGIC_VECTOR((size_sigma_degree - 1) downto 0);
signal address_value_x : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_message : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_acc : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal address_new_value_syndrome : STD_LOGIC_VECTOR((size_sigma_degree) downto 0);
signal address_value_error : STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
signal write_enable_new_value_acc : STD_LOGIC;
signal write_enable_new_value_syndrome : STD_LOGIC;
signal write_enable_new_value_message : STD_LOGIC;
signal write_enable_value_error : STD_LOGIC;
signal new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal new_value_acc : STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal new_value_message : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
signal value_error : STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
constant test_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant true_codeword_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant error_rst_value : std_logic_vector(0 downto 0) := (others => '0');
constant x_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant sigma_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant true_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
constant test_acc_rst_value : std_logic_vector((gf_2_m - 1) downto 0) := (others => '0');
signal test_codeword_dump : std_logic := '0';
signal true_codeword_dump : std_logic := '0';
signal x_dump : std_logic := '0';
signal sigma_dump : std_logic := '0';
signal true_acc_dump : std_logic := '0';
signal test_acc_dump : std_logic := '0';
signal error_dump : std_logic := '0';
signal test_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal test_codeword_address : STD_LOGIC_VECTOR ((size_support_elements - 1) downto 0);
signal true_acc_value : STD_LOGIC_VECTOR (((gf_2_m)*(number_of_pipelines) - 1) downto 0);
signal true_codeword_value : STD_LOGIC_VECTOR ((number_of_pipelines - 1) downto 0);
signal error_acc : STD_LOGIC;
signal error_message : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for true_codeword : ram_bank use entity work.ram_bank(file_load);
for test_codeword : ram_double_bank use entity work.ram_double_bank(file_load);
for x : ram_bank use entity work.ram_bank(file_load);
for sigma : ram use entity work.ram(file_load);
for true_acc : ram_bank use entity work.ram_bank(file_load);
for test_acc : ram_double_bank use entity work.ram_double_bank(simple);
for error : ram_bank use entity work.ram_bank(simple);
begin
test_codeword : ram_double_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => dump_codeword_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_message,
rw_a => '0',
rw_b => write_enable_new_value_message,
clk => clk,
rst => rst,
dump => test_codeword_dump,
address_a => test_codeword_address,
address_b => address_new_value_message,
rst_value => test_codeword_rst_value,
data_out_a => value_message,
data_out_b => open
);
error : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_error_memory_file
)
Port Map(
data_in => value_error,
rw => write_enable_value_error,
clk => clk,
rst => rst,
dump => error_dump,
address => address_value_error,
rst_value => error_rst_value,
data_out => open
);
true_codeword : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_codeword_dump,
address => true_codeword_address,
rst_value => true_codeword_rst_value,
data_out => true_codeword_value
);
x : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => x_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => x_dump,
address => address_value_x,
rst_value => x_rst_value,
data_out => value_x
);
true_acc : ram_bank
Generic Map (
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => resp_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => true_acc_dump,
address => true_acc_address,
rst_value => true_acc_rst_value,
data_out => true_acc_value
);
test_acc : ram_double_bank
Generic Map(
number_of_memories => number_of_pipelines,
ram_address_size => size_support_elements,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => "",
dump_file_name => dump_acc_memory_file
)
Port Map(
data_in_a => (others => '0'),
data_in_b => new_value_acc,
rw_a => '0',
rw_b => write_enable_new_value_acc,
clk => clk,
rst => rst,
dump => test_acc_dump,
address_a => test_acc_address,
address_b => address_new_value_acc,
rst_value => test_acc_rst_value,
data_out_a => value_acc,
data_out_b => open
);
sigma : ram
Generic Map (
ram_address_size => size_sigma_degree,
ram_word_size => gf_2_m,
file_ram_word_size => gf_2_m,
load_file_name => sigma_memory_file,
dump_file_name => ""
)
Port Map (
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => sigma_dump,
address => address_value_polynomial,
rst_value => sigma_rst_value,
data_out => value_polynomial
);
poly : polynomial_syndrome_computing_n
Generic Map(
number_of_pipelines => number_of_pipelines,
pipeline_size => pipeline_size,
size_pipeline_size => size_pipeline_size,
gf_2_m => gf_2_m,
number_of_support_elements => length_support_elements,
size_number_of_support_elements => size_support_elements,
number_of_errors => sigma_degree,
size_number_of_errors => size_sigma_degree
)
Port Map(
value_x => value_x,
value_acc => value_acc,
value_polynomial => value_polynomial,
value_message => value_message,
value_h => value_h,
mode_polynomial_syndrome => mode_polynomial_syndrome,
clk => clk,
rst => rst,
computation_finalized => computation_finalized,
address_value_polynomial => address_value_polynomial,
address_value_x => address_value_x,
address_value_acc => address_value_acc,
address_value_message => address_value_message,
address_new_value_message => address_new_value_message,
address_new_value_acc => address_new_value_acc,
address_new_value_syndrome => address_new_value_syndrome,
address_value_error => address_value_error,
write_enable_new_value_acc => write_enable_new_value_acc,
write_enable_new_value_syndrome => write_enable_new_value_syndrome,
write_enable_new_value_message => write_enable_new_value_message,
write_enable_value_error => write_enable_value_error,
new_value_syndrome => new_value_syndrome,
new_value_acc => new_value_acc,
new_value_message => new_value_message,
value_error => value_error
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
test_acc_address <= address_value_acc when computation_finalized = '0' else
true_acc_address;
test_codeword_address <= address_value_x when computation_finalized = '0' else
true_codeword_address;
mode_polynomial_syndrome <= '0';
process
variable i : integer;
begin
true_acc_address <= (others => '0');
true_codeword_address <= (others => '0');
rst <= '1';
error_acc <= '0';
error_message <= '0';
wait for PERIOD*2;
rst <= '0';
wait until computation_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_support_elements)) loop
error_message <= '0';
error_acc <= '0';
true_acc_address <= std_logic_vector(to_unsigned(i, true_acc_address'Length));
true_codeword_address <= std_logic_vector(to_unsigned(i, true_codeword_address'Length));
wait for PERIOD*2;
if (true_acc_value = value_acc) then
error_acc <= '0';
else
error_acc <= '1';
report "Computed values do not match expected ones";
end if;
if (true_codeword_value = value_message) then
error_message <= '0';
else
error_message <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_acc <= '0';
error_message <= '0';
wait for PERIOD;
i := i + number_of_pipelines;
end loop;
error_message <= '0';
error_acc <= '0';
test_acc_dump <= '1';
test_codeword_dump <= '1';
wait for PERIOD;
test_acc_dump <= '0';
test_codeword_dump <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.NoCPackage.all;
entity Thor_buffer is
port(
clock: in std_logic;
reset: in std_logic;
clock_rx: in std_logic;
rx: in std_logic;
data_in: in regflit;
credit_o: out std_logic;
h: out std_logic;
ack_h: in std_logic;
data_av: out std_logic;
data: out regflit;
data_ack: in std_logic;
sender: out std_logic);
end Thor_buffer;
architecture Thor_buffer of Thor_buffer is
type fila_out is (REQ_ROUTING, SEND_DATA);
signal next_state, current_state : fila_out;
signal pull: std_logic;
signal bufferHead : regflit;
signal has_data: std_logic;
signal has_data_and_sending : std_logic;
signal counter : integer;
signal sending : std_logic;
signal sent : std_logic;
begin
circularFifoBuffer : entity work.fifo_buffer
generic map(BUFFER_DEPTH => TAM_BUFFER ,
BUFFER_WIDTH => regflit'length)
port map(
reset => reset,
clock => clock_rx,
tail => data_in,
push => rx,
pull => pull,
counter => counter,
head => bufferHead
);
data <= bufferHead;
data_av <= has_data_and_sending;
credit_o <= '1' when (counter /= TAM_BUFFER or pull = '1') else '0';
sender <= sending;
h <= has_data and not sending;
pull <= data_ack and has_data_and_sending;
has_data <= '1' when (counter /= 0) else '0';
has_data_and_sending <= has_data and sending;
process(current_state, ack_h, sent)
begin
next_state <= current_state;
case current_state is
when REQ_ROUTING =>
if ack_h = '1' then
next_state <= SEND_DATA;
end if;
when SEND_DATA =>
if sent = '1' then
next_state <= REQ_ROUTING;
end if;
end case;
end process;
process(reset, clock)
begin
if reset = '1' then
current_state <= REQ_ROUTING;
elsif rising_edge(clock) then
current_state <= next_state;
end if;
end process;
process(current_state, sent)
begin
case current_state is
when SEND_DATA =>
sending <= not sent;
when others =>
sending <= '0';
end case;
end process;
process(reset, clock)
variable flit_index : integer;
variable counter_flit : integer;
begin
if reset = '1' then
sent <= '0';
elsif rising_edge(clock) then
if sending = '1' then
if data_ack = '1' and has_data = '1' then
sent <= '0';
if flit_index = 1 then
counter_flit := to_integer(unsigned(bufferHead));
elsif counter_flit /= 1 then
counter_flit := counter_flit - 1;
else -- counter_flit = 1
sent <= '1';
end if;
flit_index := flit_index + 1;
else
end if;
else
flit_index := 0;
counter_flit := 0;
sent <= '0';
end if;
end if;
end process;
end Thor_buffer;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity score is
port
(
left_score_e, right_score_e, refresh_clk, rst : in std_logic;
left_score_out, right_score_out : out std_logic_vector(3 downto 0)
);
end score;
architecture bhv of score is
signal left_score,right_score : unsigned(3 downto 0);
begin
process(refresh_clk, rst)
begin
if(rst = '1') then
left_score <= to_unsigned(0,4);
right_score <= to_unsigned(0,4);
elsif(rising_edge(refresh_clk)) then
if(left_score_e = '1') then
left_score <= left_score + 1;
elsif(right_score_e = '1') then
right_score <= right_score + 1;
else
left_score <= left_score;
right_score <= right_score;
end if;
end if;
end process;
left_score_out <= std_logic_vector(left_score);
right_score_out <= std_logic_vector(right_score);
end bhv; |
-------------------------------------------------------------------------------
-- axi_sg_intrpt
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/14/10 v1_00_a
-- ^^^^^^
-- CR565366
-- Fixed issue where simultaneous sof and eof caused delay timer to not enable
-- thus missing a delay interrupt. This issue occurs with small packets(i.e.
-- 2 data beats)
-- ~~~~~~
-- GAB 7/1/10 v1_00_a
-- ^^^^^^
-- CR567661
-- Remapped interrupt threshold control to be driven based on whether update
-- engine is included or not. Renamed interrupt threshold decrement control here
-- to match change in upper level.
-- ~~~~~~
-- GAB 8/3/10 v1_00_a
-- ^^^^^^
-- CR570398
-- Routed dlyirq_wren to reset delay timer logic on assertion
-- ~~~~~~
-- GAB 8/12/10 v1_00_a
-- ^^^^^^
-- CR572013
-- Added ability to disable threshold count reset on delay timer timeout in
-- order to match legacy SDMA operation.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
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