content stringlengths 1 1.04M ⌀ |
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4256)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity level_info is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
level: in std_logic_vector(8 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end level_info;
architecture display of level_info is
constant WIDTH: integer := 48;
constant HEIGHT: integer := 8;
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal text_font_addr: std_logic_vector(8 downto 0);
signal number_font_addr: std_logic_vector(8 downto 0);
signal text_enable: std_logic;
signal number_enable: std_logic;
signal bcd: std_logic_vector(3 downto 0);
signal bcd0, bcd1, bcd2: std_logic_vector(3 downto 0);
begin
text_enable <= '1' when (px_x >= 0 and
px_x < WIDTH and
px_y >= 0 and
px_y < HEIGHT) else
'0';
-- +16 and +40 used to right-align the level with score
number_enable <= '1' when (px_x >= WIDTH + 16 and
px_x < WIDTH + 40 and
px_y >= 0 and
px_y < HEIGHT) else
'0';
with px_x(9 downto 3) select
text_font_addr <= "101100000" when "0000000", -- L
"100101000" when "0000001", -- E
"110110000" when "0000010", -- V
"100101000" when "0000011", -- E
"101100000" when "0000100", -- L
"000000000" when others; -- space
bcd <= bcd0 when px_x(9 downto 3) = 10 else
bcd1 when px_x(9 downto 3) = 9 else
bcd2 when px_x(9 downto 3) = 8 else
(others => '0');
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
-- bcd is multiplied by 8 to get the right digit
number_font_addr <= conv_std_logic_vector(128, 9) + (bcd & "000");
font_addr <= px_y(2 downto 0) + text_font_addr when text_enable = '1' else
px_y(2 downto 0) + number_font_addr when number_enable = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
rgb_pixel <= "111" when font_pixel = '1' else "000";
bin_to_bcd:
entity work.bin2bcd(behaviour)
generic map(N_BIN => 9)
port map(
clk => clk, not_reset => not_reset,
binary_in => level,
bcd0 => bcd0, bcd1 => bcd1, bcd2 => bcd2,
bcd3 => open, bcd4 => open
);
codepage:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
end display;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity level_info is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
level: in std_logic_vector(8 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end level_info;
architecture display of level_info is
constant WIDTH: integer := 48;
constant HEIGHT: integer := 8;
signal font_addr: std_logic_vector(8 downto 0);
signal font_data: std_logic_vector(0 to 7);
signal font_pixel: std_logic;
signal text_font_addr: std_logic_vector(8 downto 0);
signal number_font_addr: std_logic_vector(8 downto 0);
signal text_enable: std_logic;
signal number_enable: std_logic;
signal bcd: std_logic_vector(3 downto 0);
signal bcd0, bcd1, bcd2: std_logic_vector(3 downto 0);
begin
text_enable <= '1' when (px_x >= 0 and
px_x < WIDTH and
px_y >= 0 and
px_y < HEIGHT) else
'0';
-- +16 and +40 used to right-align the level with score
number_enable <= '1' when (px_x >= WIDTH + 16 and
px_x < WIDTH + 40 and
px_y >= 0 and
px_y < HEIGHT) else
'0';
with px_x(9 downto 3) select
text_font_addr <= "101100000" when "0000000", -- L
"100101000" when "0000001", -- E
"110110000" when "0000010", -- V
"100101000" when "0000011", -- E
"101100000" when "0000100", -- L
"000000000" when others; -- space
bcd <= bcd0 when px_x(9 downto 3) = 10 else
bcd1 when px_x(9 downto 3) = 9 else
bcd2 when px_x(9 downto 3) = 8 else
(others => '0');
-- numbers start at memory location 128
-- '1' starts at 136, '2' at 144 and so on
-- bcd is multiplied by 8 to get the right digit
number_font_addr <= conv_std_logic_vector(128, 9) + (bcd & "000");
font_addr <= px_y(2 downto 0) + text_font_addr when text_enable = '1' else
px_y(2 downto 0) + number_font_addr when number_enable = '1' else
(others => '0');
font_pixel <= font_data(conv_integer(px_x(2 downto 0)));
rgb_pixel <= "111" when font_pixel = '1' else "000";
bin_to_bcd:
entity work.bin2bcd(behaviour)
generic map(N_BIN => 9)
port map(
clk => clk, not_reset => not_reset,
binary_in => level,
bcd0 => bcd0, bcd1 => bcd1, bcd2 => bcd2,
bcd3 => open, bcd4 => open
);
codepage:
entity work.codepage_rom(content)
port map(addr => font_addr, data => font_data);
end display;
|
------------------------------------------------------------
-- VGA SimuLator projet VHDL
-- Generate RGB colors based on the Pixel-clk
-- Elhamer Oussama abdelkhalek
-- Generate a Pixel color at each Pixel-clk rising edge
-- No control on the count of received Pixel-clk edges
------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity MIRE is
generic ( V_SIZE, H_SIZE : integer);
Port ( Reset : in STD_LOGIC;
Pixel_clk : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (7 downto 0);
G : out STD_LOGIC_VECTOR (7 downto 0);
B : out STD_LOGIC_VECTOR (7 downto 0));
end MIRE;
architecture Behavioral of MIRE is
begin
colors: process (Pixel_clk, Reset)
variable vcount : integer :=0;
variable hcount : integer :=0;
begin
if Reset='1'
then
R <= "11111111" ;
G <= "11111111" ;
B <= "11111111" ;
vcount := 0;
hcount := 0;
elsif (rising_edge(Pixel_clk) and Pixel_clk='1')
then
if(vcount >=0 and vcount < (V_SIZE / 3))
then
if (hcount >=0 and hcount < (H_SIZE /3) )
then
R <= "11111111";
G <= "00000000";
B <= "00000000";
elsif (hcount >=(H_SIZE /3) and hcount <(2 * H_SIZE /3) )
then
R <= "00000000";
G <= "11111111";
B <= "00000000";
elsif (hcount >=(2 * H_SIZE /3) and hcount < H_SIZE )
then
R <= "00000000";
G <= "00000000";
B <= "11111111";
end if;
elsif (vcount >=( V_SIZE / 3) and vcount <( 2 * (V_SIZE / 3)))
then
R <= conv_std_logic_vector((hcount MOD 255),8);
G <= conv_std_logic_vector((hcount MOD 255),8);
B <= conv_std_logic_vector((hcount MOD 255),8);
elsif(vcount >=( 2 * (V_SIZE / 3)) and vcount < V_SIZE)
then
if ((hcount / 5) MOD 2 = 0 and (vcount / 5) MOD 2 = 0 ) or
((hcount / 5) MOD 2 = 1 and (vcount / 5) MOD 2 = 1 )
then
R <= "11111111";
else
R <= "00000000" ;
end if;
if ((hcount / 5) MOD 2 = 0 and (vcount / 5) MOD 2 = 0 ) or
((hcount / 5) MOD 2 = 1 and (vcount / 5) MOD 2 = 1 )
then
G <= "11111111" ;
else
G <= "00000000" ;
end if;
if ((hcount / 5) MOD 2 = 0 and (vcount / 5) MOD 2 = 0 ) or
((hcount / 5) MOD 2 = 1 and (vcount / 5) MOD 2 = 1 )
then
B <= "11111111" ;
else
B <= "00000000" ;
end if;
end if;
if(hcount = (H_SIZE - 1)) then
vcount := (vcount +1) MOD V_SIZE;
end if;
hcount := (hcount +1) MOD H_SIZE;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_121 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_121;
architecture augh of muxb_121 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_121 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_121;
architecture augh of muxb_121 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC Synthesis Working Group,
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number
-- : in vector form
-- : -- > UNRESOLVED_SIGNED: represents a SIGNED number
-- : in vector form
-- : The base element type is type STD_ULOGIC.
-- : Aliases U_UNSIGNED and U_SIGNED are defined for the types
-- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively.
-- : Two numeric subtypes are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The element subtypes are the same subtype as STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body NUMERIC_STD is
-- null range array constants
constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0');
constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
-- =========================Local Subprograms =================================
function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
if ARG >= 0 then
N := ARG;
else
N := -(ARG+1);
end if;
NBITS := 1;
while N > 0 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function SIGNED_NUM_BITS;
function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is
variable NBITS : NATURAL;
variable N : NATURAL;
begin
N := ARG;
NBITS := 1;
while N > 1 loop
NBITS := NBITS+1;
N := N / 2;
end loop;
return NBITS;
end function UNSIGNED_NUM_BITS;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNRESOLVED_UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC)
return UNRESOLVED_UNSIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_UNSIGNED;
-- this internal function computes the addition of two UNRESOLVED_SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC)
return UNRESOLVED_SIGNED
is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R;
variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable CBIT : STD_LOGIC := C;
begin
for I in 0 to L_LEFT loop
RESULT(I) := CBIT xor XL(I) xor XR(I);
CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I));
end loop;
return RESULT;
end function ADD_SIGNED;
-----------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED;
XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is
variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0);
variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1
downto 0);
alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM;
variable TOPBIT : INTEGER;
begin
TEMP := "0"&NUM;
QUOT := (others => '0');
TOPBIT := -1;
for J in DENOM'range loop
if DENOM(J) = '1' then
TOPBIT := J;
exit;
end if;
end loop;
assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero"
severity error;
for J in NUM'length-(TOPBIT+1) downto 0 loop
if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then
TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J))
-("0"&DENOM(TOPBIT downto 0));
QUOT(J) := '1';
end if;
assert TEMP(TOPBIT+J+1) = '0'
report "NUMERIC_STD.DIVMOD: internal error in the division algorithm"
severity error;
end loop;
XQUOT := RESIZE(QUOT, XQUOT'length);
XREMAIN := RESIZE(TEMP, XREMAIN'length);
end procedure DIVMOD;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end function XSLL;
function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT);
end if;
return RESULT;
end function XSRL;
function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT : NATURAL := COUNT;
begin
if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then XCOUNT := ARG_L;
end if;
RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L));
end if;
return RESULT;
end function XSRA;
function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end function XROL;
function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR
is
constant ARG_L : INTEGER := ARG'length-1;
alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM : INTEGER;
begin
COUNTM := COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end function XROR;
-----------------Local Subprograms - Relational ops---------------------------
--
-- General "=" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function UNSIGNED_EQUAL;
--
-- General "=" for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R);
end function SIGNED_EQUAL;
--
-- General "<" for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS;
--
-- General "<" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS;
--
-- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED)
return BOOLEAN is
begin
return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R);
end function UNSIGNED_LESS_OR_EQUAL;
--
-- General "<=" function for UNRESOLVED_SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
-- Need aliases to assure index direction
variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1);
variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1);
begin
INTERN_L := L;
INTERN_R := R;
INTERN_L(0) := not INTERN_L(0);
INTERN_R(0) := not INTERN_R(0);
return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R);
end function SIGNED_LESS_OR_EQUAL;
-- =========================Exported Functions ==========================
-- Id: A.1
function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
begin
if ARG'length < 1 then return NAS;
end if;
RESULT := TO_01(XARG, 'X');
if (RESULT(RESULT'left) = 'X') then return RESULT;
end if;
if RESULT(RESULT'left) = '1' then
RESULT := -RESULT;
end if;
return RESULT;
end function "abs";
-- Id: A.2
function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant ARG_LEFT : INTEGER := ARG'length-1;
variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0);
variable CBIT : STD_LOGIC := '1';
begin
if ARG'length < 1 then return NAS;
end if;
XARG01 := TO_01(ARG, 'X');
if (XARG01(XARG01'left) = 'X') then return XARG01;
end if;
for I in 0 to RESULT'left loop
RESULT(I) := not(XARG01(I)) xor CBIT;
CBIT := CBIT and not(XARG01(I));
end loop;
return RESULT;
end function "-";
-- ============================================================================
-- Id: A.3
function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, R01, '0');
end function "+";
-- Id: A.3R
function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4
function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, R01, '0');
end function "+";
-- Id: A.4R
function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.5
function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L + TO_UNSIGNED(R, L'length);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) + R;
end function "+";
-- Id: A.7
function "+" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L + TO_SIGNED(R, L'length);
end function "+";
-- Id: A.8
function "+" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) + R;
end function "+";
-- ============================================================================
-- Id: A.9
function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_UNSIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.9R
function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED
is
variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10
function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
return ADD_SIGNED(L01, not(R01), '1');
end function "-";
-- Id: A.10R
function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED
is
variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.11
function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L - TO_UNSIGNED(R, L'length);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) - R;
end function "-";
-- Id: A.13
function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
begin
return L - TO_SIGNED(R, L'length);
end function "-";
-- Id: A.14
function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) - R;
end function "-";
-- ============================================================================
-- Id: A.15
function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
return RESULT;
end function "*";
-- Id: A.16
function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) :=
(others => '0');
variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0);
begin
if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS;
end if;
XL := TO_01(L, 'X');
XR := TO_01(R, 'X');
if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then
RESULT := (others => 'X');
return RESULT;
end if;
ADVAL := RESIZE(XR, RESULT'length);
for I in 0 to L_LEFT-1 loop
if XL(I) = '1' then RESULT := RESULT + ADVAL;
end if;
ADVAL := SHIFT_LEFT(ADVAL, 1);
end loop;
if XL(L_LEFT) = '1' then
RESULT := RESULT - ADVAL;
end if;
return RESULT;
end function "*";
-- Id: A.17
function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return L * TO_UNSIGNED(R, L'length);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED(L, R'length) * R;
end function "*";
-- Id: A.19
function "*" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return L * TO_SIGNED(R, L'length);
end function "*";
-- Id: A.20
function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return TO_SIGNED(L, R'length) * R;
end function "*";
-- ============================================================================
-- Id: A.21
function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return FQUOT;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FQUOT;
end function "/";
-- Id: A.22
function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable QNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FQUOT := (others => 'X');
return UNRESOLVED_SIGNED(FQUOT);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
QNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
QNEG := not QNEG;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if QNEG then FQUOT := "0"-FQUOT;
end if;
return UNRESOLVED_SIGNED(FQUOT);
end function "/";
-- Id: A.23
function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- Id: A.25
function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
if (R_LENGTH > L'length) then
QUOT := (others => '0');
return RESIZE(QUOT, L'length);
end if;
XR := TO_SIGNED(R, R_LENGTH);
QUOT := RESIZE((L / XR), QUOT'length);
return RESIZE(QUOT, L'length);
end function "/";
-- Id: A.26
function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
QUOT := RESIZE((XL / R), QUOT'length);
if L_LENGTH > R'length and QUOT(0) /= 'X'
and QUOT(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => QUOT(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated"
severity warning;
end if;
return RESIZE(QUOT, R'length);
end function "/";
-- ============================================================================
-- Id: A.27
function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "rem";
-- Id: A.28
function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X'));
XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X'));
if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XNUM(XNUM'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM));
RNEG := true;
else
XNUM := UNRESOLVED_UNSIGNED(XNUM);
end if;
if XDENOM(XDENOM'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM));
else
XDENOM := UNRESOLVED_UNSIGNED(XDENOM);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG then
FREMAIN := "0"-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "rem";
-- Id: A.29
function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := L rem XR;
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := XL rem R;
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- Id: A.31
function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L rem XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "rem";
-- Id: A.32
function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL rem R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "rem";
-- ============================================================================
-- Id: A.33
function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return FREMAIN;
end if;
DIVMOD(XL, XR, FQUOT, FREMAIN);
return FREMAIN;
end function "mod";
-- Id: A.34
function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0);
variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0);
variable RNEG : BOOLEAN := false;
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
XL := TO_01(XXL, 'X');
XR := TO_01(XXR, 'X');
if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then
FREMAIN := (others => 'X');
return UNRESOLVED_SIGNED(FREMAIN);
end if;
if XL(XL'left) = '1' then
XNUM := UNRESOLVED_UNSIGNED(-XL);
else
XNUM := UNRESOLVED_UNSIGNED(XL);
end if;
if XR(XR'left) = '1' then
XDENOM := UNRESOLVED_UNSIGNED(-XR);
RNEG := true;
else
XDENOM := UNRESOLVED_UNSIGNED(XR);
end if;
DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN);
if RNEG and L(L'left) = '1' then
FREMAIN := "0"-FREMAIN;
elsif RNEG and FREMAIN /= "0" then
FREMAIN := FREMAIN-XDENOM;
elsif L(L'left) = '1' and FREMAIN /= "0" then
FREMAIN := XDENOM-FREMAIN;
end if;
return UNRESOLVED_SIGNED(FREMAIN);
end function "mod";
-- Id: A.35
function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAU;
end if;
XR := TO_UNSIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAU;
end if;
XL := TO_UNSIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => '0')
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- Id: A.37
function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED
is
constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R));
variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0);
begin
if (L'length < 1) then return NAS;
end if;
XR := TO_SIGNED(R, R_LENGTH);
XREM := RESIZE((L mod XR), XREM'length);
if R_LENGTH > L'length and XREM(0) /= 'X'
and XREM(R_LENGTH-1 downto L'length)
/= (R_LENGTH-1 downto L'length => XREM(L'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, L'length);
end function "mod";
-- Id: A.38
function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED
is
constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length);
variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0);
begin
if (R'length < 1) then return NAS;
end if;
XL := TO_SIGNED(L, L_LENGTH);
XREM := RESIZE((XL mod R), XREM'length);
if L_LENGTH > R'length and XREM(0) /= 'X'
and XREM(L_LENGTH-1 downto R'length)
/= (L_LENGTH-1 downto R'length => XREM(R'length-1))
then
assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated"
severity warning;
end if;
return RESIZE(XREM, R'length);
end function "mod";
-- ============================================================================
-- Id: A.39
function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.40
function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- Id: A.42
function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'reverse_range loop
if ARG(INDEX) ?= Y then
return INDEX;
end if;
end loop;
return -1;
end function find_rightmost;
-- ============================================================================
-- Id: C.1
function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.2
function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function ">";
-- Id: C.4
function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function ">";
-- Id: C.5
function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function ">";
-- Id: C.6
function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function ">";
-- ============================================================================
-- Id: C.7
function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.8
function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function "<";
-- Id: C.10
function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function "<";
-- Id: C.11
function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function "<";
-- Id: C.12
function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<"": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function "<";
-- ============================================================================
-- Id: C.13
function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.14
function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.16
function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L < 0;
end if;
return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "<=";
-- Id: C.17
function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "<=";
-- Id: C.18
function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L_LEFT < 0) then
assert NO_WARNING
report "NUMERIC_STD.""<="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 < R;
end if;
return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "<=";
-- ============================================================================
-- Id: C.19
function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.20
function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.22
function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return L > 0;
end if;
return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01);
end function ">=";
-- Id: C.23
function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length));
end function ">=";
-- Id: C.24
function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD."">="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return 0 > R;
end if;
return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length));
end function ">=";
-- ============================================================================
-- Id: C.25
function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.26
function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE));
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return false;
end if;
return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01);
end function "=";
-- Id: C.28
function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(L) > R'length then return false;
end if;
return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01);
end function "=";
-- Id: C.29
function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return false;
end if;
return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length));
end function "=";
-- Id: C.30
function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""="": null argument detected, returning FALSE"
severity warning;
return false;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
if SIGNED_NUM_BITS(R) > L'length then return false;
end if;
return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length));
end function "=";
-- ============================================================================
-- Id: C.31
function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.32
function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
R01 := TO_01(XR, 'X');
if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)));
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.34
function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is
constant R_LEFT : INTEGER := R'length-1;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0);
begin
if (R'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
R01 := TO_01(XR, 'X');
if (R01(R01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(L) > R'length then return true;
end if;
return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01));
end function "/=";
-- Id: C.35
function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if UNSIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)));
end function "/=";
-- Id: C.36
function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is
constant L_LEFT : INTEGER := L'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0);
begin
if (L'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.""/="": null argument detected, returning TRUE"
severity warning;
return true;
end if;
L01 := TO_01(XL, 'X');
if (L01(L01'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
if SIGNED_NUM_BITS(R) > L'length then return true;
end if;
return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)));
end function "/=";
-- ============================================================================
-- Id: C.37
function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.38
function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- ============================================================================
-- Id: C.43
function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if UNSIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.44
function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if SIGNED_LESS(L01, R01) then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER)
return UNRESOLVED_SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
-- ============================================================================
-- Id: C.49
function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.50
function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L > R then
return '1';
else
return '0';
end if;
end if;
end function "?>";
-- Id: C.51
function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.52
function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?> R;
end function "?>";
-- Id: C.53
function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?> TO_UNSIGNED(R, L'length);
end function "?>";
-- Id: C.54
function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?> TO_SIGNED(R, L'length);
end function "?>";
-- ============================================================================
-- Id: C.55
function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.56
function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L < R then
return '1';
else
return '0';
end if;
end if;
end function "?<";
-- Id: C.57
function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.58
function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?< R;
end function "?<";
-- Id: C.59
function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?< TO_UNSIGNED(R, L'length);
end function "?<";
-- Id: C.60
function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?< TO_SIGNED(R, L'length);
end function "?<";
-- ============================================================================
-- Id: C.61
function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.62
function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L <= R then
return '1';
else
return '0';
end if;
end if;
end function "?<=";
-- Id: C.63
function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.64
function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?<= R;
end function "?<=";
-- Id: C.65
function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?<= TO_UNSIGNED(R, L'length);
end function "?<=";
-- Id: C.66
function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?<= TO_SIGNED(R, L'length);
end function "?<=";
-- ============================================================================
-- Id: C.67
function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.68
function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if IS_X(L) or IS_X(R) then
return 'X';
elsif L >= R then
return '1';
else
return '0';
end if;
end if;
end function "?>=";
-- Id: C.69
function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.70
function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?>= R;
end function "?>=";
-- Id: C.71
function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?>= TO_UNSIGNED(R, L'length);
end function "?>=";
-- Id: C.72
function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?>= TO_SIGNED(R, L'length);
end function "?>=";
-- ============================================================================
-- Id: C.73
function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.74
function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := LX(i) ?= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function "?=";
-- Id: C.75
function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.76
function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?= R;
end function "?=";
-- Id: C.77
function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?= TO_UNSIGNED(R, L'length);
end function "?=";
-- Id: C.78
function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?= TO_SIGNED(R, L'length);
end function "?=";
-- ============================================================================
-- Id: C.79
function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.80
function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L;
alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'length, R'length);
variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := LX(i) ?/= RX(i);
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function "?/=";
-- Id: C.81
function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return TO_UNSIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.82
function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return TO_SIGNED(L, R'length) ?/= R;
end function "?/=";
-- Id: C.83
function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return L ?/= TO_UNSIGNED(R, L'length);
end function "?/=";
-- Id: C.84
function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return L ?/= TO_SIGNED(R, L'length);
end function "?/=";
-- ============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- Id: S.3
function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.4
function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT));
end function SHIFT_RIGHT;
-- ============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
if (ARG'length < 1) then return NAU;
end if;
return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- Id: S.7
function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.8
function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL)
return UNRESOLVED_SIGNED is
begin
if (ARG'length < 1) then return NAS;
end if;
return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT));
end function ROTATE_RIGHT;
-- ============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER)
return UNRESOLVED_UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER)
return UNRESOLVED_SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- ============================================================================
-- Id: D.1
function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0);
variable RESULT : NATURAL := 0;
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(XXARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
for I in XARG'range loop
RESULT := RESULT+RESULT;
if XARG(I) = '1' then
RESULT := RESULT + 1;
end if;
end loop;
return RESULT;
end function TO_INTEGER;
-- Id: D.2
function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is
variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0);
begin
if (ARG'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: null detected, returning 0"
severity warning;
return 0;
end if;
XARG := TO_01(ARG, 'X');
if (XARG(XARG'left) = 'X') then
assert NO_WARNING
report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if XARG(XARG'left) = '0' then
return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG));
else
return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1);
end if;
end function TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0);
variable I_VAL : NATURAL := ARG;
begin
if (SIZE < 1) then return NAU;
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
if not(I_VAL = 0) then
assert NO_WARNING
report "NUMERIC_STD.TO_UNSIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0);
variable B_VAL : STD_LOGIC := '0';
variable I_VAL : INTEGER := ARG;
begin
if (SIZE < 1) then return NAS;
end if;
if (ARG < 0) then
B_VAL := '1';
I_VAL := -(ARG+1);
end if;
for I in 0 to RESULT'left loop
if (I_VAL mod 2) = 0 then
RESULT(I) := B_VAL;
else
RESULT(I) := not B_VAL;
end if;
I_VAL := I_VAL/2;
end loop;
if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then
assert NO_WARNING
report "NUMERIC_STD.TO_SIGNED: vector truncated"
severity warning;
end if;
return RESULT;
end function TO_SIGNED;
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
-- ============================================================================
-- Id: R.1
function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_SIGNED
is
alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG;
variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'length = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'left));
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end function RESIZE;
-- Id: R.2
function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL)
return UNRESOLVED_UNSIGNED
is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) :=
(others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'length = 0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- ============================================================================
-- Id: L.1
function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.2
function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.3
function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.4
function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.5
function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.6
function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.8
function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L)));
return RESULT;
end function "not";
-- Id: L.9
function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R));
return RESULT;
end function "and";
-- Id: L.10
function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R));
return RESULT;
end function "or";
-- Id: L.11
function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nand";
-- Id: L.12
function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "nor";
-- Id: L.13
function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0);
begin
RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor
STD_ULOGIC_VECTOR(R));
return RESULT;
end function "xnor";
-- Id: L.15
function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.16
function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.17
function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.18
function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.19
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.20
function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.21
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.22
function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.23
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.24
function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.25
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.26
function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
-- Id: L.27
function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R));
end function "and";
-- Id: L.28
function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R);
end function "and";
-- Id: L.29
function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R));
end function "or";
-- Id: L.30
function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R);
end function "or";
-- Id: L.31
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R));
end function "nand";
-- Id: L.32
function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R);
end function "nand";
-- Id: L.33
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R));
end function "nor";
-- Id: L.34
function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R);
end function "nor";
-- Id: L.35
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R));
end function "xor";
-- Id: L.36
function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R);
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.37
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.38
function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R);
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.39
function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.40
function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return and (STD_ULOGIC_VECTOR (L));
end function "and";
------------------------------------------------------------------------------
-- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.41
function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.42
function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nand (STD_ULOGIC_VECTOR (L));
end function "nand";
------------------------------------------------------------------------------
-- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.43
function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.44
function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return or (STD_ULOGIC_VECTOR (L));
end function "or";
------------------------------------------------------------------------------
-- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.45
function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.46
function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return nor (STD_ULOGIC_VECTOR (L));
end function "nor";
------------------------------------------------------------------------------
-- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.47
function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.48
function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xor (STD_ULOGIC_VECTOR (L));
end function "xor";
------------------------------------------------------------------------------
-- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.49
function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
------------------------------------------------------------------------------
-- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from
-- 1987 through 2002. Comment out the function (declaration and body) for
-- compatibility with these editions.
------------------------------------------------------------------------------
-- Id: L.50
function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is
begin
return xnor (STD_ULOGIC_VECTOR (L));
end function "xnor";
-- ============================================================================
-- support constants for STD_MATCH:
type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN;
constant MATCH_TABLE : BOOLEAN_TABLE := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(false, false, false, false, false, false, false, false, true), -- | U |
(false, false, false, false, false, false, false, false, true), -- | X |
(false, false, true, false, false, false, true, false, true), -- | 0 |
(false, false, false, true, false, false, false, true, true), -- | 1 |
(false, false, false, false, false, false, false, false, true), -- | Z |
(false, false, false, false, false, false, false, false, true), -- | W |
(false, false, true, false, false, false, true, false, true), -- | L |
(false, false, false, true, false, false, false, true, true), -- | H |
(true, true, true, true, true, true, true, true, true) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is
begin
return MATCH_TABLE(L, R);
end function STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is
alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.3
function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is
alias LV : UNRESOLVED_SIGNED(1 to L'length) is L;
alias RV : UNRESOLVED_SIGNED(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- Id: M.5
function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L;
alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R;
begin
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE"
severity warning;
return false;
end if;
if LV'length /= RV'length then
assert NO_WARNING
report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE"
severity warning;
return false;
else
for I in LV'low to LV'high loop
if not (MATCH_TABLE(LV(I), RV(I))) then
return false;
end if;
end loop;
return true;
end if;
end function STD_MATCH;
-- ============================================================================
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0, 1, H, L).
-- Id: T.1
function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_UNSIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAU"
severity warning;
return NAU;
end if;
return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.2
function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0')
return UNRESOLVED_SIGNED is
begin
if (S'length < 1) then
assert NO_WARNING
report "NUMERIC_STD.TO_01: null detected, returning NAS"
severity warning;
return NAS;
end if;
return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP));
end function TO_01;
-- Id: T.3
function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.4
function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S)));
end function TO_X01;
-- Id: T.5
function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.6
function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S)));
end function TO_X01Z;
-- Id: T.7
function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.8
function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S)));
end function TO_UX01;
-- Id: T.9
function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- Id: T.10
function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is
begin
return IS_X(STD_ULOGIC_VECTOR(S));
end function IS_X;
-- ============================================================================
-- string conversion and write operations
-- ============================================================================
function TO_OSTRING (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return TO_OSTRING(STD_ULOGIC_VECTOR (value));
end function TO_OSTRING;
function TO_OSTRING (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return TO_OSTRING(pad & STD_ULOGIC_VECTOR (value));
end function TO_OSTRING;
function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is
begin
return to_hstring(STD_ULOGIC_VECTOR (value));
end function to_hstring;
function to_hstring (value : UNRESOLVED_SIGNED) return STRING is
constant result_length : INTEGER := (value'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 -
value'length))
:= (others => value (value'left)); -- Extend sign bit
begin
return to_hstring(pad & STD_ULOGIC_VECTOR (value));
end function to_hstring;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
WRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1)
:= (others => VALUE (VALUE'left));
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
OWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable ivalue : STD_ULOGIC_VECTOR(VALUE'range);
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - VALUE'length) - 1)
:= (others => VALUE(VALUE'left));
begin
ivalue := STD_ULOGIC_VECTOR (VALUE);
HWRITE (L => L,
VALUE => pad & ivalue,
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
end package body NUMERIC_STD;
|
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: CONTROL **
-- ** Creacion: Julio 07 **
-- ** Por: Mauricio Guerrero H. **
-- ** Revisión: Marzo 08 **
-- ** Conjunto de Instrucciones **
-- ** Por: Mauricio Guerrero H. **
-- ** Diego Mendez Chaves **
-- ***********************************************
-- Descripcion: CLK| |Rst_n
-- ______|____|___________________
-- | _________ __________ |
-- HRI-->|-->| | | | |
-- INST(7..3)-->|-->| OPCODE |-->|Dir_H | |
-- | |_________| | MEMORIA |->|-> Uinst
-- | _________ | uINST | |
-- uDIR(2..0)-->|-->| uPC |-->| Dir_L | |
-- | |_________| |__________| |
-- | ´|` |
-- | _|_______ | |
-- COND-->|-->| EVAL | |
-- FLAGS-->|-->|_SALTOS__| |
-- (C,N,Z,P,INT)|_______________________________|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- UNIDAD DE CONTROL MG
entity ctrl is
Port ( clk : in std_logic;
rst_n : in std_logic;
urst_n : in std_logic;
HRI : in std_logic;
INST : in std_logic_vector(4 downto 0);
C : in std_logic;
Z : in std_logic;
N : in std_logic;
P : in std_logic;
INT : in std_logic;
COND : in std_logic_vector(2 downto 0);
DIR : in std_logic_vector(2 downto 0);
UI : out std_logic_vector(24 downto 0));
end ctrl;
architecture Behavioral of ctrl is
signal load : std_logic;
signal uaddr: std_logic_vector(7 downto 0);
begin
RI: process(clk)
begin
if (clk'event and clk = '1') then
if rst_n = '0' then
uaddr(7 downto 3) <= (others => '0');
elsif HRI = '1' then
uaddr(7 downto 3) <= INST;
elsif urst_n = '0' then
uaddr(7 downto 3) <= (others => '0');
end if;
end if;
end process;
CONT: process(clk)
begin
if (clk'event and clk = '1') then
if rst_n = '0' or urst_n = '0' or HRI = '1' then
uaddr(2 downto 0) <= (others => '0');
elsif load = '1' then
uaddr(2 downto 0) <= DIR;
else
uaddr(2 downto 0) <= uaddr(2 downto 0) + 1;
end if;
end if;
end process;
EVS: process(C,Z,N,P,INT,COND)
begin
case cond is
when "000" => load <= '0';
when "001" => load <= '1';
when "010" => load <= Z;
when "011" => load <= N;
when "100" => load <= C;
when "101" => load <= P;
when "110" => load <= INT;
when others => load <= '0';
end case;
end process;
MUI: process(uaddr)
begin
case uaddr is
-- HF BUSB(3) SELOP(3) DESP(2) BUSC(3) HR MAR MBR RW IOM HRI RUPC COND(3) OFFS(3)
-- FETCH
when "00000000" => UI <= "000100000XXX0100001110100"; -- JINT 100 (MAR=SP)
when "00000001" => UI <= "000000000XXX0100101000XXX"; -- MAR = PC,RD MREQ
when "00000010" => UI <= "0000110000001000101000XXX"; -- PC= PC+1,RD MREQ
when "00000011" => UI <= "0000000000000010110000XXX"; -- MDR=DEX, INST=MDR, RD MREQ
-- Reset UPC
-- INT
when "00000100" => UI <= "000000000XXX0011101000XXX"; -- [SP]<-PC,WR MREQ
when "00000101" => UI <= "0001110000011000101000XXX"; -- SP++
when "00000110" => UI <= "010000000XXX0100101000XXX"; -- MAR=vector,RD,MREQ
when "00000111" => UI <= "0000000000001010100000XXX"; -- PC<-[vector],rst upc
--00001 MOV ACC,A
when "00001000" => UI <= "1011000001111000000000XXX"; -- ACC = A , Reset UPC
when "00001001" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00001010" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00001011" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00001100" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00001101" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00001110" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX"; -- Las posiciones no utilizadas
when "00001111" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX"; -- no importan (no existen)
--00010 MOV A,ACC
when "00010000" => UI <= "1111000000111000000000000"; -- PC = ACC, Reset UPC
when "00010001" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00010010" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00010011" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00010100" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00010101" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00010110" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "00010111" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
--00011 MOV ACC,CTE
when "00011000" => UI <= "000000000XXX0100101000XXX"; -- MAR = PC, RD MREQ
when "00011001" => UI <= "0000110000001000101000XXX"; -- PC = PC + 1, RD MREQ
when "00011010" => UI <= "0000000001111010100000XXX"; -- ACC = DATA, RD MREQ, Reset UPC
when "00011011" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
--00100 MOV ACC,[DPTR]
when "00100000" => UI <= "001000000XXX0100101000XXX"; -- MAR = DPTR, RD MREQ
when "00100001" => UI <= "0XXXXXXXX1111010100000XXX"; -- MDR=DEX,RD MREQ,ACC=MDR,RST UPC
when "00100010" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
--00101 MOV DPTR,ACC
when "00101000" => UI <= "1111000000101000000000XXX"; -- DPTR = ACC , Reset UPC
when "00101001" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 00110 MOV [DPTR],ACC
when "00110000" => UI <= "001000000XXX0100101000XXX"; -- MAR=DPTR
when "00110001" => UI <= "111100000XXX0011100000XXX"; -- MDR = ACC, WR MREQ, RST UPC
when "00110010" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- BUSB(3) SELOP(3) DESP(2) BUSC(3) HR MAR MBR RW IOM HRI RUPC COND(3) OFFS(3)
-- 00111 INV ACC
when "00111000" => UI <= "1111001001111000000000XXX"; -- ACC = not ACC, Reset UPC
when "00111001" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 01000 AND ACC,A
when "01000000" => UI <= "1011010001111000000000XXX"; -- ACC = ACC and A, Reset UPC
when "01000001" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX"; --
-- 01001 ADD ACC,A
when "01001000" => UI <= "1011101001111000000000XXX"; -- ACC = ACC + A, Reset UPC
when "01001001" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 01010 JMP DIR
when "01010000" => UI <= "000000000XXX0100101000XXX"; -- MAR = PC,RD MREQ
when "01010001" => UI <= "0000110000001000101000XXX"; -- PC= PC+1,RD MREQ
when "01010010" => UI <= "XXXXXXXXX0001010100000XXX"; -- MDR=DEX,RD MREQ,PC=MDR,RST UPC
when "01010011" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 01011 JZ DIR
when "01011000" => UI <= "0XXXXXXXXXXX0000001010010"; -- JZ 010
when "01011001" => UI <= "0000110000001000000000XXX"; -- PC=PC+1;Reset upc
when "01011010" => UI <= "000000000XXX0100101000XXX"; -- MAR = PC,RD MREQ
when "01011011" => UI <= "0XXXXXXXX0001010100000XXX"; -- MDR=DEX,RD MREQ,PC=MDR,RST UPC
when "01011100" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 01100 JN DIR
when "01100000" => UI <= "0XXXXXXXXXXX0000001011010"; -- JN 010
when "01100001" => UI <= "0000110000001000000000XXX"; -- PC=PC+1,Reset upc
when "01100010" => UI <= "000000000XXX0100101000XXX"; -- MAR = PC,RD MREQ
when "01100011" => UI <= "0XXXXXXXX0001010100000XXX"; -- MDR=DEX,RD MREQ,PC=MDR,RST UPC
when "01100100" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 01101 JC DIR
when "01101000" => UI <= "0XXXXXXXXXXX0000001100010"; -- JC 010
when "01101001" => UI <= "0000110000001000000000XXX"; -- PC=PC+1,Reset upc
when "01101010" => UI <= "000000000XXX0100101000XXX"; -- MAR = PC,RD MREQ
when "01101011" => UI <= "0XXXXXXXX0001010100000XXX"; -- MDR=DEX,RD MREQ,PC=MDR,RST UPC
when "01101100" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 01110 CALL DIR
when "01110000" => UI <= "000000000XXX0100101000XXX"; -- MAR = PC
when "01110001" => UI <= "0XXXXXXXX1011010101000XXX"; -- MDR=DEX,RD MREQ,TEMP=DIR
when "01110010" => UI <= "0000110000001000101000XXX"; -- PC= PC+1
when "01110011" => UI <= "000100000XXX0100101000XXX"; -- MAR = SP
when "01110100" => UI <= "000000000XXX0011101000XXX"; -- MDR = PC,WR MREQ,[SP]<-PC
when "01110101" => UI <= "0001110000011000101000XXX"; -- SP= SP+1
when "01110110" => UI <= "0101000000001000000000XXX"; -- PC=temp, rst upc
when "01110111" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
-- 01111 RET
when "01111000" => UI <= "0111000001011000001000XXX"; -- temp=acc
when "01111001" => UI <= "0001000001111000001000XXX"; -- ACC = SP
when "01111010" => UI <= "0110101000011000001000XXX"; -- SP= ACC+(-1)
when "01111011" => UI <= "000100000XXX0100101000XXX"; -- MAR = SP
when "01111100" => UI <= "0XXXXXXXX0001010101000XXX"; -- MDR=DEX,RD MREQ,PC=MDR
when "01111101" => UI <= "0101000001111000000000XXX"; -- ACC = TEMP, RST upc
when "01111110" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when "01111111" => UI <= "XXXXXXXXXXXXXXXXXXXXXXXXX";
when others => UI <= (others => 'X');
end case;
end process;
end Behavioral;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Common functions and types
--
-- Description:
-- -------------------------------------
-- For detailed documentation see below.
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library PoC;
use PoC.my_config.all;
package utils is
-- PoC settings
-- ==========================================================================
constant POC_VERBOSE : boolean := MY_VERBOSE;
-- Environment
-- ==========================================================================
-- Distinguishes simulation from synthesis
constant SIMULATION : boolean; -- deferred constant declaration
-- Type declarations
-- ==========================================================================
--+ Vectors of primitive standard types +++++++++++++++++++++++++++++++++++++
type T_BOOLVEC is array(natural range <>) of boolean;
type T_INTVEC is array(natural range <>) of integer;
type T_NATVEC is array(natural range <>) of natural;
type T_POSVEC is array(natural range <>) of positive;
type T_REALVEC is array(natural range <>) of REAL;
--+ Integer subranges sometimes useful for speeding up simulation ++++++++++
subtype T_INT_8 is integer range -128 to 127;
subtype T_INT_16 is integer range -32768 to 32767;
subtype T_UINT_8 is integer range 0 to 255;
subtype T_UINT_16 is integer range 0 to 65535;
--+ Enums ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Intellectual Property (IP) type
type T_IPSTYLE is (IPSTYLE_HARD, IPSTYLE_SOFT);
-- Bit Order
type T_BIT_ORDER is (LSB_FIRST, MSB_FIRST);
-- Byte Order (Endian)
type T_BYTE_ORDER is (LITTLE_ENDIAN, BIG_ENDIAN);
-- rounding style
type T_ROUNDING_STYLE is (ROUND_TO_NEAREST, ROUND_TO_ZERO, ROUND_TO_INF, ROUND_UP, ROUND_DOWN);
-- define a new unrelated type T_BCD for arithmetic
-- QUESTION: extract to an own BCD package?
-- => overloaded operators for +/-/=/... and conversion functions
type T_BCD is array(3 downto 0) of std_logic;
type T_BCD_VECTOR is array(natural range <>) of T_BCD;
constant C_BCD_MINUS : T_BCD := "1010";
constant C_BCD_OFF : T_BCD := "1011";
subtype byte is std_logic_vector(7 downto 0);
type byte_vector is array(natural range<>) of byte;
-- Function declarations
-- ==========================================================================
--+ Division ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(a / b)
function div_ceil(a : natural; b : positive) return natural;
--+ Power +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- is input a power of 2?
function is_pow2(int : natural) return boolean;
-- round to next power of 2
function ceil_pow2(int : natural) return positive;
-- round to previous power of 2
function floor_pow2(int : natural) return natural;
--+ Logarithm ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Calculates: ceil(ld(arg))
function log2ceil(arg : positive) return natural;
-- Calculates: max(1, ceil(ld(arg)))
function log2ceilnz(arg : positive) return positive;
-- Calculates: ceil(lg(arg))
function log10ceil(arg : positive) return natural;
-- Calculates: max(1, ceil(lg(arg)))
function log10ceilnz(arg : positive) return positive;
--+ if-then-else (ite) +++++++++++++++++++++++++++++++++++++++++++++++++++++
function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean;
function ite(cond : boolean; value1 : integer; value2 : integer) return integer;
function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL;
function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic;
function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector;
function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector;
function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned;
function ite(cond : boolean; value1 : character; value2 : character) return character;
function ite(cond : boolean; value1 : string; value2 : string) return string;
-- conditional increment / decrement
function inc_if(cond : boolean; value : integer; increment : integer := 1) return integer;
function dec_if(cond : boolean; value : integer; decrement : integer := 1) return integer;
--+ Max / Min / Sum ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
function imin(arg1 : integer; arg2 : integer) return integer; -- Calculates: min(arg1, arg2) for integers
alias rmin is IEEE.math_real.realmin[real, real return real];
-- function rmin(arg1 : real; arg2 : real) return real; -- Calculates: min(arg1, arg2) for reals
function imin(vec : T_INTVEC) return integer; -- Calculates: min(vec) for a integer vector
function imin(vec : T_NATVEC) return natural; -- Calculates: min(vec) for a natural vector
function imin(vec : T_POSVEC) return positive; -- Calculates: min(vec) for a positive vector
function rmin(vec : T_REALVEC) return real; -- Calculates: min(vec) of real vector
function imax(arg1 : integer; arg2 : integer) return integer; -- Calculates: max(arg1, arg2) for integers
alias rmax is IEEE.math_real.realmax[real, real return real];
-- function rmax(arg1 : real; arg2 : real) return real; -- Calculates: max(arg1, arg2) for reals
function imax(vec : T_INTVEC) return integer; -- Calculates: max(vec) for a integer vector
function imax(vec : T_NATVEC) return natural; -- Calculates: max(vec) for a natural vector
function imax(vec : T_POSVEC) return positive; -- Calculates: max(vec) for a positive vector
function rmax(vec : T_REALVEC) return real; -- Calculates: max(vec) of real vector
function isum(vec : T_NATVEC) return natural; -- Calculates: sum(vec) for a natural vector
function isum(vec : T_POSVEC) return natural; -- Calculates: sum(vec) for a positive vector
function isum(vec : T_INTVEC) return integer; -- Calculates: sum(vec) of integer vector
function rsum(vec : T_REALVEC) return real; -- Calculates: sum(vec) of real vector
--+ Conversions ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- to integer: to_int
function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer;
function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer;
-- to std_logic: to_sl
function to_sl(Value : boolean) return std_logic;
function to_sl(Value : character) return std_logic;
-- to std_logic_vector: to_slv
function to_slv(Value : natural; Size : positive) return std_logic_vector; -- short for std_logic_vector(to_unsigned(Value, Size))
function to_BCD(Digit : integer) return T_BCD;
function to_BCD(Digit : character) return T_BCD;
function to_BCD(Digit : unsigned) return T_BCD;
function to_BCD(Digit : std_logic_vector) return T_BCD;
function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR;
function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR;
-- TODO: comment
function to_index(slv : unsigned; max : natural := 0) return integer;
function to_index(slv : std_logic_vector; max : natural := 0) return integer;
-- is_*
function is_sl(c : character) return boolean;
--+ Basic Vector Utilities +++++++++++++++++++++++++++++++++++++++++++++++++
-- Aggregate functions
function slv_or (vec : std_logic_vector) return std_logic;
function slv_nor (vec : std_logic_vector) return std_logic;
function slv_and (vec : std_logic_vector) return std_logic;
function slv_nand(vec : std_logic_vector) return std_logic;
function slv_xor (vec : std_logic_vector) return std_logic;
-- NO slv_xnor! This operation would not be well-defined as
-- not xor(vec) /= vec_{n-1} xnor ... xnor vec_1 xnor vec_0 iff n is odd.
-- Reverses the elements of the passed Vector.
--
-- @synthesis supported
--
function reverse(vec : std_logic_vector) return std_logic_vector;
function reverse(vec : bit_vector) return bit_vector;
function reverse(vec : unsigned) return unsigned;
-- scale a value into a range [Minimum, Maximum]
function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer;
function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL;
-- Resizes the vector to the specified length. The adjustment is make on
-- on the 'high end of the vector. The 'low index remains as in the argument.
-- If the result vector is larger, the extension uses the provided fill value
-- (default: '0').
-- Use the resize functions of the numeric_std package for value-preserving
-- resizes of the signed and unsigned data types.
--
-- @synthesis supported
--
function resize(vec : bit_vector; length : natural; fill : bit := '0')
return bit_vector;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0')
return std_logic_vector;
-- Shift the index range of a vector by the specified offset.
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector;
-- Shift the index range of a vector making vec'low = 0.
function movez(vec : std_logic_vector) return std_logic_vector;
function ascend(vec : std_logic_vector) return std_logic_vector;
function descend(vec : std_logic_vector) return std_logic_vector;
-- Least-Significant Set Bit (lssb):
-- Computes a vector of the same length as the argument with
-- at most one bit set at the rightmost '1' found in arg.
--
-- @synthesis supported
--
function lssb(arg : std_logic_vector) return std_logic_vector;
function lssb(arg : bit_vector) return bit_vector;
-- Returns the index of the least-significant set bit.
--
-- @synthesis supported
--
function lssb_idx(arg : std_logic_vector) return integer;
function lssb_idx(arg : bit_vector) return integer;
-- Most-Significant Set Bit (mssb): computes a vector of the same length
-- with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector;
function mssb(arg : bit_vector) return bit_vector;
function mssb_idx(arg : std_logic_vector) return integer;
function mssb_idx(arg : bit_vector) return integer;
-- Swap sub vectors in vector (endian reversal)
function swap(slv : std_logic_vector; Size : positive) return std_logic_vector;
-- generate bit masks
function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector;
function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector;
function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector;
--+ Encodings ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- One-Hot-Code to Binary-Code.
-- If a non-negative value empty_val is specified, its unsigned
-- representation will be returned upon an all-zero input. As a consequence
-- of specifying this value, no simulation warnings will be issued upon empty
-- inputs. Alleged 1-hot-encoded inputs with more than one bit asserted
-- will always raise a simulation warning.
function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned;
-- Converts Gray-Code into Binary-Code.
--
-- @synthesis supported
--
function gray2bin (gray_val : std_logic_vector) return std_logic_vector;
-- Binary-Code to One-Hot-Code
function bin2onehot(value : std_logic_vector) return std_logic_vector;
-- Binary-Code to Gray-Code
function bin2gray(value : std_logic_vector) return std_logic_vector;
end package;
package body utils is
-- Environment
-- ==========================================================================
function is_simulation return boolean is
variable ret : boolean;
begin
ret := false;
-- WORKAROUND: for Xilinx ISE
-- Version: all versions with enabled 'use_new_parser' option
-- Issue: Is_X('X') does not evaluate to FALSE in synthesis
-- Solution: Use '--synthesis translate_on/off' pragmas
--synthesis translate_off
if Is_X('X') then ret := true; end if;
--synthesis translate_on
return ret;
end function;
-- deferred constant assignment
constant SIMULATION : boolean := is_simulation;
-- Divisions: div_*
-- ===========================================================================
-- integer division; always round-up
function div_ceil(a : natural; b : positive) return natural is -- calculates: ceil(a / b)
begin
return (a + (b - 1)) / b;
end function;
-- Power functions: *_pow2
-- ==========================================================================
-- return TRUE, if input is a power of 2
function is_pow2(int : natural) return boolean is
begin
return ceil_pow2(int) = int;
end function;
-- round to next power of 2
function ceil_pow2(int : natural) return positive is
begin
return 2 ** log2ceil(int);
end function;
-- round to previous power of 2
function floor_pow2(int : natural) return natural is
variable temp : unsigned(30 downto 0);
begin
temp := to_unsigned(int, 31);
for i in temp'range loop
if (temp(i) = '1') then
return 2 ** i;
end if;
end loop;
return 0;
end function;
-- Logarithms: log*ceil*
-- ==========================================================================
-- return log2; always rounded up
function log2ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 2;
log := log + 1;
end loop;
return log;
end function;
-- return log2; always rounded up; the return value is >= 1
function log2ceilnz(arg : positive) return positive is
begin
return imax(1, log2ceil(arg));
end function;
-- return log10; always rounded up
function log10ceil(arg : positive) return natural is
variable tmp : positive;
variable log : natural;
begin
if arg = 1 then return 0; end if;
tmp := 1;
log := 0;
while arg > tmp loop
tmp := tmp * 10;
log := log + 1;
end loop;
return log;
end function;
-- return log2; always rounded up; the return value is >= 1
function log10ceilnz(arg : positive) return positive is
begin
return imax(1, log10ceil(arg));
end function;
-- if-then-else (ite)
-- ==========================================================================
function ite(cond : boolean; value1 : boolean; value2 : boolean) return boolean is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : integer; value2 : integer) return integer is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : REAL; value2 : REAL) return REAL is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : std_logic; value2 : std_logic) return std_logic is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : std_logic_vector; value2 : std_logic_vector) return std_logic_vector is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : bit_vector; value2 : bit_vector) return bit_vector is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : unsigned; value2 : unsigned) return unsigned is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : character; value2 : character) return character is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
function ite(cond : boolean; value1 : string; value2 : string) return string is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
-- conditional increment / decrement
-- ===========================================================================
-- return the by increment incremented Value if cond is true else passthrough Value
function inc_if(cond : boolean; Value : integer; increment : integer := 1) return integer is
begin
if cond then
return Value + increment;
else
return Value;
end if;
end function;
-- return the by decrement decremented Value if cond is true else passthrough Value
function dec_if(cond : boolean; Value : integer; decrement : integer := 1) return integer is
begin
if cond then
return Value - decrement;
else
return Value;
end if;
end function;
-- *min / *max / *sum
-- ===========================================================================
function imin(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 < arg2 then return arg1; end if;
return arg2;
end function;
-- function rmin(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 < arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imin(vec : T_INTVEC) return integer is
variable Result : integer;
begin
Result := integer'high;
for i in vec'range loop
if (vec(i) < Result) then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imin(vec : T_NATVEC) return natural is
variable Result : natural;
begin
Result := natural'high;
for i in vec'range loop
if (vec(i) < Result) then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imin(vec : T_POSVEC) return positive is
variable Result : positive;
begin
Result := positive'high;
for i in vec'range loop
if (vec(i) < Result) then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function rmin(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'high;
for i in vec'range loop
if vec(i) < Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(arg1 : integer; arg2 : integer) return integer is
begin
if arg1 > arg2 then return arg1; end if;
return arg2;
end function;
-- function rmax(arg1 : real; arg2 : real) return real is
-- begin
-- if arg1 > arg2 then return arg1; end if;
-- return arg2;
-- end function;
function imax(vec : T_INTVEC) return integer is
variable Result : integer;
begin
Result := integer'low;
for i in vec'range loop
if (vec(i) > Result) then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(vec : T_NATVEC) return natural is
variable Result : natural;
begin
Result := natural'low;
for i in vec'range loop
if (vec(i) > Result) then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function imax(vec : T_POSVEC) return positive is
variable Result : positive;
begin
Result := positive'low;
for i in vec'range loop
if (vec(i) > Result) then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function rmax(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := REAL'low;
for i in vec'range loop
if vec(i) > Result then
Result := vec(i);
end if;
end loop;
return Result;
end function;
function isum(vec : T_INTVEC) return integer is
variable Result : integer;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function isum(vec : T_NATVEC) return natural is
variable Result : natural;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function isum(vec : T_POSVEC) return natural is
variable Result : natural;
begin
Result := 0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
function rsum(vec : T_REALVEC) return REAL is
variable Result : REAL;
begin
Result := 0.0;
for i in vec'range loop
Result := Result + vec(i);
end loop;
return Result;
end function;
-- Vector aggregate functions: slv_*
-- ==========================================================================
function slv_or(vec : std_logic_vector) return std_logic is
variable Result : std_logic;
begin
Result := '0';
for i in vec'range loop
Result := Result or vec(i);
end loop;
return Result;
end function;
function slv_nor(vec : std_logic_vector) return std_logic is
begin
return not slv_or(vec);
end function;
function slv_and(vec : std_logic_vector) return std_logic is
variable Result : std_logic;
begin
Result := '1';
for i in vec'range loop
Result := Result and vec(i);
end loop;
return Result;
end function;
function slv_nand(vec : std_logic_vector) return std_logic is
begin
return not slv_and(vec);
end function;
function slv_xor(vec : std_logic_vector) return std_logic is
variable res : std_logic;
begin
res := '0';
for i in vec'range loop
res := res xor vec(i);
end loop;
return res;
end function;
-- ===========================================================================
-- Type conversion
-- ===========================================================================
-- Convert to integer: to_int
function to_int(bool : boolean; zero : integer := 0; one : integer := 1) return integer is
begin
return ite(bool, one, zero);
end function;
function to_int(sl : std_logic; zero : integer := 0; one : integer := 1) return integer is
begin
if (sl = '1') then
return one;
end if;
return zero;
end function;
-- Convert to bit: to_sl
-- ===========================================================================
function to_sl(Value : boolean) return std_logic is
begin
return ite(Value, '1', '0');
end function;
function to_sl(Value : character) return std_logic is
begin
case Value is
when 'U' => return 'U';
when '0' => return '0';
when '1' => return '1';
when 'Z' => return 'Z';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when '-' => return '-';
when others => return 'X';
end case;
end function;
-- Convert to vector: to_slv
-- ===========================================================================
-- short for std_logic_vector(to_unsigned(Value, Size))
-- the return value is guaranteed to have the range (Size-1 downto 0)
function to_slv(Value : natural; Size : positive) return std_logic_vector is
constant res : std_logic_vector(Size-1 downto 0) := std_logic_vector(to_unsigned(Value, Size));
begin
return res;
end function;
-- Convert to T_BCD or T_BCD_VECTOR: to_BCD*
-- ===========================================================================
function to_BCD(Digit : integer) return T_BCD is
begin
return T_BCD(to_unsigned(Digit, T_BCD'length));
end function;
function to_BCD(Digit : character) return T_BCD is
begin
return T_BCD(to_unsigned((character'pos(Digit) - CHARACTER'pos('0')), T_BCD'length));
end function;
function to_BCD(Digit : unsigned) return T_BCD is
begin
return T_BCD(Digit);
end function;
function to_BCD(Digit : std_logic_vector) return T_BCD is
begin
return T_BCD(Digit);
end function;
function to_BCD_Vector(Value : integer; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is
begin
return to_BCD_Vector(integer'image(Value), Size, Fill);
end function;
function to_BCD_Vector(Value : string; Size : natural := 0; Fill : T_BCD := x"0") return T_BCD_VECTOR is
variable Result : T_BCD_VECTOR(Size - 1 downto 0);
begin
Result := (others => Fill);
for i in Value'range loop
Result(Value'length - (i - Value'low) - 1) := to_BCD(Value(i));
end loop;
return Result;
end function;
-- bound array indices for simulation, to prevent out of range errors
function to_index(slv : unsigned; max : natural := 0) return integer is
variable res : integer;
begin
if (slv'length = 0) then return 0; end if;
res := to_integer(slv);
if SIMULATION and max > 0 then
res := imin(res, max);
end if;
return res;
end function;
-- bound array indices for simulation, to prevent out of range errors
function to_index(slv : std_logic_vector; max : natural := 0) return integer is
begin
return to_index(unsigned(slv), max);
end function;
-- is_*
-- ===========================================================================
function is_sl(c : character) return boolean is
begin
case c is
when 'U'|'X'|'0'|'1'|'Z'|'W'|'L'|'H'|'-' => return true;
when others => return false;
end case;
end function;
-- Reverse vector elements
function reverse(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high-i)) := vec(i);
end loop;
return res;
end function;
function reverse(vec : bit_vector) return bit_vector is
variable res : bit_vector(vec'range);
begin
res := to_bitvector(reverse(to_stdlogicvector(vec)));
return res;
end function;
function reverse(vec : unsigned) return unsigned is
begin
return unsigned(reverse(std_logic_vector(vec)));
end function;
-- Swap sub vectors in vector
-- ==========================================================================
function swap(slv : std_logic_vector; Size : positive) return std_logic_vector is
constant SegmentCount : natural := slv'length / Size;
variable FromH : natural;
variable FromL : natural;
variable ToH : natural;
variable ToL : natural;
variable Result : std_logic_vector(slv'length - 1 downto 0);
begin
for i in 0 to SegmentCount - 1 loop
FromH := ((i + 1) * Size) - 1;
FromL := i * Size;
ToH := ((SegmentCount - i) * Size) - 1;
ToL := (SegmentCount - i - 1) * Size;
Result(ToH downto ToL) := slv(FromH downto FromL);
end loop;
return Result;
end function;
-- generate bit masks
-- ==========================================================================
function genmask_high(Bits : natural; MaskLength : positive) return std_logic_vector is
begin
if (Bits = 0) then
return (MaskLength - 1 downto 0 => '0');
else
return (MaskLength - 1 downto MaskLength - Bits + 1 => '1') & (MaskLength - Bits downto 0 => '0');
end if;
end function;
function genmask_low(Bits : natural; MaskLength : positive) return std_logic_vector is
begin
if (Bits = 0) then
return (MaskLength - 1 downto 0 => '0');
else
return (MaskLength - 1 downto Bits => '0') & (Bits - 1 downto 0 => '1');
end if;
end function;
function genmask_alternate(len : positive; lsb : std_logic := '0') return std_logic_vector is
variable curr : std_logic;
variable res : std_logic_vector(len-1 downto 0);
begin
curr := lsb;
for i in res'reverse_range loop
res(i) := curr;
curr := not curr;
end loop;
return res;
end function;
-- binary encoding conversion functions
-- ==========================================================================
-- One-Hot-Code to Binary-Code
function onehot2bin(onehot : std_logic_vector; empty_val : integer := -1) return unsigned is
variable res : unsigned(log2ceilnz(imax(onehot'high, empty_val)+1)-1 downto 0);
variable chk : natural;
begin
-- Note: empty_val = 0 takes the regular path to reduce on synthesized hardware
if empty_val > 0 and onehot = (onehot'range => '0') then
res := to_unsigned(empty_val, res'length);
else
res := (others => '0');
chk := 0;
for i in onehot'range loop
if onehot(i) = '1' then
res := res or to_unsigned(i, res'length);
chk := chk + 1;
end if;
end loop;
if SIMULATION and chk /= 1 and (chk > 1 or empty_val < 0) then
report "Broken 1-Hot-Code with "&integer'image(chk)&" bits set."
severity warning;
res := (others => 'X'); -- computed result is implementation-dependant
end if;
end if;
return res;
end function;
-- Gray-Code to Binary-Code
function gray2bin(gray_val : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(gray_val'length downto 0);
variable res : std_logic_vector(gray_val'range);
begin
tmp := '0' & gray_val;
for i in tmp'left-1 downto 0 loop
tmp(i) := tmp(i+1) xor tmp(i);
end loop;
res := tmp(tmp'left-1 downto 0);
return res;
end function;
-- Binary-Code to One-Hot-Code
function bin2onehot(Value : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(2**Value'length - 1 downto 0);
begin
result := (others => '0');
result(to_index(Value, 0)) := '1';
return result;
end function;
-- Binary-Code to Gray-Code
function bin2gray(Value : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(Value'length downto 0);
variable res : std_logic_vector(Value'range);
begin
tmp := ('0' & Value) xor (Value & '0');
res := tmp(Value'length downto 1);
return res;
end function;
-- bit searching / bit indices
-- ==========================================================================
-- Least-Significant Set Bit (lssb): computes a vector of the same length with at most one bit set at the rightmost '1' found in arg.
function lssb(arg : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(arg'range);
begin
res := arg and std_logic_vector(unsigned(not arg)+1);
return res;
end function;
function lssb(arg : bit_vector) return bit_vector is
variable res : bit_vector(arg'range);
begin
res := to_bitvector(lssb(to_stdlogicvector(arg)));
return res;
end function;
-- Most-Significant Set Bit (mssb): computes a vector of the same length with at most one bit set at the leftmost '1' found in arg.
function mssb(arg : std_logic_vector) return std_logic_vector is
begin
return reverse(lssb(reverse(arg)));
end function;
function mssb(arg : bit_vector) return bit_vector is
begin
return reverse(lssb(reverse(arg)));
end function;
-- Index of lssb
function lssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(lssb(arg)));
end function;
function lssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return lssb_idx(slv);
end function;
-- Index of mssb
function mssb_idx(arg : std_logic_vector) return integer is
begin
return to_integer(onehot2bin(mssb(arg)));
end function;
function mssb_idx(arg : bit_vector) return integer is
variable slv : std_logic_vector(arg'range);
begin
slv := to_stdlogicvector(arg);
return mssb_idx(slv);
end function;
-- scale a value into a given range
function scale(Value : integer; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is
begin
return scale(real(Value), Minimum, Maximum, RoundingStyle);
end function;
function scale(Value : REAL; Minimum : integer; Maximum : integer; RoundingStyle : T_ROUNDING_STYLE := ROUND_TO_NEAREST) return integer is
variable Result : REAL;
begin
if (Maximum < Minimum) then
return integer'low;
else
Result := real(Value) * ((real(Maximum) + 0.5) - (real(Minimum) - 0.5)) + (real(Minimum) - 0.5);
case RoundingStyle is
when ROUND_TO_NEAREST => return integer(round(Result));
when ROUND_TO_ZERO => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_TO_INF => report "scale: unsupported RoundingStyle." severity FAILURE;
when ROUND_UP => return integer(ceil(Result));
when ROUND_DOWN => return integer(floor(Result));
when others => report "scale: unsupported RoundingStyle." severity FAILURE;
end case;
end if;
end function;
function scale(Value : REAL; Minimum : REAL; Maximum : REAL) return REAL is
begin
if (Maximum < Minimum) then
return REAL'low;
else
return Value * (Maximum - Minimum) + Minimum;
end if;
end function;
function resize(vec : bit_vector; length : natural; fill : bit := '0') return bit_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : bit_vector(vec'low to high2b);
variable res_dn : bit_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end function;
function resize(vec : std_logic_vector; length : natural; fill : std_logic := '0') return std_logic_vector is
constant high2b : natural := vec'low+length-1;
constant highcp : natural := imin(vec'high, high2b);
variable res_up : std_logic_vector(vec'low to high2b);
variable res_dn : std_logic_vector(high2b downto vec'low);
begin
if vec'ascending then
res_up := (others => fill);
res_up(vec'low to highcp) := vec(vec'low to highcp);
return res_up;
else
res_dn := (others => fill);
res_dn(highcp downto vec'low) := vec(highcp downto vec'low);
return res_dn;
end if;
end function;
-- Move vector boundaries
-- ==========================================================================
function move(vec : std_logic_vector; ofs : integer) return std_logic_vector is
variable res_up : std_logic_vector(vec'low +ofs to vec'high+ofs);
variable res_dn : std_logic_vector(vec'high+ofs downto vec'low +ofs);
begin
if vec'ascending then
res_up := vec;
return res_up;
else
res_dn := vec;
return res_dn;
end if;
end function;
function movez(vec : std_logic_vector) return std_logic_vector is
begin
return move(vec, -vec'low);
end function;
function ascend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'low to vec'high);
begin
res := vec;
return res;
end function;
function descend(vec : std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(vec'high downto vec'low);
begin
res := vec;
return res;
end function;
end package body;
|
library ieee;
use ieee.std_logic_1164.all;
entity fp is port
(
l,r : in std_logic_vector(1 to 32);
pt : out std_logic_vector(1 to 64)
);
end fp;
architecture behaviour of fp is
begin
pt(1)<=r(8); pt(2)<=l(8); pt(3)<=r(16);pt(4)<=l(16);pt(5)<=r(24);pt(6)<=l(24); pt(7)<=r(32);pt(8)<=l(32);
pt(9)<=r(7); pt(10)<=l(7);pt(11)<=r(15); pt(12)<=l(15); pt(13)<=r(23); pt(14)<=l(23); pt(15)<=r(31); pt(16)<=l(31);
pt(17)<=r(6);pt(18)<=l(6);pt(19)<=r(14); pt(20)<=l(14); pt(21)<=r(22); pt(22)<=l(22); pt(23)<=r(30); pt(24)<=l(30);
pt(25)<=r(5);pt(26)<=l(5);pt(27)<=r(13); pt(28)<=l(13); pt(29)<=r(21); pt(30)<=l(21); pt(31)<=r(29); pt(32)<=l(29);
pt(33)<=r(4);pt(34)<=l(4);pt(35)<=r(12); pt(36)<=l(12); pt(37)<=r(20); pt(38)<=l(20);pt(39)<=r(28); pt(40)<=l(28);
pt(41)<=r(3);pt(42)<=l(3);pt(43)<=r(11); pt(44)<=l(11); pt(45)<=r(19); pt(46)<=l(19); pt(47)<=r(27); pt(48)<=l(27);
pt(49)<=r(2);pt(50)<=l(2);pt(51)<=r(10); pt(52)<=l(10); pt(53)<=r(18); pt(54)<=l(18); pt(55)<=r(26); pt(56)<=l(26);
pt(57)<=r(1);pt(58)<=l(1);pt(59)<=r(9);pt(60)<=l(9);pt(61)<=r(17); pt(62)<=l(17); pt(63)<=r(25); pt(64)<=l(25);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity fp is port
(
l,r : in std_logic_vector(1 to 32);
pt : out std_logic_vector(1 to 64)
);
end fp;
architecture behaviour of fp is
begin
pt(1)<=r(8); pt(2)<=l(8); pt(3)<=r(16);pt(4)<=l(16);pt(5)<=r(24);pt(6)<=l(24); pt(7)<=r(32);pt(8)<=l(32);
pt(9)<=r(7); pt(10)<=l(7);pt(11)<=r(15); pt(12)<=l(15); pt(13)<=r(23); pt(14)<=l(23); pt(15)<=r(31); pt(16)<=l(31);
pt(17)<=r(6);pt(18)<=l(6);pt(19)<=r(14); pt(20)<=l(14); pt(21)<=r(22); pt(22)<=l(22); pt(23)<=r(30); pt(24)<=l(30);
pt(25)<=r(5);pt(26)<=l(5);pt(27)<=r(13); pt(28)<=l(13); pt(29)<=r(21); pt(30)<=l(21); pt(31)<=r(29); pt(32)<=l(29);
pt(33)<=r(4);pt(34)<=l(4);pt(35)<=r(12); pt(36)<=l(12); pt(37)<=r(20); pt(38)<=l(20);pt(39)<=r(28); pt(40)<=l(28);
pt(41)<=r(3);pt(42)<=l(3);pt(43)<=r(11); pt(44)<=l(11); pt(45)<=r(19); pt(46)<=l(19); pt(47)<=r(27); pt(48)<=l(27);
pt(49)<=r(2);pt(50)<=l(2);pt(51)<=r(10); pt(52)<=l(10); pt(53)<=r(18); pt(54)<=l(18); pt(55)<=r(26); pt(56)<=l(26);
pt(57)<=r(1);pt(58)<=l(1);pt(59)<=r(9);pt(60)<=l(9);pt(61)<=r(17); pt(62)<=l(17); pt(63)<=r(25); pt(64)<=l(25);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc517.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00517pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00517pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00517pkg;
USE work.c03s03b00x00p03n04i00517pkg.ALL;
ENTITY c03s03b00x00p03n04i00517ent IS
END c03s03b00x00p03n04i00517ent;
ARCHITECTURE c03s03b00x00p03n04i00517arch OF c03s03b00x00p03n04i00517ent IS
--
-- Access type declarations
--
TYPE at_scre_1 IS ACCESS t_scre_1 ;
TYPE at_cca1_1 IS ACCESS t_cca1_1 ;
TYPE at_cca1_2 IS ACCESS t_cca1_2 ;
TYPE at_cca1_3 IS ACCESS t_cca1_3 ;
TYPE at_cca1_4 IS ACCESS t_cca1_4 ;
TYPE at_cmre_1 IS ACCESS t_cmre_1 ;
TYPE at_cmre_2 IS ACCESS t_cmre_2 ;
TYPE at_cca1_7 IS ACCESS t_cca1_7 ;
TYPE at_cmre_3 IS ACCESS t_cmre_3 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_scre_1 : at_scre_1 ;
VARIABLE AV2_scre_1 : at_scre_1 ;
VARIABLE AV0_cca1_1 : at_cca1_1 ;
VARIABLE AV2_cca1_1 : at_cca1_1 ;
VARIABLE AV0_cca1_2 : at_cca1_2 ;
VARIABLE AV2_cca1_2 : at_cca1_2 ;
VARIABLE AV0_cca1_3 : at_cca1_3 ;
VARIABLE AV2_cca1_3 : at_cca1_3 ;
VARIABLE AV0_cca1_4 : at_cca1_4 ;
VARIABLE AV2_cca1_4 : at_cca1_4 ;
VARIABLE AV0_cmre_1 : at_cmre_1 ;
VARIABLE AV2_cmre_1 : at_cmre_1 ;
VARIABLE AV0_cmre_2 : at_cmre_2 ;
VARIABLE AV2_cmre_2 : at_cmre_2 ;
VARIABLE AV0_cca1_7 : at_cca1_7 ;
VARIABLE AV2_cca1_7 : at_cca1_7 ;
VARIABLE AV0_cmre_3 : at_cmre_3 ;
VARIABLE AV2_cmre_3 : at_cmre_3 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_scre_1 := NEW t_scre_1 ;
AV0_cca1_1 := NEW t_cca1_1 ;
AV0_cca1_2 := NEW t_cca1_2 ;
AV0_cca1_3 := NEW t_cca1_3 ;
AV0_cca1_4 := NEW t_cca1_4 ;
AV0_cmre_1 := NEW t_cmre_1 ;
AV0_cmre_2 := NEW t_cmre_2 ;
AV0_cca1_7 := NEW t_cca1_7 ;
AV0_cmre_3 := NEW t_cmre_3 ;
---
AV2_scre_1 := NEW t_scre_1 ' ( C2_scre_1 ) ;
AV2_cca1_1 := NEW t_cca1_1 ' ( C2_cca1_1 ) ;
AV2_cca1_2 := NEW t_cca1_2 ' ( C2_cca1_2 ) ;
AV2_cca1_3 := NEW t_cca1_3 ' ( C2_cca1_3 ) ;
AV2_cca1_4 := NEW t_cca1_4 ' ( C2_cca1_4 ) ;
AV2_cmre_1 := NEW t_cmre_1 ' ( C2_cmre_1 ) ;
AV2_cmre_2 := NEW t_cmre_2 ' ( C2_cmre_2 ) ;
AV2_cca1_7 := NEW t_cca1_7 ' ( C2_cca1_7 ) ;
AV2_cmre_3 := NEW t_cmre_3 ' ( C2_cmre_3 ) ;
--
--
ASSERT AV0_scre_1.all = C0_scre_1
REPORT "Improper initialization of AV0_scre_1" SEVERITY FAILURE;
ASSERT AV2_scre_1.all = C2_scre_1
REPORT "Improper initialization of AV2_scre_1" SEVERITY FAILURE;
ASSERT AV0_cca1_1.all = C0_cca1_1
REPORT "Improper initialization of AV0_cca1_1" SEVERITY FAILURE;
ASSERT AV2_cca1_1.all = C2_cca1_1
REPORT "Improper initialization of AV2_cca1_1" SEVERITY FAILURE;
ASSERT AV0_cca1_2.all = C0_cca1_2
REPORT "Improper initialization of AV0_cca1_2" SEVERITY FAILURE;
ASSERT AV2_cca1_2.all = C2_cca1_2
REPORT "Improper initialization of AV2_cca1_2" SEVERITY FAILURE;
ASSERT AV0_cca1_3.all = C0_cca1_3
REPORT "Improper initialization of AV0_cca1_3" SEVERITY FAILURE;
ASSERT AV2_cca1_3.all = C2_cca1_3
REPORT "Improper initialization of AV2_cca1_3" SEVERITY FAILURE;
ASSERT AV0_cca1_4.all = C0_cca1_4
REPORT "Improper initialization of AV0_cca1_4" SEVERITY FAILURE;
ASSERT AV2_cca1_4.all = C2_cca1_4
REPORT "Improper initialization of AV2_cca1_4" SEVERITY FAILURE;
ASSERT AV0_cmre_1.all = C0_cmre_1
REPORT "Improper initialization of AV0_cmre_1" SEVERITY FAILURE;
ASSERT AV2_cmre_1.all = C2_cmre_1
REPORT "Improper initialization of AV2_cmre_1" SEVERITY FAILURE;
ASSERT AV0_cmre_2.all = C0_cmre_2
REPORT "Improper initialization of AV0_cmre_2" SEVERITY FAILURE;
ASSERT AV2_cmre_2.all = C2_cmre_2
REPORT "Improper initialization of AV2_cmre_2" SEVERITY FAILURE;
ASSERT AV0_cca1_7.all = C0_cca1_7
REPORT "Improper initialization of AV0_cca1_7" SEVERITY FAILURE;
ASSERT AV2_cca1_7.all = C2_cca1_7
REPORT "Improper initialization of AV2_cca1_7" SEVERITY FAILURE;
ASSERT AV0_cmre_3.all = C0_cmre_3
REPORT "Improper initialization of AV0_cmre_3" SEVERITY FAILURE;
ASSERT AV2_cmre_3.all = C2_cmre_3
REPORT "Improper initialization of AV2_cmre_3" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***PASSED TEST: c03s03b00x00p03n04i00517"
severity NOTE;
assert ( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***FAILED TEST: c03s03b00x00p03n04i00517 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00517arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc517.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00517pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00517pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00517pkg;
USE work.c03s03b00x00p03n04i00517pkg.ALL;
ENTITY c03s03b00x00p03n04i00517ent IS
END c03s03b00x00p03n04i00517ent;
ARCHITECTURE c03s03b00x00p03n04i00517arch OF c03s03b00x00p03n04i00517ent IS
--
-- Access type declarations
--
TYPE at_scre_1 IS ACCESS t_scre_1 ;
TYPE at_cca1_1 IS ACCESS t_cca1_1 ;
TYPE at_cca1_2 IS ACCESS t_cca1_2 ;
TYPE at_cca1_3 IS ACCESS t_cca1_3 ;
TYPE at_cca1_4 IS ACCESS t_cca1_4 ;
TYPE at_cmre_1 IS ACCESS t_cmre_1 ;
TYPE at_cmre_2 IS ACCESS t_cmre_2 ;
TYPE at_cca1_7 IS ACCESS t_cca1_7 ;
TYPE at_cmre_3 IS ACCESS t_cmre_3 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_scre_1 : at_scre_1 ;
VARIABLE AV2_scre_1 : at_scre_1 ;
VARIABLE AV0_cca1_1 : at_cca1_1 ;
VARIABLE AV2_cca1_1 : at_cca1_1 ;
VARIABLE AV0_cca1_2 : at_cca1_2 ;
VARIABLE AV2_cca1_2 : at_cca1_2 ;
VARIABLE AV0_cca1_3 : at_cca1_3 ;
VARIABLE AV2_cca1_3 : at_cca1_3 ;
VARIABLE AV0_cca1_4 : at_cca1_4 ;
VARIABLE AV2_cca1_4 : at_cca1_4 ;
VARIABLE AV0_cmre_1 : at_cmre_1 ;
VARIABLE AV2_cmre_1 : at_cmre_1 ;
VARIABLE AV0_cmre_2 : at_cmre_2 ;
VARIABLE AV2_cmre_2 : at_cmre_2 ;
VARIABLE AV0_cca1_7 : at_cca1_7 ;
VARIABLE AV2_cca1_7 : at_cca1_7 ;
VARIABLE AV0_cmre_3 : at_cmre_3 ;
VARIABLE AV2_cmre_3 : at_cmre_3 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_scre_1 := NEW t_scre_1 ;
AV0_cca1_1 := NEW t_cca1_1 ;
AV0_cca1_2 := NEW t_cca1_2 ;
AV0_cca1_3 := NEW t_cca1_3 ;
AV0_cca1_4 := NEW t_cca1_4 ;
AV0_cmre_1 := NEW t_cmre_1 ;
AV0_cmre_2 := NEW t_cmre_2 ;
AV0_cca1_7 := NEW t_cca1_7 ;
AV0_cmre_3 := NEW t_cmre_3 ;
---
AV2_scre_1 := NEW t_scre_1 ' ( C2_scre_1 ) ;
AV2_cca1_1 := NEW t_cca1_1 ' ( C2_cca1_1 ) ;
AV2_cca1_2 := NEW t_cca1_2 ' ( C2_cca1_2 ) ;
AV2_cca1_3 := NEW t_cca1_3 ' ( C2_cca1_3 ) ;
AV2_cca1_4 := NEW t_cca1_4 ' ( C2_cca1_4 ) ;
AV2_cmre_1 := NEW t_cmre_1 ' ( C2_cmre_1 ) ;
AV2_cmre_2 := NEW t_cmre_2 ' ( C2_cmre_2 ) ;
AV2_cca1_7 := NEW t_cca1_7 ' ( C2_cca1_7 ) ;
AV2_cmre_3 := NEW t_cmre_3 ' ( C2_cmre_3 ) ;
--
--
ASSERT AV0_scre_1.all = C0_scre_1
REPORT "Improper initialization of AV0_scre_1" SEVERITY FAILURE;
ASSERT AV2_scre_1.all = C2_scre_1
REPORT "Improper initialization of AV2_scre_1" SEVERITY FAILURE;
ASSERT AV0_cca1_1.all = C0_cca1_1
REPORT "Improper initialization of AV0_cca1_1" SEVERITY FAILURE;
ASSERT AV2_cca1_1.all = C2_cca1_1
REPORT "Improper initialization of AV2_cca1_1" SEVERITY FAILURE;
ASSERT AV0_cca1_2.all = C0_cca1_2
REPORT "Improper initialization of AV0_cca1_2" SEVERITY FAILURE;
ASSERT AV2_cca1_2.all = C2_cca1_2
REPORT "Improper initialization of AV2_cca1_2" SEVERITY FAILURE;
ASSERT AV0_cca1_3.all = C0_cca1_3
REPORT "Improper initialization of AV0_cca1_3" SEVERITY FAILURE;
ASSERT AV2_cca1_3.all = C2_cca1_3
REPORT "Improper initialization of AV2_cca1_3" SEVERITY FAILURE;
ASSERT AV0_cca1_4.all = C0_cca1_4
REPORT "Improper initialization of AV0_cca1_4" SEVERITY FAILURE;
ASSERT AV2_cca1_4.all = C2_cca1_4
REPORT "Improper initialization of AV2_cca1_4" SEVERITY FAILURE;
ASSERT AV0_cmre_1.all = C0_cmre_1
REPORT "Improper initialization of AV0_cmre_1" SEVERITY FAILURE;
ASSERT AV2_cmre_1.all = C2_cmre_1
REPORT "Improper initialization of AV2_cmre_1" SEVERITY FAILURE;
ASSERT AV0_cmre_2.all = C0_cmre_2
REPORT "Improper initialization of AV0_cmre_2" SEVERITY FAILURE;
ASSERT AV2_cmre_2.all = C2_cmre_2
REPORT "Improper initialization of AV2_cmre_2" SEVERITY FAILURE;
ASSERT AV0_cca1_7.all = C0_cca1_7
REPORT "Improper initialization of AV0_cca1_7" SEVERITY FAILURE;
ASSERT AV2_cca1_7.all = C2_cca1_7
REPORT "Improper initialization of AV2_cca1_7" SEVERITY FAILURE;
ASSERT AV0_cmre_3.all = C0_cmre_3
REPORT "Improper initialization of AV0_cmre_3" SEVERITY FAILURE;
ASSERT AV2_cmre_3.all = C2_cmre_3
REPORT "Improper initialization of AV2_cmre_3" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***PASSED TEST: c03s03b00x00p03n04i00517"
severity NOTE;
assert ( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***FAILED TEST: c03s03b00x00p03n04i00517 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00517arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc517.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c03s03b00x00p03n04i00517pkg IS
--
-- Index types for array declarations
--
SUBTYPE st_ind1 IS INTEGER RANGE 1 TO 8; -- index from 1 (POSITIVE)
SUBTYPE st_ind2 IS INTEGER RANGE 0 TO 3; -- index from 0 (NATURAL)
SUBTYPE st_ind3 IS CHARACTER RANGE 'a' TO 'd'; -- non-INTEGER index
SUBTYPE st_ind4 IS INTEGER RANGE 0 DOWNTO -3; -- descending range
--
-- Scalar type for subelements
--
SUBTYPE st_scl1 IS CHARACTER ;
SUBTYPE st_scl3 IS INTEGER RANGE 1 TO INTEGER'HIGH;
SUBTYPE st_scl4 IS REAL RANGE 0.0 TO 1024.0;
-- -----------------------------------------------------------------------------------------
-- Composite type declarations
-- -----------------------------------------------------------------------------------------
--
-- Records of scalars
--
TYPE t_scre_1 IS RECORD
left : st_scl1;
second : TIME;
third : st_scl3;
right : st_scl4;
END RECORD;
--
-- Unconstrained arrays of scalars
--
TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
st_ind3 RANGE <>,
st_ind2 RANGE <>,
st_ind1 RANGE <>) OF st_scl1;
--
--
-- Constrained arrays of scalars (make compatable with unconstrained types
--
SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 , -- ( i2, i1 ) of CHAR
st_ind1 );
SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 , -- ( i3, i2, i1) of CHAR
st_ind2 ,
st_ind1 );
SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 , -- ( i4, i3, i2, i1 ) of CHAR
st_ind3 ,
st_ind2 ,
st_ind1 );
--
--
-- constrained arrays of composites
--
TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1; -- ( i1 ) is RECORD of scalar
TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1; -- ( i2 )( i1 ) is CHAR
TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2; -- ( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3; -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1; -- ( i3 )( i2, i1 ) is CHAR
TYPE t_cca2_2 IS ARRAY (st_ind4, -- ( i4, i3 )( i2, i1 ) of CHAR
st_ind3) OF t_csa2_1;
TYPE t_cca3_1 IS ARRAY (st_ind4, -- ( i4, i3, i2 )( i1 ) of CHAR
st_ind3,
st_ind2) OF t_csa1_1;
TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1; -- ( i4 )( i3, i2, i1 ) is CHAR
--
-- Records of composites
--
TYPE t_cmre_1 IS RECORD
left : t_csa1_1; -- .fN(i1) is CHAR
second : t_scre_1; -- .fN.fN
END RECORD;
TYPE t_cmre_2 IS RECORD
left ,
second ,
third ,
right : t_csa1_1; -- .fN(i1) is CHAR
END RECORD;
--
-- Mixed Records/arrays
--
TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2; -- (i3).fN(i1) is CHAR
TYPE t_cmre_3 IS RECORD
left ,
second ,
third ,
right : t_cca1_7; -- .fN(i3).fN(i1) is CHAR
END RECORD;
--
-- TYPE declarations for resolution function (Constrained types only)
--
TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
--
-- Declaration of Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
--
-- Resolved SUBTYPE declaration
--
SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
--
-- Functions declarations for multi-dimensional comosite values
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
-- -------------------------------------------------------------------------------------------
-- Data values for Composite Types
-- -------------------------------------------------------------------------------------------
CONSTANT CX_scl1 : st_scl1 := 'X' ;
CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
CONSTANT C1_scl1 : st_scl1 := 'A' ;
CONSTANT C2_scl1 : st_scl1 := 'Z' ;
CONSTANT CX_scl2 : TIME := 99 fs ;
CONSTANT C0_scl2 : TIME := TIME'LEFT ;
CONSTANT C1_scl2 : TIME := 0 fs;
CONSTANT C2_scl2 : TIME := 2 ns;
CONSTANT CX_scl3 : st_scl3 := 15 ;
CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
CONSTANT C1_scl3 : st_scl3 := 6 ;
CONSTANT C2_scl3 : st_scl3 := 8 ;
CONSTANT CX_scl4 : st_scl4 := 99.9 ;
CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
CONSTANT C1_scl4 : st_scl4 := 1.0 ;
CONSTANT C2_scl4 : st_scl4 := 2.1 ;
CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
OTHERS =>C0_scl1);
CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
OTHERS =>C0_scl2);
CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
OTHERS =>C0_scl3);
CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
OTHERS =>C0_scl4);
--
CONSTANT CX_csa2_1 : t_csa2_1 ;
CONSTANT C0_csa2_1 : t_csa2_1 ;
CONSTANT C1_csa2_1 : t_csa2_1 ;
CONSTANT C2_csa2_1 : t_csa2_1 ;
CONSTANT CX_csa3_1 : t_csa3_1 ;
CONSTANT C0_csa3_1 : t_csa3_1 ;
CONSTANT C1_csa3_1 : t_csa3_1 ;
CONSTANT C2_csa3_1 : t_csa3_1 ;
CONSTANT CX_csa4_1 : t_csa4_1 ;
CONSTANT C0_csa4_1 : t_csa4_1 ;
CONSTANT C1_csa4_1 : t_csa4_1 ;
CONSTANT C2_csa4_1 : t_csa4_1 ;
--
CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 );
CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 );
CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 );
CONSTANT CX_cca2_1 : t_cca2_1 ;
CONSTANT C0_cca2_1 : t_cca2_1 ;
CONSTANT C1_cca2_1 : t_cca2_1 ;
CONSTANT C2_cca2_1 : t_cca2_1 ;
--
CONSTANT CX_cca2_2 : t_cca2_2 ;
CONSTANT C0_cca2_2 : t_cca2_2 ;
CONSTANT C1_cca2_2 : t_cca2_2 ;
CONSTANT C2_cca2_2 : t_cca2_2 ;
CONSTANT CX_cca3_1 : t_cca3_1 ;
CONSTANT C0_cca3_1 : t_cca3_1 ;
CONSTANT C1_cca3_1 : t_cca3_1 ;
CONSTANT C2_cca3_1 : t_cca3_1 ;
--
CONSTANT CX_cca3_2 : t_cca3_2 ;
CONSTANT C0_cca3_2 : t_cca3_2 ;
CONSTANT C1_cca3_2 : t_cca3_2 ;
CONSTANT C2_cca3_2 : t_cca3_2 ;
CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 );
CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
-- --------------------------------------------------------------------------------------------
-- Functions for mapping from integer test values to/from values of the Test types
-- --------------------------------------------------------------------------------------------
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
FUNCTION val_t ( i : INTEGER ) RETURN TIME;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER;
FUNCTION val_i ( i : TIME ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING;
FUNCTION val_s ( i : TIME ) RETURN STRING;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
END;
PACKAGE BODY c03s03b00x00p03n04i00517pkg IS
CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 );
--
-- Functions to provide values for multi-dimensional composites
--
FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
VARIABLE res : t_csa2_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
VARIABLE res : t_csa3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
VARIABLE res : t_csa4_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
FOR l IN res'RANGE(4) LOOP
res(i,j,k,l) := v0;
END LOOP;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
RETURN res;
END;
FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
VARIABLE res : t_cca2_2;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
res(i,j) := v0;
END LOOP;
END LOOP;
res(res'left (1),res'left (2)) := v2;
res(res'left (1),res'right(2)) := v2;
res(res'right(1),res'left (2)) := v2;
res(res'right(1),res'right(2)) := v2;
RETURN res;
END;
FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
VARIABLE res : t_cca3_1;
BEGIN
FOR i IN res'RANGE(1) LOOP
FOR j IN res'RANGE(2) LOOP
FOR k IN res'RANGE(3) LOOP
res(i,j,k) := v0;
END LOOP;
END LOOP;
END LOOP;
res(res'left (1),res'left (2),res'left (3)) := v2;
res(res'right(1),res'left (2),res'left (3)) := v2;
res(res'left (1),res'right(2),res'left (3)) := v2;
res(res'right(1),res'right(2),res'left (3)) := v2;
res(res'left (1),res'left (2),res'right(3)) := v2;
res(res'right(1),res'left (2),res'right(3)) := v2;
res(res'left (1),res'right(2),res'right(3)) := v2;
res(res'right(1),res'right(2),res'right(3)) := v2;
RETURN res;
END;
--
-- Resolution Functions
--
FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_scre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_csa4_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_3;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_4;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca2_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca3_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_1;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_2;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cca1_7;
ELSE RETURN v(1);
END IF;
END;
FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
BEGIN
IF v'LENGTH=0
THEN RETURN CX_cmre_3;
ELSE RETURN v(1);
END IF;
END;
--
--
FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
BEGIN
IF i = 0 THEN RETURN C0_scl1; END IF;
IF i = 1 THEN RETURN C1_scl1; END IF;
IF i = 2 THEN RETURN C2_scl1; END IF;
RETURN CX_scl1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
BEGIN
IF i = 0 THEN RETURN C0_scl2; END IF;
IF i = 1 THEN RETURN C1_scl2; END IF;
IF i = 2 THEN RETURN C2_scl2; END IF;
RETURN CX_scl2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
BEGIN
IF i = 0 THEN RETURN C0_scl3; END IF;
IF i = 1 THEN RETURN C1_scl3; END IF;
IF i = 2 THEN RETURN C2_scl3; END IF;
RETURN CX_scl3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
BEGIN
IF i = 0 THEN RETURN C0_scl4; END IF;
IF i = 1 THEN RETURN C1_scl4; END IF;
IF i = 2 THEN RETURN C2_scl4; END IF;
RETURN CX_scl4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_scre_1; END IF;
IF i = 1 THEN RETURN C1_scre_1; END IF;
IF i = 2 THEN RETURN C2_scre_1; END IF;
RETURN CX_scre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_1; END IF;
IF i = 1 THEN RETURN C1_csa1_1; END IF;
IF i = 2 THEN RETURN C2_csa1_1; END IF;
RETURN CX_csa1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_2; END IF;
IF i = 1 THEN RETURN C1_csa1_2; END IF;
IF i = 2 THEN RETURN C2_csa1_2; END IF;
RETURN CX_csa1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_3; END IF;
IF i = 1 THEN RETURN C1_csa1_3; END IF;
IF i = 2 THEN RETURN C2_csa1_3; END IF;
RETURN CX_csa1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_csa1_4; END IF;
IF i = 1 THEN RETURN C1_csa1_4; END IF;
IF i = 2 THEN RETURN C2_csa1_4; END IF;
RETURN CX_csa1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa2_1; END IF;
IF i = 1 THEN RETURN C1_csa2_1; END IF;
IF i = 2 THEN RETURN C2_csa2_1; END IF;
RETURN CX_csa2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa3_1; END IF;
IF i = 1 THEN RETURN C1_csa3_1; END IF;
IF i = 2 THEN RETURN C2_csa3_1; END IF;
RETURN CX_csa3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
BEGIN
IF i = 0 THEN RETURN C0_csa4_1; END IF;
IF i = 1 THEN RETURN C1_csa4_1; END IF;
IF i = 2 THEN RETURN C2_csa4_1; END IF;
RETURN CX_csa4_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_1; END IF;
IF i = 1 THEN RETURN C1_cca1_1; END IF;
IF i = 2 THEN RETURN C2_cca1_1; END IF;
RETURN CX_cca1_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_2; END IF;
IF i = 1 THEN RETURN C1_cca1_2; END IF;
IF i = 2 THEN RETURN C2_cca1_2; END IF;
RETURN CX_cca1_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_3; END IF;
IF i = 1 THEN RETURN C1_cca1_3; END IF;
IF i = 2 THEN RETURN C2_cca1_3; END IF;
RETURN CX_cca1_3;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_4; END IF;
IF i = 1 THEN RETURN C1_cca1_4; END IF;
IF i = 2 THEN RETURN C2_cca1_4; END IF;
RETURN CX_cca1_4;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_1; END IF;
IF i = 1 THEN RETURN C1_cca2_1; END IF;
IF i = 2 THEN RETURN C2_cca2_1; END IF;
RETURN CX_cca2_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca2_2; END IF;
IF i = 1 THEN RETURN C1_cca2_2; END IF;
IF i = 2 THEN RETURN C2_cca2_2; END IF;
RETURN CX_cca2_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_1; END IF;
IF i = 1 THEN RETURN C1_cca3_1; END IF;
IF i = 2 THEN RETURN C2_cca3_1; END IF;
RETURN CX_cca3_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cca3_2; END IF;
IF i = 1 THEN RETURN C1_cca3_2; END IF;
IF i = 2 THEN RETURN C2_cca3_2; END IF;
RETURN CX_cca3_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_1; END IF;
IF i = 1 THEN RETURN C1_cmre_1; END IF;
IF i = 2 THEN RETURN C2_cmre_1; END IF;
RETURN CX_cmre_1;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_2; END IF;
IF i = 1 THEN RETURN C1_cmre_2; END IF;
IF i = 2 THEN RETURN C2_cmre_2; END IF;
RETURN CX_cmre_2;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
BEGIN
IF i = 0 THEN RETURN C0_cca1_7; END IF;
IF i = 1 THEN RETURN C1_cca1_7; END IF;
IF i = 2 THEN RETURN C2_cca1_7; END IF;
RETURN CX_cca1_7;
END;
FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
BEGIN
IF i = 0 THEN RETURN C0_cmre_3; END IF;
IF i = 1 THEN RETURN C1_cmre_3; END IF;
IF i = 2 THEN RETURN C2_cmre_3; END IF;
RETURN CX_cmre_3;
END;
--
--
FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl1 THEN RETURN 0; END IF;
IF i = C1_scl1 THEN RETURN 1; END IF;
IF i = C2_scl1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
BEGIN
IF i = C0_scl2 THEN RETURN 0; END IF;
IF i = C1_scl2 THEN RETURN 1; END IF;
IF i = C2_scl2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl3 THEN RETURN 0; END IF;
IF i = C1_scl3 THEN RETURN 1; END IF;
IF i = C2_scl3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
BEGIN
IF i = C0_scl4 THEN RETURN 0; END IF;
IF i = C1_scl4 THEN RETURN 1; END IF;
IF i = C2_scl4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_scre_1 THEN RETURN 0; END IF;
IF i = C1_scre_1 THEN RETURN 1; END IF;
IF i = C2_scre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_1 THEN RETURN 0; END IF;
IF i = C1_csa1_1 THEN RETURN 1; END IF;
IF i = C2_csa1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_2 THEN RETURN 0; END IF;
IF i = C1_csa1_2 THEN RETURN 1; END IF;
IF i = C2_csa1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_3 THEN RETURN 0; END IF;
IF i = C1_csa1_3 THEN RETURN 1; END IF;
IF i = C2_csa1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa1_4 THEN RETURN 0; END IF;
IF i = C1_csa1_4 THEN RETURN 1; END IF;
IF i = C2_csa1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa2_1 THEN RETURN 0; END IF;
IF i = C1_csa2_1 THEN RETURN 1; END IF;
IF i = C2_csa2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa3_1 THEN RETURN 0; END IF;
IF i = C1_csa3_1 THEN RETURN 1; END IF;
IF i = C2_csa3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_csa4_1 THEN RETURN 0; END IF;
IF i = C1_csa4_1 THEN RETURN 1; END IF;
IF i = C2_csa4_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_1 THEN RETURN 0; END IF;
IF i = C1_cca1_1 THEN RETURN 1; END IF;
IF i = C2_cca1_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_2 THEN RETURN 0; END IF;
IF i = C1_cca1_2 THEN RETURN 1; END IF;
IF i = C2_cca1_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_3 THEN RETURN 0; END IF;
IF i = C1_cca1_3 THEN RETURN 1; END IF;
IF i = C2_cca1_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_4 THEN RETURN 0; END IF;
IF i = C1_cca1_4 THEN RETURN 1; END IF;
IF i = C2_cca1_4 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_1 THEN RETURN 0; END IF;
IF i = C1_cca2_1 THEN RETURN 1; END IF;
IF i = C2_cca2_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca2_2 THEN RETURN 0; END IF;
IF i = C1_cca2_2 THEN RETURN 1; END IF;
IF i = C2_cca2_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_1 THEN RETURN 0; END IF;
IF i = C1_cca3_1 THEN RETURN 1; END IF;
IF i = C2_cca3_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca3_2 THEN RETURN 0; END IF;
IF i = C1_cca3_2 THEN RETURN 1; END IF;
IF i = C2_cca3_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_1 THEN RETURN 0; END IF;
IF i = C1_cmre_1 THEN RETURN 1; END IF;
IF i = C2_cmre_1 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_2 THEN RETURN 0; END IF;
IF i = C1_cmre_2 THEN RETURN 1; END IF;
IF i = C2_cmre_2 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
BEGIN
IF i = C0_cca1_7 THEN RETURN 0; END IF;
IF i = C1_cca1_7 THEN RETURN 1; END IF;
IF i = C2_cca1_7 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
BEGIN
IF i = C0_cmre_3 THEN RETURN 0; END IF;
IF i = C1_cmre_3 THEN RETURN 1; END IF;
IF i = C2_cmre_3 THEN RETURN 2; END IF;
RETURN -1;
END;
FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
BEGIN
IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : TIME ) RETURN STRING IS
BEGIN
IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
BEGIN
IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
BEGIN
IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
BEGIN
IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
BEGIN
IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
BEGIN
IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
BEGIN
IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
BEGIN
IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
RETURN "UNKNOWN";
END;
FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
BEGIN
IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
RETURN "UNKNOWN";
END;
END c03s03b00x00p03n04i00517pkg;
USE work.c03s03b00x00p03n04i00517pkg.ALL;
ENTITY c03s03b00x00p03n04i00517ent IS
END c03s03b00x00p03n04i00517ent;
ARCHITECTURE c03s03b00x00p03n04i00517arch OF c03s03b00x00p03n04i00517ent IS
--
-- Access type declarations
--
TYPE at_scre_1 IS ACCESS t_scre_1 ;
TYPE at_cca1_1 IS ACCESS t_cca1_1 ;
TYPE at_cca1_2 IS ACCESS t_cca1_2 ;
TYPE at_cca1_3 IS ACCESS t_cca1_3 ;
TYPE at_cca1_4 IS ACCESS t_cca1_4 ;
TYPE at_cmre_1 IS ACCESS t_cmre_1 ;
TYPE at_cmre_2 IS ACCESS t_cmre_2 ;
TYPE at_cca1_7 IS ACCESS t_cca1_7 ;
TYPE at_cmre_3 IS ACCESS t_cmre_3 ;
--
--
BEGIN
TESTING: PROCESS
--
-- ACCESS VARIABLE declarations
--
VARIABLE AV0_scre_1 : at_scre_1 ;
VARIABLE AV2_scre_1 : at_scre_1 ;
VARIABLE AV0_cca1_1 : at_cca1_1 ;
VARIABLE AV2_cca1_1 : at_cca1_1 ;
VARIABLE AV0_cca1_2 : at_cca1_2 ;
VARIABLE AV2_cca1_2 : at_cca1_2 ;
VARIABLE AV0_cca1_3 : at_cca1_3 ;
VARIABLE AV2_cca1_3 : at_cca1_3 ;
VARIABLE AV0_cca1_4 : at_cca1_4 ;
VARIABLE AV2_cca1_4 : at_cca1_4 ;
VARIABLE AV0_cmre_1 : at_cmre_1 ;
VARIABLE AV2_cmre_1 : at_cmre_1 ;
VARIABLE AV0_cmre_2 : at_cmre_2 ;
VARIABLE AV2_cmre_2 : at_cmre_2 ;
VARIABLE AV0_cca1_7 : at_cca1_7 ;
VARIABLE AV2_cca1_7 : at_cca1_7 ;
VARIABLE AV0_cmre_3 : at_cmre_3 ;
VARIABLE AV2_cmre_3 : at_cmre_3 ;
--
--
BEGIN
--
-- Allocation of access values
--
AV0_scre_1 := NEW t_scre_1 ;
AV0_cca1_1 := NEW t_cca1_1 ;
AV0_cca1_2 := NEW t_cca1_2 ;
AV0_cca1_3 := NEW t_cca1_3 ;
AV0_cca1_4 := NEW t_cca1_4 ;
AV0_cmre_1 := NEW t_cmre_1 ;
AV0_cmre_2 := NEW t_cmre_2 ;
AV0_cca1_7 := NEW t_cca1_7 ;
AV0_cmre_3 := NEW t_cmre_3 ;
---
AV2_scre_1 := NEW t_scre_1 ' ( C2_scre_1 ) ;
AV2_cca1_1 := NEW t_cca1_1 ' ( C2_cca1_1 ) ;
AV2_cca1_2 := NEW t_cca1_2 ' ( C2_cca1_2 ) ;
AV2_cca1_3 := NEW t_cca1_3 ' ( C2_cca1_3 ) ;
AV2_cca1_4 := NEW t_cca1_4 ' ( C2_cca1_4 ) ;
AV2_cmre_1 := NEW t_cmre_1 ' ( C2_cmre_1 ) ;
AV2_cmre_2 := NEW t_cmre_2 ' ( C2_cmre_2 ) ;
AV2_cca1_7 := NEW t_cca1_7 ' ( C2_cca1_7 ) ;
AV2_cmre_3 := NEW t_cmre_3 ' ( C2_cmre_3 ) ;
--
--
ASSERT AV0_scre_1.all = C0_scre_1
REPORT "Improper initialization of AV0_scre_1" SEVERITY FAILURE;
ASSERT AV2_scre_1.all = C2_scre_1
REPORT "Improper initialization of AV2_scre_1" SEVERITY FAILURE;
ASSERT AV0_cca1_1.all = C0_cca1_1
REPORT "Improper initialization of AV0_cca1_1" SEVERITY FAILURE;
ASSERT AV2_cca1_1.all = C2_cca1_1
REPORT "Improper initialization of AV2_cca1_1" SEVERITY FAILURE;
ASSERT AV0_cca1_2.all = C0_cca1_2
REPORT "Improper initialization of AV0_cca1_2" SEVERITY FAILURE;
ASSERT AV2_cca1_2.all = C2_cca1_2
REPORT "Improper initialization of AV2_cca1_2" SEVERITY FAILURE;
ASSERT AV0_cca1_3.all = C0_cca1_3
REPORT "Improper initialization of AV0_cca1_3" SEVERITY FAILURE;
ASSERT AV2_cca1_3.all = C2_cca1_3
REPORT "Improper initialization of AV2_cca1_3" SEVERITY FAILURE;
ASSERT AV0_cca1_4.all = C0_cca1_4
REPORT "Improper initialization of AV0_cca1_4" SEVERITY FAILURE;
ASSERT AV2_cca1_4.all = C2_cca1_4
REPORT "Improper initialization of AV2_cca1_4" SEVERITY FAILURE;
ASSERT AV0_cmre_1.all = C0_cmre_1
REPORT "Improper initialization of AV0_cmre_1" SEVERITY FAILURE;
ASSERT AV2_cmre_1.all = C2_cmre_1
REPORT "Improper initialization of AV2_cmre_1" SEVERITY FAILURE;
ASSERT AV0_cmre_2.all = C0_cmre_2
REPORT "Improper initialization of AV0_cmre_2" SEVERITY FAILURE;
ASSERT AV2_cmre_2.all = C2_cmre_2
REPORT "Improper initialization of AV2_cmre_2" SEVERITY FAILURE;
ASSERT AV0_cca1_7.all = C0_cca1_7
REPORT "Improper initialization of AV0_cca1_7" SEVERITY FAILURE;
ASSERT AV2_cca1_7.all = C2_cca1_7
REPORT "Improper initialization of AV2_cca1_7" SEVERITY FAILURE;
ASSERT AV0_cmre_3.all = C0_cmre_3
REPORT "Improper initialization of AV0_cmre_3" SEVERITY FAILURE;
ASSERT AV2_cmre_3.all = C2_cmre_3
REPORT "Improper initialization of AV2_cmre_3" SEVERITY FAILURE;
--
--
assert NOT( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***PASSED TEST: c03s03b00x00p03n04i00517"
severity NOTE;
assert ( ( AV0_scre_1.all = C0_scre_1 )
and ( AV2_scre_1.all = C2_scre_1 )
and ( AV0_cca1_1.all = C0_cca1_1 )
and ( AV2_cca1_1.all = C2_cca1_1 )
and ( AV0_cca1_2.all = C0_cca1_2 )
and ( AV2_cca1_2.all = C2_cca1_2 )
and ( AV0_cca1_3.all = C0_cca1_3 )
and ( AV2_cca1_3.all = C2_cca1_3 )
and ( AV0_cca1_4.all = C0_cca1_4 )
and ( AV2_cca1_4.all = C2_cca1_4 )
and ( AV0_cmre_1.all = C0_cmre_1 )
and ( AV2_cmre_1.all = C2_cmre_1 )
and ( AV0_cmre_2.all = C0_cmre_2 )
and ( AV2_cmre_2.all = C2_cmre_2 )
and ( AV0_cca1_7.all = C0_cca1_7 )
and ( AV2_cca1_7.all = C2_cca1_7 )
and ( AV0_cmre_3.all = C0_cmre_3 )
and ( AV2_cmre_3.all = C2_cmre_3 ))
report "***FAILED TEST: c03s03b00x00p03n04i00517 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00517arch;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
package foo is
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
end foo;
use work.foo.all;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
begin -- process
assert resolution_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
assert resolution_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
assert resolution_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
assert resolution_table( '0', '1' ) = 'X' report "TEST FAILED-0x1";
assert resolution_table( 'H', 'Z' ) = 'H' report "TEST FAILED-HxZ";
assert resolution_table( 'Z', 'W' ) = 'W' report "TEST FAILED-ZxW";
assert resolution_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1";
assert resolution_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
assert resolution_table( 'Z', 'L' ) = 'L' report "TEST FAILED-ZxL";
assert resolution_table( 'Z', 'H' ) = 'H' report "TEST FAILED-ZxH";
wait;
end process;
end only;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
package foo is
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
end foo;
use work.foo.all;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
begin -- process
assert resolution_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
assert resolution_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
assert resolution_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
assert resolution_table( '0', '1' ) = 'X' report "TEST FAILED-0x1";
assert resolution_table( 'H', 'Z' ) = 'H' report "TEST FAILED-HxZ";
assert resolution_table( 'Z', 'W' ) = 'W' report "TEST FAILED-ZxW";
assert resolution_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1";
assert resolution_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
assert resolution_table( 'Z', 'L' ) = 'L' report "TEST FAILED-ZxL";
assert resolution_table( 'Z', 'H' ) = 'H' report "TEST FAILED-ZxH";
wait;
end process;
end only;
|
entity test is
end test;
library ieee;
use ieee.std_logic_1164.all;
package foo is
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
end foo;
use work.foo.all;
library ieee;
use ieee.std_logic_1164.all;
architecture only of test is
begin -- only
process
begin -- process
assert resolution_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
assert resolution_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
assert resolution_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
assert resolution_table( '0', '1' ) = 'X' report "TEST FAILED-0x1";
assert resolution_table( 'H', 'Z' ) = 'H' report "TEST FAILED-HxZ";
assert resolution_table( 'Z', 'W' ) = 'W' report "TEST FAILED-ZxW";
assert resolution_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1";
assert resolution_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
assert resolution_table( 'Z', 'L' ) = 'L' report "TEST FAILED-ZxL";
assert resolution_table( 'Z', 'H' ) = 'H' report "TEST FAILED-ZxH";
wait;
end process;
end only;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use work.common.all;
entity synthesizer_sim_test is
end entity;
architecture synthesizer_sim_test_impl of synthesizer_sim_test is
type step is
record
step_key: keys_signal;
step_event: key_event_t;
step_duration: natural;
end record;
type step_table is array(integer range <>) of step;
constant steps: step_table(0 to 4) :=
(("000000", key_event_idle, 524288)
,("000001", key_event_make, 1)
,("000001", key_event_idle, 524288) -- 1s
,("000001", key_event_break, 1)
,("000001", key_event_idle, 5242880)
);
signal CLK: std_logic := '1';
signal KEY_CODE: keys_signal;
signal KEY_EVENT: key_event_t;
signal AUDIO: audio_signal;
begin
synthesizer_sim : entity work.synthesizer_sim(synthesizer_sim_impl)
port map (CLK, KEY_CODE, KEY_EVENT, AUDIO);
process
file out_file: text is out "synthesizer_sim_test.out";
variable out_line: line;
begin
for j in steps'range loop
KEY_CODE <= steps(j).step_key;
KEY_EVENT <= steps(j).step_event;
wait for 0.8 us;
for k in 0 to steps(j).step_duration loop
CLK <= not CLK;
wait for 0.8 us;
CLK <= not CLK;
wait for 0.8 us;
write(out_line, to_integer(AUDIO(10 downto 8)));
writeline(out_file, out_line);
write(out_line, to_integer(AUDIO(7 downto 0)));
writeline(out_file, out_line);
end loop;
end loop;
report "end of test" severity note;
wait;
end process;
end architecture;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use work.common.all;
entity synthesizer_sim_test is
end entity;
architecture synthesizer_sim_test_impl of synthesizer_sim_test is
type step is
record
step_key: keys_signal;
step_event: key_event_t;
step_duration: natural;
end record;
type step_table is array(integer range <>) of step;
constant steps: step_table(0 to 4) :=
(("000000", key_event_idle, 524288)
,("000001", key_event_make, 1)
,("000001", key_event_idle, 524288) -- 1s
,("000001", key_event_break, 1)
,("000001", key_event_idle, 5242880)
);
signal CLK: std_logic := '1';
signal KEY_CODE: keys_signal;
signal KEY_EVENT: key_event_t;
signal AUDIO: audio_signal;
begin
synthesizer_sim : entity work.synthesizer_sim(synthesizer_sim_impl)
port map (CLK, KEY_CODE, KEY_EVENT, AUDIO);
process
file out_file: text is out "synthesizer_sim_test.out";
variable out_line: line;
begin
for j in steps'range loop
KEY_CODE <= steps(j).step_key;
KEY_EVENT <= steps(j).step_event;
wait for 0.8 us;
for k in 0 to steps(j).step_duration loop
CLK <= not CLK;
wait for 0.8 us;
CLK <= not CLK;
wait for 0.8 us;
write(out_line, to_integer(AUDIO(10 downto 8)));
writeline(out_file, out_line);
write(out_line, to_integer(AUDIO(7 downto 0)));
writeline(out_file, out_line);
end loop;
end loop;
report "end of test" severity note;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity dflipflop is
port( d, clk : in std_logic;
q : out std_logic );
end entity;
architecture arc of dflipflop is
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= d;
end if;
end process;
end architecture;
|
-- $Id: tb_nexys4_cram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4_cram - sim
-- Description: Test bench for nexys4 (base+cram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4_core
-- serport/tb/serport_master_tb
-- nexys4_cram_aif [UUT]
-- simlib/simbididly
-- bplib/micron/mt45w8mw16b
--
-- To test: generic, any nexys4_cram_aif target
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-03 1064 1.3.2 use sfs_gsim_core
-- 2016-09-02 805 1.3.1 tbcore_rlink without CLK_STOP now
-- 2016-07-20 791 1.3 use simbididly
-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4_cram is
end tb_nexys4_cram;
architecture sim of tb_nexys4_cram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal TB_MEM_CE_N : slbit := '1';
signal TB_MEM_BE_N : slv2 := (others=>'1');
signal TB_MEM_WE_N : slbit := '1';
signal TB_MEM_OE_N : slbit := '1';
signal TB_MEM_ADV_N : slbit := '1';
signal TB_MEM_CLK : slbit := '0';
signal TB_MEM_CRE : slbit := '0';
signal TB_MEM_WAIT : slbit := '0';
signal TB_MEM_ADDR : slv23 := (others=>'Z');
signal TB_MEM_DATA : slv16 := (others=>'0');
signal MM_MEM_CE_N : slbit := '1';
signal MM_MEM_BE_N : slv2 := (others=>'1');
signal MM_MEM_WE_N : slbit := '1';
signal MM_MEM_OE_N : slbit := '1';
signal MM_MEM_ADV_N : slbit := '1';
signal MM_MEM_CLK : slbit := '0';
signal MM_MEM_CRE : slbit := '0';
signal MM_MEM_WAIT : slbit := '0';
signal MM_MEM_ADDR : slv23 := (others=>'Z');
signal MM_MEM_DATA : slv16 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
constant pcb_delay : Delay_length := 1 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4_cram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => TB_MEM_CE_N,
O_MEM_BE_N => TB_MEM_BE_N,
O_MEM_WE_N => TB_MEM_WE_N,
O_MEM_OE_N => TB_MEM_OE_N,
O_MEM_ADV_N => TB_MEM_ADV_N,
O_MEM_CLK => TB_MEM_CLK,
O_MEM_CRE => TB_MEM_CRE,
I_MEM_WAIT => TB_MEM_WAIT,
O_MEM_ADDR => TB_MEM_ADDR,
IO_MEM_DATA => TB_MEM_DATA
);
MM_MEM_CE_N <= TB_MEM_CE_N after pcb_delay;
MM_MEM_BE_N <= TB_MEM_BE_N after pcb_delay;
MM_MEM_WE_N <= TB_MEM_WE_N after pcb_delay;
MM_MEM_OE_N <= TB_MEM_OE_N after pcb_delay;
MM_MEM_ADV_N <= TB_MEM_ADV_N after pcb_delay;
MM_MEM_CLK <= TB_MEM_CLK after pcb_delay;
MM_MEM_CRE <= TB_MEM_CRE after pcb_delay;
MM_MEM_ADDR <= TB_MEM_ADDR after pcb_delay;
TB_MEM_WAIT <= MM_MEM_WAIT after pcb_delay;
BUSDLY: simbididly
generic map (
DELAY => pcb_delay,
DWIDTH => 16)
port map (
A => TB_MEM_DATA,
B => MM_MEM_DATA);
MEM : entity work.mt45w8mw16b
port map (
CLK => MM_MEM_CLK,
CE_N => MM_MEM_CE_N,
OE_N => MM_MEM_OE_N,
WE_N => MM_MEM_WE_N,
UB_N => MM_MEM_BE_N(1),
LB_N => MM_MEM_BE_N(0),
ADV_N => MM_MEM_ADV_N,
CRE => MM_MEM_CRE,
MWAIT => MM_MEM_WAIT,
ADDR => MM_MEM_ADDR,
DATA => MM_MEM_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
-- IRAM, not synth.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Instruction memory for DLX
-- Memory filled by a process which reads from a file
-- file name is "test.asm.mem"
entity IRAM is
generic (
RAM_DEPTH : integer := 128;
I_SIZE : integer := 32);
port (
Rst : in std_logic;
Addr : in std_logic_vector(I_SIZE - 1 downto 0);
Dout : out std_logic_vector(I_SIZE - 1 downto 0)
);
end IRAM;
architecture IRam_Bhe of IRAM is
type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0);
signal IRAM_mem : RAMtype;
begin -- IRam_Bhe
Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))),I_SIZE);
-- purpose: This process is in charge of filling the Instruction RAM with the firmware
-- type : combinational
-- inputs : Rst
-- outputs: IRAM_mem
FILL_MEM_P: process (Rst)
file mem_fp: text;
variable file_line : line;
variable index : integer := 0;
variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0);
begin -- process FILL_MEM_P
if (Rst = '1') then
file_open(mem_fp,"test.asm.mem",READ_MODE);
while (not endfile(mem_fp)) loop
readline(mem_fp,file_line);
hread(file_line,tmp_data_u);
IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u));
index := index + 1;
end loop;
end if;
end process FILL_MEM_P;
end IRam_Bhe;
|
package bug2 is
generic ( gen: natural );
constant test: natural:=gen;
function get_val return natural;
end package;
package mygbug2 is new work.bug2 generic map ( gen => 17 );
|
package bug2 is
generic ( gen: natural );
constant test: natural:=gen;
function get_val return natural;
end package;
package mygbug2 is new work.bug2 generic map ( gen => 17 );
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
architecture test of inline_03 is
signal clk, ready : bit;
begin
dut1 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, false )
-- end code from book
port map ( clk, ready, open, open );
dut2 : entity work.control_unit
-- code from book (in text)
generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
-- end code from book
port map ( clk, ready, open, open );
dut3 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, debug => open )
-- end code from book
port map ( clk, ready, open, open );
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
architecture test of inline_03 is
signal clk, ready : bit;
begin
dut1 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, false )
-- end code from book
port map ( clk, ready, open, open );
dut2 : entity work.control_unit
-- code from book (in text)
generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
-- end code from book
port map ( clk, ready, open, open );
dut3 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, debug => open )
-- end code from book
port map ( clk, ready, open, open );
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
architecture test of inline_03 is
signal clk, ready : bit;
begin
dut1 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, false )
-- end code from book
port map ( clk, ready, open, open );
dut2 : entity work.control_unit
-- code from book (in text)
generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
-- end code from book
port map ( clk, ready, open, open );
dut3 : entity work.control_unit
-- code from book (in text)
generic map ( 200 ps, 1500 ps, debug => open )
-- end code from book
port map ( clk, ready, open, open );
end architecture test;
|
package Util is
type integer_list_t is array (natural range <>) of integer;
end package;
|
package Util is
type integer_list_t is array (natural range <>) of integer;
end package;
|
-------------------------------------------------------------------------------
--
-- The serial input/output unit.
--
-- $Id: t400_sio-c.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_sio_rtl_c0 of t400_sio is
for rtl
end for;
end t400_sio_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:12:43 03/13/2017
-- Design Name:
-- Module Name: /home/julian/Projekt/Xilinx Projects/klein-vhdl/sim/klein-64_tb.vhd
-- Project Name: klein-vhdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: klein_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_textio.ALL;
USE work.util.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY klein96_tb IS
END klein96_tb;
ARCHITECTURE behavior OF klein96_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT klein_top
GENERIC(
k : key_enum
);
PORT(
plaintext : IN std_logic_vector(63 downto 0);
key : IN std_logic_vector(key_bits(k)-1 downto 0);
clk : IN std_logic;
reset : IN std_logic;
ciphertext : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal plaintext : std_logic_vector(63 downto 0) := (others => '0');
signal key : std_logic_vector(95 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal ciphertext : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: klein_top GENERIC MAP (
k => K_96
) PORT MAP (
plaintext => plaintext,
key => key,
clk => clk,
reset => reset,
ciphertext => ciphertext
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable ct: line;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- Test the test vectors specified in the KLEIN paper.
-- first test vector
reset <= '1';
plaintext <= x"FFFFFFFFFFFFFFFF";
key <= x"000000000000000000000000";
wait for 10 ns;
reset <= '0';
wait for 210 ns;
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: DB9FA7D33D8E8E36)";
deallocate(ct);
-- second test vector
reset <= '1';
plaintext <= x"0000000000000000";
key <= x"FFFFFFFFFFFFFFFFFFFFFFFF";
wait for 10 ns;
reset <= '0';
wait for 210 ns;
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: 15A3A03386A7FEC6)";
deallocate(ct);
-- third test vector
reset <= '1';
plaintext <= x"FFFFFFFFFFFFFFFF";
key <= x"1234567890ABCDEF12345678";
wait for 10 ns;
reset <= '0';
wait for 210 ns;
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: 79687798AFDA0BC3)";
deallocate(ct);
-- fourth test vector
reset <= '1';
plaintext <= x"1234567890ABCDEF";
key <= x"000000000000000000000000";
wait for 10 ns;
reset <= '0';
wait for 210 ns;
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: 5006A987A500BFDD)";
deallocate(ct);
wait;
end process;
END;
|
-- NEED RESULT: ARCH00451: A concurrent procedure call may appear in a generate stm passed
-- NEED RESULT: ARCH00451: A concurrent procedure call may appear in a generate stm passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00451
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.7 (1)
-- 9.7 (4)
-- 9.7 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00451)
-- ENT00451_Test_Bench(ARCH00451_Test_Bench)
--
-- REVISION HISTORY:
--
-- 5-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00451 of E00000 is
constant C : boolean := True;
procedure Proc (constant P : boolean) is
begin
test_report ( "ARCH00451" ,
"A concurrent procedure call may appear in a generate stm" ,
P ) ;
end Proc ;
begin
For_Gen :
for i in 1 to 1 generate
-- Test that a concurrent procedure call is allowed.
Proc (i = 1) ;
end generate For_Gen ;
If_Gen :
if C generate
-- Test that a concurrent procedure call is allowed.
Proc (C) ;
end generate If_Gen ;
end ARCH00451 ;
entity ENT00451_Test_Bench is
end ENT00451_Test_Bench ;
architecture ARCH00451_Test_Bench of ENT00451_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00451 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00451_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc50.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p04n01i00050ent IS
END c04s03b01x01p04n01i00050ent;
ARCHITECTURE c04s03b01x01p04n01i00050arch OF c04s03b01x01p04n01i00050ent IS
constant A1 : bit; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p04n01i00050 - Deferred constant declaration can not appear in an architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p04n01i00050arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc50.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p04n01i00050ent IS
END c04s03b01x01p04n01i00050ent;
ARCHITECTURE c04s03b01x01p04n01i00050arch OF c04s03b01x01p04n01i00050ent IS
constant A1 : bit; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p04n01i00050 - Deferred constant declaration can not appear in an architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p04n01i00050arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc50.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p04n01i00050ent IS
END c04s03b01x01p04n01i00050ent;
ARCHITECTURE c04s03b01x01p04n01i00050arch OF c04s03b01x01p04n01i00050ent IS
constant A1 : bit; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p04n01i00050 - Deferred constant declaration can not appear in an architecture body."
severity ERROR;
wait;
END PROCESS TESTING;
ENDc04s03b01x01p04n01i00050arch;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_sm
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_sm.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 6/10/10 v1_00_a
-- ^^^^^^
-- Fixed issue with fetch idle asserting too soon when simultaneous update
-- decode error and stale descriptor error detected. This fixes CR564855.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 12/07/10 v4_03
-- ^^^^^^
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under
-- associated generate
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_sg_ftch_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
updt_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_sg_idle : in std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
ch1_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_sg_idle : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_fetch_address : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
-- DataMover Status --
ftch_done : in std_logic ; --
ftch_error : in std_logic ; --
ftch_interr : in std_logic ; --
ftch_slverr : in std_logic ; --
ftch_decerr : in std_logic ; --
ftch_stale_desc : in std_logic ; --
ftch_error_early : in std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant FETCH_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
constant FETCH_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant FETCH_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant FETCH_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant FETCH_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant FETCH_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_FETCH*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant FETCH_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- Required width in bits for C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
--
---- Vector version of C_SG_FTCH_DESC2QUEUE
--constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_FTCH_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
FETCH_STATUS,
FETCH_ERROR
);
signal ftch_cs : SG_FTCH_STATE_TYPE;
signal ftch_ns : SG_FTCH_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_ftch_sm_idle : std_logic := '0';
signal ch2_ftch_sm_idle : std_logic := '0';
signal ch1_pause_fetch : std_logic := '0';
signal ch2_pause_fetch : std_logic := '0';
-- Misc Signals
signal fetch_cmd_addr : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal fetch_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal ch1_stale_descriptor : std_logic := '0';
signal ch2_stale_descriptor : std_logic := '0';
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
-- CR585958 Constant declaration in axi_sg_ftch_sm needs to move under associated generate
-- counts for keeping track of queue descriptors to prevent
-- fifo fill
--signal ch1_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--signal ch2_desc_ftched_count : std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_ftch_active <= ch1_active_i;
ch2_ftch_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_FTCH_MACHINE : process(ftch_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ftch_error,
ftch_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_ftch_sm_idle <= '0';
ch2_ftch_sm_idle <= '0';
ftch_ns <= ftch_cs;
case ftch_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_ftch_sm_idle <= not service_ch1;
ch2_ftch_sm_idle <= not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
else
ftch_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
else
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_STATUS =>
ch1_ftch_sm_idle <= not ch1_active_i and not service_ch1;
ch2_ftch_sm_idle <= not ch2_active_i and not service_ch2;
-- sg error during fetch - shut down
if(ftch_error = '1')then
ftch_ns <= FETCH_ERROR;
elsif(ftch_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, fetch descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 2 still ready then fetch
-- another descriptor for channel 2
elsif(service_ch2 = '1')then
ch1_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, fetch descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Else if channel 1 still ready then fetch
-- another descriptor for channel 1
elsif(service_ch1 = '1')then
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_DESCRIPTOR;
-- Otherwise return to IDLE
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= IDLE;
end if;
else
ftch_ns <= FETCH_STATUS;
end if;
-------------------------------------------------------------------
when FETCH_ERROR =>
ch1_ftch_sm_idle <= '1';
ch2_ftch_sm_idle <= '1';
ftch_ns <= FETCH_ERROR;
-------------------------------------------------------------------
when others =>
ftch_ns <= IDLE;
end case;
end process SG_FTCH_MACHINE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cs <= IDLE;
else
ftch_cs <= ftch_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_FETCH : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_active_set = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 IDLE process. Indicates channel 1 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH1_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
--elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch1_ftch_interr_set_i = '1')then
ch1_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch1_sg_idle = '0')then
ch1_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch1_sg_idle = '1' and ch1_ftch_queue_empty = '1' and ch1_ftch_sm_idle = '1')then
ch1_ftch_idle <= '1';
end if;
end if;
end process CH1_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH1_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch1_updt_done = '1')then
ch1_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch1_active_i='1' and write_cmnd_cmb = '1')then
ch1_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH1_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH1_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch1_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
-- begin
--
-- desc_queued_incr <= '1' when ch1_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch1_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch1_ftch_descpulled = '1'
-- and not (ch1_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch1_desc_ftched_count <= std_logic_vector(unsigned(ch1_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch1_pause_fetch <= '0';
-- elsif(ch1_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch1_pause_fetch <= '1';
-- else
-- ch1_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
--
--
ch1_pause_fetch <= ch1_ftch_pause;
end generate GEN_CH1_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_run_stop = '1' -- Channel running
and ch1_sg_idle = '0' -- SG Engine running
and ch1_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch1_stale_descriptor = '0' -- No Stale Descriptors
and ch1_desc_flush = '0' -- Not flushing desc
and ch1_pause_fetch = '0' -- Not pausing
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch1_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch1_stale_descriptor = '1'))then
ch1_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_slverr_set <= '0';
elsif(ch1_active_i = '1' and ftch_slverr = '1')then
ch1_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch1_ftch_decerr_set <= '0';
elsif(ch1_active_i = '1' and ftch_decerr = '1')then
ch1_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch1_ftch_err_early <= '1' when ftch_error_early = '1' and ch1_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH1_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH1_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch1_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch1_active_i = '1' )then
ch1_stale_descriptor <= '1';
end if;
end if;
end process CH1_STALE_DESC;
end generate GEN_CH1_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH1_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 generate
begin
ch1_stale_descriptor <= '0';
end generate GEN_CH1_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch1_ftch_stale_desc <= ch1_stale_descriptor;
end generate GEN_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_FETCH : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_ftch_idle <= '0';
ch1_ftch_interr_set <= '0';
ch1_ftch_slverr_set <= '0';
ch1_ftch_decerr_set <= '0';
ch1_ftch_err_early <= '0';
ch1_ftch_stale_desc <= '0';
end generate GEN_NO_CH1_FETCH;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_FETCH : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_active_set = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 IDLE process. Indicates channel 2 fetch process is IDLE
-- This is 1 part of determining IDLE for a channel
-------------------------------------------------------------------------------
CH2_IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_idle <= '1';
-- SG Error therefore force IDLE
-- CR564855 - fetch idle asserted too soon when update error occured.
-- fetch idle does not need to be concerned with updt_error. This is
-- because on going fetch is guarentteed to complete regardless of dma
-- controller or sg update engine.
-- elsif(updt_error = '1' or ftch_error = '1'
elsif(ftch_error = '1'
or ch2_ftch_interr_set_i = '1')then
ch2_ftch_idle <= '1';
-- When SG Fetch no longer idle then clear fetch idle
elsif(ch2_sg_idle = '0')then
ch2_ftch_idle <= '0';
-- If tail = cur and fetch queue is empty then
elsif(ch2_sg_idle = '1' and ch2_ftch_queue_empty = '1' and ch2_ftch_sm_idle = '1')then
ch2_ftch_idle <= '1';
end if;
end if;
end process CH2_IDLE_PROCESS;
-------------------------------------------------------------------------------
-- For No Fetch Queue, generate pause logic to prevent partial descriptor from
-- being fetched and then endless throttle on AXI read bus
-------------------------------------------------------------------------------
GEN_CH2_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
REG_PAUSE_FETCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- On descriptor update done clear pause
if(m_axi_sg_aresetn = '0' or ch2_updt_done = '1')then
ch2_pause_fetch <= '0';
-- If channel active and command written then pause
elsif(ch2_active_i='1' and write_cmnd_cmb = '1')then
ch2_pause_fetch <= '1';
end if;
end if;
end process REG_PAUSE_FETCH;
end generate GEN_CH2_FETCH_PAUSE;
-- Fetch queues so do not need to pause
GEN_CH2_NO_FETCH_PAUSE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
-- -- CR585958
-- -- Required width in bits for C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_WIDTH : integer := clog2(C_SG_FTCH_DESC2QUEUE+1);
-- -- Vector version of C_SG_FTCH_DESC2QUEUE
-- constant SG_FTCH_DESC2QUEUE_VEC : std_logic_vector(SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned
-- (C_SG_FTCH_DESC2QUEUE,SG_FTCH_DESC2QUEUE_WIDTH));
-- signal desc_queued_incr : std_logic := '0';
-- signal desc_queued_decr : std_logic := '0';
--
-- -- CR585958
-- signal ch2_desc_ftched_count: std_logic_vector
-- (SG_FTCH_DESC2QUEUE_WIDTH-1 downto 0) := (others => '0');
--
-- begin
--
-- desc_queued_incr <= '1' when ch2_active_i = '1'
-- and write_cmnd_cmb = '1'
-- and ch2_ftch_descpulled = '0'
-- else '0';
--
-- desc_queued_decr <= '1' when ch2_ftch_descpulled = '1'
-- and not (ch2_active_i = '1' and write_cmnd_cmb = '1')
-- else '0';
--
-- -- Keep track of descriptors queued version descriptors updated
-- DESC_FETCHED_CNTR : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_desc_ftched_count <= (others => '0');
-- elsif(desc_queued_incr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) + 1);
-- elsif(desc_queued_decr = '1')then
-- ch2_desc_ftched_count <= std_logic_vector(unsigned(ch2_desc_ftched_count) - 1);
-- end if;
-- end if;
-- end process DESC_FETCHED_CNTR;
--
-- REG_PAUSE_FETCH : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- ch2_pause_fetch <= '0';
-- elsif(ch2_desc_ftched_count >= SG_FTCH_DESC2QUEUE_VEC)then
-- ch2_pause_fetch <= '1';
-- else
-- ch2_pause_fetch <= '0';
-- end if;
-- end if;
-- end process REG_PAUSE_FETCH;
--
ch2_pause_fetch <= ch2_ftch_pause;
end generate GEN_CH2_NO_FETCH_PAUSE;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_run_stop = '1' -- Channel running
and ch2_sg_idle = '0' -- SG Engine running
and ch2_ftch_queue_full = '0' -- Queue not full
and updt_error = '0' -- No SG Update error
and ch2_stale_descriptor = '0' -- No Stale Descriptors
and ch2_desc_flush = '0' -- Not flushing desc
and ch2_pause_fetch = '0' -- No fetch pause
else '0';
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
INT_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_interr_set_i <= '0';
-- Channel active and datamover int error or fetch done and descriptor stale
elsif((ch2_active_i = '1' and ftch_interr = '1')
or ((ftch_done = '1' or ftch_error = '1') and ch2_stale_descriptor = '1'))then
ch2_ftch_interr_set_i <= '1';
end if;
end if;
end process INT_ERROR_PROCESS;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
SLV_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_slverr_set <= '0';
elsif(ch2_active_i = '1' and ftch_slverr = '1')then
ch2_ftch_slverr_set <= '1';
end if;
end if;
end process SLV_ERROR_PROCESS;
DEC_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset or stopped then clear idle bit
if(m_axi_sg_aresetn = '0')then
ch2_ftch_decerr_set <= '0';
elsif(ch2_active_i = '1' and ftch_decerr = '1')then
ch2_ftch_decerr_set <= '1';
end if;
end if;
end process DEC_ERROR_PROCESS;
-- Early detection of SlvErr or DecErr, used to prevent error'ed descriptor
-- from being used by dma controller
ch2_ftch_err_early <= '1' when ftch_error_early = '1' and ch2_active_i = '1'
else '0';
-- Enable stale descriptor check
GEN_CH2_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
-----------------------------------------------------------------------
-- Stale Descriptor Error
-----------------------------------------------------------------------
CH2_STALE_DESC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- If reset then clear flag
if(m_axi_sg_aresetn = '0')then
ch2_stale_descriptor <= '0';
elsif(ftch_stale_desc = '1' and ch2_active_i = '1' )then
ch2_stale_descriptor <= '1';
end if;
end if;
end process CH2_STALE_DESC;
end generate GEN_CH2_STALE_CHECK;
-- Disable stale descriptor check
GEN_CH2_NO_STALE_CHECK : if C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ch2_stale_descriptor <= '0';
end generate GEN_CH2_NO_STALE_CHECK;
-- Early detection of Stale Descriptor (valid only in tailpntr mode) used
-- to prevent error'ed descriptor from being used.
ch2_ftch_stale_desc <= ch2_stale_descriptor;
end generate GEN_CH2_FETCH;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_FETCH : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_ftch_idle <= '0';
ch2_ftch_interr_set <= '0';
ch2_ftch_slverr_set <= '0';
ch2_ftch_decerr_set <= '0';
ch2_ftch_err_early <= '0';
ch2_ftch_stale_desc <= '0';
end generate GEN_NO_CH2_FETCH;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- Assign fetch address
fetch_cmd_addr <= ch1_fetch_address when ch1_active_i = '1'
else ch2_fetch_address;
-- Assign bytes to transfer (BTT)
fetch_cmd_btt <= FETCH_CH1_CMD_BTT when ch1_active_i = '1'
else FETCH_CH2_CMD_BTT;
-- When command by sm, drive command to ftch_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_cmnd_wr <= '0';
ftch_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
ftch_cmnd_wr <= '1';
ftch_cmnd_data <= FETCH_CMD_RSVD
& FETCH_CMD_TAG
& fetch_cmd_addr
& FETCH_MSB_IGNORED
& FETCH_CMD_TYPE
& FETCH_LSB_IGNORED
& fetch_cmd_btt;
else
ftch_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_addr <= (others => '0');
elsif(write_cmnd_cmb = '1')then
ftch_error_addr <= fetch_cmd_addr;
end if;
end if;
end process LOG_ERROR_ADDR;
end implementation;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rstgen
-- File: rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity rstgen is
generic (
acthigh : integer := 0;
syncrst : integer := 0;
scanen : integer := 0;
syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end;
architecture rtl of rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst, rstoutl, clklockl, arst : std_ulogic;
signal rstsyncin : std_ulogic;
signal inrst_syncreg : std_ulogic;
signal genrst : std_ulogic;
signal genrst_syncreg : std_logic_vector(1 downto 0);
begin
nosyncinrst : if syncin = 0 generate
rst <= not rstin when acthigh = 1 else rstin;
clklockl <= clklock;
end generate;
syncinrst : if syncin = 1 generate
rstsyncin <= not rstin when acthigh = 1 else rstin;
syncreg0 : syncreg port map (clk, rstsyncin, inrst_syncreg);
genrst <= testrst when (scanen = 1) and (testen = '1') else inrst_syncreg;
gensyncrest : process (clk, genrst) begin
if rising_edge(clk) then
genrst_syncreg(0) <= '1';
genrst_syncreg(1) <= genrst_syncreg(0);
end if;
if ( genrst = '0') then genrst_syncreg <= (others => '0'); end if;
end process;
rst <= genrst_syncreg(1);
syncreg1 : syncreg port map (clk, clklock, clklockl);
end generate;
rstoutraw <= not rstin when acthigh = 1 else rstin;
arst <= testrst when (scanen = 1) and (testen = '1') else rst;
async : if (syncrst = 0 and syncin = 0) generate
reg1 : process (clk, arst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklockl;
rstoutl <= r(4) and r(3) and r(2);
end if;
if (arst = '0') then r <= "00000"; rstoutl <= '0'; end if;
end process;
rstout <= (rstoutl and rst) when scanen = 1 else rstoutl;
end generate;
sync : if (syncrst = 1 or syncin = 1) generate
reg1 : process (clk) begin
if rising_edge(clk) then
r <= (r(3 downto 0) & clklockl) and (rst & rst & rst & rst & rst);
rstoutl <= r(4) and r(3) and r(2);
end if;
end process;
rstout <= rstoutl and rst;
end generate;
end;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! GPIO Core's Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity plasoc_gpio_cntrl is
generic (
constant data_in_width : integer := 16 );
port (
clock : in std_logic;
nreset : in std_logic;
enable : in std_logic;
ack : in std_logic;
int : out std_logic;
data_in_axi : out std_logic_vector(data_in_width-1 downto 0);
data_in_periph : in std_logic_vector(data_in_width-1 downto 0) );
end plasoc_gpio_cntrl;
architecture Behavioral of plasoc_gpio_cntrl is
signal data_in_axi_buff : std_logic_vector(data_in_width-1 downto 0) := (others=>'0');
signal int_buff : std_logic := '0';
begin
data_in_axi <= data_in_axi_buff;
int <= int_buff;
process (clock)
begin
-- Perform operations in synch with positive edge of clock.
if rising_edge(clock) then
-- Reset on low.
if nreset='0' then
int_buff <= '0';
-- Normal operation occurs when reset is high.
else
-- The interrupt operation only occurs when enable is set high.
if enable='1' then
-- If no interrupt is occurring, check for new data.
if int_buff='0' and data_in_axi_buff/=data_in_periph then
-- If new data is available, sample the input and set the interrupt.
data_in_axi_buff <= data_in_periph;
int_buff <= '1';
-- Once the interrupt is acknowledged, set the interrupt to low.
elsif ack='1' then
int_buff <= '0';
end if;
-- If interrupts are not enabled, always register the input.
else
data_in_axi_buff <= data_in_periph;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- $Id: sramif_mig_artys7.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_artys7 - syn
-- Description: SRAM to DDR via MIG for artys7
--
-- Dependencies: bplib/mig/sramif2migui_core
-- cdclib/cdc_pulse
-- cdclib/cdc_value
-- migui_artys7 (generated core)
-- Test bench: -
-- Target Devices: artys7 board
-- Tool versions: viv 2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-12 1105 1.0 Initial version (cloned from sramif_mig_arty)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.miglib.all;
use work.miglib_artys7.all;
entity sramif_mig_artys7 is -- SRAM to DDR via MIG for artys7
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- xadc die temp for mig core
MONI : out sramif2migui_moni_type;-- monitor signals
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sramif_mig_artys7;
architecture syn of sramif_mig_artys7 is
signal MIG_BUSY : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_EN : slbit := '0';
signal APP_CMD : slv3 := (others=>'0');
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_WDF_RDY : slbit := '0';
signal APP_WDF_WREN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal UI_CLK_SYNC_RST : slbit := '0';
signal INIT_CALIB_COMPLETE : slbit := '0';
signal SYS_RST : slbit := '0';
signal SYS_RST_BUSY : slbit := '0';
signal CLKMUI : slbit := '0';
signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
begin
SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => MIG_BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
MONI => MONI,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
CDC_SYSRST: cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => true)
port map (
CLKM => CLK,
RESET => '0',
CLKS => CLKMIG,
PIN => RESET,
BUSY => SYS_RST_BUSY,
POUT => SYS_RST
);
CDC_TEMP: cdc_value
generic map (
DWIDTH => TEMP'length)
port map (
CLKI => CLK,
CLKO => CLKMUI,
DI => TEMP,
DO => TEMP_MUI,
UPDT => open
);
MIG_CTL: migui_artys7
port map (
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => '0',
APP_REF_REQ => '0',
APP_ZQ_REQ => '0',
APP_SR_ACTIVE => open,
APP_REF_ACK => open,
APP_ZQ_ACK => open,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => TEMP_MUI,
SYS_RST => SYS_RST
);
BUSY <= MIG_BUSY or SYS_RST_BUSY;
end syn;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:53:44 11/17/2013
-- Design Name:
-- Module Name: My_32bitAdder_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity My_32bitAdder_948282 is
Port ( A_reg : in STD_LOGIC_VECTOR (31 downto 0);
B_reg : in STD_LOGIC_VECTOR (31 downto 0);
CarryIn : in STD_LOGIC;
CarryOut : out STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0));
end My_32bitAdder_948282;
architecture Behavioral of My_32bitAdder_948282 is
component My_4bitAdder_948282 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
R : out STD_LOGIC_VECTOR (3 downto 0);
Carry_In : in STD_LOGIC;
Carry_Out : out STD_LOGIC);
end component;
signal sig1: std_logic;
signal sig2, sig3, sig4, sig5, sig6, sig7: std_logic;
begin
u0: My_4bitAdder_948282 port map (A=>A_reg(3 downto 0), B=>B_reg(3 downto 0), Carry_In=>CarryIn, Carry_Out=>sig1, R=>Result(3 downto 0));
u1: My_4bitAdder_948282 port map (A=>A_reg(7 downto 4), B=>B_reg(7 downto 4), Carry_In=>sig1, Carry_Out=>sig2, R=>Result(7 downto 4));
u2: My_4bitAdder_948282 port map (A=>A_reg(11 downto 8), B=>B_reg(11 downto 8), Carry_In=>sig2, Carry_Out=>sig3, R=>Result(11 downto 8));
u3: My_4bitAdder_948282 port map (A=>A_reg(15 downto 12), B=>B_reg(15 downto 12), Carry_In=>sig3, Carry_Out=>sig4, R=>Result(15 downto 12));
u4: My_4bitAdder_948282 port map (A=>A_reg(19 downto 16), B=>B_reg(19 downto 16), Carry_In=>sig4, Carry_Out=>sig5, R=>Result(19 downto 16));
u5: My_4bitAdder_948282 port map (A=>A_reg(23 downto 20), B=>B_reg(23 downto 20), Carry_In=>sig5, Carry_Out=>sig6, R=>Result(23 downto 20));
u6: My_4bitAdder_948282 port map (A=>A_reg(27 downto 24), B=>B_reg(27 downto 24), Carry_In=>sig6, Carry_Out=>sig7, R=>Result(27 downto 24));
u7: My_4bitAdder_948282 port map (A=>A_reg(31 downto 28), B=>B_reg(31 downto 28), Carry_In=>sig7, Carry_Out=>CarryOut, R=>Result(31 downto 28));
end Behavioral;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file afifo_64i_16o_s6.vhd when simulating
-- the core, afifo_64i_16o_s6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY afifo_64i_16o_s6 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END afifo_64i_16o_s6;
ARCHITECTURE afifo_64i_16o_s6_a OF afifo_64i_16o_s6 IS
-- synthesis translate_off
COMPONENT wrapped_afifo_64i_16o_s6
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_afifo_64i_16o_s6 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 12,
c_default_value => "BlankString",
c_din_width => 64,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "4kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 4093,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 4092,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 14,
c_rd_depth => 16384,
c_rd_freq => 1,
c_rd_pntr_width => 14,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 12,
c_wr_depth => 4096,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 12,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_afifo_64i_16o_s6
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END afifo_64i_16o_s6_a;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: EX_MEM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY EX_MEM_tb IS
END ENTITY;
ARCHITECTURE EX_MEM_tb_ARCH OF EX_MEM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
EX_MEM_synth_inst:ENTITY work.EX_MEM_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_402 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_402;
architecture augh of cmp_402 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_402 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_402;
architecture augh of cmp_402 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
------------------------------------------------------------------------------------------------
-- Datapath
------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
entity DataPath is
port(
-- INPUTS
clk : in std_logic;
rst : in std_logic;
fromIRAM : in std_logic_vector(31 downto 0); -- data coming from IRAM
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- Control Word + ALU operation for the current instruction decoded
-- from external DRAM
Data_out_fromRAM : in std_logic_vector(31 downto 0); -- data to be read from the DRAM (load op)
--
-- OUTPUTS
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode field in instruction register
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field in instruction register
Addr : out std_logic_vector(31 downto 0); -- address coming from PC (goes to IRAM)
-- to external DRAM
read_op : out std_logic; -- ctrl sig for read operation
write_op : out std_logic; -- ctrl sig for write operation
nibble : out std_logic_vector(1 downto 0); -- specifies which byte of the 32-bit word to access
write_byte : out std_logic; -- if '1' write operation on a single byte
Address_toRAM : out std_logic_vector(31 downto 0); -- address
Data_in : out std_logic_vector(31 downto 0) -- data to be written into the DRAM (store op)
--
);
end DataPath;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
architecture struct of DataPath is
-- component declarations
component fetch is
port (
--INPTUS
jump_address : in std_logic_vector(31 downto 0);
branch_target : in std_logic_vector(31 downto 0);
from_iram : in std_logic_vector(31 downto 0);
flush : in std_logic;
clk : in std_logic;
rst : in std_logic;
pcsrc : in std_logic;
jump : in std_logic;
pcwrite : in std_logic;
--OUTPUTS
to_iram : out std_logic_vector(31 downto 0);
pc_4 : out std_logic_vector(31 downto 0);
instruction_fetch : out std_logic_vector(31 downto 0)
);
end component;
component decode_unit is
port (
-- INPUTS
address_write : in std_logic_vector(4 downto 0); -- register address that should be written
data_write : in std_logic_vector(31 downto 0); -- data to be written in the reg file
pc_4_from_dec : in std_logic_vector(31 downto 0); -- Program counter incremented by 4
instruction : in std_logic_vector(31 downto 0); -- instruction fetched
idex_rt : in std_logic_vector(4 downto 0); -- Rt register coming from the ex stage
clk : in std_logic; -- global clock
rst : in std_logic; -- global reset signal
reg_write : in std_logic; -- Reg Write signal to enable the write operation
idex_mem_read : in std_logic_vector(3 downto 0); -- control signals for Mem Read (lb,lhu, lw, lbu)
cw : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-1 downto 0); -- control word + alu operation produced by the CU
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word + alu operation for the ex stage (-2 since unsigned control signal used i the decode stage)
jump_address : out std_logic_vector(31 downto 0); -- jump address sign-extended
pc_4_to_ex : out std_logic_vector(31 downto 0); -- Program counter incremented by 4 directed to the ex stage
data_read_1 : out std_logic_vector(31 downto 0); -- Output of read port 1 of reg file
data_read_2 : out std_logic_vector(31 downto 0); -- Output of read port 2 of reg file
immediate_ext : out std_logic_vector(31 downto 0); -- Immediate field signe-exntended
immediate : out std_logic_vector(15 downto 0); -- Immediate filed not sign extended (for LUI instruction)
rt : out std_logic_Vector(4 downto 0); -- rt address (instruction 20-16)
rd : out std_logic_vector(4 downto 0); -- rd address (instruction 15-11)
rs : out std_logic_vector(4 downto 0); -- rs address (instruction 25-21)
opcode : out std_logic_vector(OPCODE_SIZE-1 downto 0); -- opcode for the CU, instruction (31-26)
func : out std_logic_vector(FUNC_SIZE-1 downto 0); -- func field of instruction (10-0) to the CU
pcwrite : out std_logic; -- write enable generated by the Hazard Detection Unit for the PC
ifid_write : out std_logic -- write enable generated by the Hazard Detection Unit for the IF/ID pipeline register
);
end component;
component execute is
port(
clk : in std_logic;
rst : in std_logic;
-- inputs from IDEX pipeline reg
controls_in : in std_logic_vector(21 downto 0); -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) is already exhausted in the DECODE stage
ext25_0 : in std_logic_vector(31 downto 0); -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC : in std_logic_vector(31 downto 0);
op_A : in std_logic_vector(31 downto 0);
op_B : in std_logic_vector(31 downto 0);
ext15_0 : in std_logic_vector(31 downto 0); -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 : in std_logic_vector(15 downto 0); -- bits 15_0 of instr.
rt_inst : in std_logic_vector(4 downto 0);
rd_inst : in std_logic_vector(4 downto 0);
rs_inst : in std_logic_vector(4 downto 0);
-- inputs from other sources
unaligned : in std_logic; -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB : in std_logic_vector(31 downto 0); -- data from WB stage that is used if forwarding needed
forw_dataMEM : in std_logic_vector(31 downto 0); -- data from MEM stage that is used if forwarding needed
RFaddr_WB : in std_logic_vector(4 downto 0); -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM : in std_logic_vector(4 downto 0); -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB : in std_logic; -- reg_write ctrl signal from WB stage
regwriteMEM : in std_logic; -- reg_write ctrl signal from MEM stage
-- outputs
controls_out : out std_logic_vector(10 downto 0); -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 : out std_logic_vector(31 downto 0);
toPC2 : out std_logic_vector(31 downto 0);
branchTaken : out std_logic;
addrMem : out std_logic_vector(31 downto 0);
writeData : out std_logic_vector(31 downto 0);
addrRF : out std_logic_vector(4 downto 0);
IDEX_rt : out std_logic_vector(4 downto 0); -- goes to hazard unit
IDEX_memread : out std_logic_vector(3 downto 0) -- goes to hazard unit
);
end component;
component memory is
port(
-- inputs
controls_in : in std_logic_vector(10 downto 0);
PC1_in : in std_logic_vector(31 downto 0);
PC2_in : in std_logic_vector(31 downto 0);
takeBranch : in std_logic;
addrMem : in std_logic_vector(31 downto 0);
writeData : in std_logic_vector(31 downto 0);
RFaddr_in : in std_logic_vector(4 downto 0);
--
Data_out_fromRAM : in std_logic_vector(31 downto 0); -- data to be read from the DRAM (load op)
--
-- outputs
controls_out : out std_logic_vector(2 downto 0);
dataOut_mem : out std_logic_vector(31 downto 0); -- data that has been read directly from memory
dataOut_exe : out std_logic_vector(31 downto 0); -- data that has been produced in exe stage
RFaddr_out : out std_logic_vector(4 downto 0);
unaligned : out std_logic;
PCsrc : out std_logic;
flush : out std_logic;
jump : out std_logic;
PC1_out : out std_logic_vector(31 downto 0);
PC2_out : out std_logic_vector(31 downto 0);
regwrite_MEM : out std_logic; -- goes to forwarding unit
RFaddr_MEM : out std_logic_vector(4 downto 0); -- goes to forwarding unit
forw_addr_MEM : out std_logic_vector(31 downto 0); -- goes to EXE stage and is used if forwarding detected by forwarding unit
--
read_op : out std_logic; -- ctrl sig for read operation
write_op : out std_logic; -- ctrl sig for write operation
nibble : out std_logic_vector(1 downto 0); -- specifies which byte of the 32-bit word to access
write_byte : out std_logic; -- if '1' write operation on a single byte
Address_toRAM : out std_logic_vector(31 downto 0); -- address
Data_in : out std_logic_vector(31 downto 0) -- data to be written into the DRAM (store op)
--
);
end component;
component writeback is
port(
-- inputs
from_mem_data : in std_logic_vector(31 downto 0);
from_alu_data : in std_logic_vector(31 downto 0); -- named from_alu but data can come from other sources as well, but not from memory
regfile_addr_in : in std_logic_vector(4 downto 0); -- address of register to write
regwrite_in : in std_logic; -- control signal (1 -> write in reg file)
link : in std_logic; -- control signal (1 -> link the instruction, save IP in R31)
memtoreg : in std_logic;
-- outputs
regwrite_out : out std_logic; -- control signal (send regwrite signal back to other stages)
regfile_data : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
component ifid_reg is
port (
-- INPUTS
pc_4 : in std_logic_vector(31 downto 0); -- PC + 4 coming from the fetch stage
instruction_fetch : in std_logic_vector(31 downto 0); -- Instruction to be decoded
flush : in std_logic; -- flush control signal
ifid_write : in std_logic; -- write enable
clk : in std_logic; -- clock signal
rst : in std_logic; -- reset signal
-- OUTPUTS
instruction_decode : out std_logic_vector(31 downto 0); -- Instruction for the decode stage
new_pc : out std_logic_vector(31 downto 0) -- PC + 4 directed to the next pipeline register
);
end component;
component idex_reg is
port (
-- INPUTS
cw_to_ex_dec : in std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec : in std_logic_vector(31 downto 0); -- jump address extended
pc_4_dec : in std_logic_vector(31 downto 0); -- PC incremented by 4 from decode
read_data_1_dec : in std_logic_vector(31 downto 0); -- reg 1 read from decode
read_data_2_dec : in std_logic_vector(31 downto 0); -- reg 2 read from decode
immediate_ext_dec : in std_logic_vector(31 downto 0); -- immediate sign extended from decode
immediate_dec : in std_logic_vector(15 downto 0); -- immediate for lui instrucion from decode
rt_dec : in std_logic_vector(4 downto 0); -- rt address from decode
rd_dec : in std_logic_vector(4 downto 0); -- rs address from decode
rs_dec : in std_logic_vector(4 downto 0); -- rd address from decode
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
-- OUTPUTS
cw_to_ex : out std_logic_vector((CW_SIZE+ALUOP_SIZE)-2 downto 0); -- control word for ex stage
jump_address : out std_logic_vector(31 downto 0); -- jump address to ex stage
pc_4 : out std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0);
immediate_ext : out std_logic_vector(31 downto 0);
immediate : out std_logic_vector(15 downto 0);
rt : out std_logic_vector(4 downto 0);
rd : out std_logic_vector(4 downto 0);
rs : out std_logic_vector(4 downto 0)
);
end component;
component EX_MEM_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in : in std_logic_vector(10 downto 0); -- 11 control signals go from exe to mem stage
toPC1_in : in std_logic_vector(31 downto 0); -- from jreg controlled mux
toPC2_in : in std_logic_vector(31 downto 0); -- from adder2
takeBranch_in : in std_logic; -- from Branch circuit, if 1 branch must be taken (if inst. is a branch, see AND in MEM stage)
mem_addr_in : in std_logic_vector(31 downto 0);
mem_writedata_in : in std_logic_vector(31 downto 0);
regfile_addr_in : in std_logic_vector(4 downto 0);
-- output signals
controls_out : out std_logic_vector(10 downto 0);
toPC1_out : out std_logic_vector(31 downto 0);
toPC2_out : out std_logic_vector(31 downto 0);
takeBranch_out : out std_logic;
mem_addr_out : out std_logic_vector(31 downto 0);
mem_writedata_out : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
component MEM_WB_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in : in std_logic_vector(2 downto 0); -- in order, from MSB to LSB : regwrite, link, memtoreg
from_mem_data_in : in std_logic_vector(31 downto 0);
from_alu_data_in : in std_logic_vector(31 downto 0);
regfile_addr_in : in std_logic_vector(4 downto 0);
-- output signals
controls_out : out std_logic_vector(2 downto 0);
from_mem_data_out : out std_logic_vector(31 downto 0);
from_alu_data_out : out std_logic_vector(31 downto 0);
regfile_addr_out : out std_logic_vector(4 downto 0)
);
end component;
-- signal declarations
signal jump_address_i : std_logic_vector(31 downto 0);
signal branch_target_i : std_logic_vector(31 downto 0);
signal flush_i : std_logic;
signal pcsrc_i : std_logic;
signal jump_i : std_logic;
signal pcwrite_i : std_logic;
signal pc_4_i : std_logic_vector(31 downto 0);
signal instruction_fetch_i : std_logic_vector(31 downto 0);
signal instruction_decode_i : std_logic_vector(31 downto 0);
signal new_pc_i : std_logic_vector(31 downto 0);
signal ifid_write_i : std_logic;
signal address_write_i : std_logic_vector(4 downto 0);
signal data_write_i : std_logic_vector(31 downto 0);
signal idex_rt_i : std_logic_vector(4 downto 0);
signal reg_write_i : std_logic;
signal idex_mem_read_i : std_logic_vector(3 downto 0);
signal jaddr_i : std_logic_vector(31 downto 0);
signal pc4_to_idexreg_i : std_logic_vector(31 downto 0);
signal data_read_dec_1_i : std_logic_vector(31 downto 0);
signal data_read_dec_2_i : std_logic_vector(31 downto 0);
signal immediate_ext_dec_i : std_logic_vector(31 downto 0);
signal immediate_dec_i : std_logic_vector(15 downto 0);
signal rt_dec_i : std_logic_vector(4 downto 0);
signal rd_dec_i : std_logic_vector(4 downto 0);
signal rs_dec_i : std_logic_vector(4 downto 0);
signal cw_to_idex_i : std_logic_vector(21 downto 0);
signal cw_to_ex_i : std_logic_vector(21 downto 0);
signal jump_address_toex_i : std_logic_vector(31 downto 0);
signal pc_4_to_ex_i : std_logic_vector(31 downto 0);
signal data_read_ex_1_i : std_logic_vector(31 downto 0);
signal data_read_ex_2_i : std_logic_vector(31 downto 0);
signal immediate_ext_ex_i : std_logic_vector(31 downto 0);
signal immediate_ex_i : std_logic_vector(15 downto 0);
signal rt_ex_i : std_logic_vector(4 downto 0);
signal rd_ex_i : std_logic_vector(4 downto 0);
signal rs_ex_i : std_logic_vector(4 downto 0);
signal unaligned_i : std_logic;
signal forw_dataMEM_i : std_logic_vector(31 downto 0);
signal RFaddr_MEM_i : std_logic_vector(4 downto 0);
signal regwriteMEM_i : std_logic;
signal cw_exmem_i : std_logic_vector(10 downto 0);
signal toPC1_i : std_logic_vector(31 downto 0);
signal toPC2_i : std_logic_vector(31 downto 0);
signal branchTaken_i : std_logic;
signal addrMem_exmem_i : std_logic_vector(31 downto 0);
signal writeData_exmem_i : std_logic_vector(31 downto 0);
signal addrRF_exmem_i : std_logic_vector(4 downto 0);
signal cw_tomem_i : std_logic_vector(10 downto 0);
signal PC1_tomem_i : std_logic_vector(31 downto 0);
signal PC2_tomem_i : std_logic_vector(31 downto 0);
signal takeBranch_out_i : std_logic;
signal mem_addr_out_i : std_logic_vector(31 downto 0);
signal mem_writedata_out_i : std_logic_vector(31 downto 0);
signal regfile_addr_out_tomem_i : std_logic_vector(4 downto 0);
signal cw_memwb_i : std_logic_vector(2 downto 0);
signal dataOut_mem_i : std_logic_vector(31 downto 0);
signal dataOut_exe_i : std_logic_vector(31 downto 0);
signal RFaddr_out_memwb_i : std_logic_vector(4 downto 0);
signal cw_towb_i : std_logic_vector(2 downto 0);
signal from_mem_data_out_i : std_logic_vector(31 downto 0);
signal from_alu_data_out_i : std_logic_vector(31 downto 0);
signal regfile_addr_out_towb_i : std_logic_vector(4 downto 0);
begin
-- component instantiations
u_fetch: fetch
port map (
--INPTUS
jump_address => jump_address_i,
branch_target => branch_target_i,
from_iram => fromIRAM,
flush => flush_i,
clk => clk,
rst => rst,
pcsrc => pcsrc_i,
jump => jump_i,
pcwrite => pcwrite_i,
--OUTPUTS
to_iram => Addr,
pc_4 => pc_4_i,
instruction_fetch => instruction_fetch_i
);
u_ifidreg : ifid_reg port map(
-- INPUTS
pc_4 => pc_4_i, -- PC + 4 coming from the fetch stage
instruction_fetch => instruction_fetch_i, -- Instruction to be decoded
flush => flush_i, -- flush control signal
ifid_write => ifid_write_i, -- write enable
clk => clk, -- clock signal
rst => rst, -- reset signal
-- OUTPUTS
instruction_decode => instruction_decode_i, -- Instruction for the decode stage
new_pc => new_pc_i -- PC + 4 directed to the next pipeline register
);
u_decode_unit: decode_unit
port map (
-- INPUTS
address_write => address_write_i, -- regter address that should be written
data_write => data_write_i, -- data to be written in the reg file
pc_4_from_dec => new_pc_i, -- Program counter incremented by 4
instruction => instruction_decode_i, -- instruction fetched
idex_rt => idex_rt_i, -- Rt regter coming from the ex stage
clk => clk, -- global clock
rst => rst, -- global reset signal
reg_write => reg_write_i, -- Reg Write signal to enable the write operation
idex_mem_read => idex_mem_read_i, -- control signals for Mem Read (lb,lhu, lw, lbu)
cw => cw, -- control word + alu operation produced by the CU
-- OUTPUTS
cw_to_ex => cw_to_idex_i, -- control word + alu operation for the ex stage (-2 since unsigned control signal used i the decode stage)
jump_address => jaddr_i, -- jump address sign-extended
pc_4_to_ex => pc4_to_idexreg_i, -- Program counter incremented by 4 directed to the ex stage
data_read_1 => data_read_dec_1_i, -- Output of read port 1 of reg file
data_read_2 => data_read_dec_2_i, -- Output of read port 2 of reg file
immediate_ext => immediate_ext_dec_i, -- Immediate field signe-exntended
immediate => immediate_dec_i, -- Immediate filed not sign extended (for LUI instruction)
rt => rt_dec_i, -- rt address (instruction 20-16)
rd => rd_dec_i, -- rd address (instruction 15-11)
rs => rs_dec_i, -- rs address (instruction 25-21)
opcode => opcode, -- opcode for the CU, instruction (31-26)
func => func, -- func field of instruction (10-0) to the CU
pcwrite => pcwrite_i, -- write enable generated by the Hazard Detection Unit for the PC
ifid_write => ifid_write_i -- write enable generated by the Hazard Detection Unit for the IF/ID pipeline regter
);
u_idexreg: idex_reg port map(
-- INPUTS
cw_to_ex_dec => cw_to_idex_i, -- control word directed to the ex stage (note -2 since unsigned control signal is alredy used in decode thus no need to propagate)
jump_address_dec => jaddr_i, -- jump address extended
pc_4_dec => pc4_to_idexreg_i, -- PC incremented by 4 from decode
read_data_1_dec => data_read_dec_1_i, -- reg 1 read from decode
read_data_2_dec => data_read_dec_2_i, -- reg 2 read from decode
immediate_ext_dec => immediate_ext_dec_i, -- immediate sign extended from decode
immediate_dec => immediate_dec_i, -- immediate for lui instrucion from decode
rt_dec => rt_dec_i, -- rt address from decode
rd_dec => rd_dec_i, -- rs address from decode
rs_dec => rs_dec_i, -- rd address from decode
clk => clk, -- global clock signal
rst => rst, -- global reset signal
-- OUTPUTS
cw_to_ex => cw_to_ex_i, -- control word for ex stage
jump_address => jump_address_toex_i, -- jump address to ex stage
pc_4 => pc_4_to_ex_i,
read_data_1 => data_read_ex_1_i,
read_data_2 => data_read_ex_2_i,
immediate_ext => immediate_ext_ex_i,
immediate => immediate_ex_i,
rt => rt_ex_i,
rd => rd_ex_i,
rs => rs_ex_i
);
u_execute: execute
port map (
clk => clk,
rst => rst,
-- inputs from IDEX pipeline reg
controls_in => cw_to_ex_i, -- we have 22 signals: CU generates a total of 23 signals (including 5 ALUOP signals), but 1 signal (unsigned) already exhausted in the DECODE stage
ext25_0 => jump_address_toex_i, -- bits 25_0 of instr. sign/unsign extended to 32 bits
nextPC => pc_4_to_ex_i,
op_A => data_read_ex_1_i,
op_B => data_read_ex_2_i,
ext15_0 => immediate_ext_ex_i, -- bits 15_0 of instr. sign/unsign extended to 32 bits
inst15_0 => immediate_ex_i, -- bits 15_0 of instr.
rt_inst => rt_ex_i,
rd_inst => rd_ex_i,
rs_inst => rs_ex_i,
-- inputs from other sources
unaligned => unaligned_i, -- from MMU, '1' when an unaligned access to memory has been done
forw_dataWB => data_write_i, -- data from WB stage that used if forwarding needed
forw_dataMEM => forw_dataMEM_i, -- data from MEM stage that used if forwarding needed
RFaddr_WB => address_write_i, -- addr of RF from WB stage, goes to forwarding unit
RFaddr_MEM => RFaddr_MEM_i, -- addr of RF from MEM stage, goes to forwarding unit
regwriteWB => reg_write_i, -- reg_write ctrl signal from WB stage
regwriteMEM => regwriteMEM_i, -- reg_write ctrl signal from MEM stage
-- outputs
controls_out => cw_exmem_i, -- 11 control signals go to MEM stage (11 are exhausted in the EXE stage)
toPC1 => toPC1_i,
toPC2 => toPC2_i,
branchTaken => branchTaken_i,
addrMem => addrMem_exmem_i,
writeData => writeData_exmem_i,
addrRF => addrRF_exmem_i,
IDEX_rt => idex_rt_i, -- goes to hazard unit
IDEX_memread => idex_mem_read_i -- goes to hazard unit
);
u_exmemreg: EX_MEM_Reg port map (
-- input signals
clk => clk, -- clock source
rst => rst, -- reset signal
controls_in => cw_exmem_i, -- 11 control signals go from exe to mem stage
toPC1_in => toPC1_i, -- from jreg controlled mux
toPC2_in => toPC2_i, -- from adder2
takeBranch_in => branchTaken_i, -- from Branch circuit, if 1 branch must be taken (if inst. is a branch, see AND in MEM stage)
mem_addr_in => addrMem_exmem_i,
mem_writedata_in => writeData_exmem_i,
regfile_addr_in => addrRF_exmem_i,
-- output signals
controls_out => cw_tomem_i,
toPC1_out => PC1_tomem_i,
toPC2_out => PC2_tomem_i,
takeBranch_out => takeBranch_out_i,
mem_addr_out => mem_addr_out_i,
mem_writedata_out => mem_writedata_out_i,
regfile_addr_out => regfile_addr_out_tomem_i
);
u_memory: memory
port map (
-- inputs
controls_in => cw_tomem_i,
PC1_in => PC1_tomem_i,
PC2_in => PC2_tomem_i,
takeBranch => takeBranch_out_i,
addrMem => mem_addr_out_i,
writeData => mem_writedata_out_i,
RFaddr_in => regfile_addr_out_tomem_i,
--
Data_out_fromRAM => Data_out_fromRAM, -- data to be read from the DRAM (load op)
--
-- outputs
controls_out => cw_memwb_i,
dataOut_mem => dataOut_mem_i, -- data that has been read directly from memory
dataOut_exe => dataOut_exe_i, -- data that has been produced in exe stage
RFaddr_out => RFaddr_out_memwb_i,
unaligned => unaligned_i,
PCsrc => pcsrc_i,
flush => flush_i,
jump => jump_i,
PC1_out => jump_address_i,
PC2_out => branch_target_i,
regwrite_MEM => regwriteMEM_i, -- goes to forwarding unit
RFaddr_MEM => RFaddr_MEM_i, -- goes to forwarding unit
forw_addr_MEM => forw_dataMEM_i, -- goes to EXE stage and used if forwarding detected by forwarding unit
--
read_op => read_op, -- ctrl sig for read operation
write_op => write_op, -- ctrl sig for write operation
nibble => nibble, -- specifies which byte of the 32-bit word to access
write_byte => write_byte, -- if '1' write operation on a single byte
Address_toRAM => Address_toRAM, -- address
Data_in => Data_in -- data to be written into the DRAM (store op)
--
);
u_memwbreg: MEM_WB_Reg port map (
clk => clk, -- clock source
rst => rst, -- reset signal
controls_in => cw_memwb_i, -- in order, from MSB to LSB : regwrite, link, memtoreg
from_mem_data_in => dataOut_mem_i,
from_alu_data_in => dataOut_exe_i,
regfile_addr_in => RFaddr_out_memwb_i,
-- output signals
controls_out => cw_towb_i,
from_mem_data_out => from_mem_data_out_i,
from_alu_data_out => from_alu_data_out_i,
regfile_addr_out => regfile_addr_out_towb_i
);
u_writeback: writeback
port map (
-- inputs
from_mem_data => from_mem_data_out_i,
from_alu_data => from_alu_data_out_i, -- named from_alu but data can come from other sources as well, but not from memory
regfile_addr_in => regfile_addr_out_towb_i, -- address of regter to write
regwrite_in => cw_towb_i(2), -- control signal (1 -> write in reg file)
link => cw_towb_i(1), -- control signal (1 -> link the instruction, save IP in R31)
memtoreg => cw_towb_i(0),
-- outputs
regwrite_out => reg_write_i, -- control signal (send regwrite signal back to other stages)
regfile_data => data_write_i,
regfile_addr_out => address_write_i
);
end struct;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks13@live.com)
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks13@live.com)
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks13@live.com)
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS DARTMOUTH
-- Engineer: CHRISTOPHER PARKS (cparks13@live.com)
--
-- Create Date: 14:45:47 03/31/2016
-- Design Name:
-- Module Name: word_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity word_unit is
Port ( DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
IMMAddr : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0); -- Pass OP(2) to this (OP=0=Load, OP=1=Write)
RESULT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (7 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0));
end word_unit;
architecture Combinational of word_unit is
signal WREN : STD_LOGIC_VECTOR(0 downto 0) := "0";
begin
DST_ADR <= IMMAddr;
STORE_DATA <= DATAIN;
WREN <= "0" when OP = x"9" else -- x"9" is load word
"1" when OP = x"A"; -- x"A" is store word
DATAMEMORY : entity work.DATAMEM port map(ADDRA => IMMAddr,
DINA => DATAIN,
WEA => WREN, -- Write enable
CLKA => CLK,
DOUTA => RESULT);
-- When OP = 1 then WRITE is enabled, IMMAddr gives us the address to write to, DATAIN gives us the data to write. RESULT will soon show data written if untouched
-- When OP = 0 then WRITE is disabled, DATAIN is ignored, IMMAddr gives us the address to read from, and RESULT is set to the RESULT.
end Combinational;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_outputMem_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END blk_mem_gen_outputMem_top;
ARCHITECTURE xilinx OF blk_mem_gen_outputMem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_outputMem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : blk_mem_gen_outputMem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
-- NEED RESULT: ARCH00556: Variable declarations - scalar static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00556
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (7)
-- 4.3.1.3 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00556)
-- ENT00556_Test_Bench(ARCH00556_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00556 of E00000 is
begin
process
variable correct : boolean := true ;
variable va_boolean_1 : boolean
:= c_boolean_1 ;
variable va_bit_1 : bit
:= c_bit_1 ;
variable va_severity_level_1 : severity_level
:= c_severity_level_1 ;
variable va_character_1 : character
:= c_character_1 ;
variable va_t_enum1_1 : t_enum1
:= c_t_enum1_1 ;
variable va_st_enum1_1 : st_enum1
:= c_st_enum1_1 ;
variable va_integer_1 : integer
:= c_integer_1 ;
variable va_t_int1_1 : t_int1
:= c_t_int1_1 ;
variable va_st_int1_1 : st_int1
:= c_st_int1_1 ;
variable va_time_1 : time
:= c_time_1 ;
variable va_t_phys1_1 : t_phys1
:= c_t_phys1_1 ;
variable va_st_phys1_1 : st_phys1
:= c_st_phys1_1 ;
variable va_real_1 : real
:= c_real_1 ;
variable va_t_real1_1 : t_real1
:= c_t_real1_1 ;
variable va_st_real1_1 : st_real1
:= c_st_real1_1 ;
begin
correct := correct and va_boolean_1 = c_boolean_1 ;
correct := correct and va_bit_1 = c_bit_1 ;
correct := correct and va_severity_level_1 = c_severity_level_1 ;
correct := correct and va_character_1 = c_character_1 ;
correct := correct and va_t_enum1_1 = c_t_enum1_1 ;
correct := correct and va_st_enum1_1 = c_st_enum1_1 ;
correct := correct and va_integer_1 = c_integer_1 ;
correct := correct and va_t_int1_1 = c_t_int1_1 ;
correct := correct and va_st_int1_1 = c_st_int1_1 ;
correct := correct and va_time_1 = c_time_1 ;
correct := correct and va_t_phys1_1 = c_t_phys1_1 ;
correct := correct and va_st_phys1_1 = c_st_phys1_1 ;
correct := correct and va_real_1 = c_real_1 ;
correct := correct and va_t_real1_1 = c_t_real1_1 ;
correct := correct and va_st_real1_1 = c_st_real1_1 ;
va_boolean_1 := c_boolean_2 ;
va_bit_1 := c_bit_2 ;
va_severity_level_1 := c_severity_level_2 ;
va_character_1 := c_character_2 ;
va_t_enum1_1 := c_t_enum1_2 ;
va_st_enum1_1 := c_st_enum1_2 ;
va_integer_1 := c_integer_2 ;
va_t_int1_1 := c_t_int1_2 ;
va_st_int1_1 := c_st_int1_2 ;
va_time_1 := c_time_2 ;
va_t_phys1_1 := c_t_phys1_2 ;
va_st_phys1_1 := c_st_phys1_2 ;
va_real_1 := c_real_2 ;
va_t_real1_1 := c_t_real1_2 ;
va_st_real1_1 := c_st_real1_2 ;
correct := correct and va_boolean_1 = c_boolean_2 ;
correct := correct and va_bit_1 = c_bit_2 ;
correct := correct and va_severity_level_1 = c_severity_level_2 ;
correct := correct and va_character_1 = c_character_2 ;
correct := correct and va_t_enum1_1 = c_t_enum1_2 ;
correct := correct and va_st_enum1_1 = c_st_enum1_2 ;
correct := correct and va_integer_1 = c_integer_2 ;
correct := correct and va_t_int1_1 = c_t_int1_2 ;
correct := correct and va_st_int1_1 = c_st_int1_2 ;
correct := correct and va_time_1 = c_time_2 ;
correct := correct and va_t_phys1_1 = c_t_phys1_2 ;
correct := correct and va_st_phys1_1 = c_st_phys1_2 ;
correct := correct and va_real_1 = c_real_2 ;
correct := correct and va_t_real1_1 = c_t_real1_2 ;
correct := correct and va_st_real1_1 = c_st_real1_2 ;
test_report ( "ARCH00556" ,
"Variable declarations - scalar static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00556 ;
--
entity ENT00556_Test_Bench is
end ENT00556_Test_Bench ;
--
architecture ARCH00556_Test_Bench of ENT00556_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00556 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00556_Test_Bench ;
|
entity sub is
generic ( N : natural );
end entity;
architecture test of sub is
type rec is record
x : natural;
y : bit_vector(1 to N);
z : natural;
end record;
type rec2 is record
x : natural;
y : rec;
z : natural;
end record;
function func (q : bit_vector) return natural is
type rec3 is record
x : natural;
y : bit_vector(1 to q'length);
z : natural;
end record;
variable r : rec3;
begin
r := ( 1, q, q'length );
r.y(1) := '1';
for i in r.y'range loop
if i = 1 then
assert r.y(i) = '1';
else
assert r.y(i) = '0';
end if;
end loop;
return r.z;
end function;
signal s : rec;
signal s2 : rec2;
begin
p1: process is
variable r : rec;
begin
assert r = (0, (1 to N => '0'), 0);
r.y(1) := '1';
assert r.y = (1 => '1', 2 to 4 => '0');
assert func(r.y) = N;
assert s = (0, (1 to N => '0'), 0);
s.y(1) <= '1';
wait for 1 ns;
assert s.y = (1 => '1', 2 to 4 => '0');
assert s2 = (0, (0, (1 to N => '0'), 0), 0);
s2.y.y(1) <= '1';
wait for 1 ns;
assert s2.y.y = (1 => '1', 2 to 4 => '0');
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
entity record14 is
end entity;
architecture test of record14 is
begin
sub_i: entity work.sub generic map ( 4 );
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity ball is
end entity ball;
----------------------------------------------------------------
architecture bouncer of ball is
quantity v : velocity := 0.0;
quantity s : displacement := 10.0;
constant g : real := 9.81;
constant air_res : real := 0.1;
begin
if v'above(0.0) use
v'dot == -g - v**2*air_res;
else
v'dot == -g + v**2*air_res;
end use;
reversal_tester : process is
begin
wait on s'above(0.0);
break v => -v when s < 0.0;
end process reversal_tester;
s'dot == v;
end architecture bouncer;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity ball is
end entity ball;
----------------------------------------------------------------
architecture bouncer of ball is
quantity v : velocity := 0.0;
quantity s : displacement := 10.0;
constant g : real := 9.81;
constant air_res : real := 0.1;
begin
if v'above(0.0) use
v'dot == -g - v**2*air_res;
else
v'dot == -g + v**2*air_res;
end use;
reversal_tester : process is
begin
wait on s'above(0.0);
break v => -v when s < 0.0;
end process reversal_tester;
s'dot == v;
end architecture bouncer;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity ball is
end entity ball;
----------------------------------------------------------------
architecture bouncer of ball is
quantity v : velocity := 0.0;
quantity s : displacement := 10.0;
constant g : real := 9.81;
constant air_res : real := 0.1;
begin
if v'above(0.0) use
v'dot == -g - v**2*air_res;
else
v'dot == -g + v**2*air_res;
end use;
reversal_tester : process is
begin
wait on s'above(0.0);
break v => -v when s < 0.0;
end process reversal_tester;
s'dot == v;
end architecture bouncer;
|
--sync.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.game.all;
entity sync is
port(clk_s:in std_logic;
r_shift,l_shift,start,resetgame,pause:in std_logic;
level_select:in std_logic_vector(2 downto 0);
hsync,vsync:out std_logic;
r,g,b:out std_logic_vector(3 downto 0));
end sync;
architecture sync_arch of sync is
signal notstarted:std_logic:='1';--to check if game is not yet started and to display welcome message
signal hpos:integer range 1 to 800:=1;--pixel position including fp, bp and hsync
signal vpos:integer range 1 to 525:=1;--pixel position including fp,bp and vsync
signal hpos_scr:integer range 1 to 640:=1;--cursor position on screen
signal vpos_scr:integer range 1 to 480:=1;--cursor position on screen
signal r_bat,g_bat,b_bat,r_ball,g_ball,b_ball,r_gameover,g_gameover,b_gameover,r_lives,b_lives,g_lives,r_welmes,g_welmes,b_welmes,r_winmes,g_winmes,b_winmes,r_paused,g_paused,b_paused:std_logic_vector(3 downto 0);--rgb signals
signal draw_bat:std_logic; --validity signals
signal isalive:integer:=3;--to check if lives are over
signal bat_x:integer:=275; --starting x coordinate for bat
signal bat_y:integer:=460; --y coordinate of bat is fixed
signal ball_x:integer:=299;--starting coordinates for ball
signal ball_y:integer:=450;
signal lives_x:integer:=550;--fixed coordinates to display lives
signal lives_y:integer:=0;
signal welmes_x:integer:=72;--fixed coordinates to display welcome message
signal welmes_y:integer:=45;
signal gameover_x:integer:=84;--fixed coordinates to display gameover
signal gameover_y:integer:=195;
signal winmes_x:integer:=90;--fixed coordinates to display winning message
signal winmes_y:integer:=175;
signal paused_x:integer:=128;--fixed coordinates to display paused message
signal paused_y:integer:=202;
signal rand_x:integer range 26 to 611:=26;--used to randomly assign x cood to bat and ball;
signal stopball:std_logic:='0';--to stop the ball after gameover or game has been won
signal l2notstarted,l3notstarted,l4notstarted,l5notstarted:std_logic:='1';--to reposition bat,ball and give initial velocity to ball at start of each level except 1st
signal l1complete,l2complete,l3complete,l4complete,l5complete:std_logic:='0';--to say that level is completed
signal level_selected:std_logic:='0';--to select level at start of the game
type rom_lives is array (24 downto 0)of std_logic_vector(91 downto 0);-- ROM definition of lives
signal lives_row,lives_col: integer;--signals required by lives ROM
signal lives_single_row: std_logic_vector(91 downto 0);
signal lives_validity_bit: std_logic;
type rom_gameover is array (89 downto 0)of std_logic_vector(471 downto 0);--ROM definition of gameover
signal gameover_row,gameover_col: integer;--signals required by gameover ROM
signal gameover_single_row: std_logic_vector(471 downto 0);
signal gameover_validity_bit: std_logic;
type rom_welmes is array (389 downto 0)of std_logic_vector(495 downto 0);--ROM definition of welcome message
signal welmes_row,welmes_col: integer;--signals required by welcome ROM
signal welmes_single_row: std_logic_vector(495 downto 0);
signal welmes_validity_bit: std_logic;
type rom_paused is array (75 downto 0)of std_logic_vector(383 downto 0);--ROM definition of pause message
signal paused_row,paused_col: integer;--signals required by pause ROM
signal paused_single_row: std_logic_vector(383 downto 0);
signal paused_validity_bit: std_logic;
type rom_winmes is array (129 downto 0)of std_logic_vector(459 downto 0);--ROM definition of winning message
signal winmes_row,winmes_col: integer;--signals required by win ROM
signal winmes_single_row: std_logic_vector(459 downto 0);
signal winmes_validity_bit: std_logic;
type rom_ball is array (12 downto 0)of std_logic_vector(12 downto 0);-- ROM definition of ball
signal ball_row,ball_col: integer;--signals required by ball ROM
signal ball_single_row: std_logic_vector(12 downto 0);
signal ball_validity_bit: std_logic;
signal ball_x_vel:std_logic:='1';--used to change ball movements in x and y direction after hitting a wall or brick
signal ball_y_vel:std_logic:='0';
signal ball_x_vel_rand:std_logic:='0';
type brick_cood is array (71 downto 0) of integer;--array to store coordinates of bricks
type brick_color is array (71 downto 0) of std_logic_vector(3 downto 0);--array to give color to each brick
signal x_cood_l1:brick_cood:=--x coordinates of bricks in level1
(20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580,
20,100,180,260,340,420,500,580);
signal y_cood_l1:brick_cood:=--y coordinates of bricks in level1
(25,25,25,25,25,25,25,25,
65,65,65,65,65,65,65,65,
105,105,105,105,105,105,105,105,
145,145,145,145,145,145,145,145,
185,185,185,185,185,185,185,185,
225,225,225,225,225,225,225,225,
265,265,265,265,265,265,265,265,
305,305,305,305,305,305,305,305,
345,345,345,345,345,345,345,345);
signal x_cood_l2:brick_cood:=--x coordinates of bricks in level2
(40,80,120,160,200,240,280,
560,520,480,440,400,360,320,
280,240,200,160,120,80,40,
320,360,400,440,480,520,560,others=>0);
signal y_cood_l2:brick_cood:=--y coordinates of bricks in level2
(40,60,80,100,120,140,160,
40,60,80,100,120,140,160,
180,200,220,240,260,280,300,
180,200,220,240,260,280,300,others=>0);
signal x_cood_l3:brick_cood:=--x coordinates of bricks in level3
(300,260,220,180,140,100,60,20,
340,380,420,460,500,540,580,
300,260,220,180,140,100,60,20,
340,380,420,460,500,540,580,
300,260,220,180,140,100,
340,380,420,460,500,
300,260,220,180,140,100,
340,380,420,460,500,
300,260,220,180,
340,380,420,
300,260,220,180,
340,380,420,
300,260,
340,
300,260,
340);
signal y_cood_l3:brick_cood:=--y coordinates of bricks in level3
(25,45,65,85,105,125,145,165,
45,65,85,105,125,145,165,
325,305,285,265,245,225,205,185,
305,285,265,245,225,205,185,
65,85,105,125,145,165,
85,105,125,145,165,
285,265,245,225,205,185,
265,245,225,205,185,
105,125,145,165,
125,145,165,
245,225,205,185,
225,205,185,
145,165,
165,
205,185,
185);
signal x_cood_l4:brick_cood:=--x coordinates of bricks in level4
(40,80,120,160,200,240,280,
560,520,480,440,400,360,320,
280,240,200,160,120,80,40,
320,360,400,440,480,520,560,
40,40,40,40,40,40,40,40,40,
560,560,560,560,560,560,560,560,560,
100,150,200,250,300,350,400,450,500,
100,150,200,250,300,350,400,450,500,others=>0);
signal y_cood_l4:brick_cood:=--y coordinates of bricks in level4
(40,60,80,100,120,140,160,
40,60,80,100,120,140,160,
180,200,220,240,260,280,300,
180,200,220,240,260,280,300,
70,95,120,145,170,195,220,245,270,
70,95,120,145,170,195,220,245,270,
40,40,40,40,40,40,40,40,40,
300,300,300,300,300,300,300,300,300,others=>0);
signal x_cood_l5:brick_cood:=--x coordinates of bricks in level5
(20,60,100,140,180,220,260,
340,380,420,460,500,540,580,
140,140,140,140,140,140,140,140,140,140,140,
460,460,460,460,460,460,460,460,460,460,460,others=>0);
signal y_cood_l5:brick_cood:=--y coordinates of bricks in level5
(85,65,45,25,45,65,85,
85,65,45,25,45,65,85,
65,90,115,140,165,190,215,240,265,290,315,
65,90,115,140,165,190,215,240,265,290,315,others=>0);
signal is_destroyed_l1,coll_x_l1,coll_y_l1,draw_l1:std_logic_vector(71 downto 0):=x"000000000000000000";--for level 1
signal is_destroyed_l2,coll_x_l2,coll_y_l2,draw_l2:std_logic_vector(71 downto 44):=x"0000000";--for level 2
signal is_destroyed_l3,coll_x_l3,coll_y_l3,draw_l3:std_logic_vector(71 downto 0):=x"000000000000000000";--for level 3
signal is_destroyed_l4,coll_x_l4,coll_y_l4,draw_l4:std_logic_vector(71 downto 8):=x"0000000000000000";--for level 4
signal is_destroyed_l5,coll_x_l5,coll_y_l5,draw_l5:std_logic_vector(71 downto 36):=x"000000000";--for level 5
signal r_brick,g_brick,b_brick:brick_color;--rgb for bricks
constant lives0_rom: rom_lives:= --lives 0 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"000780f0038747c020f3ffe",
x"0018c318038cc9e07073078",
x"0018c318038c40e07072078",
x"0038e71c000e00707872078",
x"0038e71c000f0070b870078",
x"0038e71c0007cff0b870078",
x"0038e71c0003cc711c70078",
x"0038e71c0388cc611c70078",
x"0038e71c038cc6e31e70078",
x"0038e71c038b8387bf70078",
x"0038e71c000000000000078",
x"0018c318000000000060078",
x"0018c318000000000070078",
x"000780f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant lives1_rom: rom_lives:= --lives 1 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"001fc0f0038747c020f3ffe",
x"00070318038cc9e07073078",
x"00070318038c40e07072078",
x"0007071c000e00707872078",
x"0007071c000f0070b870078",
x"0007071c0007cff0b870078",
x"0007071c0003cc711c70078",
x"0007071c0388cc611c70078",
x"0007071c038cc6e31e70078",
x"0007071c038b8387bf70078",
x"0007071c000000000000078",
x"0007c318000000000060078",
x"00078318000000000070078",
x"000600f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant lives2_rom: rom_lives:= --lives 2 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"001fe0f0038747c020f3ffe",
x"001fc318038cc9e07073078",
x"003fc318038c40e07072078",
x"0020871c000e00707872078",
x"0001071c000f0070b870078",
x"0002071c0007cff0b870078",
x"0006071c0003cc711c70078",
x"000c071c0388cc611c70078",
x"001c071c038cc6e31e70078",
x"001c071c038b8387bf70078",
x"001c071c000000000000078",
x"001e2318000000000060078",
x"000fc318000000000070078",
x"000780f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant lives3_rom: rom_lives := --lives 3 image
(
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"0007e0f0038747c020f3ffe",
x"0008f318038cc9e07073078",
x"00186318038c40e07072078",
x"0038071c000e00707872078",
x"0038071c000f0070b870078",
x"003c071c0007cff0b870078",
x"003e071c0003cc711c70078",
x"001f871c0388cc611c70078",
x"0006071c038cc6e31e70078",
x"001c071c038b8387bf70078",
x"001c071c000000000000078",
x"001e2318000000000060078",
x"001fc318000000000070078",
x"000f80f00000000000601fe",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000",
x"00000000000000000000000"
);
constant winmes_rom: rom_winmes:= --winning image
(
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000780000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000fc0000000000000000000000000000000000",
x"00000000000000000000000000000000000000000000000000000000000000000000000000000013c0000000000000000000000000000000000",
x"00000000000000000000000000000000000000000000000000000000000000000000000000000013c0000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000002380000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000006000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000004000000000000000000000000000000000000",
x"008003fcffefff83fe00ff800fff83fe0001fff81fff07fcfffffc00fff80007e00f000001fc004000f81fff1ffe0007cc1f303e001ff003ffe",
x"00c000f03f83fc007807fff003fc007800003f8007f800f0fffff0001fe0001e781f800007ff00e003fe07fc07f0000e3c38f0ff800fc0007f8",
x"00e000603f81fc00301f81f801fc003000003f8003f80060f80fe0000fc0003c3c27c0001fff00e0063f03fc03f0001c1c70718fc007c0003f0",
x"00f000601f80fc00203f007e00fc002000001f8001f80040e007e0000fc0007c3c07c0003c3f01f0001f81fc03f0003c0cf03007e007c0003f0",
x"00f800601f80fe00603f003f00fe006000001f8001fc00c0c007e0000fc0007c3e07c000381f01f0080f80fe03f0003e04f81203e007c0003f0",
x"00f800601f80fe00403f003f80fe004000001f8001fc0080c007e0000fc0007c3e07c000780701f8000f807f03f0003f00fc0003e007c0003f0",
x"00fc00601f807e00c03f001f807e00c000001f8000fc01818007e0000fc000fc3f07c000700003f8000fc07f83f0003fc0ff0003f007c0003f0",
x"00fe00601f807fffc03f001fc07fffc000001f8000ffff818007e0000fc000f83f07c000f80002fc0007c03f83f0001fe07f8001f007c0003f0",
x"00ff00601f803fff803f000fc03fff8000001f80007fff010007e0000fc000f83f07c000f80006fc0007c01fc3f0001ff07fc001f007c0003f0",
x"00ff80601f803f81807f800fc03f818000001f80007f03000007e0000fc000f83f07c000f800047c0fffc00fe3f0000ff83fe3fff007c0003f0",
x"00ffc0601f801f8101ffe00fc01f810000003f80003f02000007e0000fc000f83f07c000fc00047e0f07c007f3f00003f80fe3c1f007c0003f0",
x"00dfc0601f801f830000000fe01f830000003fc0003f06000007e003ffc0007c3e07c000ff00083e0f078007fff00001fc07f3c1e00fc00fff0",
x"00dfe0601f801fc20000000fe01fc20000006fc0003f84000007e01fffc0007c3e07c0007fc0083f0f078003fff000107c41f3c1e30fc07fff0",
x"00cff0601f800fc60000000fc00fc60000004fe0001f8c000007e03f8fc0007c3c07c0003ff0181f070f0001fff000183860e1c3c78fc0fe3f0",
x"00c7f8601f800fe60000000fc00fe6000000c7e0001fcc000007e07e0fc0003c3c07c0001fc0181f878f0000f3f0001c3870e1e3c7d7c1f83f0",
x"00c3fc601f8007ec0000000fc007ec00000187f0000fd8000007e07e0fc0001e787ff8000f00381fc39e0000e3f0001e3078c0e787e7c1f83f0",
x"00c1fe601f8007fc0000001fc007fc00000183f0000ff8000007e0fc0fc00007e07fe0001e007e3fe0f8000183f00013e04f803e03c7f3f03f0",
x"00c0fe601f8003f80020001f8003f800000301f80007f0000007e0fc0fc000000007c0003e0000000000000303f0000000000000000003f03f0",
x"00c0ff601f8003f80030001f8003f800000201fc0007f0000007e0fc0fc00000000780003e0000000000000603f0000000000000000003f03f0",
x"00c07fe01f8003f00030003f0003f000000600fc0007e0000007e0fc0fc00000000700003e0000000000001c03f0000000000000000003f03f0",
x"00c03fe01f8001f00038003e0001f000000c00fe0003e0000007e0fe0fc00000000600007e0200000000003803f0000000000000000003f83f0",
x"00c01fe01f8001f0003e007c0001f000000c007e0003e0000007e07e0fc00000000600003f0600000000006003f0000000000000000001f83f0",
x"00c00fe03f8000e0003f81f80000e000001c007f0001c0000007e03f8fc00000000400003ffc0000000001e003f0000000000000000000fe3f0",
x"01e00ff83f8000e00033ffe00000e000003c007f8001c000000ff01fffe00000000000001ff80000000003e007f00000000000000000007fff8",
x"07f807feffe0004000207f8000004000007f01ffe0008000007ffc07fff800000000000007e0000000000ff81ffe0000000000000000001fffe",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"001fffff7ffe0c0ff7ffc1ff007fc000001f01ff7fc3c00008003fc007fc00001000c000001f0001001e0f0fffbffe003f9f800fc001fff8000",
x"003ffff80ff00c03c1fe003c03fff800007fc07c3f07e0000c000f001fff00003800c000007fc003807f7f83fc07f8000fffc03cf0003f80000",
x"003e03f807e00e0180fe00180fc0fc0000c7e07c1f09f0000e0006007e0fc0003801c00000c7e003801f9f81f803f0000fe7c07878003f80000",
x"003801f807e01e01807e00101f803f000003f07c1f01f0000f000600fc07e0003801e0000003f007c01f0f81f803f0000fc3e0f878001f80000",
x"003001f807e01f01807f00301f801f800101f07c1f01f0000f800601f803f0007c03e0000101f007c01f0f81f803f0000f83e0f87c001f80000",
x"002001f807e03f01807f00201f801fc00001f07c1f01f0000f800603f001f8007c03f0000001f007c01f0f81f803f0000f83e0f87c001f80000",
x"002041f807e03f81803f00601f800fc00001f87c1f01f0000fc00603f001f800fc03f0000001f80fe01f0f01f803f0000f83e1f87e001f80000",
x"002041f807e07f81803fffe01f800fe00000f87c1f01f0000fe00607e001fc00fe07f0000000f80be01f1c01f803f0000f83e1f07e001f80000",
x"000041f807e07fc1801fffc01f8007e00000f87c1f01f0000ff00607e000fc00fe07f8000000f813f01f3801f803f0000f83e1f07e001f80000",
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);
constant gameover_rom: rom_gameover:= --gameover image
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);
constant welmes_rom: rom_welmes:= --welcome message image
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x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000ff81f03f9ff0f07807c003fe01ffff003f9ff03e07fc07fc03fffe000000000000000000000000000000000000",
x"00000000000000000000000000000000007e07fc1f8fe3fbfc1ff001f807fff8001f8fe0ff81f803f00ffff0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e0c7e0f87c0fcfc31f800f81fe1f8000f87c10fc1f001f03fc3f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e003f0f87c0f87c00fc00f83f81f8000f87c207e1f001f07f03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e101f07c7c0f87c407c00f83f01f80007c7c007e1f001f07e03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e001f07e7c0f87c007c00f87f01f80007e7c003e1f001f0fe03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e001f83e7c0f878007e00f87f01f80003e7c003f1f001f0fe03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e000f81ffc0f8e0003e00f87f01f80001ffc003f1f001f0fe03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e000f81ffc0f9c0003e00f87f01f80001ffc001f1f001f0fe03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e1fff80f7c0ff007ffe00f83f01f80000f7c001f1f001f07e03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000003e1e0f8067c0f878783e00f81f81f8000067c001f1f001f03f03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000007e1e0f0047c0f87c783c01f80fe1f8000047c001e1f003f01fc3f0000000000000000000000000000000000000",
x"00000000000000000000000000000000187e1e0f0087c0f87c783c61f807fff8000087c1c1e1f0c3f00ffff0000000000000000000000000000000000000",
x"000000000000000000000000000000003c7e0e1e0107c0f87c3878f1f801fff8000107c3e3c1f1e3f003fff0000000000000000000000000000000000000",
x"000000000000000000000000000000003ebe0f1e0307c0f8383c78faf807e1f8000307c3e3c1f1f5f00fc3f0000000000000000000000000000000000000",
x"000000000000000000000000000000003f3e073c0707c07c701cf0fcf80fc1f8000707c1e781f9f9f01f83f0000000000000000000000000000000000000",
x"000000000000000000000000000000001e3f81f01fc7c01fc007c078fe1f81f8001fc7c07e01fcf1fc3f03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007c00000000000003f81f8000007c000000000007f03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007c00000000000003f81f8000007c000000000007f03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007c00000000000003f81f8000007c000000000007f03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007c00000000000001f81f8000007c00000e000003f03f0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007c00000000000001fc1f8000007c00001f000003f83f0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007c00000000000000fe1f8000007c00001f800001fc3f0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007e000000000000007fff8000007e00001f000000ffff0000000000000000000000000000000000000",
x"00000000000000000000000000000000000000000007f000000000000001ffff000007f00000e0000003fffe000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
constant paused_rom: rom_paused :=
(
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000003ff8000c00000001fff800000000000000000000000000000000000000",
x"00000000fffffffff807fffffffffffff00001ffff000c0000001fffff8000007fffffff0001fffff0000007fffffffc",
x"0000001ffffffffff807fffffffffffff00007ffffe01c0000007fffffe000007fffffff0001fffff0000007fffffffc",
x"000000fffffffffe0007fffffffffffe00001ff00ff87c000001fffffff800001fffffc000001fffc00000003fffff00",
x"000003ffe03ffffc0007fff0007ffff800007fc001fffc000003f803fffc000007ffff80000003ff000000000ffffc00",
x"00000fff000ffff8000fff80003ffff00000ff00007ffc000007c000ffff000003ffff00000001fe0000000007fffc00",
x"00003ffe000ffff0000ffe00001fffe00001fe00003ffc00001f80003fff800001ffff00000001fc0000000007fff800",
x"00007ff8000ffff0000ff800001fffe00003fc00000ffc00001e00001fff800000ffff00000001f80000000003fff800",
x"0001fff0000ffff0000ff000001fffe00007fc000007fc00003c00000fffc00000ffff80000001f80000000003fff800",
x"0003fff0000ffff0000fe000000fffe00007f8000003fc00007800000fffe000007fff80000001f00000000003fff800",
x"0007ffe0000ffff0000fc000000fffe0000ff8000001fc0000f8000007ffe000007fffc0000001f00000000003fff800",
x"000fffc0000ffff0000f8000000fffe0000ff8000001fc0000f0000007fff000003fffc0000001e00000000003fff800",
x"001fffc0000ffff0001f0000000fffe0001ff8000000fc0001f0000007fff000003fffc0000003e00000000003fff800",
x"001fff80000ffff0001e0000000fffe0001ff80000007c0001e0000003fff800001fffe0000003c00000000003fff800",
x"003fff80000ffff0001e0000000fffe0001ff80000007c0001e0000003fff800001fffe0000007c00000000003fff800",
x"007fff80000ffff0001c0000000fffe0003ff80000003c0001e0000003fff800000ffff0000007800000000003fff800",
x"007fff00000ffff0001c0000000fffe0003ffc0000003c0003c0000003fff800000ffff0000007800000000003fff800",
x"00ffff00000ffff00018000c000fffe0003ffc0000001c0003c0000003fff800000ffff800000f000000000003fff800",
x"00ffff00000ffff00018000c000fffe0003ffe0000001c0003c0000003fff8000007fff800000f000000000003fff800",
x"01fffe00000ffff00038000e000fffe0003fff0000001c0003c0000003fffc000007fffffffffe000000000003fff800",
x"01fffe00000ffff00030000e000fffe0003fff8000000c0003c0000003fffc000003fffffffffe000000000003fff800",
x"01fffe00000ffff00000000e000fffe0003fffc000000c0003c0000003fffc000003fffffffffc000000000003fff800",
x"03fffe00000ffff00000000e000fffe0003ffff000000c0003c0000003fffc000001fffffffffc000000000003fff800",
x"03fffe00000ffff00000000f000fffe0003ffff800000c0003c0000003fffc000001fffe00007c000000000003fff800",
x"03fffe00000ffff00000000f000fffe0001ffffe0000000003c0000003fffc000001ffff000078000000000003fff800",
x"03fffc00000ffff00000000f000fffe0001fffff8000000003c0000003fffc000000ffff000078000000000003fff800",
x"07fffc00000ffff00000000f800fffe0001fffffe000000003c0000003fffc000000ffff0000f0000000000003fff800",
x"07fffc00000ffff00000000f800fffe0000ffffff800000003c0000003fffc0000007fff8000f0000000000003fff800",
x"07fffc00000ffff00000000fc00fffe0000ffffffe00000003c0000003fffc0000007fff8001e0000000000003fff800",
x"07fffc00000ffff00000000fe00fffe00007ffffff80000003c0000003fffc0000003fffc001e0000000000003fff800",
x"07fffc00000ffff00000000ff00fffe00003ffffffc0000003c0000003fffc0000003fffc003c0000000000003fff800",
x"07fffc00000ffff00000000ffe0fffe00001fffffff0000003c0000003fffc0000001fffe003c0000000003ffffff800",
x"07fffc00000ffff00000000fffffffe00000fffffff8000003c0000003fffc0000001fffe007c000000007fffffff800",
x"07fffc00000ffff00000000fffffffe000007ffffffe000003c0000003fffc0000001fffe007800000003ffffffff800",
x"07fffc00000ffff00000000fffffffe000003fffffff000003c0000003fffc0000000ffff00f80000000fffe03fff800",
x"07fffc00000ffff00000000ffe0fffe000001fffffff800003c0000003fffc0000000ffff00f00000001fff803fff800",
x"07fffc00000ffff00000000ff00fffe0000007ffffffc00003c0000003fffc00000007fff80f00000007fff003fff800",
x"07fffc00000ffff00000000fe00fffe0000001ffffffe00003c0000003fffc00000007fff81e0000000fffe003fff800",
x"07fffc00000ffff00000000fc00fffe0000000ffffffe00003c0000003fffc00000003fffc1e0000001fffc003fff800",
x"07fffc00000ffff00000000f800fffe00000003ffffff00003c0000003fffc00000003fffc3c0000001fff8003fff800",
x"03fffe00000ffff00000000f800fffe00000000ffffff00003c0000003fffc00000003fffc3c0000003fff8003fff800",
x"03fffe00000ffff00000000f000fffe000000003fffff80003c0000003fffc00000001fffe7c0000007fff8003fff800",
x"03fffe00000ffff00000000f000fffe000000000fffff80003c0000003fffc00000001fffe780000007fff0003fff800",
x"03fffe00000ffff00000000f000fffe0000000003ffffc0003c0000003fffc00000000fffff80000007fff0003fff800",
x"01fffe00000ffff00000000e000fffe0000000000ffffc0003c0000003fffc00000000fffff0000000ffff0003fff800",
x"01fffe00000ffff00000000e000fffe00003000007fffc0003c0000003fffc000000007ffff0000000ffff0003fff800",
x"01ffff00000ffff00001800e000fffe00003000001fffc0003c0000003fffc000000007fffe0000000ffff0003fff800",
x"00ffff00000ffff00001800e000fffe00003000000fffc0003c0000003fffc000000007fffe0000000ffff0003fff800",
x"00ffff00000ffff00001800c000fffe000038000007ffc0003c0000003fffc000000003fffc0000000ffff0003fff800",
x"007fff80000ffff00001800c000fffe000038000003ffc0003c0000003fffc000000003fffc0000000ffff0003fff800",
x"007fff80000ffff00001c000000fffe000038000001ffc0003c0000003fffc000000001fffc0000000ffff0003fff800",
x"003fff80000ffff00001c000000fffe00003c000001ffc0003c0000003fffc000000001fff80000000ffff0003fff800",
x"001fffc0000ffff00001e000000fffe00003c000000ffc0003c0000003fffc000000000fff80000000ffff0003fff800",
x"001fffc0000ffff00001e000000fffe00003e000000ff80003c0000003fffc000000000fff000000007fff0003fff800",
x"000fffe0000ffff00001f000000fffe00003e000000ff80003c0000003fffc000000000fff000000007fff0003fff800",
x"0007fff0000ffff00001f000000fffe00003f000000ff00003c0000003fffc0000000007fe000000003fff8003fff800",
x"0003fff0000ffff00001f800000fffe00003f800000ff00007c0000003fffc0000000007fe000000003fff8003fff800",
x"0001fff8000ffff00001fc00000fffe00003fc00001fe00007c0000003fffc0000000003fc000000001fffc003fff800",
x"0000fffc000ffff00001ff00000fffe00003fe00001fe00007c0000003fffc0000000003fc000000000fffe003fff800",
x"00003fff000ffff00001ffc0000fffe00003ff00003fc00007c0000003fffc0000000001fc0000000007fff003fff800",
x"00001fff800ffff80001fff8000ffff00003ffc0007f80000fe0000003fffc0000000001f80000000003fff803fffc00",
x"000007fff80ffffc0001fffffffffff80003ffe000ff00001ff0000007fffe0000000000f80000000000ffff03fffc00",
x"000000fffffffffe0001fffffffffffe000387fc07fe00007ffc00001fffff8000000000f000000000003fffffffff00",
x"0000001ffffffffff801fffffffffffff00380fffff80007ffffe007fffffffc00000000f0000000000007fffffffffc",
x"00000000fffffffff801fffffffffffff003003fffe00007ffffe007fffffffc00000000600000000000003ffffffffc",
x"0000000000000000000000000000000000030007ff000000000000000000000000000000600000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
x"000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"
);
constant ball_rom: rom_ball :=
(
"0000000000000",
"0000000000000",
"0000000000000",
"0000111110000",
"0001111111000",
"0011111111100",
"0011111111100",
"0011111111100",
"0011111111100",
"0001111111000",
"0000111110000",
"0000000000000",
"0000000000000"
);
begin
ball_single_row <= ball_rom(ball_row);--to determine which pixel to color with ball color
ball_validity_bit <= ball_single_row(ball_col);
r_ball<="0000";--ball color
g_ball<="1111";
b_ball<="0000";
welmes_single_row <= welmes_rom(welmes_row);--to determine which pixel to color with welcome message color
welmes_validity_bit <= welmes_single_row(welmes_col);
r_welmes<="1111";--welcome message color
g_welmes<="1111";
b_welmes<="0000";
paused_single_row <= paused_rom(paused_row);--to determine which pixel to color with pause message color
paused_validity_bit <= paused_single_row(paused_col);
r_paused<="1111";--pause message color
g_paused<="1000";
b_paused<="0000";
winmes_single_row <= winmes_rom(winmes_row);--to determine which pixel to color with win message color
winmes_validity_bit <= winmes_single_row(winmes_col);
r_winmes<="0000";--win message color
g_winmes<="0000";
b_winmes<="1111";
gameover_single_row <= gameover_rom(gameover_row);--to determine which pixel to color with gameover message color
gameover_validity_bit <= gameover_single_row(gameover_col);
r_gameover<="1111";--gameover message color
g_gameover<="0000";
b_gameover<="0000";
lives_single_row <=lives3_rom(lives_row)when isalive=3 else--to determine which pixel to color with lives message color
lives2_rom(lives_row)when isalive=2 else
lives1_rom(lives_row)when isalive=1 else
lives0_rom(lives_row);
lives_validity_bit <= lives_single_row(lives_col);
r_lives<="0000";--lives message color
g_lives<="1111";
b_lives<="1111";
hpos_scr<=hpos-152 when (hpos>152 and hpos<793)else
1;--bring x and y position inside screen by
vpos_scr<=vpos-37 when (vpos>37 and vpos<518)else
1;--subtracting fp,bp and sync period
process(clk_s)--process to generate random postion of x for ball and bat
begin
if(clk_s'event and clk_s='0') then
ball_x_vel_rand<=not ball_x_vel_rand;
if(rand_x=611)then
rand_x<=26;
else
rand_x<=rand_x+3;
end if;
end if;
end process;
process(clk_s)--main synchronization process
begin
if(clk_s'event and clk_s='1') then
if(resetgame='0') then--to reset game after key3 has been pressed
notstarted<='1';
isalive<=3;
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
is_destroyed_l1<=x"000000000000000000";
coll_x_l1<=x"000000000000000000";
coll_y_l1<=x"000000000000000000";
is_destroyed_l2<=x"0000000";
coll_x_l2<=x"0000000";
coll_y_l2<=x"0000000";
is_destroyed_l3<=x"000000000000000000";
coll_x_l3<=x"000000000000000000";
coll_y_l3<=x"000000000000000000";
is_destroyed_l4<=x"0000000000000000";
coll_x_l4<=x"0000000000000000";
coll_y_l4<=x"0000000000000000";
is_destroyed_l5<=x"000000000";
coll_x_l5<=x"000000000";
coll_y_l5<=x"000000000";
l1complete<='0';
l2complete<='0';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='1';
l3notstarted<='1';
l4notstarted<='1';
l5notstarted<='1';
level_selected<='0';
stopball<='0';
else
null;
end if;
if(level_selected='0')then--to select level at the start of the game
case level_select is
when "010"=>l1complete<='1';
l2complete<='0';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='1';
l4notstarted<='1';
l5notstarted<='1';
when "011"=>l1complete<='1';
l2complete<='1';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='0';
l4notstarted<='1';
l5notstarted<='1';
when "100"=>l1complete<='1';
l2complete<='1';
l3complete<='1';
l4complete<='0';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='0';
l4notstarted<='0';
l5notstarted<='1';
when "101"=>l1complete<='1';
l2complete<='1';
l3complete<='1';
l4complete<='1';
l5complete<='0';
l2notstarted<='0';
l3notstarted<='0';
l4notstarted<='0';
l5notstarted<='0';
when others=>l1complete<='0';
l2complete<='0';
l3complete<='0';
l4complete<='0';
l5complete<='0';
l2notstarted<='1';
l3notstarted<='1';
l4notstarted<='1';
l5notstarted<='1';
end case;
else
null;
end if;
if(l2notstarted='1'and is_destroyed_l1=x"ffffffffffffffffff")then--to start level 2
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l1complete<='1';
l2notstarted<='0';
elsif(l3notstarted='1'and is_destroyed_l2=x"fffffff")then--to start level 3
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l2complete<='1';
l3notstarted<='0';
elsif(l4notstarted='1'and is_destroyed_l3=x"ffffffffffffffffff")then--to start level 4
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l3complete<='1';
l4notstarted<='0';
elsif(l5notstarted='1'and is_destroyed_l4=x"ffffffffffffffff")then--to start level 5
ball_x<=rand_x;
ball_y<=450;
bat_x<=rand_x-25;
bat_y<=460;
ball_x_vel<=ball_x_vel_rand;
ball_y_vel<='0';
l4complete<='1';
l5notstarted<='0';
elsif(is_destroyed_l5=x"fffffffff")then--to complete level 5
l5complete<='1';
else
null;
end if;
if(start='0' and level_select/="000" and level_select/="110" and level_select/="111") then--start the game and stop level selection only if valid level is selected
notstarted<='0';
level_selected<='1';
else
null;
end if;
if(notstarted='0') then
if(l1complete='0')then--display bricks of level 1
brick(hpos_scr,vpos_scr,x_cood_l1(71),y_cood_l1(71),ball_x,ball_y,draw_l1(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l1(71),coll_y_l1(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(70),y_cood_l1(70),ball_x,ball_y,draw_l1(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l1(70),coll_y_l1(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(69),y_cood_l1(69),ball_x,ball_y,draw_l1(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l1(69),coll_y_l1(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(68),y_cood_l1(68),ball_x,ball_y,draw_l1(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l1(68),coll_y_l1(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(67),y_cood_l1(67),ball_x,ball_y,draw_l1(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l1(67),coll_y_l1(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(66),y_cood_l1(66),ball_x,ball_y,draw_l1(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l1(66),coll_y_l1(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(65),y_cood_l1(65),ball_x,ball_y,draw_l1(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l1(65),coll_y_l1(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(64),y_cood_l1(64),ball_x,ball_y,draw_l1(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l1(64),coll_y_l1(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(63),y_cood_l1(63),ball_x,ball_y,draw_l1(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l1(63),coll_y_l1(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(62),y_cood_l1(62),ball_x,ball_y,draw_l1(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l1(62),coll_y_l1(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(61),y_cood_l1(61),ball_x,ball_y,draw_l1(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l1(61),coll_y_l1(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(60),y_cood_l1(60),ball_x,ball_y,draw_l1(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l1(60),coll_y_l1(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(59),y_cood_l1(59),ball_x,ball_y,draw_l1(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l1(59),coll_y_l1(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(58),y_cood_l1(58),ball_x,ball_y,draw_l1(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l1(58),coll_y_l1(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(57),y_cood_l1(57),ball_x,ball_y,draw_l1(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l1(57),coll_y_l1(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(56),y_cood_l1(56),ball_x,ball_y,draw_l1(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l1(56),coll_y_l1(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(55),y_cood_l1(55),ball_x,ball_y,draw_l1(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l1(55),coll_y_l1(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(54),y_cood_l1(54),ball_x,ball_y,draw_l1(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l1(54),coll_y_l1(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(53),y_cood_l1(53),ball_x,ball_y,draw_l1(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l1(53),coll_y_l1(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(52),y_cood_l1(52),ball_x,ball_y,draw_l1(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l1(52),coll_y_l1(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(51),y_cood_l1(51),ball_x,ball_y,draw_l1(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l1(51),coll_y_l1(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(50),y_cood_l1(50),ball_x,ball_y,draw_l1(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l1(50),coll_y_l1(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(49),y_cood_l1(49),ball_x,ball_y,draw_l1(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l1(49),coll_y_l1(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(48),y_cood_l1(48),ball_x,ball_y,draw_l1(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l1(48),coll_y_l1(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(47),y_cood_l1(47),ball_x,ball_y,draw_l1(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l1(47),coll_y_l1(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(46),y_cood_l1(46),ball_x,ball_y,draw_l1(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l1(46),coll_y_l1(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(45),y_cood_l1(45),ball_x,ball_y,draw_l1(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l1(45),coll_y_l1(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(44),y_cood_l1(44),ball_x,ball_y,draw_l1(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l1(44),coll_y_l1(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(43),y_cood_l1(43),ball_x,ball_y,draw_l1(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l1(43),coll_y_l1(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(42),y_cood_l1(42),ball_x,ball_y,draw_l1(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l1(42),coll_y_l1(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(41),y_cood_l1(41),ball_x,ball_y,draw_l1(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l1(41),coll_y_l1(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(40),y_cood_l1(40),ball_x,ball_y,draw_l1(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l1(40),coll_y_l1(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(39),y_cood_l1(39),ball_x,ball_y,draw_l1(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l1(39),coll_y_l1(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(38),y_cood_l1(38),ball_x,ball_y,draw_l1(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l1(38),coll_y_l1(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(37),y_cood_l1(37),ball_x,ball_y,draw_l1(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l1(37),coll_y_l1(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(36),y_cood_l1(36),ball_x,ball_y,draw_l1(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l1(36),coll_y_l1(36),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(35),y_cood_l1(35),ball_x,ball_y,draw_l1(35),r_brick(35),g_brick(35),b_brick(35),coll_x_l1(35),coll_y_l1(35),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(34),y_cood_l1(34),ball_x,ball_y,draw_l1(34),r_brick(34),g_brick(34),b_brick(34),coll_x_l1(34),coll_y_l1(34),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(33),y_cood_l1(33),ball_x,ball_y,draw_l1(33),r_brick(33),g_brick(33),b_brick(33),coll_x_l1(33),coll_y_l1(33),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(32),y_cood_l1(32),ball_x,ball_y,draw_l1(32),r_brick(32),g_brick(32),b_brick(32),coll_x_l1(32),coll_y_l1(32),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(31),y_cood_l1(31),ball_x,ball_y,draw_l1(31),r_brick(31),g_brick(31),b_brick(31),coll_x_l1(31),coll_y_l1(31),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(30),y_cood_l1(30),ball_x,ball_y,draw_l1(30),r_brick(30),g_brick(30),b_brick(30),coll_x_l1(30),coll_y_l1(30),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(29),y_cood_l1(29),ball_x,ball_y,draw_l1(29),r_brick(29),g_brick(29),b_brick(29),coll_x_l1(29),coll_y_l1(29),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(28),y_cood_l1(28),ball_x,ball_y,draw_l1(28),r_brick(28),g_brick(28),b_brick(28),coll_x_l1(28),coll_y_l1(28),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(27),y_cood_l1(27),ball_x,ball_y,draw_l1(27),r_brick(27),g_brick(27),b_brick(27),coll_x_l1(27),coll_y_l1(27),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(26),y_cood_l1(26),ball_x,ball_y,draw_l1(26),r_brick(26),g_brick(26),b_brick(26),coll_x_l1(26),coll_y_l1(26),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(25),y_cood_l1(25),ball_x,ball_y,draw_l1(25),r_brick(25),g_brick(25),b_brick(25),coll_x_l1(25),coll_y_l1(25),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(24),y_cood_l1(24),ball_x,ball_y,draw_l1(24),r_brick(24),g_brick(24),b_brick(24),coll_x_l1(24),coll_y_l1(24),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(23),y_cood_l1(23),ball_x,ball_y,draw_l1(23),r_brick(23),g_brick(23),b_brick(23),coll_x_l1(23),coll_y_l1(23),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(22),y_cood_l1(22),ball_x,ball_y,draw_l1(22),r_brick(22),g_brick(22),b_brick(22),coll_x_l1(22),coll_y_l1(22),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(21),y_cood_l1(21),ball_x,ball_y,draw_l1(21),r_brick(21),g_brick(21),b_brick(21),coll_x_l1(21),coll_y_l1(21),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(20),y_cood_l1(20),ball_x,ball_y,draw_l1(20),r_brick(20),g_brick(20),b_brick(20),coll_x_l1(20),coll_y_l1(20),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(19),y_cood_l1(19),ball_x,ball_y,draw_l1(19),r_brick(19),g_brick(19),b_brick(19),coll_x_l1(19),coll_y_l1(19),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(18),y_cood_l1(18),ball_x,ball_y,draw_l1(18),r_brick(18),g_brick(18),b_brick(18),coll_x_l1(18),coll_y_l1(18),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(17),y_cood_l1(17),ball_x,ball_y,draw_l1(17),r_brick(17),g_brick(17),b_brick(17),coll_x_l1(17),coll_y_l1(17),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(16),y_cood_l1(16),ball_x,ball_y,draw_l1(16),r_brick(16),g_brick(16),b_brick(16),coll_x_l1(16),coll_y_l1(16),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(15),y_cood_l1(15),ball_x,ball_y,draw_l1(15),r_brick(15),g_brick(15),b_brick(15),coll_x_l1(15),coll_y_l1(15),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(14),y_cood_l1(14),ball_x,ball_y,draw_l1(14),r_brick(14),g_brick(14),b_brick(14),coll_x_l1(14),coll_y_l1(14),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(13),y_cood_l1(13),ball_x,ball_y,draw_l1(13),r_brick(13),g_brick(13),b_brick(13),coll_x_l1(13),coll_y_l1(13),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(12),y_cood_l1(12),ball_x,ball_y,draw_l1(12),r_brick(12),g_brick(12),b_brick(12),coll_x_l1(12),coll_y_l1(12),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(11),y_cood_l1(11),ball_x,ball_y,draw_l1(11),r_brick(11),g_brick(11),b_brick(11),coll_x_l1(11),coll_y_l1(11),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(10),y_cood_l1(10),ball_x,ball_y,draw_l1(10),r_brick(10),g_brick(10),b_brick(10),coll_x_l1(10),coll_y_l1(10),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(9),y_cood_l1(9),ball_x,ball_y,draw_l1(9),r_brick(9),g_brick(9),b_brick(9),coll_x_l1(9),coll_y_l1(9),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(8),y_cood_l1(8),ball_x,ball_y,draw_l1(8),r_brick(8),g_brick(8),b_brick(8),coll_x_l1(8),coll_y_l1(8),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(7),y_cood_l1(7),ball_x,ball_y,draw_l1(7),r_brick(7),g_brick(7),b_brick(7),coll_x_l1(7),coll_y_l1(7),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(6),y_cood_l1(6),ball_x,ball_y,draw_l1(6),r_brick(6),g_brick(6),b_brick(6),coll_x_l1(6),coll_y_l1(6),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(5),y_cood_l1(5),ball_x,ball_y,draw_l1(5),r_brick(5),g_brick(5),b_brick(5),coll_x_l1(5),coll_y_l1(5),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(4),y_cood_l1(4),ball_x,ball_y,draw_l1(4),r_brick(4),g_brick(4),b_brick(4),coll_x_l1(4),coll_y_l1(4),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(3),y_cood_l1(3),ball_x,ball_y,draw_l1(3),r_brick(3),g_brick(3),b_brick(3),coll_x_l1(3),coll_y_l1(3),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(2),y_cood_l1(2),ball_x,ball_y,draw_l1(2),r_brick(2),g_brick(2),b_brick(2),coll_x_l1(2),coll_y_l1(2),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(1),y_cood_l1(1),ball_x,ball_y,draw_l1(1),r_brick(1),g_brick(1),b_brick(1),coll_x_l1(1),coll_y_l1(1),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l1(0),y_cood_l1(0),ball_x,ball_y,draw_l1(0),r_brick(0),g_brick(0),b_brick(0),coll_x_l1(0),coll_y_l1(0),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l2complete='0')then--display bricks of level 2
brick(hpos_scr,vpos_scr,x_cood_l2(71),y_cood_l2(71),ball_x,ball_y,draw_l2(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l2(71),coll_y_l2(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(70),y_cood_l2(70),ball_x,ball_y,draw_l2(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l2(70),coll_y_l2(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(69),y_cood_l2(69),ball_x,ball_y,draw_l2(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l2(69),coll_y_l2(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(68),y_cood_l2(68),ball_x,ball_y,draw_l2(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l2(68),coll_y_l2(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(67),y_cood_l2(67),ball_x,ball_y,draw_l2(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l2(67),coll_y_l2(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(66),y_cood_l2(66),ball_x,ball_y,draw_l2(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l2(66),coll_y_l2(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(65),y_cood_l2(65),ball_x,ball_y,draw_l2(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l2(65),coll_y_l2(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(64),y_cood_l2(64),ball_x,ball_y,draw_l2(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l2(64),coll_y_l2(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(63),y_cood_l2(63),ball_x,ball_y,draw_l2(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l2(63),coll_y_l2(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(62),y_cood_l2(62),ball_x,ball_y,draw_l2(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l2(62),coll_y_l2(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(61),y_cood_l2(61),ball_x,ball_y,draw_l2(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l2(61),coll_y_l2(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(60),y_cood_l2(60),ball_x,ball_y,draw_l2(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l2(60),coll_y_l2(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(59),y_cood_l2(59),ball_x,ball_y,draw_l2(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l2(59),coll_y_l2(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(58),y_cood_l2(58),ball_x,ball_y,draw_l2(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l2(58),coll_y_l2(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(57),y_cood_l2(57),ball_x,ball_y,draw_l2(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l2(57),coll_y_l2(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(56),y_cood_l2(56),ball_x,ball_y,draw_l2(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l2(56),coll_y_l2(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(55),y_cood_l2(55),ball_x,ball_y,draw_l2(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l2(55),coll_y_l2(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(54),y_cood_l2(54),ball_x,ball_y,draw_l2(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l2(54),coll_y_l2(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(53),y_cood_l2(53),ball_x,ball_y,draw_l2(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l2(53),coll_y_l2(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(52),y_cood_l2(52),ball_x,ball_y,draw_l2(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l2(52),coll_y_l2(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(51),y_cood_l2(51),ball_x,ball_y,draw_l2(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l2(51),coll_y_l2(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(50),y_cood_l2(50),ball_x,ball_y,draw_l2(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l2(50),coll_y_l2(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(49),y_cood_l2(49),ball_x,ball_y,draw_l2(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l2(49),coll_y_l2(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(48),y_cood_l2(48),ball_x,ball_y,draw_l2(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l2(48),coll_y_l2(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(47),y_cood_l2(47),ball_x,ball_y,draw_l2(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l2(47),coll_y_l2(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(46),y_cood_l2(46),ball_x,ball_y,draw_l2(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l2(46),coll_y_l2(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(45),y_cood_l2(45),ball_x,ball_y,draw_l2(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l2(45),coll_y_l2(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l2(44),y_cood_l2(44),ball_x,ball_y,draw_l2(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l2(44),coll_y_l2(44),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l3complete='0')then--display bricks of level 3
brick(hpos_scr,vpos_scr,x_cood_l3(71),y_cood_l3(71),ball_x,ball_y,draw_l3(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l3(71),coll_y_l3(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(70),y_cood_l3(70),ball_x,ball_y,draw_l3(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l3(70),coll_y_l3(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(69),y_cood_l3(69),ball_x,ball_y,draw_l3(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l3(69),coll_y_l3(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(68),y_cood_l3(68),ball_x,ball_y,draw_l3(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l3(68),coll_y_l3(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(67),y_cood_l3(67),ball_x,ball_y,draw_l3(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l3(67),coll_y_l3(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(66),y_cood_l3(66),ball_x,ball_y,draw_l3(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l3(66),coll_y_l3(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(65),y_cood_l3(65),ball_x,ball_y,draw_l3(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l3(65),coll_y_l3(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(64),y_cood_l3(64),ball_x,ball_y,draw_l3(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l3(64),coll_y_l3(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(63),y_cood_l3(63),ball_x,ball_y,draw_l3(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l3(63),coll_y_l3(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(62),y_cood_l3(62),ball_x,ball_y,draw_l3(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l3(62),coll_y_l3(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(61),y_cood_l3(61),ball_x,ball_y,draw_l3(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l3(61),coll_y_l3(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(60),y_cood_l3(60),ball_x,ball_y,draw_l3(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l3(60),coll_y_l3(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(59),y_cood_l3(59),ball_x,ball_y,draw_l3(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l3(59),coll_y_l3(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(58),y_cood_l3(58),ball_x,ball_y,draw_l3(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l3(58),coll_y_l3(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(57),y_cood_l3(57),ball_x,ball_y,draw_l3(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l3(57),coll_y_l3(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(56),y_cood_l3(56),ball_x,ball_y,draw_l3(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l3(56),coll_y_l3(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(55),y_cood_l3(55),ball_x,ball_y,draw_l3(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l3(55),coll_y_l3(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(54),y_cood_l3(54),ball_x,ball_y,draw_l3(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l3(54),coll_y_l3(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(53),y_cood_l3(53),ball_x,ball_y,draw_l3(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l3(53),coll_y_l3(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(52),y_cood_l3(52),ball_x,ball_y,draw_l3(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l3(52),coll_y_l3(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(51),y_cood_l3(51),ball_x,ball_y,draw_l3(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l3(51),coll_y_l3(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(50),y_cood_l3(50),ball_x,ball_y,draw_l3(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l3(50),coll_y_l3(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(49),y_cood_l3(49),ball_x,ball_y,draw_l3(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l3(49),coll_y_l3(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(48),y_cood_l3(48),ball_x,ball_y,draw_l3(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l3(48),coll_y_l3(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(47),y_cood_l3(47),ball_x,ball_y,draw_l3(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l3(47),coll_y_l3(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(46),y_cood_l3(46),ball_x,ball_y,draw_l3(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l3(46),coll_y_l3(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(45),y_cood_l3(45),ball_x,ball_y,draw_l3(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l3(45),coll_y_l3(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(44),y_cood_l3(44),ball_x,ball_y,draw_l3(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l3(44),coll_y_l3(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(43),y_cood_l3(43),ball_x,ball_y,draw_l3(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l3(43),coll_y_l3(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(42),y_cood_l3(42),ball_x,ball_y,draw_l3(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l3(42),coll_y_l3(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(41),y_cood_l3(41),ball_x,ball_y,draw_l3(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l3(41),coll_y_l3(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(40),y_cood_l3(40),ball_x,ball_y,draw_l3(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l3(40),coll_y_l3(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(39),y_cood_l3(39),ball_x,ball_y,draw_l3(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l3(39),coll_y_l3(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(38),y_cood_l3(38),ball_x,ball_y,draw_l3(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l3(38),coll_y_l3(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(37),y_cood_l3(37),ball_x,ball_y,draw_l3(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l3(37),coll_y_l3(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(36),y_cood_l3(36),ball_x,ball_y,draw_l3(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l3(36),coll_y_l3(36),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(35),y_cood_l3(35),ball_x,ball_y,draw_l3(35),r_brick(35),g_brick(35),b_brick(35),coll_x_l3(35),coll_y_l3(35),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(34),y_cood_l3(34),ball_x,ball_y,draw_l3(34),r_brick(34),g_brick(34),b_brick(34),coll_x_l3(34),coll_y_l3(34),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(33),y_cood_l3(33),ball_x,ball_y,draw_l3(33),r_brick(33),g_brick(33),b_brick(33),coll_x_l3(33),coll_y_l3(33),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(32),y_cood_l3(32),ball_x,ball_y,draw_l3(32),r_brick(32),g_brick(32),b_brick(32),coll_x_l3(32),coll_y_l3(32),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(31),y_cood_l3(31),ball_x,ball_y,draw_l3(31),r_brick(31),g_brick(31),b_brick(31),coll_x_l3(31),coll_y_l3(31),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(30),y_cood_l3(30),ball_x,ball_y,draw_l3(30),r_brick(30),g_brick(30),b_brick(30),coll_x_l3(30),coll_y_l3(30),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(29),y_cood_l3(29),ball_x,ball_y,draw_l3(29),r_brick(29),g_brick(29),b_brick(29),coll_x_l3(29),coll_y_l3(29),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(28),y_cood_l3(28),ball_x,ball_y,draw_l3(28),r_brick(28),g_brick(28),b_brick(28),coll_x_l3(28),coll_y_l3(28),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(27),y_cood_l3(27),ball_x,ball_y,draw_l3(27),r_brick(27),g_brick(27),b_brick(27),coll_x_l3(27),coll_y_l3(27),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(26),y_cood_l3(26),ball_x,ball_y,draw_l3(26),r_brick(26),g_brick(26),b_brick(26),coll_x_l3(26),coll_y_l3(26),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(25),y_cood_l3(25),ball_x,ball_y,draw_l3(25),r_brick(25),g_brick(25),b_brick(25),coll_x_l3(25),coll_y_l3(25),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(24),y_cood_l3(24),ball_x,ball_y,draw_l3(24),r_brick(24),g_brick(24),b_brick(24),coll_x_l3(24),coll_y_l3(24),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(23),y_cood_l3(23),ball_x,ball_y,draw_l3(23),r_brick(23),g_brick(23),b_brick(23),coll_x_l3(23),coll_y_l3(23),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(22),y_cood_l3(22),ball_x,ball_y,draw_l3(22),r_brick(22),g_brick(22),b_brick(22),coll_x_l3(22),coll_y_l3(22),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(21),y_cood_l3(21),ball_x,ball_y,draw_l3(21),r_brick(21),g_brick(21),b_brick(21),coll_x_l3(21),coll_y_l3(21),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(20),y_cood_l3(20),ball_x,ball_y,draw_l3(20),r_brick(20),g_brick(20),b_brick(20),coll_x_l3(20),coll_y_l3(20),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(19),y_cood_l3(19),ball_x,ball_y,draw_l3(19),r_brick(19),g_brick(19),b_brick(19),coll_x_l3(19),coll_y_l3(19),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(18),y_cood_l3(18),ball_x,ball_y,draw_l3(18),r_brick(18),g_brick(18),b_brick(18),coll_x_l3(18),coll_y_l3(18),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(17),y_cood_l3(17),ball_x,ball_y,draw_l3(17),r_brick(17),g_brick(17),b_brick(17),coll_x_l3(17),coll_y_l3(17),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(16),y_cood_l3(16),ball_x,ball_y,draw_l3(16),r_brick(16),g_brick(16),b_brick(16),coll_x_l3(16),coll_y_l3(16),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(15),y_cood_l3(15),ball_x,ball_y,draw_l3(15),r_brick(15),g_brick(15),b_brick(15),coll_x_l3(15),coll_y_l3(15),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(14),y_cood_l3(14),ball_x,ball_y,draw_l3(14),r_brick(14),g_brick(14),b_brick(14),coll_x_l3(14),coll_y_l3(14),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(13),y_cood_l3(13),ball_x,ball_y,draw_l3(13),r_brick(13),g_brick(13),b_brick(13),coll_x_l3(13),coll_y_l3(13),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(12),y_cood_l3(12),ball_x,ball_y,draw_l3(12),r_brick(12),g_brick(12),b_brick(12),coll_x_l3(12),coll_y_l3(12),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(11),y_cood_l3(11),ball_x,ball_y,draw_l3(11),r_brick(11),g_brick(11),b_brick(11),coll_x_l3(11),coll_y_l3(11),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(10),y_cood_l3(10),ball_x,ball_y,draw_l3(10),r_brick(10),g_brick(10),b_brick(10),coll_x_l3(10),coll_y_l3(10),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(9),y_cood_l3(9),ball_x,ball_y,draw_l3(9),r_brick(9),g_brick(9),b_brick(9),coll_x_l3(9),coll_y_l3(9),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(8),y_cood_l3(8),ball_x,ball_y,draw_l3(8),r_brick(8),g_brick(8),b_brick(8),coll_x_l3(8),coll_y_l3(8),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(7),y_cood_l3(7),ball_x,ball_y,draw_l3(7),r_brick(7),g_brick(7),b_brick(7),coll_x_l3(7),coll_y_l3(7),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(6),y_cood_l3(6),ball_x,ball_y,draw_l3(6),r_brick(6),g_brick(6),b_brick(6),coll_x_l3(6),coll_y_l3(6),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(5),y_cood_l3(5),ball_x,ball_y,draw_l3(5),r_brick(5),g_brick(5),b_brick(5),coll_x_l3(5),coll_y_l3(5),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(4),y_cood_l3(4),ball_x,ball_y,draw_l3(4),r_brick(4),g_brick(4),b_brick(4),coll_x_l3(4),coll_y_l3(4),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(3),y_cood_l3(3),ball_x,ball_y,draw_l3(3),r_brick(3),g_brick(3),b_brick(3),coll_x_l3(3),coll_y_l3(3),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(2),y_cood_l3(2),ball_x,ball_y,draw_l3(2),r_brick(2),g_brick(2),b_brick(2),coll_x_l3(2),coll_y_l3(2),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(1),y_cood_l3(1),ball_x,ball_y,draw_l3(1),r_brick(1),g_brick(1),b_brick(1),coll_x_l3(1),coll_y_l3(1),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l3(0),y_cood_l3(0),ball_x,ball_y,draw_l3(0),r_brick(0),g_brick(0),b_brick(0),coll_x_l3(0),coll_y_l3(0),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l4complete='0')then--display bricks of level 4
brick(hpos_scr,vpos_scr,x_cood_l4(71),y_cood_l4(71),ball_x,ball_y,draw_l4(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l4(71),coll_y_l4(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(70),y_cood_l4(70),ball_x,ball_y,draw_l4(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l4(70),coll_y_l4(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(69),y_cood_l4(69),ball_x,ball_y,draw_l4(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l4(69),coll_y_l4(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(68),y_cood_l4(68),ball_x,ball_y,draw_l4(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l4(68),coll_y_l4(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(67),y_cood_l4(67),ball_x,ball_y,draw_l4(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l4(67),coll_y_l4(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(66),y_cood_l4(66),ball_x,ball_y,draw_l4(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l4(66),coll_y_l4(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(65),y_cood_l4(65),ball_x,ball_y,draw_l4(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l4(65),coll_y_l4(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(64),y_cood_l4(64),ball_x,ball_y,draw_l4(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l4(64),coll_y_l4(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(63),y_cood_l4(63),ball_x,ball_y,draw_l4(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l4(63),coll_y_l4(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(62),y_cood_l4(62),ball_x,ball_y,draw_l4(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l4(62),coll_y_l4(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(61),y_cood_l4(61),ball_x,ball_y,draw_l4(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l4(61),coll_y_l4(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(60),y_cood_l4(60),ball_x,ball_y,draw_l4(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l4(60),coll_y_l4(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(59),y_cood_l4(59),ball_x,ball_y,draw_l4(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l4(59),coll_y_l4(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(58),y_cood_l4(58),ball_x,ball_y,draw_l4(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l4(58),coll_y_l4(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(57),y_cood_l4(57),ball_x,ball_y,draw_l4(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l4(57),coll_y_l4(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(56),y_cood_l4(56),ball_x,ball_y,draw_l4(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l4(56),coll_y_l4(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(55),y_cood_l4(55),ball_x,ball_y,draw_l4(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l4(55),coll_y_l4(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(54),y_cood_l4(54),ball_x,ball_y,draw_l4(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l4(54),coll_y_l4(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(53),y_cood_l4(53),ball_x,ball_y,draw_l4(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l4(53),coll_y_l4(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(52),y_cood_l4(52),ball_x,ball_y,draw_l4(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l4(52),coll_y_l4(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(51),y_cood_l4(51),ball_x,ball_y,draw_l4(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l4(51),coll_y_l4(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(50),y_cood_l4(50),ball_x,ball_y,draw_l4(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l4(50),coll_y_l4(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(49),y_cood_l4(49),ball_x,ball_y,draw_l4(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l4(49),coll_y_l4(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(48),y_cood_l4(48),ball_x,ball_y,draw_l4(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l4(48),coll_y_l4(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(47),y_cood_l4(47),ball_x,ball_y,draw_l4(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l4(47),coll_y_l4(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(46),y_cood_l4(46),ball_x,ball_y,draw_l4(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l4(46),coll_y_l4(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(45),y_cood_l4(45),ball_x,ball_y,draw_l4(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l4(45),coll_y_l4(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(44),y_cood_l4(44),ball_x,ball_y,draw_l4(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l4(44),coll_y_l4(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(43),y_cood_l4(43),ball_x,ball_y,draw_l4(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l4(43),coll_y_l4(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(42),y_cood_l4(42),ball_x,ball_y,draw_l4(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l4(42),coll_y_l4(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(41),y_cood_l4(41),ball_x,ball_y,draw_l4(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l4(41),coll_y_l4(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(40),y_cood_l4(40),ball_x,ball_y,draw_l4(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l4(40),coll_y_l4(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(39),y_cood_l4(39),ball_x,ball_y,draw_l4(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l4(39),coll_y_l4(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(38),y_cood_l4(38),ball_x,ball_y,draw_l4(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l4(38),coll_y_l4(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(37),y_cood_l4(37),ball_x,ball_y,draw_l4(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l4(37),coll_y_l4(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(36),y_cood_l4(36),ball_x,ball_y,draw_l4(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l4(36),coll_y_l4(36),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(35),y_cood_l4(35),ball_x,ball_y,draw_l4(35),r_brick(35),g_brick(35),b_brick(35),coll_x_l4(35),coll_y_l4(35),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(34),y_cood_l4(34),ball_x,ball_y,draw_l4(34),r_brick(34),g_brick(34),b_brick(34),coll_x_l4(34),coll_y_l4(34),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(33),y_cood_l4(33),ball_x,ball_y,draw_l4(33),r_brick(33),g_brick(33),b_brick(33),coll_x_l4(33),coll_y_l4(33),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(32),y_cood_l4(32),ball_x,ball_y,draw_l4(32),r_brick(32),g_brick(32),b_brick(32),coll_x_l4(32),coll_y_l4(32),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(31),y_cood_l4(31),ball_x,ball_y,draw_l4(31),r_brick(31),g_brick(31),b_brick(31),coll_x_l4(31),coll_y_l4(31),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(30),y_cood_l4(30),ball_x,ball_y,draw_l4(30),r_brick(30),g_brick(30),b_brick(30),coll_x_l4(30),coll_y_l4(30),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(29),y_cood_l4(29),ball_x,ball_y,draw_l4(29),r_brick(29),g_brick(29),b_brick(29),coll_x_l4(29),coll_y_l4(29),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(28),y_cood_l4(28),ball_x,ball_y,draw_l4(28),r_brick(28),g_brick(28),b_brick(28),coll_x_l4(28),coll_y_l4(28),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(27),y_cood_l4(27),ball_x,ball_y,draw_l4(27),r_brick(27),g_brick(27),b_brick(27),coll_x_l4(27),coll_y_l4(27),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(26),y_cood_l4(26),ball_x,ball_y,draw_l4(26),r_brick(26),g_brick(26),b_brick(26),coll_x_l4(26),coll_y_l4(26),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(25),y_cood_l4(25),ball_x,ball_y,draw_l4(25),r_brick(25),g_brick(25),b_brick(25),coll_x_l4(25),coll_y_l4(25),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(24),y_cood_l4(24),ball_x,ball_y,draw_l4(24),r_brick(24),g_brick(24),b_brick(24),coll_x_l4(24),coll_y_l4(24),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(23),y_cood_l4(23),ball_x,ball_y,draw_l4(23),r_brick(23),g_brick(23),b_brick(23),coll_x_l4(23),coll_y_l4(23),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(22),y_cood_l4(22),ball_x,ball_y,draw_l4(22),r_brick(22),g_brick(22),b_brick(22),coll_x_l4(22),coll_y_l4(22),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(21),y_cood_l4(21),ball_x,ball_y,draw_l4(21),r_brick(21),g_brick(21),b_brick(21),coll_x_l4(21),coll_y_l4(21),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(20),y_cood_l4(20),ball_x,ball_y,draw_l4(20),r_brick(20),g_brick(20),b_brick(20),coll_x_l4(20),coll_y_l4(20),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(19),y_cood_l4(19),ball_x,ball_y,draw_l4(19),r_brick(19),g_brick(19),b_brick(19),coll_x_l4(19),coll_y_l4(19),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(18),y_cood_l4(18),ball_x,ball_y,draw_l4(18),r_brick(18),g_brick(18),b_brick(18),coll_x_l4(18),coll_y_l4(18),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(17),y_cood_l4(17),ball_x,ball_y,draw_l4(17),r_brick(17),g_brick(17),b_brick(17),coll_x_l4(17),coll_y_l4(17),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(16),y_cood_l4(16),ball_x,ball_y,draw_l4(16),r_brick(16),g_brick(16),b_brick(16),coll_x_l4(16),coll_y_l4(16),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(15),y_cood_l4(15),ball_x,ball_y,draw_l4(15),r_brick(15),g_brick(15),b_brick(15),coll_x_l4(15),coll_y_l4(15),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(14),y_cood_l4(14),ball_x,ball_y,draw_l4(14),r_brick(14),g_brick(14),b_brick(14),coll_x_l4(14),coll_y_l4(14),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(13),y_cood_l4(13),ball_x,ball_y,draw_l4(13),r_brick(13),g_brick(13),b_brick(13),coll_x_l4(13),coll_y_l4(13),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(12),y_cood_l4(12),ball_x,ball_y,draw_l4(12),r_brick(12),g_brick(12),b_brick(12),coll_x_l4(12),coll_y_l4(12),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(11),y_cood_l4(11),ball_x,ball_y,draw_l4(11),r_brick(11),g_brick(11),b_brick(11),coll_x_l4(11),coll_y_l4(11),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(10),y_cood_l4(10),ball_x,ball_y,draw_l4(10),r_brick(10),g_brick(10),b_brick(10),coll_x_l4(10),coll_y_l4(10),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(9),y_cood_l4(9),ball_x,ball_y,draw_l4(9),r_brick(9),g_brick(9),b_brick(9),coll_x_l4(9),coll_y_l4(9),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l4(8),y_cood_l4(8),ball_x,ball_y,draw_l4(8),r_brick(8),g_brick(8),b_brick(8),coll_x_l4(8),coll_y_l4(8),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
elsif(l5complete='0')then--display bricks of level 5
brick(hpos_scr,vpos_scr,x_cood_l5(71),y_cood_l5(71),ball_x,ball_y,draw_l5(71),r_brick(71),g_brick(71),b_brick(71),coll_x_l5(71),coll_y_l5(71),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(70),y_cood_l5(70),ball_x,ball_y,draw_l5(70),r_brick(70),g_brick(70),b_brick(70),coll_x_l5(70),coll_y_l5(70),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(69),y_cood_l5(69),ball_x,ball_y,draw_l5(69),r_brick(69),g_brick(69),b_brick(69),coll_x_l5(69),coll_y_l5(69),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(68),y_cood_l5(68),ball_x,ball_y,draw_l5(68),r_brick(68),g_brick(68),b_brick(68),coll_x_l5(68),coll_y_l5(68),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(67),y_cood_l5(67),ball_x,ball_y,draw_l5(67),r_brick(67),g_brick(67),b_brick(67),coll_x_l5(67),coll_y_l5(67),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(66),y_cood_l5(66),ball_x,ball_y,draw_l5(66),r_brick(66),g_brick(66),b_brick(66),coll_x_l5(66),coll_y_l5(66),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(65),y_cood_l5(65),ball_x,ball_y,draw_l5(65),r_brick(65),g_brick(65),b_brick(65),coll_x_l5(65),coll_y_l5(65),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(64),y_cood_l5(64),ball_x,ball_y,draw_l5(64),r_brick(64),g_brick(64),b_brick(64),coll_x_l5(64),coll_y_l5(64),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(63),y_cood_l5(63),ball_x,ball_y,draw_l5(63),r_brick(63),g_brick(63),b_brick(63),coll_x_l5(63),coll_y_l5(63),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(62),y_cood_l5(62),ball_x,ball_y,draw_l5(62),r_brick(62),g_brick(62),b_brick(62),coll_x_l5(62),coll_y_l5(62),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(61),y_cood_l5(61),ball_x,ball_y,draw_l5(61),r_brick(61),g_brick(61),b_brick(61),coll_x_l5(61),coll_y_l5(61),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(60),y_cood_l5(60),ball_x,ball_y,draw_l5(60),r_brick(60),g_brick(60),b_brick(60),coll_x_l5(60),coll_y_l5(60),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(59),y_cood_l5(59),ball_x,ball_y,draw_l5(59),r_brick(59),g_brick(59),b_brick(59),coll_x_l5(59),coll_y_l5(59),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(58),y_cood_l5(58),ball_x,ball_y,draw_l5(58),r_brick(58),g_brick(58),b_brick(58),coll_x_l5(58),coll_y_l5(58),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(57),y_cood_l5(57),ball_x,ball_y,draw_l5(57),r_brick(57),g_brick(57),b_brick(57),coll_x_l5(57),coll_y_l5(57),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(56),y_cood_l5(56),ball_x,ball_y,draw_l5(56),r_brick(56),g_brick(56),b_brick(56),coll_x_l5(56),coll_y_l5(56),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(55),y_cood_l5(55),ball_x,ball_y,draw_l5(55),r_brick(55),g_brick(55),b_brick(55),coll_x_l5(55),coll_y_l5(55),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(54),y_cood_l5(54),ball_x,ball_y,draw_l5(54),r_brick(54),g_brick(54),b_brick(54),coll_x_l5(54),coll_y_l5(54),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(53),y_cood_l5(53),ball_x,ball_y,draw_l5(53),r_brick(53),g_brick(53),b_brick(53),coll_x_l5(53),coll_y_l5(53),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(52),y_cood_l5(52),ball_x,ball_y,draw_l5(52),r_brick(52),g_brick(52),b_brick(52),coll_x_l5(52),coll_y_l5(52),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(51),y_cood_l5(51),ball_x,ball_y,draw_l5(51),r_brick(51),g_brick(51),b_brick(51),coll_x_l5(51),coll_y_l5(51),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(50),y_cood_l5(50),ball_x,ball_y,draw_l5(50),r_brick(50),g_brick(50),b_brick(50),coll_x_l5(50),coll_y_l5(50),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(49),y_cood_l5(49),ball_x,ball_y,draw_l5(49),r_brick(49),g_brick(49),b_brick(49),coll_x_l5(49),coll_y_l5(49),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(48),y_cood_l5(48),ball_x,ball_y,draw_l5(48),r_brick(48),g_brick(48),b_brick(48),coll_x_l5(48),coll_y_l5(48),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(47),y_cood_l5(47),ball_x,ball_y,draw_l5(47),r_brick(47),g_brick(47),b_brick(47),coll_x_l5(47),coll_y_l5(47),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(46),y_cood_l5(46),ball_x,ball_y,draw_l5(46),r_brick(46),g_brick(46),b_brick(46),coll_x_l5(46),coll_y_l5(46),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(45),y_cood_l5(45),ball_x,ball_y,draw_l5(45),r_brick(45),g_brick(45),b_brick(45),coll_x_l5(45),coll_y_l5(45),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(44),y_cood_l5(44),ball_x,ball_y,draw_l5(44),r_brick(44),g_brick(44),b_brick(44),coll_x_l5(44),coll_y_l5(44),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(43),y_cood_l5(43),ball_x,ball_y,draw_l5(43),r_brick(43),g_brick(43),b_brick(43),coll_x_l5(43),coll_y_l5(43),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(42),y_cood_l5(42),ball_x,ball_y,draw_l5(42),r_brick(42),g_brick(42),b_brick(42),coll_x_l5(42),coll_y_l5(42),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(41),y_cood_l5(41),ball_x,ball_y,draw_l5(41),r_brick(41),g_brick(41),b_brick(41),coll_x_l5(41),coll_y_l5(41),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(40),y_cood_l5(40),ball_x,ball_y,draw_l5(40),r_brick(40),g_brick(40),b_brick(40),coll_x_l5(40),coll_y_l5(40),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(39),y_cood_l5(39),ball_x,ball_y,draw_l5(39),r_brick(39),g_brick(39),b_brick(39),coll_x_l5(39),coll_y_l5(39),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(38),y_cood_l5(38),ball_x,ball_y,draw_l5(38),r_brick(38),g_brick(38),b_brick(38),coll_x_l5(38),coll_y_l5(38),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(37),y_cood_l5(37),ball_x,ball_y,draw_l5(37),r_brick(37),g_brick(37),b_brick(37),coll_x_l5(37),coll_y_l5(37),ball_x_vel,ball_y_vel);
brick(hpos_scr,vpos_scr,x_cood_l5(36),y_cood_l5(36),ball_x,ball_y,draw_l5(36),r_brick(36),g_brick(36),b_brick(36),coll_x_l5(36),coll_y_l5(36),ball_x_vel,ball_y_vel);
ball(hpos_scr,vpos_scr,ball_x,ball_y,ball_row,ball_col); --get the ball image
else--all levels are completed sucessfully
winmes(hpos_scr,vpos_scr,winmes_x,winmes_y,winmes_row,winmes_col);--get gameover image
stopball<='1';--to stop the ball motion
end if;
bat(hpos_scr,vpos_scr,bat_x,bat_y,draw_bat,r_bat,g_bat,b_bat);--display bat
lives(hpos_scr,vpos_scr,lives_x,lives_y,lives_row,lives_col);--get lives image
else--game has not started yet
welmes(hpos_scr,vpos_scr,welmes_x,welmes_y,welmes_row,welmes_col);--welcome message
end if;
if(ball_y>480 and isalive=0) then--if last life is used uo
gameover(hpos_scr,vpos_scr,gameover_x,gameover_y,gameover_row,gameover_col);--get gameover image
stopball<='1';--to stop the ball motion
else
null;
end if;
if(pause='1' and stopball='0' and notstarted='0')then--if pause switch is on
paused(hpos_scr,vpos_scr,paused_x,paused_y,paused_row,paused_col);--get paused image
else
null;
end if;
if(hpos>152 and hpos<793 and vpos>37 and vpos<518) then
if(welmes_validity_bit='1') then
r<=r_welmes; --display welcome message
g<=g_welmes;
b<=b_welmes;
elsif(lives_validity_bit='1') then
r<=r_lives; --display lives
g<=g_lives;
b<=b_lives;
elsif(ball_validity_bit='1') then
r<=r_ball; --display ball
g<=g_ball;
b<=b_ball;
elsif(draw_bat='1') then
r<=r_bat; --display bat
g<=g_bat;
b<=b_bat;
elsif(paused_validity_bit='1') then
r<=r_paused; --display pause message
g<=g_paused;
b<=b_paused;
elsif(gameover_validity_bit='1') then
r<=r_gameover; --display gameover
g<=g_gameover;
b<=b_gameover;
elsif(winmes_validity_bit='1') then
r<=r_winmes; --display winning message
g<=g_winmes;
b<=b_winmes;
elsif(draw_l1(71)='1' and is_destroyed_l1(71)='0') then--display bricks of level1
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l1(70)='1' and is_destroyed_l1(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l1(69)='1' and is_destroyed_l1(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l1(68)='1' and is_destroyed_l1(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l1(67)='1' and is_destroyed_l1(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l1(66)='1' and is_destroyed_l1(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l1(65)='1' and is_destroyed_l1(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l1(64)='1' and is_destroyed_l1(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l1(63)='1' and is_destroyed_l1(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l1(62)='1' and is_destroyed_l1(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l1(61)='1' and is_destroyed_l1(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l1(60)='1' and is_destroyed_l1(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l1(59)='1' and is_destroyed_l1(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l1(58)='1' and is_destroyed_l1(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l1(57)='1' and is_destroyed_l1(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l1(56)='1' and is_destroyed_l1(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l1(55)='1' and is_destroyed_l1(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l1(54)='1' and is_destroyed_l1(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l1(53)='1' and is_destroyed_l1(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l1(52)='1' and is_destroyed_l1(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l1(51)='1' and is_destroyed_l1(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l1(50)='1' and is_destroyed_l1(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l1(49)='1' and is_destroyed_l1(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l1(48)='1' and is_destroyed_l1(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l1(47)='1' and is_destroyed_l1(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l1(46)='1' and is_destroyed_l1(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l1(45)='1' and is_destroyed_l1(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l1(44)='1' and is_destroyed_l1(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l1(43)='1' and is_destroyed_l1(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l1(42)='1' and is_destroyed_l1(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l1(41)='1' and is_destroyed_l1(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l1(40)='1' and is_destroyed_l1(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l1(39)='1' and is_destroyed_l1(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l1(38)='1' and is_destroyed_l1(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l1(37)='1' and is_destroyed_l1(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l1(36)='1' and is_destroyed_l1(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
elsif(draw_l1(35)='1' and is_destroyed_l1(35)='0') then
r<=r_brick(35);
g<=g_brick(35);
b<=b_brick(35);
elsif(draw_l1(34)='1' and is_destroyed_l1(34)='0') then
r<=r_brick(34);
g<=g_brick(34);
b<=b_brick(34);
elsif(draw_l1(33)='1' and is_destroyed_l1(33)='0') then
r<=r_brick(33);
g<=g_brick(33);
b<=b_brick(33);
elsif(draw_l1(32)='1' and is_destroyed_l1(32)='0') then
r<=r_brick(32);
g<=g_brick(32);
b<=b_brick(32);
elsif(draw_l1(31)='1' and is_destroyed_l1(31)='0') then
r<=r_brick(31);
g<=g_brick(31);
b<=b_brick(31);
elsif(draw_l1(30)='1' and is_destroyed_l1(30)='0') then
r<=r_brick(30);
g<=g_brick(30);
b<=b_brick(30);
elsif(draw_l1(29)='1' and is_destroyed_l1(29)='0') then
r<=r_brick(29);
g<=g_brick(29);
b<=b_brick(29);
elsif(draw_l1(28)='1' and is_destroyed_l1(28)='0') then
r<=r_brick(28);
g<=g_brick(28);
b<=b_brick(28);
elsif(draw_l1(27)='1' and is_destroyed_l1(27)='0') then
r<=r_brick(27);
g<=g_brick(27);
b<=b_brick(27);
elsif(draw_l1(26)='1' and is_destroyed_l1(26)='0') then
r<=r_brick(26);
g<=g_brick(26);
b<=b_brick(26);
elsif(draw_l1(25)='1' and is_destroyed_l1(25)='0') then
r<=r_brick(25);
g<=g_brick(25);
b<=b_brick(25);
elsif(draw_l1(24)='1' and is_destroyed_l1(24)='0') then
r<=r_brick(24);
g<=g_brick(24);
b<=b_brick(24);
elsif(draw_l1(23)='1' and is_destroyed_l1(23)='0') then
r<=r_brick(23);
g<=g_brick(23);
b<=b_brick(23);
elsif(draw_l1(22)='1' and is_destroyed_l1(22)='0') then
r<=r_brick(22);
g<=g_brick(22);
b<=b_brick(22);
elsif(draw_l1(21)='1' and is_destroyed_l1(21)='0') then
r<=r_brick(21);
g<=g_brick(21);
b<=b_brick(21);
elsif(draw_l1(20)='1' and is_destroyed_l1(20)='0') then
r<=r_brick(20);
g<=g_brick(20);
b<=b_brick(20);
elsif(draw_l1(19)='1' and is_destroyed_l1(19)='0') then
r<=r_brick(19);
g<=g_brick(19);
b<=b_brick(19);
elsif(draw_l1(18)='1' and is_destroyed_l1(18)='0') then
r<=r_brick(18);
g<=g_brick(18);
b<=b_brick(18);
elsif(draw_l1(17)='1' and is_destroyed_l1(17)='0') then
r<=r_brick(17);
g<=g_brick(17);
b<=b_brick(17);
elsif(draw_l1(16)='1' and is_destroyed_l1(16)='0') then
r<=r_brick(16);
g<=g_brick(16);
b<=b_brick(16);
elsif(draw_l1(15)='1' and is_destroyed_l1(15)='0') then
r<=r_brick(15);
g<=g_brick(15);
b<=b_brick(15);
elsif(draw_l1(14)='1' and is_destroyed_l1(14)='0') then
r<=r_brick(14);
g<=g_brick(14);
b<=b_brick(14);
elsif(draw_l1(13)='1' and is_destroyed_l1(13)='0') then
r<=r_brick(13);
g<=g_brick(13);
b<=b_brick(13);
elsif(draw_l1(12)='1' and is_destroyed_l1(12)='0') then
r<=r_brick(12);
g<=g_brick(12);
b<=b_brick(12);
elsif(draw_l1(11)='1' and is_destroyed_l1(11)='0') then
r<=r_brick(11);
g<=g_brick(11);
b<=b_brick(11);
elsif(draw_l1(10)='1' and is_destroyed_l1(10)='0') then
r<=r_brick(10);
g<=g_brick(10);
b<=b_brick(10);
elsif(draw_l1(9)='1' and is_destroyed_l1(9)='0') then
r<=r_brick(9);
g<=g_brick(9);
b<=b_brick(9);
elsif(draw_l1(8)='1' and is_destroyed_l1(8)='0') then
r<=r_brick(8);
g<=g_brick(8);
b<=b_brick(8);
elsif(draw_l1(7)='1' and is_destroyed_l1(7)='0') then
r<=r_brick(7);
g<=g_brick(7);
b<=b_brick(7);
elsif(draw_l1(6)='1' and is_destroyed_l1(6)='0') then
r<=r_brick(6);
g<=g_brick(6);
b<=b_brick(6);
elsif(draw_l1(5)='1' and is_destroyed_l1(5)='0') then
r<=r_brick(5);
g<=g_brick(5);
b<=b_brick(5);
elsif(draw_l1(4)='1' and is_destroyed_l1(4)='0') then
r<=r_brick(4);
g<=g_brick(4);
b<=b_brick(4);
elsif(draw_l1(3)='1' and is_destroyed_l1(3)='0') then
r<=r_brick(3);
g<=g_brick(3);
b<=b_brick(3);
elsif(draw_l1(2)='1' and is_destroyed_l1(2)='0') then
r<=r_brick(2);
g<=g_brick(2);
b<=b_brick(2);
elsif(draw_l1(1)='1' and is_destroyed_l1(1)='0') then
r<=r_brick(1);
g<=g_brick(1);
b<=b_brick(1);
elsif(draw_l1(0)='1' and is_destroyed_l1(0)='0') then
r<=r_brick(0);
g<=g_brick(0);
b<=b_brick(0);
elsif(draw_l2(71)='1' and is_destroyed_l2(71)='0') then--display bricks of level2
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l2(70)='1' and is_destroyed_l2(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l2(69)='1' and is_destroyed_l2(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l2(68)='1' and is_destroyed_l2(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l2(67)='1' and is_destroyed_l2(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l2(66)='1' and is_destroyed_l2(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l2(65)='1' and is_destroyed_l2(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l2(64)='1' and is_destroyed_l2(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l2(63)='1' and is_destroyed_l2(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l2(62)='1' and is_destroyed_l2(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l2(61)='1' and is_destroyed_l2(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l2(60)='1' and is_destroyed_l2(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l2(59)='1' and is_destroyed_l2(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l2(58)='1' and is_destroyed_l2(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l2(57)='1' and is_destroyed_l2(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l2(56)='1' and is_destroyed_l2(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l2(55)='1' and is_destroyed_l2(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l2(54)='1' and is_destroyed_l2(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l2(53)='1' and is_destroyed_l2(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l2(52)='1' and is_destroyed_l2(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l2(51)='1' and is_destroyed_l2(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l2(50)='1' and is_destroyed_l2(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l2(49)='1' and is_destroyed_l2(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l2(48)='1' and is_destroyed_l2(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l2(47)='1' and is_destroyed_l2(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l2(46)='1' and is_destroyed_l2(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l2(45)='1' and is_destroyed_l2(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l2(44)='1' and is_destroyed_l2(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l3(71)='1' and is_destroyed_l3(71)='0') then--display bricks of level3
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l3(70)='1' and is_destroyed_l3(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l3(69)='1' and is_destroyed_l3(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l3(68)='1' and is_destroyed_l3(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l3(67)='1' and is_destroyed_l3(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l3(66)='1' and is_destroyed_l3(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l3(65)='1' and is_destroyed_l3(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l3(64)='1' and is_destroyed_l3(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l3(63)='1' and is_destroyed_l3(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l3(62)='1' and is_destroyed_l3(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l3(61)='1' and is_destroyed_l3(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l3(60)='1' and is_destroyed_l3(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l3(59)='1' and is_destroyed_l3(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l3(58)='1' and is_destroyed_l3(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l3(57)='1' and is_destroyed_l3(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l3(56)='1' and is_destroyed_l3(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l3(55)='1' and is_destroyed_l3(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l3(54)='1' and is_destroyed_l3(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l3(53)='1' and is_destroyed_l3(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l3(52)='1' and is_destroyed_l3(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l3(51)='1' and is_destroyed_l3(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l3(50)='1' and is_destroyed_l3(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l3(49)='1' and is_destroyed_l3(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l3(48)='1' and is_destroyed_l3(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l3(47)='1' and is_destroyed_l3(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l3(46)='1' and is_destroyed_l3(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l3(45)='1' and is_destroyed_l3(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l3(44)='1' and is_destroyed_l3(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l3(43)='1' and is_destroyed_l3(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l3(42)='1' and is_destroyed_l3(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l3(41)='1' and is_destroyed_l3(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l3(40)='1' and is_destroyed_l3(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l3(39)='1' and is_destroyed_l3(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l3(38)='1' and is_destroyed_l3(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l3(37)='1' and is_destroyed_l3(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l3(36)='1' and is_destroyed_l3(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
elsif(draw_l3(35)='1' and is_destroyed_l3(35)='0') then
r<=r_brick(35);
g<=g_brick(35);
b<=b_brick(35);
elsif(draw_l3(34)='1' and is_destroyed_l3(34)='0') then
r<=r_brick(34);
g<=g_brick(34);
b<=b_brick(34);
elsif(draw_l3(33)='1' and is_destroyed_l3(33)='0') then
r<=r_brick(33);
g<=g_brick(33);
b<=b_brick(33);
elsif(draw_l3(32)='1' and is_destroyed_l3(32)='0') then
r<=r_brick(32);
g<=g_brick(32);
b<=b_brick(32);
elsif(draw_l3(31)='1' and is_destroyed_l3(31)='0') then
r<=r_brick(31);
g<=g_brick(31);
b<=b_brick(31);
elsif(draw_l3(30)='1' and is_destroyed_l3(30)='0') then
r<=r_brick(30);
g<=g_brick(30);
b<=b_brick(30);
elsif(draw_l3(29)='1' and is_destroyed_l3(29)='0') then
r<=r_brick(29);
g<=g_brick(29);
b<=b_brick(29);
elsif(draw_l3(28)='1' and is_destroyed_l3(28)='0') then
r<=r_brick(28);
g<=g_brick(28);
b<=b_brick(28);
elsif(draw_l3(27)='1' and is_destroyed_l3(27)='0') then
r<=r_brick(27);
g<=g_brick(27);
b<=b_brick(27);
elsif(draw_l3(26)='1' and is_destroyed_l3(26)='0') then
r<=r_brick(26);
g<=g_brick(26);
b<=b_brick(26);
elsif(draw_l3(25)='1' and is_destroyed_l3(25)='0') then
r<=r_brick(25);
g<=g_brick(25);
b<=b_brick(25);
elsif(draw_l3(24)='1' and is_destroyed_l3(24)='0') then
r<=r_brick(24);
g<=g_brick(24);
b<=b_brick(24);
elsif(draw_l3(23)='1' and is_destroyed_l3(23)='0') then
r<=r_brick(23);
g<=g_brick(23);
b<=b_brick(23);
elsif(draw_l3(22)='1' and is_destroyed_l3(22)='0') then
r<=r_brick(22);
g<=g_brick(22);
b<=b_brick(22);
elsif(draw_l3(21)='1' and is_destroyed_l3(21)='0') then
r<=r_brick(21);
g<=g_brick(21);
b<=b_brick(21);
elsif(draw_l3(20)='1' and is_destroyed_l3(20)='0') then
r<=r_brick(20);
g<=g_brick(20);
b<=b_brick(20);
elsif(draw_l3(19)='1' and is_destroyed_l3(19)='0') then
r<=r_brick(19);
g<=g_brick(19);
b<=b_brick(19);
elsif(draw_l3(18)='1' and is_destroyed_l3(18)='0') then
r<=r_brick(18);
g<=g_brick(18);
b<=b_brick(18);
elsif(draw_l3(17)='1' and is_destroyed_l3(17)='0') then
r<=r_brick(17);
g<=g_brick(17);
b<=b_brick(17);
elsif(draw_l3(16)='1' and is_destroyed_l3(16)='0') then
r<=r_brick(16);
g<=g_brick(16);
b<=b_brick(16);
elsif(draw_l3(15)='1' and is_destroyed_l3(15)='0') then
r<=r_brick(15);
g<=g_brick(15);
b<=b_brick(15);
elsif(draw_l3(14)='1' and is_destroyed_l3(14)='0') then
r<=r_brick(14);
g<=g_brick(14);
b<=b_brick(14);
elsif(draw_l3(13)='1' and is_destroyed_l3(13)='0') then
r<=r_brick(13);
g<=g_brick(13);
b<=b_brick(13);
elsif(draw_l3(12)='1' and is_destroyed_l3(12)='0') then
r<=r_brick(12);
g<=g_brick(12);
b<=b_brick(12);
elsif(draw_l3(11)='1' and is_destroyed_l3(11)='0') then
r<=r_brick(11);
g<=g_brick(11);
b<=b_brick(11);
elsif(draw_l3(10)='1' and is_destroyed_l3(10)='0') then
r<=r_brick(10);
g<=g_brick(10);
b<=b_brick(10);
elsif(draw_l3(9)='1' and is_destroyed_l3(9)='0') then
r<=r_brick(9);
g<=g_brick(9);
b<=b_brick(9);
elsif(draw_l3(8)='1' and is_destroyed_l3(8)='0') then
r<=r_brick(8);
g<=g_brick(8);
b<=b_brick(8);
elsif(draw_l3(7)='1' and is_destroyed_l3(7)='0') then
r<=r_brick(7);
g<=g_brick(7);
b<=b_brick(7);
elsif(draw_l3(6)='1' and is_destroyed_l3(6)='0') then
r<=r_brick(6);
g<=g_brick(6);
b<=b_brick(6);
elsif(draw_l3(5)='1' and is_destroyed_l3(5)='0') then
r<=r_brick(5);
g<=g_brick(5);
b<=b_brick(5);
elsif(draw_l3(4)='1' and is_destroyed_l3(4)='0') then
r<=r_brick(4);
g<=g_brick(4);
b<=b_brick(4);
elsif(draw_l3(3)='1' and is_destroyed_l3(3)='0') then
r<=r_brick(3);
g<=g_brick(3);
b<=b_brick(3);
elsif(draw_l3(2)='1' and is_destroyed_l3(2)='0') then
r<=r_brick(2);
g<=g_brick(2);
b<=b_brick(2);
elsif(draw_l3(1)='1' and is_destroyed_l3(1)='0') then
r<=r_brick(1);
g<=g_brick(1);
b<=b_brick(1);
elsif(draw_l3(0)='1' and is_destroyed_l3(0)='0') then
r<=r_brick(0);
g<=g_brick(0);
b<=b_brick(0);
elsif(draw_l4(71)='1' and is_destroyed_l4(71)='0') then--display bricks of level4
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l4(70)='1' and is_destroyed_l4(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l4(69)='1' and is_destroyed_l4(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l4(68)='1' and is_destroyed_l4(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l4(67)='1' and is_destroyed_l4(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l4(66)='1' and is_destroyed_l4(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l4(65)='1' and is_destroyed_l4(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l4(64)='1' and is_destroyed_l4(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l4(63)='1' and is_destroyed_l4(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l4(62)='1' and is_destroyed_l4(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l4(61)='1' and is_destroyed_l4(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l4(60)='1' and is_destroyed_l4(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l4(59)='1' and is_destroyed_l4(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l4(58)='1' and is_destroyed_l4(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l4(57)='1' and is_destroyed_l4(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l4(56)='1' and is_destroyed_l4(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l4(55)='1' and is_destroyed_l4(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l4(54)='1' and is_destroyed_l4(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l4(53)='1' and is_destroyed_l4(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l4(52)='1' and is_destroyed_l4(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l4(51)='1' and is_destroyed_l4(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l4(50)='1' and is_destroyed_l4(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l4(49)='1' and is_destroyed_l4(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l4(48)='1' and is_destroyed_l4(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l4(47)='1' and is_destroyed_l4(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l4(46)='1' and is_destroyed_l4(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l4(45)='1' and is_destroyed_l4(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l4(44)='1' and is_destroyed_l4(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l4(43)='1' and is_destroyed_l4(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l4(42)='1' and is_destroyed_l4(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l4(41)='1' and is_destroyed_l4(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l4(40)='1' and is_destroyed_l4(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l4(39)='1' and is_destroyed_l4(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l4(38)='1' and is_destroyed_l4(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l4(37)='1' and is_destroyed_l4(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l4(36)='1' and is_destroyed_l4(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
elsif(draw_l4(35)='1' and is_destroyed_l4(35)='0') then
r<=r_brick(35);
g<=g_brick(35);
b<=b_brick(35);
elsif(draw_l4(34)='1' and is_destroyed_l4(34)='0') then
r<=r_brick(34);
g<=g_brick(34);
b<=b_brick(34);
elsif(draw_l4(33)='1' and is_destroyed_l4(33)='0') then
r<=r_brick(33);
g<=g_brick(33);
b<=b_brick(33);
elsif(draw_l4(32)='1' and is_destroyed_l4(32)='0') then
r<=r_brick(32);
g<=g_brick(32);
b<=b_brick(32);
elsif(draw_l4(31)='1' and is_destroyed_l4(31)='0') then
r<=r_brick(31);
g<=g_brick(31);
b<=b_brick(31);
elsif(draw_l4(30)='1' and is_destroyed_l4(30)='0') then
r<=r_brick(30);
g<=g_brick(30);
b<=b_brick(30);
elsif(draw_l4(29)='1' and is_destroyed_l4(29)='0') then
r<=r_brick(29);
g<=g_brick(29);
b<=b_brick(29);
elsif(draw_l4(28)='1' and is_destroyed_l4(28)='0') then
r<=r_brick(28);
g<=g_brick(28);
b<=b_brick(28);
elsif(draw_l4(27)='1' and is_destroyed_l4(27)='0') then
r<=r_brick(27);
g<=g_brick(27);
b<=b_brick(27);
elsif(draw_l4(26)='1' and is_destroyed_l4(26)='0') then
r<=r_brick(26);
g<=g_brick(26);
b<=b_brick(26);
elsif(draw_l4(25)='1' and is_destroyed_l4(25)='0') then
r<=r_brick(25);
g<=g_brick(25);
b<=b_brick(25);
elsif(draw_l4(24)='1' and is_destroyed_l4(24)='0') then
r<=r_brick(24);
g<=g_brick(24);
b<=b_brick(24);
elsif(draw_l4(23)='1' and is_destroyed_l4(23)='0') then
r<=r_brick(23);
g<=g_brick(23);
b<=b_brick(23);
elsif(draw_l4(22)='1' and is_destroyed_l4(22)='0') then
r<=r_brick(22);
g<=g_brick(22);
b<=b_brick(22);
elsif(draw_l4(21)='1' and is_destroyed_l4(21)='0') then
r<=r_brick(21);
g<=g_brick(21);
b<=b_brick(21);
elsif(draw_l4(20)='1' and is_destroyed_l4(20)='0') then
r<=r_brick(20);
g<=g_brick(20);
b<=b_brick(20);
elsif(draw_l4(19)='1' and is_destroyed_l4(19)='0') then
r<=r_brick(19);
g<=g_brick(19);
b<=b_brick(19);
elsif(draw_l4(18)='1' and is_destroyed_l4(18)='0') then
r<=r_brick(18);
g<=g_brick(18);
b<=b_brick(18);
elsif(draw_l4(17)='1' and is_destroyed_l4(17)='0') then
r<=r_brick(17);
g<=g_brick(17);
b<=b_brick(17);
elsif(draw_l4(16)='1' and is_destroyed_l4(16)='0') then
r<=r_brick(16);
g<=g_brick(16);
b<=b_brick(16);
elsif(draw_l4(15)='1' and is_destroyed_l4(15)='0') then
r<=r_brick(15);
g<=g_brick(15);
b<=b_brick(15);
elsif(draw_l4(14)='1' and is_destroyed_l4(14)='0') then
r<=r_brick(14);
g<=g_brick(14);
b<=b_brick(14);
elsif(draw_l4(13)='1' and is_destroyed_l4(13)='0') then
r<=r_brick(13);
g<=g_brick(13);
b<=b_brick(13);
elsif(draw_l4(12)='1' and is_destroyed_l4(12)='0') then
r<=r_brick(12);
g<=g_brick(12);
b<=b_brick(12);
elsif(draw_l4(11)='1' and is_destroyed_l4(11)='0') then
r<=r_brick(11);
g<=g_brick(11);
b<=b_brick(11);
elsif(draw_l4(10)='1' and is_destroyed_l4(10)='0') then
r<=r_brick(10);
g<=g_brick(10);
b<=b_brick(10);
elsif(draw_l4(9)='1' and is_destroyed_l4(9)='0') then
r<=r_brick(9);
g<=g_brick(9);
b<=b_brick(9);
elsif(draw_l4(8)='1' and is_destroyed_l4(8)='0') then
r<=r_brick(8);
g<=g_brick(8);
b<=b_brick(8);
elsif(draw_l5(71)='1' and is_destroyed_l5(71)='0') then--display bricks of level5
r<=r_brick(71);
g<=g_brick(71);
b<=b_brick(71);
elsif(draw_l5(70)='1' and is_destroyed_l5(70)='0') then
r<=r_brick(70);
g<=g_brick(70);
b<=b_brick(70);
elsif(draw_l5(69)='1' and is_destroyed_l5(69)='0') then
r<=r_brick(69);
g<=g_brick(69);
b<=b_brick(69);
elsif(draw_l5(68)='1' and is_destroyed_l5(68)='0') then
r<=r_brick(68);
g<=g_brick(68);
b<=b_brick(68);
elsif(draw_l5(67)='1' and is_destroyed_l5(67)='0') then
r<=r_brick(67);
g<=g_brick(67);
b<=b_brick(67);
elsif(draw_l5(66)='1' and is_destroyed_l5(66)='0') then
r<=r_brick(66);
g<=g_brick(66);
b<=b_brick(66);
elsif(draw_l5(65)='1' and is_destroyed_l5(65)='0') then
r<=r_brick(65);
g<=g_brick(65);
b<=b_brick(65);
elsif(draw_l5(64)='1' and is_destroyed_l5(64)='0') then
r<=r_brick(64);
g<=g_brick(64);
b<=b_brick(64);
elsif(draw_l5(63)='1' and is_destroyed_l5(63)='0') then
r<=r_brick(63);
g<=g_brick(63);
b<=b_brick(63);
elsif(draw_l5(62)='1' and is_destroyed_l5(62)='0') then
r<=r_brick(62);
g<=g_brick(62);
b<=b_brick(62);
elsif(draw_l5(61)='1' and is_destroyed_l5(61)='0') then
r<=r_brick(61);
g<=g_brick(61);
b<=b_brick(61);
elsif(draw_l5(60)='1' and is_destroyed_l5(60)='0') then
r<=r_brick(60);
g<=g_brick(60);
b<=b_brick(60);
elsif(draw_l5(59)='1' and is_destroyed_l5(59)='0') then
r<=r_brick(59);
g<=g_brick(59);
b<=b_brick(59);
elsif(draw_l5(58)='1' and is_destroyed_l5(58)='0') then
r<=r_brick(58);
g<=g_brick(58);
b<=b_brick(58);
elsif(draw_l5(57)='1' and is_destroyed_l5(57)='0') then
r<=r_brick(57);
g<=g_brick(57);
b<=b_brick(57);
elsif(draw_l5(56)='1' and is_destroyed_l5(56)='0') then
r<=r_brick(56);
g<=g_brick(56);
b<=b_brick(56);
elsif(draw_l5(55)='1' and is_destroyed_l5(55)='0') then
r<=r_brick(55);
g<=g_brick(55);
b<=b_brick(55);
elsif(draw_l5(54)='1' and is_destroyed_l5(54)='0') then
r<=r_brick(54);
g<=g_brick(54);
b<=b_brick(54);
elsif(draw_l5(53)='1' and is_destroyed_l5(53)='0') then
r<=r_brick(53);
g<=g_brick(53);
b<=b_brick(53);
elsif(draw_l5(52)='1' and is_destroyed_l5(52)='0') then
r<=r_brick(52);
g<=g_brick(52);
b<=b_brick(52);
elsif(draw_l5(51)='1' and is_destroyed_l5(51)='0') then
r<=r_brick(51);
g<=g_brick(51);
b<=b_brick(51);
elsif(draw_l5(50)='1' and is_destroyed_l5(50)='0') then
r<=r_brick(50);
g<=g_brick(50);
b<=b_brick(50);
elsif(draw_l5(49)='1' and is_destroyed_l5(49)='0') then
r<=r_brick(49);
g<=g_brick(49);
b<=b_brick(49);
elsif(draw_l5(48)='1' and is_destroyed_l5(48)='0') then
r<=r_brick(48);
g<=g_brick(48);
b<=b_brick(48);
elsif(draw_l5(47)='1' and is_destroyed_l5(47)='0') then
r<=r_brick(47);
g<=g_brick(47);
b<=b_brick(47);
elsif(draw_l5(46)='1' and is_destroyed_l5(46)='0') then
r<=r_brick(46);
g<=g_brick(46);
b<=b_brick(46);
elsif(draw_l5(45)='1' and is_destroyed_l5(45)='0') then
r<=r_brick(45);
g<=g_brick(45);
b<=b_brick(45);
elsif(draw_l5(44)='1' and is_destroyed_l5(44)='0') then
r<=r_brick(44);
g<=g_brick(44);
b<=b_brick(44);
elsif(draw_l5(43)='1' and is_destroyed_l5(43)='0') then
r<=r_brick(43);
g<=g_brick(43);
b<=b_brick(43);
elsif(draw_l5(42)='1' and is_destroyed_l5(42)='0') then
r<=r_brick(42);
g<=g_brick(42);
b<=b_brick(42);
elsif(draw_l5(41)='1' and is_destroyed_l5(41)='0') then
r<=r_brick(41);
g<=g_brick(41);
b<=b_brick(41);
elsif(draw_l5(40)='1' and is_destroyed_l5(40)='0') then
r<=r_brick(40);
g<=g_brick(40);
b<=b_brick(40);
elsif(draw_l5(39)='1' and is_destroyed_l5(39)='0') then
r<=r_brick(39);
g<=g_brick(39);
b<=b_brick(39);
elsif(draw_l5(38)='1' and is_destroyed_l5(38)='0') then
r<=r_brick(38);
g<=g_brick(38);
b<=b_brick(38);
elsif(draw_l5(37)='1' and is_destroyed_l5(37)='0') then
r<=r_brick(37);
g<=g_brick(37);
b<=b_brick(37);
elsif(draw_l5(36)='1' and is_destroyed_l5(36)='0') then
r<=r_brick(36);
g<=g_brick(36);
b<=b_brick(36);
else
r<="0000"; --if nothing then black screen
g<="0000";
b<="0000";
end if;
else
r<="0000"; --make rgb 0 for period of fp,bp and sync duration
g<="0000";
b<="0000";
end if;
if(hpos<800) then
hpos<=hpos+1; --increment the horizontal pixel
else
hpos<=1; --if entire line covered then reset
if(vpos<525) then
vpos<=vpos+1; --increment the vertical pixel
else
vpos<=1; --if entire screen covered then reset
--1 means right direction or downwards
--0 means left direction or upwards
if(ball_x=5) then
ball_x_vel<='1'; --if reached left edge then change direction to right
elsif(ball_x=623) then
ball_x_vel<='0'; --if reached right end then change direction to left
else
null;
end if;
if(ball_y=2) then
ball_y_vel<='1'; --if reached top then reverse direction
elsif(ball_y=448 and (ball_x>=bat_x-14 and ball_x<=bat_x+51)) then --if reached bat height then check if hit the bat and then reverse direction else don't change
ball_y_vel<='0';
else
null;
end if;
if(is_destroyed_l1(71)='0')then--detect collision for ball and bricks of level1
if(coll_x_l1(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(71)<='1';
end if;
if(coll_y_l1(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(71)<='1';
end if;
end if;
if(is_destroyed_l1(70)='0')then
if(coll_x_l1(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(70)<='1';
end if;
if(coll_y_l1(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(70)<='1';
end if;
end if;
if(is_destroyed_l1(69)='0')then
if(coll_x_l1(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(69)<='1';
end if;
if(coll_y_l1(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(69)<='1';
end if;
end if;
if(is_destroyed_l1(68)='0')then
if(coll_x_l1(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(68)<='1';
end if;
if(coll_y_l1(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(68)<='1';
end if;
end if;
if(is_destroyed_l1(67)='0')then
if(coll_x_l1(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(67)<='1';
end if;
if(coll_y_l1(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(67)<='1';
end if;
end if;
if(is_destroyed_l1(66)='0')then
if(coll_x_l1(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(66)<='1';
end if;
if(coll_y_l1(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(66)<='1';
end if;
end if;
if(is_destroyed_l1(65)='0')then
if(coll_x_l1(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(65)<='1';
end if;
if(coll_y_l1(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(65)<='1';
end if;
end if;
if(is_destroyed_l1(64)='0')then
if(coll_x_l1(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(64)<='1';
end if;
if(coll_y_l1(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(64)<='1';
end if;
end if;
if(is_destroyed_l1(63)='0')then
if(coll_x_l1(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(63)<='1';
end if;
if(coll_y_l1(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(63)<='1';
end if;
end if;
if(is_destroyed_l1(62)='0')then
if(coll_x_l1(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(62)<='1';
end if;
if(coll_y_l1(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(62)<='1';
end if;
end if;
if(is_destroyed_l1(61)='0')then
if(coll_x_l1(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(61)<='1';
end if;
if(coll_y_l1(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(61)<='1';
end if;
end if;
if(is_destroyed_l1(60)='0')then
if(coll_x_l1(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(60)<='1';
end if;
if(coll_y_l1(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(60)<='1';
end if;
end if;
if(is_destroyed_l1(59)='0')then
if(coll_x_l1(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(59)<='1';
end if;
if(coll_y_l1(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(59)<='1';
end if;
end if;
if(is_destroyed_l1(58)='0')then
if(coll_x_l1(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(58)<='1';
end if;
if(coll_y_l1(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(58)<='1';
end if;
end if;
if(is_destroyed_l1(57)='0')then
if(coll_x_l1(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(57)<='1';
end if;
if(coll_y_l1(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(57)<='1';
end if;
end if;
if(is_destroyed_l1(56)='0')then
if(coll_x_l1(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(56)<='1';
end if;
if(coll_y_l1(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(56)<='1';
end if;
end if;
if(is_destroyed_l1(55)='0')then
if(coll_x_l1(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(55)<='1';
end if;
if(coll_y_l1(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(55)<='1';
end if;
end if;
if(is_destroyed_l1(54)='0')then
if(coll_x_l1(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(54)<='1';
end if;
if(coll_y_l1(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(54)<='1';
end if;
end if;
if(is_destroyed_l1(53)='0')then
if(coll_x_l1(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(53)<='1';
end if;
if(coll_y_l1(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(53)<='1';
end if;
end if;
if(is_destroyed_l1(52)='0')then
if(coll_x_l1(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(52)<='1';
end if;
if(coll_y_l1(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(52)<='1';
end if;
end if;
if(is_destroyed_l1(51)='0')then
if(coll_x_l1(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(51)<='1';
end if;
if(coll_y_l1(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(51)<='1';
end if;
end if;
if(is_destroyed_l1(50)='0')then
if(coll_x_l1(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(50)<='1';
end if;
if(coll_y_l1(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(50)<='1';
end if;
end if;
if(is_destroyed_l1(49)='0')then
if(coll_x_l1(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(49)<='1';
end if;
if(coll_y_l1(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(49)<='1';
end if;
end if;
if(is_destroyed_l1(48)='0')then
if(coll_x_l1(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(48)<='1';
end if;
if(coll_y_l1(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(48)<='1';
end if;
end if;
if(is_destroyed_l1(47)='0')then
if(coll_x_l1(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(47)<='1';
end if;
if(coll_y_l1(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(47)<='1';
end if;
end if;
if(is_destroyed_l1(46)='0')then
if(coll_x_l1(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(46)<='1';
end if;
if(coll_y_l1(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(46)<='1';
end if;
end if;
if(is_destroyed_l1(45)='0')then
if(coll_x_l1(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(45)<='1';
end if;
if(coll_y_l1(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(45)<='1';
end if;
end if;
if(is_destroyed_l1(44)='0')then
if(coll_x_l1(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(44)<='1';
end if;
if(coll_y_l1(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(44)<='1';
end if;
end if;
if(is_destroyed_l1(43)='0')then
if(coll_x_l1(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(43)<='1';
end if;
if(coll_y_l1(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(43)<='1';
end if;
end if;
if(is_destroyed_l1(42)='0')then
if(coll_x_l1(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(42)<='1';
end if;
if(coll_y_l1(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(42)<='1';
end if;
end if;
if(is_destroyed_l1(41)='0')then
if(coll_x_l1(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(41)<='1';
end if;
if(coll_y_l1(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(41)<='1';
end if;
end if;
if(is_destroyed_l1(40)='0')then
if(coll_x_l1(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(40)<='1';
end if;
if(coll_y_l1(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(40)<='1';
end if;
end if;
if(is_destroyed_l1(39)='0')then
if(coll_x_l1(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(39)<='1';
end if;
if(coll_y_l1(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(39)<='1';
end if;
end if;
if(is_destroyed_l1(38)='0')then
if(coll_x_l1(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(38)<='1';
end if;
if(coll_y_l1(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(38)<='1';
end if;
end if;
if(is_destroyed_l1(37)='0')then
if(coll_x_l1(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(37)<='1';
end if;
if(coll_y_l1(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(37)<='1';
end if;
end if;
if(is_destroyed_l1(36)='0')then
if(coll_x_l1(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(36)<='1';
end if;
if(coll_y_l1(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(36)<='1';
end if;
end if;
if(is_destroyed_l1(35)='0')then
if(coll_x_l1(35)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(35)<='1';
end if;
if(coll_y_l1(35)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(35)<='1';
end if;
end if;
if(is_destroyed_l1(34)='0')then
if(coll_x_l1(34)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(34)<='1';
end if;
if(coll_y_l1(34)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(34)<='1';
end if;
end if;
if(is_destroyed_l1(33)='0')then
if(coll_x_l1(33)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(33)<='1';
end if;
if(coll_y_l1(33)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(33)<='1';
end if;
end if;
if(is_destroyed_l1(32)='0')then
if(coll_x_l1(32)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(32)<='1';
end if;
if(coll_y_l1(32)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(32)<='1';
end if;
end if;
if(is_destroyed_l1(31)='0')then
if(coll_x_l1(31)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(31)<='1';
end if;
if(coll_y_l1(31)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(31)<='1';
end if;
end if;
if(is_destroyed_l1(30)='0')then
if(coll_x_l1(30)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(30)<='1';
end if;
if(coll_y_l1(30)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(30)<='1';
end if;
end if;
if(is_destroyed_l1(29)='0')then
if(coll_x_l1(29)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(29)<='1';
end if;
if(coll_y_l1(29)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(29)<='1';
end if;
end if;
if(is_destroyed_l1(28)='0')then
if(coll_x_l1(28)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(28)<='1';
end if;
if(coll_y_l1(28)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(28)<='1';
end if;
end if;
if(is_destroyed_l1(27)='0')then
if(coll_x_l1(27)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(27)<='1';
end if;
if(coll_y_l1(27)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(27)<='1';
end if;
end if;
if(is_destroyed_l1(26)='0')then
if(coll_x_l1(26)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(26)<='1';
end if;
if(coll_y_l1(26)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(26)<='1';
end if;
end if;
if(is_destroyed_l1(25)='0')then
if(coll_x_l1(25)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(25)<='1';
end if;
if(coll_y_l1(25)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(25)<='1';
end if;
end if;
if(is_destroyed_l1(24)='0')then
if(coll_x_l1(24)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(24)<='1';
end if;
if(coll_y_l1(24)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(24)<='1';
end if;
end if;
if(is_destroyed_l1(23)='0')then
if(coll_x_l1(23)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(23)<='1';
end if;
if(coll_y_l1(23)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(23)<='1';
end if;
end if;
if(is_destroyed_l1(22)='0')then
if(coll_x_l1(22)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(22)<='1';
end if;
if(coll_y_l1(22)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(22)<='1';
end if;
end if;
if(is_destroyed_l1(21)='0')then
if(coll_x_l1(21)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(21)<='1';
end if;
if(coll_y_l1(21)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(21)<='1';
end if;
end if;
if(is_destroyed_l1(20)='0')then
if(coll_x_l1(20)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(20)<='1';
end if;
if(coll_y_l1(20)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(20)<='1';
end if;
end if;
if(is_destroyed_l1(19)='0')then
if(coll_x_l1(19)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(19)<='1';
end if;
if(coll_y_l1(19)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(19)<='1';
end if;
end if;
if(is_destroyed_l1(18)='0')then
if(coll_x_l1(18)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(18)<='1';
end if;
if(coll_y_l1(18)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(18)<='1';
end if;
end if;
if(is_destroyed_l1(17)='0')then
if(coll_x_l1(17)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(17)<='1';
end if;
if(coll_y_l1(17)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(17)<='1';
end if;
end if;
if(is_destroyed_l1(16)='0')then
if(coll_x_l1(16)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(16)<='1';
end if;
if(coll_y_l1(16)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(16)<='1';
end if;
end if;
if(is_destroyed_l1(15)='0')then
if(coll_x_l1(15)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(15)<='1';
end if;
if(coll_y_l1(15)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(15)<='1';
end if;
end if;
if(is_destroyed_l1(14)='0')then
if(coll_x_l1(14)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(14)<='1';
end if;
if(coll_y_l1(14)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(14)<='1';
end if;
end if;
if(is_destroyed_l1(13)='0')then
if(coll_x_l1(13)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(13)<='1';
end if;
if(coll_y_l1(13)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(13)<='1';
end if;
end if;
if(is_destroyed_l1(12)='0')then
if(coll_x_l1(12)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(12)<='1';
end if;
if(coll_y_l1(12)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(12)<='1';
end if;
end if;
if(is_destroyed_l1(11)='0')then
if(coll_x_l1(11)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(11)<='1';
end if;
if(coll_y_l1(11)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(11)<='1';
end if;
end if;
if(is_destroyed_l1(10)='0')then
if(coll_x_l1(10)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(10)<='1';
end if;
if(coll_y_l1(10)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(10)<='1';
end if;
end if;
if(is_destroyed_l1(9)='0')then
if(coll_x_l1(9)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(9)<='1';
end if;
if(coll_y_l1(9)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(9)<='1';
end if;
end if;
if(is_destroyed_l1(8)='0')then
if(coll_x_l1(8)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(8)<='1';
end if;
if(coll_y_l1(8)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(8)<='1';
end if;
end if;
if(is_destroyed_l1(7)='0')then
if(coll_x_l1(7)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(7)<='1';
end if;
if(coll_y_l1(7)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(7)<='1';
end if;
end if;
if(is_destroyed_l1(6)='0')then
if(coll_x_l1(6)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(6)<='1';
end if;
if(coll_y_l1(6)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(6)<='1';
end if;
end if;
if(is_destroyed_l1(5)='0')then
if(coll_x_l1(5)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(5)<='1';
end if;
if(coll_y_l1(5)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(5)<='1';
end if;
end if;
if(is_destroyed_l1(4)='0')then
if(coll_x_l1(4)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(4)<='1';
end if;
if(coll_y_l1(4)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(4)<='1';
end if;
end if;
if(is_destroyed_l1(3)='0')then
if(coll_x_l1(3)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(3)<='1';
end if;
if(coll_y_l1(3)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(3)<='1';
end if;
end if;
if(is_destroyed_l1(2)='0')then
if(coll_x_l1(2)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(2)<='1';
end if;
if(coll_y_l1(2)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(2)<='1';
end if;
end if;
if(is_destroyed_l1(1)='0')then
if(coll_x_l1(1)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(1)<='1';
end if;
if(coll_y_l1(1)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(1)<='1';
end if;
end if;
if(is_destroyed_l1(0)='0')then
if(coll_x_l1(0)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l1(0)<='1';
end if;
if(coll_y_l1(0)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l1(0)<='1';
end if;
end if;
if(is_destroyed_l2(71)='0')then--detect collision for ball and bricks of level2
if(coll_x_l2(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(71)<='1';
end if;
if(coll_y_l2(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(71)<='1';
end if;
end if;
if(is_destroyed_l2(70)='0')then
if(coll_x_l2(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(70)<='1';
end if;
if(coll_y_l2(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(70)<='1';
end if;
end if;
if(is_destroyed_l2(69)='0')then
if(coll_x_l2(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(69)<='1';
end if;
if(coll_y_l2(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(69)<='1';
end if;
end if;
if(is_destroyed_l2(68)='0')then
if(coll_x_l2(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(68)<='1';
end if;
if(coll_y_l2(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(68)<='1';
end if;
end if;
if(is_destroyed_l2(67)='0')then
if(coll_x_l2(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(67)<='1';
end if;
if(coll_y_l2(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(67)<='1';
end if;
end if;
if(is_destroyed_l2(66)='0')then
if(coll_x_l2(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(66)<='1';
end if;
if(coll_y_l2(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(66)<='1';
end if;
end if;
if(is_destroyed_l2(65)='0')then
if(coll_x_l2(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(65)<='1';
end if;
if(coll_y_l2(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(65)<='1';
end if;
end if;
if(is_destroyed_l2(64)='0')then
if(coll_x_l2(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(64)<='1';
end if;
if(coll_y_l2(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(64)<='1';
end if;
end if;
if(is_destroyed_l2(63)='0')then
if(coll_x_l2(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(63)<='1';
end if;
if(coll_y_l2(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(63)<='1';
end if;
end if;
if(is_destroyed_l2(62)='0')then
if(coll_x_l2(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(62)<='1';
end if;
if(coll_y_l2(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(62)<='1';
end if;
end if;
if(is_destroyed_l2(61)='0')then
if(coll_x_l2(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(61)<='1';
end if;
if(coll_y_l2(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(61)<='1';
end if;
end if;
if(is_destroyed_l2(60)='0')then
if(coll_x_l2(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(60)<='1';
end if;
if(coll_y_l2(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(60)<='1';
end if;
end if;
if(is_destroyed_l2(59)='0')then
if(coll_x_l2(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(59)<='1';
end if;
if(coll_y_l2(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(59)<='1';
end if;
end if;
if(is_destroyed_l2(58)='0')then
if(coll_x_l2(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(58)<='1';
end if;
if(coll_y_l2(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(58)<='1';
end if;
end if;
if(is_destroyed_l2(57)='0')then
if(coll_x_l2(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(57)<='1';
end if;
if(coll_y_l2(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(57)<='1';
end if;
end if;
if(is_destroyed_l2(56)='0')then
if(coll_x_l2(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(56)<='1';
end if;
if(coll_y_l2(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(56)<='1';
end if;
end if;
if(is_destroyed_l2(55)='0')then
if(coll_x_l2(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(55)<='1';
end if;
if(coll_y_l2(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(55)<='1';
end if;
end if;
if(is_destroyed_l2(54)='0')then
if(coll_x_l2(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(54)<='1';
end if;
if(coll_y_l2(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(54)<='1';
end if;
end if;
if(is_destroyed_l2(53)='0')then
if(coll_x_l2(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(53)<='1';
end if;
if(coll_y_l2(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(53)<='1';
end if;
end if;
if(is_destroyed_l2(52)='0')then
if(coll_x_l2(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(52)<='1';
end if;
if(coll_y_l2(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(52)<='1';
end if;
end if;
if(is_destroyed_l2(51)='0')then
if(coll_x_l2(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(51)<='1';
end if;
if(coll_y_l2(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(51)<='1';
end if;
end if;
if(is_destroyed_l2(50)='0')then
if(coll_x_l2(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(50)<='1';
end if;
if(coll_y_l2(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(50)<='1';
end if;
end if;
if(is_destroyed_l2(49)='0')then
if(coll_x_l2(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(49)<='1';
end if;
if(coll_y_l2(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(49)<='1';
end if;
end if;
if(is_destroyed_l2(48)='0')then
if(coll_x_l2(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(48)<='1';
end if;
if(coll_y_l2(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(48)<='1';
end if;
end if;
if(is_destroyed_l2(47)='0')then
if(coll_x_l2(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(47)<='1';
end if;
if(coll_y_l2(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(47)<='1';
end if;
end if;
if(is_destroyed_l2(46)='0')then
if(coll_x_l2(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(46)<='1';
end if;
if(coll_y_l2(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(46)<='1';
end if;
end if;
if(is_destroyed_l2(45)='0')then
if(coll_x_l2(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(45)<='1';
end if;
if(coll_y_l2(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(45)<='1';
end if;
end if;
if(is_destroyed_l2(44)='0')then
if(coll_x_l2(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l2(44)<='1';
end if;
if(coll_y_l2(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l2(44)<='1';
end if;
end if;
if(is_destroyed_l3(71)='0')then--detect collision for ball and bricks of level3
if(coll_x_l3(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(71)<='1';
end if;
if(coll_y_l3(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(71)<='1';
end if;
end if;
if(is_destroyed_l3(70)='0')then
if(coll_x_l3(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(70)<='1';
end if;
if(coll_y_l3(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(70)<='1';
end if;
end if;
if(is_destroyed_l3(69)='0')then
if(coll_x_l3(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(69)<='1';
end if;
if(coll_y_l3(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(69)<='1';
end if;
end if;
if(is_destroyed_l3(68)='0')then
if(coll_x_l3(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(68)<='1';
end if;
if(coll_y_l3(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(68)<='1';
end if;
end if;
if(is_destroyed_l3(67)='0')then
if(coll_x_l3(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(67)<='1';
end if;
if(coll_y_l3(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(67)<='1';
end if;
end if;
if(is_destroyed_l3(66)='0')then
if(coll_x_l3(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(66)<='1';
end if;
if(coll_y_l3(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(66)<='1';
end if;
end if;
if(is_destroyed_l3(65)='0')then
if(coll_x_l3(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(65)<='1';
end if;
if(coll_y_l3(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(65)<='1';
end if;
end if;
if(is_destroyed_l3(64)='0')then
if(coll_x_l3(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(64)<='1';
end if;
if(coll_y_l3(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(64)<='1';
end if;
end if;
if(is_destroyed_l3(63)='0')then
if(coll_x_l3(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(63)<='1';
end if;
if(coll_y_l3(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(63)<='1';
end if;
end if;
if(is_destroyed_l3(62)='0')then
if(coll_x_l3(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(62)<='1';
end if;
if(coll_y_l3(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(62)<='1';
end if;
end if;
if(is_destroyed_l3(61)='0')then
if(coll_x_l3(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(61)<='1';
end if;
if(coll_y_l3(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(61)<='1';
end if;
end if;
if(is_destroyed_l3(60)='0')then
if(coll_x_l3(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(60)<='1';
end if;
if(coll_y_l3(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(60)<='1';
end if;
end if;
if(is_destroyed_l3(59)='0')then
if(coll_x_l3(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(59)<='1';
end if;
if(coll_y_l3(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(59)<='1';
end if;
end if;
if(is_destroyed_l3(58)='0')then
if(coll_x_l3(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(58)<='1';
end if;
if(coll_y_l3(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(58)<='1';
end if;
end if;
if(is_destroyed_l3(57)='0')then
if(coll_x_l3(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(57)<='1';
end if;
if(coll_y_l3(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(57)<='1';
end if;
end if;
if(is_destroyed_l3(56)='0')then
if(coll_x_l3(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(56)<='1';
end if;
if(coll_y_l3(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(56)<='1';
end if;
end if;
if(is_destroyed_l3(55)='0')then
if(coll_x_l3(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(55)<='1';
end if;
if(coll_y_l3(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(55)<='1';
end if;
end if;
if(is_destroyed_l3(54)='0')then
if(coll_x_l3(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(54)<='1';
end if;
if(coll_y_l3(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(54)<='1';
end if;
end if;
if(is_destroyed_l3(53)='0')then
if(coll_x_l3(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(53)<='1';
end if;
if(coll_y_l3(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(53)<='1';
end if;
end if;
if(is_destroyed_l3(52)='0')then
if(coll_x_l3(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(52)<='1';
end if;
if(coll_y_l3(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(52)<='1';
end if;
end if;
if(is_destroyed_l3(51)='0')then
if(coll_x_l3(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(51)<='1';
end if;
if(coll_y_l3(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(51)<='1';
end if;
end if;
if(is_destroyed_l3(50)='0')then
if(coll_x_l3(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(50)<='1';
end if;
if(coll_y_l3(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(50)<='1';
end if;
end if;
if(is_destroyed_l3(49)='0')then
if(coll_x_l3(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(49)<='1';
end if;
if(coll_y_l3(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(49)<='1';
end if;
end if;
if(is_destroyed_l3(48)='0')then
if(coll_x_l3(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(48)<='1';
end if;
if(coll_y_l3(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(48)<='1';
end if;
end if;
if(is_destroyed_l3(47)='0')then
if(coll_x_l3(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(47)<='1';
end if;
if(coll_y_l3(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(47)<='1';
end if;
end if;
if(is_destroyed_l3(46)='0')then
if(coll_x_l3(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(46)<='1';
end if;
if(coll_y_l3(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(46)<='1';
end if;
end if;
if(is_destroyed_l3(45)='0')then
if(coll_x_l3(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(45)<='1';
end if;
if(coll_y_l3(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(45)<='1';
end if;
end if;
if(is_destroyed_l3(44)='0')then
if(coll_x_l3(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(44)<='1';
end if;
if(coll_y_l3(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(44)<='1';
end if;
end if;
if(is_destroyed_l3(43)='0')then
if(coll_x_l3(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(43)<='1';
end if;
if(coll_y_l3(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(43)<='1';
end if;
end if;
if(is_destroyed_l3(42)='0')then
if(coll_x_l3(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(42)<='1';
end if;
if(coll_y_l3(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(42)<='1';
end if;
end if;
if(is_destroyed_l3(41)='0')then
if(coll_x_l3(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(41)<='1';
end if;
if(coll_y_l3(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(41)<='1';
end if;
end if;
if(is_destroyed_l3(40)='0')then
if(coll_x_l3(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(40)<='1';
end if;
if(coll_y_l3(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(40)<='1';
end if;
end if;
if(is_destroyed_l3(39)='0')then
if(coll_x_l3(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(39)<='1';
end if;
if(coll_y_l3(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(39)<='1';
end if;
end if;
if(is_destroyed_l3(38)='0')then
if(coll_x_l3(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(38)<='1';
end if;
if(coll_y_l3(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(38)<='1';
end if;
end if;
if(is_destroyed_l3(37)='0')then
if(coll_x_l3(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(37)<='1';
end if;
if(coll_y_l3(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(37)<='1';
end if;
end if;
if(is_destroyed_l3(36)='0')then
if(coll_x_l3(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(36)<='1';
end if;
if(coll_y_l3(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(36)<='1';
end if;
end if;
if(is_destroyed_l3(35)='0')then
if(coll_x_l3(35)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(35)<='1';
end if;
if(coll_y_l3(35)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(35)<='1';
end if;
end if;
if(is_destroyed_l3(34)='0')then
if(coll_x_l3(34)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(34)<='1';
end if;
if(coll_y_l3(34)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(34)<='1';
end if;
end if;
if(is_destroyed_l3(33)='0')then
if(coll_x_l3(33)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(33)<='1';
end if;
if(coll_y_l3(33)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(33)<='1';
end if;
end if;
if(is_destroyed_l3(32)='0')then
if(coll_x_l3(32)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(32)<='1';
end if;
if(coll_y_l3(32)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(32)<='1';
end if;
end if;
if(is_destroyed_l3(31)='0')then
if(coll_x_l3(31)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(31)<='1';
end if;
if(coll_y_l3(31)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(31)<='1';
end if;
end if;
if(is_destroyed_l3(30)='0')then
if(coll_x_l3(30)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(30)<='1';
end if;
if(coll_y_l3(30)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(30)<='1';
end if;
end if;
if(is_destroyed_l3(29)='0')then
if(coll_x_l3(29)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(29)<='1';
end if;
if(coll_y_l3(29)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(29)<='1';
end if;
end if;
if(is_destroyed_l3(28)='0')then
if(coll_x_l3(28)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(28)<='1';
end if;
if(coll_y_l3(28)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(28)<='1';
end if;
end if;
if(is_destroyed_l3(27)='0')then
if(coll_x_l3(27)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(27)<='1';
end if;
if(coll_y_l3(27)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(27)<='1';
end if;
end if;
if(is_destroyed_l3(26)='0')then
if(coll_x_l3(26)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(26)<='1';
end if;
if(coll_y_l3(26)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(26)<='1';
end if;
end if;
if(is_destroyed_l3(25)='0')then
if(coll_x_l3(25)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(25)<='1';
end if;
if(coll_y_l3(25)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(25)<='1';
end if;
end if;
if(is_destroyed_l3(24)='0')then
if(coll_x_l3(24)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(24)<='1';
end if;
if(coll_y_l3(24)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(24)<='1';
end if;
end if;
if(is_destroyed_l3(23)='0')then
if(coll_x_l3(23)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(23)<='1';
end if;
if(coll_y_l3(23)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(23)<='1';
end if;
end if;
if(is_destroyed_l3(22)='0')then
if(coll_x_l3(22)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(22)<='1';
end if;
if(coll_y_l3(22)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(22)<='1';
end if;
end if;
if(is_destroyed_l3(21)='0')then
if(coll_x_l3(21)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(21)<='1';
end if;
if(coll_y_l3(21)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(21)<='1';
end if;
end if;
if(is_destroyed_l3(20)='0')then
if(coll_x_l3(20)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(20)<='1';
end if;
if(coll_y_l3(20)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(20)<='1';
end if;
end if;
if(is_destroyed_l3(19)='0')then
if(coll_x_l3(19)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(19)<='1';
end if;
if(coll_y_l3(19)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(19)<='1';
end if;
end if;
if(is_destroyed_l3(18)='0')then
if(coll_x_l3(18)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(18)<='1';
end if;
if(coll_y_l3(18)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(18)<='1';
end if;
end if;
if(is_destroyed_l3(17)='0')then
if(coll_x_l3(17)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(17)<='1';
end if;
if(coll_y_l3(17)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(17)<='1';
end if;
end if;
if(is_destroyed_l3(16)='0')then
if(coll_x_l3(16)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(16)<='1';
end if;
if(coll_y_l3(16)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(16)<='1';
end if;
end if;
if(is_destroyed_l3(15)='0')then
if(coll_x_l3(15)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(15)<='1';
end if;
if(coll_y_l3(15)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(15)<='1';
end if;
end if;
if(is_destroyed_l3(14)='0')then
if(coll_x_l3(14)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(14)<='1';
end if;
if(coll_y_l3(14)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(14)<='1';
end if;
end if;
if(is_destroyed_l3(13)='0')then
if(coll_x_l3(13)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(13)<='1';
end if;
if(coll_y_l3(13)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(13)<='1';
end if;
end if;
if(is_destroyed_l3(12)='0')then
if(coll_x_l3(12)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(12)<='1';
end if;
if(coll_y_l3(12)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(12)<='1';
end if;
end if;
if(is_destroyed_l3(11)='0')then
if(coll_x_l3(11)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(11)<='1';
end if;
if(coll_y_l3(11)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(11)<='1';
end if;
end if;
if(is_destroyed_l3(10)='0')then
if(coll_x_l3(10)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(10)<='1';
end if;
if(coll_y_l3(10)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(10)<='1';
end if;
end if;
if(is_destroyed_l3(9)='0')then
if(coll_x_l3(9)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(9)<='1';
end if;
if(coll_y_l3(9)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(9)<='1';
end if;
end if;
if(is_destroyed_l3(8)='0')then
if(coll_x_l3(8)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(8)<='1';
end if;
if(coll_y_l3(8)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(8)<='1';
end if;
end if;
if(is_destroyed_l3(7)='0')then
if(coll_x_l3(7)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(7)<='1';
end if;
if(coll_y_l3(7)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(7)<='1';
end if;
end if;
if(is_destroyed_l3(6)='0')then
if(coll_x_l3(6)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(6)<='1';
end if;
if(coll_y_l3(6)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(6)<='1';
end if;
end if;
if(is_destroyed_l3(5)='0')then
if(coll_x_l3(5)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(5)<='1';
end if;
if(coll_y_l3(5)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(5)<='1';
end if;
end if;
if(is_destroyed_l3(4)='0')then
if(coll_x_l3(4)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(4)<='1';
end if;
if(coll_y_l3(4)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(4)<='1';
end if;
end if;
if(is_destroyed_l3(3)='0')then
if(coll_x_l3(3)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(3)<='1';
end if;
if(coll_y_l3(3)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(3)<='1';
end if;
end if;
if(is_destroyed_l3(2)='0')then
if(coll_x_l3(2)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(2)<='1';
end if;
if(coll_y_l3(2)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(2)<='1';
end if;
end if;
if(is_destroyed_l3(1)='0')then
if(coll_x_l3(1)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(1)<='1';
end if;
if(coll_y_l3(1)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(1)<='1';
end if;
end if;
if(is_destroyed_l3(0)='0')then
if(coll_x_l3(0)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l3(0)<='1';
end if;
if(coll_y_l3(0)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l3(0)<='1';
end if;
end if;
if(is_destroyed_l4(71)='0')then--detect collision for ball and bricks of level4
if(coll_x_l4(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(71)<='1';
end if;
if(coll_y_l4(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(71)<='1';
end if;
end if;
if(is_destroyed_l4(70)='0')then
if(coll_x_l4(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(70)<='1';
end if;
if(coll_y_l4(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(70)<='1';
end if;
end if;
if(is_destroyed_l4(69)='0')then
if(coll_x_l4(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(69)<='1';
end if;
if(coll_y_l4(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(69)<='1';
end if;
end if;
if(is_destroyed_l4(68)='0')then
if(coll_x_l4(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(68)<='1';
end if;
if(coll_y_l4(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(68)<='1';
end if;
end if;
if(is_destroyed_l4(67)='0')then
if(coll_x_l4(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(67)<='1';
end if;
if(coll_y_l4(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(67)<='1';
end if;
end if;
if(is_destroyed_l4(66)='0')then
if(coll_x_l4(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(66)<='1';
end if;
if(coll_y_l4(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(66)<='1';
end if;
end if;
if(is_destroyed_l4(65)='0')then
if(coll_x_l4(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(65)<='1';
end if;
if(coll_y_l4(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(65)<='1';
end if;
end if;
if(is_destroyed_l4(64)='0')then
if(coll_x_l4(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(64)<='1';
end if;
if(coll_y_l4(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(64)<='1';
end if;
end if;
if(is_destroyed_l4(63)='0')then
if(coll_x_l4(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(63)<='1';
end if;
if(coll_y_l4(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(63)<='1';
end if;
end if;
if(is_destroyed_l4(62)='0')then
if(coll_x_l4(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(62)<='1';
end if;
if(coll_y_l4(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(62)<='1';
end if;
end if;
if(is_destroyed_l4(61)='0')then
if(coll_x_l4(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(61)<='1';
end if;
if(coll_y_l4(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(61)<='1';
end if;
end if;
if(is_destroyed_l4(60)='0')then
if(coll_x_l4(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(60)<='1';
end if;
if(coll_y_l4(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(60)<='1';
end if;
end if;
if(is_destroyed_l4(59)='0')then
if(coll_x_l4(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(59)<='1';
end if;
if(coll_y_l4(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(59)<='1';
end if;
end if;
if(is_destroyed_l4(58)='0')then
if(coll_x_l4(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(58)<='1';
end if;
if(coll_y_l4(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(58)<='1';
end if;
end if;
if(is_destroyed_l4(57)='0')then
if(coll_x_l4(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(57)<='1';
end if;
if(coll_y_l4(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(57)<='1';
end if;
end if;
if(is_destroyed_l4(56)='0')then
if(coll_x_l4(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(56)<='1';
end if;
if(coll_y_l4(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(56)<='1';
end if;
end if;
if(is_destroyed_l4(55)='0')then
if(coll_x_l4(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(55)<='1';
end if;
if(coll_y_l4(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(55)<='1';
end if;
end if;
if(is_destroyed_l4(54)='0')then
if(coll_x_l4(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(54)<='1';
end if;
if(coll_y_l4(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(54)<='1';
end if;
end if;
if(is_destroyed_l4(53)='0')then
if(coll_x_l4(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(53)<='1';
end if;
if(coll_y_l4(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(53)<='1';
end if;
end if;
if(is_destroyed_l4(52)='0')then
if(coll_x_l4(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(52)<='1';
end if;
if(coll_y_l4(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(52)<='1';
end if;
end if;
if(is_destroyed_l4(51)='0')then
if(coll_x_l4(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(51)<='1';
end if;
if(coll_y_l4(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(51)<='1';
end if;
end if;
if(is_destroyed_l4(50)='0')then
if(coll_x_l4(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(50)<='1';
end if;
if(coll_y_l4(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(50)<='1';
end if;
end if;
if(is_destroyed_l4(49)='0')then
if(coll_x_l4(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(49)<='1';
end if;
if(coll_y_l4(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(49)<='1';
end if;
end if;
if(is_destroyed_l4(48)='0')then
if(coll_x_l4(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(48)<='1';
end if;
if(coll_y_l4(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(48)<='1';
end if;
end if;
if(is_destroyed_l4(47)='0')then
if(coll_x_l4(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(47)<='1';
end if;
if(coll_y_l4(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(47)<='1';
end if;
end if;
if(is_destroyed_l4(46)='0')then
if(coll_x_l4(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(46)<='1';
end if;
if(coll_y_l4(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(46)<='1';
end if;
end if;
if(is_destroyed_l4(45)='0')then
if(coll_x_l4(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(45)<='1';
end if;
if(coll_y_l4(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(45)<='1';
end if;
end if;
if(is_destroyed_l4(44)='0')then
if(coll_x_l4(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(44)<='1';
end if;
if(coll_y_l4(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(44)<='1';
end if;
end if;
if(is_destroyed_l4(43)='0')then
if(coll_x_l4(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(43)<='1';
end if;
if(coll_y_l4(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(43)<='1';
end if;
end if;
if(is_destroyed_l4(42)='0')then
if(coll_x_l4(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(42)<='1';
end if;
if(coll_y_l4(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(42)<='1';
end if;
end if;
if(is_destroyed_l4(41)='0')then
if(coll_x_l4(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(41)<='1';
end if;
if(coll_y_l4(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(41)<='1';
end if;
end if;
if(is_destroyed_l4(40)='0')then
if(coll_x_l4(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(40)<='1';
end if;
if(coll_y_l4(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(40)<='1';
end if;
end if;
if(is_destroyed_l4(39)='0')then
if(coll_x_l4(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(39)<='1';
end if;
if(coll_y_l4(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(39)<='1';
end if;
end if;
if(is_destroyed_l4(38)='0')then
if(coll_x_l4(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(38)<='1';
end if;
if(coll_y_l4(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(38)<='1';
end if;
end if;
if(is_destroyed_l4(37)='0')then
if(coll_x_l4(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(37)<='1';
end if;
if(coll_y_l4(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(37)<='1';
end if;
end if;
if(is_destroyed_l4(36)='0')then
if(coll_x_l4(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(36)<='1';
end if;
if(coll_y_l4(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(36)<='1';
end if;
end if;
if(is_destroyed_l4(35)='0')then
if(coll_x_l4(35)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(35)<='1';
end if;
if(coll_y_l4(35)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(35)<='1';
end if;
end if;
if(is_destroyed_l4(34)='0')then
if(coll_x_l4(34)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(34)<='1';
end if;
if(coll_y_l4(34)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(34)<='1';
end if;
end if;
if(is_destroyed_l4(33)='0')then
if(coll_x_l4(33)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(33)<='1';
end if;
if(coll_y_l4(33)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(33)<='1';
end if;
end if;
if(is_destroyed_l4(32)='0')then
if(coll_x_l4(32)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(32)<='1';
end if;
if(coll_y_l4(32)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(32)<='1';
end if;
end if;
if(is_destroyed_l4(31)='0')then
if(coll_x_l4(31)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(31)<='1';
end if;
if(coll_y_l4(31)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(31)<='1';
end if;
end if;
if(is_destroyed_l4(30)='0')then
if(coll_x_l4(30)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(30)<='1';
end if;
if(coll_y_l4(30)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(30)<='1';
end if;
end if;
if(is_destroyed_l4(29)='0')then
if(coll_x_l4(29)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(29)<='1';
end if;
if(coll_y_l4(29)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(29)<='1';
end if;
end if;
if(is_destroyed_l4(28)='0')then
if(coll_x_l4(28)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(28)<='1';
end if;
if(coll_y_l4(28)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(28)<='1';
end if;
end if;
if(is_destroyed_l4(27)='0')then
if(coll_x_l4(27)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(27)<='1';
end if;
if(coll_y_l4(27)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(27)<='1';
end if;
end if;
if(is_destroyed_l4(26)='0')then
if(coll_x_l4(26)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(26)<='1';
end if;
if(coll_y_l4(26)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(26)<='1';
end if;
end if;
if(is_destroyed_l4(25)='0')then
if(coll_x_l4(25)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(25)<='1';
end if;
if(coll_y_l4(25)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(25)<='1';
end if;
end if;
if(is_destroyed_l4(24)='0')then
if(coll_x_l4(24)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(24)<='1';
end if;
if(coll_y_l4(24)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(24)<='1';
end if;
end if;
if(is_destroyed_l4(23)='0')then
if(coll_x_l4(23)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(23)<='1';
end if;
if(coll_y_l4(23)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(23)<='1';
end if;
end if;
if(is_destroyed_l4(22)='0')then
if(coll_x_l4(22)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(22)<='1';
end if;
if(coll_y_l4(22)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(22)<='1';
end if;
end if;
if(is_destroyed_l4(21)='0')then
if(coll_x_l4(21)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(21)<='1';
end if;
if(coll_y_l4(21)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(21)<='1';
end if;
end if;
if(is_destroyed_l4(20)='0')then
if(coll_x_l4(20)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(20)<='1';
end if;
if(coll_y_l4(20)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(20)<='1';
end if;
end if;
if(is_destroyed_l4(19)='0')then
if(coll_x_l4(19)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(19)<='1';
end if;
if(coll_y_l4(19)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(19)<='1';
end if;
end if;
if(is_destroyed_l4(18)='0')then
if(coll_x_l4(18)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(18)<='1';
end if;
if(coll_y_l4(18)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(18)<='1';
end if;
end if;
if(is_destroyed_l4(17)='0')then
if(coll_x_l4(17)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(17)<='1';
end if;
if(coll_y_l4(17)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(17)<='1';
end if;
end if;
if(is_destroyed_l4(16)='0')then
if(coll_x_l4(16)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(16)<='1';
end if;
if(coll_y_l4(16)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(16)<='1';
end if;
end if;
if(is_destroyed_l4(15)='0')then
if(coll_x_l4(15)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(15)<='1';
end if;
if(coll_y_l4(15)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(15)<='1';
end if;
end if;
if(is_destroyed_l4(14)='0')then
if(coll_x_l4(14)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(14)<='1';
end if;
if(coll_y_l4(14)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(14)<='1';
end if;
end if;
if(is_destroyed_l4(13)='0')then
if(coll_x_l4(13)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(13)<='1';
end if;
if(coll_y_l4(13)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(13)<='1';
end if;
end if;
if(is_destroyed_l4(12)='0')then
if(coll_x_l4(12)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(12)<='1';
end if;
if(coll_y_l4(12)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(12)<='1';
end if;
end if;
if(is_destroyed_l4(11)='0')then
if(coll_x_l4(11)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(11)<='1';
end if;
if(coll_y_l4(11)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(11)<='1';
end if;
end if;
if(is_destroyed_l4(10)='0')then
if(coll_x_l4(10)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(10)<='1';
end if;
if(coll_y_l4(10)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(10)<='1';
end if;
end if;
if(is_destroyed_l4(9)='0')then
if(coll_x_l4(9)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(9)<='1';
end if;
if(coll_y_l4(9)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(9)<='1';
end if;
end if;
if(is_destroyed_l4(8)='0')then
if(coll_x_l4(8)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l4(8)<='1';
end if;
if(coll_y_l4(8)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l4(8)<='1';
end if;
end if;
if(is_destroyed_l5(71)='0')then--detect collision for ball and bricks of level5
if(coll_x_l5(71)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(71)<='1';
end if;
if(coll_y_l5(71)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(71)<='1';
end if;
end if;
if(is_destroyed_l5(70)='0')then
if(coll_x_l5(70)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(70)<='1';
end if;
if(coll_y_l5(70)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(70)<='1';
end if;
end if;
if(is_destroyed_l5(69)='0')then
if(coll_x_l5(69)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(69)<='1';
end if;
if(coll_y_l5(69)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(69)<='1';
end if;
end if;
if(is_destroyed_l5(68)='0')then
if(coll_x_l5(68)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(68)<='1';
end if;
if(coll_y_l5(68)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(68)<='1';
end if;
end if;
if(is_destroyed_l5(67)='0')then
if(coll_x_l5(67)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(67)<='1';
end if;
if(coll_y_l5(67)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(67)<='1';
end if;
end if;
if(is_destroyed_l5(66)='0')then
if(coll_x_l5(66)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(66)<='1';
end if;
if(coll_y_l5(66)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(66)<='1';
end if;
end if;
if(is_destroyed_l5(65)='0')then
if(coll_x_l5(65)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(65)<='1';
end if;
if(coll_y_l5(65)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(65)<='1';
end if;
end if;
if(is_destroyed_l5(64)='0')then
if(coll_x_l5(64)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(64)<='1';
end if;
if(coll_y_l5(64)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(64)<='1';
end if;
end if;
if(is_destroyed_l5(63)='0')then
if(coll_x_l5(63)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(63)<='1';
end if;
if(coll_y_l5(63)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(63)<='1';
end if;
end if;
if(is_destroyed_l5(62)='0')then
if(coll_x_l5(62)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(62)<='1';
end if;
if(coll_y_l5(62)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(62)<='1';
end if;
end if;
if(is_destroyed_l5(61)='0')then
if(coll_x_l5(61)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(61)<='1';
end if;
if(coll_y_l5(61)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(61)<='1';
end if;
end if;
if(is_destroyed_l5(60)='0')then
if(coll_x_l5(60)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(60)<='1';
end if;
if(coll_y_l5(60)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(60)<='1';
end if;
end if;
if(is_destroyed_l5(59)='0')then
if(coll_x_l5(59)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(59)<='1';
end if;
if(coll_y_l5(59)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(59)<='1';
end if;
end if;
if(is_destroyed_l5(58)='0')then
if(coll_x_l5(58)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(58)<='1';
end if;
if(coll_y_l5(58)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(58)<='1';
end if;
end if;
if(is_destroyed_l5(57)='0')then
if(coll_x_l5(57)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(57)<='1';
end if;
if(coll_y_l5(57)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(57)<='1';
end if;
end if;
if(is_destroyed_l5(56)='0')then
if(coll_x_l5(56)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(56)<='1';
end if;
if(coll_y_l5(56)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(56)<='1';
end if;
end if;
if(is_destroyed_l5(55)='0')then
if(coll_x_l5(55)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(55)<='1';
end if;
if(coll_y_l5(55)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(55)<='1';
end if;
end if;
if(is_destroyed_l5(54)='0')then
if(coll_x_l5(54)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(54)<='1';
end if;
if(coll_y_l5(54)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(54)<='1';
end if;
end if;
if(is_destroyed_l5(53)='0')then
if(coll_x_l5(53)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(53)<='1';
end if;
if(coll_y_l5(53)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(53)<='1';
end if;
end if;
if(is_destroyed_l5(52)='0')then
if(coll_x_l5(52)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(52)<='1';
end if;
if(coll_y_l5(52)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(52)<='1';
end if;
end if;
if(is_destroyed_l5(51)='0')then
if(coll_x_l5(51)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(51)<='1';
end if;
if(coll_y_l5(51)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(51)<='1';
end if;
end if;
if(is_destroyed_l5(50)='0')then
if(coll_x_l5(50)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(50)<='1';
end if;
if(coll_y_l5(50)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(50)<='1';
end if;
end if;
if(is_destroyed_l5(49)='0')then
if(coll_x_l5(49)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(49)<='1';
end if;
if(coll_y_l5(49)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(49)<='1';
end if;
end if;
if(is_destroyed_l5(48)='0')then
if(coll_x_l5(48)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(48)<='1';
end if;
if(coll_y_l5(48)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(48)<='1';
end if;
end if;
if(is_destroyed_l5(47)='0')then
if(coll_x_l5(47)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(47)<='1';
end if;
if(coll_y_l5(47)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(47)<='1';
end if;
end if;
if(is_destroyed_l5(46)='0')then
if(coll_x_l5(46)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(46)<='1';
end if;
if(coll_y_l5(46)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(46)<='1';
end if;
end if;
if(is_destroyed_l5(45)='0')then
if(coll_x_l5(45)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(45)<='1';
end if;
if(coll_y_l5(45)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(45)<='1';
end if;
end if;
if(is_destroyed_l5(44)='0')then
if(coll_x_l5(44)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(44)<='1';
end if;
if(coll_y_l5(44)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(44)<='1';
end if;
end if;
if(is_destroyed_l5(43)='0')then
if(coll_x_l5(43)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(43)<='1';
end if;
if(coll_y_l5(43)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(43)<='1';
end if;
end if;
if(is_destroyed_l5(42)='0')then
if(coll_x_l5(42)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(42)<='1';
end if;
if(coll_y_l5(42)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(42)<='1';
end if;
end if;
if(is_destroyed_l5(41)='0')then
if(coll_x_l5(41)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(41)<='1';
end if;
if(coll_y_l5(41)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(41)<='1';
end if;
end if;
if(is_destroyed_l5(40)='0')then
if(coll_x_l5(40)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(40)<='1';
end if;
if(coll_y_l5(40)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(40)<='1';
end if;
end if;
if(is_destroyed_l5(39)='0')then
if(coll_x_l5(39)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(39)<='1';
end if;
if(coll_y_l5(39)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(39)<='1';
end if;
end if;
if(is_destroyed_l5(38)='0')then
if(coll_x_l5(38)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(38)<='1';
end if;
if(coll_y_l5(38)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(38)<='1';
end if;
end if;
if(is_destroyed_l5(37)='0')then
if(coll_x_l5(37)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(37)<='1';
end if;
if(coll_y_l5(37)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(37)<='1';
end if;
end if;
if(is_destroyed_l5(36)='0')then
if(coll_x_l5(36)='1')then
ball_x_vel<=not ball_x_vel;
is_destroyed_l5(36)<='1';
end if;
if(coll_y_l5(36)='1')then
ball_y_vel<=not ball_y_vel;
is_destroyed_l5(36)<='1';
end if;
end if;
if(ball_y>480 and isalive/=0) then--respawn ball
ball_x<=rand_x;
ball_x_vel<=ball_x_vel_rand;
bat_x<=rand_x-25;
elsif(ball_x_vel='1' and notstarted='0' and pause='0' and stopball='0') then
ball_x <= ball_x + 3;--move ball right
elsif(ball_x_vel='0' and notstarted='0' and pause='0' and stopball='0') then
ball_x <= ball_x - 3;--move ball left
else
null;
end if;
if(ball_y>480 and isalive/=0) then--respawn ball and decrement lives
ball_y<=450;
ball_y_vel<='0';
bat_y<=460;
isalive<=isalive-1;
elsif(ball_y_vel='1' and notstarted='0' and pause='0' and stopball='0') then
ball_y <= ball_y + 1;--move ball down
elsif(ball_y_vel='0' and notstarted='0' and pause='0' and stopball='0') then
ball_y <= ball_y - 1;--move ball up
else
null;
end if;
if(r_shift='0' and bat_x<590 and pause='0' and stopball='0' and ball_y<470) then
bat_x<=bat_x+3;--move bat right
elsif(l_shift='0' and bat_x>3 and pause='0' and stopball='0' and ball_y<470) then
bat_x<=bat_x-3;--move bat left
else
null;
end if;
end if;
end if;
if(hpos>7 and hpos<104) then
hsync<='0'; --generate the horizontal sync
else
hsync<='1';
end if;
if(vpos>2 and vpos<5) then
vsync<='0'; --generate vertical sync
else
vsync<='1';
end if;
end if;
end process;
end sync_arch; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:02:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0_1/system_ov7670_vga_1_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_1_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_1_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_1_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal p_0_in0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => pclk,
CE => '1',
D => p_0_in0,
Q => cycle,
R => '0'
);
\rgb[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => cycle,
O => p_0_in0
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(0),
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(2),
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(3),
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(4),
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(5),
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(6),
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(7),
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(1),
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(2),
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(3),
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(4),
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(5),
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(6),
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => cycle,
D => data(7),
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(0),
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => pclk,
CE => p_0_in0,
D => data(1),
Q => rgb(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_1_0 is
port (
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_1_0 : entity is "system_ov7670_vga_1_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_1_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_1_0;
architecture STRUCTURE of system_ov7670_vga_1_0 is
begin
U0: entity work.system_ov7670_vga_1_0_ov7670_vga
port map (
data(7 downto 0) => data(7 downto 0),
pclk => pclk,
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
--
-- Interrupt controller for ZPUINO
--
-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
entity zpuino_intr is
generic (
INTERRUPT_LINES: integer := 16 -- MAX 32 lines
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
poppc_inst:in std_logic;
cache_flush: out std_logic;
memory_enable: out std_logic;
intr_in: in std_logic_vector(INTERRUPT_LINES-1 downto 0); -- edge interrupts
intr_cfglvl: in std_logic_vector(INTERRUPT_LINES-1 downto 0) -- user-configurable interrupt level
);
end entity zpuino_intr;
architecture behave of zpuino_intr is
signal mask_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_line: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal ien_q: std_logic;
signal iready_q: std_logic;
signal interrupt_active: std_logic;
signal masked_ivecs: std_logic_vector(31 downto 0); -- Max interrupt lines here, for priority encoder
signal intr_detected_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_in_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_level_q: std_logic_vector(INTERRUPT_LINES-1 downto 0);
signal intr_served_q: std_logic_vector(INTERRUPT_LINES-1 downto 0); -- Interrupt being served
signal memory_enable_q: std_logic;
begin
-- Edge detector
process(wb_clk_i)
variable level: std_logic;
variable not_level: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
else
for i in 0 to INTERRUPT_LINES-1 loop
if ien_q='1' and poppc_inst='1' and iready_q='0' then -- Exiting interrupt
if intr_served_q(i)='1' then
intr_detected_q(i) <= '0';
end if;
else
level := intr_level_q(i);
not_level := not intr_level_q(i);
if ( intr_in(i) = not_level and intr_in_q(i)=level) then -- edge detection
intr_detected_q(i) <= '1';
end if;
end if;
end loop;
intr_in_q <= intr_in;
end if;
end if;
end process;
masked_ivecs(INTERRUPT_LINES-1 downto 0) <= intr_detected_q and mask_q;
masked_ivecs(31 downto INTERRUPT_LINES) <= (others => '0');
-- Priority
intr_line <= "00000000000000000000000000000001" when masked_ivecs(0)='1' else
"00000000000000000000000000000010" when masked_ivecs(1)='1' else
"00000000000000000000000000000100" when masked_ivecs(2)='1' else
"00000000000000000000000000001000" when masked_ivecs(3)='1' else
"00000000000000000000000000010000" when masked_ivecs(4)='1' else
"00000000000000000000000000100000" when masked_ivecs(5)='1' else
"00000000000000000000000001000000" when masked_ivecs(6)='1' else
"00000000000000000000000010000000" when masked_ivecs(7)='1' else
"00000000000000000000000100000000" when masked_ivecs(8)='1' else
"00000000000000000000001000000000" when masked_ivecs(9)='1' else
"00000000000000000000010000000000" when masked_ivecs(10)='1' else
"00000000000000000000100000000000" when masked_ivecs(11)='1' else
"00000000000000000001000000000000" when masked_ivecs(12)='1' else
"00000000000000000010000000000000" when masked_ivecs(13)='1' else
"00000000000000000100000000000000" when masked_ivecs(14)='1' else
"00000000000000001000000000000000" when masked_ivecs(15)='1' else
"00000000000000010000000000000000" when masked_ivecs(16)='1' else
"00000000000000100000000000000000" when masked_ivecs(17)='1' else
"00000000000001000000000000000000" when masked_ivecs(18)='1' else
"00000000000010000000000000000000" when masked_ivecs(19)='1' else
"00000000000100000000000000000000" when masked_ivecs(20)='1' else
"00000000001000000000000000000000" when masked_ivecs(21)='1' else
"00000000010000000000000000000000" when masked_ivecs(22)='1' else
"00000000100000000000000000000000" when masked_ivecs(23)='1' else
"00000001000000000000000000000000" when masked_ivecs(24)='1' else
"00000010000000000000000000000000" when masked_ivecs(25)='1' else
"00000100000000000000000000000000" when masked_ivecs(26)='1' else
"00001000000000000000000000000000" when masked_ivecs(27)='1' else
"00010000000000000000000000000000" when masked_ivecs(28)='1' else
"00100000000000000000000000000000" when masked_ivecs(29)='1' else
"01000000000000000000000000000000" when masked_ivecs(30)='1' else
"10000000000000000000000000000000" when masked_ivecs(31)='1' else
"XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
wb_ack_o <= wb_stb_i and wb_cyc_i;
-- Select
interrupt_active<='1' when masked_ivecs(0)='1' or
masked_ivecs(1)='1' or
masked_ivecs(2)='1' or
masked_ivecs(3)='1' or
masked_ivecs(4)='1' or
masked_ivecs(5)='1' or
masked_ivecs(6)='1' or
masked_ivecs(7)='1' or
masked_ivecs(8)='1' or
masked_ivecs(9)='1' or
masked_ivecs(10)='1' or
masked_ivecs(11)='1' or
masked_ivecs(12)='1' or
masked_ivecs(13)='1' or
masked_ivecs(14)='1' or
masked_ivecs(15)='1' or
masked_ivecs(16)='1' or
masked_ivecs(17)='1' or
masked_ivecs(18)='1' or
masked_ivecs(19)='1' or
masked_ivecs(20)='1' or
masked_ivecs(21)='1' or
masked_ivecs(22)='1' or
masked_ivecs(23)='1' or
masked_ivecs(24)='1' or
masked_ivecs(25)='1' or
masked_ivecs(26)='1' or
masked_ivecs(27)='1' or
masked_ivecs(28)='1' or
masked_ivecs(29)='1' or
masked_ivecs(30)='1' or
masked_ivecs(31)='1'
else '0';
process(wb_adr_i,mask_q,ien_q,intr_served_q,intr_cfglvl,intr_level_q)
begin
wb_dat_o <= (others => Undefined);
case wb_adr_i(3 downto 2) is
when "00" =>
--wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
wb_dat_o(0) <= ien_q;
when "01" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= mask_q;
when "10" =>
wb_dat_o(INTERRUPT_LINES-1 downto 0) <= intr_served_q;
when "11" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
wb_dat_o(i) <= intr_level_q(i);
end if;
end loop;
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
process(wb_clk_i,wb_rst_i)
variable do_interrupt: std_logic;
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
mask_q <= (others => '0'); -- Start with all interrupts masked out
ien_q <= '0';
iready_q <= '1';
wb_inta_o <= '0';
intr_level_q<=(others =>'0');
--intr_q <= (others =>'0');
memory_enable<='1'; -- '1' to boot from internal bootloader
cache_flush<='0';
else
cache_flush<='0';
if wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' then
case wb_adr_i(4 downto 2) is
when "000" =>
ien_q <= wb_dat_i(0); -- Interrupt enable
wb_inta_o <= '0';
when "001" =>
mask_q <= wb_dat_i(INTERRUPT_LINES-1 downto 0);
when "011" =>
for i in 0 to INTERRUPT_LINES-1 loop
if intr_cfglvl(i)='1' then
intr_level_q(i) <= wb_dat_i(i);
end if;
end loop;
when "100" =>
memory_enable <= wb_dat_i(0);
cache_flush <= wb_dat_i(1);
when others =>
end case;
end if;
do_interrupt := '0';
if interrupt_active='1' then
if ien_q='1' and iready_q='1' then
do_interrupt := '1';
end if;
end if;
if do_interrupt='1' then
intr_served_q <= intr_line(INTERRUPT_LINES-1 downto 0);
ien_q <= '0';
wb_inta_o<='1';
iready_q <= '0';
else
if ien_q='1' and poppc_inst='1' then
iready_q<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
-------------------------------------------------------------------------------
-- axi_bram_ctrl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_wrapper.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller IP core.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v3_0)
-- |
-- |--axi_bram_ctrl_top.vhd
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_top;
use work.axi_bram_ctrl_funcs.all;
--use work.coregen_comp_defs.all;
library blk_mem_gen_v8_1;
use blk_mem_gen_v8_1.blk_mem_gen_v8_1;
------------------------------------------------------------------------------
entity axi_bram_ctrl is
generic (
C_BRAM_INST_MODE : string := "EXTERNAL"; -- external ; internal
--determines whether the bmg is external or internal to axi bram ctrl wrapper
C_MEMORY_DEPTH : integer := 4096;
--Memory depth specified by the user
C_BRAM_ADDR_WIDTH : integer := 12;
-- Width of AXI address bus (in bits)
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
C_FAMILY : string := "virtex7";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_TYPE : integer := 1;
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE : integer := 1
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
ecc_interrupt : out std_logic := '0';
ecc_ue : out std_logic := '0';
-- axi write address channel Signals (AW)
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- axi write data channel Signals (W)
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- axi write data response Channel Signals (B)
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- axi read address channel Signals (AR)
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- axi read data channel Signals (R)
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- axi-lite ecc register Interface Signals
-- axi-lite clock and Reset
-- note: axi-lite control IF and AXI IF share the same clock.
-- s_axi_ctrl_aclk : in std_logic;
-- s_axi_ctrl_aresetn : in std_logic;
-- axi-lite write address Channel Signals (AW)
s_axi_ctrl_awvalid : in std_logic;
s_axi_ctrl_awready : out std_logic;
s_axi_ctrl_awaddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- axi-lite write data Channel Signals (W)
s_axi_ctrl_wdata : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_wvalid : in std_logic;
s_axi_ctrl_wready : out std_logic;
-- axi-lite write data Response Channel Signals (B)
s_axi_ctrl_bresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_bvalid : out std_logic;
s_axi_ctrl_bready : in std_logic;
-- axi-lite read address Channel Signals (AR)
s_axi_ctrl_araddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_arvalid : in std_logic;
s_axi_ctrl_arready : out std_logic;
-- axi-lite read data Channel Signals (R)
s_axi_ctrl_rdata : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_rresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_rvalid : out std_logic;
s_axi_ctrl_rready : in std_logic;
-- bram interface signals (Port A)
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_a : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_a : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_a : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- bram interface signals (Port B)
bram_rst_b : out std_logic;
bram_clk_b : out std_logic;
bram_en_b : out std_logic;
bram_we_b : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_b : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_b : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_b : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity axi_bram_ctrl;
-------------------------------------------------------------------------------
architecture implementation of axi_bram_ctrl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (data_value : integer) RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Only instantiate logic based on C_S_AXI_PROTOCOL.
-- Determine external ECC width.
-- Use function defined in axi_bram_ctrl_funcs package.
-- Set internal parameters for ECC register enabling when C_ECC = 1
-- Catastrophic error indicated with ECC_UE & Interrupt flags.
-- Counter only sized when C_ECC = 1.
-- Selects CE counter width/threshold to assert ECC_Interrupt
-- Hard coded at 8-bits to capture and count up to 256 correctable errors.
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
constant GND : std_logic := '0';
constant VCC : std_logic := '1';
constant ZERO1 : std_logic_vector(0 downto 0) := (others => '0');
constant ZERO2 : std_logic_vector(1 downto 0) := (others => '0');
constant ZERO3 : std_logic_vector(2 downto 0) := (others => '0');
constant ZERO4 : std_logic_vector(3 downto 0) := (others => '0');
constant ZERO8 : std_logic_vector(7 downto 0) := (others => '0');
constant WSTRB_ZERO : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
constant ZERO16 : std_logic_vector(15 downto 0) := (others => '0');
constant ZERO32 : std_logic_vector(31 downto 0) := (others => '0');
constant ZERO64 : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
CONSTANT MEM_TYPE : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,2);
CONSTANT BWE_B : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,1);
CONSTANT BMG_ADDR_WIDTH : INTEGER := log2roundup(C_MEMORY_DEPTH) + log2roundup(C_S_AXI_DATA_WIDTH/8) ;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal clka_bram_clka_i : std_logic := '0';
signal rsta_bram_rsta_i : std_logic := '0';
signal ena_bram_ena_i : std_logic := '0';
signal REGCEA : std_logic := '0';
signal wea_bram_wea_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addra_bram_addra_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dina_bram_dina_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal douta_bram_douta_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
signal clkb_bram_clkb_i : std_logic := '0';
signal rstb_bram_rstb_i : std_logic := '0';
signal enb_bram_enb_i : std_logic := '0';
signal REGCEB : std_logic := '0';
signal web_bram_web_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addrb_bram_addrb_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dinb_bram_dinb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal doutb_bram_doutb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-----------------------------------------------------------------------
-- Architecture Body
-----------------------------------------------------------------------
begin
gint_inst: IF (C_BRAM_INST_MODE = "INTERNAL" ) GENERATE
constant c_addrb_width : INTEGER := log2roundup(C_MEMORY_DEPTH);
signal s_axi_rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal s_axi_dbiterr_bmg_int : STD_LOGIC;
signal s_axi_sbiterr_bmg_int : STD_LOGIC;
signal s_axi_rvalid_bmg_int : STD_LOGIC;
signal s_axi_rlast_bmg_int : STD_LOGIC;
signal s_axi_rresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_rdata_bmg_int : STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
signal s_axi_rid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s_axi_arready_bmg_int : STD_LOGIC;
signal s_axi_bvalid_bmg_int : STD_LOGIC;
signal s_axi_bresp_bmg_int : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal s_axi_bid_bmg_int : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s_axi_wready_bmg_int : STD_LOGIC;
signal s_axi_awready_bmg_int : STD_LOGIC;
signal rdaddrecc_bmg_int : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0);
signal dbiterr_bmg_int : STD_LOGIC;
signal sbiterr_bmg_int : STD_LOGIC;
begin
bmgv81_inst : entity blk_mem_gen_v8_1.blk_mem_gen_v8_1
GENERIC MAP(
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_FAMILY,
---- C_ELABORATION_DIR => "NULL" ,
C_INTERFACE_TYPE => 0 ,
--General Memory Parameters:
----- C_ENABLE_32BIT_ADDRESS => 0 ,
C_MEM_TYPE => MEM_TYPE ,
C_BYTE_SIZE => 8 ,
C_ALGORITHM => 1 ,
C_PRIM_TYPE => 1 ,
--Memory Initialization Parameters:
C_LOAD_INIT_FILE => 0 ,
C_INIT_FILE_NAME => "no_coe_file_loaded" ,
C_USE_DEFAULT_DATA => 0 ,
C_DEFAULT_DATA => "NULL" ,
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA => 0 ,
--Enable Parameters:
C_HAS_ENA => 1 ,
C_HAS_REGCEA => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEA => 1 ,
C_WEA_WIDTH => (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_A => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_A => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_A => C_MEMORY_DEPTH ,
C_READ_DEPTH_A => C_MEMORY_DEPTH ,
C_ADDRA_WIDTH => log2roundup(C_MEMORY_DEPTH) ,
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB => 0 ,
--Enable Parameters:
C_HAS_ENB => 1 ,
C_HAS_REGCEB => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEB => BWE_B ,
C_WEB_WIDTH => (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_B => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_B => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_B => C_MEMORY_DEPTH ,
C_READ_DEPTH_B => C_MEMORY_DEPTH ,
C_ADDRB_WIDTH => log2roundup(C_MEMORY_DEPTH) ,
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A => 0 ,
C_HAS_MEM_OUTPUT_REGS_B => 0 ,
C_HAS_MUX_OUTPUT_REGS_A => 0 ,
C_HAS_MUX_OUTPUT_REGS_B => 0 ,
C_MUX_PIPELINE_STAGES => 0 ,
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B=> 0 ,
--ECC Parameters
C_USE_ECC => 0 ,
C_USE_SOFTECC => 0 ,
C_HAS_INJECTERR => 0 ,
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK => "NONE" ,
C_COMMON_CLK => 1 ,
C_DISABLE_WARN_BHV_COLL => 1 ,
C_DISABLE_WARN_BHV_RANGE => 1
)
PORT MAP(
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
clka => clka_bram_clka_i ,
rsta => rsta_bram_rsta_i ,
ena => ena_bram_ena_i ,
regcea => GND ,
wea => wea_bram_wea_i ,
addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addra => addra_bram_addra_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dina => dina_bram_dina_i ,
douta => douta_bram_douta_i ,
--port b:
clkb => clkb_bram_clkb_i ,
rstb => rstb_bram_rstb_i ,
enb => enb_bram_enb_i ,
regceb => GND ,
web => web_bram_web_i ,
addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addrb => addrb_bram_addrb_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dinb => dinb_bram_dinb_i ,
doutb => doutb_bram_doutb_i ,
--ecc:
injectsbiterr => GND ,
injectdbiterr => GND ,
sbiterr => sbiterr_bmg_int,
dbiterr => dbiterr_bmg_int,
rdaddrecc => rdaddrecc_bmg_int,
-- axi bmg input and output Port Declarations
-- axi global signals
s_aclk => GND ,
s_aresetn => GND ,
-- axi full/lite slave write (write side)
s_axi_awid => ZERO4 ,
s_axi_awaddr => ZERO32 ,
s_axi_awlen => ZERO8 ,
s_axi_awsize => ZERO3 ,
s_axi_awburst => ZERO2 ,
s_axi_awvalid => GND ,
s_axi_awready => s_axi_awready_bmg_int,
s_axi_wdata => ZERO64 ,
s_axi_wstrb => WSTRB_ZERO,
s_axi_wlast => GND ,
s_axi_wvalid => GND ,
s_axi_wready => s_axi_wready_bmg_int,
s_axi_bid => s_axi_bid_bmg_int,
s_axi_bresp => s_axi_bresp_bmg_int,
s_axi_bvalid => s_axi_bvalid_bmg_int,
s_axi_bready => GND ,
-- axi full/lite slave read (Write side)
s_axi_arid => ZERO4,
s_axi_araddr => "00000000000000000000000000000000",
s_axi_arlen => "00000000",
s_axi_arsize => "000",
s_axi_arburst => "00",
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready_bmg_int,
s_axi_rid => s_axi_rid_bmg_int,
s_axi_rdata => s_axi_rdata_bmg_int,
s_axi_rresp => s_axi_rresp_bmg_int,
s_axi_rlast => s_axi_rlast_bmg_int,
s_axi_rvalid => s_axi_rvalid_bmg_int,
s_axi_rready => GND ,
-- axi full/lite sideband Signals
s_axi_injectsbiterr => GND ,
s_axi_injectdbiterr => GND ,
s_axi_sbiterr => s_axi_sbiterr_bmg_int,
s_axi_dbiterr => s_axi_dbiterr_bmg_int,
s_axi_rdaddrecc => s_axi_rdaddrecc_bmg_int
);
abcv3_0_int_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_ECC_TYPE => C_ECC_TYPE ,
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID => S_AXI_AWID ,
S_AXI_AWADDR => S_AXI_AWADDR ,
S_AXI_AWLEN => S_AXI_AWLEN ,
S_AXI_AWSIZE => S_AXI_AWSIZE ,
S_AXI_AWBURST => S_AXI_AWBURST ,
S_AXI_AWLOCK => S_AXI_AWLOCK ,
S_AXI_AWCACHE => S_AXI_AWCACHE ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID ,
S_AXI_AWREADY => S_AXI_AWREADY ,
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WLAST => S_AXI_WLAST ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID => S_AXI_BID ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID => S_AXI_ARID ,
S_AXI_ARADDR => S_AXI_ARADDR ,
S_AXI_ARLEN => S_AXI_ARLEN ,
S_AXI_ARSIZE => S_AXI_ARSIZE ,
S_AXI_ARBURST => S_AXI_ARBURST ,
S_AXI_ARLOCK => S_AXI_ARLOCK ,
S_AXI_ARCACHE => S_AXI_ARCACHE ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID ,
S_AXI_ARREADY => S_AXI_ARREADY ,
-- AXI Read Data Channel Signals (R)
S_AXI_RID => S_AXI_RID ,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RLAST => S_AXI_RLAST ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY ,
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
-- BRAM Interface Signals (Port A)
BRAM_Rst_A => rsta_bram_rsta_i ,
BRAM_Clk_A => clka_bram_clka_i ,
BRAM_En_A => ena_bram_ena_i ,
BRAM_WE_A => wea_bram_wea_i ,
BRAM_Addr_A => addra_bram_addra_i,
BRAM_WrData_A => dina_bram_dina_i ,
BRAM_RdData_A => douta_bram_douta_i ,
-- BRAM Interface Signals (Port B)
BRAM_Rst_B => rstb_bram_rstb_i ,
BRAM_Clk_B => clkb_bram_clkb_i ,
BRAM_En_B => enb_bram_enb_i ,
BRAM_WE_B => web_bram_web_i ,
BRAM_Addr_B => addrb_bram_addrb_i ,
BRAM_WrData_B => dinb_bram_dinb_i ,
BRAM_RdData_B => doutb_bram_doutb_i
);
-- The following signals are driven 0's to remove the synthesis warnings
bram_rst_a <= '0';
bram_clk_a <= '0';
bram_en_a <= '0';
bram_we_a <= (others => '0');
bram_addr_a <= (others => '0');
bram_wrdata_a <= (others => '0');
bram_rst_b <= '0';
bram_clk_b <= '0';
bram_en_b <= '0';
bram_we_b <= (others => '0');
bram_addr_b <= (others => '0');
bram_wrdata_b <= (others => '0');
END GENERATE gint_inst; -- End of internal bram instance
gext_inst: IF (C_BRAM_INST_MODE = "EXTERNAL" ) GENERATE
abcv3_0_ext_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_ECC_TYPE => C_ECC_TYPE ,
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk => s_axi_aclk ,
s_axi_aresetn => s_axi_aresetn ,
ecc_interrupt => ecc_interrupt ,
ecc_ue => ecc_ue ,
-- axi write address channel signals (aw)
s_axi_awid => s_axi_awid ,
s_axi_awaddr => s_axi_awaddr ,
s_axi_awlen => s_axi_awlen ,
s_axi_awsize => s_axi_awsize ,
s_axi_awburst => s_axi_awburst ,
s_axi_awlock => s_axi_awlock ,
s_axi_awcache => s_axi_awcache ,
s_axi_awprot => s_axi_awprot ,
s_axi_awvalid => s_axi_awvalid ,
s_axi_awready => s_axi_awready ,
-- axi write data channel signals (w)
s_axi_wdata => s_axi_wdata ,
s_axi_wstrb => s_axi_wstrb ,
s_axi_wlast => s_axi_wlast ,
s_axi_wvalid => s_axi_wvalid ,
s_axi_wready => s_axi_wready ,
-- axi write data response channel signals (b)
s_axi_bid => s_axi_bid ,
s_axi_bresp => s_axi_bresp ,
s_axi_bvalid => s_axi_bvalid ,
s_axi_bready => s_axi_bready ,
-- axi read address channel signals (ar)
s_axi_arid => s_axi_arid ,
s_axi_araddr => s_axi_araddr ,
s_axi_arlen => s_axi_arlen ,
s_axi_arsize => s_axi_arsize ,
s_axi_arburst => s_axi_arburst ,
s_axi_arlock => s_axi_arlock ,
s_axi_arcache => s_axi_arcache ,
s_axi_arprot => s_axi_arprot ,
s_axi_arvalid => s_axi_arvalid ,
s_axi_arready => s_axi_arready ,
-- axi read data channel signals (r)
s_axi_rid => s_axi_rid ,
s_axi_rdata => s_axi_rdata ,
s_axi_rresp => s_axi_rresp ,
s_axi_rlast => s_axi_rlast ,
s_axi_rvalid => s_axi_rvalid ,
s_axi_rready => s_axi_rready ,
-- axi-lite ecc register interface signals
-- axi-lite write address channel signals (aw)
s_axi_ctrl_awvalid => s_axi_ctrl_awvalid ,
s_axi_ctrl_awready => s_axi_ctrl_awready ,
s_axi_ctrl_awaddr => s_axi_ctrl_awaddr ,
-- axi-lite write data channel signals (w)
s_axi_ctrl_wdata => s_axi_ctrl_wdata ,
s_axi_ctrl_wvalid => s_axi_ctrl_wvalid ,
s_axi_ctrl_wready => s_axi_ctrl_wready ,
-- axi-lite write data response channel signals (b)
s_axi_ctrl_bresp => s_axi_ctrl_bresp ,
s_axi_ctrl_bvalid => s_axi_ctrl_bvalid ,
s_axi_ctrl_bready => s_axi_ctrl_bready ,
-- axi-lite read address channel signals (ar)
s_axi_ctrl_araddr => s_axi_ctrl_araddr ,
s_axi_ctrl_arvalid => s_axi_ctrl_arvalid ,
s_axi_ctrl_arready => s_axi_ctrl_arready ,
-- axi-lite read data channel signals (r)
s_axi_ctrl_rdata => s_axi_ctrl_rdata ,
s_axi_ctrl_rresp => s_axi_ctrl_rresp ,
s_axi_ctrl_rvalid => s_axi_ctrl_rvalid ,
s_axi_ctrl_rready => s_axi_ctrl_rready ,
-- bram interface signals (port a)
bram_rst_a => bram_rst_a ,
bram_clk_a => bram_clk_a ,
bram_en_a => bram_en_a ,
bram_we_a => bram_we_a ,
bram_addr_a => bram_addr_a ,
bram_wrdata_a => bram_wrdata_a ,
bram_rddata_a => bram_rddata_a ,
-- bram interface signals (port b)
bram_rst_b => bram_rst_b ,
bram_clk_b => bram_clk_b ,
bram_en_b => bram_en_b ,
bram_we_b => bram_we_b ,
bram_addr_b => bram_addr_b ,
bram_wrdata_b => bram_wrdata_b ,
bram_rddata_b => bram_rddata_b
);
END GENERATE gext_inst; -- End of internal bram instance
end architecture implementation;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Gray_Binarization_example is
end entity;
architecture rtl of tb_Gray_Binarization_example is
component tb_Gray_Binarization
end component;
begin
tb_Gray_Binarization_instance :
component tb_Gray_Binarization
port map();
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Gray_Binarization_example is
end entity;
architecture rtl of tb_Gray_Binarization_example is
component tb_Gray_Binarization
end component;
begin
tb_Gray_Binarization_instance :
component tb_Gray_Binarization
port map();
end architecture rtl;
|
-- update.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity update is
port (
busy : out std_logic; -- busy.busy
clock : in std_logic := '0'; -- clock.clk
data_out : out std_logic_vector(28 downto 0); -- data_out.data_out
param : in std_logic_vector(2 downto 0) := (others => '0'); -- param.param
read_param : in std_logic := '0'; -- read_param.read_param
read_source : in std_logic_vector(1 downto 0) := (others => '0'); -- read_source.read_source
reconfig : in std_logic := '0'; -- reconfig.reconfig
reset : in std_logic := '0'; -- reset.reset
reset_timer : in std_logic := '0' -- reset_timer.reset_timer
);
end entity update;
architecture rtl of update is
component update_remote_update_0 is
port (
busy : out std_logic; -- busy
data_out : out std_logic_vector(28 downto 0); -- data_out
param : in std_logic_vector(2 downto 0) := (others => 'X'); -- param
read_param : in std_logic := 'X'; -- read_param
reconfig : in std_logic := 'X'; -- reconfig
reset_timer : in std_logic := 'X'; -- reset_timer
read_source : in std_logic_vector(1 downto 0) := (others => 'X'); -- read_source
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X' -- reset
);
end component update_remote_update_0;
begin
remote_update_0 : component update_remote_update_0
port map (
busy => busy, -- busy.busy
data_out => data_out, -- data_out.data_out
param => param, -- param.param
read_param => read_param, -- read_param.read_param
reconfig => reconfig, -- reconfig.reconfig
reset_timer => reset_timer, -- reset_timer.reset_timer
read_source => read_source, -- read_source.read_source
clock => clock, -- clock.clk
reset => reset -- reset.reset
);
end architecture rtl; -- of update
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity match_db_contact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
db_item_V : IN STD_LOGIC_VECTOR (511 downto 0);
contacts_V_address0 : OUT STD_LOGIC_VECTOR (6 downto 0);
contacts_V_ce0 : OUT STD_LOGIC;
contacts_V_q0 : IN STD_LOGIC_VECTOR (511 downto 0);
contacts_V_address1 : OUT STD_LOGIC_VECTOR (6 downto 0);
contacts_V_ce1 : OUT STD_LOGIC;
contacts_V_q1 : IN STD_LOGIC_VECTOR (511 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of match_db_contact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage40 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage41 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage42 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage43 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage44 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage45 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage46 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage47 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage48 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage49 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage50 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage51 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage52 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage53 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage54 : STD_LOGIC_VECTOR (63 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage55 : STD_LOGIC_VECTOR (63 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage56 : STD_LOGIC_VECTOR (63 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage57 : STD_LOGIC_VECTOR (63 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage58 : STD_LOGIC_VECTOR (63 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage59 : STD_LOGIC_VECTOR (63 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage60 : STD_LOGIC_VECTOR (63 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage61 : STD_LOGIC_VECTOR (63 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage62 : STD_LOGIC_VECTOR (63 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage63 : STD_LOGIC_VECTOR (63 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv7_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_const_lv7_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_const_lv7_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_const_lv7_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_const_lv7_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_const_lv7_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_const_lv7_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_const_lv7_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_const_lv7_A : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_const_lv7_B : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_const_lv7_C : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_const_lv7_D : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_const_lv7_E : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_const_lv7_F : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_const_lv7_10 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_const_lv7_11 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_const_lv7_12 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_const_lv7_13 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_const_lv7_14 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_const_lv7_15 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_const_lv7_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_const_lv7_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_const_lv7_18 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_const_lv7_19 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_const_lv7_1A : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_const_lv7_1B : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_const_lv7_1C : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_const_lv7_1D : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_const_lv7_1E : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_const_lv7_1F : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_const_lv7_20 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_const_lv7_21 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_const_lv7_22 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_const_lv7_23 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_const_lv7_24 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_const_lv7_25 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_const_lv7_26 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_const_lv7_27 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_const_lv7_28 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_const_lv7_29 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_const_lv7_2A : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_const_lv7_2B : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_const_lv7_2C : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_const_lv7_2D : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_const_lv7_2E : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_const_lv7_2F : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_const_lv7_30 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_const_lv7_31 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv7_33 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_const_lv7_34 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_const_lv7_35 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_const_lv7_36 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_const_lv7_37 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_const_lv7_38 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_const_lv7_39 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_const_lv7_3A : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_const_lv7_3B : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_const_lv7_3C : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_const_lv7_3D : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_const_lv7_3E : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_const_lv7_3F : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_41 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_const_lv7_42 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_const_lv7_43 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_const_lv7_44 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_const_lv7_45 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_const_lv7_46 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_const_lv7_47 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_const_lv7_48 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_const_lv7_49 : STD_LOGIC_VECTOR (6 downto 0) := "1001001";
constant ap_const_lv7_4A : STD_LOGIC_VECTOR (6 downto 0) := "1001010";
constant ap_const_lv7_4B : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_const_lv7_4C : STD_LOGIC_VECTOR (6 downto 0) := "1001100";
constant ap_const_lv7_4D : STD_LOGIC_VECTOR (6 downto 0) := "1001101";
constant ap_const_lv7_4E : STD_LOGIC_VECTOR (6 downto 0) := "1001110";
constant ap_const_lv7_4F : STD_LOGIC_VECTOR (6 downto 0) := "1001111";
constant ap_const_lv7_50 : STD_LOGIC_VECTOR (6 downto 0) := "1010000";
constant ap_const_lv7_51 : STD_LOGIC_VECTOR (6 downto 0) := "1010001";
constant ap_const_lv7_52 : STD_LOGIC_VECTOR (6 downto 0) := "1010010";
constant ap_const_lv7_53 : STD_LOGIC_VECTOR (6 downto 0) := "1010011";
constant ap_const_lv7_54 : STD_LOGIC_VECTOR (6 downto 0) := "1010100";
constant ap_const_lv7_55 : STD_LOGIC_VECTOR (6 downto 0) := "1010101";
constant ap_const_lv7_56 : STD_LOGIC_VECTOR (6 downto 0) := "1010110";
constant ap_const_lv7_57 : STD_LOGIC_VECTOR (6 downto 0) := "1010111";
constant ap_const_lv7_58 : STD_LOGIC_VECTOR (6 downto 0) := "1011000";
constant ap_const_lv7_59 : STD_LOGIC_VECTOR (6 downto 0) := "1011001";
constant ap_const_lv7_5A : STD_LOGIC_VECTOR (6 downto 0) := "1011010";
constant ap_const_lv7_5B : STD_LOGIC_VECTOR (6 downto 0) := "1011011";
constant ap_const_lv7_5C : STD_LOGIC_VECTOR (6 downto 0) := "1011100";
constant ap_const_lv7_5D : STD_LOGIC_VECTOR (6 downto 0) := "1011101";
constant ap_const_lv7_5E : STD_LOGIC_VECTOR (6 downto 0) := "1011110";
constant ap_const_lv7_5F : STD_LOGIC_VECTOR (6 downto 0) := "1011111";
constant ap_const_lv7_60 : STD_LOGIC_VECTOR (6 downto 0) := "1100000";
constant ap_const_lv7_61 : STD_LOGIC_VECTOR (6 downto 0) := "1100001";
constant ap_const_lv7_62 : STD_LOGIC_VECTOR (6 downto 0) := "1100010";
constant ap_const_lv7_63 : STD_LOGIC_VECTOR (6 downto 0) := "1100011";
constant ap_const_lv7_64 : STD_LOGIC_VECTOR (6 downto 0) := "1100100";
constant ap_const_lv7_65 : STD_LOGIC_VECTOR (6 downto 0) := "1100101";
constant ap_const_lv7_66 : STD_LOGIC_VECTOR (6 downto 0) := "1100110";
constant ap_const_lv7_67 : STD_LOGIC_VECTOR (6 downto 0) := "1100111";
constant ap_const_lv7_68 : STD_LOGIC_VECTOR (6 downto 0) := "1101000";
constant ap_const_lv7_69 : STD_LOGIC_VECTOR (6 downto 0) := "1101001";
constant ap_const_lv7_6A : STD_LOGIC_VECTOR (6 downto 0) := "1101010";
constant ap_const_lv7_6B : STD_LOGIC_VECTOR (6 downto 0) := "1101011";
constant ap_const_lv7_6C : STD_LOGIC_VECTOR (6 downto 0) := "1101100";
constant ap_const_lv7_6D : STD_LOGIC_VECTOR (6 downto 0) := "1101101";
constant ap_const_lv7_6E : STD_LOGIC_VECTOR (6 downto 0) := "1101110";
constant ap_const_lv7_6F : STD_LOGIC_VECTOR (6 downto 0) := "1101111";
constant ap_const_lv7_70 : STD_LOGIC_VECTOR (6 downto 0) := "1110000";
constant ap_const_lv7_71 : STD_LOGIC_VECTOR (6 downto 0) := "1110001";
constant ap_const_lv7_72 : STD_LOGIC_VECTOR (6 downto 0) := "1110010";
constant ap_const_lv7_73 : STD_LOGIC_VECTOR (6 downto 0) := "1110011";
constant ap_const_lv7_74 : STD_LOGIC_VECTOR (6 downto 0) := "1110100";
constant ap_const_lv7_75 : STD_LOGIC_VECTOR (6 downto 0) := "1110101";
constant ap_const_lv7_76 : STD_LOGIC_VECTOR (6 downto 0) := "1110110";
constant ap_const_lv7_77 : STD_LOGIC_VECTOR (6 downto 0) := "1110111";
constant ap_const_lv7_78 : STD_LOGIC_VECTOR (6 downto 0) := "1111000";
constant ap_const_lv7_79 : STD_LOGIC_VECTOR (6 downto 0) := "1111001";
constant ap_const_lv7_7A : STD_LOGIC_VECTOR (6 downto 0) := "1111010";
constant ap_const_lv7_7B : STD_LOGIC_VECTOR (6 downto 0) := "1111011";
constant ap_const_lv7_7C : STD_LOGIC_VECTOR (6 downto 0) := "1111100";
constant ap_const_lv7_7D : STD_LOGIC_VECTOR (6 downto 0) := "1111101";
constant ap_const_lv7_7E : STD_LOGIC_VECTOR (6 downto 0) := "1111110";
constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_CS_fsm_pp0_stage63 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage63 : signal is "none";
signal ap_block_state64_pp0_stage63_iter0 : BOOLEAN;
signal ap_block_pp0_stage63_flag00011001 : BOOLEAN;
signal db_item_V_read_reg_1082 : STD_LOGIC_VECTOR (511 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state2_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal grp_fu_403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1088 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_1_reg_1093 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_reg_1098 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state3_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal tmp_1_4_reg_1103 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state4_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal tmp_1_5_reg_1108 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_reg_1113 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state5_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal tmp_1_8_reg_1118 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state6_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal tmp_1_9_reg_1123 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_fu_462_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_reg_1128 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state7_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal tmp_1_11_reg_1133 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state8_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal tmp_1_12_reg_1138 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_reg_1143 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state9_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal tmp_1_15_reg_1148 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state10_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal tmp_1_16_reg_1153 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_fu_504_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_reg_1158 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state11_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal tmp_1_19_reg_1163 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state12_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal tmp_1_20_reg_1168 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_fu_526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_reg_1173 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_state13_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal tmp_1_23_reg_1178 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
signal ap_block_state14_pp0_stage13_iter0 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011001 : BOOLEAN;
signal tmp_1_24_reg_1183 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_fu_541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_reg_1188 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
signal ap_block_state15_pp0_stage14_iter0 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011001 : BOOLEAN;
signal tmp_1_27_reg_1193 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none";
signal ap_block_state16_pp0_stage15_iter0 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011001 : BOOLEAN;
signal tmp_1_28_reg_1198 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_fu_568_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_reg_1203 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none";
signal ap_block_state17_pp0_stage16_iter0 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011001 : BOOLEAN;
signal tmp_1_31_reg_1208 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none";
signal ap_block_state18_pp0_stage17_iter0 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011001 : BOOLEAN;
signal tmp_1_32_reg_1213 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp35_fu_583_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp35_reg_1218 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none";
signal ap_block_state19_pp0_stage18_iter0 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011001 : BOOLEAN;
signal tmp_1_35_reg_1223 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none";
signal ap_block_state20_pp0_stage19_iter0 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011001 : BOOLEAN;
signal tmp_1_36_reg_1228 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp34_fu_605_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp34_reg_1233 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none";
signal ap_block_state21_pp0_stage20_iter0 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011001 : BOOLEAN;
signal tmp_1_39_reg_1238 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none";
signal ap_block_state22_pp0_stage21_iter0 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011001 : BOOLEAN;
signal tmp_1_40_reg_1243 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp42_fu_620_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp42_reg_1248 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none";
signal ap_block_state23_pp0_stage22_iter0 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011001 : BOOLEAN;
signal tmp_1_43_reg_1253 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none";
signal ap_block_state24_pp0_stage23_iter0 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011001 : BOOLEAN;
signal tmp_1_44_reg_1258 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp33_fu_647_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp33_reg_1263 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none";
signal ap_block_state25_pp0_stage24_iter0 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011001 : BOOLEAN;
signal tmp_1_47_reg_1268 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none";
signal ap_block_state26_pp0_stage25_iter0 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011001 : BOOLEAN;
signal tmp_1_48_reg_1273 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp50_fu_662_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp50_reg_1278 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none";
signal ap_block_state27_pp0_stage26_iter0 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011001 : BOOLEAN;
signal tmp_1_51_reg_1283 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none";
signal ap_block_state28_pp0_stage27_iter0 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011001 : BOOLEAN;
signal tmp_1_52_reg_1288 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp49_fu_684_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp49_reg_1293 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none";
signal ap_block_state29_pp0_stage28_iter0 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011001 : BOOLEAN;
signal tmp_1_55_reg_1298 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage29 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none";
signal ap_block_state30_pp0_stage29_iter0 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011001 : BOOLEAN;
signal tmp_1_56_reg_1303 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp57_fu_699_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp57_reg_1308 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none";
signal ap_block_state31_pp0_stage30_iter0 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011001 : BOOLEAN;
signal tmp_1_59_reg_1313 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none";
signal ap_block_state32_pp0_stage31_iter0 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011001 : BOOLEAN;
signal tmp_1_60_reg_1318 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_1323 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage32 : signal is "none";
signal ap_block_state33_pp0_stage32_iter0 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011001 : BOOLEAN;
signal tmp_1_63_reg_1328 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage33 : signal is "none";
signal ap_block_state34_pp0_stage33_iter0 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011001 : BOOLEAN;
signal tmp_1_64_reg_1333 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp67_fu_756_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp67_reg_1338 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage34 : signal is "none";
signal ap_block_state35_pp0_stage34_iter0 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011001 : BOOLEAN;
signal tmp_1_67_reg_1343 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none";
signal ap_block_state36_pp0_stage35_iter0 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011001 : BOOLEAN;
signal tmp_1_68_reg_1348 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp66_fu_778_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp66_reg_1353 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage36 : signal is "none";
signal ap_block_state37_pp0_stage36_iter0 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011001 : BOOLEAN;
signal tmp_1_71_reg_1358 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage37 : signal is "none";
signal ap_block_state38_pp0_stage37_iter0 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011001 : BOOLEAN;
signal tmp_1_72_reg_1363 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp74_fu_793_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp74_reg_1368 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage38 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage38 : signal is "none";
signal ap_block_state39_pp0_stage38_iter0 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011001 : BOOLEAN;
signal tmp_1_75_reg_1373 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage39 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none";
signal ap_block_state40_pp0_stage39_iter0 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011001 : BOOLEAN;
signal tmp_1_76_reg_1378 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp65_fu_820_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp65_reg_1383 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage40 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage40 : signal is "none";
signal ap_block_state41_pp0_stage40_iter0 : BOOLEAN;
signal ap_block_pp0_stage40_flag00011001 : BOOLEAN;
signal tmp_1_79_reg_1388 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage41 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage41 : signal is "none";
signal ap_block_state42_pp0_stage41_iter0 : BOOLEAN;
signal ap_block_pp0_stage41_flag00011001 : BOOLEAN;
signal tmp_1_80_reg_1393 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp82_fu_835_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp82_reg_1398 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage42 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage42 : signal is "none";
signal ap_block_state43_pp0_stage42_iter0 : BOOLEAN;
signal ap_block_pp0_stage42_flag00011001 : BOOLEAN;
signal tmp_1_83_reg_1403 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage43 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage43 : signal is "none";
signal ap_block_state44_pp0_stage43_iter0 : BOOLEAN;
signal ap_block_pp0_stage43_flag00011001 : BOOLEAN;
signal tmp_1_84_reg_1408 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp81_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp81_reg_1413 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage44 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage44 : signal is "none";
signal ap_block_state45_pp0_stage44_iter0 : BOOLEAN;
signal ap_block_pp0_stage44_flag00011001 : BOOLEAN;
signal tmp_1_87_reg_1418 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage45 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage45 : signal is "none";
signal ap_block_state46_pp0_stage45_iter0 : BOOLEAN;
signal ap_block_pp0_stage45_flag00011001 : BOOLEAN;
signal tmp_1_88_reg_1423 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp89_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp89_reg_1428 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage46 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage46 : signal is "none";
signal ap_block_state47_pp0_stage46_iter0 : BOOLEAN;
signal ap_block_pp0_stage46_flag00011001 : BOOLEAN;
signal tmp_1_91_reg_1433 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage47 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage47 : signal is "none";
signal ap_block_state48_pp0_stage47_iter0 : BOOLEAN;
signal ap_block_pp0_stage47_flag00011001 : BOOLEAN;
signal tmp_1_92_reg_1438 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp80_fu_899_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp80_reg_1443 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage48 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage48 : signal is "none";
signal ap_block_state49_pp0_stage48_iter0 : BOOLEAN;
signal ap_block_pp0_stage48_flag00011001 : BOOLEAN;
signal tmp_1_95_reg_1448 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage49 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage49 : signal is "none";
signal ap_block_state50_pp0_stage49_iter0 : BOOLEAN;
signal ap_block_pp0_stage49_flag00011001 : BOOLEAN;
signal tmp_1_96_reg_1453 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp98_fu_914_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp98_reg_1458 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage50 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage50 : signal is "none";
signal ap_block_state51_pp0_stage50_iter0 : BOOLEAN;
signal ap_block_pp0_stage50_flag00011001 : BOOLEAN;
signal tmp_1_99_reg_1463 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage51 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage51 : signal is "none";
signal ap_block_state52_pp0_stage51_iter0 : BOOLEAN;
signal ap_block_pp0_stage51_flag00011001 : BOOLEAN;
signal tmp_1_100_reg_1468 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp97_fu_936_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp97_reg_1473 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage52 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage52 : signal is "none";
signal ap_block_state53_pp0_stage52_iter0 : BOOLEAN;
signal ap_block_pp0_stage52_flag00011001 : BOOLEAN;
signal tmp_1_103_reg_1478 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage53 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage53 : signal is "none";
signal ap_block_state54_pp0_stage53_iter0 : BOOLEAN;
signal ap_block_pp0_stage53_flag00011001 : BOOLEAN;
signal tmp_1_104_reg_1483 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp105_fu_951_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp105_reg_1488 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage54 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage54 : signal is "none";
signal ap_block_state55_pp0_stage54_iter0 : BOOLEAN;
signal ap_block_pp0_stage54_flag00011001 : BOOLEAN;
signal tmp_1_107_reg_1493 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage55 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage55 : signal is "none";
signal ap_block_state56_pp0_stage55_iter0 : BOOLEAN;
signal ap_block_pp0_stage55_flag00011001 : BOOLEAN;
signal tmp_1_108_reg_1498 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp96_fu_978_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp96_reg_1503 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage56 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage56 : signal is "none";
signal ap_block_state57_pp0_stage56_iter0 : BOOLEAN;
signal ap_block_pp0_stage56_flag00011001 : BOOLEAN;
signal tmp_1_111_reg_1508 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage57 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage57 : signal is "none";
signal ap_block_state58_pp0_stage57_iter0 : BOOLEAN;
signal ap_block_pp0_stage57_flag00011001 : BOOLEAN;
signal tmp_1_112_reg_1513 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp113_fu_993_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp113_reg_1518 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage58 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage58 : signal is "none";
signal ap_block_state59_pp0_stage58_iter0 : BOOLEAN;
signal ap_block_pp0_stage58_flag00011001 : BOOLEAN;
signal tmp_1_115_reg_1523 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage59 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage59 : signal is "none";
signal ap_block_state60_pp0_stage59_iter0 : BOOLEAN;
signal ap_block_pp0_stage59_flag00011001 : BOOLEAN;
signal tmp_1_116_reg_1528 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp112_fu_1015_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp112_reg_1533 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage60 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage60 : signal is "none";
signal ap_block_state61_pp0_stage60_iter0 : BOOLEAN;
signal ap_block_pp0_stage60_flag00011001 : BOOLEAN;
signal tmp_1_119_reg_1538 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage61 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage61 : signal is "none";
signal ap_block_state62_pp0_stage61_iter0 : BOOLEAN;
signal ap_block_pp0_stage61_flag00011001 : BOOLEAN;
signal tmp_1_120_reg_1543 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp120_fu_1030_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp120_reg_1548 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage62 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage62 : signal is "none";
signal ap_block_state63_pp0_stage62_iter0 : BOOLEAN;
signal ap_block_pp0_stage62_flag00011001 : BOOLEAN;
signal tmp_1_123_reg_1553 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_124_reg_1558 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_enable_reg_pp0_iter0_reg : STD_LOGIC := '0';
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state65_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage63_flag00011011 : BOOLEAN;
signal ap_port_reg_db_item_V : STD_LOGIC_VECTOR (511 downto 0);
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage13_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage14_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage15_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage16_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage17_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage18_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage19_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage20_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage21_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage22_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage23_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage24_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage25_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage26_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage27_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage28_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage29_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage30_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage31_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage32_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage33_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage34_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage35_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage36_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage37_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage38_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage39_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage40_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage41_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage42_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage43_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage44_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage45_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage46_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage47_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage48_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage49_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage50_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage51_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage52_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage53_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage54_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage55_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage56_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage57_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage58_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage59_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage60_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage61_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage62_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage63_flag00000000 : BOOLEAN;
signal grp_fu_403_p1 : STD_LOGIC_VECTOR (511 downto 0);
signal grp_fu_409_p1 : STD_LOGIC_VECTOR (511 downto 0);
signal tmp6_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_415_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_fu_435_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp7_fu_441_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp13_fu_456_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_fu_452_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp16_fu_472_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_fu_468_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_fu_478_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp10_fu_484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp21_fu_498_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_fu_494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp24_fu_514_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_fu_510_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp22_fu_520_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp28_fu_535_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp27_fu_531_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp31_fu_551_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp30_fu_547_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp29_fu_557_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_fu_563_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp37_fu_577_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp36_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp40_fu_593_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp39_fu_589_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp38_fu_599_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp44_fu_614_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp43_fu_610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp47_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp46_fu_626_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp45_fu_636_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp41_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp52_fu_656_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp51_fu_652_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp55_fu_672_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp54_fu_668_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp53_fu_678_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp59_fu_693_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp58_fu_689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp62_fu_713_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp61_fu_709_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp60_fu_719_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp56_fu_725_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp48_fu_730_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp32_fu_735_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp1_fu_705_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp69_fu_750_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp68_fu_746_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp72_fu_766_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp71_fu_762_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp70_fu_772_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp76_fu_787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp75_fu_783_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp79_fu_803_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp78_fu_799_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp77_fu_809_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp73_fu_815_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp84_fu_829_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp83_fu_825_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp87_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp86_fu_841_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp85_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp91_fu_866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp90_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp94_fu_882_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp93_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp92_fu_888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp88_fu_894_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp100_fu_908_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp99_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp103_fu_924_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp102_fu_920_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp101_fu_930_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp107_fu_945_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp106_fu_941_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp110_fu_961_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp109_fu_957_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp108_fu_967_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp104_fu_973_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp115_fu_987_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp114_fu_983_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp118_fu_1003_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp117_fu_999_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp116_fu_1009_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp122_fu_1024_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp121_fu_1020_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp125_fu_1044_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp124_fu_1040_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp123_fu_1050_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp119_fu_1056_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp111_fu_1061_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp95_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp64_fu_1036_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp63_fu_1071_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (63 downto 0);
signal ap_idle_pp0_0to0 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_idle_pp0_1to1 : STD_LOGIC;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage40_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage41_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage42_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage43_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage44_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage45_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage46_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage47_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage48_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage49_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage50_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage51_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage52_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage53_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage54_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage55_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage56_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage57_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage58_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage59_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage60_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage61_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage62_flag00011011 : BOOLEAN;
signal ap_enable_pp0 : STD_LOGIC;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0_reg <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_port_reg_db_item_V <= db_item_V;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
db_item_V_read_reg_1082 <= ap_port_reg_db_item_V;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0))) then
tmp105_reg_1488 <= tmp105_fu_951_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0))) then
tmp112_reg_1533 <= tmp112_fu_1015_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0))) then
tmp113_reg_1518 <= tmp113_fu_993_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp11_reg_1128 <= tmp11_fu_462_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0))) then
tmp120_reg_1548 <= tmp120_fu_1030_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0))) then
tmp17_reg_1203 <= tmp17_fu_568_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
tmp18_reg_1173 <= tmp18_fu_526_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp19_reg_1158 <= tmp19_fu_504_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
tmp26_reg_1188 <= tmp26_fu_541_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp2_reg_1143 <= tmp2_fu_489_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0))) then
tmp33_reg_1263 <= tmp33_fu_647_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0))) then
tmp34_reg_1233 <= tmp34_fu_605_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0))) then
tmp35_reg_1218 <= tmp35_fu_583_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp3_reg_1113 <= tmp3_fu_447_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0))) then
tmp42_reg_1248 <= tmp42_fu_620_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0))) then
tmp49_reg_1293 <= tmp49_fu_684_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp4_reg_1098 <= tmp4_fu_425_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0))) then
tmp50_reg_1278 <= tmp50_fu_662_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0))) then
tmp57_reg_1308 <= tmp57_fu_699_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0))) then
tmp65_reg_1383 <= tmp65_fu_820_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0))) then
tmp66_reg_1353 <= tmp66_fu_778_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0))) then
tmp67_reg_1338 <= tmp67_fu_756_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0))) then
tmp74_reg_1368 <= tmp74_fu_793_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0))) then
tmp80_reg_1443 <= tmp80_fu_899_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0))) then
tmp81_reg_1413 <= tmp81_fu_857_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0))) then
tmp82_reg_1398 <= tmp82_fu_835_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0))) then
tmp89_reg_1428 <= tmp89_fu_872_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0))) then
tmp96_reg_1503 <= tmp96_fu_978_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0))) then
tmp97_reg_1473 <= tmp97_fu_936_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0))) then
tmp98_reg_1458 <= tmp98_fu_914_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0))) then
tmp_1_100_reg_1468 <= grp_fu_409_p2;
tmp_1_99_reg_1463 <= grp_fu_403_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0))) then
tmp_1_103_reg_1478 <= grp_fu_403_p2;
tmp_1_104_reg_1483 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0))) then
tmp_1_107_reg_1493 <= grp_fu_403_p2;
tmp_1_108_reg_1498 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0))) then
tmp_1_111_reg_1508 <= grp_fu_403_p2;
tmp_1_112_reg_1513 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0))) then
tmp_1_115_reg_1523 <= grp_fu_403_p2;
tmp_1_116_reg_1528 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0))) then
tmp_1_119_reg_1538 <= grp_fu_403_p2;
tmp_1_120_reg_1543 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_1_11_reg_1133 <= grp_fu_403_p2;
tmp_1_12_reg_1138 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
tmp_1_123_reg_1553 <= grp_fu_403_p2;
tmp_1_124_reg_1558 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_1_15_reg_1148 <= grp_fu_403_p2;
tmp_1_16_reg_1153 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_1_19_reg_1163 <= grp_fu_403_p2;
tmp_1_20_reg_1168 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_1_1_reg_1093 <= grp_fu_409_p2;
tmp_1_reg_1088 <= grp_fu_403_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
tmp_1_23_reg_1178 <= grp_fu_403_p2;
tmp_1_24_reg_1183 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
tmp_1_27_reg_1193 <= grp_fu_403_p2;
tmp_1_28_reg_1198 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0))) then
tmp_1_31_reg_1208 <= grp_fu_403_p2;
tmp_1_32_reg_1213 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0))) then
tmp_1_35_reg_1223 <= grp_fu_403_p2;
tmp_1_36_reg_1228 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0))) then
tmp_1_39_reg_1238 <= grp_fu_403_p2;
tmp_1_40_reg_1243 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0))) then
tmp_1_43_reg_1253 <= grp_fu_403_p2;
tmp_1_44_reg_1258 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0))) then
tmp_1_47_reg_1268 <= grp_fu_403_p2;
tmp_1_48_reg_1273 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_1_4_reg_1103 <= grp_fu_403_p2;
tmp_1_5_reg_1108 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0))) then
tmp_1_51_reg_1283 <= grp_fu_403_p2;
tmp_1_52_reg_1288 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0))) then
tmp_1_55_reg_1298 <= grp_fu_403_p2;
tmp_1_56_reg_1303 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0))) then
tmp_1_59_reg_1313 <= grp_fu_403_p2;
tmp_1_60_reg_1318 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0))) then
tmp_1_63_reg_1328 <= grp_fu_403_p2;
tmp_1_64_reg_1333 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0))) then
tmp_1_67_reg_1343 <= grp_fu_403_p2;
tmp_1_68_reg_1348 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0))) then
tmp_1_71_reg_1358 <= grp_fu_403_p2;
tmp_1_72_reg_1363 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0))) then
tmp_1_75_reg_1373 <= grp_fu_403_p2;
tmp_1_76_reg_1378 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0))) then
tmp_1_79_reg_1388 <= grp_fu_403_p2;
tmp_1_80_reg_1393 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0))) then
tmp_1_83_reg_1403 <= grp_fu_403_p2;
tmp_1_84_reg_1408 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0))) then
tmp_1_87_reg_1418 <= grp_fu_403_p2;
tmp_1_88_reg_1423 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
tmp_1_8_reg_1118 <= grp_fu_403_p2;
tmp_1_9_reg_1123 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0))) then
tmp_1_91_reg_1433 <= grp_fu_403_p2;
tmp_1_92_reg_1438 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0))) then
tmp_1_95_reg_1448 <= grp_fu_403_p2;
tmp_1_96_reg_1453 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0))) then
tmp_reg_1323 <= tmp_fu_740_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage63_flag00011011, ap_reset_idle_pp0, ap_idle_pp0_1to1, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage40_flag00011011, ap_block_pp0_stage41_flag00011011, ap_block_pp0_stage42_flag00011011, ap_block_pp0_stage43_flag00011011, ap_block_pp0_stage44_flag00011011, ap_block_pp0_stage45_flag00011011, ap_block_pp0_stage46_flag00011011, ap_block_pp0_stage47_flag00011011, ap_block_pp0_stage48_flag00011011, ap_block_pp0_stage49_flag00011011, ap_block_pp0_stage50_flag00011011, ap_block_pp0_stage51_flag00011011, ap_block_pp0_stage52_flag00011011, ap_block_pp0_stage53_flag00011011, ap_block_pp0_stage54_flag00011011, ap_block_pp0_stage55_flag00011011, ap_block_pp0_stage56_flag00011011, ap_block_pp0_stage57_flag00011011, ap_block_pp0_stage58_flag00011011, ap_block_pp0_stage59_flag00011011, ap_block_pp0_stage60_flag00011011, ap_block_pp0_stage61_flag00011011, ap_block_pp0_stage62_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_reset_idle_pp0 = ap_const_logic_0) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_1to1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when ap_ST_fsm_pp0_stage13 =>
if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
end if;
when ap_ST_fsm_pp0_stage14 =>
if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
end if;
when ap_ST_fsm_pp0_stage15 =>
if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
end if;
when ap_ST_fsm_pp0_stage16 =>
if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
end if;
when ap_ST_fsm_pp0_stage17 =>
if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
end if;
when ap_ST_fsm_pp0_stage18 =>
if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
end if;
when ap_ST_fsm_pp0_stage19 =>
if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
end if;
when ap_ST_fsm_pp0_stage20 =>
if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
end if;
when ap_ST_fsm_pp0_stage21 =>
if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
end if;
when ap_ST_fsm_pp0_stage22 =>
if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
end if;
when ap_ST_fsm_pp0_stage23 =>
if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
end if;
when ap_ST_fsm_pp0_stage24 =>
if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
end if;
when ap_ST_fsm_pp0_stage25 =>
if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
end if;
when ap_ST_fsm_pp0_stage26 =>
if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
end if;
when ap_ST_fsm_pp0_stage27 =>
if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
end if;
when ap_ST_fsm_pp0_stage28 =>
if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
end if;
when ap_ST_fsm_pp0_stage29 =>
if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
end if;
when ap_ST_fsm_pp0_stage30 =>
if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
end if;
when ap_ST_fsm_pp0_stage31 =>
if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
end if;
when ap_ST_fsm_pp0_stage32 =>
if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
end if;
when ap_ST_fsm_pp0_stage33 =>
if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
end if;
when ap_ST_fsm_pp0_stage34 =>
if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
end if;
when ap_ST_fsm_pp0_stage35 =>
if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
end if;
when ap_ST_fsm_pp0_stage36 =>
if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
end if;
when ap_ST_fsm_pp0_stage37 =>
if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
end if;
when ap_ST_fsm_pp0_stage38 =>
if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
end if;
when ap_ST_fsm_pp0_stage39 =>
if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
end if;
when ap_ST_fsm_pp0_stage40 =>
if ((ap_block_pp0_stage40_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
end if;
when ap_ST_fsm_pp0_stage41 =>
if ((ap_block_pp0_stage41_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
end if;
when ap_ST_fsm_pp0_stage42 =>
if ((ap_block_pp0_stage42_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
end if;
when ap_ST_fsm_pp0_stage43 =>
if ((ap_block_pp0_stage43_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
end if;
when ap_ST_fsm_pp0_stage44 =>
if ((ap_block_pp0_stage44_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
end if;
when ap_ST_fsm_pp0_stage45 =>
if ((ap_block_pp0_stage45_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
end if;
when ap_ST_fsm_pp0_stage46 =>
if ((ap_block_pp0_stage46_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
end if;
when ap_ST_fsm_pp0_stage47 =>
if ((ap_block_pp0_stage47_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
end if;
when ap_ST_fsm_pp0_stage48 =>
if ((ap_block_pp0_stage48_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
end if;
when ap_ST_fsm_pp0_stage49 =>
if ((ap_block_pp0_stage49_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
end if;
when ap_ST_fsm_pp0_stage50 =>
if ((ap_block_pp0_stage50_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
end if;
when ap_ST_fsm_pp0_stage51 =>
if ((ap_block_pp0_stage51_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
end if;
when ap_ST_fsm_pp0_stage52 =>
if ((ap_block_pp0_stage52_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
end if;
when ap_ST_fsm_pp0_stage53 =>
if ((ap_block_pp0_stage53_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
end if;
when ap_ST_fsm_pp0_stage54 =>
if ((ap_block_pp0_stage54_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
end if;
when ap_ST_fsm_pp0_stage55 =>
if ((ap_block_pp0_stage55_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
end if;
when ap_ST_fsm_pp0_stage56 =>
if ((ap_block_pp0_stage56_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
end if;
when ap_ST_fsm_pp0_stage57 =>
if ((ap_block_pp0_stage57_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
end if;
when ap_ST_fsm_pp0_stage58 =>
if ((ap_block_pp0_stage58_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
end if;
when ap_ST_fsm_pp0_stage59 =>
if ((ap_block_pp0_stage59_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
end if;
when ap_ST_fsm_pp0_stage60 =>
if ((ap_block_pp0_stage60_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
end if;
when ap_ST_fsm_pp0_stage61 =>
if ((ap_block_pp0_stage61_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
end if;
when ap_ST_fsm_pp0_stage62 =>
if ((ap_block_pp0_stage62_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
end if;
when ap_ST_fsm_pp0_stage63 =>
if ((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(10);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(13);
ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(14);
ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(15);
ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(16);
ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(17);
ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(18);
ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(19);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(20);
ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(21);
ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(22);
ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(23);
ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(24);
ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(25);
ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(26);
ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(27);
ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(28);
ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(29);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(30);
ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(31);
ap_CS_fsm_pp0_stage32 <= ap_CS_fsm(32);
ap_CS_fsm_pp0_stage33 <= ap_CS_fsm(33);
ap_CS_fsm_pp0_stage34 <= ap_CS_fsm(34);
ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(35);
ap_CS_fsm_pp0_stage36 <= ap_CS_fsm(36);
ap_CS_fsm_pp0_stage37 <= ap_CS_fsm(37);
ap_CS_fsm_pp0_stage38 <= ap_CS_fsm(38);
ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(39);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage40 <= ap_CS_fsm(40);
ap_CS_fsm_pp0_stage41 <= ap_CS_fsm(41);
ap_CS_fsm_pp0_stage42 <= ap_CS_fsm(42);
ap_CS_fsm_pp0_stage43 <= ap_CS_fsm(43);
ap_CS_fsm_pp0_stage44 <= ap_CS_fsm(44);
ap_CS_fsm_pp0_stage45 <= ap_CS_fsm(45);
ap_CS_fsm_pp0_stage46 <= ap_CS_fsm(46);
ap_CS_fsm_pp0_stage47 <= ap_CS_fsm(47);
ap_CS_fsm_pp0_stage48 <= ap_CS_fsm(48);
ap_CS_fsm_pp0_stage49 <= ap_CS_fsm(49);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage50 <= ap_CS_fsm(50);
ap_CS_fsm_pp0_stage51 <= ap_CS_fsm(51);
ap_CS_fsm_pp0_stage52 <= ap_CS_fsm(52);
ap_CS_fsm_pp0_stage53 <= ap_CS_fsm(53);
ap_CS_fsm_pp0_stage54 <= ap_CS_fsm(54);
ap_CS_fsm_pp0_stage55 <= ap_CS_fsm(55);
ap_CS_fsm_pp0_stage56 <= ap_CS_fsm(56);
ap_CS_fsm_pp0_stage57 <= ap_CS_fsm(57);
ap_CS_fsm_pp0_stage58 <= ap_CS_fsm(58);
ap_CS_fsm_pp0_stage59 <= ap_CS_fsm(59);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage60 <= ap_CS_fsm(60);
ap_CS_fsm_pp0_stage61 <= ap_CS_fsm(61);
ap_CS_fsm_pp0_stage62 <= ap_CS_fsm(62);
ap_CS_fsm_pp0_stage63 <= ap_CS_fsm(63);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(9);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0, ap_ce)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_ce = ap_const_logic_0) or ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)));
end process;
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage10_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage11_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage12_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage13_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage14_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage15_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage16_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage17_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage18_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage19_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage1_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage20_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage21_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage22_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage23_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage24_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage25_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage26_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage27_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage28_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage29_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage2_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage30_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage31_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage32_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage32_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage33_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage33_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage34_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage34_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage35_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage36_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage36_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage37_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage37_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage38_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage38_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage39_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage39_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage3_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage40_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage40_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage41_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage41_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage42_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage42_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage43_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage43_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage44_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage44_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage45_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage45_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage46_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage46_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage47_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage47_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage48_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage48_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage49_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage49_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage4_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage50_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage50_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage51_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage51_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage52_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage52_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage53_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage53_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage54_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage54_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage55_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage55_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage56_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage56_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage57_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage57_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage58_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage58_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage59_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage59_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage5_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage60_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage60_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage61_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage61_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage62_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage62_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage63_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage63_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage6_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage7_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage8_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage9_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_state10_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state20_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage32_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage33_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage34_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage35_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage36_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage37_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage38_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage39_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage40_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage41_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage42_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage43_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage44_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage45_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage46_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage47_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage48_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage49_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage50_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage51_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage52_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage53_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage54_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage55_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage56_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage57_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage58_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage59_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage60_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage61_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage62_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage63_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_ce, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0_reg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0 <= ap_start;
else
ap_enable_reg_pp0_iter0 <= ap_enable_reg_pp0_iter0_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to0_assign_proc : process(ap_enable_reg_pp0_iter0)
begin
if ((ap_const_logic_0 = ap_enable_reg_pp0_iter0)) then
ap_idle_pp0_0to0 <= ap_const_logic_1;
else
ap_idle_pp0_0to0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_1to1_assign_proc : process(ap_enable_reg_pp0_iter1)
begin
if ((ap_const_logic_0 = ap_enable_reg_pp0_iter1)) then
ap_idle_pp0_1to1 <= ap_const_logic_1;
else
ap_idle_pp0_1to1 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to0))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_return <= (tmp63_fu_1071_p2 or tmp_reg_1323);
contacts_V_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_78;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_76;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_74;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_72;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_70;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_68;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_66;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_64;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_62;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_60;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_58;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_56;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_54;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_52;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_50;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_48;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_46;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_44;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_42;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_40;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_38;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_36;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_34;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_32;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_30;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_28;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_26;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_24;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_22;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_20;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_18;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_16;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_14;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_12;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_10;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_8;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_0;
else
contacts_V_address0 <= "XXXXXXX";
end if;
else
contacts_V_address0 <= "XXXXXXX";
end if;
end process;
contacts_V_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_79;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_77;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_75;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_73;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_71;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_69;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_67;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_65;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_63;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_61;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_59;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_57;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_55;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_53;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_51;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_49;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_47;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_45;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_43;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_41;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_39;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_37;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_35;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_33;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_31;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_29;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_27;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_25;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_23;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_21;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_19;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_17;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_15;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_13;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_11;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_9;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1;
else
contacts_V_address1 <= "XXXXXXX";
end if;
else
contacts_V_address1 <= "XXXXXXX";
end if;
end process;
contacts_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then
contacts_V_ce0 <= ap_const_logic_1;
else
contacts_V_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_V_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then
contacts_V_ce1 <= ap_const_logic_1;
else
contacts_V_ce1 <= ap_const_logic_0;
end if;
end process;
grp_fu_403_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
grp_fu_403_p1 <= db_item_V_read_reg_1082;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_403_p1 <= ap_port_reg_db_item_V;
else
grp_fu_403_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_403_p2 <= "1" when (contacts_V_q0 = grp_fu_403_p1) else "0";
grp_fu_409_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
grp_fu_409_p1 <= db_item_V_read_reg_1082;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_409_p1 <= ap_port_reg_db_item_V;
else
grp_fu_409_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_409_p2 <= "1" when (contacts_V_q1 = grp_fu_409_p1) else "0";
tmp100_fu_908_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp101_fu_930_p2 <= (tmp103_fu_924_p2 or tmp102_fu_920_p2);
tmp102_fu_920_p2 <= (tmp_1_99_reg_1463 or tmp_1_100_reg_1468);
tmp103_fu_924_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp104_fu_973_p2 <= (tmp108_fu_967_p2 or tmp105_reg_1488);
tmp105_fu_951_p2 <= (tmp107_fu_945_p2 or tmp106_fu_941_p2);
tmp106_fu_941_p2 <= (tmp_1_103_reg_1478 or tmp_1_104_reg_1483);
tmp107_fu_945_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp108_fu_967_p2 <= (tmp110_fu_961_p2 or tmp109_fu_957_p2);
tmp109_fu_957_p2 <= (tmp_1_107_reg_1493 or tmp_1_108_reg_1498);
tmp10_fu_484_p2 <= (tmp14_fu_478_p2 or tmp11_reg_1128);
tmp110_fu_961_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp111_fu_1061_p2 <= (tmp119_fu_1056_p2 or tmp112_reg_1533);
tmp112_fu_1015_p2 <= (tmp116_fu_1009_p2 or tmp113_reg_1518);
tmp113_fu_993_p2 <= (tmp115_fu_987_p2 or tmp114_fu_983_p2);
tmp114_fu_983_p2 <= (tmp_1_111_reg_1508 or tmp_1_112_reg_1513);
tmp115_fu_987_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp116_fu_1009_p2 <= (tmp118_fu_1003_p2 or tmp117_fu_999_p2);
tmp117_fu_999_p2 <= (tmp_1_115_reg_1523 or tmp_1_116_reg_1528);
tmp118_fu_1003_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp119_fu_1056_p2 <= (tmp123_fu_1050_p2 or tmp120_reg_1548);
tmp11_fu_462_p2 <= (tmp13_fu_456_p2 or tmp12_fu_452_p2);
tmp120_fu_1030_p2 <= (tmp122_fu_1024_p2 or tmp121_fu_1020_p2);
tmp121_fu_1020_p2 <= (tmp_1_119_reg_1538 or tmp_1_120_reg_1543);
tmp122_fu_1024_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp123_fu_1050_p2 <= (tmp125_fu_1044_p2 or tmp124_fu_1040_p2);
tmp124_fu_1040_p2 <= (tmp_1_123_reg_1553 or tmp_1_124_reg_1558);
tmp125_fu_1044_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp12_fu_452_p2 <= (tmp_1_8_reg_1118 or tmp_1_9_reg_1123);
tmp13_fu_456_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp14_fu_478_p2 <= (tmp16_fu_472_p2 or tmp15_fu_468_p2);
tmp15_fu_468_p2 <= (tmp_1_11_reg_1133 or tmp_1_12_reg_1138);
tmp16_fu_472_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp17_fu_568_p2 <= (tmp25_fu_563_p2 or tmp18_reg_1173);
tmp18_fu_526_p2 <= (tmp22_fu_520_p2 or tmp19_reg_1158);
tmp19_fu_504_p2 <= (tmp21_fu_498_p2 or tmp20_fu_494_p2);
tmp1_fu_705_p2 <= (tmp17_reg_1203 or tmp2_reg_1143);
tmp20_fu_494_p2 <= (tmp_1_15_reg_1148 or tmp_1_16_reg_1153);
tmp21_fu_498_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp22_fu_520_p2 <= (tmp24_fu_514_p2 or tmp23_fu_510_p2);
tmp23_fu_510_p2 <= (tmp_1_19_reg_1163 or tmp_1_20_reg_1168);
tmp24_fu_514_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp25_fu_563_p2 <= (tmp29_fu_557_p2 or tmp26_reg_1188);
tmp26_fu_541_p2 <= (tmp28_fu_535_p2 or tmp27_fu_531_p2);
tmp27_fu_531_p2 <= (tmp_1_23_reg_1178 or tmp_1_24_reg_1183);
tmp28_fu_535_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp29_fu_557_p2 <= (tmp31_fu_551_p2 or tmp30_fu_547_p2);
tmp2_fu_489_p2 <= (tmp10_fu_484_p2 or tmp3_reg_1113);
tmp30_fu_547_p2 <= (tmp_1_27_reg_1193 or tmp_1_28_reg_1198);
tmp31_fu_551_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp32_fu_735_p2 <= (tmp48_fu_730_p2 or tmp33_reg_1263);
tmp33_fu_647_p2 <= (tmp41_fu_642_p2 or tmp34_reg_1233);
tmp34_fu_605_p2 <= (tmp38_fu_599_p2 or tmp35_reg_1218);
tmp35_fu_583_p2 <= (tmp37_fu_577_p2 or tmp36_fu_573_p2);
tmp36_fu_573_p2 <= (tmp_1_31_reg_1208 or tmp_1_32_reg_1213);
tmp37_fu_577_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp38_fu_599_p2 <= (tmp40_fu_593_p2 or tmp39_fu_589_p2);
tmp39_fu_589_p2 <= (tmp_1_35_reg_1223 or tmp_1_36_reg_1228);
tmp3_fu_447_p2 <= (tmp7_fu_441_p2 or tmp4_reg_1098);
tmp40_fu_593_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp41_fu_642_p2 <= (tmp45_fu_636_p2 or tmp42_reg_1248);
tmp42_fu_620_p2 <= (tmp44_fu_614_p2 or tmp43_fu_610_p2);
tmp43_fu_610_p2 <= (tmp_1_39_reg_1238 or tmp_1_40_reg_1243);
tmp44_fu_614_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp45_fu_636_p2 <= (tmp47_fu_630_p2 or tmp46_fu_626_p2);
tmp46_fu_626_p2 <= (tmp_1_43_reg_1253 or tmp_1_44_reg_1258);
tmp47_fu_630_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp48_fu_730_p2 <= (tmp56_fu_725_p2 or tmp49_reg_1293);
tmp49_fu_684_p2 <= (tmp53_fu_678_p2 or tmp50_reg_1278);
tmp4_fu_425_p2 <= (tmp6_fu_419_p2 or tmp5_fu_415_p2);
tmp50_fu_662_p2 <= (tmp52_fu_656_p2 or tmp51_fu_652_p2);
tmp51_fu_652_p2 <= (tmp_1_47_reg_1268 or tmp_1_48_reg_1273);
tmp52_fu_656_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp53_fu_678_p2 <= (tmp55_fu_672_p2 or tmp54_fu_668_p2);
tmp54_fu_668_p2 <= (tmp_1_51_reg_1283 or tmp_1_52_reg_1288);
tmp55_fu_672_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp56_fu_725_p2 <= (tmp60_fu_719_p2 or tmp57_reg_1308);
tmp57_fu_699_p2 <= (tmp59_fu_693_p2 or tmp58_fu_689_p2);
tmp58_fu_689_p2 <= (tmp_1_55_reg_1298 or tmp_1_56_reg_1303);
tmp59_fu_693_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp5_fu_415_p2 <= (tmp_1_reg_1088 or tmp_1_1_reg_1093);
tmp60_fu_719_p2 <= (tmp62_fu_713_p2 or tmp61_fu_709_p2);
tmp61_fu_709_p2 <= (tmp_1_59_reg_1313 or tmp_1_60_reg_1318);
tmp62_fu_713_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp63_fu_1071_p2 <= (tmp95_fu_1066_p2 or tmp64_fu_1036_p2);
tmp64_fu_1036_p2 <= (tmp80_reg_1443 or tmp65_reg_1383);
tmp65_fu_820_p2 <= (tmp73_fu_815_p2 or tmp66_reg_1353);
tmp66_fu_778_p2 <= (tmp70_fu_772_p2 or tmp67_reg_1338);
tmp67_fu_756_p2 <= (tmp69_fu_750_p2 or tmp68_fu_746_p2);
tmp68_fu_746_p2 <= (tmp_1_63_reg_1328 or tmp_1_64_reg_1333);
tmp69_fu_750_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp6_fu_419_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp70_fu_772_p2 <= (tmp72_fu_766_p2 or tmp71_fu_762_p2);
tmp71_fu_762_p2 <= (tmp_1_67_reg_1343 or tmp_1_68_reg_1348);
tmp72_fu_766_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp73_fu_815_p2 <= (tmp77_fu_809_p2 or tmp74_reg_1368);
tmp74_fu_793_p2 <= (tmp76_fu_787_p2 or tmp75_fu_783_p2);
tmp75_fu_783_p2 <= (tmp_1_71_reg_1358 or tmp_1_72_reg_1363);
tmp76_fu_787_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp77_fu_809_p2 <= (tmp79_fu_803_p2 or tmp78_fu_799_p2);
tmp78_fu_799_p2 <= (tmp_1_75_reg_1373 or tmp_1_76_reg_1378);
tmp79_fu_803_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp7_fu_441_p2 <= (tmp9_fu_435_p2 or tmp8_fu_431_p2);
tmp80_fu_899_p2 <= (tmp88_fu_894_p2 or tmp81_reg_1413);
tmp81_fu_857_p2 <= (tmp85_fu_851_p2 or tmp82_reg_1398);
tmp82_fu_835_p2 <= (tmp84_fu_829_p2 or tmp83_fu_825_p2);
tmp83_fu_825_p2 <= (tmp_1_79_reg_1388 or tmp_1_80_reg_1393);
tmp84_fu_829_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp85_fu_851_p2 <= (tmp87_fu_845_p2 or tmp86_fu_841_p2);
tmp86_fu_841_p2 <= (tmp_1_83_reg_1403 or tmp_1_84_reg_1408);
tmp87_fu_845_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp88_fu_894_p2 <= (tmp92_fu_888_p2 or tmp89_reg_1428);
tmp89_fu_872_p2 <= (tmp91_fu_866_p2 or tmp90_fu_862_p2);
tmp8_fu_431_p2 <= (tmp_1_4_reg_1103 or tmp_1_5_reg_1108);
tmp90_fu_862_p2 <= (tmp_1_87_reg_1418 or tmp_1_88_reg_1423);
tmp91_fu_866_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp92_fu_888_p2 <= (tmp94_fu_882_p2 or tmp93_fu_878_p2);
tmp93_fu_878_p2 <= (tmp_1_91_reg_1433 or tmp_1_92_reg_1438);
tmp94_fu_882_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp95_fu_1066_p2 <= (tmp111_fu_1061_p2 or tmp96_reg_1503);
tmp96_fu_978_p2 <= (tmp104_fu_973_p2 or tmp97_reg_1473);
tmp97_fu_936_p2 <= (tmp101_fu_930_p2 or tmp98_reg_1458);
tmp98_fu_914_p2 <= (tmp100_fu_908_p2 or tmp99_fu_904_p2);
tmp99_fu_904_p2 <= (tmp_1_95_reg_1448 or tmp_1_96_reg_1453);
tmp9_fu_435_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp_fu_740_p2 <= (tmp32_fu_735_p2 or tmp1_fu_705_p2);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity match_db_contact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
db_item_V : IN STD_LOGIC_VECTOR (511 downto 0);
contacts_V_address0 : OUT STD_LOGIC_VECTOR (6 downto 0);
contacts_V_ce0 : OUT STD_LOGIC;
contacts_V_q0 : IN STD_LOGIC_VECTOR (511 downto 0);
contacts_V_address1 : OUT STD_LOGIC_VECTOR (6 downto 0);
contacts_V_ce1 : OUT STD_LOGIC;
contacts_V_q1 : IN STD_LOGIC_VECTOR (511 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of match_db_contact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage40 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage41 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage42 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage43 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage44 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage45 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage46 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage47 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage48 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage49 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage50 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage51 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage52 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage53 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage54 : STD_LOGIC_VECTOR (63 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage55 : STD_LOGIC_VECTOR (63 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage56 : STD_LOGIC_VECTOR (63 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage57 : STD_LOGIC_VECTOR (63 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage58 : STD_LOGIC_VECTOR (63 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage59 : STD_LOGIC_VECTOR (63 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage60 : STD_LOGIC_VECTOR (63 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage61 : STD_LOGIC_VECTOR (63 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage62 : STD_LOGIC_VECTOR (63 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage63 : STD_LOGIC_VECTOR (63 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv7_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_const_lv7_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_const_lv7_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_const_lv7_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_const_lv7_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_const_lv7_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_const_lv7_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_const_lv7_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_const_lv7_A : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_const_lv7_B : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_const_lv7_C : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_const_lv7_D : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_const_lv7_E : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_const_lv7_F : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_const_lv7_10 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_const_lv7_11 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_const_lv7_12 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_const_lv7_13 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_const_lv7_14 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_const_lv7_15 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_const_lv7_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_const_lv7_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_const_lv7_18 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_const_lv7_19 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_const_lv7_1A : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_const_lv7_1B : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_const_lv7_1C : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_const_lv7_1D : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_const_lv7_1E : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_const_lv7_1F : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_const_lv7_20 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_const_lv7_21 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_const_lv7_22 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_const_lv7_23 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_const_lv7_24 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_const_lv7_25 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_const_lv7_26 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_const_lv7_27 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_const_lv7_28 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_const_lv7_29 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_const_lv7_2A : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_const_lv7_2B : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_const_lv7_2C : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_const_lv7_2D : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_const_lv7_2E : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_const_lv7_2F : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_const_lv7_30 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_const_lv7_31 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv7_33 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_const_lv7_34 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_const_lv7_35 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_const_lv7_36 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_const_lv7_37 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_const_lv7_38 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_const_lv7_39 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_const_lv7_3A : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_const_lv7_3B : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_const_lv7_3C : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_const_lv7_3D : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_const_lv7_3E : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_const_lv7_3F : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_41 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_const_lv7_42 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_const_lv7_43 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_const_lv7_44 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_const_lv7_45 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_const_lv7_46 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_const_lv7_47 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_const_lv7_48 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_const_lv7_49 : STD_LOGIC_VECTOR (6 downto 0) := "1001001";
constant ap_const_lv7_4A : STD_LOGIC_VECTOR (6 downto 0) := "1001010";
constant ap_const_lv7_4B : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_const_lv7_4C : STD_LOGIC_VECTOR (6 downto 0) := "1001100";
constant ap_const_lv7_4D : STD_LOGIC_VECTOR (6 downto 0) := "1001101";
constant ap_const_lv7_4E : STD_LOGIC_VECTOR (6 downto 0) := "1001110";
constant ap_const_lv7_4F : STD_LOGIC_VECTOR (6 downto 0) := "1001111";
constant ap_const_lv7_50 : STD_LOGIC_VECTOR (6 downto 0) := "1010000";
constant ap_const_lv7_51 : STD_LOGIC_VECTOR (6 downto 0) := "1010001";
constant ap_const_lv7_52 : STD_LOGIC_VECTOR (6 downto 0) := "1010010";
constant ap_const_lv7_53 : STD_LOGIC_VECTOR (6 downto 0) := "1010011";
constant ap_const_lv7_54 : STD_LOGIC_VECTOR (6 downto 0) := "1010100";
constant ap_const_lv7_55 : STD_LOGIC_VECTOR (6 downto 0) := "1010101";
constant ap_const_lv7_56 : STD_LOGIC_VECTOR (6 downto 0) := "1010110";
constant ap_const_lv7_57 : STD_LOGIC_VECTOR (6 downto 0) := "1010111";
constant ap_const_lv7_58 : STD_LOGIC_VECTOR (6 downto 0) := "1011000";
constant ap_const_lv7_59 : STD_LOGIC_VECTOR (6 downto 0) := "1011001";
constant ap_const_lv7_5A : STD_LOGIC_VECTOR (6 downto 0) := "1011010";
constant ap_const_lv7_5B : STD_LOGIC_VECTOR (6 downto 0) := "1011011";
constant ap_const_lv7_5C : STD_LOGIC_VECTOR (6 downto 0) := "1011100";
constant ap_const_lv7_5D : STD_LOGIC_VECTOR (6 downto 0) := "1011101";
constant ap_const_lv7_5E : STD_LOGIC_VECTOR (6 downto 0) := "1011110";
constant ap_const_lv7_5F : STD_LOGIC_VECTOR (6 downto 0) := "1011111";
constant ap_const_lv7_60 : STD_LOGIC_VECTOR (6 downto 0) := "1100000";
constant ap_const_lv7_61 : STD_LOGIC_VECTOR (6 downto 0) := "1100001";
constant ap_const_lv7_62 : STD_LOGIC_VECTOR (6 downto 0) := "1100010";
constant ap_const_lv7_63 : STD_LOGIC_VECTOR (6 downto 0) := "1100011";
constant ap_const_lv7_64 : STD_LOGIC_VECTOR (6 downto 0) := "1100100";
constant ap_const_lv7_65 : STD_LOGIC_VECTOR (6 downto 0) := "1100101";
constant ap_const_lv7_66 : STD_LOGIC_VECTOR (6 downto 0) := "1100110";
constant ap_const_lv7_67 : STD_LOGIC_VECTOR (6 downto 0) := "1100111";
constant ap_const_lv7_68 : STD_LOGIC_VECTOR (6 downto 0) := "1101000";
constant ap_const_lv7_69 : STD_LOGIC_VECTOR (6 downto 0) := "1101001";
constant ap_const_lv7_6A : STD_LOGIC_VECTOR (6 downto 0) := "1101010";
constant ap_const_lv7_6B : STD_LOGIC_VECTOR (6 downto 0) := "1101011";
constant ap_const_lv7_6C : STD_LOGIC_VECTOR (6 downto 0) := "1101100";
constant ap_const_lv7_6D : STD_LOGIC_VECTOR (6 downto 0) := "1101101";
constant ap_const_lv7_6E : STD_LOGIC_VECTOR (6 downto 0) := "1101110";
constant ap_const_lv7_6F : STD_LOGIC_VECTOR (6 downto 0) := "1101111";
constant ap_const_lv7_70 : STD_LOGIC_VECTOR (6 downto 0) := "1110000";
constant ap_const_lv7_71 : STD_LOGIC_VECTOR (6 downto 0) := "1110001";
constant ap_const_lv7_72 : STD_LOGIC_VECTOR (6 downto 0) := "1110010";
constant ap_const_lv7_73 : STD_LOGIC_VECTOR (6 downto 0) := "1110011";
constant ap_const_lv7_74 : STD_LOGIC_VECTOR (6 downto 0) := "1110100";
constant ap_const_lv7_75 : STD_LOGIC_VECTOR (6 downto 0) := "1110101";
constant ap_const_lv7_76 : STD_LOGIC_VECTOR (6 downto 0) := "1110110";
constant ap_const_lv7_77 : STD_LOGIC_VECTOR (6 downto 0) := "1110111";
constant ap_const_lv7_78 : STD_LOGIC_VECTOR (6 downto 0) := "1111000";
constant ap_const_lv7_79 : STD_LOGIC_VECTOR (6 downto 0) := "1111001";
constant ap_const_lv7_7A : STD_LOGIC_VECTOR (6 downto 0) := "1111010";
constant ap_const_lv7_7B : STD_LOGIC_VECTOR (6 downto 0) := "1111011";
constant ap_const_lv7_7C : STD_LOGIC_VECTOR (6 downto 0) := "1111100";
constant ap_const_lv7_7D : STD_LOGIC_VECTOR (6 downto 0) := "1111101";
constant ap_const_lv7_7E : STD_LOGIC_VECTOR (6 downto 0) := "1111110";
constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_CS_fsm_pp0_stage63 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage63 : signal is "none";
signal ap_block_state64_pp0_stage63_iter0 : BOOLEAN;
signal ap_block_pp0_stage63_flag00011001 : BOOLEAN;
signal db_item_V_read_reg_1082 : STD_LOGIC_VECTOR (511 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state2_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal grp_fu_403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1088 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_1_reg_1093 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_reg_1098 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state3_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal tmp_1_4_reg_1103 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state4_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal tmp_1_5_reg_1108 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_reg_1113 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state5_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal tmp_1_8_reg_1118 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state6_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal tmp_1_9_reg_1123 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_fu_462_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_reg_1128 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state7_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal tmp_1_11_reg_1133 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state8_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal tmp_1_12_reg_1138 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_reg_1143 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state9_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal tmp_1_15_reg_1148 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state10_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal tmp_1_16_reg_1153 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_fu_504_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_reg_1158 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state11_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal tmp_1_19_reg_1163 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state12_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal tmp_1_20_reg_1168 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_fu_526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_reg_1173 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_state13_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal tmp_1_23_reg_1178 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
signal ap_block_state14_pp0_stage13_iter0 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011001 : BOOLEAN;
signal tmp_1_24_reg_1183 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_fu_541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_reg_1188 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
signal ap_block_state15_pp0_stage14_iter0 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011001 : BOOLEAN;
signal tmp_1_27_reg_1193 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none";
signal ap_block_state16_pp0_stage15_iter0 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011001 : BOOLEAN;
signal tmp_1_28_reg_1198 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_fu_568_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_reg_1203 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none";
signal ap_block_state17_pp0_stage16_iter0 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011001 : BOOLEAN;
signal tmp_1_31_reg_1208 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none";
signal ap_block_state18_pp0_stage17_iter0 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011001 : BOOLEAN;
signal tmp_1_32_reg_1213 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp35_fu_583_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp35_reg_1218 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none";
signal ap_block_state19_pp0_stage18_iter0 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011001 : BOOLEAN;
signal tmp_1_35_reg_1223 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none";
signal ap_block_state20_pp0_stage19_iter0 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011001 : BOOLEAN;
signal tmp_1_36_reg_1228 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp34_fu_605_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp34_reg_1233 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none";
signal ap_block_state21_pp0_stage20_iter0 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011001 : BOOLEAN;
signal tmp_1_39_reg_1238 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none";
signal ap_block_state22_pp0_stage21_iter0 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011001 : BOOLEAN;
signal tmp_1_40_reg_1243 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp42_fu_620_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp42_reg_1248 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none";
signal ap_block_state23_pp0_stage22_iter0 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011001 : BOOLEAN;
signal tmp_1_43_reg_1253 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none";
signal ap_block_state24_pp0_stage23_iter0 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011001 : BOOLEAN;
signal tmp_1_44_reg_1258 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp33_fu_647_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp33_reg_1263 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none";
signal ap_block_state25_pp0_stage24_iter0 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011001 : BOOLEAN;
signal tmp_1_47_reg_1268 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none";
signal ap_block_state26_pp0_stage25_iter0 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011001 : BOOLEAN;
signal tmp_1_48_reg_1273 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp50_fu_662_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp50_reg_1278 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none";
signal ap_block_state27_pp0_stage26_iter0 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011001 : BOOLEAN;
signal tmp_1_51_reg_1283 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none";
signal ap_block_state28_pp0_stage27_iter0 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011001 : BOOLEAN;
signal tmp_1_52_reg_1288 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp49_fu_684_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp49_reg_1293 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none";
signal ap_block_state29_pp0_stage28_iter0 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011001 : BOOLEAN;
signal tmp_1_55_reg_1298 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage29 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none";
signal ap_block_state30_pp0_stage29_iter0 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011001 : BOOLEAN;
signal tmp_1_56_reg_1303 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp57_fu_699_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp57_reg_1308 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none";
signal ap_block_state31_pp0_stage30_iter0 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011001 : BOOLEAN;
signal tmp_1_59_reg_1313 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none";
signal ap_block_state32_pp0_stage31_iter0 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011001 : BOOLEAN;
signal tmp_1_60_reg_1318 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_1323 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage32 : signal is "none";
signal ap_block_state33_pp0_stage32_iter0 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011001 : BOOLEAN;
signal tmp_1_63_reg_1328 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage33 : signal is "none";
signal ap_block_state34_pp0_stage33_iter0 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011001 : BOOLEAN;
signal tmp_1_64_reg_1333 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp67_fu_756_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp67_reg_1338 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage34 : signal is "none";
signal ap_block_state35_pp0_stage34_iter0 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011001 : BOOLEAN;
signal tmp_1_67_reg_1343 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none";
signal ap_block_state36_pp0_stage35_iter0 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011001 : BOOLEAN;
signal tmp_1_68_reg_1348 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp66_fu_778_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp66_reg_1353 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage36 : signal is "none";
signal ap_block_state37_pp0_stage36_iter0 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011001 : BOOLEAN;
signal tmp_1_71_reg_1358 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage37 : signal is "none";
signal ap_block_state38_pp0_stage37_iter0 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011001 : BOOLEAN;
signal tmp_1_72_reg_1363 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp74_fu_793_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp74_reg_1368 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage38 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage38 : signal is "none";
signal ap_block_state39_pp0_stage38_iter0 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011001 : BOOLEAN;
signal tmp_1_75_reg_1373 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage39 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none";
signal ap_block_state40_pp0_stage39_iter0 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011001 : BOOLEAN;
signal tmp_1_76_reg_1378 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp65_fu_820_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp65_reg_1383 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage40 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage40 : signal is "none";
signal ap_block_state41_pp0_stage40_iter0 : BOOLEAN;
signal ap_block_pp0_stage40_flag00011001 : BOOLEAN;
signal tmp_1_79_reg_1388 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage41 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage41 : signal is "none";
signal ap_block_state42_pp0_stage41_iter0 : BOOLEAN;
signal ap_block_pp0_stage41_flag00011001 : BOOLEAN;
signal tmp_1_80_reg_1393 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp82_fu_835_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp82_reg_1398 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage42 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage42 : signal is "none";
signal ap_block_state43_pp0_stage42_iter0 : BOOLEAN;
signal ap_block_pp0_stage42_flag00011001 : BOOLEAN;
signal tmp_1_83_reg_1403 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage43 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage43 : signal is "none";
signal ap_block_state44_pp0_stage43_iter0 : BOOLEAN;
signal ap_block_pp0_stage43_flag00011001 : BOOLEAN;
signal tmp_1_84_reg_1408 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp81_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp81_reg_1413 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage44 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage44 : signal is "none";
signal ap_block_state45_pp0_stage44_iter0 : BOOLEAN;
signal ap_block_pp0_stage44_flag00011001 : BOOLEAN;
signal tmp_1_87_reg_1418 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage45 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage45 : signal is "none";
signal ap_block_state46_pp0_stage45_iter0 : BOOLEAN;
signal ap_block_pp0_stage45_flag00011001 : BOOLEAN;
signal tmp_1_88_reg_1423 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp89_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp89_reg_1428 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage46 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage46 : signal is "none";
signal ap_block_state47_pp0_stage46_iter0 : BOOLEAN;
signal ap_block_pp0_stage46_flag00011001 : BOOLEAN;
signal tmp_1_91_reg_1433 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage47 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage47 : signal is "none";
signal ap_block_state48_pp0_stage47_iter0 : BOOLEAN;
signal ap_block_pp0_stage47_flag00011001 : BOOLEAN;
signal tmp_1_92_reg_1438 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp80_fu_899_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp80_reg_1443 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage48 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage48 : signal is "none";
signal ap_block_state49_pp0_stage48_iter0 : BOOLEAN;
signal ap_block_pp0_stage48_flag00011001 : BOOLEAN;
signal tmp_1_95_reg_1448 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage49 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage49 : signal is "none";
signal ap_block_state50_pp0_stage49_iter0 : BOOLEAN;
signal ap_block_pp0_stage49_flag00011001 : BOOLEAN;
signal tmp_1_96_reg_1453 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp98_fu_914_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp98_reg_1458 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage50 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage50 : signal is "none";
signal ap_block_state51_pp0_stage50_iter0 : BOOLEAN;
signal ap_block_pp0_stage50_flag00011001 : BOOLEAN;
signal tmp_1_99_reg_1463 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage51 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage51 : signal is "none";
signal ap_block_state52_pp0_stage51_iter0 : BOOLEAN;
signal ap_block_pp0_stage51_flag00011001 : BOOLEAN;
signal tmp_1_100_reg_1468 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp97_fu_936_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp97_reg_1473 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage52 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage52 : signal is "none";
signal ap_block_state53_pp0_stage52_iter0 : BOOLEAN;
signal ap_block_pp0_stage52_flag00011001 : BOOLEAN;
signal tmp_1_103_reg_1478 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage53 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage53 : signal is "none";
signal ap_block_state54_pp0_stage53_iter0 : BOOLEAN;
signal ap_block_pp0_stage53_flag00011001 : BOOLEAN;
signal tmp_1_104_reg_1483 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp105_fu_951_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp105_reg_1488 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage54 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage54 : signal is "none";
signal ap_block_state55_pp0_stage54_iter0 : BOOLEAN;
signal ap_block_pp0_stage54_flag00011001 : BOOLEAN;
signal tmp_1_107_reg_1493 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage55 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage55 : signal is "none";
signal ap_block_state56_pp0_stage55_iter0 : BOOLEAN;
signal ap_block_pp0_stage55_flag00011001 : BOOLEAN;
signal tmp_1_108_reg_1498 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp96_fu_978_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp96_reg_1503 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage56 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage56 : signal is "none";
signal ap_block_state57_pp0_stage56_iter0 : BOOLEAN;
signal ap_block_pp0_stage56_flag00011001 : BOOLEAN;
signal tmp_1_111_reg_1508 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage57 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage57 : signal is "none";
signal ap_block_state58_pp0_stage57_iter0 : BOOLEAN;
signal ap_block_pp0_stage57_flag00011001 : BOOLEAN;
signal tmp_1_112_reg_1513 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp113_fu_993_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp113_reg_1518 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage58 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage58 : signal is "none";
signal ap_block_state59_pp0_stage58_iter0 : BOOLEAN;
signal ap_block_pp0_stage58_flag00011001 : BOOLEAN;
signal tmp_1_115_reg_1523 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage59 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage59 : signal is "none";
signal ap_block_state60_pp0_stage59_iter0 : BOOLEAN;
signal ap_block_pp0_stage59_flag00011001 : BOOLEAN;
signal tmp_1_116_reg_1528 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp112_fu_1015_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp112_reg_1533 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage60 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage60 : signal is "none";
signal ap_block_state61_pp0_stage60_iter0 : BOOLEAN;
signal ap_block_pp0_stage60_flag00011001 : BOOLEAN;
signal tmp_1_119_reg_1538 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage61 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage61 : signal is "none";
signal ap_block_state62_pp0_stage61_iter0 : BOOLEAN;
signal ap_block_pp0_stage61_flag00011001 : BOOLEAN;
signal tmp_1_120_reg_1543 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp120_fu_1030_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp120_reg_1548 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage62 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage62 : signal is "none";
signal ap_block_state63_pp0_stage62_iter0 : BOOLEAN;
signal ap_block_pp0_stage62_flag00011001 : BOOLEAN;
signal tmp_1_123_reg_1553 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_124_reg_1558 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_enable_reg_pp0_iter0_reg : STD_LOGIC := '0';
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state65_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage63_flag00011011 : BOOLEAN;
signal ap_port_reg_db_item_V : STD_LOGIC_VECTOR (511 downto 0);
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage13_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage14_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage15_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage16_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage17_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage18_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage19_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage20_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage21_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage22_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage23_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage24_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage25_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage26_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage27_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage28_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage29_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage30_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage31_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage32_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage33_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage34_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage35_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage36_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage37_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage38_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage39_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage40_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage41_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage42_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage43_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage44_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage45_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage46_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage47_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage48_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage49_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage50_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage51_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage52_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage53_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage54_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage55_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage56_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage57_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage58_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage59_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage60_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage61_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage62_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage63_flag00000000 : BOOLEAN;
signal grp_fu_403_p1 : STD_LOGIC_VECTOR (511 downto 0);
signal grp_fu_409_p1 : STD_LOGIC_VECTOR (511 downto 0);
signal tmp6_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_415_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_fu_435_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp7_fu_441_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp13_fu_456_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_fu_452_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp16_fu_472_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_fu_468_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_fu_478_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp10_fu_484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp21_fu_498_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_fu_494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp24_fu_514_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_fu_510_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp22_fu_520_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp28_fu_535_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp27_fu_531_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp31_fu_551_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp30_fu_547_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp29_fu_557_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_fu_563_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp37_fu_577_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp36_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp40_fu_593_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp39_fu_589_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp38_fu_599_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp44_fu_614_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp43_fu_610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp47_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp46_fu_626_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp45_fu_636_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp41_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp52_fu_656_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp51_fu_652_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp55_fu_672_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp54_fu_668_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp53_fu_678_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp59_fu_693_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp58_fu_689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp62_fu_713_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp61_fu_709_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp60_fu_719_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp56_fu_725_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp48_fu_730_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp32_fu_735_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp1_fu_705_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp69_fu_750_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp68_fu_746_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp72_fu_766_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp71_fu_762_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp70_fu_772_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp76_fu_787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp75_fu_783_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp79_fu_803_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp78_fu_799_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp77_fu_809_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp73_fu_815_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp84_fu_829_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp83_fu_825_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp87_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp86_fu_841_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp85_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp91_fu_866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp90_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp94_fu_882_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp93_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp92_fu_888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp88_fu_894_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp100_fu_908_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp99_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp103_fu_924_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp102_fu_920_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp101_fu_930_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp107_fu_945_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp106_fu_941_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp110_fu_961_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp109_fu_957_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp108_fu_967_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp104_fu_973_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp115_fu_987_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp114_fu_983_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp118_fu_1003_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp117_fu_999_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp116_fu_1009_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp122_fu_1024_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp121_fu_1020_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp125_fu_1044_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp124_fu_1040_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp123_fu_1050_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp119_fu_1056_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp111_fu_1061_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp95_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp64_fu_1036_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp63_fu_1071_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (63 downto 0);
signal ap_idle_pp0_0to0 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_idle_pp0_1to1 : STD_LOGIC;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage40_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage41_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage42_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage43_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage44_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage45_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage46_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage47_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage48_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage49_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage50_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage51_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage52_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage53_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage54_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage55_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage56_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage57_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage58_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage59_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage60_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage61_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage62_flag00011011 : BOOLEAN;
signal ap_enable_pp0 : STD_LOGIC;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0_reg <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_port_reg_db_item_V <= db_item_V;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
db_item_V_read_reg_1082 <= ap_port_reg_db_item_V;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0))) then
tmp105_reg_1488 <= tmp105_fu_951_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0))) then
tmp112_reg_1533 <= tmp112_fu_1015_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0))) then
tmp113_reg_1518 <= tmp113_fu_993_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp11_reg_1128 <= tmp11_fu_462_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0))) then
tmp120_reg_1548 <= tmp120_fu_1030_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0))) then
tmp17_reg_1203 <= tmp17_fu_568_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
tmp18_reg_1173 <= tmp18_fu_526_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp19_reg_1158 <= tmp19_fu_504_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
tmp26_reg_1188 <= tmp26_fu_541_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp2_reg_1143 <= tmp2_fu_489_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0))) then
tmp33_reg_1263 <= tmp33_fu_647_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0))) then
tmp34_reg_1233 <= tmp34_fu_605_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0))) then
tmp35_reg_1218 <= tmp35_fu_583_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp3_reg_1113 <= tmp3_fu_447_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0))) then
tmp42_reg_1248 <= tmp42_fu_620_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0))) then
tmp49_reg_1293 <= tmp49_fu_684_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp4_reg_1098 <= tmp4_fu_425_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0))) then
tmp50_reg_1278 <= tmp50_fu_662_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0))) then
tmp57_reg_1308 <= tmp57_fu_699_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0))) then
tmp65_reg_1383 <= tmp65_fu_820_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0))) then
tmp66_reg_1353 <= tmp66_fu_778_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0))) then
tmp67_reg_1338 <= tmp67_fu_756_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0))) then
tmp74_reg_1368 <= tmp74_fu_793_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0))) then
tmp80_reg_1443 <= tmp80_fu_899_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0))) then
tmp81_reg_1413 <= tmp81_fu_857_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0))) then
tmp82_reg_1398 <= tmp82_fu_835_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0))) then
tmp89_reg_1428 <= tmp89_fu_872_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0))) then
tmp96_reg_1503 <= tmp96_fu_978_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0))) then
tmp97_reg_1473 <= tmp97_fu_936_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0))) then
tmp98_reg_1458 <= tmp98_fu_914_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0))) then
tmp_1_100_reg_1468 <= grp_fu_409_p2;
tmp_1_99_reg_1463 <= grp_fu_403_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0))) then
tmp_1_103_reg_1478 <= grp_fu_403_p2;
tmp_1_104_reg_1483 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0))) then
tmp_1_107_reg_1493 <= grp_fu_403_p2;
tmp_1_108_reg_1498 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0))) then
tmp_1_111_reg_1508 <= grp_fu_403_p2;
tmp_1_112_reg_1513 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0))) then
tmp_1_115_reg_1523 <= grp_fu_403_p2;
tmp_1_116_reg_1528 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0))) then
tmp_1_119_reg_1538 <= grp_fu_403_p2;
tmp_1_120_reg_1543 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_1_11_reg_1133 <= grp_fu_403_p2;
tmp_1_12_reg_1138 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
tmp_1_123_reg_1553 <= grp_fu_403_p2;
tmp_1_124_reg_1558 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_1_15_reg_1148 <= grp_fu_403_p2;
tmp_1_16_reg_1153 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_1_19_reg_1163 <= grp_fu_403_p2;
tmp_1_20_reg_1168 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_1_1_reg_1093 <= grp_fu_409_p2;
tmp_1_reg_1088 <= grp_fu_403_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
tmp_1_23_reg_1178 <= grp_fu_403_p2;
tmp_1_24_reg_1183 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
tmp_1_27_reg_1193 <= grp_fu_403_p2;
tmp_1_28_reg_1198 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0))) then
tmp_1_31_reg_1208 <= grp_fu_403_p2;
tmp_1_32_reg_1213 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0))) then
tmp_1_35_reg_1223 <= grp_fu_403_p2;
tmp_1_36_reg_1228 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0))) then
tmp_1_39_reg_1238 <= grp_fu_403_p2;
tmp_1_40_reg_1243 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0))) then
tmp_1_43_reg_1253 <= grp_fu_403_p2;
tmp_1_44_reg_1258 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0))) then
tmp_1_47_reg_1268 <= grp_fu_403_p2;
tmp_1_48_reg_1273 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_1_4_reg_1103 <= grp_fu_403_p2;
tmp_1_5_reg_1108 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0))) then
tmp_1_51_reg_1283 <= grp_fu_403_p2;
tmp_1_52_reg_1288 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0))) then
tmp_1_55_reg_1298 <= grp_fu_403_p2;
tmp_1_56_reg_1303 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0))) then
tmp_1_59_reg_1313 <= grp_fu_403_p2;
tmp_1_60_reg_1318 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0))) then
tmp_1_63_reg_1328 <= grp_fu_403_p2;
tmp_1_64_reg_1333 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0))) then
tmp_1_67_reg_1343 <= grp_fu_403_p2;
tmp_1_68_reg_1348 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0))) then
tmp_1_71_reg_1358 <= grp_fu_403_p2;
tmp_1_72_reg_1363 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0))) then
tmp_1_75_reg_1373 <= grp_fu_403_p2;
tmp_1_76_reg_1378 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0))) then
tmp_1_79_reg_1388 <= grp_fu_403_p2;
tmp_1_80_reg_1393 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0))) then
tmp_1_83_reg_1403 <= grp_fu_403_p2;
tmp_1_84_reg_1408 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0))) then
tmp_1_87_reg_1418 <= grp_fu_403_p2;
tmp_1_88_reg_1423 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
tmp_1_8_reg_1118 <= grp_fu_403_p2;
tmp_1_9_reg_1123 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0))) then
tmp_1_91_reg_1433 <= grp_fu_403_p2;
tmp_1_92_reg_1438 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0))) then
tmp_1_95_reg_1448 <= grp_fu_403_p2;
tmp_1_96_reg_1453 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0))) then
tmp_reg_1323 <= tmp_fu_740_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage63_flag00011011, ap_reset_idle_pp0, ap_idle_pp0_1to1, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage40_flag00011011, ap_block_pp0_stage41_flag00011011, ap_block_pp0_stage42_flag00011011, ap_block_pp0_stage43_flag00011011, ap_block_pp0_stage44_flag00011011, ap_block_pp0_stage45_flag00011011, ap_block_pp0_stage46_flag00011011, ap_block_pp0_stage47_flag00011011, ap_block_pp0_stage48_flag00011011, ap_block_pp0_stage49_flag00011011, ap_block_pp0_stage50_flag00011011, ap_block_pp0_stage51_flag00011011, ap_block_pp0_stage52_flag00011011, ap_block_pp0_stage53_flag00011011, ap_block_pp0_stage54_flag00011011, ap_block_pp0_stage55_flag00011011, ap_block_pp0_stage56_flag00011011, ap_block_pp0_stage57_flag00011011, ap_block_pp0_stage58_flag00011011, ap_block_pp0_stage59_flag00011011, ap_block_pp0_stage60_flag00011011, ap_block_pp0_stage61_flag00011011, ap_block_pp0_stage62_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_reset_idle_pp0 = ap_const_logic_0) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_1to1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when ap_ST_fsm_pp0_stage13 =>
if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
end if;
when ap_ST_fsm_pp0_stage14 =>
if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
end if;
when ap_ST_fsm_pp0_stage15 =>
if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
end if;
when ap_ST_fsm_pp0_stage16 =>
if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
end if;
when ap_ST_fsm_pp0_stage17 =>
if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
end if;
when ap_ST_fsm_pp0_stage18 =>
if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
end if;
when ap_ST_fsm_pp0_stage19 =>
if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
end if;
when ap_ST_fsm_pp0_stage20 =>
if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
end if;
when ap_ST_fsm_pp0_stage21 =>
if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
end if;
when ap_ST_fsm_pp0_stage22 =>
if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
end if;
when ap_ST_fsm_pp0_stage23 =>
if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
end if;
when ap_ST_fsm_pp0_stage24 =>
if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
end if;
when ap_ST_fsm_pp0_stage25 =>
if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
end if;
when ap_ST_fsm_pp0_stage26 =>
if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
end if;
when ap_ST_fsm_pp0_stage27 =>
if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
end if;
when ap_ST_fsm_pp0_stage28 =>
if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
end if;
when ap_ST_fsm_pp0_stage29 =>
if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
end if;
when ap_ST_fsm_pp0_stage30 =>
if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
end if;
when ap_ST_fsm_pp0_stage31 =>
if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
end if;
when ap_ST_fsm_pp0_stage32 =>
if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
end if;
when ap_ST_fsm_pp0_stage33 =>
if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
end if;
when ap_ST_fsm_pp0_stage34 =>
if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
end if;
when ap_ST_fsm_pp0_stage35 =>
if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
end if;
when ap_ST_fsm_pp0_stage36 =>
if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
end if;
when ap_ST_fsm_pp0_stage37 =>
if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
end if;
when ap_ST_fsm_pp0_stage38 =>
if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
end if;
when ap_ST_fsm_pp0_stage39 =>
if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
end if;
when ap_ST_fsm_pp0_stage40 =>
if ((ap_block_pp0_stage40_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
end if;
when ap_ST_fsm_pp0_stage41 =>
if ((ap_block_pp0_stage41_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
end if;
when ap_ST_fsm_pp0_stage42 =>
if ((ap_block_pp0_stage42_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
end if;
when ap_ST_fsm_pp0_stage43 =>
if ((ap_block_pp0_stage43_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
end if;
when ap_ST_fsm_pp0_stage44 =>
if ((ap_block_pp0_stage44_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
end if;
when ap_ST_fsm_pp0_stage45 =>
if ((ap_block_pp0_stage45_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
end if;
when ap_ST_fsm_pp0_stage46 =>
if ((ap_block_pp0_stage46_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
end if;
when ap_ST_fsm_pp0_stage47 =>
if ((ap_block_pp0_stage47_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
end if;
when ap_ST_fsm_pp0_stage48 =>
if ((ap_block_pp0_stage48_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
end if;
when ap_ST_fsm_pp0_stage49 =>
if ((ap_block_pp0_stage49_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
end if;
when ap_ST_fsm_pp0_stage50 =>
if ((ap_block_pp0_stage50_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
end if;
when ap_ST_fsm_pp0_stage51 =>
if ((ap_block_pp0_stage51_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
end if;
when ap_ST_fsm_pp0_stage52 =>
if ((ap_block_pp0_stage52_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
end if;
when ap_ST_fsm_pp0_stage53 =>
if ((ap_block_pp0_stage53_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
end if;
when ap_ST_fsm_pp0_stage54 =>
if ((ap_block_pp0_stage54_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
end if;
when ap_ST_fsm_pp0_stage55 =>
if ((ap_block_pp0_stage55_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
end if;
when ap_ST_fsm_pp0_stage56 =>
if ((ap_block_pp0_stage56_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
end if;
when ap_ST_fsm_pp0_stage57 =>
if ((ap_block_pp0_stage57_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
end if;
when ap_ST_fsm_pp0_stage58 =>
if ((ap_block_pp0_stage58_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
end if;
when ap_ST_fsm_pp0_stage59 =>
if ((ap_block_pp0_stage59_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
end if;
when ap_ST_fsm_pp0_stage60 =>
if ((ap_block_pp0_stage60_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
end if;
when ap_ST_fsm_pp0_stage61 =>
if ((ap_block_pp0_stage61_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
end if;
when ap_ST_fsm_pp0_stage62 =>
if ((ap_block_pp0_stage62_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
end if;
when ap_ST_fsm_pp0_stage63 =>
if ((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(10);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(13);
ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(14);
ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(15);
ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(16);
ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(17);
ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(18);
ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(19);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(20);
ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(21);
ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(22);
ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(23);
ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(24);
ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(25);
ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(26);
ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(27);
ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(28);
ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(29);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(30);
ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(31);
ap_CS_fsm_pp0_stage32 <= ap_CS_fsm(32);
ap_CS_fsm_pp0_stage33 <= ap_CS_fsm(33);
ap_CS_fsm_pp0_stage34 <= ap_CS_fsm(34);
ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(35);
ap_CS_fsm_pp0_stage36 <= ap_CS_fsm(36);
ap_CS_fsm_pp0_stage37 <= ap_CS_fsm(37);
ap_CS_fsm_pp0_stage38 <= ap_CS_fsm(38);
ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(39);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage40 <= ap_CS_fsm(40);
ap_CS_fsm_pp0_stage41 <= ap_CS_fsm(41);
ap_CS_fsm_pp0_stage42 <= ap_CS_fsm(42);
ap_CS_fsm_pp0_stage43 <= ap_CS_fsm(43);
ap_CS_fsm_pp0_stage44 <= ap_CS_fsm(44);
ap_CS_fsm_pp0_stage45 <= ap_CS_fsm(45);
ap_CS_fsm_pp0_stage46 <= ap_CS_fsm(46);
ap_CS_fsm_pp0_stage47 <= ap_CS_fsm(47);
ap_CS_fsm_pp0_stage48 <= ap_CS_fsm(48);
ap_CS_fsm_pp0_stage49 <= ap_CS_fsm(49);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage50 <= ap_CS_fsm(50);
ap_CS_fsm_pp0_stage51 <= ap_CS_fsm(51);
ap_CS_fsm_pp0_stage52 <= ap_CS_fsm(52);
ap_CS_fsm_pp0_stage53 <= ap_CS_fsm(53);
ap_CS_fsm_pp0_stage54 <= ap_CS_fsm(54);
ap_CS_fsm_pp0_stage55 <= ap_CS_fsm(55);
ap_CS_fsm_pp0_stage56 <= ap_CS_fsm(56);
ap_CS_fsm_pp0_stage57 <= ap_CS_fsm(57);
ap_CS_fsm_pp0_stage58 <= ap_CS_fsm(58);
ap_CS_fsm_pp0_stage59 <= ap_CS_fsm(59);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage60 <= ap_CS_fsm(60);
ap_CS_fsm_pp0_stage61 <= ap_CS_fsm(61);
ap_CS_fsm_pp0_stage62 <= ap_CS_fsm(62);
ap_CS_fsm_pp0_stage63 <= ap_CS_fsm(63);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(9);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0, ap_ce)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_ce = ap_const_logic_0) or ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)));
end process;
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage10_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage11_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage12_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage13_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage14_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage15_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage16_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage17_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage18_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage19_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage1_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage20_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage21_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage22_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage23_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage24_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage25_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage26_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage27_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage28_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage29_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage2_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage30_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage31_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage32_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage32_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage33_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage33_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage34_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage34_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage35_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage36_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage36_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage37_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage37_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage38_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage38_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage39_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage39_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage3_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage40_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage40_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage41_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage41_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage42_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage42_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage43_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage43_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage44_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage44_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage45_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage45_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage46_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage46_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage47_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage47_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage48_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage48_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage49_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage49_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage4_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage50_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage50_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage51_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage51_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage52_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage52_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage53_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage53_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage54_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage54_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage55_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage55_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage56_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage56_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage57_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage57_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage58_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage58_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage59_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage59_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage5_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage60_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage60_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage61_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage61_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage62_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage62_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage63_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage63_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage6_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage7_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage8_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage9_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_state10_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state20_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage32_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage33_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage34_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage35_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage36_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage37_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage38_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage39_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage40_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage41_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage42_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage43_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage44_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage45_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage46_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage47_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage48_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage49_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage50_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage51_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage52_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage53_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage54_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage55_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage56_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage57_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage58_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage59_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage60_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage61_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage62_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage63_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_ce, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0_reg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0 <= ap_start;
else
ap_enable_reg_pp0_iter0 <= ap_enable_reg_pp0_iter0_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to0_assign_proc : process(ap_enable_reg_pp0_iter0)
begin
if ((ap_const_logic_0 = ap_enable_reg_pp0_iter0)) then
ap_idle_pp0_0to0 <= ap_const_logic_1;
else
ap_idle_pp0_0to0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_1to1_assign_proc : process(ap_enable_reg_pp0_iter1)
begin
if ((ap_const_logic_0 = ap_enable_reg_pp0_iter1)) then
ap_idle_pp0_1to1 <= ap_const_logic_1;
else
ap_idle_pp0_1to1 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to0))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_return <= (tmp63_fu_1071_p2 or tmp_reg_1323);
contacts_V_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_78;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_76;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_74;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_72;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_70;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_68;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_66;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_64;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_62;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_60;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_58;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_56;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_54;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_52;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_50;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_48;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_46;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_44;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_42;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_40;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_38;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_36;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_34;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_32;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_30;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_28;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_26;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_24;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_22;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_20;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_18;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_16;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_14;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_12;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_10;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_8;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_0;
else
contacts_V_address0 <= "XXXXXXX";
end if;
else
contacts_V_address0 <= "XXXXXXX";
end if;
end process;
contacts_V_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_79;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_77;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_75;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_73;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_71;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_69;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_67;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_65;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_63;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_61;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_59;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_57;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_55;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_53;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_51;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_49;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_47;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_45;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_43;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_41;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_39;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_37;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_35;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_33;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_31;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_29;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_27;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_25;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_23;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_21;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_19;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_17;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_15;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_13;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_11;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_9;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1;
else
contacts_V_address1 <= "XXXXXXX";
end if;
else
contacts_V_address1 <= "XXXXXXX";
end if;
end process;
contacts_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then
contacts_V_ce0 <= ap_const_logic_1;
else
contacts_V_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_V_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then
contacts_V_ce1 <= ap_const_logic_1;
else
contacts_V_ce1 <= ap_const_logic_0;
end if;
end process;
grp_fu_403_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
grp_fu_403_p1 <= db_item_V_read_reg_1082;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_403_p1 <= ap_port_reg_db_item_V;
else
grp_fu_403_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_403_p2 <= "1" when (contacts_V_q0 = grp_fu_403_p1) else "0";
grp_fu_409_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
grp_fu_409_p1 <= db_item_V_read_reg_1082;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_409_p1 <= ap_port_reg_db_item_V;
else
grp_fu_409_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_409_p2 <= "1" when (contacts_V_q1 = grp_fu_409_p1) else "0";
tmp100_fu_908_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp101_fu_930_p2 <= (tmp103_fu_924_p2 or tmp102_fu_920_p2);
tmp102_fu_920_p2 <= (tmp_1_99_reg_1463 or tmp_1_100_reg_1468);
tmp103_fu_924_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp104_fu_973_p2 <= (tmp108_fu_967_p2 or tmp105_reg_1488);
tmp105_fu_951_p2 <= (tmp107_fu_945_p2 or tmp106_fu_941_p2);
tmp106_fu_941_p2 <= (tmp_1_103_reg_1478 or tmp_1_104_reg_1483);
tmp107_fu_945_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp108_fu_967_p2 <= (tmp110_fu_961_p2 or tmp109_fu_957_p2);
tmp109_fu_957_p2 <= (tmp_1_107_reg_1493 or tmp_1_108_reg_1498);
tmp10_fu_484_p2 <= (tmp14_fu_478_p2 or tmp11_reg_1128);
tmp110_fu_961_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp111_fu_1061_p2 <= (tmp119_fu_1056_p2 or tmp112_reg_1533);
tmp112_fu_1015_p2 <= (tmp116_fu_1009_p2 or tmp113_reg_1518);
tmp113_fu_993_p2 <= (tmp115_fu_987_p2 or tmp114_fu_983_p2);
tmp114_fu_983_p2 <= (tmp_1_111_reg_1508 or tmp_1_112_reg_1513);
tmp115_fu_987_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp116_fu_1009_p2 <= (tmp118_fu_1003_p2 or tmp117_fu_999_p2);
tmp117_fu_999_p2 <= (tmp_1_115_reg_1523 or tmp_1_116_reg_1528);
tmp118_fu_1003_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp119_fu_1056_p2 <= (tmp123_fu_1050_p2 or tmp120_reg_1548);
tmp11_fu_462_p2 <= (tmp13_fu_456_p2 or tmp12_fu_452_p2);
tmp120_fu_1030_p2 <= (tmp122_fu_1024_p2 or tmp121_fu_1020_p2);
tmp121_fu_1020_p2 <= (tmp_1_119_reg_1538 or tmp_1_120_reg_1543);
tmp122_fu_1024_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp123_fu_1050_p2 <= (tmp125_fu_1044_p2 or tmp124_fu_1040_p2);
tmp124_fu_1040_p2 <= (tmp_1_123_reg_1553 or tmp_1_124_reg_1558);
tmp125_fu_1044_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp12_fu_452_p2 <= (tmp_1_8_reg_1118 or tmp_1_9_reg_1123);
tmp13_fu_456_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp14_fu_478_p2 <= (tmp16_fu_472_p2 or tmp15_fu_468_p2);
tmp15_fu_468_p2 <= (tmp_1_11_reg_1133 or tmp_1_12_reg_1138);
tmp16_fu_472_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp17_fu_568_p2 <= (tmp25_fu_563_p2 or tmp18_reg_1173);
tmp18_fu_526_p2 <= (tmp22_fu_520_p2 or tmp19_reg_1158);
tmp19_fu_504_p2 <= (tmp21_fu_498_p2 or tmp20_fu_494_p2);
tmp1_fu_705_p2 <= (tmp17_reg_1203 or tmp2_reg_1143);
tmp20_fu_494_p2 <= (tmp_1_15_reg_1148 or tmp_1_16_reg_1153);
tmp21_fu_498_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp22_fu_520_p2 <= (tmp24_fu_514_p2 or tmp23_fu_510_p2);
tmp23_fu_510_p2 <= (tmp_1_19_reg_1163 or tmp_1_20_reg_1168);
tmp24_fu_514_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp25_fu_563_p2 <= (tmp29_fu_557_p2 or tmp26_reg_1188);
tmp26_fu_541_p2 <= (tmp28_fu_535_p2 or tmp27_fu_531_p2);
tmp27_fu_531_p2 <= (tmp_1_23_reg_1178 or tmp_1_24_reg_1183);
tmp28_fu_535_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp29_fu_557_p2 <= (tmp31_fu_551_p2 or tmp30_fu_547_p2);
tmp2_fu_489_p2 <= (tmp10_fu_484_p2 or tmp3_reg_1113);
tmp30_fu_547_p2 <= (tmp_1_27_reg_1193 or tmp_1_28_reg_1198);
tmp31_fu_551_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp32_fu_735_p2 <= (tmp48_fu_730_p2 or tmp33_reg_1263);
tmp33_fu_647_p2 <= (tmp41_fu_642_p2 or tmp34_reg_1233);
tmp34_fu_605_p2 <= (tmp38_fu_599_p2 or tmp35_reg_1218);
tmp35_fu_583_p2 <= (tmp37_fu_577_p2 or tmp36_fu_573_p2);
tmp36_fu_573_p2 <= (tmp_1_31_reg_1208 or tmp_1_32_reg_1213);
tmp37_fu_577_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp38_fu_599_p2 <= (tmp40_fu_593_p2 or tmp39_fu_589_p2);
tmp39_fu_589_p2 <= (tmp_1_35_reg_1223 or tmp_1_36_reg_1228);
tmp3_fu_447_p2 <= (tmp7_fu_441_p2 or tmp4_reg_1098);
tmp40_fu_593_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp41_fu_642_p2 <= (tmp45_fu_636_p2 or tmp42_reg_1248);
tmp42_fu_620_p2 <= (tmp44_fu_614_p2 or tmp43_fu_610_p2);
tmp43_fu_610_p2 <= (tmp_1_39_reg_1238 or tmp_1_40_reg_1243);
tmp44_fu_614_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp45_fu_636_p2 <= (tmp47_fu_630_p2 or tmp46_fu_626_p2);
tmp46_fu_626_p2 <= (tmp_1_43_reg_1253 or tmp_1_44_reg_1258);
tmp47_fu_630_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp48_fu_730_p2 <= (tmp56_fu_725_p2 or tmp49_reg_1293);
tmp49_fu_684_p2 <= (tmp53_fu_678_p2 or tmp50_reg_1278);
tmp4_fu_425_p2 <= (tmp6_fu_419_p2 or tmp5_fu_415_p2);
tmp50_fu_662_p2 <= (tmp52_fu_656_p2 or tmp51_fu_652_p2);
tmp51_fu_652_p2 <= (tmp_1_47_reg_1268 or tmp_1_48_reg_1273);
tmp52_fu_656_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp53_fu_678_p2 <= (tmp55_fu_672_p2 or tmp54_fu_668_p2);
tmp54_fu_668_p2 <= (tmp_1_51_reg_1283 or tmp_1_52_reg_1288);
tmp55_fu_672_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp56_fu_725_p2 <= (tmp60_fu_719_p2 or tmp57_reg_1308);
tmp57_fu_699_p2 <= (tmp59_fu_693_p2 or tmp58_fu_689_p2);
tmp58_fu_689_p2 <= (tmp_1_55_reg_1298 or tmp_1_56_reg_1303);
tmp59_fu_693_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp5_fu_415_p2 <= (tmp_1_reg_1088 or tmp_1_1_reg_1093);
tmp60_fu_719_p2 <= (tmp62_fu_713_p2 or tmp61_fu_709_p2);
tmp61_fu_709_p2 <= (tmp_1_59_reg_1313 or tmp_1_60_reg_1318);
tmp62_fu_713_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp63_fu_1071_p2 <= (tmp95_fu_1066_p2 or tmp64_fu_1036_p2);
tmp64_fu_1036_p2 <= (tmp80_reg_1443 or tmp65_reg_1383);
tmp65_fu_820_p2 <= (tmp73_fu_815_p2 or tmp66_reg_1353);
tmp66_fu_778_p2 <= (tmp70_fu_772_p2 or tmp67_reg_1338);
tmp67_fu_756_p2 <= (tmp69_fu_750_p2 or tmp68_fu_746_p2);
tmp68_fu_746_p2 <= (tmp_1_63_reg_1328 or tmp_1_64_reg_1333);
tmp69_fu_750_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp6_fu_419_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp70_fu_772_p2 <= (tmp72_fu_766_p2 or tmp71_fu_762_p2);
tmp71_fu_762_p2 <= (tmp_1_67_reg_1343 or tmp_1_68_reg_1348);
tmp72_fu_766_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp73_fu_815_p2 <= (tmp77_fu_809_p2 or tmp74_reg_1368);
tmp74_fu_793_p2 <= (tmp76_fu_787_p2 or tmp75_fu_783_p2);
tmp75_fu_783_p2 <= (tmp_1_71_reg_1358 or tmp_1_72_reg_1363);
tmp76_fu_787_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp77_fu_809_p2 <= (tmp79_fu_803_p2 or tmp78_fu_799_p2);
tmp78_fu_799_p2 <= (tmp_1_75_reg_1373 or tmp_1_76_reg_1378);
tmp79_fu_803_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp7_fu_441_p2 <= (tmp9_fu_435_p2 or tmp8_fu_431_p2);
tmp80_fu_899_p2 <= (tmp88_fu_894_p2 or tmp81_reg_1413);
tmp81_fu_857_p2 <= (tmp85_fu_851_p2 or tmp82_reg_1398);
tmp82_fu_835_p2 <= (tmp84_fu_829_p2 or tmp83_fu_825_p2);
tmp83_fu_825_p2 <= (tmp_1_79_reg_1388 or tmp_1_80_reg_1393);
tmp84_fu_829_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp85_fu_851_p2 <= (tmp87_fu_845_p2 or tmp86_fu_841_p2);
tmp86_fu_841_p2 <= (tmp_1_83_reg_1403 or tmp_1_84_reg_1408);
tmp87_fu_845_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp88_fu_894_p2 <= (tmp92_fu_888_p2 or tmp89_reg_1428);
tmp89_fu_872_p2 <= (tmp91_fu_866_p2 or tmp90_fu_862_p2);
tmp8_fu_431_p2 <= (tmp_1_4_reg_1103 or tmp_1_5_reg_1108);
tmp90_fu_862_p2 <= (tmp_1_87_reg_1418 or tmp_1_88_reg_1423);
tmp91_fu_866_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp92_fu_888_p2 <= (tmp94_fu_882_p2 or tmp93_fu_878_p2);
tmp93_fu_878_p2 <= (tmp_1_91_reg_1433 or tmp_1_92_reg_1438);
tmp94_fu_882_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp95_fu_1066_p2 <= (tmp111_fu_1061_p2 or tmp96_reg_1503);
tmp96_fu_978_p2 <= (tmp104_fu_973_p2 or tmp97_reg_1473);
tmp97_fu_936_p2 <= (tmp101_fu_930_p2 or tmp98_reg_1458);
tmp98_fu_914_p2 <= (tmp100_fu_908_p2 or tmp99_fu_904_p2);
tmp99_fu_904_p2 <= (tmp_1_95_reg_1448 or tmp_1_96_reg_1453);
tmp9_fu_435_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp_fu_740_p2 <= (tmp32_fu_735_p2 or tmp1_fu_705_p2);
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity match_db_contact is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_ce : IN STD_LOGIC;
db_item_V : IN STD_LOGIC_VECTOR (511 downto 0);
contacts_V_address0 : OUT STD_LOGIC_VECTOR (6 downto 0);
contacts_V_ce0 : OUT STD_LOGIC;
contacts_V_q0 : IN STD_LOGIC_VECTOR (511 downto 0);
contacts_V_address1 : OUT STD_LOGIC_VECTOR (6 downto 0);
contacts_V_ce1 : OUT STD_LOGIC;
contacts_V_q1 : IN STD_LOGIC_VECTOR (511 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end;
architecture behav of match_db_contact is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_fsm_pp0_stage13 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_fsm_pp0_stage14 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_fsm_pp0_stage15 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_fsm_pp0_stage16 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_fsm_pp0_stage17 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_fsm_pp0_stage18 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_fsm_pp0_stage19 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_fsm_pp0_stage20 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_fsm_pp0_stage21 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_fsm_pp0_stage22 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_fsm_pp0_stage23 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_fsm_pp0_stage24 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_fsm_pp0_stage25 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_fsm_pp0_stage26 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_fsm_pp0_stage27 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_fsm_pp0_stage28 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_fsm_pp0_stage29 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_fsm_pp0_stage30 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage31 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage32 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage33 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage34 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage35 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage36 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage37 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage38 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage39 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage40 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage41 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage42 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage43 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage44 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage45 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage46 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage47 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage48 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage49 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage50 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage51 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage52 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage53 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage54 : STD_LOGIC_VECTOR (63 downto 0) := "0000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage55 : STD_LOGIC_VECTOR (63 downto 0) := "0000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage56 : STD_LOGIC_VECTOR (63 downto 0) := "0000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage57 : STD_LOGIC_VECTOR (63 downto 0) := "0000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage58 : STD_LOGIC_VECTOR (63 downto 0) := "0000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage59 : STD_LOGIC_VECTOR (63 downto 0) := "0000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage60 : STD_LOGIC_VECTOR (63 downto 0) := "0001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage61 : STD_LOGIC_VECTOR (63 downto 0) := "0010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage62 : STD_LOGIC_VECTOR (63 downto 0) := "0100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_fsm_pp0_stage63 : STD_LOGIC_VECTOR (63 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
constant ap_const_lv32_1B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011011";
constant ap_const_lv32_1C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011100";
constant ap_const_lv32_1D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011101";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_21 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100001";
constant ap_const_lv32_22 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100010";
constant ap_const_lv32_23 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100011";
constant ap_const_lv32_24 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100100";
constant ap_const_lv32_25 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100101";
constant ap_const_lv32_26 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100110";
constant ap_const_lv32_27 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100111";
constant ap_const_lv32_28 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101000";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_2A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101010";
constant ap_const_lv32_2B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101011";
constant ap_const_lv32_2C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101100";
constant ap_const_lv32_2D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101101";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_2F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101111";
constant ap_const_lv32_30 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110000";
constant ap_const_lv32_31 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110001";
constant ap_const_lv32_32 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110010";
constant ap_const_lv32_33 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110011";
constant ap_const_lv32_34 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110100";
constant ap_const_lv32_35 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110101";
constant ap_const_lv32_36 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110110";
constant ap_const_lv32_37 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000110111";
constant ap_const_lv32_38 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111000";
constant ap_const_lv32_39 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111001";
constant ap_const_lv32_3A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111010";
constant ap_const_lv32_3B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111011";
constant ap_const_lv32_3C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111100";
constant ap_const_lv32_3D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111101";
constant ap_const_lv32_3E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111110";
constant ap_const_lv7_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
constant ap_const_lv7_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_const_lv7_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_const_lv7_3 : STD_LOGIC_VECTOR (6 downto 0) := "0000011";
constant ap_const_lv7_4 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_const_lv7_5 : STD_LOGIC_VECTOR (6 downto 0) := "0000101";
constant ap_const_lv7_6 : STD_LOGIC_VECTOR (6 downto 0) := "0000110";
constant ap_const_lv7_7 : STD_LOGIC_VECTOR (6 downto 0) := "0000111";
constant ap_const_lv7_8 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_const_lv7_9 : STD_LOGIC_VECTOR (6 downto 0) := "0001001";
constant ap_const_lv7_A : STD_LOGIC_VECTOR (6 downto 0) := "0001010";
constant ap_const_lv7_B : STD_LOGIC_VECTOR (6 downto 0) := "0001011";
constant ap_const_lv7_C : STD_LOGIC_VECTOR (6 downto 0) := "0001100";
constant ap_const_lv7_D : STD_LOGIC_VECTOR (6 downto 0) := "0001101";
constant ap_const_lv7_E : STD_LOGIC_VECTOR (6 downto 0) := "0001110";
constant ap_const_lv7_F : STD_LOGIC_VECTOR (6 downto 0) := "0001111";
constant ap_const_lv7_10 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_const_lv7_11 : STD_LOGIC_VECTOR (6 downto 0) := "0010001";
constant ap_const_lv7_12 : STD_LOGIC_VECTOR (6 downto 0) := "0010010";
constant ap_const_lv7_13 : STD_LOGIC_VECTOR (6 downto 0) := "0010011";
constant ap_const_lv7_14 : STD_LOGIC_VECTOR (6 downto 0) := "0010100";
constant ap_const_lv7_15 : STD_LOGIC_VECTOR (6 downto 0) := "0010101";
constant ap_const_lv7_16 : STD_LOGIC_VECTOR (6 downto 0) := "0010110";
constant ap_const_lv7_17 : STD_LOGIC_VECTOR (6 downto 0) := "0010111";
constant ap_const_lv7_18 : STD_LOGIC_VECTOR (6 downto 0) := "0011000";
constant ap_const_lv7_19 : STD_LOGIC_VECTOR (6 downto 0) := "0011001";
constant ap_const_lv7_1A : STD_LOGIC_VECTOR (6 downto 0) := "0011010";
constant ap_const_lv7_1B : STD_LOGIC_VECTOR (6 downto 0) := "0011011";
constant ap_const_lv7_1C : STD_LOGIC_VECTOR (6 downto 0) := "0011100";
constant ap_const_lv7_1D : STD_LOGIC_VECTOR (6 downto 0) := "0011101";
constant ap_const_lv7_1E : STD_LOGIC_VECTOR (6 downto 0) := "0011110";
constant ap_const_lv7_1F : STD_LOGIC_VECTOR (6 downto 0) := "0011111";
constant ap_const_lv7_20 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_const_lv7_21 : STD_LOGIC_VECTOR (6 downto 0) := "0100001";
constant ap_const_lv7_22 : STD_LOGIC_VECTOR (6 downto 0) := "0100010";
constant ap_const_lv7_23 : STD_LOGIC_VECTOR (6 downto 0) := "0100011";
constant ap_const_lv7_24 : STD_LOGIC_VECTOR (6 downto 0) := "0100100";
constant ap_const_lv7_25 : STD_LOGIC_VECTOR (6 downto 0) := "0100101";
constant ap_const_lv7_26 : STD_LOGIC_VECTOR (6 downto 0) := "0100110";
constant ap_const_lv7_27 : STD_LOGIC_VECTOR (6 downto 0) := "0100111";
constant ap_const_lv7_28 : STD_LOGIC_VECTOR (6 downto 0) := "0101000";
constant ap_const_lv7_29 : STD_LOGIC_VECTOR (6 downto 0) := "0101001";
constant ap_const_lv7_2A : STD_LOGIC_VECTOR (6 downto 0) := "0101010";
constant ap_const_lv7_2B : STD_LOGIC_VECTOR (6 downto 0) := "0101011";
constant ap_const_lv7_2C : STD_LOGIC_VECTOR (6 downto 0) := "0101100";
constant ap_const_lv7_2D : STD_LOGIC_VECTOR (6 downto 0) := "0101101";
constant ap_const_lv7_2E : STD_LOGIC_VECTOR (6 downto 0) := "0101110";
constant ap_const_lv7_2F : STD_LOGIC_VECTOR (6 downto 0) := "0101111";
constant ap_const_lv7_30 : STD_LOGIC_VECTOR (6 downto 0) := "0110000";
constant ap_const_lv7_31 : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv7_33 : STD_LOGIC_VECTOR (6 downto 0) := "0110011";
constant ap_const_lv7_34 : STD_LOGIC_VECTOR (6 downto 0) := "0110100";
constant ap_const_lv7_35 : STD_LOGIC_VECTOR (6 downto 0) := "0110101";
constant ap_const_lv7_36 : STD_LOGIC_VECTOR (6 downto 0) := "0110110";
constant ap_const_lv7_37 : STD_LOGIC_VECTOR (6 downto 0) := "0110111";
constant ap_const_lv7_38 : STD_LOGIC_VECTOR (6 downto 0) := "0111000";
constant ap_const_lv7_39 : STD_LOGIC_VECTOR (6 downto 0) := "0111001";
constant ap_const_lv7_3A : STD_LOGIC_VECTOR (6 downto 0) := "0111010";
constant ap_const_lv7_3B : STD_LOGIC_VECTOR (6 downto 0) := "0111011";
constant ap_const_lv7_3C : STD_LOGIC_VECTOR (6 downto 0) := "0111100";
constant ap_const_lv7_3D : STD_LOGIC_VECTOR (6 downto 0) := "0111101";
constant ap_const_lv7_3E : STD_LOGIC_VECTOR (6 downto 0) := "0111110";
constant ap_const_lv7_3F : STD_LOGIC_VECTOR (6 downto 0) := "0111111";
constant ap_const_lv7_40 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv7_41 : STD_LOGIC_VECTOR (6 downto 0) := "1000001";
constant ap_const_lv7_42 : STD_LOGIC_VECTOR (6 downto 0) := "1000010";
constant ap_const_lv7_43 : STD_LOGIC_VECTOR (6 downto 0) := "1000011";
constant ap_const_lv7_44 : STD_LOGIC_VECTOR (6 downto 0) := "1000100";
constant ap_const_lv7_45 : STD_LOGIC_VECTOR (6 downto 0) := "1000101";
constant ap_const_lv7_46 : STD_LOGIC_VECTOR (6 downto 0) := "1000110";
constant ap_const_lv7_47 : STD_LOGIC_VECTOR (6 downto 0) := "1000111";
constant ap_const_lv7_48 : STD_LOGIC_VECTOR (6 downto 0) := "1001000";
constant ap_const_lv7_49 : STD_LOGIC_VECTOR (6 downto 0) := "1001001";
constant ap_const_lv7_4A : STD_LOGIC_VECTOR (6 downto 0) := "1001010";
constant ap_const_lv7_4B : STD_LOGIC_VECTOR (6 downto 0) := "1001011";
constant ap_const_lv7_4C : STD_LOGIC_VECTOR (6 downto 0) := "1001100";
constant ap_const_lv7_4D : STD_LOGIC_VECTOR (6 downto 0) := "1001101";
constant ap_const_lv7_4E : STD_LOGIC_VECTOR (6 downto 0) := "1001110";
constant ap_const_lv7_4F : STD_LOGIC_VECTOR (6 downto 0) := "1001111";
constant ap_const_lv7_50 : STD_LOGIC_VECTOR (6 downto 0) := "1010000";
constant ap_const_lv7_51 : STD_LOGIC_VECTOR (6 downto 0) := "1010001";
constant ap_const_lv7_52 : STD_LOGIC_VECTOR (6 downto 0) := "1010010";
constant ap_const_lv7_53 : STD_LOGIC_VECTOR (6 downto 0) := "1010011";
constant ap_const_lv7_54 : STD_LOGIC_VECTOR (6 downto 0) := "1010100";
constant ap_const_lv7_55 : STD_LOGIC_VECTOR (6 downto 0) := "1010101";
constant ap_const_lv7_56 : STD_LOGIC_VECTOR (6 downto 0) := "1010110";
constant ap_const_lv7_57 : STD_LOGIC_VECTOR (6 downto 0) := "1010111";
constant ap_const_lv7_58 : STD_LOGIC_VECTOR (6 downto 0) := "1011000";
constant ap_const_lv7_59 : STD_LOGIC_VECTOR (6 downto 0) := "1011001";
constant ap_const_lv7_5A : STD_LOGIC_VECTOR (6 downto 0) := "1011010";
constant ap_const_lv7_5B : STD_LOGIC_VECTOR (6 downto 0) := "1011011";
constant ap_const_lv7_5C : STD_LOGIC_VECTOR (6 downto 0) := "1011100";
constant ap_const_lv7_5D : STD_LOGIC_VECTOR (6 downto 0) := "1011101";
constant ap_const_lv7_5E : STD_LOGIC_VECTOR (6 downto 0) := "1011110";
constant ap_const_lv7_5F : STD_LOGIC_VECTOR (6 downto 0) := "1011111";
constant ap_const_lv7_60 : STD_LOGIC_VECTOR (6 downto 0) := "1100000";
constant ap_const_lv7_61 : STD_LOGIC_VECTOR (6 downto 0) := "1100001";
constant ap_const_lv7_62 : STD_LOGIC_VECTOR (6 downto 0) := "1100010";
constant ap_const_lv7_63 : STD_LOGIC_VECTOR (6 downto 0) := "1100011";
constant ap_const_lv7_64 : STD_LOGIC_VECTOR (6 downto 0) := "1100100";
constant ap_const_lv7_65 : STD_LOGIC_VECTOR (6 downto 0) := "1100101";
constant ap_const_lv7_66 : STD_LOGIC_VECTOR (6 downto 0) := "1100110";
constant ap_const_lv7_67 : STD_LOGIC_VECTOR (6 downto 0) := "1100111";
constant ap_const_lv7_68 : STD_LOGIC_VECTOR (6 downto 0) := "1101000";
constant ap_const_lv7_69 : STD_LOGIC_VECTOR (6 downto 0) := "1101001";
constant ap_const_lv7_6A : STD_LOGIC_VECTOR (6 downto 0) := "1101010";
constant ap_const_lv7_6B : STD_LOGIC_VECTOR (6 downto 0) := "1101011";
constant ap_const_lv7_6C : STD_LOGIC_VECTOR (6 downto 0) := "1101100";
constant ap_const_lv7_6D : STD_LOGIC_VECTOR (6 downto 0) := "1101101";
constant ap_const_lv7_6E : STD_LOGIC_VECTOR (6 downto 0) := "1101110";
constant ap_const_lv7_6F : STD_LOGIC_VECTOR (6 downto 0) := "1101111";
constant ap_const_lv7_70 : STD_LOGIC_VECTOR (6 downto 0) := "1110000";
constant ap_const_lv7_71 : STD_LOGIC_VECTOR (6 downto 0) := "1110001";
constant ap_const_lv7_72 : STD_LOGIC_VECTOR (6 downto 0) := "1110010";
constant ap_const_lv7_73 : STD_LOGIC_VECTOR (6 downto 0) := "1110011";
constant ap_const_lv7_74 : STD_LOGIC_VECTOR (6 downto 0) := "1110100";
constant ap_const_lv7_75 : STD_LOGIC_VECTOR (6 downto 0) := "1110101";
constant ap_const_lv7_76 : STD_LOGIC_VECTOR (6 downto 0) := "1110110";
constant ap_const_lv7_77 : STD_LOGIC_VECTOR (6 downto 0) := "1110111";
constant ap_const_lv7_78 : STD_LOGIC_VECTOR (6 downto 0) := "1111000";
constant ap_const_lv7_79 : STD_LOGIC_VECTOR (6 downto 0) := "1111001";
constant ap_const_lv7_7A : STD_LOGIC_VECTOR (6 downto 0) := "1111010";
constant ap_const_lv7_7B : STD_LOGIC_VECTOR (6 downto 0) := "1111011";
constant ap_const_lv7_7C : STD_LOGIC_VECTOR (6 downto 0) := "1111100";
constant ap_const_lv7_7D : STD_LOGIC_VECTOR (6 downto 0) := "1111101";
constant ap_const_lv7_7E : STD_LOGIC_VECTOR (6 downto 0) := "1111110";
constant ap_const_lv7_7F : STD_LOGIC_VECTOR (6 downto 0) := "1111111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_CS_fsm_pp0_stage63 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage63 : signal is "none";
signal ap_block_state64_pp0_stage63_iter0 : BOOLEAN;
signal ap_block_pp0_stage63_flag00011001 : BOOLEAN;
signal db_item_V_read_reg_1082 : STD_LOGIC_VECTOR (511 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state2_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal grp_fu_403_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1088 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_409_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_1_reg_1093 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_fu_425_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp4_reg_1098 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state3_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal tmp_1_4_reg_1103 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state4_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal tmp_1_5_reg_1108 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_fu_447_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp3_reg_1113 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state5_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal tmp_1_8_reg_1118 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state6_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal tmp_1_9_reg_1123 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_fu_462_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp11_reg_1128 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state7_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal tmp_1_11_reg_1133 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state8_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal tmp_1_12_reg_1138 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_fu_489_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp2_reg_1143 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state9_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal tmp_1_15_reg_1148 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state10_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal tmp_1_16_reg_1153 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_fu_504_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp19_reg_1158 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state11_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal tmp_1_19_reg_1163 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state12_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal tmp_1_20_reg_1168 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_fu_526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp18_reg_1173 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_state13_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal tmp_1_23_reg_1178 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage13 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage13 : signal is "none";
signal ap_block_state14_pp0_stage13_iter0 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011001 : BOOLEAN;
signal tmp_1_24_reg_1183 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_fu_541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp26_reg_1188 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage14 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage14 : signal is "none";
signal ap_block_state15_pp0_stage14_iter0 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011001 : BOOLEAN;
signal tmp_1_27_reg_1193 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage15 : signal is "none";
signal ap_block_state16_pp0_stage15_iter0 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011001 : BOOLEAN;
signal tmp_1_28_reg_1198 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_fu_568_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp17_reg_1203 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage16 : signal is "none";
signal ap_block_state17_pp0_stage16_iter0 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011001 : BOOLEAN;
signal tmp_1_31_reg_1208 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage17 : signal is "none";
signal ap_block_state18_pp0_stage17_iter0 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011001 : BOOLEAN;
signal tmp_1_32_reg_1213 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp35_fu_583_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp35_reg_1218 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage18 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage18 : signal is "none";
signal ap_block_state19_pp0_stage18_iter0 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011001 : BOOLEAN;
signal tmp_1_35_reg_1223 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage19 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage19 : signal is "none";
signal ap_block_state20_pp0_stage19_iter0 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011001 : BOOLEAN;
signal tmp_1_36_reg_1228 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp34_fu_605_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp34_reg_1233 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage20 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage20 : signal is "none";
signal ap_block_state21_pp0_stage20_iter0 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011001 : BOOLEAN;
signal tmp_1_39_reg_1238 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage21 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage21 : signal is "none";
signal ap_block_state22_pp0_stage21_iter0 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011001 : BOOLEAN;
signal tmp_1_40_reg_1243 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp42_fu_620_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp42_reg_1248 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage22 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage22 : signal is "none";
signal ap_block_state23_pp0_stage22_iter0 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011001 : BOOLEAN;
signal tmp_1_43_reg_1253 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage23 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage23 : signal is "none";
signal ap_block_state24_pp0_stage23_iter0 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011001 : BOOLEAN;
signal tmp_1_44_reg_1258 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp33_fu_647_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp33_reg_1263 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage24 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage24 : signal is "none";
signal ap_block_state25_pp0_stage24_iter0 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011001 : BOOLEAN;
signal tmp_1_47_reg_1268 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage25 : signal is "none";
signal ap_block_state26_pp0_stage25_iter0 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011001 : BOOLEAN;
signal tmp_1_48_reg_1273 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp50_fu_662_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp50_reg_1278 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage26 : signal is "none";
signal ap_block_state27_pp0_stage26_iter0 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011001 : BOOLEAN;
signal tmp_1_51_reg_1283 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage27 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage27 : signal is "none";
signal ap_block_state28_pp0_stage27_iter0 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011001 : BOOLEAN;
signal tmp_1_52_reg_1288 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp49_fu_684_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp49_reg_1293 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage28 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage28 : signal is "none";
signal ap_block_state29_pp0_stage28_iter0 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011001 : BOOLEAN;
signal tmp_1_55_reg_1298 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage29 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage29 : signal is "none";
signal ap_block_state30_pp0_stage29_iter0 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011001 : BOOLEAN;
signal tmp_1_56_reg_1303 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp57_fu_699_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp57_reg_1308 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage30 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage30 : signal is "none";
signal ap_block_state31_pp0_stage30_iter0 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011001 : BOOLEAN;
signal tmp_1_59_reg_1313 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage31 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage31 : signal is "none";
signal ap_block_state32_pp0_stage31_iter0 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011001 : BOOLEAN;
signal tmp_1_60_reg_1318 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_740_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_1323 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage32 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage32 : signal is "none";
signal ap_block_state33_pp0_stage32_iter0 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011001 : BOOLEAN;
signal tmp_1_63_reg_1328 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage33 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage33 : signal is "none";
signal ap_block_state34_pp0_stage33_iter0 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011001 : BOOLEAN;
signal tmp_1_64_reg_1333 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp67_fu_756_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp67_reg_1338 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage34 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage34 : signal is "none";
signal ap_block_state35_pp0_stage34_iter0 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011001 : BOOLEAN;
signal tmp_1_67_reg_1343 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage35 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage35 : signal is "none";
signal ap_block_state36_pp0_stage35_iter0 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011001 : BOOLEAN;
signal tmp_1_68_reg_1348 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp66_fu_778_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp66_reg_1353 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage36 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage36 : signal is "none";
signal ap_block_state37_pp0_stage36_iter0 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011001 : BOOLEAN;
signal tmp_1_71_reg_1358 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage37 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage37 : signal is "none";
signal ap_block_state38_pp0_stage37_iter0 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011001 : BOOLEAN;
signal tmp_1_72_reg_1363 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp74_fu_793_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp74_reg_1368 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage38 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage38 : signal is "none";
signal ap_block_state39_pp0_stage38_iter0 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011001 : BOOLEAN;
signal tmp_1_75_reg_1373 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage39 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage39 : signal is "none";
signal ap_block_state40_pp0_stage39_iter0 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011001 : BOOLEAN;
signal tmp_1_76_reg_1378 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp65_fu_820_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp65_reg_1383 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage40 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage40 : signal is "none";
signal ap_block_state41_pp0_stage40_iter0 : BOOLEAN;
signal ap_block_pp0_stage40_flag00011001 : BOOLEAN;
signal tmp_1_79_reg_1388 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage41 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage41 : signal is "none";
signal ap_block_state42_pp0_stage41_iter0 : BOOLEAN;
signal ap_block_pp0_stage41_flag00011001 : BOOLEAN;
signal tmp_1_80_reg_1393 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp82_fu_835_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp82_reg_1398 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage42 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage42 : signal is "none";
signal ap_block_state43_pp0_stage42_iter0 : BOOLEAN;
signal ap_block_pp0_stage42_flag00011001 : BOOLEAN;
signal tmp_1_83_reg_1403 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage43 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage43 : signal is "none";
signal ap_block_state44_pp0_stage43_iter0 : BOOLEAN;
signal ap_block_pp0_stage43_flag00011001 : BOOLEAN;
signal tmp_1_84_reg_1408 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp81_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp81_reg_1413 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage44 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage44 : signal is "none";
signal ap_block_state45_pp0_stage44_iter0 : BOOLEAN;
signal ap_block_pp0_stage44_flag00011001 : BOOLEAN;
signal tmp_1_87_reg_1418 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage45 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage45 : signal is "none";
signal ap_block_state46_pp0_stage45_iter0 : BOOLEAN;
signal ap_block_pp0_stage45_flag00011001 : BOOLEAN;
signal tmp_1_88_reg_1423 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp89_fu_872_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp89_reg_1428 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage46 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage46 : signal is "none";
signal ap_block_state47_pp0_stage46_iter0 : BOOLEAN;
signal ap_block_pp0_stage46_flag00011001 : BOOLEAN;
signal tmp_1_91_reg_1433 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage47 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage47 : signal is "none";
signal ap_block_state48_pp0_stage47_iter0 : BOOLEAN;
signal ap_block_pp0_stage47_flag00011001 : BOOLEAN;
signal tmp_1_92_reg_1438 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp80_fu_899_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp80_reg_1443 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage48 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage48 : signal is "none";
signal ap_block_state49_pp0_stage48_iter0 : BOOLEAN;
signal ap_block_pp0_stage48_flag00011001 : BOOLEAN;
signal tmp_1_95_reg_1448 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage49 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage49 : signal is "none";
signal ap_block_state50_pp0_stage49_iter0 : BOOLEAN;
signal ap_block_pp0_stage49_flag00011001 : BOOLEAN;
signal tmp_1_96_reg_1453 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp98_fu_914_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp98_reg_1458 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage50 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage50 : signal is "none";
signal ap_block_state51_pp0_stage50_iter0 : BOOLEAN;
signal ap_block_pp0_stage50_flag00011001 : BOOLEAN;
signal tmp_1_99_reg_1463 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage51 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage51 : signal is "none";
signal ap_block_state52_pp0_stage51_iter0 : BOOLEAN;
signal ap_block_pp0_stage51_flag00011001 : BOOLEAN;
signal tmp_1_100_reg_1468 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp97_fu_936_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp97_reg_1473 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage52 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage52 : signal is "none";
signal ap_block_state53_pp0_stage52_iter0 : BOOLEAN;
signal ap_block_pp0_stage52_flag00011001 : BOOLEAN;
signal tmp_1_103_reg_1478 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage53 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage53 : signal is "none";
signal ap_block_state54_pp0_stage53_iter0 : BOOLEAN;
signal ap_block_pp0_stage53_flag00011001 : BOOLEAN;
signal tmp_1_104_reg_1483 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp105_fu_951_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp105_reg_1488 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage54 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage54 : signal is "none";
signal ap_block_state55_pp0_stage54_iter0 : BOOLEAN;
signal ap_block_pp0_stage54_flag00011001 : BOOLEAN;
signal tmp_1_107_reg_1493 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage55 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage55 : signal is "none";
signal ap_block_state56_pp0_stage55_iter0 : BOOLEAN;
signal ap_block_pp0_stage55_flag00011001 : BOOLEAN;
signal tmp_1_108_reg_1498 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp96_fu_978_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp96_reg_1503 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage56 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage56 : signal is "none";
signal ap_block_state57_pp0_stage56_iter0 : BOOLEAN;
signal ap_block_pp0_stage56_flag00011001 : BOOLEAN;
signal tmp_1_111_reg_1508 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage57 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage57 : signal is "none";
signal ap_block_state58_pp0_stage57_iter0 : BOOLEAN;
signal ap_block_pp0_stage57_flag00011001 : BOOLEAN;
signal tmp_1_112_reg_1513 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp113_fu_993_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp113_reg_1518 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage58 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage58 : signal is "none";
signal ap_block_state59_pp0_stage58_iter0 : BOOLEAN;
signal ap_block_pp0_stage58_flag00011001 : BOOLEAN;
signal tmp_1_115_reg_1523 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage59 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage59 : signal is "none";
signal ap_block_state60_pp0_stage59_iter0 : BOOLEAN;
signal ap_block_pp0_stage59_flag00011001 : BOOLEAN;
signal tmp_1_116_reg_1528 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp112_fu_1015_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp112_reg_1533 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage60 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage60 : signal is "none";
signal ap_block_state61_pp0_stage60_iter0 : BOOLEAN;
signal ap_block_pp0_stage60_flag00011001 : BOOLEAN;
signal tmp_1_119_reg_1538 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage61 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage61 : signal is "none";
signal ap_block_state62_pp0_stage61_iter0 : BOOLEAN;
signal ap_block_pp0_stage61_flag00011001 : BOOLEAN;
signal tmp_1_120_reg_1543 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp120_fu_1030_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp120_reg_1548 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_pp0_stage62 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage62 : signal is "none";
signal ap_block_state63_pp0_stage62_iter0 : BOOLEAN;
signal ap_block_pp0_stage62_flag00011001 : BOOLEAN;
signal tmp_1_123_reg_1553 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_124_reg_1558 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_enable_reg_pp0_iter0_reg : STD_LOGIC := '0';
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state65_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage63_flag00011011 : BOOLEAN;
signal ap_port_reg_db_item_V : STD_LOGIC_VECTOR (511 downto 0);
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage13_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage14_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage15_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage16_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage17_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage18_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage19_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage20_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage21_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage22_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage23_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage24_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage25_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage26_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage27_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage28_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage29_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage30_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage31_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage32_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage33_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage34_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage35_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage36_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage37_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage38_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage39_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage40_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage41_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage42_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage43_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage44_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage45_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage46_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage47_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage48_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage49_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage50_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage51_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage52_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage53_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage54_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage55_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage56_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage57_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage58_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage59_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage60_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage61_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage62_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage63_flag00000000 : BOOLEAN;
signal grp_fu_403_p1 : STD_LOGIC_VECTOR (511 downto 0);
signal grp_fu_409_p1 : STD_LOGIC_VECTOR (511 downto 0);
signal tmp6_fu_419_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp5_fu_415_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp9_fu_435_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp8_fu_431_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp7_fu_441_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp13_fu_456_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp12_fu_452_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp16_fu_472_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp15_fu_468_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp14_fu_478_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp10_fu_484_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp21_fu_498_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp20_fu_494_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp24_fu_514_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp23_fu_510_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp22_fu_520_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp28_fu_535_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp27_fu_531_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp31_fu_551_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp30_fu_547_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp29_fu_557_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp25_fu_563_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp37_fu_577_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp36_fu_573_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp40_fu_593_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp39_fu_589_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp38_fu_599_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp44_fu_614_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp43_fu_610_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp47_fu_630_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp46_fu_626_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp45_fu_636_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp41_fu_642_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp52_fu_656_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp51_fu_652_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp55_fu_672_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp54_fu_668_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp53_fu_678_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp59_fu_693_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp58_fu_689_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp62_fu_713_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp61_fu_709_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp60_fu_719_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp56_fu_725_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp48_fu_730_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp32_fu_735_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp1_fu_705_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp69_fu_750_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp68_fu_746_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp72_fu_766_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp71_fu_762_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp70_fu_772_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp76_fu_787_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp75_fu_783_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp79_fu_803_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp78_fu_799_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp77_fu_809_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp73_fu_815_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp84_fu_829_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp83_fu_825_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp87_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp86_fu_841_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp85_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp91_fu_866_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp90_fu_862_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp94_fu_882_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp93_fu_878_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp92_fu_888_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp88_fu_894_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp100_fu_908_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp99_fu_904_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp103_fu_924_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp102_fu_920_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp101_fu_930_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp107_fu_945_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp106_fu_941_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp110_fu_961_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp109_fu_957_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp108_fu_967_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp104_fu_973_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp115_fu_987_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp114_fu_983_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp118_fu_1003_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp117_fu_999_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp116_fu_1009_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp122_fu_1024_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp121_fu_1020_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp125_fu_1044_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp124_fu_1040_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp123_fu_1050_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp119_fu_1056_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp111_fu_1061_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp95_fu_1066_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp64_fu_1036_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp63_fu_1071_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (63 downto 0);
signal ap_idle_pp0_0to0 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_idle_pp0_1to1 : STD_LOGIC;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage13_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage14_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage15_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage16_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage17_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage18_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage19_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage20_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage21_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage22_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage23_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage24_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage25_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage26_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage27_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage28_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage29_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage30_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage31_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage32_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage33_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage34_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage35_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage36_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage37_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage38_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage39_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage40_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage41_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage42_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage43_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage44_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage45_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage46_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage47_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage48_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage49_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage50_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage51_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage52_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage53_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage54_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage55_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage56_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage57_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage58_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage59_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage60_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage61_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage62_flag00011011 : BOOLEAN;
signal ap_enable_pp0 : STD_LOGIC;
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0_reg <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter0 = ap_const_logic_0))) then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
ap_port_reg_db_item_V <= db_item_V;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
db_item_V_read_reg_1082 <= ap_port_reg_db_item_V;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0))) then
tmp105_reg_1488 <= tmp105_fu_951_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0))) then
tmp112_reg_1533 <= tmp112_fu_1015_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0))) then
tmp113_reg_1518 <= tmp113_fu_993_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp11_reg_1128 <= tmp11_fu_462_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0))) then
tmp120_reg_1548 <= tmp120_fu_1030_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0))) then
tmp17_reg_1203 <= tmp17_fu_568_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
tmp18_reg_1173 <= tmp18_fu_526_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp19_reg_1158 <= tmp19_fu_504_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0))) then
tmp26_reg_1188 <= tmp26_fu_541_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp2_reg_1143 <= tmp2_fu_489_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0))) then
tmp33_reg_1263 <= tmp33_fu_647_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0))) then
tmp34_reg_1233 <= tmp34_fu_605_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0))) then
tmp35_reg_1218 <= tmp35_fu_583_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp3_reg_1113 <= tmp3_fu_447_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0))) then
tmp42_reg_1248 <= tmp42_fu_620_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0))) then
tmp49_reg_1293 <= tmp49_fu_684_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp4_reg_1098 <= tmp4_fu_425_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0))) then
tmp50_reg_1278 <= tmp50_fu_662_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0))) then
tmp57_reg_1308 <= tmp57_fu_699_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0))) then
tmp65_reg_1383 <= tmp65_fu_820_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0))) then
tmp66_reg_1353 <= tmp66_fu_778_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0))) then
tmp67_reg_1338 <= tmp67_fu_756_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0))) then
tmp74_reg_1368 <= tmp74_fu_793_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0))) then
tmp80_reg_1443 <= tmp80_fu_899_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0))) then
tmp81_reg_1413 <= tmp81_fu_857_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0))) then
tmp82_reg_1398 <= tmp82_fu_835_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0))) then
tmp89_reg_1428 <= tmp89_fu_872_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0))) then
tmp96_reg_1503 <= tmp96_fu_978_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0))) then
tmp97_reg_1473 <= tmp97_fu_936_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0))) then
tmp98_reg_1458 <= tmp98_fu_914_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0))) then
tmp_1_100_reg_1468 <= grp_fu_409_p2;
tmp_1_99_reg_1463 <= grp_fu_403_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0))) then
tmp_1_103_reg_1478 <= grp_fu_403_p2;
tmp_1_104_reg_1483 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0))) then
tmp_1_107_reg_1493 <= grp_fu_403_p2;
tmp_1_108_reg_1498 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0))) then
tmp_1_111_reg_1508 <= grp_fu_403_p2;
tmp_1_112_reg_1513 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0))) then
tmp_1_115_reg_1523 <= grp_fu_403_p2;
tmp_1_116_reg_1528 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0))) then
tmp_1_119_reg_1538 <= grp_fu_403_p2;
tmp_1_120_reg_1543 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_1_11_reg_1133 <= grp_fu_403_p2;
tmp_1_12_reg_1138 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
tmp_1_123_reg_1553 <= grp_fu_403_p2;
tmp_1_124_reg_1558 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_1_15_reg_1148 <= grp_fu_403_p2;
tmp_1_16_reg_1153 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_1_19_reg_1163 <= grp_fu_403_p2;
tmp_1_20_reg_1168 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_1_1_reg_1093 <= grp_fu_409_p2;
tmp_1_reg_1088 <= grp_fu_403_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0))) then
tmp_1_23_reg_1178 <= grp_fu_403_p2;
tmp_1_24_reg_1183 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0))) then
tmp_1_27_reg_1193 <= grp_fu_403_p2;
tmp_1_28_reg_1198 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0))) then
tmp_1_31_reg_1208 <= grp_fu_403_p2;
tmp_1_32_reg_1213 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0))) then
tmp_1_35_reg_1223 <= grp_fu_403_p2;
tmp_1_36_reg_1228 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0))) then
tmp_1_39_reg_1238 <= grp_fu_403_p2;
tmp_1_40_reg_1243 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0))) then
tmp_1_43_reg_1253 <= grp_fu_403_p2;
tmp_1_44_reg_1258 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0))) then
tmp_1_47_reg_1268 <= grp_fu_403_p2;
tmp_1_48_reg_1273 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_1_4_reg_1103 <= grp_fu_403_p2;
tmp_1_5_reg_1108 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0))) then
tmp_1_51_reg_1283 <= grp_fu_403_p2;
tmp_1_52_reg_1288 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0))) then
tmp_1_55_reg_1298 <= grp_fu_403_p2;
tmp_1_56_reg_1303 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0))) then
tmp_1_59_reg_1313 <= grp_fu_403_p2;
tmp_1_60_reg_1318 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0))) then
tmp_1_63_reg_1328 <= grp_fu_403_p2;
tmp_1_64_reg_1333 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0))) then
tmp_1_67_reg_1343 <= grp_fu_403_p2;
tmp_1_68_reg_1348 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0))) then
tmp_1_71_reg_1358 <= grp_fu_403_p2;
tmp_1_72_reg_1363 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0))) then
tmp_1_75_reg_1373 <= grp_fu_403_p2;
tmp_1_76_reg_1378 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0))) then
tmp_1_79_reg_1388 <= grp_fu_403_p2;
tmp_1_80_reg_1393 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0))) then
tmp_1_83_reg_1403 <= grp_fu_403_p2;
tmp_1_84_reg_1408 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0))) then
tmp_1_87_reg_1418 <= grp_fu_403_p2;
tmp_1_88_reg_1423 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
tmp_1_8_reg_1118 <= grp_fu_403_p2;
tmp_1_9_reg_1123 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0))) then
tmp_1_91_reg_1433 <= grp_fu_403_p2;
tmp_1_92_reg_1438 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0))) then
tmp_1_95_reg_1448 <= grp_fu_403_p2;
tmp_1_96_reg_1453 <= grp_fu_409_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0))) then
tmp_reg_1323 <= tmp_fu_740_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_block_pp0_stage0_flag00011011, ap_block_pp0_stage63_flag00011011, ap_reset_idle_pp0, ap_idle_pp0_1to1, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage13_flag00011011, ap_block_pp0_stage14_flag00011011, ap_block_pp0_stage15_flag00011011, ap_block_pp0_stage16_flag00011011, ap_block_pp0_stage17_flag00011011, ap_block_pp0_stage18_flag00011011, ap_block_pp0_stage19_flag00011011, ap_block_pp0_stage20_flag00011011, ap_block_pp0_stage21_flag00011011, ap_block_pp0_stage22_flag00011011, ap_block_pp0_stage23_flag00011011, ap_block_pp0_stage24_flag00011011, ap_block_pp0_stage25_flag00011011, ap_block_pp0_stage26_flag00011011, ap_block_pp0_stage27_flag00011011, ap_block_pp0_stage28_flag00011011, ap_block_pp0_stage29_flag00011011, ap_block_pp0_stage30_flag00011011, ap_block_pp0_stage31_flag00011011, ap_block_pp0_stage32_flag00011011, ap_block_pp0_stage33_flag00011011, ap_block_pp0_stage34_flag00011011, ap_block_pp0_stage35_flag00011011, ap_block_pp0_stage36_flag00011011, ap_block_pp0_stage37_flag00011011, ap_block_pp0_stage38_flag00011011, ap_block_pp0_stage39_flag00011011, ap_block_pp0_stage40_flag00011011, ap_block_pp0_stage41_flag00011011, ap_block_pp0_stage42_flag00011011, ap_block_pp0_stage43_flag00011011, ap_block_pp0_stage44_flag00011011, ap_block_pp0_stage45_flag00011011, ap_block_pp0_stage46_flag00011011, ap_block_pp0_stage47_flag00011011, ap_block_pp0_stage48_flag00011011, ap_block_pp0_stage49_flag00011011, ap_block_pp0_stage50_flag00011011, ap_block_pp0_stage51_flag00011011, ap_block_pp0_stage52_flag00011011, ap_block_pp0_stage53_flag00011011, ap_block_pp0_stage54_flag00011011, ap_block_pp0_stage55_flag00011011, ap_block_pp0_stage56_flag00011011, ap_block_pp0_stage57_flag00011011, ap_block_pp0_stage58_flag00011011, ap_block_pp0_stage59_flag00011011, ap_block_pp0_stage60_flag00011011, ap_block_pp0_stage61_flag00011011, ap_block_pp0_stage62_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_reset_idle_pp0 = ap_const_logic_0) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_1to1))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when ap_ST_fsm_pp0_stage13 =>
if ((ap_block_pp0_stage13_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage13;
end if;
when ap_ST_fsm_pp0_stage14 =>
if ((ap_block_pp0_stage14_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage14;
end if;
when ap_ST_fsm_pp0_stage15 =>
if ((ap_block_pp0_stage15_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage15;
end if;
when ap_ST_fsm_pp0_stage16 =>
if ((ap_block_pp0_stage16_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage16;
end if;
when ap_ST_fsm_pp0_stage17 =>
if ((ap_block_pp0_stage17_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage17;
end if;
when ap_ST_fsm_pp0_stage18 =>
if ((ap_block_pp0_stage18_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage18;
end if;
when ap_ST_fsm_pp0_stage19 =>
if ((ap_block_pp0_stage19_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage19;
end if;
when ap_ST_fsm_pp0_stage20 =>
if ((ap_block_pp0_stage20_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage20;
end if;
when ap_ST_fsm_pp0_stage21 =>
if ((ap_block_pp0_stage21_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage21;
end if;
when ap_ST_fsm_pp0_stage22 =>
if ((ap_block_pp0_stage22_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage22;
end if;
when ap_ST_fsm_pp0_stage23 =>
if ((ap_block_pp0_stage23_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage23;
end if;
when ap_ST_fsm_pp0_stage24 =>
if ((ap_block_pp0_stage24_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage24;
end if;
when ap_ST_fsm_pp0_stage25 =>
if ((ap_block_pp0_stage25_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage25;
end if;
when ap_ST_fsm_pp0_stage26 =>
if ((ap_block_pp0_stage26_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage26;
end if;
when ap_ST_fsm_pp0_stage27 =>
if ((ap_block_pp0_stage27_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage27;
end if;
when ap_ST_fsm_pp0_stage28 =>
if ((ap_block_pp0_stage28_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage28;
end if;
when ap_ST_fsm_pp0_stage29 =>
if ((ap_block_pp0_stage29_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage29;
end if;
when ap_ST_fsm_pp0_stage30 =>
if ((ap_block_pp0_stage30_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage30;
end if;
when ap_ST_fsm_pp0_stage31 =>
if ((ap_block_pp0_stage31_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage31;
end if;
when ap_ST_fsm_pp0_stage32 =>
if ((ap_block_pp0_stage32_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage32;
end if;
when ap_ST_fsm_pp0_stage33 =>
if ((ap_block_pp0_stage33_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage33;
end if;
when ap_ST_fsm_pp0_stage34 =>
if ((ap_block_pp0_stage34_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage34;
end if;
when ap_ST_fsm_pp0_stage35 =>
if ((ap_block_pp0_stage35_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage35;
end if;
when ap_ST_fsm_pp0_stage36 =>
if ((ap_block_pp0_stage36_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage36;
end if;
when ap_ST_fsm_pp0_stage37 =>
if ((ap_block_pp0_stage37_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage37;
end if;
when ap_ST_fsm_pp0_stage38 =>
if ((ap_block_pp0_stage38_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage38;
end if;
when ap_ST_fsm_pp0_stage39 =>
if ((ap_block_pp0_stage39_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage39;
end if;
when ap_ST_fsm_pp0_stage40 =>
if ((ap_block_pp0_stage40_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage40;
end if;
when ap_ST_fsm_pp0_stage41 =>
if ((ap_block_pp0_stage41_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage41;
end if;
when ap_ST_fsm_pp0_stage42 =>
if ((ap_block_pp0_stage42_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage42;
end if;
when ap_ST_fsm_pp0_stage43 =>
if ((ap_block_pp0_stage43_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage43;
end if;
when ap_ST_fsm_pp0_stage44 =>
if ((ap_block_pp0_stage44_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage44;
end if;
when ap_ST_fsm_pp0_stage45 =>
if ((ap_block_pp0_stage45_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage45;
end if;
when ap_ST_fsm_pp0_stage46 =>
if ((ap_block_pp0_stage46_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage46;
end if;
when ap_ST_fsm_pp0_stage47 =>
if ((ap_block_pp0_stage47_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage47;
end if;
when ap_ST_fsm_pp0_stage48 =>
if ((ap_block_pp0_stage48_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage48;
end if;
when ap_ST_fsm_pp0_stage49 =>
if ((ap_block_pp0_stage49_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage49;
end if;
when ap_ST_fsm_pp0_stage50 =>
if ((ap_block_pp0_stage50_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage50;
end if;
when ap_ST_fsm_pp0_stage51 =>
if ((ap_block_pp0_stage51_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage51;
end if;
when ap_ST_fsm_pp0_stage52 =>
if ((ap_block_pp0_stage52_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage52;
end if;
when ap_ST_fsm_pp0_stage53 =>
if ((ap_block_pp0_stage53_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage53;
end if;
when ap_ST_fsm_pp0_stage54 =>
if ((ap_block_pp0_stage54_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage54;
end if;
when ap_ST_fsm_pp0_stage55 =>
if ((ap_block_pp0_stage55_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage55;
end if;
when ap_ST_fsm_pp0_stage56 =>
if ((ap_block_pp0_stage56_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage56;
end if;
when ap_ST_fsm_pp0_stage57 =>
if ((ap_block_pp0_stage57_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage57;
end if;
when ap_ST_fsm_pp0_stage58 =>
if ((ap_block_pp0_stage58_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage58;
end if;
when ap_ST_fsm_pp0_stage59 =>
if ((ap_block_pp0_stage59_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage59;
end if;
when ap_ST_fsm_pp0_stage60 =>
if ((ap_block_pp0_stage60_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage60;
end if;
when ap_ST_fsm_pp0_stage61 =>
if ((ap_block_pp0_stage61_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage61;
end if;
when ap_ST_fsm_pp0_stage62 =>
if ((ap_block_pp0_stage62_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage62;
end if;
when ap_ST_fsm_pp0_stage63 =>
if ((ap_block_pp0_stage63_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage63;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(10);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage13 <= ap_CS_fsm(13);
ap_CS_fsm_pp0_stage14 <= ap_CS_fsm(14);
ap_CS_fsm_pp0_stage15 <= ap_CS_fsm(15);
ap_CS_fsm_pp0_stage16 <= ap_CS_fsm(16);
ap_CS_fsm_pp0_stage17 <= ap_CS_fsm(17);
ap_CS_fsm_pp0_stage18 <= ap_CS_fsm(18);
ap_CS_fsm_pp0_stage19 <= ap_CS_fsm(19);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage20 <= ap_CS_fsm(20);
ap_CS_fsm_pp0_stage21 <= ap_CS_fsm(21);
ap_CS_fsm_pp0_stage22 <= ap_CS_fsm(22);
ap_CS_fsm_pp0_stage23 <= ap_CS_fsm(23);
ap_CS_fsm_pp0_stage24 <= ap_CS_fsm(24);
ap_CS_fsm_pp0_stage25 <= ap_CS_fsm(25);
ap_CS_fsm_pp0_stage26 <= ap_CS_fsm(26);
ap_CS_fsm_pp0_stage27 <= ap_CS_fsm(27);
ap_CS_fsm_pp0_stage28 <= ap_CS_fsm(28);
ap_CS_fsm_pp0_stage29 <= ap_CS_fsm(29);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage30 <= ap_CS_fsm(30);
ap_CS_fsm_pp0_stage31 <= ap_CS_fsm(31);
ap_CS_fsm_pp0_stage32 <= ap_CS_fsm(32);
ap_CS_fsm_pp0_stage33 <= ap_CS_fsm(33);
ap_CS_fsm_pp0_stage34 <= ap_CS_fsm(34);
ap_CS_fsm_pp0_stage35 <= ap_CS_fsm(35);
ap_CS_fsm_pp0_stage36 <= ap_CS_fsm(36);
ap_CS_fsm_pp0_stage37 <= ap_CS_fsm(37);
ap_CS_fsm_pp0_stage38 <= ap_CS_fsm(38);
ap_CS_fsm_pp0_stage39 <= ap_CS_fsm(39);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage40 <= ap_CS_fsm(40);
ap_CS_fsm_pp0_stage41 <= ap_CS_fsm(41);
ap_CS_fsm_pp0_stage42 <= ap_CS_fsm(42);
ap_CS_fsm_pp0_stage43 <= ap_CS_fsm(43);
ap_CS_fsm_pp0_stage44 <= ap_CS_fsm(44);
ap_CS_fsm_pp0_stage45 <= ap_CS_fsm(45);
ap_CS_fsm_pp0_stage46 <= ap_CS_fsm(46);
ap_CS_fsm_pp0_stage47 <= ap_CS_fsm(47);
ap_CS_fsm_pp0_stage48 <= ap_CS_fsm(48);
ap_CS_fsm_pp0_stage49 <= ap_CS_fsm(49);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage50 <= ap_CS_fsm(50);
ap_CS_fsm_pp0_stage51 <= ap_CS_fsm(51);
ap_CS_fsm_pp0_stage52 <= ap_CS_fsm(52);
ap_CS_fsm_pp0_stage53 <= ap_CS_fsm(53);
ap_CS_fsm_pp0_stage54 <= ap_CS_fsm(54);
ap_CS_fsm_pp0_stage55 <= ap_CS_fsm(55);
ap_CS_fsm_pp0_stage56 <= ap_CS_fsm(56);
ap_CS_fsm_pp0_stage57 <= ap_CS_fsm(57);
ap_CS_fsm_pp0_stage58 <= ap_CS_fsm(58);
ap_CS_fsm_pp0_stage59 <= ap_CS_fsm(59);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage60 <= ap_CS_fsm(60);
ap_CS_fsm_pp0_stage61 <= ap_CS_fsm(61);
ap_CS_fsm_pp0_stage62 <= ap_CS_fsm(62);
ap_CS_fsm_pp0_stage63 <= ap_CS_fsm(63);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(9);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0, ap_ce)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_ce = ap_const_logic_0) or ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)));
end process;
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage10_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage11_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage12_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage13_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage13_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage13_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage14_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage14_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage14_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage15_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage15_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage15_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage16_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage16_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage16_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage17_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage17_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage17_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage18_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage18_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage18_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage19_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage19_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage19_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage1_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage20_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage20_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage20_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage21_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage21_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage21_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage22_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage22_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage22_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage23_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage23_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage23_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage24_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage24_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage24_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage25_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage25_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage25_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage26_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage26_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage26_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage27_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage27_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage27_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage28_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage28_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage28_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage29_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage29_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage29_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage2_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage30_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage30_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage30_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage31_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage31_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage31_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage32_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage32_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage32_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage33_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage33_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage33_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage34_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage34_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage34_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage35_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage35_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage35_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage36_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage36_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage36_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage37_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage37_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage37_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage38_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage38_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage38_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage39_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage39_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage39_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage3_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage40_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage40_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage40_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage41_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage41_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage41_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage42_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage42_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage42_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage43_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage43_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage43_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage44_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage44_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage44_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage45_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage45_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage45_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage46_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage46_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage46_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage47_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage47_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage47_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage48_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage48_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage48_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage49_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage49_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage49_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage4_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage50_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage50_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage50_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage51_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage51_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage51_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage52_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage52_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage52_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage53_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage53_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage53_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage54_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage54_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage54_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage55_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage55_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage55_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage56_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage56_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage56_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage57_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage57_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage57_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage58_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage58_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage58_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage59_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage59_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage59_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage5_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage60_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage60_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage60_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage61_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage61_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage61_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage62_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage62_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage62_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage63_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage63_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage63_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage6_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage7_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage8_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011_assign_proc : process(ap_ce)
begin
ap_block_pp0_stage9_flag00011011 <= (ap_ce = ap_const_logic_0);
end process;
ap_block_state10_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage13_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage14_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage15_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage16_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage17_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage18_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state20_pp0_stage19_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage20_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage21_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage22_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage23_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage24_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage25_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage26_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage27_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage28_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage29_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage30_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage31_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage32_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage33_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage34_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage35_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage36_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage37_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage38_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage39_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage40_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage41_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage42_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage43_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage44_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage45_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage46_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage47_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage48_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage49_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage50_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage51_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage52_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage53_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage54_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage55_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage56_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage57_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage58_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage59_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage60_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage61_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage62_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage63_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_ce, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0_reg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0 <= ap_start;
else
ap_enable_reg_pp0_iter0 <= ap_enable_reg_pp0_iter0_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to0_assign_proc : process(ap_enable_reg_pp0_iter0)
begin
if ((ap_const_logic_0 = ap_enable_reg_pp0_iter0)) then
ap_idle_pp0_0to0 <= ap_const_logic_1;
else
ap_idle_pp0_0to0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_1to1_assign_proc : process(ap_enable_reg_pp0_iter1)
begin
if ((ap_const_logic_0 = ap_enable_reg_pp0_iter1)) then
ap_idle_pp0_1to1 <= ap_const_logic_1;
else
ap_idle_pp0_1to1 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce)
begin
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to0))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_return <= (tmp63_fu_1071_p2 or tmp_reg_1323);
contacts_V_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_7A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_78;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_76;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_74;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_72;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_70;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_68;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_66;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_64;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_62;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_60;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_5A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_58;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_56;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_54;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_52;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_50;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_48;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_46;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_44;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_42;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_40;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_3A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_38;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_36;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_34;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_32;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_30;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_28;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_26;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_24;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_22;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_20;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_1A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_18;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_16;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_14;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_12;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_10;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_E;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_C;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_A;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_8;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_6;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_4;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_2;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
contacts_V_address0 <= ap_const_lv7_0;
else
contacts_V_address0 <= "XXXXXXX";
end if;
else
contacts_V_address0 <= "XXXXXXX";
end if;
end process;
contacts_V_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_CS_fsm_pp0_stage63, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_79;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_77;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_75;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_73;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_71;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_6B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_69;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_67;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_65;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_63;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_61;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_59;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_57;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_55;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_53;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_51;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_4B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_49;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_47;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_45;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_43;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_41;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_39;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_37;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_35;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_33;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_31;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_2B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_29;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_27;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_25;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_23;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_21;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_19;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_17;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_15;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_13;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_11;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_F;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_D;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_B;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_9;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_7;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_5;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_3;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
contacts_V_address1 <= ap_const_lv7_1;
else
contacts_V_address1 <= "XXXXXXX";
end if;
else
contacts_V_address1 <= "XXXXXXX";
end if;
end process;
contacts_V_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then
contacts_V_ce0 <= ap_const_logic_1;
else
contacts_V_ce0 <= ap_const_logic_0;
end if;
end process;
contacts_V_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage63, ap_block_pp0_stage63_flag00011001, ap_ce, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage13, ap_block_pp0_stage13_flag00011001, ap_CS_fsm_pp0_stage14, ap_block_pp0_stage14_flag00011001, ap_CS_fsm_pp0_stage15, ap_block_pp0_stage15_flag00011001, ap_CS_fsm_pp0_stage16, ap_block_pp0_stage16_flag00011001, ap_CS_fsm_pp0_stage17, ap_block_pp0_stage17_flag00011001, ap_CS_fsm_pp0_stage18, ap_block_pp0_stage18_flag00011001, ap_CS_fsm_pp0_stage19, ap_block_pp0_stage19_flag00011001, ap_CS_fsm_pp0_stage20, ap_block_pp0_stage20_flag00011001, ap_CS_fsm_pp0_stage21, ap_block_pp0_stage21_flag00011001, ap_CS_fsm_pp0_stage22, ap_block_pp0_stage22_flag00011001, ap_CS_fsm_pp0_stage23, ap_block_pp0_stage23_flag00011001, ap_CS_fsm_pp0_stage24, ap_block_pp0_stage24_flag00011001, ap_CS_fsm_pp0_stage25, ap_block_pp0_stage25_flag00011001, ap_CS_fsm_pp0_stage26, ap_block_pp0_stage26_flag00011001, ap_CS_fsm_pp0_stage27, ap_block_pp0_stage27_flag00011001, ap_CS_fsm_pp0_stage28, ap_block_pp0_stage28_flag00011001, ap_CS_fsm_pp0_stage29, ap_block_pp0_stage29_flag00011001, ap_CS_fsm_pp0_stage30, ap_block_pp0_stage30_flag00011001, ap_CS_fsm_pp0_stage31, ap_block_pp0_stage31_flag00011001, ap_CS_fsm_pp0_stage32, ap_block_pp0_stage32_flag00011001, ap_CS_fsm_pp0_stage33, ap_block_pp0_stage33_flag00011001, ap_CS_fsm_pp0_stage34, ap_block_pp0_stage34_flag00011001, ap_CS_fsm_pp0_stage35, ap_block_pp0_stage35_flag00011001, ap_CS_fsm_pp0_stage36, ap_block_pp0_stage36_flag00011001, ap_CS_fsm_pp0_stage37, ap_block_pp0_stage37_flag00011001, ap_CS_fsm_pp0_stage38, ap_block_pp0_stage38_flag00011001, ap_CS_fsm_pp0_stage39, ap_block_pp0_stage39_flag00011001, ap_CS_fsm_pp0_stage40, ap_block_pp0_stage40_flag00011001, ap_CS_fsm_pp0_stage41, ap_block_pp0_stage41_flag00011001, ap_CS_fsm_pp0_stage42, ap_block_pp0_stage42_flag00011001, ap_CS_fsm_pp0_stage43, ap_block_pp0_stage43_flag00011001, ap_CS_fsm_pp0_stage44, ap_block_pp0_stage44_flag00011001, ap_CS_fsm_pp0_stage45, ap_block_pp0_stage45_flag00011001, ap_CS_fsm_pp0_stage46, ap_block_pp0_stage46_flag00011001, ap_CS_fsm_pp0_stage47, ap_block_pp0_stage47_flag00011001, ap_CS_fsm_pp0_stage48, ap_block_pp0_stage48_flag00011001, ap_CS_fsm_pp0_stage49, ap_block_pp0_stage49_flag00011001, ap_CS_fsm_pp0_stage50, ap_block_pp0_stage50_flag00011001, ap_CS_fsm_pp0_stage51, ap_block_pp0_stage51_flag00011001, ap_CS_fsm_pp0_stage52, ap_block_pp0_stage52_flag00011001, ap_CS_fsm_pp0_stage53, ap_block_pp0_stage53_flag00011001, ap_CS_fsm_pp0_stage54, ap_block_pp0_stage54_flag00011001, ap_CS_fsm_pp0_stage55, ap_block_pp0_stage55_flag00011001, ap_CS_fsm_pp0_stage56, ap_block_pp0_stage56_flag00011001, ap_CS_fsm_pp0_stage57, ap_block_pp0_stage57_flag00011001, ap_CS_fsm_pp0_stage58, ap_block_pp0_stage58_flag00011001, ap_CS_fsm_pp0_stage59, ap_block_pp0_stage59_flag00011001, ap_CS_fsm_pp0_stage60, ap_block_pp0_stage60_flag00011001, ap_CS_fsm_pp0_stage61, ap_block_pp0_stage61_flag00011001, ap_CS_fsm_pp0_stage62, ap_block_pp0_stage62_flag00011001, ap_block_pp0_stage0_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00011001 = ap_const_boolean_0) and (ap_ce = ap_const_logic_1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_ce = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00011001 = ap_const_boolean_0)))) then
contacts_V_ce1 <= ap_const_logic_1;
else
contacts_V_ce1 <= ap_const_logic_0;
end if;
end process;
grp_fu_403_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
grp_fu_403_p1 <= db_item_V_read_reg_1082;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_403_p1 <= ap_port_reg_db_item_V;
else
grp_fu_403_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_403_p2 <= "1" when (contacts_V_q0 = grp_fu_403_p1) else "0";
grp_fu_409_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00000000, ap_enable_reg_pp0_iter1, ap_CS_fsm_pp0_stage63, db_item_V_read_reg_1082, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage13, ap_CS_fsm_pp0_stage14, ap_CS_fsm_pp0_stage15, ap_CS_fsm_pp0_stage16, ap_CS_fsm_pp0_stage17, ap_CS_fsm_pp0_stage18, ap_CS_fsm_pp0_stage19, ap_CS_fsm_pp0_stage20, ap_CS_fsm_pp0_stage21, ap_CS_fsm_pp0_stage22, ap_CS_fsm_pp0_stage23, ap_CS_fsm_pp0_stage24, ap_CS_fsm_pp0_stage25, ap_CS_fsm_pp0_stage26, ap_CS_fsm_pp0_stage27, ap_CS_fsm_pp0_stage28, ap_CS_fsm_pp0_stage29, ap_CS_fsm_pp0_stage30, ap_CS_fsm_pp0_stage31, ap_CS_fsm_pp0_stage32, ap_CS_fsm_pp0_stage33, ap_CS_fsm_pp0_stage34, ap_CS_fsm_pp0_stage35, ap_CS_fsm_pp0_stage36, ap_CS_fsm_pp0_stage37, ap_CS_fsm_pp0_stage38, ap_CS_fsm_pp0_stage39, ap_CS_fsm_pp0_stage40, ap_CS_fsm_pp0_stage41, ap_CS_fsm_pp0_stage42, ap_CS_fsm_pp0_stage43, ap_CS_fsm_pp0_stage44, ap_CS_fsm_pp0_stage45, ap_CS_fsm_pp0_stage46, ap_CS_fsm_pp0_stage47, ap_CS_fsm_pp0_stage48, ap_CS_fsm_pp0_stage49, ap_CS_fsm_pp0_stage50, ap_CS_fsm_pp0_stage51, ap_CS_fsm_pp0_stage52, ap_CS_fsm_pp0_stage53, ap_CS_fsm_pp0_stage54, ap_CS_fsm_pp0_stage55, ap_CS_fsm_pp0_stage56, ap_CS_fsm_pp0_stage57, ap_CS_fsm_pp0_stage58, ap_CS_fsm_pp0_stage59, ap_CS_fsm_pp0_stage60, ap_CS_fsm_pp0_stage61, ap_CS_fsm_pp0_stage62, ap_port_reg_db_item_V, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000, ap_block_pp0_stage13_flag00000000, ap_block_pp0_stage14_flag00000000, ap_block_pp0_stage15_flag00000000, ap_block_pp0_stage16_flag00000000, ap_block_pp0_stage17_flag00000000, ap_block_pp0_stage18_flag00000000, ap_block_pp0_stage19_flag00000000, ap_block_pp0_stage20_flag00000000, ap_block_pp0_stage21_flag00000000, ap_block_pp0_stage22_flag00000000, ap_block_pp0_stage23_flag00000000, ap_block_pp0_stage24_flag00000000, ap_block_pp0_stage25_flag00000000, ap_block_pp0_stage26_flag00000000, ap_block_pp0_stage27_flag00000000, ap_block_pp0_stage28_flag00000000, ap_block_pp0_stage29_flag00000000, ap_block_pp0_stage30_flag00000000, ap_block_pp0_stage31_flag00000000, ap_block_pp0_stage32_flag00000000, ap_block_pp0_stage33_flag00000000, ap_block_pp0_stage34_flag00000000, ap_block_pp0_stage35_flag00000000, ap_block_pp0_stage36_flag00000000, ap_block_pp0_stage37_flag00000000, ap_block_pp0_stage38_flag00000000, ap_block_pp0_stage39_flag00000000, ap_block_pp0_stage40_flag00000000, ap_block_pp0_stage41_flag00000000, ap_block_pp0_stage42_flag00000000, ap_block_pp0_stage43_flag00000000, ap_block_pp0_stage44_flag00000000, ap_block_pp0_stage45_flag00000000, ap_block_pp0_stage46_flag00000000, ap_block_pp0_stage47_flag00000000, ap_block_pp0_stage48_flag00000000, ap_block_pp0_stage49_flag00000000, ap_block_pp0_stage50_flag00000000, ap_block_pp0_stage51_flag00000000, ap_block_pp0_stage52_flag00000000, ap_block_pp0_stage53_flag00000000, ap_block_pp0_stage54_flag00000000, ap_block_pp0_stage55_flag00000000, ap_block_pp0_stage56_flag00000000, ap_block_pp0_stage57_flag00000000, ap_block_pp0_stage58_flag00000000, ap_block_pp0_stage59_flag00000000, ap_block_pp0_stage60_flag00000000, ap_block_pp0_stage61_flag00000000, ap_block_pp0_stage62_flag00000000, ap_block_pp0_stage63_flag00000000)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage13) and (ap_block_pp0_stage13_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage14) and (ap_block_pp0_stage14_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage15) and (ap_block_pp0_stage15_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage16) and (ap_block_pp0_stage16_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage17) and (ap_block_pp0_stage17_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage18) and (ap_block_pp0_stage18_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage19) and (ap_block_pp0_stage19_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage20) and (ap_block_pp0_stage20_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage21) and (ap_block_pp0_stage21_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage22) and (ap_block_pp0_stage22_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage23) and (ap_block_pp0_stage23_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage24) and (ap_block_pp0_stage24_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage25) and (ap_block_pp0_stage25_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage26) and (ap_block_pp0_stage26_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage27) and (ap_block_pp0_stage27_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage28) and (ap_block_pp0_stage28_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage29) and (ap_block_pp0_stage29_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage30) and (ap_block_pp0_stage30_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage31) and (ap_block_pp0_stage31_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage32) and (ap_block_pp0_stage32_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage33) and (ap_block_pp0_stage33_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage34) and (ap_block_pp0_stage34_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage35) and (ap_block_pp0_stage35_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage36) and (ap_block_pp0_stage36_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage37) and (ap_block_pp0_stage37_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage38) and (ap_block_pp0_stage38_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage39) and (ap_block_pp0_stage39_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage40) and (ap_block_pp0_stage40_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage41) and (ap_block_pp0_stage41_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage42) and (ap_block_pp0_stage42_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage43) and (ap_block_pp0_stage43_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage44) and (ap_block_pp0_stage44_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage45) and (ap_block_pp0_stage45_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage46) and (ap_block_pp0_stage46_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage47) and (ap_block_pp0_stage47_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage48) and (ap_block_pp0_stage48_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage49) and (ap_block_pp0_stage49_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage50) and (ap_block_pp0_stage50_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage51) and (ap_block_pp0_stage51_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage52) and (ap_block_pp0_stage52_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage53) and (ap_block_pp0_stage53_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage54) and (ap_block_pp0_stage54_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage55) and (ap_block_pp0_stage55_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage56) and (ap_block_pp0_stage56_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage57) and (ap_block_pp0_stage57_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage58) and (ap_block_pp0_stage58_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage59) and (ap_block_pp0_stage59_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage60) and (ap_block_pp0_stage60_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage61) and (ap_block_pp0_stage61_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage62) and (ap_block_pp0_stage62_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage63) and (ap_block_pp0_stage63_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)))) then
grp_fu_409_p1 <= db_item_V_read_reg_1082;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
grp_fu_409_p1 <= ap_port_reg_db_item_V;
else
grp_fu_409_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_409_p2 <= "1" when (contacts_V_q1 = grp_fu_409_p1) else "0";
tmp100_fu_908_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp101_fu_930_p2 <= (tmp103_fu_924_p2 or tmp102_fu_920_p2);
tmp102_fu_920_p2 <= (tmp_1_99_reg_1463 or tmp_1_100_reg_1468);
tmp103_fu_924_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp104_fu_973_p2 <= (tmp108_fu_967_p2 or tmp105_reg_1488);
tmp105_fu_951_p2 <= (tmp107_fu_945_p2 or tmp106_fu_941_p2);
tmp106_fu_941_p2 <= (tmp_1_103_reg_1478 or tmp_1_104_reg_1483);
tmp107_fu_945_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp108_fu_967_p2 <= (tmp110_fu_961_p2 or tmp109_fu_957_p2);
tmp109_fu_957_p2 <= (tmp_1_107_reg_1493 or tmp_1_108_reg_1498);
tmp10_fu_484_p2 <= (tmp14_fu_478_p2 or tmp11_reg_1128);
tmp110_fu_961_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp111_fu_1061_p2 <= (tmp119_fu_1056_p2 or tmp112_reg_1533);
tmp112_fu_1015_p2 <= (tmp116_fu_1009_p2 or tmp113_reg_1518);
tmp113_fu_993_p2 <= (tmp115_fu_987_p2 or tmp114_fu_983_p2);
tmp114_fu_983_p2 <= (tmp_1_111_reg_1508 or tmp_1_112_reg_1513);
tmp115_fu_987_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp116_fu_1009_p2 <= (tmp118_fu_1003_p2 or tmp117_fu_999_p2);
tmp117_fu_999_p2 <= (tmp_1_115_reg_1523 or tmp_1_116_reg_1528);
tmp118_fu_1003_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp119_fu_1056_p2 <= (tmp123_fu_1050_p2 or tmp120_reg_1548);
tmp11_fu_462_p2 <= (tmp13_fu_456_p2 or tmp12_fu_452_p2);
tmp120_fu_1030_p2 <= (tmp122_fu_1024_p2 or tmp121_fu_1020_p2);
tmp121_fu_1020_p2 <= (tmp_1_119_reg_1538 or tmp_1_120_reg_1543);
tmp122_fu_1024_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp123_fu_1050_p2 <= (tmp125_fu_1044_p2 or tmp124_fu_1040_p2);
tmp124_fu_1040_p2 <= (tmp_1_123_reg_1553 or tmp_1_124_reg_1558);
tmp125_fu_1044_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp12_fu_452_p2 <= (tmp_1_8_reg_1118 or tmp_1_9_reg_1123);
tmp13_fu_456_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp14_fu_478_p2 <= (tmp16_fu_472_p2 or tmp15_fu_468_p2);
tmp15_fu_468_p2 <= (tmp_1_11_reg_1133 or tmp_1_12_reg_1138);
tmp16_fu_472_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp17_fu_568_p2 <= (tmp25_fu_563_p2 or tmp18_reg_1173);
tmp18_fu_526_p2 <= (tmp22_fu_520_p2 or tmp19_reg_1158);
tmp19_fu_504_p2 <= (tmp21_fu_498_p2 or tmp20_fu_494_p2);
tmp1_fu_705_p2 <= (tmp17_reg_1203 or tmp2_reg_1143);
tmp20_fu_494_p2 <= (tmp_1_15_reg_1148 or tmp_1_16_reg_1153);
tmp21_fu_498_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp22_fu_520_p2 <= (tmp24_fu_514_p2 or tmp23_fu_510_p2);
tmp23_fu_510_p2 <= (tmp_1_19_reg_1163 or tmp_1_20_reg_1168);
tmp24_fu_514_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp25_fu_563_p2 <= (tmp29_fu_557_p2 or tmp26_reg_1188);
tmp26_fu_541_p2 <= (tmp28_fu_535_p2 or tmp27_fu_531_p2);
tmp27_fu_531_p2 <= (tmp_1_23_reg_1178 or tmp_1_24_reg_1183);
tmp28_fu_535_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp29_fu_557_p2 <= (tmp31_fu_551_p2 or tmp30_fu_547_p2);
tmp2_fu_489_p2 <= (tmp10_fu_484_p2 or tmp3_reg_1113);
tmp30_fu_547_p2 <= (tmp_1_27_reg_1193 or tmp_1_28_reg_1198);
tmp31_fu_551_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp32_fu_735_p2 <= (tmp48_fu_730_p2 or tmp33_reg_1263);
tmp33_fu_647_p2 <= (tmp41_fu_642_p2 or tmp34_reg_1233);
tmp34_fu_605_p2 <= (tmp38_fu_599_p2 or tmp35_reg_1218);
tmp35_fu_583_p2 <= (tmp37_fu_577_p2 or tmp36_fu_573_p2);
tmp36_fu_573_p2 <= (tmp_1_31_reg_1208 or tmp_1_32_reg_1213);
tmp37_fu_577_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp38_fu_599_p2 <= (tmp40_fu_593_p2 or tmp39_fu_589_p2);
tmp39_fu_589_p2 <= (tmp_1_35_reg_1223 or tmp_1_36_reg_1228);
tmp3_fu_447_p2 <= (tmp7_fu_441_p2 or tmp4_reg_1098);
tmp40_fu_593_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp41_fu_642_p2 <= (tmp45_fu_636_p2 or tmp42_reg_1248);
tmp42_fu_620_p2 <= (tmp44_fu_614_p2 or tmp43_fu_610_p2);
tmp43_fu_610_p2 <= (tmp_1_39_reg_1238 or tmp_1_40_reg_1243);
tmp44_fu_614_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp45_fu_636_p2 <= (tmp47_fu_630_p2 or tmp46_fu_626_p2);
tmp46_fu_626_p2 <= (tmp_1_43_reg_1253 or tmp_1_44_reg_1258);
tmp47_fu_630_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp48_fu_730_p2 <= (tmp56_fu_725_p2 or tmp49_reg_1293);
tmp49_fu_684_p2 <= (tmp53_fu_678_p2 or tmp50_reg_1278);
tmp4_fu_425_p2 <= (tmp6_fu_419_p2 or tmp5_fu_415_p2);
tmp50_fu_662_p2 <= (tmp52_fu_656_p2 or tmp51_fu_652_p2);
tmp51_fu_652_p2 <= (tmp_1_47_reg_1268 or tmp_1_48_reg_1273);
tmp52_fu_656_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp53_fu_678_p2 <= (tmp55_fu_672_p2 or tmp54_fu_668_p2);
tmp54_fu_668_p2 <= (tmp_1_51_reg_1283 or tmp_1_52_reg_1288);
tmp55_fu_672_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp56_fu_725_p2 <= (tmp60_fu_719_p2 or tmp57_reg_1308);
tmp57_fu_699_p2 <= (tmp59_fu_693_p2 or tmp58_fu_689_p2);
tmp58_fu_689_p2 <= (tmp_1_55_reg_1298 or tmp_1_56_reg_1303);
tmp59_fu_693_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp5_fu_415_p2 <= (tmp_1_reg_1088 or tmp_1_1_reg_1093);
tmp60_fu_719_p2 <= (tmp62_fu_713_p2 or tmp61_fu_709_p2);
tmp61_fu_709_p2 <= (tmp_1_59_reg_1313 or tmp_1_60_reg_1318);
tmp62_fu_713_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp63_fu_1071_p2 <= (tmp95_fu_1066_p2 or tmp64_fu_1036_p2);
tmp64_fu_1036_p2 <= (tmp80_reg_1443 or tmp65_reg_1383);
tmp65_fu_820_p2 <= (tmp73_fu_815_p2 or tmp66_reg_1353);
tmp66_fu_778_p2 <= (tmp70_fu_772_p2 or tmp67_reg_1338);
tmp67_fu_756_p2 <= (tmp69_fu_750_p2 or tmp68_fu_746_p2);
tmp68_fu_746_p2 <= (tmp_1_63_reg_1328 or tmp_1_64_reg_1333);
tmp69_fu_750_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp6_fu_419_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp70_fu_772_p2 <= (tmp72_fu_766_p2 or tmp71_fu_762_p2);
tmp71_fu_762_p2 <= (tmp_1_67_reg_1343 or tmp_1_68_reg_1348);
tmp72_fu_766_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp73_fu_815_p2 <= (tmp77_fu_809_p2 or tmp74_reg_1368);
tmp74_fu_793_p2 <= (tmp76_fu_787_p2 or tmp75_fu_783_p2);
tmp75_fu_783_p2 <= (tmp_1_71_reg_1358 or tmp_1_72_reg_1363);
tmp76_fu_787_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp77_fu_809_p2 <= (tmp79_fu_803_p2 or tmp78_fu_799_p2);
tmp78_fu_799_p2 <= (tmp_1_75_reg_1373 or tmp_1_76_reg_1378);
tmp79_fu_803_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp7_fu_441_p2 <= (tmp9_fu_435_p2 or tmp8_fu_431_p2);
tmp80_fu_899_p2 <= (tmp88_fu_894_p2 or tmp81_reg_1413);
tmp81_fu_857_p2 <= (tmp85_fu_851_p2 or tmp82_reg_1398);
tmp82_fu_835_p2 <= (tmp84_fu_829_p2 or tmp83_fu_825_p2);
tmp83_fu_825_p2 <= (tmp_1_79_reg_1388 or tmp_1_80_reg_1393);
tmp84_fu_829_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp85_fu_851_p2 <= (tmp87_fu_845_p2 or tmp86_fu_841_p2);
tmp86_fu_841_p2 <= (tmp_1_83_reg_1403 or tmp_1_84_reg_1408);
tmp87_fu_845_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp88_fu_894_p2 <= (tmp92_fu_888_p2 or tmp89_reg_1428);
tmp89_fu_872_p2 <= (tmp91_fu_866_p2 or tmp90_fu_862_p2);
tmp8_fu_431_p2 <= (tmp_1_4_reg_1103 or tmp_1_5_reg_1108);
tmp90_fu_862_p2 <= (tmp_1_87_reg_1418 or tmp_1_88_reg_1423);
tmp91_fu_866_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp92_fu_888_p2 <= (tmp94_fu_882_p2 or tmp93_fu_878_p2);
tmp93_fu_878_p2 <= (tmp_1_91_reg_1433 or tmp_1_92_reg_1438);
tmp94_fu_882_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp95_fu_1066_p2 <= (tmp111_fu_1061_p2 or tmp96_reg_1503);
tmp96_fu_978_p2 <= (tmp104_fu_973_p2 or tmp97_reg_1473);
tmp97_fu_936_p2 <= (tmp101_fu_930_p2 or tmp98_reg_1458);
tmp98_fu_914_p2 <= (tmp100_fu_908_p2 or tmp99_fu_904_p2);
tmp99_fu_904_p2 <= (tmp_1_95_reg_1448 or tmp_1_96_reg_1453);
tmp9_fu_435_p2 <= (grp_fu_403_p2 or grp_fu_409_p2);
tmp_fu_740_p2 <= (tmp32_fu_735_p2 or tmp1_fu_705_p2);
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug is
end entity;
architecture a of bug is
signal irunning :natural range 0 to 1;
begin
irunning <= 2; -- reports error, but no information
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug is
end entity;
architecture a of bug is
signal irunning :natural range 0 to 1;
begin
irunning <= 2; -- reports error, but no information
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity bug is
end entity;
architecture a of bug is
signal irunning :natural range 0 to 1;
begin
irunning <= 2; -- reports error, but no information
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
|
package pack is
type id_alloc_t is protected
impure function next_id return integer;
end protected;
type rec_t is record
id : integer;
end record;
impure function get_next_rec return rec_t;
end package;
package body pack is
type id_alloc_t is protected body
variable counter : integer := 0;
impure function next_id return integer is
begin
counter := counter + 1;
return counter;
end function;
end protected body;
shared variable id_alloc : id_alloc_t;
impure function get_next_rec return rec_t is
begin
return (id => id_alloc.next_id);
end function;
end package body;
-------------------------------------------------------------------------------
use work.pack.all;
entity sub is
generic ( r1, r2 : rec_t );
end entity;
architecture test of sub is
begin
p1: process is
begin
assert r1.id = 1;
assert r2.id = 2;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack.all;
entity protected7 is
end entity;
architecture test of protected7 is
constant cr1 : rec_t := get_next_rec;
constant cr2 : rec_t := get_next_rec;
begin
u: entity work.sub generic map ( cr1, cr2 );
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY ALU IS
PORT(
X : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
OP : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
FR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
RES : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END ALU;
ARCHITECTURE main OF ALU IS
BEGIN
END main; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY ALU IS
PORT(
X : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
OP : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
FR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
RES : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END ALU;
ARCHITECTURE main OF ALU IS
BEGIN
END main; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY ALU IS
PORT(
X : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
OP : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
FR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
RES : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END ALU;
ARCHITECTURE main OF ALU IS
BEGIN
END main; |
-- $Id: migui_artys7_gsim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: migui_artys7 - sim
-- Description: MIG generated for artys7 - simple simulator
--
-- Dependencies: bplib/mig/migui_core_gsim
-- Test bench: tb_tst_sram_artys7
-- Target Devices: artys7 board
-- Tool versions: viv 2018.3; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-12 1105 1.0 Initial version (cloned from migui_arty_gsim)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.miglib.all;
use work.miglib_artys7.all;
entity migui_artys7 is -- MIG generated for artys7
port (
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0);-- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI inital calibration complete
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end migui_artys7;
architecture sim of migui_artys7 is
begin
MIG_SIM : migui_core_gsim
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth,
SAWIDTH => 24,
CLKMUI_MUL => 7,
CLKMUI_DIV => 14)
port map (
SYS_CLK => SYS_CLK_I,
SYS_RST => SYS_RST,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK
);
DDR3_DQ <= (others=>'Z');
DDR3_DQS_P <= (others=>'Z');
DDR3_DQS_N <= (others=>'Z');
DDR3_ADDR <= (others=>'0');
DDR3_BA <= (others=>'0');
DDR3_RAS_N <= '1';
DDR3_CAS_N <= '1';
DDR3_WE_N <= '1';
DDR3_RESET_N <= '1';
DDR3_CK_P <= (others=>'0');
DDR3_CK_N <= (others=>'1');
DDR3_CKE <= (others=>'0');
DDR3_CS_N <= (others=>'1');
DDR3_DM <= (others=>'0');
DDR3_ODT <= (others=>'0');
APP_SR_ACTIVE <= '0';
end sim;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test real to integer conversion
library ieee;
use ieee.numeric_std.all;
entity vhdl_rtoi is
end;
architecture test of vhdl_rtoi is
signal a, b, c, d : integer;
begin
-- test rounding
a <= integer(2.3); -- should be 2
b <= integer(3.7); -- should be 4
c <= integer(4.5); -- should be 5
d <= integer(8.1 * 2.1); -- ==17.01, should be 17
end test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test real to integer conversion
library ieee;
use ieee.numeric_std.all;
entity vhdl_rtoi is
end;
architecture test of vhdl_rtoi is
signal a, b, c, d : integer;
begin
-- test rounding
a <= integer(2.3); -- should be 2
b <= integer(3.7); -- should be 4
c <= integer(4.5); -- should be 5
d <= integer(8.1 * 2.1); -- ==17.01, should be 17
end test;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test real to integer conversion
library ieee;
use ieee.numeric_std.all;
entity vhdl_rtoi is
end;
architecture test of vhdl_rtoi is
signal a, b, c, d : integer;
begin
-- test rounding
a <= integer(2.3); -- should be 2
b <= integer(3.7); -- should be 4
c <= integer(4.5); -- should be 5
d <= integer(8.1 * 2.1); -- ==17.01, should be 17
end test;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/29/2015 11:33:59 AM
-- Design Name:
-- Module Name: dsp_dff_block - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dsp_dff_block is
Generic (
WIDTH : natural
);
Port (
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0)
);
end dsp_dff_block;
architecture Behavioral of dsp_dff_block is
begin
process (RST, CLK)
begin
if RST = '1' then
Q <= (others => '0');
elsif (CLK'event AND CLK = '1') then
Q <= D;
end if;
end process;
end Behavioral;
|
-- Nothing should fail in this entity
entity ENT1 is
generic (
G_GENERIC1 : std_logic_vector(3 downto 0);
G_GENERIC2 : std_logic_vector(0 to 256)
);
port (
P_PORT1 : std_logic_vector(15 downto 6); -- DOWNTO
P_PORT2 : std_logic_vector(56 to 132)
);
end entity ENT1;
-- Everything should fail in this entity
entity ENT1 is
generic (
G_GENERIC1 : std_logic_vector(3 downto 0);
G_GENERIC2 : std_logic_vector(0 TO 256)
);
port (
P_PORT1 : std_logic_vector(15 downto 6);
P_PORT2 : std_logic_vector(56 tO 132)
);
end entity ENT1;
architecture ARCH of ENT1 is
constant c_const1 : std_logic_vector(3 downto 0); -- downto
constant c_const2 : std_logic_vector(3 downto 0);
constant c_const3 : std_logic_vector(345 To 670);
constant c_const4 : std_logic_vector(345 to 670);
signal w_sig1 : std_logic_vector(50 downto 45);
signal w_sig2 : std_logic_vector(50 downto 45);
signal w_sig3 : std_logic_vector(46 TO 345);
signal w_sig4 : std_logic_vector(46 to 345);
begin
end architecture ARCH;
|
-- Table that defines what register and data pairs to write to the OV7660 via
-- SCCB after startup. A delay is needed before writing the actual data
-- Also perform a register reset first of all in order to ensure that we know
-- what state we are writing. A simple FPGA flash might not reset the OV7660 firmware.
-- Copyright Erik Zachrisson - erik@zachrisson.info
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.OV76X0Pack.all;
entity OV7660Init is
port (
Clk : in bit1;
Rst_N : in bit1;
--
NextInst : in bit1;
--
We : out bit1;
Start : out bit1;
AddrData : out word(16-1 downto 0);
--
InstPtr : out word(InstPtrW-1 downto 0)
);
end entity;
architecture fpga of OV7660Init is
constant COM2 : word(8-1 downto 0) := x"09";
constant AECH : word(8-1 downto 0) := x"10";
constant CLKRC : word(8-1 downto 0) := x"11";
constant COM7 : word(8-1 downto 0) := x"12";
constant COM8 : word(8-1 downto 0) := x"13";
constant COM9 : word(8-1 downto 0) := x"14";
constant COM10 : word(8-1 downto 0) := x"15";
constant MVFP : word(8-1 downto 0) := x"1e";
constant TSLB : word(8-1 downto 0) := x"3a";
constant COM15 : word(8-1 downto 0) := x"40";
constant MANU : word(8-1 downto 0) := x"67";
constant MANV : word(8-1 downto 0) := x"68";
constant NbrOfInst : positive := 1;
signal InstPtr_N, InstPtr_D : word(InstPtrW-1 downto 0);
-- FIXME: Potentially listen for a number of vsync pulses instead. This would
-- same a number of flops
signal Delay_N, Delay_D : word(16-1 downto 0);
begin
SyncProc : process (Clk, Rst_N)
begin
if Rst_N = '0' then
InstPtr_D <= (others => '0');
if Simulation then
Delay_D <= "1111111111111100";
end if;
if Synthesis then
Delay_D <= (others => '0');
end if;
elsif rising_edge(Clk) then
InstPtr_D <= InstPtr_N;
Delay_D <= Delay_N;
end if;
end process;
ASyncProc : process (InstPtr_D, NextInst, Delay_D)
variable InstPtr_T : word(InstPtrW-1 downto 0);
begin
InstPtr_T := InstPtr_D;
AddrData <= (others => '0');
We <= '0';
Start <= '0';
Delay_N <= Delay_D + 1;
if (RedAnd(Delay_D) = '1') then
Delay_N <= Delay_D;
if (NextInst = '1') then
InstPtr_T := InstPtr_D + 1;
end if;
case InstPtr_D is
when "0000" =>
AddrData <= COM7 & x"80"; -- SCCB Register reset
We <= '1';
Start <= '1';
when "0001" =>
AddrData <= COM2 & x"00"; -- Enable 4x drive
We <= '1';
Start <= '1';
when "0010" =>
AddrData <= MVFP & x"10"; -- Flip image to it mount
We <= '1';
Start <= '1';
-- when "0001" =>
-- AddrData <= COM7 & x"00"; -- SCCB Register reset release
-- We <= '1';
-- Start <= '1';
--
-- when "0001" =>
-- AddrData <= COM7 & x"04"; -- Enable RGB
-- We <= '1';
-- Start <= '1';
----
-- when "0010" =>
-- AddrData <= COM15 & x"D0"; -- Enable RGB565
-- We <= '1';
-- Start <= '1';
-- when "0010" =>
-- AddrData <= AECH & x"01"; --
-- We <= '1';
-- Start <= '1';
-- when "0010" =>
-- AddrData <= COM8 & x"A9"; -- Enable banding filter, disable AGC
-- We <= '1';
-- Start <= '1';
-- when "0010" =>
-- AddrData <= CLKRC & x"80"; -- Reverse PCLK
-- We <= '1';
-- Start <= '1';
-- when "0010" =>
-- AddrData <= COM2 & x"11"; -- enable soft sleep
-- We <= '1';
-- Start <= '1';
-- when "0000" =>
-- AddrData <= TSLB & x"1C"; -- enable line buffer test option
-- We <= '1';
-- Start <= '1';
when others =>
InstPtr_T := (others => '1');
Start <= '0';
end case;
end if;
InstPtr_N <= InstPtr_T;
end process;
InstPtr <= InstPtr_D;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbtrace_mmb
-- File: ahbtrace_mmb.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB trace unit that can have registers on a separate bus and
-- select between several trace buses.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbtrace_mmb is
generic (
hindex : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#E00#;
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 1;
bwidth : integer := 32;
ahbfilt : integer := 0;
ntrace : integer range 1 to 8 := 1;
scantest : integer range 0 to 1 := 0;
exttimer : integer range 0 to 1 := 0;
exten : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type; -- Register interface
ahbso : out ahb_slv_out_type;
tahbmiv : in ahb_mst_in_vector_type(0 to ntrace-1); -- Trace
tahbsiv : in ahb_slv_in_vector_type(0 to ntrace-1);
timer : in std_logic_vector(30 downto 0);
astat : out amba_stat_type;
resen : in std_ulogic := '0'
);
end;
architecture rtl of ahbtrace_mmb is
constant TBUFABITS : integer := log2(kbytes) + 6;
constant TIMEBITS : integer := 32 - exttimer;
constant FILTEN : boolean := ahbfilt /= 0;
constant PERFEN : boolean := (ahbfilt > 1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBTRACE, 0, 0, irq),
4 => ahb_iobar (ioaddr, iomask),
others => zero32);
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS-1 downto 0);
data : std_logic_vector(255 downto 0);
enable : std_logic;
write : std_logic_vector(7 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(255 downto 0);
end record;
type trace_break_reg is record
addr : std_logic_vector(31 downto 2);
mask : std_logic_vector(31 downto 2);
read : std_logic;
write : std_logic;
end record;
type regtype is record
thaddr : std_logic_vector(31 downto 0);
thwrite : std_logic;
thtrans : std_logic_vector(1 downto 0);
thsize : std_logic_vector(2 downto 0);
thburst : std_logic_vector(2 downto 0);
thmaster : std_logic_vector(3 downto 0);
thmastlock : std_logic;
ahbactive : std_logic;
timer : std_logic_vector((TIMEBITS-1)*(1-exttimer) downto 0);
aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
hready : std_logic;
hready2 : std_logic;
hready3 : std_logic;
hsel : std_logic;
hwrite : std_logic;
haddr : std_logic_vector(TBUFABITS+4 downto 2);
hrdata : std_logic_vector(31 downto 0);
regacc : std_logic;
enable : std_logic; -- trace enable
bahb : std_logic; -- break on AHB watchpoint hit
bhit : std_logic; -- breakpoint hit
dcnten : std_logic; -- delay counter enable
delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
tbreg1 : trace_break_reg;
tbreg2 : trace_break_reg;
end record;
type pregtype is record
stat : amba_stat_type;
split : std_ulogic;
splmst : std_logic_vector(3 downto 0);
hready : std_ulogic;
hresp : std_logic_vector(1 downto 0);
end record;
type fregtype is record
shsel : std_logic_vector(0 to NAHBSLV-1);
pf : std_ulogic; -- Filter perf outputs
af : std_ulogic; -- Address filtering
fr : std_ulogic; -- Filter reads
fw : std_ulogic; -- Filter writes
smask : std_logic_vector(15 downto 0);
mmask : std_logic_vector(15 downto 0);
rf : std_ulogic; -- Retry filtering
end record;
type bregtype is record
bsel : std_logic_vector(log2(ntrace) downto 0);
end record;
function ahb_filt_hit (
r : regtype;
rf : fregtype;
hresp : std_logic_vector(1 downto 0)) return boolean is
variable hit : boolean;
begin
-- filter hit -> inhibit
hit := false;
-- Filter on read/write
if ((rf.fw and r.thwrite) or (rf.fr and not r.thwrite)) = '1' then
hit := true;
end if;
-- Filter on address range
if (((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) /= zero32(29 downto 0)) then
if rf.af = '1' then hit := true; end if;
end if;
-- Filter on master mask
for i in rf.mmask'range loop
if i > NAHBMST-1 then exit; end if;
if i = conv_integer(r.thmaster) and rf.mmask(i) = '1' then
hit := true;
end if;
end loop;
-- Filter on slave mask
for i in rf.smask'range loop
if i > NAHBSLV-1 then exit; end if;
if (rf.shsel(i) and rf.smask(i)) /= '0' then
hit := true;
end if;
end loop;
-- Filter on retry response
if (rf.rf = '1' and hresp = HRESP_RETRY) then
hit := true;
end if;
return hit;
end function ahb_filt_hit;
function getnrams return integer is
variable v: integer;
begin
v := 2;
if bwidth > 32 then v:=v+1; end if;
if bwidth > 64 then v:=v+1; end if;
return v;
end getnrams;
constant nrams: integer := getnrams;
subtype mtest64_vector is std_logic_vector(2*memtest_vlen-1 downto 0);
type mtest64_type is array(0 to 2) of mtest64_vector;
signal mtesti64, mtesto64: mtest64_type;
signal tbi : tracebuf_in_type;
signal tbo : tracebuf_out_type;
signal enable : std_logic_vector(1 downto 0);
signal r, rin : regtype;
signal rf, rfin : fregtype;
signal rb, rbin : bregtype;
signal pr, prin : pregtype;
begin
ctrl : process(rst, ahbsi, tahbmiv, tahbsiv, r, rf, rb, tbo, pr, timer, resen)
variable v : regtype;
variable vabufi : tracebuf_in_type;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
variable bphit : std_logic;
variable wdata, rdata : std_logic_vector(127 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable tahbmi : ahb_mst_in_type;
variable tahbsi : ahb_slv_in_type;
variable vf : fregtype;
variable vb : bregtype;
variable regaddr : std_logic_vector(4 downto 2);
variable tbaddr : std_logic_vector(3 downto 2);
variable timeval : std_logic_vector(31 downto 0);
variable pv : pregtype;
begin
v := r; regsd := (others => '0'); vabufi.enable := '0';
vabufi.data := (others => '0'); vabufi.addr := (others => '0');
vabufi.write := (others => '0'); bphit := '0';
v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
hirq := (others => '0'); hirq(irq) := r.bhit;
vf := rf; vb := rb; pv := pr;
if ntrace = 1 then
tahbmi := tahbmiv(0); tahbsi := tahbsiv(0);
else
tahbmi := tahbmiv(conv_integer(rb.bsel));
tahbsi := tahbsiv(conv_integer(rb.bsel));
end if;
regaddr := r.haddr(4 downto 2); --tbaddr := r.haddr(3 downto 2);
timeval := (others => '0');
timeval((TIMEBITS-1)*(1-exttimer) downto 0) := r.timer;
if exttimer /= 0 then
timeval(TIMEBITS-1 downto 0) := timer(TIMEBITS-1 downto 0);
end if;
-- trace buffer index and delay counters
if exttimer = 0 and r.enable = '1' then v.timer := r.timer + 1; end if;
aindex := r.aindex + 1;
-- check for AHB watchpoints
if (tahbsi.hready and r.ahbactive ) = '1' then
if ((((r.tbreg1.addr xor r.thaddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
(((r.tbreg1.read and not r.thwrite) or (r.tbreg1.write and r.thwrite)) = '1'))
or ((((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
(((r.tbreg2.read and not r.thwrite) or (r.tbreg2.write and r.thwrite)) = '1'))
then
if (r.enable = '1') and (r.dcnten = '0') and
(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
then v.dcnten := '1'; bphit := '1';
--else bphit := '1'; v.enable := '0'; end if;
elsif (r.enable = '1') and (r.dcnten = '0') then bphit := '1'; v.enable := '0'; end if;
end if;
end if;
-- generate buffer inputs
vabufi.write := "00000000";
wdata(AHBDW-1 downto 0) := tahbsi.hwdata;
rdata(AHBDW-1 downto 0) := tahbmi.hrdata;
if r.enable = '1' then
vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
vabufi.data(127 downto 96) := timeval;
vabufi.data(95) := bphit;
vabufi.data(94 downto 80) := (others => '0'); --tahbmi.hirq(15 downto 1);
vabufi.data(79) := r.thwrite;
vabufi.data(78 downto 77) := r.thtrans;
vabufi.data(76 downto 74) := r.thsize;
vabufi.data(73 downto 71) := r.thburst;
vabufi.data(70 downto 67) := r.thmaster;
vabufi.data(66) := r.thmastlock;
vabufi.data(65 downto 64) := tahbmi.hresp;
if r.thwrite = '1' then
vabufi.data(63 downto 32) := wdata(31 downto 0);
vabufi.data(223 downto 128) := wdata(127 downto 32);
else
vabufi.data(63 downto 32) := rdata(31 downto 0);
vabufi.data(223 downto 128) := rdata(127 downto 32);
end if;
vabufi.data(31 downto 0) := r.thaddr;
else
if bwidth = 32 then
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
else
vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+4 downto 5);
end if;
-- Note: HWDATA from register i/f
vabufi.data := hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata;
end if;
-- write trace buffer
if r.enable = '1' then
if (r.ahbactive and tahbsi.hready) = '1' then
if not (FILTEN and ahb_filt_hit(r, rf, tahbmi.hresp)) then
v.aindex := aindex;
vabufi.enable := '1'; vabufi.write := "11111111";
end if;
end if;
end if;
-- trace buffer delay counter handling
if (r.dcnten = '1') and (r.ahbactive and tahbsi.hready) = '1' then
if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
v.enable := '0'; v.dcnten := '0';
end if;
v.delaycnt := r.delaycnt - 1;
end if;
-- AHB statistics
if PERFEN then
pv.hready := tahbsi.hready;
pv.hresp := tahbmi.hresp;
pv.stat := amba_stat_none;
if pr.hready = '1' then
case r.thtrans is
when HTRANS_IDLE => pv.stat.idle := '1';
when HTRANS_BUSY => pv.stat.busy := '1';
when HTRANS_NONSEQ => pv.stat.nseq := '1';
when others => pv.stat.seq := '1';
end case;
if r.ahbactive = '1' then
pv.stat.read := not r.thwrite;
pv.stat.write := r.thwrite;
case r.thsize is
when HSIZE_BYTE => pv.stat.hsize(0) := '1';
when HSIZE_HWORD => pv.stat.hsize(1) := '1';
when HSIZE_WORD => pv.stat.hsize(2) := '1';
when HSIZE_DWORD => pv.stat.hsize(3) := '1';
when HSIZE_4WORD => pv.stat.hsize(4) := '1';
when others => pv.stat.hsize(5) := '1';
end case;
end if;
pv.stat.hmaster := r.thmaster;
end if;
if pr.hresp = HRESP_OKAY then
pv.stat.ws := not pr.hready;
end if;
-- It may also be interesting to count the maximum grant latency. That
-- is; the delay between asserting hbusreq and receiving hgrant. This
-- would require that all bus request signals were present in this
-- entity. This has been left as a possible future extension.
if pr.hready = '1' then
if pr.hresp = HRESP_SPLIT then
pv.stat.split := '1';
pv.split := '1';
if pr.split = '0' then
pv.splmst := r.thmaster;
end if;
end if;
if pr.hresp = HRESP_RETRY then
pv.stat.retry := '1';
end if;
end if;
pv.stat.locked := r.thmastlock;
if rf.pf = '1' and ahb_filt_hit(r, rf, tahbmi.hresp) then
pv.stat := amba_stat_none;
pv.split := pr.split; pv.splmst := pr.splmst;
end if;
-- Count cycles where master is in SPLIT
if pr.split = '1' then
for i in tahbmi.hgrant'range loop
if i = conv_integer(pr.splmst) and tahbmi.hgrant(i) = '1' then
pv.split := '0';
end if;
end loop;
pv.stat.spdel := pv.split;
end if;
end if;
-- save AHB transfer parameters
if (tahbsi.hready = '1' ) then
v.thaddr := tahbsi.haddr; v.thwrite := tahbsi.hwrite; v.thtrans := tahbsi.htrans;
v.thsize := tahbsi.hsize; v.thburst := tahbsi.hburst;
v.thmaster := tahbsi.hmaster; v.thmastlock := tahbsi.hmastlock;
v.ahbactive := tahbsi.htrans(1);
if FILTEN then vf.shsel := tahbsi.hsel; end if;
end if;
-- AHB transfer parameters for register accesses
if (ahbsi.hready = '1' ) then
v.haddr := ahbsi.haddr(TBUFABITS+4 downto 2); v.hwrite := ahbsi.hwrite;
v.regacc := ahbsi.haddr(16);
v.hsel := ahbsi.htrans(1) and ahbsi.hsel(hindex);
end if;
-- AHB slave access to DSU registers and trace buffers
if (r.hsel and not r.hready) = '1' then
if r.regacc = '0' then -- registers
v.hready := '1';
case regaddr is
when "000" =>
regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
if ntrace /= 1 then
regsd(15) := '1';
regsd(log2(ntrace)+12 downto 12) := vb.bsel;
end if;
regsd(7 downto 6) := conv_std_logic_vector(log2(bwidth/32), 2);
if FILTEN then
regsd(8) := rf.pf;
regsd(5) := rf.rf;
regsd(4) := rf.af;
regsd(3) := rf.fr;
regsd(2) := rf.fw;
end if;
regsd(1 downto 0) := r.dcnten & r.enable;
if r.hwrite = '1' then
v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
if ntrace /= 1 then
vb.bsel := ahbsi.hwdata(log2(ntrace)+12 downto 12);
end if;
if FILTEN then
vf.pf := ahbsi.hwdata(8);
vf.rf := ahbsi.hwdata(5);
vf.af := ahbsi.hwdata(4);
vf.fr := ahbsi.hwdata(3);
vf.fw := ahbsi.hwdata(2);
end if;
v.dcnten := ahbsi.hwdata(1);
v.enable := ahbsi.hwdata(0);
end if;
when "001" =>
regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
if r.hwrite = '1' then
v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
end if;
when "010" =>
regsd := timeval;
if exttimer = 0 and r.hwrite = '1' then
v.timer := ahbsi.hwdata((TIMEBITS- 1)*(1-exttimer) downto 0);
end if;
when "011" =>
if FILTEN then
regsd(31 downto 0) := rf.smask & rf.mmask;
if r.hwrite = '1' then
vf.smask := ahbsi.hwdata(31 downto 16);
vf.mmask := ahbsi.hwdata(15 downto 0);
end if;
end if;
when "100" =>
regsd(31 downto 2) := r.tbreg1.addr;
if r.hwrite = '1' then
v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
end if;
when "101" =>
regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
if r.hwrite = '1' then
v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
v.tbreg1.read := ahbsi.hwdata(1);
v.tbreg1.write := ahbsi.hwdata(0);
end if;
when "110" =>
regsd(31 downto 2) := r.tbreg2.addr;
if r.hwrite = '1' then
v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
end if;
when others =>
regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
if r.hwrite = '1' then
v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
v.tbreg2.read := ahbsi.hwdata(1);
v.tbreg2.write := ahbsi.hwdata(0);
end if;
end case;
v.hrdata := regsd;
else -- read/write access to trace buffer
if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
vabufi.enable := not r.enable;
case regaddr is
when "000" =>
v.hrdata := tbo.data(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
when "001" =>
v.hrdata := tbo.data(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
when "010" =>
v.hrdata := tbo.data(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
when "011" =>
v.hrdata := tbo.data(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
when "100" =>
if bwidth > 32 then
v.hrdata := tbo.data(159 downto 128);
if r.hwrite = '1' then
vabufi.write(7) := vabufi.enable;
end if;
else
v.hrdata := tbo.data(127 downto 96);
if r.hwrite = '1' then
vabufi.write(3) := vabufi.enable;
end if;
end if;
when "101" =>
if bwidth > 32 then
if bwidth > 64 then
v.hrdata := tbo.data(223 downto 192);
if r.hwrite = '1' then
vabufi.write(6) := vabufi.enable;
end if;
else v.hrdata := zero32; end if;
else
v.hrdata := tbo.data(95 downto 64);
if r.hwrite = '1' then
vabufi.write(2) := vabufi.enable;
end if;
end if;
when "110" =>
if bwidth > 32 then
if bwidth > 64 then
v.hrdata := tbo.data(191 downto 160);
if r.hwrite = '1' then
vabufi.write(5) := vabufi.enable;
end if;
else v.hrdata := zero32; end if;
else
v.hrdata := tbo.data(63 downto 32);
if r.hwrite = '1' then
vabufi.write(1) := vabufi.enable;
end if;
end if;
when others =>
if bwidth > 32 then
v.hrdata := zero32;
else
v.hrdata := tbo.data(31 downto 0);
if r.hwrite = '1' then
vabufi.write(0) := vabufi.enable;
end if;
end if;
end case;
end if;
end if;
if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
then v.hready := '1'; end if;
if rst = '0' then
v.ahbactive := '0';
if exten /= 0 then v.enable := resen;
else v.enable := '0'; end if;
v.timer := (others => '0');
v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
v.regacc := '0'; v.hready := '1';
v.tbreg1.read := '0'; v.tbreg1.write := '0';
v.tbreg2.read := '0'; v.tbreg2.write := '0';
if FILTEN then
vf.smask := (others => '0'); vf.mmask := (others => '0');
end if;
if PERFEN then
pv.split := '0'; pv.splmst := (others => '0');
end if;
if ntrace /= 1 then vb.bsel := (others => '0'); end if;
end if;
if PERFEN then astat <= pr.stat; else astat <= amba_stat_none; end if;
tbi <= vabufi;
rin <= v; rfin <= vf; rbin <= vb; prin <= pv;
ahbso.hconfig <= hconfig;
ahbso.hirq <= hirq;
ahbso.hsplit <= (others => '0');
ahbso.hrdata <= ahbdrivedata(r.hrdata);
ahbso.hready <= r.hready;
ahbso.hindex <= hindex;
end process;
ahbso.hresp <= HRESP_OKAY;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
fregs : if FILTEN generate
regs : process(clk)
begin if rising_edge(clk) then rf <= rfin; end if; end process;
end generate;
nofregs : if not FILTEN generate
rf.shsel <= (others => '0');
rf.pf <= '0';
rf.af <= '0';
rf.fr <= '0';
rf.fw <= '0';
rf.smask <= (others => '0');
rf.mmask <= (others => '0');
rf.rf <= '0';
end generate;
perf : if PERFEN generate
preg : process(clk)
begin
if rising_edge(clk) then
pr <= prin;
end if;
end process;
end generate;
noperf : if not PERFEN generate
pr.stat <= amba_stat_none;
pr.split <= '0';
pr.splmst <= (others => '0');
pr.hready <= '0';
pr.hresp <= (others => '0');
end generate;
bregs : if ntrace /= 1 generate
regs : process(clk)
begin if rising_edge(clk) then rb <= rbin; end if; end process;
end generate;
nobregs : if ntrace = 1 generate
rb.bsel <= (others => '0');
end generate;
enable <= tbi.enable & tbi.enable;
mem32 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS, testen => scantest, custombits => memtest_vlen)
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2),
ahbsi.testin
);
end generate;
mem64 : if bwidth > 32 generate -- extra data buffer for 64-bit bus
ram0 : syncram generic map (tech => tech, abits => TBUFABITS, dbits => 32, testen => scantest, custombits => memtest_vlen)
port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+31) downto 128),
tbo.data((128+31) downto 128), tbi.enable, tbi.write(7),
ahbsi.testin
);
end generate;
mem128 : if bwidth > 64 generate -- extra data buffer for 128-bit bus
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS, testen => scantest, custombits => memtest_vlen)
port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+95) downto (128+32)),
tbo.data((128+95) downto (128+32)), enable, tbi.write(6 downto 5),
ahbsi.testin
);
end generate;
nomem64 : if bwidth < 64 generate -- no extra data buffer for 64-bit bus
tbo.data((128+31) downto 128) <= (others => '0');
end generate;
nomem128 : if bwidth < 128 generate -- no extra data buffer for 128-bit bus
tbo.data((128+95) downto (128+32)) <= (others => '0');
end generate;
tbo.data(255 downto 224) <= (others => '0');
-- pragma translate_off
bootmsg : report_version
generic map ("ahbtrace" & tost(hindex) &
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
--
-- File : imx51_wb16_wrapper.vhd
-- Related files : (none)
--
-- Author(s) : Fabien Marteau <fabien.marteau@armadeus.com>
-- Project : i.MX51 wrapper to Wishbone bus
--
-- Creation Date : 17/12/2010
--
-- Description : This is the top file of the IP
-------------------------------------------------------------------------------
-- Modifications :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Entity imx51_wb16_wrapper is
port
(
-- i.MX Signals
imx_da : inout std_logic_vector(15 downto 0);
imx_cs_n : in std_logic;
imx_rw : in std_logic;
imx_adv : in std_logic;
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-- Wishbone interface signals
wbm_clk : out std_logic;
wbm_rst : out std_logic;
wbm_address : out std_logic_vector(15 downto 0); -- Address bus
wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
Architecture RTL of imx51_wb16_wrapper is
signal write : std_logic;
signal read : std_logic;
signal strobe : std_logic;
signal writedata : std_logic_vector(15 downto 0);
signal address : std_logic_vector(15 downto 0);
begin
wbm_clk <= gls_clk;
wbm_rst <= gls_reset;
-- External signals synchronization process
process(gls_clk, gls_reset)
begin
if(gls_reset='1') then
writedata <= (others => '0');
address <= (others => '0');
elsif(rising_edge(gls_clk)) then
if (imx_adv = '0') then
address <= imx_da;
else
writedata <= imx_da;
end if;
end if;
end process;
strobe <= not (imx_cs_n);
write <= (not (imx_cs_n)) and (not(imx_rw));
read <= (not (imx_cs_n)) and imx_rw;
wbm_address <= address;
wbm_writedata <= writedata when (write = '1') else (others => '0');
wbm_strobe <= strobe;
wbm_write <= write;
wbm_cycle <= strobe;
imx_da <= wbm_readdata when ((read = '1') and (strobe = '1')) else (others => 'Z');
end architecture RTL;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e.vhd,v 1.3 2005/11/30 14:04:04 wig Exp $
-- $Date: 2005/11/30 14:04:04 $
-- $Log: inst_ab_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:04 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ab_e
--
entity inst_ab_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_ab_e
FOO : integer := 64; -- Generic width for entity
WIDTH : integer -- apply generic value 31 to inst_ab __W_NODEFAULT
-- End of Generated Generics for Entity inst_ab_e
);
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ab_e
end inst_ab_e;
--
-- End of Generated Entity inst_ab_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company: US
-- Engineer: Pedro Morales Hernandez
--
-- Create Date: 19:32:08 06/07/2015
-- Design Name:
-- Module Name: PRBS - Behavioral
-- Project Name: OFDM
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PRBS is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC);
end PRBS;
architecture Behavioral of PRBS is
signal registro : STD_LOGIC_VECTOR(10 DOWNTO 0);
signal p_registro : STD_LOGIC_VECTOR(10 DOWNTO 0);
begin
comb: process (registro, enable)
begin
if(enable = '1') then
p_registro(10 DOWNTO 1) <= registro(9 DOWNTO 0);
p_registro(0) <= registro(10) XOR registro(8);
else
p_registro <= registro;
end if;
end process;
output <= registro(10);
seq: process(clk,rst)
begin
if(rst = '1') then
registro <= (OTHERS => '1');
elsif(rising_edge(clk)) then
registro <= p_registro;
end if;
end process;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY blah IS
GENERIC (
g_blah : STD_LOGIC
);
PORT (
i_input : IN STD_LOGIC;
o_output : OUT STD_LOGIC;
io_inout : INOUT STD_LOGIC
);
END ENTITY blah;
ARCHITECTURE rtl OF blah IS
CONSTANT con_a : STD_LOGIC;
SIGNAL sig_a : STD_LOGIC;
COMPONENT comp_1 IS
GENERIC (
g_gen_1 : INTEGER
);
PORT (
i_input : IN INTEGER;
o_output : OUT STD_LOGIC;
io_inout : INOUT INTEGER
);
END COMPONENT comp_1;
BEGIN
proc_label : PROCESS (Ab, Cd, Ef) IS
VARIABLE var_a : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
a <= b OR c AND d XOR e;
END PROCESS proc_label;
u_inst : COMPONENT my_comp
GENERIC MAP (
g_gen_1 => 1
)
PORT MAP (
i_input => W_sig_1
);
END ARCHITECTURE rtl;
PACKAGE some_pkg IS
PROCEDURE proc_1;
FUNCTION func_1 Return INTEGER;
END PACKAGE some_pkg;
PACKAGE BODY some_pkg_body IS
PROCEDURE proc_1 IS
BEGIN
END PROCEDURE proc_1;
END PACKAGE BODY some_pkg_body;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY blah IS
GENERIC (
g_blah : STD_LOGIC
);
PORT (
i_input : IN STD_LOGIC;
o_output : OUT STD_LOGIC;
io_inout : INOUT STD_LOGIC
);
END ENTITY blah;
ARCHITECTURE rtl OF blah IS
CONSTANT con_a : STD_LOGIC;
SIGNAL sig_a : STD_LOGIC;
COMPONENT comp_1 IS
GENERIC (
g_gen_1 : INTEGER
);
PORT (
i_input : IN INTEGER;
o_output : OUT STD_LOGIC;
io_inout : INOUT INTEGER
);
END COMPONENT comp_1;
BEGIN
proc_label : PROCESS (Ab, Cd, Ef) IS
VARIABLE var_a : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
a <= b OR c AND d XOR e;
END PROCESS proc_label;
u_inst : COMPONENT my_comp
GENERIC MAP (
g_gen_1 => 1
)
PORT MAP (
i_input => W_sig_1
);
END ARCHITECTURE rtl;
PACKAGE some_pkg IS
PROCEDURE proc_1;
FUNCTION func_1 Return INTEGER;
END PACKAGE some_pkg;
PACKAGE BODY some_pkg_body IS
PROCEDURE proc_1 IS
BEGIN
END PROCEDURE proc_1;
END PACKAGE BODY some_pkg_body;
|
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