content stringlengths 1 1.04M ⌀ |
|---|
architecture RTL of FIFO is
begin
block_label : block is begin end block block_label;
block_label : BLOCK IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
|
-- $Id: sys_conf.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_atlys (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
-- $Id: sys_conf.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_atlys (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
component mi_nios is
port (
clk_clk : in std_logic := 'X'; -- clk
flash_dclk : out std_logic; -- dclk
flash_sce : out std_logic; -- sce
flash_sdo : out std_logic; -- sdo
flash_data0 : in std_logic := 'X'; -- data0
led_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_addr : out std_logic_vector(11 downto 0); -- addr
sdram_ba : out std_logic_vector(1 downto 0); -- ba
sdram_cas_n : out std_logic; -- cas_n
sdram_cke : out std_logic; -- cke
sdram_cs_n : out std_logic; -- cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_ras_n : out std_logic; -- ras_n
sdram_we_n : out std_logic; -- we_n
sdram_clk_clk : out std_logic; -- clk
sw_export : in std_logic_vector(3 downto 0) := (others => 'X') -- export
);
end component mi_nios;
u0 : component mi_nios
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
flash_dclk => CONNECTED_TO_flash_dclk, -- flash.dclk
flash_sce => CONNECTED_TO_flash_sce, -- .sce
flash_sdo => CONNECTED_TO_flash_sdo, -- .sdo
flash_data0 => CONNECTED_TO_flash_data0, -- .data0
led_export => CONNECTED_TO_led_export, -- led.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_addr => CONNECTED_TO_sdram_addr, -- sdram.addr
sdram_ba => CONNECTED_TO_sdram_ba, -- .ba
sdram_cas_n => CONNECTED_TO_sdram_cas_n, -- .cas_n
sdram_cke => CONNECTED_TO_sdram_cke, -- .cke
sdram_cs_n => CONNECTED_TO_sdram_cs_n, -- .cs_n
sdram_dq => CONNECTED_TO_sdram_dq, -- .dq
sdram_dqm => CONNECTED_TO_sdram_dqm, -- .dqm
sdram_ras_n => CONNECTED_TO_sdram_ras_n, -- .ras_n
sdram_we_n => CONNECTED_TO_sdram_we_n, -- .we_n
sdram_clk_clk => CONNECTED_TO_sdram_clk_clk, -- sdram_clk.clk
sw_export => CONNECTED_TO_sw_export -- sw.export
);
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:13:56 09/26/2017
-- Design Name:
-- Module Name: PC - arqPC
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC is
Port ( inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture arqPC of PC is
begin
process(Clk,Reset,inPC)
begin
if(Reset = '1')then
outPC<="00000000000000000000000000000000";
else
if(rising_edge(Clk)) then
outPC<=inPC;
end if;
end if;
end process;
end arqPC;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:13:56 09/26/2017
-- Design Name:
-- Module Name: PC - arqPC
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PC is
Port ( inPC : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Clk : in STD_LOGIC;
outPC : out STD_LOGIC_VECTOR (31 downto 0));
end PC;
architecture arqPC of PC is
begin
process(Clk,Reset,inPC)
begin
if(Reset = '1')then
outPC<="00000000000000000000000000000000";
else
if(rising_edge(Clk)) then
outPC<=inPC;
end if;
end if;
end process;
end arqPC;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if rising_edge(clk) then
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
state <= STATE_IDLE;
else
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end if;
end process;
end Behavioral;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if rising_edge(clk) then
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
state <= STATE_IDLE;
else
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end if;
end process;
end Behavioral;
|
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <luebbers@reconos.de>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if rising_edge(clk) then
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
state <= STATE_IDLE;
else
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity car_sequencer is
port(
main_clk, reset: in std_logic;
i2s_lr_st: in std_logic;
--
lvds_io: inout std_logic;
--
i2s_spkr_dat: in std_logic;
i2s_spkr_sh, i2s_spkr_ld: out std_logic;
i2s_mic_ld, i2s_mic_sh, i2s_mic_dat: out std_logic;
--
spi_sck, spi_mosi, spi_cs0_n, spi_cs1_n: in std_logic;
spi_miso: out std_logic;
--
fmexg_mic_sync: in std_logic;
muted: in std_logic;
--
test_djb_present: out std_logic
);
end entity;
architecture a of car_sequencer is
signal lvdscounter: unsigned(4 downto 0);
signal djb_present: std_logic;
signal djb_got16: std_logic;
begin
test_djb_present <= djb_present;
process(main_clk, reset) is begin
if reset = '1' then
-- Initialize signals
lvdscounter <= (others => '1');
djb_present <= '0';
djb_got16 <= '1';
--
lvds_io <= '0';
--
i2s_spkr_sh <= '0';
i2s_spkr_ld <= '0';
i2s_mic_ld <= '0';
i2s_mic_sh <= '0';
i2s_mic_dat <= '0';
--
spi_miso <= '0';
elsif falling_edge(main_clk) then
-- Capture data on falling edge
-- The following signals will be in registers triggered on falling edge:
i2s_mic_ld <= '0';
i2s_mic_sh <= '0';
i2s_mic_dat <= '0';
-- Also spi_miso which keeps its last state
-- Bits of LVDS packet
case to_integer(lvdscounter) is
when 16 =>
djb_got16 <= lvds_io;
when 17 =>
-- Make sure DJB responded with 0-1 transition
if djb_got16 = '0' and lvds_io = '1' then
djb_present <= '1';
else
djb_present <= '0';
end if;
when 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 =>
if djb_present = '1' then
i2s_mic_dat <= '0' when fmexg_mic_sync = '1' else lvds_io;
i2s_mic_sh <= '1';
end if;
when 26 =>
if djb_present = '1' then
i2s_mic_ld <= '1';
spi_miso <= lvds_io;
else
spi_miso <= '0';
end if;
when others =>
null; --handled below
end case;
elsif rising_edge(main_clk) then
-- Signal default values:
i2s_spkr_ld <= '0';
i2s_spkr_sh <= '0';
-- State change on rising edge
if djb_present = '1' then
-- Normal mode
case to_integer(lvdscounter)+1 is --Plus 1 because this is looking at the last value of the counter
when 0 | 32 =>
lvds_io <= '0';
when 1 =>
lvds_io <= '1';
i2s_spkr_ld <= '1';
when 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 =>
lvds_io <= '0' when muted = '1' else i2s_spkr_dat;
i2s_spkr_sh <= '1'; --Should actually be '0' for 9, but doesn't matter if we shift an extra 0 around
when 10 =>
lvds_io <= i2s_lr_st;
when 11 =>
lvds_io <= spi_sck;
when 12 =>
lvds_io <= spi_mosi;
when 13 =>
lvds_io <= spi_cs0_n;
when 14 =>
lvds_io <= spi_cs1_n;
when 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 =>
lvds_io <= 'Z';
when others =>
lvds_io <= '0';
end case;
else
-- If DJB not connected, send all normally-driven data as 0s, so the only
-- possible rising edge is the correct one at the beginning
case to_integer(lvdscounter)+1 is --Plus 1 because this is looking at the last value of the counter
when 0 | 32 =>
lvds_io <= '0';
when 1 =>
lvds_io <= '1';
when 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 =>
lvds_io <= '0';
when 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 =>
lvds_io <= 'Z';
when others =>
lvds_io <= '0';
end case;
end if;
lvdscounter <= lvdscounter + 1;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.std_logic;
use ieee.std_logic_1164.to_x01;
use ieee.std_logic_1164.is_x;
package std_logic_warning is
function "="(l, r : std_logic) return boolean;
end package;
package body std_logic_warning is
use ieee.std_logic_1164."=";
function "="(l, r : std_logic) return boolean is
begin
if is_x(l) or is_x(r) then
report "std_logic_warning.""="": metavalue detected, returning FALSE"
severity WARNING;
return FALSE;
end if;
return l = r; -- std_logic_1164."="(l, r);
end function;
end package body;
library ieee;
use ieee.std_logic_1164.std_ulogic;
use ieee.std_logic_1164.std_logic;
-- use ieee.std_logic_1164.all;
use work.std_logic_warning.all;
entity warning_test is
end entity;
architecture foo of warning_test is
signal a: std_logic;
signal b: std_logic;
begin
UNLABELLED:
process
begin
wait for 1 ns;
a <= 'X';
wait for 1 ns;
b <= '1';
wait for 1 ns;
a <= '0';
wait for 1 ns;
b <= '0';
wait;
end process;
MONITOR:
process (a,b)
begin
assert a = b
report "a = b " & "( " & std_logic'image(a)
& "=" & std_logic'image(b) & " )"
severity NOTE;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_t_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-e.vhd,v 1.1 2004/04/06 10:50:12 wig Exp $
-- $Date: 2004/04/06 10:50:12 $
-- $Log: inst_t_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:12 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_t_e
--
entity inst_t_e is
-- Generics:
-- No Generated Generics for Entity inst_t_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_t_e
cgs_ramclk : out std_ulogic;
nreset : out std_ulogic;
si_vclkx2 : in std_ulogic;
tmu_dac_reset : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_t_e
);
end inst_t_e;
--
-- End of Generated Entity inst_t_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Vhdl test bench created from schematic C:\Users\fafik\Dropbox\infa\git\ethernet\ethernet4b\stupid.sch - Sun Aug 24 00:48:15 2014
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY stupid_stupid_sch_tb IS
END stupid_stupid_sch_tb;
ARCHITECTURE behavioral OF stupid_stupid_sch_tb IS
COMPONENT stupid
PORT( clk : IN STD_LOGIC;
start : IN STD_LOGIC;
test : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL start : STD_LOGIC;
SIGNAL test : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
UUT: stupid PORT MAP(
clk => clk,
start => start,
test => test
);
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
start <= '1', '0' after 20 ns;
END;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_02 is
end entity test_bench_04_02;
----------------------------------------------------------------
architecture test_and_multiple_behavioral of test_bench_04_02 is
-- code from book:
signal count_value : bit_vector(7 downto 0);
signal terminal_count : bit;
-- end of code from book
begin
-- code from book:
tc_gate : entity work.and_multiple(behavioral)
port map ( i => count_value, y => terminal_count);
-- end of code from book
stumulus : process is
begin
wait for 10 ns;
count_value <= "10000000"; wait for 10 ns;
count_value <= "11111110"; wait for 10 ns;
count_value <= "01111111"; wait for 10 ns;
count_value <= "11111111"; wait for 10 ns;
count_value <= "00000000"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_and_multiple_behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_02 is
end entity test_bench_04_02;
----------------------------------------------------------------
architecture test_and_multiple_behavioral of test_bench_04_02 is
-- code from book:
signal count_value : bit_vector(7 downto 0);
signal terminal_count : bit;
-- end of code from book
begin
-- code from book:
tc_gate : entity work.and_multiple(behavioral)
port map ( i => count_value, y => terminal_count);
-- end of code from book
stumulus : process is
begin
wait for 10 ns;
count_value <= "10000000"; wait for 10 ns;
count_value <= "11111110"; wait for 10 ns;
count_value <= "01111111"; wait for 10 ns;
count_value <= "11111111"; wait for 10 ns;
count_value <= "00000000"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_and_multiple_behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_02 is
end entity test_bench_04_02;
----------------------------------------------------------------
architecture test_and_multiple_behavioral of test_bench_04_02 is
-- code from book:
signal count_value : bit_vector(7 downto 0);
signal terminal_count : bit;
-- end of code from book
begin
-- code from book:
tc_gate : entity work.and_multiple(behavioral)
port map ( i => count_value, y => terminal_count);
-- end of code from book
stumulus : process is
begin
wait for 10 ns;
count_value <= "10000000"; wait for 10 ns;
count_value <= "11111110"; wait for 10 ns;
count_value <= "01111111"; wait for 10 ns;
count_value <= "11111111"; wait for 10 ns;
count_value <= "00000000"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_and_multiple_behavioral;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--! Package which provides functions to create Look Up Tables for various functions
--! The generated Look Up Table can be placed in a lookup_table entity.
--! \see lookup_table
package curves_pkg is
--! Bit depth of pixels
constant wordsize : integer := 8;
--! \brief array of std_logic_vectors
type array_pixel is array (natural range <>) of std_logic_vector(wordsize-1 downto 0);
----------------------------------------------------------------------
--! Function to create Look up table for a straight line
--! Used for testing purposes, creates a straight line.
--! The straight function is \f[p_{out}=c*p_{in} \f]
--! \param[in] size Number of elements to create
--! \param[in] c Amplification factor
--! \image html straight.png
function create_straight_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a negated line
--! The negate function is \f[p_{out}=p_{max}-p_{in} \f]
--! \param[in] size Number of elements to create
--! \image html negate.png
function create_negated_lut( size: integer)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a sigmoid function
--! The sigmoid function is \f[p_{out}=\frac{p_{max}}{1+\exp({-c/p_{max}*(p_{in}-p_{max})})} \f]
--! \param[in] size Number of elements to create
--! \param[in] c Amplification factor
--! \image html sigmoid.png
function create_sigmoid_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a gamma function
--! The gamma function is \f[p_{out}=c*p_{max}*(\frac{p_{in}}{p_{max}})^{\gamma} \f]
--! \param[in] size Number of elements to create
--! \param[in] gamma Gamma factor
--! \param[in] c Amplification factor
--! \image html gamma.png
function create_gamma_lut( size: integer;
gamma: real := 1.0;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a sine function
--! The sine function is \f[p_{out}=p_{max} * sin^c\left (\frac{\pi*x}{width} \right)\f]
--! \param[in] size Number of elements to create
--! \param[in] c Order
--! \image html vignette_curve.png
function create_sine_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Procedure to assert that value can be represented in bit range
--! \param[in] value Value to compare
--! \param[in] wordsize Bit depth
procedure verify_valid_value( variable value: in real;
constant wordsize: in integer);
----------------------------------------------------------------------
--! Procedure to pretty print out a LUT value
--! \param[in] value Value to be printed
--! \param[in] index Index to print
procedure report_lut_value( variable value: in real;
constant index: in integer);
end curves_pkg;
package body curves_pkg is
--======================================================================================--
function create_straight_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable calc_val: real := 0.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := c * real(i);
calc_val := realmin( calc_val, real( 2**wordsize ) - 1.0 );
calc_val := realmax( calc_val, 0.0 );
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_straight_lut;
--======================================================================================--
function create_negated_lut( size: integer)
return array_pixel is
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := max_val-real(i);
-- report_lut_value( calc_val, i);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_negated_lut;
--======================================================================================--
function create_sigmoid_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable exponent: real := 0.0;
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
exponent := (c/max_val)*(real(i) - max_val * 0.5 );
calc_val := ceil(max_val / (real(1) + exp(-exponent)));
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_sigmoid_lut;
--======================================================================================--
function create_gamma_lut( size: integer;
gamma: real := 1.0;
c: real := 1.0)
return array_pixel is
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := c*max_val*(real(i)/max_val)**gamma;
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_gamma_lut;
--======================================================================================--
function create_sine_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable exponent: real := 0.0;
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := max_val * sin( math_pi * real(i) / real(size))**c;
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_sine_lut;
--======================================================================================--
procedure verify_valid_value( variable value: in real;
constant wordsize: in integer) is
constant max_val : integer := integer(2**wordsize)-1;
begin
assert(integer(value) <= max_val) report "LUT filled with invalid value: " & integer'image(integer(value)) severity failure;
assert(integer(value) >= 0) report "LUT filled with invalid value" severity failure;
end procedure verify_valid_value;
--======================================================================================--
procedure report_lut_value( variable value: in real;
constant index: in integer) is
begin
report "LUT[" & integer'image(index) & "]: " & integer'image(integer(value));
end procedure report_lut_value;
end curves_pkg;
|
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--! Package which provides functions to create Look Up Tables for various functions
--! The generated Look Up Table can be placed in a lookup_table entity.
--! \see lookup_table
package curves_pkg is
--! Bit depth of pixels
constant wordsize : integer := 8;
--! \brief array of std_logic_vectors
type array_pixel is array (natural range <>) of std_logic_vector(wordsize-1 downto 0);
----------------------------------------------------------------------
--! Function to create Look up table for a straight line
--! Used for testing purposes, creates a straight line.
--! The straight function is \f[p_{out}=c*p_{in} \f]
--! \param[in] size Number of elements to create
--! \param[in] c Amplification factor
--! \image html straight.png
function create_straight_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a negated line
--! The negate function is \f[p_{out}=p_{max}-p_{in} \f]
--! \param[in] size Number of elements to create
--! \image html negate.png
function create_negated_lut( size: integer)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a sigmoid function
--! The sigmoid function is \f[p_{out}=\frac{p_{max}}{1+\exp({-c/p_{max}*(p_{in}-p_{max})})} \f]
--! \param[in] size Number of elements to create
--! \param[in] c Amplification factor
--! \image html sigmoid.png
function create_sigmoid_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a gamma function
--! The gamma function is \f[p_{out}=c*p_{max}*(\frac{p_{in}}{p_{max}})^{\gamma} \f]
--! \param[in] size Number of elements to create
--! \param[in] gamma Gamma factor
--! \param[in] c Amplification factor
--! \image html gamma.png
function create_gamma_lut( size: integer;
gamma: real := 1.0;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Function to create Look up table for a sine function
--! The sine function is \f[p_{out}=p_{max} * sin^c\left (\frac{\pi*x}{width} \right)\f]
--! \param[in] size Number of elements to create
--! \param[in] c Order
--! \image html vignette_curve.png
function create_sine_lut( size: integer;
c: real := 1.0)
return array_pixel;
----------------------------------------------------------------------
--! Procedure to assert that value can be represented in bit range
--! \param[in] value Value to compare
--! \param[in] wordsize Bit depth
procedure verify_valid_value( variable value: in real;
constant wordsize: in integer);
----------------------------------------------------------------------
--! Procedure to pretty print out a LUT value
--! \param[in] value Value to be printed
--! \param[in] index Index to print
procedure report_lut_value( variable value: in real;
constant index: in integer);
end curves_pkg;
package body curves_pkg is
--======================================================================================--
function create_straight_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable calc_val: real := 0.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := c * real(i);
calc_val := realmin( calc_val, real( 2**wordsize ) - 1.0 );
calc_val := realmax( calc_val, 0.0 );
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_straight_lut;
--======================================================================================--
function create_negated_lut( size: integer)
return array_pixel is
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := max_val-real(i);
-- report_lut_value( calc_val, i);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_negated_lut;
--======================================================================================--
function create_sigmoid_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable exponent: real := 0.0;
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
exponent := (c/max_val)*(real(i) - max_val * 0.5 );
calc_val := ceil(max_val / (real(1) + exp(-exponent)));
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_sigmoid_lut;
--======================================================================================--
function create_gamma_lut( size: integer;
gamma: real := 1.0;
c: real := 1.0)
return array_pixel is
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := c*max_val*(real(i)/max_val)**gamma;
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_gamma_lut;
--======================================================================================--
function create_sine_lut( size: integer;
c: real := 1.0)
return array_pixel is
variable exponent: real := 0.0;
variable calc_val: real := 0.0;
constant max_val: real := real(2**wordsize)-1.0;
variable return_value: array_pixel(0 to size-1);
begin
for i in return_value'range loop
calc_val := max_val * sin( math_pi * real(i) / real(size))**c;
-- report_lut_value( calc_val, i);
verify_valid_value(calc_val, wordsize);
return_value(i) := std_logic_vector(to_unsigned(integer(calc_val), wordsize));
end loop;
return return_value;
end create_sine_lut;
--======================================================================================--
procedure verify_valid_value( variable value: in real;
constant wordsize: in integer) is
constant max_val : integer := integer(2**wordsize)-1;
begin
assert(integer(value) <= max_val) report "LUT filled with invalid value: " & integer'image(integer(value)) severity failure;
assert(integer(value) >= 0) report "LUT filled with invalid value" severity failure;
end procedure verify_valid_value;
--======================================================================================--
procedure report_lut_value( variable value: in real;
constant index: in integer) is
begin
report "LUT[" & integer'image(index) & "]: " & integer'image(integer(value));
end procedure report_lut_value;
end curves_pkg;
|
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_mdio.vhd
-- Author : liyi <alxiuyain@foxmail.com>
-- Company : OE@HUST
-- Created : 2012-12-02
-- Last update: 2012-12-02
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-12-02 1.0 liyi Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_mdio IS
PORT (
iWbClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
---------------------------------------------------------------------------
-- signals from register file
---------------------------------------------------------------------------
iPHYAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
iRegAddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
iNoPre : IN STD_LOGIC;
iData2PHY : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
iClkDiv : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRdOp : IN STD_LOGIC;
iWrOp : IN STD_LOGIC;
---------------------------------------------------------------------------
-- signals to register file
---------------------------------------------------------------------------
oDataFromPHY : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); -- data from PHY registers
oDataFromPHYValid : OUT STD_LOGIC; -- only valid for 1 clock cycle
oClrRdOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
oClrWrOp : OUT STD_LOGIC; -- only valid for 1 clock cycle
oMDIOBusy : OUT STD_LOGIC; -- manegement is busy
---------------------------------------------------------------------------
-- Management interface
---------------------------------------------------------------------------
iMDI : IN STD_LOGIC;
oMDHz : OUT STD_LOGIC; -- mdio is in HighZ state
oMDC : OUT STD_LOGIC
);
END ENTITY rgmii_mdio;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_mdio IS
SIGNAL rdPend, wrPend : STD_LOGIC;
SIGNAL endOp : STD_LOGIC;
SIGNAL busy : STD_LOGIC;
SIGNAL sendEn : BOOLEAN; -- Data is output on sendEn. Delay it slightly from the
--clock to ensure setup and hold timing is met
SIGNAL receiveEn : BOOLEAN; -- Sample read data just before rising edge of MDC
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
-- receive command from wishbone
-----------------------------------------------------------------------------
oMDIOBusy <= busy;
busy <= wrPend OR rdPend;
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rdPend <= '0';
wrPend <= '0';
oClrWrOp <= '0';
oClrRdOp <= '0';
ELSIF rising_edge(iWbClk) THEN
oClrWrOp <= '0';
oClrRdOp <= '0';
IF busy = '0' THEN
IF iRdOp = '1' THEN
rdPend <= '1';
oClrRdOp <= '1';
ELSIF iWrOp = '1' THEN
wrPend <= '1';
oClrWrOp <= '1';
END IF;
ELSIF endOp = '1' THEN
rdPend <= '0';
wrPend <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MDC generation
-----------------------------------------------------------------------------
mdcGen : BLOCK IS
SIGNAL mdc : STD_LOGIC;
SIGNAL mdcClkDiv : INTEGER RANGE 0 TO 127;
SIGNAL clkDivTmp : INTEGER RANGE 0 TO 126;
BEGIN -- BLOCK mdc
oMDC <= mdc;
clkDivTmp <= 1 WHEN iClkDiv < 4 ELSE (conv_integer(iClkDiv(7 DOWNTO 1))-1);
sendEn <= mdc = '1' AND mdcClkDiv = 0; -- falling edge send
receiveEn <= mdc = '0' AND mdcClkDiv = 0; -- rising edge receive
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
mdc <= '0';
mdcClkDiv <= 0;
ELSIF rising_edge(iWbClk) THEN
IF mdcClkDiv = 0 THEN
mdcClkDiv <= clkDivTmp;
mdc <= NOT mdc;
ELSE
mdcClkDiv <= mdcClkDiv - 1;
END IF;
END IF;
END PROCESS;
END BLOCK mdcGen;
operation : BLOCK IS
TYPE state_t IS (PREAMBLE, IDLE, CTRL, WRITE, READ);
SIGNAL state : state_t;
SIGNAL bitCnt : INTEGER RANGE 0 TO 31;
SIGNAL shiftReg : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN -- BLOCK operation
PROCESS (iWbClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oMDHz <= '1';
state <= PREAMBLE;
endOp <= '0';
bitCnt <= 0;
shiftReg <= (OTHERS => '0');
oDataFromPHYValid <= '0';
oDataFromPHY <= (OTHERS => '0');
ELSIF rising_edge(iWbClk) THEN
endOp <= '0';
oDataFromPHYValid <= '0';
CASE state IS
WHEN PREAMBLE =>
IF sendEn THEN
bitCnt <= bitCnt + 1;
oMDHz <= '1';
IF bitCnt = 30 THEN
state <= IDLE;
END IF;
END IF;
WHEN IDLE =>
IF sendEn THEN
IF busy = '1' THEN -- start transaction
oMDHz <= '0'; -- firstbit of start word
state <= CTRL;
bitCnt <= 0;
shiftReg <= iData2PHY;
END IF;
END IF;
WHEN CTRL =>
IF sendEn THEN
bitCnt <= bitCnt + 1;
CASE bitCnt IS
WHEN 0 => oMDHz <= '1'; -- second bit of start word
-- OPCODE. 1 then 0 for read, 0 then 1 for write
WHEN 1 => oMDHz <= rdPend;
WHEN 2 => oMDHz <= NOT rdPend;
-- PHY address
WHEN 3 => oMDHz <= iPHYAddr(4);
WHEN 4 => oMDHz <= iPHYAddr(3);
WHEN 5 => oMDHz <= iPHYAddr(2);
WHEN 6 => oMDHz <= iPHYAddr(1);
WHEN 7 => oMDHz <= iPHYAddr(0);
-- Register address
WHEN 8 => oMDHz <= iRegAddr(4);
WHEN 9 => oMDHz <= iRegAddr(3);
WHEN 10 => oMDHz <= iRegAddr(2);
WHEN 11 => oMDHz <= iRegAddr(1);
WHEN 12 => oMDHz <= iRegAddr(0);
-- TA
WHEN 13 => oMDHz <= '1';
WHEN 14 =>
IF rdPend = '0' THEN
state <= WRITE;
oMDHz <= '0';
bitCnt <= 0;
END IF;
WHEN 15 =>
state <= READ;
bitCnt <= 0;
WHEN OTHERS => NULL;
END CASE;
END IF;
WHEN WRITE =>
IF sendEn THEN
oMDHz <= shiftReg(15);
shiftReg <= shiftReg(14 DOWNTO 0) & '0';
bitCnt <= bitCnt + 1;
IF bitCnt = 15 THEN
endOp <= '1';
bitCnt <= 0;
IF iNoPre = '1' THEN
state <= IDLE;
ELSE
state <= PREAMBLE;
END IF;
END IF;
END IF;
WHEN READ =>
IF receiveEn THEN
bitCnt <= bitCnt + 1;
shiftReg <= shiftReg(14 DOWNTO 0) & iMDI;
IF bitCnt = 15 THEN
bitCnt <= 0;
endOp <= '1';
oDataFromPHY <= shiftReg(14 DOWNTO 0) & iMDI;
oDataFromPHYValid <= '1';
IF iNoPre = '1' THEN
state <= IDLE;
ELSE
state <= PREAMBLE;
END IF;
END IF;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK operation;
END ARCHITECTURE rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_pk_04_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package pk_04_01 is
subtype coeff_ram_address is integer range 0 to 63;
end package pk_04_01;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_pk_04_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package pk_04_01 is
subtype coeff_ram_address is integer range 0 to 63;
end package pk_04_01;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_pk_04_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package pk_04_01 is
subtype coeff_ram_address is integer range 0 to 63;
end package pk_04_01;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Stage_Polynomial_Calc_v3
-- Module Name: Stage_Polynomial_Calc_v3
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st and 3rd step in Goppa Code Decoding.
--
-- This circuit is the stage for pipeline_polynomial_calc_v3. The pipeline is composed of
-- an arbitrary number of this stages.
--
-- For the computation this circuit applies the Horner scheme, where at each stage
-- an accumulator is multiplied by respective x and then added accumulated with coefficient.
-- In Horner scheme algorithm, it begin from the most significative coefficient until reaches
-- lesser significative coefficient.
--
-- It can also change the inner working to compute syndrome at each stage.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- Dependencies:
-- VHDL-93
--
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity stage_polynomial_calc_v3 is
Generic(gf_2_m : integer range 1 to 20 := 11);
Port (
value_x : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_polynomial_coefficient : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC;
mode_polynomial_syndrome : in STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_acc : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end stage_polynomial_calc_v3;
architecture Behavioral of stage_polynomial_calc_v3 is
component mult_gf_2_m
Generic(gf_2_m : integer range 1 to 20 := 11);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal mult_x_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_x_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal mult_x_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal value_accumulated : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
begin
value_accumulated <= value_acc xor value_polynomial_coefficient;
mult_x : mult_gf_2_m
Generic Map (gf_2_m => gf_2_m)
Port Map (
a => mult_x_a,
b => mult_x_b,
o => mult_x_o
);
mult_x_a <= value_x;
mult_x_b <= value_acc when mode_polynomial_syndrome = '1' else
value_accumulated;
new_value_syndrome <= value_accumulated when value_codeword = '1' else
value_polynomial_coefficient;
new_value_acc <= mult_x_o;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
library ethernet_mac;
use ethernet_mac.framing_common.all;
use ethernet_mac.crc32.all;
entity gigabee_tb is
end entity;
architecture behavioral of gigabee_tb is
--Inputs
signal CLK_IN : std_logic := '0';
signal RXDV : std_logic := '0';
signal RXER : std_logic := '0';
signal RXCLK : std_logic := '0';
signal RXD : std_logic_vector(7 downto 0) := (others => '0');
signal TXCLK : std_logic := '0';
--BiDirs
signal MDIO : std_logic;
--Outputs
signal PHY_RESET : std_logic;
signal GTXCLK : std_logic;
signal TXD : std_logic_vector(7 downto 0);
signal TXEN : std_logic;
signal TXER : std_logic;
signal MDC : std_logic;
signal GPIO_LEDS : std_logic_vector(3 downto 0);
-- Clock period definitions
constant CLK_IN_period : time := 8 ns;
constant mii_tx_clk_i_period : time := 40 ns;
constant mii_rx_clk_i_period : time := 40 ns;
constant SPEED_10100 : boolean := FALSE;
-- ARP Request
type t_memory is array (natural range <>) of std_logic_vector(7 downto 0);
-- ICMP Ping Request
constant test_packet_1 : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"00",
x"45", x"00", x"00", x"54", x"c0", x"04", x"40", x"00", x"40",
x"01", x"f5", x"4c",
x"c0", x"a8", x"01", x"05",
x"c0", x"a8", x"01", x"01",
x"08", x"00",
x"95", x"80",
x"0c", x"4f", x"00", x"01",
x"b6", x"c4", x"7d", x"55", x"00", x"00", x"00", x"00",
x"5f", x"42", x"04", x"00", x"00", x"00", x"00", x"00",
x"10", x"11", x"12", x"13", x"14", x"15", x"16", x"17", x"18", x"19", x"1a", x"1b",
x"1c", x"1d", x"1e", x"1f", x"20", x"21", x"22", x"23", x"24", x"25", x"26", x"27", x"28",
x"29", x"2a", x"2b", x"2c", x"2d", x"2e", x"2f", x"30", x"31", x"32", x"33", x"34", x"35",
x"36", x"37"
);
-- ARP Reply
constant test_packet_2 : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"06",
x"00", x"01", x"08", x"00",
x"06", x"04", x"00", x"02",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"c0", x"a8", x"02", x"05",
x"00", x"01", x"02", x"03", x"04", x"05",
x"c0", x"a8", x"02", x"02"
);
-- ARP Request
constant test_packet_3 : t_memory := (
x"FF", x"FF", x"FF", x"FF", x"FF", x"FF",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"08", x"06",
x"00", x"01", x"08", x"00",
x"06", x"04", x"00", x"01",
x"54", x"EE", x"75", x"34", x"2a", x"7e",
x"c0", x"a8", x"01", x"05",
x"ff", x"ff", x"ff", x"ff", x"ff", x"ff",
x"c0", x"a8", x"01", x"01",
-- Padding
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"
);
constant test_packet : t_memory := test_packet_3;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : entity work.gigabee port map(
CLK_IN => CLK_IN,
PHY_RESET => PHY_RESET,
RXDV => RXDV,
RXER => RXER,
RXCLK => RXCLK,
RXD => RXD,
TXCLK => TXCLK,
GTXCLK => GTXCLK,
TXD => TXD,
TXEN => TXEN,
TXER => TXER,
MDC => MDC,
MDIO => MDIO,
GPIO_LEDS => GPIO_LEDS,
RS232_RX => '0'
);
-- Clock process definitions
CLK_IN_process : process
begin
CLK_IN <= '0';
wait for CLK_IN_period / 2;
CLK_IN <= '1';
wait for CLK_IN_period / 2;
end process;
mii_tx_clk_i_process : process
begin
TXCLK <= '0';
wait for mii_tx_clk_i_period / 2;
TXCLK <= '1';
wait for mii_tx_clk_i_period / 2;
end process;
-- Stimulus process
stim_proc : process is
procedure mii_put1(
-- lolisim
-- crashes if (others => '0') is used instead of "00000000"
data : in std_logic_vector(7 downto 0) := "00000000";
dv : in std_logic := '1';
er : in std_logic := '0') is
begin
RXCLK <= '0';
RXDV <= dv;
RXER <= er;
RXD <= data;
wait for mii_rx_clk_i_period / 2;
RXCLK <= '1';
wait for mii_rx_clk_i_period / 2;
end procedure;
procedure mii_put(
data : in std_logic_vector(7 downto 0) := "00000000";
dv : in std_logic := '1';
er : in std_logic := '0') is
begin
if SPEED_10100 = TRUE then
mii_put1("0000" & data(3 downto 0), dv, er);
mii_put1("0000" & data(7 downto 4), dv, er);
else
mii_put1(data, dv, er);
end if;
end procedure;
procedure mii_toggle is
begin
mii_put(dv => '0', er => '0', data => open);
end procedure;
variable fcs : t_crc32;
begin
wait until PHY_RESET = '1';
wait for CLK_IN_period * 1100;
while TRUE loop
for i in 0 to 10 loop
mii_toggle;
end loop;
mii_put(std_logic_vector(START_FRAME_DELIMITER_DATA));
fcs := (others => '1');
for j in test_packet'range loop
mii_put(test_packet(j));
fcs := update_crc32(fcs, std_ulogic_vector(test_packet(j)));
end loop;
-- for j in 1 to 1000 loop
-- mii_put(x"23");
-- end loop;
for b in 0 to 3 loop
mii_put(std_logic_vector(fcs_output_byte(fcs, b)));
end loop;
while TRUE loop
mii_toggle;
end loop;
end loop;
wait;
end process;
end architecture; |
package pkg is
function other_fun return integer;
function fun return integer;
end package;
package body pkg is
function other_fun return integer is
begin
return 0;
end function;
function fun return integer is
function nested return integer is
begin
return other_fun;
end;
begin
return nested;
end function;
end package body;
use work.pkg.all;
entity issue194 is
end entity;
architecture a of issue194 is
begin
main : process
begin
assert fun = 0;
wait;
end process;
end architecture;
|
package pkg is
function other_fun return integer;
function fun return integer;
end package;
package body pkg is
function other_fun return integer is
begin
return 0;
end function;
function fun return integer is
function nested return integer is
begin
return other_fun;
end;
begin
return nested;
end function;
end package body;
use work.pkg.all;
entity issue194 is
end entity;
architecture a of issue194 is
begin
main : process
begin
assert fun = 0;
wait;
end process;
end architecture;
|
package pkg is
function other_fun return integer;
function fun return integer;
end package;
package body pkg is
function other_fun return integer is
begin
return 0;
end function;
function fun return integer is
function nested return integer is
begin
return other_fun;
end;
begin
return nested;
end function;
end package body;
use work.pkg.all;
entity issue194 is
end entity;
architecture a of issue194 is
begin
main : process
begin
assert fun = 0;
wait;
end process;
end architecture;
|
package pkg is
function other_fun return integer;
function fun return integer;
end package;
package body pkg is
function other_fun return integer is
begin
return 0;
end function;
function fun return integer is
function nested return integer is
begin
return other_fun;
end;
begin
return nested;
end function;
end package body;
use work.pkg.all;
entity issue194 is
end entity;
architecture a of issue194 is
begin
main : process
begin
assert fun = 0;
wait;
end process;
end architecture;
|
package pkg is
function other_fun return integer;
function fun return integer;
end package;
package body pkg is
function other_fun return integer is
begin
return 0;
end function;
function fun return integer is
function nested return integer is
begin
return other_fun;
end;
begin
return nested;
end function;
end package body;
use work.pkg.all;
entity issue194 is
end entity;
architecture a of issue194 is
begin
main : process
begin
assert fun = 0;
wait;
end process;
end architecture;
|
-- $Id: sys_tst_sram_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_sram_arty - syn
-- Description: test of arty ddr and its mig controller
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_2line_iob
-- rlink/rlink_sp2c
-- tst_sram
-- bplib/arty/sramif_mig_arty
-- bplib/bpgen/sn_humanio_eum_rbus
-- bplib/sysmon/sysmonx_rbus_arty
-- rbus/rbd_usracc
-- rbus/rb_sres_or_4
--
-- Test bench: tb/tb_tst_sram_arty
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1l 4648 4594 611 5 1849
-- 2019-02-02 1108 2018.3 xc7a35t-1l 4648 4968 644 5 1983
-- 2019-02-02 1108 2017.2 xc7a35t-1l 4643 5334 644 5 1929
-- 2019-01-02 1101 2017.2 xc7a35t-1l 4643 5334 644 5 1929
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.0.1 use bufg_unisim
-- 2018-12-20 1090 1.0 Initial version
-- 2018-11-17 1071 0.1 First draft (derived from sys_tst_sram_c7)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_arty.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_sram_arty is -- top level
-- implements arty_sram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_sram_arty;
architecture syn of sys_tst_sram_arty is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal MEM_RESET : slbit := '0';
signal MEM_RESET_RRI : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACK_W : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal R_DIMCNT : slv2 := (others=>'0');
signal R_DIMFLG : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0104"; -- tst_sram
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 10, -- vco 1000 MHz
CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 8, -- 256 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => GBL_RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_sram
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
AWIDTH => 18)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
SWI => SWI(7 downto 0),
BTN => BTN(3 downto 0),
LED => LED(7 downto 0),
DSP_DAT => DSP_DAT(15 downto 0),
MEM_RESET => MEM_RESET_RRI,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ACK_W => MEM_ACK_W,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
MEM_ADDR => MEM_ADDR(17 downto 0), -- ?? FIXME ?? allow AWIDTH=20
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO
);
MEM_ADDR(19 downto 18) <= (others=>'0'); --?? FIXME ?? allow AWIDTH=20
MEM_RESET <= not LOCKED_CLK or MEM_RESET_RRI;
MEMCTL: sramif_mig_arty -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => MEM_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => MEM_ACK_W,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLKMIG,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT
);
HIO : sn_humanio_emu_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DCWIDTH => 3)
port map (
CLK => CLK,
RESET => '0',
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
SMRB: sysmonx_rbus_arty
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => GBL_RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_4 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_HIO,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
proc_dim: process (CLKMIG)
begin
if rising_edge(CLKMIG) then
R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1);
if unsigned(R_DIMCNT) = 0 then
R_DIMFLG <= '1';
else
R_DIMFLG <= '0';
end if;
end if;
end process proc_dim;
RB_LAM(0) <= RB_LAM_TST;
O_LED(1) <= SER_MONI.txact;
O_LED(0) <= SER_MONI.rxact;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
DSP_DP(7 downto 4) <= "0010";
DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
'0' & SER_MONI.abclkdiv_f;
-- red LED for serious error conditions
O_RGBLED0(0) <= R_DIMFLG and (I_BTN(0) or not LOCKED);
O_RGBLED1(0) <= R_DIMFLG and (I_BTN(0));
O_RGBLED2(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.miguirst);
O_RGBLED3(0) <= R_DIMFLG and (I_BTN(0) or MIG_MONI.migcacow);
-- green LED for activity
O_RGBLED0(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_R);
O_RGBLED1(1) <= R_DIMFLG and (I_BTN(1) or MEM_ACT_W);
O_RGBLED2(1) <= R_DIMFLG and (I_BTN(1) or (MIG_MONI.migcbusy xor I_BTN(3)));
O_RGBLED3(1) <= R_DIMFLG and (I_BTN(1) or MIG_MONI.migwbusy);
-- blue LED currently unused
O_RGBLED0(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED1(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED2(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED3(2) <= R_DIMFLG and (I_BTN(2));
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_296 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_296;
architecture augh of add_296 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_296 is
port (
result : out std_logic_vector(19 downto 0);
in_a : in std_logic_vector(19 downto 0);
in_b : in std_logic_vector(19 downto 0)
);
end add_296;
architecture augh of add_296 is
signal carry_inA : std_logic_vector(21 downto 0);
signal carry_inB : std_logic_vector(21 downto 0);
signal carry_res : std_logic_vector(21 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(20 downto 1);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity immediate_memory is
port(immediate_addr : in std_logic_vector(5 downto 0);
immediate_out : out std_logic_vector(31 downto 0));
end immediate_memory;
architecture Behavioral of immediate_memory is
type immediate_data_type is array (63 downto 0) of std_logic_vector(31 downto 0);
signal immediate_data : immediate_data_type;
begin
immediate_out <= immediate_data(conv_integer(unsigned(immediate_addr)));
immediate_data(0) <= x"00000000";
immediate_data(1) <= x"00000001";
immediate_data(2) <= x"e0000000";
immediate_data(3) <= x"20000000";
immediate_data(4) <= x"00000002";
immediate_data(5) <= x"00000003";
immediate_data(6) <= x"00000004";
immediate_data(7) <= x"00000005";
immediate_data(8) <= x"00000006";
immediate_data(9) <= x"00000007";
immediate_data(10) <= x"00000019";
immediate_data(11) <= x"0000001f";
immediate_data(12) <= x"00000032";
immediate_data(13) <= x"000000ff";
immediate_data(14) <= x"40000000";
immediate_data(15) <= x"0000006c";
immediate_data(16) <= x"00000099";
immediate_data(17) <= x"000000a5";
immediate_data(18) <= x"00190000";
immediate_data(19) <= x"00000280";
immediate_data(20) <= x"000000bd";
immediate_data(21) <= x"ffde0000";
immediate_data(22) <= x"000001e0";
immediate_data(23) <= x"000000d5";
immediate_data(24) <= x"000000d8";
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY debounce IS
PORT(pb, clock_100Hz : IN STD_LOGIC;
pb_debounced : OUT STD_LOGIC);
END debounce;
ARCHITECTURE a OF debounce IS
SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Debounce Button: Filters out mechanical switch bounce for around 40Ms.
-- Debounce clock should be approximately 10ms
process
begin
wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1');
SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1);
SHIFT_PB(3) <= PB;
If SHIFT_PB(3 Downto 0)="0000" THEN
PB_DEBOUNCED <= '0';
ELSE
PB_DEBOUNCED <= '1';
End if;
end process;
end a; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY debounce IS
PORT(pb, clock_100Hz : IN STD_LOGIC;
pb_debounced : OUT STD_LOGIC);
END debounce;
ARCHITECTURE a OF debounce IS
SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Debounce Button: Filters out mechanical switch bounce for around 40Ms.
-- Debounce clock should be approximately 10ms
process
begin
wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1');
SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1);
SHIFT_PB(3) <= PB;
If SHIFT_PB(3 Downto 0)="0000" THEN
PB_DEBOUNCED <= '0';
ELSE
PB_DEBOUNCED <= '1';
End if;
end process;
end a; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY debounce IS
PORT(pb, clock_100Hz : IN STD_LOGIC;
pb_debounced : OUT STD_LOGIC);
END debounce;
ARCHITECTURE a OF debounce IS
SIGNAL SHIFT_PB : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- Debounce Button: Filters out mechanical switch bounce for around 40Ms.
-- Debounce clock should be approximately 10ms
process
begin
wait until (clock_100Hz'EVENT) AND (clock_100Hz = '1');
SHIFT_PB(2 Downto 0) <= SHIFT_PB(3 Downto 1);
SHIFT_PB(3) <= PB;
If SHIFT_PB(3 Downto 0)="0000" THEN
PB_DEBOUNCED <= '0';
ELSE
PB_DEBOUNCED <= '1';
End if;
end process;
end a; |
-- TV Interface Adapter (TIA)
-- Copyright 2006, 2010 Retromaster
--
-- This file is part of A2601.
--
-- A2601 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License,
-- or any later version.
--
-- A2601 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with A2601. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package TIA_common is
subtype w_adr is std_logic_vector(5 downto 0);
constant A_VSYNC: w_adr := "000000";
constant A_VBLANK: w_adr := "000001";
constant A_WSYNC: w_adr := "000010";
constant A_RSYNC: w_adr := "000011";
constant A_NUSIZ0: w_adr := "000100";
constant A_NUSIZ1: w_adr := "000101";
constant A_COLUP0: w_adr := "000110";
constant A_COLUP1: w_adr := "000111";
constant A_COLUPF: w_adr := "001000";
constant A_COLUBK: w_adr := "001001";
constant A_CTRLPF: w_adr := "001010";
constant A_REFP0: w_adr := "001011";
constant A_REFP1: w_adr := "001100";
constant A_PF0: w_adr := "001101";
constant A_PF1: w_adr := "001110";
constant A_PF2: w_adr := "001111";
constant A_RESP0: w_adr := "010000";
constant A_RESP1: w_adr := "010001";
constant A_RESM0: w_adr := "010010";
constant A_RESM1: w_adr := "010011";
constant A_RESBL: w_adr := "010100";
constant A_AUDC0: w_adr := "010101";
constant A_AUDC1: w_adr := "010110";
constant A_AUDF0: w_adr := "010111";
constant A_AUDF1: w_adr := "011000";
constant A_AUDV0: w_adr := "011001";
constant A_AUDV1: w_adr := "011010";
constant A_GRP0: w_adr := "011011";
constant A_GRP1: w_adr := "011100";
constant A_ENAM0: w_adr := "011101";
constant A_ENAM1: w_adr := "011110";
constant A_ENABL: w_adr := "011111";
constant A_HMP0: w_adr := "100000";
constant A_HMP1: w_adr := "100001";
constant A_HMM0: w_adr := "100010";
constant A_HMM1: w_adr := "100011";
constant A_HMBL: w_adr := "100100";
constant A_VDELP0: w_adr := "100101";
constant A_VDELP1: w_adr := "100110";
constant A_VDELBL: w_adr := "100111";
constant A_RESMP0: w_adr := "101000";
constant A_RESMP1: w_adr := "101001";
constant A_HMOVE: w_adr := "101010";
constant A_HMCLR: w_adr := "101011";
constant A_CXCLR: w_adr := "101100";
subtype r_adr is std_logic_vector(3 downto 0);
constant A_CXM0P: r_adr := "0000";
constant A_CXM1P: r_adr := "0001";
constant A_CXP0FB: r_adr := "0010";
constant A_CXP1FB: r_adr := "0011";
constant A_CXM0FB: r_adr := "0100";
constant A_CXM1FB: r_adr := "0101";
constant A_CXBLPF: r_adr := "0110";
constant A_CXPPMM: r_adr := "0111";
constant A_INPT0: r_adr := "1000";
constant A_INPT1: r_adr := "1001";
constant A_INPT2: r_adr := "1010";
constant A_INPT3: r_adr := "1011";
constant A_INPT4: r_adr := "1100";
constant A_INPT5: r_adr := "1101";
end TIA_common;
package body TIA_common is
end TIA_common;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk27_hot is
port(
clock: in std_logic;
input: in std_logic_vector(0 downto 0);
output: out std_logic_vector(1 downto 0)
);
end dk27_hot;
architecture behaviour of dk27_hot is
constant START: std_logic_vector(6 downto 0) := "1000000";
constant state6: std_logic_vector(6 downto 0) := "0100000";
constant state2: std_logic_vector(6 downto 0) := "0010000";
constant state5: std_logic_vector(6 downto 0) := "0001000";
constant state3: std_logic_vector(6 downto 0) := "0000100";
constant state4: std_logic_vector(6 downto 0) := "0000010";
constant state7: std_logic_vector(6 downto 0) := "0000001";
signal current_state, next_state: std_logic_vector(6 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------"; output <= "--";
case current_state is
when START =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state4; output <= "00";
end if;
when state2 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state3; output <= "00";
end if;
when state3 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state7; output <= "00";
end if;
when state4 =>
if std_match(input, "0") then next_state <= state6; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when state5 =>
if std_match(input, "0") then next_state <= START; output <= "10";
elsif std_match(input, "1") then next_state <= state2; output <= "10";
end if;
when state6 =>
if std_match(input, "0") then next_state <= START; output <= "01";
elsif std_match(input, "1") then next_state <= state2; output <= "01";
end if;
when state7 =>
if std_match(input, "0") then next_state <= state5; output <= "00";
elsif std_match(input, "1") then next_state <= state6; output <= "10";
end if;
when others => next_state <= "-------"; output <= "--";
end case;
end process;
end behaviour;
|
--------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project :
--------------------------------------------------------------------------------
-- File : aeg_64_byte_full_load_tb.vhd
-- -----------------------------------------------------------------------------
--
-- This testbench performs the following operations:
--
-- 256 Frames a pushed into the receiver from the PHY interface (GMII).
-- Their destination MAC addresses are in range FF:00:00:00:00:00 to FF:00:00:00:00:FF
-- Each frame is 64 Byte in size and frames are inserted back to back (after the
-- minimum interframe gap)
-- These insertions are done by the stimulus process.
-- The monitor process observes the messages coming out of the transmitter side of
-- the switch and compare to the data expected
-- The lookup module skips every forth frame as it is not in the lookup memory
-- FF:00:00:00:00:FE has an error and should be skipped
entity aeg_64_byte_full_load_tb is
end aeg_64_byte_full_load_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture testbench of aeg_64_byte_full_load_tb is
constant RECEIVER_DATA_WIDTH : integer := 8;
constant NR_PORTS : integer := 4;
constant GMII_DATA_WIDTH : integer := 8;
constant RX_STATISTICS_WIDTH : integer := 28;
constant TX_STATISTICS_WIDTH : integer := 32;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
GMII_DATA_WIDTH : integer;
RX_STATISTICS_WIDTH : integer;
TX_STATISTICS_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_response : out std_logic;
enable_phy_loopback : in std_logic;
reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data : frame_typ := (
columns => (
0 => ( DATA => X"FF", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"00", VALID => '1', ERROR => '0'),
2 => ( DATA => X"00", VALID => '1', ERROR => '0'),
3 => ( DATA => X"00", VALID => '1', ERROR => '0'),
4 => ( DATA => X"00", VALID => '1', ERROR => '0'),
5 => ( DATA => X"00", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')
)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
shared variable counter : integer := 0;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal frames_received : std_logic_vector(7 downto 0) := x"00";
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
RX_STATISTICS_WIDTH => RX_STATISTICS_WIDTH,
TX_STATISTICS_WIDTH => TX_STATISTICS_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
serial_response => serial_response,
enable_phy_loopback => enable_phy_loopback,
reset_error => '0'
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 300 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- reset process.
-----------------------------------------------------------------------------
p_reset : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
wait for 800 ns;
mac_reset;
management_config_finished <= true;
-- wait for 167.8 us;
-- mac_reset;
wait;
end process p_reset;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject 256 frames back to back
for dest_address6 in 0 to 255 loop
frame_data.columns(5).data := std_logic_vector(to_unsigned(dest_address6, frame_data.columns(5).data'length));
if dest_address6 = 254 then
frame_data.columns(40).error := '1';
else
frame_data.columns(40).error := '0';
end if;
send_frame_1g;
end loop;
send_complete <= '1';
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
procedure check_frame_1g(dest_address6 : integer) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := frame_data.columns(current_col).data;
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data.columns(current_col).valid)='1') loop
if gmii_tx_en /= frame_data.columns(current_col).valid then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 5 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
elsif current_col = 5 then
if gmii_txd(7 downto 0) /= std_logic_vector(to_unsigned(dest_address6, gmii_txd'length)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during 6th Destination Address field" & cr
severity error;
end if;
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
begin -- process p_monitor
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until management_config_finished;
wait for 100 ns;
for dest_address6 in 0 to 253 loop
check_frame_1g(dest_address6);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
end loop;
-- provoking an error to see if tb works correctly
check_frame_1g(255);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end testbench;
|
--------------------------------------------------------------------------------
-- Title : Demo testbench
-- Project :
--------------------------------------------------------------------------------
-- File : aeg_64_byte_full_load_tb.vhd
-- -----------------------------------------------------------------------------
--
-- This testbench performs the following operations:
--
-- 256 Frames a pushed into the receiver from the PHY interface (GMII).
-- Their destination MAC addresses are in range FF:00:00:00:00:00 to FF:00:00:00:00:FF
-- Each frame is 64 Byte in size and frames are inserted back to back (after the
-- minimum interframe gap)
-- These insertions are done by the stimulus process.
-- The monitor process observes the messages coming out of the transmitter side of
-- the switch and compare to the data expected
-- The lookup module skips every forth frame as it is not in the lookup memory
-- FF:00:00:00:00:FE has an error and should be skipped
entity aeg_64_byte_full_load_tb is
end aeg_64_byte_full_load_tb;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture testbench of aeg_64_byte_full_load_tb is
constant RECEIVER_DATA_WIDTH : integer := 8;
constant NR_PORTS : integer := 4;
constant GMII_DATA_WIDTH : integer := 8;
constant RX_STATISTICS_WIDTH : integer := 28;
constant TX_STATISTICS_WIDTH : integer := 32;
constant TX_IFG_DELAY_WIDTH : integer := 8;
constant PAUSE_VAL_WIDTH : integer := 16;
------------------------------------------------------------------------------
-- Component Declaration for Device Under Test (DUT).
------------------------------------------------------------------------------
component automotive_ethernet_gateway
Generic (
RECEIVER_DATA_WIDTH : integer;
NR_PORTS : integer;
GMII_DATA_WIDTH : integer;
RX_STATISTICS_WIDTH : integer;
TX_STATISTICS_WIDTH : integer;
TX_IFG_DELAY_WIDTH : integer;
PAUSE_VAL_WIDTH : integer
);
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- 200MHz clock input from board
clk_in_p : in std_logic;
clk_in_n : in std_logic;
phy_resetn : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_tx_clk : out std_logic;
gmii_rxd : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
gmii_rx_clk : in std_logic;
mii_tx_clk : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- Serialised statistics vectors
--------------------------------
tx_statistics_s : out std_logic;
rx_statistics_s : out std_logic;
-- Serialised Pause interface controls
--------------------------------------
pause_req_s : in std_logic;
-- Main example design controls
-------------------------------
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_response : out std_logic;
enable_phy_loopback : in std_logic;
reset_error : in std_logic
);
end component;
------------------------------------------------------------------------------
-- types to support frame data
------------------------------------------------------------------------------
-- Tx Data and Data_valid record
type data_typ is record
data : std_logic_vector(7 downto 0); -- data
valid : std_logic; -- data_valid
error : std_logic; -- data_error
end record;
type frame_of_data_typ is array (natural range <>) of data_typ;
-- Tx Data, Data_valid and underrun record
type frame_typ is record
columns : frame_of_data_typ(0 to 65);-- data field
end record;
------------------------------------------------------------------------------
-- Stimulus - Frame data
------------------------------------------------------------------------------
shared variable frame_data : frame_typ := (
columns => (
0 => ( DATA => X"FF", VALID => '1', ERROR => '0'), -- Destination Address (DA)
1 => ( DATA => X"00", VALID => '1', ERROR => '0'),
2 => ( DATA => X"00", VALID => '1', ERROR => '0'),
3 => ( DATA => X"00", VALID => '1', ERROR => '0'),
4 => ( DATA => X"00", VALID => '1', ERROR => '0'),
5 => ( DATA => X"00", VALID => '1', ERROR => '0'),
6 => ( DATA => X"5A", VALID => '1', ERROR => '0'), -- Source Address (5A)
7 => ( DATA => X"02", VALID => '1', ERROR => '0'),
8 => ( DATA => X"03", VALID => '1', ERROR => '0'),
9 => ( DATA => X"04", VALID => '1', ERROR => '0'),
10 => ( DATA => X"05", VALID => '1', ERROR => '0'),
11 => ( DATA => X"06", VALID => '1', ERROR => '0'),
12 => ( DATA => X"00", VALID => '1', ERROR => '0'),
13 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- Length/Type = Length = 46
14 => ( DATA => X"01", VALID => '1', ERROR => '0'),
15 => ( DATA => X"02", VALID => '1', ERROR => '0'),
16 => ( DATA => X"03", VALID => '1', ERROR => '0'),
17 => ( DATA => X"04", VALID => '1', ERROR => '0'),
18 => ( DATA => X"05", VALID => '1', ERROR => '0'),
19 => ( DATA => X"06", VALID => '1', ERROR => '0'),
20 => ( DATA => X"07", VALID => '1', ERROR => '0'),
21 => ( DATA => X"08", VALID => '1', ERROR => '0'),
22 => ( DATA => X"09", VALID => '1', ERROR => '0'),
23 => ( DATA => X"0A", VALID => '1', ERROR => '0'),
24 => ( DATA => X"0B", VALID => '1', ERROR => '0'),
25 => ( DATA => X"0C", VALID => '1', ERROR => '0'),
26 => ( DATA => X"0D", VALID => '1', ERROR => '0'),
27 => ( DATA => X"0E", VALID => '1', ERROR => '0'),
28 => ( DATA => X"0F", VALID => '1', ERROR => '0'),
29 => ( DATA => X"10", VALID => '1', ERROR => '0'),
30 => ( DATA => X"11", VALID => '1', ERROR => '0'),
31 => ( DATA => X"12", VALID => '1', ERROR => '0'),
32 => ( DATA => X"13", VALID => '1', ERROR => '0'),
33 => ( DATA => X"14", VALID => '1', ERROR => '0'),
34 => ( DATA => X"15", VALID => '1', ERROR => '0'),
35 => ( DATA => X"16", VALID => '1', ERROR => '0'),
36 => ( DATA => X"17", VALID => '1', ERROR => '0'),
37 => ( DATA => X"18", VALID => '1', ERROR => '0'),
38 => ( DATA => X"19", VALID => '1', ERROR => '0'),
39 => ( DATA => X"1A", VALID => '1', ERROR => '0'),
40 => ( DATA => X"1B", VALID => '1', ERROR => '0'),
41 => ( DATA => X"1C", VALID => '1', ERROR => '0'),
42 => ( DATA => X"1D", VALID => '1', ERROR => '0'),
43 => ( DATA => X"1E", VALID => '1', ERROR => '0'),
44 => ( DATA => X"1F", VALID => '1', ERROR => '0'),
45 => ( DATA => X"20", VALID => '1', ERROR => '0'),
46 => ( DATA => X"21", VALID => '1', ERROR => '0'),
47 => ( DATA => X"22", VALID => '1', ERROR => '0'),
48 => ( DATA => X"23", VALID => '1', ERROR => '0'),
49 => ( DATA => X"24", VALID => '1', ERROR => '0'),
50 => ( DATA => X"25", VALID => '1', ERROR => '0'),
51 => ( DATA => X"26", VALID => '1', ERROR => '0'),
52 => ( DATA => X"27", VALID => '1', ERROR => '0'),
53 => ( DATA => X"28", VALID => '1', ERROR => '0'),
54 => ( DATA => X"29", VALID => '1', ERROR => '0'),
55 => ( DATA => X"2A", VALID => '1', ERROR => '0'),
56 => ( DATA => X"2B", VALID => '1', ERROR => '0'),
57 => ( DATA => X"2C", VALID => '1', ERROR => '0'),
58 => ( DATA => X"2D", VALID => '1', ERROR => '0'),
59 => ( DATA => X"2E", VALID => '1', ERROR => '0'), -- 46th Byte of Data
others => ( DATA => X"00", VALID => '0', ERROR => '0')
)
);
------------------------------------------------------------------------------
-- CRC engine
------------------------------------------------------------------------------
function calc_crc (data : in std_logic_vector;
fcs : in std_logic_vector)
return std_logic_vector is
variable crc : std_logic_vector(31 downto 0);
variable crc_feedback : std_logic;
begin
crc := not fcs;
for I in 0 to 7 loop
crc_feedback := crc(0) xor data(I);
crc(4 downto 0) := crc(5 downto 1);
crc(5) := crc(6) xor crc_feedback;
crc(7 downto 6) := crc(8 downto 7);
crc(8) := crc(9) xor crc_feedback;
crc(9) := crc(10) xor crc_feedback;
crc(14 downto 10) := crc(15 downto 11);
crc(15) := crc(16) xor crc_feedback;
crc(18 downto 16) := crc(19 downto 17);
crc(19) := crc(20) xor crc_feedback;
crc(20) := crc(21) xor crc_feedback;
crc(21) := crc(22) xor crc_feedback;
crc(22) := crc(23);
crc(23) := crc(24) xor crc_feedback;
crc(24) := crc(25) xor crc_feedback;
crc(25) := crc(26);
crc(26) := crc(27) xor crc_feedback;
crc(27) := crc(28) xor crc_feedback;
crc(28) := crc(29);
crc(29) := crc(30) xor crc_feedback;
crc(30) := crc(31) xor crc_feedback;
crc(31) := crc_feedback;
end loop;
-- return the CRC result
return not crc;
end calc_crc;
------------------------------------------------------------------------------
-- Test Bench signals and constants
------------------------------------------------------------------------------
-- Delay to provide setup and hold timing at the GMII/RGMII.
constant dly : time := 4.8 ns;
constant gtx_period : time := 2.5 ns;
shared variable counter : integer := 0;
-- testbench signals
signal gtx_clk : std_logic;
signal gtx_clkn : std_logic;
signal reset : std_logic := '0';
signal demo_mode_error : std_logic := '0';
signal frames_received : std_logic_vector(7 downto 0) := x"00";
signal mdc : std_logic;
signal mdio : std_logic;
signal mdio_count : unsigned(5 downto 0) := (others => '0');
signal last_mdio : std_logic;
signal mdio_read : std_logic;
signal mdio_addr : std_logic;
signal mdio_fail : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0) := (others => '0');
signal gmii_rx_clk : std_logic;
signal gmii_rx_dv : std_logic := '0';
signal gmii_rx_er : std_logic := '0';
signal gmii_rxd : std_logic_vector(7 downto 0) := (others => '0');
signal mii_tx_clk : std_logic := '0';
-- testbench control signals
signal tx_monitor_finished_1G : boolean := false;
signal management_config_finished : boolean := false;
signal rx_stimulus_finished : boolean := false;
signal send_complete : std_logic := '0';
signal phy_speed : std_logic_vector(1 downto 0) := "10";
signal mac_speed : std_logic_vector(1 downto 0) := "10";
signal update_speed : std_logic := '0';
signal serial_response : std_logic;
signal enable_phy_loopback : std_logic := '0';
begin
------------------------------------------------------------------------------
-- Wire up Device Under Test
------------------------------------------------------------------------------
dut: automotive_ethernet_gateway
Generic map (
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
NR_PORTS => NR_PORTS,
GMII_DATA_WIDTH => GMII_DATA_WIDTH,
RX_STATISTICS_WIDTH => RX_STATISTICS_WIDTH,
TX_STATISTICS_WIDTH => TX_STATISTICS_WIDTH,
TX_IFG_DELAY_WIDTH => TX_IFG_DELAY_WIDTH,
PAUSE_VAL_WIDTH => PAUSE_VAL_WIDTH
)
port map (
-- asynchronous reset
--------------------------------
glbl_rst => reset,
-- 200MHz clock input from board
clk_in_p => gtx_clk,
clk_in_n => gtx_clkn,
phy_resetn => open,
-- GMII Interface
--------------------------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_tx_clk => gmii_tx_clk,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_rx_clk => gmii_rx_clk,
mii_tx_clk => mii_tx_clk,
-- MDIO Interface
mdc => mdc,
mdio => mdio,
-- Serialised statistics vectors
--------------------------------
tx_statistics_s => open,
rx_statistics_s => open,
-- Serialised Pause interface controls
--------------------------------------
pause_req_s => '0',
-- Main example design controls
-------------------------------
mac_speed => mac_speed,
update_speed => update_speed,
serial_response => serial_response,
enable_phy_loopback => enable_phy_loopback,
reset_error => '0'
);
------------------------------------------------------------------------------
-- If the simulation is still going after delay below
-- then something has gone wrong: terminate with an error
------------------------------------------------------------------------------
p_timebomb : process
begin
wait for 300 us;
assert false
report "ERROR - Simulation running forever!"
severity failure;
end process p_timebomb;
------------------------------------------------------------------------------
-- Clock drivers
------------------------------------------------------------------------------
-- drives input to an MMCM at 200MHz which creates gtx_clk at 125 MHz
p_gtx_clk : process
begin
gtx_clk <= '0';
gtx_clkn <= '1';
wait for 80 ns;
loop
wait for gtx_period;
gtx_clk <= '1';
gtx_clkn <= '0';
wait for gtx_period;
gtx_clk <= '0';
gtx_clkn <= '1';
end loop;
end process p_gtx_clk;
gmii_rx_clk <= gmii_tx_clk;
-----------------------------------------------------------------------------
-- reset process.
-----------------------------------------------------------------------------
p_reset : process
procedure mac_reset is
begin
assert false
report "Resetting core..." & cr
severity note;
reset <= '1';
wait for 200 ns;
reset <= '0';
assert false
report "Timing checks are valid" & cr
severity note;
end procedure mac_reset;
begin
assert false
report "Timing checks are not valid" & cr
severity note;
mac_speed <= "10";
phy_speed <= "10";
update_speed <= '0';
wait for 800 ns;
mac_reset;
management_config_finished <= true;
-- wait for 167.8 us;
-- mac_reset;
wait;
end process p_reset;
------------------------------------------------------------------------------
-- Stimulus process. This process will inject frames of data into the
-- PHY side of the receiver.
------------------------------------------------------------------------------
p_stimulus : process
----------------------------------------------------------
-- Procedure to inject a frame into the receiver at 1Gb/s
----------------------------------------------------------
procedure send_frame_1g is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
begin
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
-- Reset the FCS calculation
fcs := (others => '0');
-- Adding the preamble field
for j in 0 to 7 loop
gmii_rxd <= "01010101" after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Adding the Start of Frame Delimiter (SFD)
gmii_rxd <= "11010101" after dly;
gmii_rx_dv <= '1' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := 0;
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
current_col := current_col + 1;
-- loop over columns in frame.
while frame_data.columns(current_col).valid /= '0' loop
-- send one column of data
gmii_rxd <= frame_data.columns(current_col).data after dly;
gmii_rx_dv <= frame_data.columns(current_col).valid after dly;
gmii_rx_er <= frame_data.columns(current_col).error after dly;
fcs := calc_crc(frame_data.columns(current_col).data, fcs);
current_col := current_col + 1;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Send the CRC.
for j in 0 to 3 loop
gmii_rxd <= fcs(((8*j)+7) downto (8*j)) after dly;
gmii_rx_dv <= '1' after dly;
gmii_rx_er <= '0' after dly;
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
-- Clear the data lines.
gmii_rxd <= (others => '0') after dly;
gmii_rx_dv <= '0' after dly;
-- Adding the minimum Interframe gap for a receiver (8 idles)
for j in 0 to 7 loop
wait until gmii_rx_clk'event and gmii_rx_clk = '1';
end loop;
end send_frame_1g;
begin
-- Wait for the Management MDIO transaction to finish.
wait until management_config_finished;
-- Wait for the internal resets to settle
wait for 800 ns;
-- inject 256 frames back to back
for dest_address6 in 0 to 255 loop
frame_data.columns(5).data := std_logic_vector(to_unsigned(dest_address6, frame_data.columns(5).data'length));
if dest_address6 = 254 then
frame_data.columns(40).error := '1';
else
frame_data.columns(40).error := '0';
end if;
send_frame_1g;
end loop;
send_complete <= '1';
-- Wait for 1G monitor process to complete.
wait until tx_monitor_finished_1G;
rx_stimulus_finished <= true;
-- Our work here is done
if (demo_mode_error = '0') then
assert false
report "Test completed successfully"
severity note;
end if;
assert false
report "Simulation stopped"
severity failure;
end process p_stimulus;
------------------------------------------------------------------------------
-- Monitor process. This process checks the data coming out of the
-- transmitter to make sure that it matches that inserted into the
-- receiver.
------------------------------------------------------------------------------
p_monitor : process
procedure check_frame_1g(dest_address6 : integer) is
variable current_col : natural := 0; -- Column counter within frame
variable fcs : std_logic_vector(31 downto 0);
variable addr_comp_reg : std_logic_vector(95 downto 0);
begin
-- Reset the FCS calculation
fcs := (others => '0');
while current_col < 12 loop
addr_comp_reg((current_col*8 + 7) downto (current_col*8)) := frame_data.columns(current_col).data;
current_col := current_col + 1;
end loop;
current_col := 0;
-- Parse over the preamble field
while gmii_tx_en /= '1' or gmii_txd = "01010101" loop
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop;
-- Parse over the Start of Frame Delimiter (SFD)
if (gmii_txd /= "11010101") then
demo_mode_error <= '1';
assert false
report "SFD not present" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
-- frame has started, loop over columns of frame
while ((frame_data.columns(current_col).valid)='1') loop
if gmii_tx_en /= frame_data.columns(current_col).valid then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect" & cr
severity error;
end if;
if gmii_tx_en = '1' then
-- The transmitted Destination Address was the Source Address of the injected frame
if current_col < 5 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Destination Address field" & cr
severity error;
end if;
elsif current_col = 5 then
if gmii_txd(7 downto 0) /= std_logic_vector(to_unsigned(dest_address6, gmii_txd'length)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during 6th Destination Address field" & cr
severity error;
end if;
elsif current_col >= 6 and current_col < 12 then
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during Source Address field" & cr
severity error;
end if;
-- for remainder of frame
else
if gmii_txd(7 downto 0) /= frame_data.columns(current_col).data(7 downto 0) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect" & cr
severity error;
end if;
end if;
end if;
-- calculate expected crc for the frame
fcs := calc_crc(gmii_txd, fcs);
-- wait for next column of data
current_col := current_col + 1;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- while data valid
-- Check the FCS matches that expected from calculation
-- Having checked all data columns, txd must contain FCS.
for j in 0 to 3 loop
if gmii_tx_en = '0' then
demo_mode_error <= '1';
assert false
report "gmii_tx_en incorrect during FCS field" & cr
severity error;
end if;
if gmii_txd /= fcs(((8*j)+7) downto (8*j)) then
demo_mode_error <= '1';
assert false
report "gmii_txd incorrect during FCS field" & cr
severity error;
end if;
wait until gmii_tx_clk'event and gmii_tx_clk = '1';
end loop; -- j
end check_frame_1g;
begin -- process p_monitor
-- wait for reset to complete before starting monitor to ignore false startup errors
wait until management_config_finished;
wait for 100 ns;
for dest_address6 in 0 to 253 loop
check_frame_1g(dest_address6);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
end loop;
-- provoking an error to see if tb works correctly
check_frame_1g(255);
counter := counter + 1;
frames_received <= std_logic_vector(to_unsigned(counter,frames_received'length));
if send_complete = '0' then
wait until send_complete'event and send_complete = '1';
end if;
wait for 200 ns;
tx_monitor_finished_1G <= true;
wait;
end process p_monitor;
end testbench;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host is
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_address : in std_logic_vector(12 downto 0); -- 8K block
sys_write : in std_logic;
sys_request : in std_logic;
sys_wdata : in std_logic_vector(7 downto 0);
sys_rdata : out std_logic_vector(7 downto 0);
sys_rack : out std_logic;
sys_dack : out std_logic );
-- -- Interface to read/write registers
-- read_reg : in std_logic;
-- write_reg : in std_logic;
-- reg_ack : out std_logic;
-- address : in std_logic_vector(5 downto 0);
-- write_data : in std_logic_vector(7 downto 0);
-- read_data : out std_logic_vector(7 downto 0) );
--
end usb_host;
architecture wrap of usb_host is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_valid : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal read_reg : std_logic := '0';
signal write_reg : std_logic;
signal reg_ack : std_logic;
signal address : std_logic_vector(5 downto 0);
signal write_data : std_logic_vector(7 downto 0);
signal read_data : std_logic_vector(7 downto 0);
signal reset_pkt : std_logic;
signal reset_valid : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal power_en : std_logic;
signal do_reset : std_logic;
signal reset_done : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic;
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to bus reset unit
power_en => power_en,
do_reset => do_reset,
reset_done => reset_done,
speed => speed,
reset_pkt => reset_pkt,
reset_data => reset_data,
reset_last => reset_last,
reset_valid => reset_valid,
-- Interface to read/write registers
-- read_reg => read_reg,
-- write_reg => write_reg,
-- address => address,
-- write_data => write_data,
-- read_data => X"55", -- read_data
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
sys_buf_en <= sys_request and sys_address(12);
sys_descr_en <= sys_request and not sys_address(12);
sys_rack <= sys_request;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_dack <= sys_request;
sys_sel_d <= sys_address(12);
end if;
end process;
sys_rdata <= sys_buf_rdata when sys_sel_d='1' else sys_descr_rdata;
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_register => rx_register,
rx_data => rx_data,
-- Status
busy => tx_busy,
tx_ack => tx_ack,
reg_ack => reg_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to read/write registers
read_reg => read_reg,
write_reg => write_reg,
address => address,
write_data => write_data,
read_data => read_data );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
port map (
clock => ulpi_clock,
reset => ulpi_reset,
do_reset => do_reset,
power_en => power_en,
reset_done => reset_done,
speed => speed,
-- status
status => status,
-- register interface
write_reg => write_reg,
write_data => write_data,
address => address,
reg_ack => reg_ack,
send_packet => reset_pkt,
user_data => reset_data,
user_last => reset_last,
user_valid => reset_valid );
end wrap;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host is
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_address : in std_logic_vector(12 downto 0); -- 8K block
sys_write : in std_logic;
sys_request : in std_logic;
sys_wdata : in std_logic_vector(7 downto 0);
sys_rdata : out std_logic_vector(7 downto 0);
sys_rack : out std_logic;
sys_dack : out std_logic );
-- -- Interface to read/write registers
-- read_reg : in std_logic;
-- write_reg : in std_logic;
-- reg_ack : out std_logic;
-- address : in std_logic_vector(5 downto 0);
-- write_data : in std_logic_vector(7 downto 0);
-- read_data : out std_logic_vector(7 downto 0) );
--
end usb_host;
architecture wrap of usb_host is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_valid : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal read_reg : std_logic := '0';
signal write_reg : std_logic;
signal reg_ack : std_logic;
signal address : std_logic_vector(5 downto 0);
signal write_data : std_logic_vector(7 downto 0);
signal read_data : std_logic_vector(7 downto 0);
signal reset_pkt : std_logic;
signal reset_valid : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal power_en : std_logic;
signal do_reset : std_logic;
signal reset_done : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic;
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to bus reset unit
power_en => power_en,
do_reset => do_reset,
reset_done => reset_done,
speed => speed,
reset_pkt => reset_pkt,
reset_data => reset_data,
reset_last => reset_last,
reset_valid => reset_valid,
-- Interface to read/write registers
-- read_reg => read_reg,
-- write_reg => write_reg,
-- address => address,
-- write_data => write_data,
-- read_data => X"55", -- read_data
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
sys_buf_en <= sys_request and sys_address(12);
sys_descr_en <= sys_request and not sys_address(12);
sys_rack <= sys_request;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_dack <= sys_request;
sys_sel_d <= sys_address(12);
end if;
end process;
sys_rdata <= sys_buf_rdata when sys_sel_d='1' else sys_descr_rdata;
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_register => rx_register,
rx_data => rx_data,
-- Status
busy => tx_busy,
tx_ack => tx_ack,
reg_ack => reg_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to read/write registers
read_reg => read_reg,
write_reg => write_reg,
address => address,
write_data => write_data,
read_data => read_data );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
port map (
clock => ulpi_clock,
reset => ulpi_reset,
do_reset => do_reset,
power_en => power_en,
reset_done => reset_done,
speed => speed,
-- status
status => status,
-- register interface
write_reg => write_reg,
write_data => write_data,
address => address,
reg_ack => reg_ack,
send_packet => reset_pkt,
user_data => reset_data,
user_last => reset_last,
user_valid => reset_valid );
end wrap;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host is
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_address : in std_logic_vector(12 downto 0); -- 8K block
sys_write : in std_logic;
sys_request : in std_logic;
sys_wdata : in std_logic_vector(7 downto 0);
sys_rdata : out std_logic_vector(7 downto 0);
sys_rack : out std_logic;
sys_dack : out std_logic );
-- -- Interface to read/write registers
-- read_reg : in std_logic;
-- write_reg : in std_logic;
-- reg_ack : out std_logic;
-- address : in std_logic_vector(5 downto 0);
-- write_data : in std_logic_vector(7 downto 0);
-- read_data : out std_logic_vector(7 downto 0) );
--
end usb_host;
architecture wrap of usb_host is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_valid : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal read_reg : std_logic := '0';
signal write_reg : std_logic;
signal reg_ack : std_logic;
signal address : std_logic_vector(5 downto 0);
signal write_data : std_logic_vector(7 downto 0);
signal read_data : std_logic_vector(7 downto 0);
signal reset_pkt : std_logic;
signal reset_valid : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal power_en : std_logic;
signal do_reset : std_logic;
signal reset_done : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic;
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to bus reset unit
power_en => power_en,
do_reset => do_reset,
reset_done => reset_done,
speed => speed,
reset_pkt => reset_pkt,
reset_data => reset_data,
reset_last => reset_last,
reset_valid => reset_valid,
-- Interface to read/write registers
-- read_reg => read_reg,
-- write_reg => write_reg,
-- address => address,
-- write_data => write_data,
-- read_data => X"55", -- read_data
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
sys_buf_en <= sys_request and sys_address(12);
sys_descr_en <= sys_request and not sys_address(12);
sys_rack <= sys_request;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_dack <= sys_request;
sys_sel_d <= sys_address(12);
end if;
end process;
sys_rdata <= sys_buf_rdata when sys_sel_d='1' else sys_descr_rdata;
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_register => rx_register,
rx_data => rx_data,
-- Status
busy => tx_busy,
tx_ack => tx_ack,
reg_ack => reg_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to read/write registers
read_reg => read_reg,
write_reg => write_reg,
address => address,
write_data => write_data,
read_data => read_data );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
port map (
clock => ulpi_clock,
reset => ulpi_reset,
do_reset => do_reset,
power_en => power_en,
reset_done => reset_done,
speed => speed,
-- status
status => status,
-- register interface
write_reg => write_reg,
write_data => write_data,
address => address,
reg_ack => reg_ack,
send_packet => reset_pkt,
user_data => reset_data,
user_last => reset_last,
user_valid => reset_valid );
end wrap;
|
architecture RTL of FIFO is
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 is
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
begin
end procedure proc1;
procedure proc1 is
constant width : integer := 32;
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
constant width : integer := 32;
begin
end procedure proc1;
-- Fixes follow
procedure proc1 is
constant width : integer := 32;
begin
end procedure proc1;
procedure proc1 (
constant a : in integer;
signal d : out std_logic
) is
constant width : integer := 32;
begin
end procedure proc1;
begin
end architecture RTL;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: TODO
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair of VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library OSVVM;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
package sortnet_tb is
generic (
META_BITS : positive;
DATA_BITS : positive;
INPUTS : positive
);
subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
function to_dv(slm : T_SLM) return T_DATA_VECTOR;
function to_slm(dv : T_DATA_VECTOR) return T_SLM;
type T_SCOREBOARD_DATA is record
IsKey : std_logic;
Meta : std_logic_vector(META_BITS - 1 downto 0);
Data : T_DATA_VECTOR(INPUTS - 1 downto 0);
end record;
function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean;
function to_string(dataset : T_SCOREBOARD_DATA) return string;
package P_SCOREBOARD is new OSVVM.ScoreboardGenericPkg
generic map (
ExpectedType => T_SCOREBOARD_DATA,
ActualType => T_SCOREBOARD_DATA,
Match => match,
expected_to_string => to_string, --[T_SCOREBOARD_DATA return string],
actual_to_string => to_string
);
alias PT_SCOREBOARD is P_SCOREBOARD.ScoreBoardPType;
end package;
package body sortnet_tb is
function match(expected : T_SCOREBOARD_DATA; actual : T_SCOREBOARD_DATA) return boolean is
variable good : boolean;
begin
good := (expected.IsKey = actual.IsKey);
good := good and (expected.Meta = actual.Meta);
if (expected.IsKey = '1') then
for i in expected.Data'range loop
good := good and (expected.Data(i) = actual.Data(i));
exit when (good = FALSE);
end loop;
end if;
return good;
end function;
function to_string(dataset : T_SCOREBOARD_DATA) return string is
variable KeyMarker : string(1 to 2);
begin
KeyMarker := ite((dataset.IsKey = '1'), "* ", " ");
-- for i in 0 to 0 loop --dataset.Key'range loop
return "Data: " & to_string(dataset.Data(0), 'h') & KeyMarker &
" Meta: " & to_string(dataset.Meta, 'h');
-- end loop;
end function;
function to_dv(slm : T_SLM) return T_DATA_VECTOR is
variable Result : T_DATA_VECTOR(slm'range(1));
begin
for i in slm'high(1) downto slm'low(1) loop
for j in T_DATA'range loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(dv : T_DATA_VECTOR) return T_SLM is
variable Result : T_SLM(dv'range, T_DATA'range);
begin
for i in dv'range loop
for j in T_DATA'range loop
Result(i, j) := dv(i)(j);
end loop;
end loop;
return Result;
end function;
end package body;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:48:08 07/24/2015
-- Design Name:
-- Module Name: C:/Users/rccoder/ALU/CPU/clock_tb.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: clock
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY clock_tb IS
END clock_tb;
ARCHITECTURE behavior OF clock_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT clock
PORT(
clk : IN std_logic;
reset : IN std_logic;
t : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal t : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: clock PORT MAP (
clk => clk,
reset => reset,
t => t
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait for 100ns;
reset <= '1';
-- insert stimulus here
wait;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
begin
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then
err_state_out_Idle_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then
err_state_out_Idle_fault_out_fault_info_in <= '1';
else
err_state_out_Idle_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info_in)
begin
if (state_out = Packet_drop and fault_info_in = '1') then
err_state_out_Packet_drop_not_fault_info_in <= '1';
else
err_state_out_Packet_drop_not_fault_info_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
process (fault_info, fault_info_out)
begin
if (fault_info /= fault_info_out) then
err_fault_info_fault_info_out_equal <= '1';
else
err_fault_info_fault_info_out_equal <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1';
else
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
begin
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then
err_state_out_Idle_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then
err_state_out_Idle_fault_out_fault_info_in <= '1';
else
err_state_out_Idle_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info_in)
begin
if (state_out = Packet_drop and fault_info_in = '1') then
err_state_out_Packet_drop_not_fault_info_in <= '1';
else
err_state_out_Packet_drop_not_fault_info_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
process (fault_info, fault_info_out)
begin
if (fault_info /= fault_info_out) then
err_fault_info_fault_info_out_equal <= '1';
else
err_fault_info_fault_info_out_equal <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1';
else
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity FIFO_credit_based_control_part_checkers is
port ( valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
read_pointer: in std_logic_vector(3 downto 0);
read_pointer_in: in std_logic_vector(3 downto 0);
write_pointer: in std_logic_vector(3 downto 0);
write_pointer_in: in std_logic_vector(3 downto 0);
credit_out: in std_logic;
empty_out: in std_logic;
full_out: in std_logic;
read_en_out: in std_logic;
write_en_out: in std_logic;
fake_credit: in std_logic;
fake_credit_counter: in std_logic_vector(1 downto 0);
fake_credit_counter_in: in std_logic_vector(1 downto 0);
state_out: in std_logic_vector(4 downto 0);
state_in: in std_logic_vector(4 downto 0);
fault_info: in std_logic;
fault_info_out: in std_logic;
fault_info_in: in std_logic;
health_info: in std_logic;
faulty_packet_out: in std_logic;
faulty_packet_in: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
fault_out: in std_logic;
write_fake_flit: in std_logic;
-- Functional checkers
err_empty_full,
err_empty_read_en,
err_full_write_en,
err_state_in_onehot,
err_read_pointer_in_onehot,
err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer,
err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full,
err_read_pointer_increment,
err_read_pointer_not_increment,
err_write_en,
err_not_write_en,
err_not_write_en1,
err_not_write_en2,
err_read_en_mismatch,
err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_fault_info_in,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal : out std_logic
);
end FIFO_credit_based_control_part_checkers;
architecture behavior of FIFO_credit_based_control_part_checkers is
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
begin
-- Functional Checkers (Might cover or be covered by some of the structural checkers)
-- Empty and full cannot be high at the same time!
process (empty_out, full_out)
begin
if (empty_out = '1' and full_out = '1') then
err_empty_full <= '1';
else
err_empty_full <= '0';
end if;
end process;
-- Reading from an empty FIFO is not possible!
process (empty_out, read_en_out)
begin
if (empty_out = '1' and read_en_out = '1') then
err_empty_read_en <= '1';
else
err_empty_read_en <= '0';
end if;
end process;
-- Writing to a full FIFO is not possible!
process (full_out, write_en_out)
begin
if (full_out = '1' and write_en_out = '1') then
err_full_write_en <= '1';
else
err_full_write_en <= '0';
end if;
end process;
-- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)!
process (state_in)
begin
if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Read pointer must always be one-hot!
process (read_pointer_in)
begin
if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then
err_read_pointer_in_onehot <= '1';
else
err_read_pointer_in_onehot <= '0';
end if;
end process;
-- Write pointer must always be one-hot!
process (write_pointer_in)
begin
if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then
err_write_pointer_in_onehot <= '1';
else
err_write_pointer_in_onehot <= '0';
end if;
end process;
---------------------------------------------------------------------------------------------------------
-- Structural Checkers
-- Write pointer and Read pointer checkers
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then
err_write_en_write_pointer <= '1';
else
err_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (write_en_out, write_pointer_in, write_pointer)
begin
if (write_en_out = '0' and write_pointer_in /= write_pointer ) then
err_not_write_en_write_pointer <= '1';
else
err_not_write_en_write_pointer <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer = write_pointer and empty_out = '0' ) then
err_read_pointer_write_pointer_not_empty <= '1';
else
err_read_pointer_write_pointer_not_empty <= '0';
end if;
end process;
-- Checked !
process (read_pointer, write_pointer, empty_out)
begin
if (read_pointer /= write_pointer and empty_out = '1' ) then
err_read_pointer_write_pointer_empty <= '1';
else
err_read_pointer_write_pointer_empty <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then
err_read_pointer_write_pointer_not_full <= '1';
else
err_read_pointer_write_pointer_not_full <= '0';
end if;
end process;
-- Checked !
process (write_pointer, read_pointer, full_out)
begin
if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then
err_read_pointer_write_pointer_full <= '1';
else
err_read_pointer_write_pointer_full <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then
err_read_pointer_increment <= '1';
else
err_read_pointer_increment <= '0';
end if;
end process;
-- Checked !
process (read_en_out, empty_out, read_pointer_in, read_pointer)
begin
if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then
err_read_pointer_not_increment <= '1';
else
err_read_pointer_not_increment <= '0';
end if;
end process;
-- Checked !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then
err_write_en <= '1';
else
err_write_en <= '0';
end if;
end process;
-- Updated !
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then
err_not_write_en <= '1';
else
err_not_write_en <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then
err_not_write_en1 <= '1';
else
err_not_write_en1 <= '0';
end if;
end process;
process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out)
begin
if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then
err_not_write_en2 <= '1';
else
err_not_write_en2 <= '0';
end if;
end process;
-- Updated !
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then
err_read_en_mismatch <= '1';
else
err_read_en_mismatch <= '0';
end if;
end process;
process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out)
begin
if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then
err_read_en_mismatch1 <= '1';
else
err_read_en_mismatch1 <= '0';
end if;
end process;
-- Newly added checkers for FIFO with packet drop and fault classifier support!
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then
err_fake_credit_read_en_fake_credit_counter_in_increment <= '1';
else
err_fake_credit_read_en_fake_credit_counter_in_increment <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter)
begin
if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1';
else
err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0';
end if;
end process;
process (fake_credit, read_en_out, credit_out)
begin
if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then
err_fake_credit_read_en_credit_out <= '1';
else
err_fake_credit_read_en_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0';
end if;
end process;
process (fake_credit, read_en_out, fake_credit_counter, credit_out)
begin
if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1';
else
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
-- Idle state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, valid_in, state_in)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, fault_out, valid_in, state_in, state_out)
begin
if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1';
else
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0';
end if;
end process;
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '0' and fake_credit = '1') then
err_state_out_Idle_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Idle_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then
err_state_out_Idle_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Idle_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, fault_out, fake_credit)
begin
if (state_out = Idle and fault_out = '1' and fake_credit = '0') then
err_state_out_Idle_fault_out_fake_credit <= '1';
else
err_state_out_Idle_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, fault_out, state_in)
begin
if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Idle_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Idle_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, fault_out, fault_info_in)
begin
if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then
err_state_out_Idle_fault_out_fault_info_in <= '1';
else
err_state_out_Idle_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, fault_out, faulty_packet_in)
begin
if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Idle_fault_out_faulty_packet_in <= '1';
else
err_state_out_Idle_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Idle and write_fake_flit = '1') then
err_state_out_Idle_not_write_fake_flit <= '1';
else
err_state_out_Idle_not_write_fake_flit <= '0';
end if;
end process;
-- Other properties for Idle state
--------------------------------------------------------------------------------------------------
process (state_out, health_info)
begin
if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then
err_state_out_Idle_not_health_info <= '1';
else
err_state_out_Idle_not_health_info <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Header_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1';
else
err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Body_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, health_info)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, health_info)
begin
if (state_out = Body_flit and valid_in = '0' and health_info = '1') then
err_state_out_Body_flit_valid_in_not_health_info <= '1';
else
err_state_out_Body_flit_valid_in_not_health_info <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, fake_credit)
begin
if (state_out = Body_flit and fake_credit = '1') then
err_state_out_Body_flit_not_fake_credit <= '1';
else
err_state_out_Body_flit_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, write_fake_flit)
begin
if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Tail_flit state
-- fault_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, flit_type, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
-- fault_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, valid_in, fault_out, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, state_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, faulty_packet_in)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1';
else
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0';
end if;
end process;
process (state_out, valid_in, state_in)
begin
if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1';
else
err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0';
end if;
end process;
process (state_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1';
else
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0';
end if;
end process;
process (state_out, valid_in, fault_info_in)
begin
if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0';
end if;
end process;
process (state_out, valid_in, fake_credit)
begin
if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0';
end if;
end process;
process (state_out, write_fake_flit)
begin
if (state_out = Tail_flit and write_fake_flit = '1') then
err_state_out_Tail_flit_not_write_fake_flit <= '1';
else
err_state_out_Tail_flit_not_write_fake_flit <= '0';
end if;
end process;
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- Packet_drop state
-- faulty_packet_out = '1'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0';
end if;
end process;
-- faulty_packet_out = '0'
--------------------------------------------------------------------------------------------------
process (state_out, faulty_packet_out, state_in, state_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0';
end if;
end process;
process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0';
end if;
end process;
process (state_out, fault_info_in)
begin
if (state_out = Packet_drop and fault_info_in = '1') then
err_state_out_Packet_drop_not_fault_info_in <= '1';
else
err_state_out_Packet_drop_not_fault_info_in <= '0';
end if;
end process;
process (state_out, faulty_packet_out, fake_credit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0';
end if;
end process;
process (state_out, faulty_packet_out, write_fake_flit)
begin
if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1';
else
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0';
end if;
end process;
process (fault_info, fault_info_out)
begin
if (fault_info /= fault_info_out) then
err_fault_info_fault_info_out_equal <= '1';
else
err_fault_info_fault_info_out_equal <= '0';
end if;
end process;
process (state_out, valid_in, state_in, state_out)
begin
if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1';
else
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0';
end if;
end process;
process (state_out, valid_in, fault_out, flit_type, state_in, state_out)
begin
if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1';
else
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0';
end if;
end process;
end behavior; |
-------------------------------------------------------------------------------
-- --
-- Simple Cordic --
-- Copyright (C) 1999 HT-LAB --
-- --
-- Contact/Feedback : http://www.ht-lab.com/feedback.htm --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-- Shift Right preserving sign bit --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity REVERSE_BYTE_32b is
port (
INPUT_1 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end REVERSE_BYTE_32b;
architecture synthesis of REVERSE_BYTE_32b is
begin
OUTPUT_1(31 downto 0) <= INPUT_1(7 downto 0) & INPUT_1(15 downto 8) & INPUT_1(23 downto 16) & INPUT_1(31 downto 24);
end synthesis;
|
entity bounds17 is
end entity;
architecture test of bounds17 is
function get_bits(n : natural) return bit_vector is
begin
return (n - 1 downto 0 => '0');
end function;
begin
process is
variable x : bit_vector(7 downto 0) := get_bits(12);
begin
report "should not print this";
wait;
end process;
end architecture;
|
entity bounds17 is
end entity;
architecture test of bounds17 is
function get_bits(n : natural) return bit_vector is
begin
return (n - 1 downto 0 => '0');
end function;
begin
process is
variable x : bit_vector(7 downto 0) := get_bits(12);
begin
report "should not print this";
wait;
end process;
end architecture;
|
entity bounds17 is
end entity;
architecture test of bounds17 is
function get_bits(n : natural) return bit_vector is
begin
return (n - 1 downto 0 => '0');
end function;
begin
process is
variable x : bit_vector(7 downto 0) := get_bits(12);
begin
report "should not print this";
wait;
end process;
end architecture;
|
entity bounds17 is
end entity;
architecture test of bounds17 is
function get_bits(n : natural) return bit_vector is
begin
return (n - 1 downto 0 => '0');
end function;
begin
process is
variable x : bit_vector(7 downto 0) := get_bits(12);
begin
report "should not print this";
wait;
end process;
end architecture;
|
entity bounds17 is
end entity;
architecture test of bounds17 is
function get_bits(n : natural) return bit_vector is
begin
return (n - 1 downto 0 => '0');
end function;
begin
process is
variable x : bit_vector(7 downto 0) := get_bits(12);
begin
report "should not print this";
wait;
end process;
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000200";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000003ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000200";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000400";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000005ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000400"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(191 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 64;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000200";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000003ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000200";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000400";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000005ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000400"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(191 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 64;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000200";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000003ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000200";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000400";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000005ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000400"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(191 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 64;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : memc3_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is top level module for test bench. which instantiates
-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
-- port.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_SIMULATION : string := "FALSE";
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_SMALL_DEVICE : string := "FALSE";
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000200";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000003ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000200";
C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000400";
C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000005ff";
C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000400"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_cmd_en_o : out std_logic;
p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p1_mcb_cmd_full_i : in std_logic;
p1_mcb_wr_en_o : out std_logic;
p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_wr_full_i : in std_logic;
p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p1_mcb_rd_en_o : out std_logic;
p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_mcb_rd_empty_i : in std_logic;
p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
cmp_data : out std_logic_vector(31 downto 0);
cmp_data_valid : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(191 downto 0)
);
end memc3_tb_top;
architecture arc of memc3_tb_top is
function ERROR_DQWIDTH (val_i : integer) return integer is
begin
if (val_i = 4) then
return 1;
else
return val_i/8;
end if;
end function ERROR_DQWIDTH;
constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
component init_mem_pattern_ctr IS
generic (
FAMILY : string;
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
DWIDTH : integer;
CMD_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_SEED_VALUE : std_logic_vector(31 downto 0);
DATA_MODE : std_logic_vector(3 downto 0);
PORT_MODE : string
);
PORT (
clk_i : in std_logic;
rst_i : in std_logic;
mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_en_i : in std_logic;
mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
mcb_init_done_i : in std_logic;
mcb_wr_en_i : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
cmp_error : in std_logic;
run_traffic_o : out std_logic;
start_addr_o : out std_logic_vector(31 downto 0);
end_addr_o : out std_logic_vector(31 downto 0);
cmd_seed_o : out std_logic_vector(31 downto 0);
data_seed_o : out std_logic_vector(31 downto 0);
load_seed_o : out std_logic;
addr_mode_o : out std_logic_vector(2 downto 0);
instr_mode_o : out std_logic_vector(3 downto 0);
bl_mode_o : out std_logic_vector(1 downto 0);
data_mode_o : out std_logic_vector(3 downto 0);
mode_load_o : out std_logic;
fixed_bl_o : out std_logic_vector(5 downto 0);
fixed_instr_o : out std_logic_vector(2 downto 0);
fixed_addr_o : out std_logic_vector(31 downto 0)
);
end component;
component mcb_traffic_gen is
generic (
FAMILY : string;
SIMULATION : string;
MEM_BURST_LEN : integer;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string;
ADDR_WIDTH : integer;
CMP_DATA_PIPE_STAGES : integer;
MEM_COL_WIDTH : integer;
NUM_DQ_PINS : integer;
DQ_ERROR_WIDTH : integer;
DWIDTH : integer;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
PRBS_EADDR : std_logic_vector(31 downto 0);
PRBS_SADDR : std_logic_vector(31 downto 0)
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
run_traffic_i : in std_logic;
manual_clear_error : in std_logic;
-- *** runtime parameter ***
start_addr_i : in std_logic_vector(31 downto 0);
end_addr_i : in std_logic_vector(31 downto 0);
cmd_seed_i : in std_logic_vector(31 downto 0);
data_seed_i : in std_logic_vector(31 downto 0);
load_seed_i : in std_logic;
addr_mode_i : in std_logic_vector(2 downto 0);
instr_mode_i : in std_logic_vector(3 downto 0);
bl_mode_i : in std_logic_vector(1 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
mode_load_i : in std_logic;
-- fixed pattern inputs interface
fixed_bl_i : in std_logic_vector(5 downto 0);
fixed_instr_i : in std_logic_vector(2 downto 0);
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
--///////////////////////////////////////////////////////////////////////////
-- MCB INTERFACE
-- interface to mcb command port
mcb_cmd_en_o : out std_logic;
mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
-- interface to mcb wr data port
mcb_wr_en_o : out std_logic;
mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
mcb_wr_data_end_o : OUT std_logic;
mcb_wr_full_i : in std_logic;
mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
-- interface to mcb rd data port
mcb_rd_en_o : out std_logic;
mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
mcb_rd_empty_i : in std_logic;
mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
--///////////////////////////////////////////////////////////////////////////
-- status feedback
counts_rst : in std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end component;
-- Function to determine the number of data patterns to be generated
function DATA_PATTERN_CALC return string is
begin
if (C_SMALL_DEVICE = "FALSE") then
return "DGEN_ALL";
else
return "DGEN_ADDR";
end if;
end function;
constant FAMILY : string := "SPARTAN6";
constant DATA_PATTERN : string := DATA_PATTERN_CALC;
constant CMD_PATTERN : string := "CGEN_ALL";
constant ADDR_WIDTH : integer := 30;
constant CMP_DATA_PIPE_STAGES : integer := 0;
constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant p0_DWIDTH : integer := 64;
constant p1_DWIDTH : integer := 32;
constant p0_PORT_MODE : string := "BI_MODE";
constant p1_PORT_MODE : string := "BI_MODE";
--p0 Signal declarations
signal p0_tg_run_traffic : std_logic;
signal p0_tg_start_addr : std_logic_vector(31 downto 0);
signal p0_tg_end_addr : std_logic_vector(31 downto 0);
signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p0_tg_data_seed : std_logic_vector(31 downto 0);
signal p0_tg_load_seed : std_logic;
signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
signal p0_tg_mode_load : std_logic;
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
signal p0_error : std_logic;
signal p0_cmp_error : std_logic;
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
signal p0_cmp_data_valid : std_logic;
signal p0_mcb_cmd_en_o_int : std_logic;
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p0_mcb_wr_en_o_int : std_logic;
--p1 Signal declarations
signal p1_tg_run_traffic : std_logic;
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
signal p1_tg_load_seed : std_logic;
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
signal p1_tg_mode_load : std_logic;
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
signal p1_error : std_logic;
signal p1_cmp_error : std_logic;
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
signal p1_cmp_data_valid : std_logic;
signal p1_mcb_cmd_en_o_int : std_logic;
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
signal p1_mcb_wr_en_o_int : std_logic;
--signal cmp_data : std_logic_vector(31 downto 0);
begin
cmp_error <= p0_cmp_error or p1_cmp_error;
error <= p0_error or p1_error;
error_status <= p0_error_status;
cmp_data <= p0_cmp_data(31 downto 0);
cmp_data_valid <= p0_cmp_data_valid;
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
generic map
(
DWIDTH => p0_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
END_ADDRESS => C_p0_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p0_DATA_MODE,
PORT_MODE => p0_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
mcb_wr_en_i => p0_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p0_error,
run_traffic_o => p0_tg_run_traffic,
start_addr_o => p0_tg_start_addr,
end_addr_o => p0_tg_end_addr ,
cmd_seed_o => p0_tg_cmd_seed ,
data_seed_o => p0_tg_data_seed ,
load_seed_o => p0_tg_load_seed ,
addr_mode_o => p0_tg_addr_mode ,
instr_mode_o => p0_tg_instr_mode ,
bl_mode_o => p0_tg_bl_mode ,
data_mode_o => p0_tg_data_mode ,
mode_load_o => p0_tg_mode_load ,
fixed_bl_o => p0_tg_fixed_bl ,
fixed_instr_o => p0_tg_fixed_instr,
fixed_addr_o => p0_tg_fixed_addr
);
m_traffic_gen_p0 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p0_PORT_MODE,
DWIDTH => p0_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
PRBS_EADDR => C_p0_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p0_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p0_tg_start_addr ,
end_addr_i => p0_tg_end_addr ,
cmd_seed_i => p0_tg_cmd_seed ,
data_seed_i => p0_tg_data_seed ,
load_seed_i => p0_tg_load_seed,
addr_mode_i => p0_tg_addr_mode,
instr_mode_i => p0_tg_instr_mode ,
bl_mode_i => p0_tg_bl_mode ,
data_mode_i => p0_tg_data_mode ,
mode_load_i => p0_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p0_tg_fixed_bl,
fixed_instr_i => p0_tg_fixed_instr,
fixed_addr_i => p0_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p0_mcb_cmd_full_i,
mcb_wr_en_o => p0_mcb_wr_en_o_int,
mcb_wr_mask_o => p0_mcb_wr_mask_o,
mcb_wr_data_o => p0_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p0_mcb_wr_full_i,
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
mcb_rd_en_o => p0_mcb_rd_en_o,
mcb_rd_data_i => p0_mcb_rd_data_i,
mcb_rd_empty_i => p0_mcb_rd_empty_i,
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p0_cmp_data,
cmp_data_valid => p0_cmp_data_valid,
cmp_error => p0_cmp_error,
error => p0_error,
error_status => p0_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
generic map
(
DWIDTH => p1_DWIDTH,
FAMILY => FAMILY,
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
END_ADDRESS => C_p1_END_ADDRESS,
CMD_SEED_VALUE => X"56456783",
DATA_SEED_VALUE => X"12345678",
DATA_MODE => C_p1_DATA_MODE,
PORT_MODE => p1_PORT_MODE
)
port map
(
clk_i => clk0,
rst_i => rst0,
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
mcb_wr_en_i => p1_mcb_wr_en_o_int,
vio_modify_enable => vio_modify_enable,
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_bl_mode_value => "10",--vio_bl_mode_value,
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
mcb_init_done_i => calib_done,
cmp_error => p1_error,
run_traffic_o => p1_tg_run_traffic,
start_addr_o => p1_tg_start_addr,
end_addr_o => p1_tg_end_addr ,
cmd_seed_o => p1_tg_cmd_seed ,
data_seed_o => p1_tg_data_seed ,
load_seed_o => p1_tg_load_seed ,
addr_mode_o => p1_tg_addr_mode ,
instr_mode_o => p1_tg_instr_mode ,
bl_mode_o => p1_tg_bl_mode ,
data_mode_o => p1_tg_data_mode ,
mode_load_o => p1_tg_mode_load ,
fixed_bl_o => p1_tg_fixed_bl ,
fixed_instr_o => p1_tg_fixed_instr,
fixed_addr_o => p1_tg_fixed_addr
);
m_traffic_gen_p1 : mcb_traffic_gen
generic map(
MEM_BURST_LEN => C_MEM_BURST_LEN,
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
NUM_DQ_PINS => C_NUM_DQ_PINS,
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
PORT_MODE => p1_PORT_MODE,
DWIDTH => p1_DWIDTH,
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
FAMILY => FAMILY,
SIMULATION => "FALSE",
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => "CGEN_ALL",
ADDR_WIDTH => 30,
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
PRBS_EADDR => C_p1_END_ADDRESS
)
port map
(
clk_i => clk0,
rst_i => rst0,
run_traffic_i => p1_tg_run_traffic,
manual_clear_error => rst0,
-- runtime parameter
start_addr_i => p1_tg_start_addr ,
end_addr_i => p1_tg_end_addr ,
cmd_seed_i => p1_tg_cmd_seed ,
data_seed_i => p1_tg_data_seed ,
load_seed_i => p1_tg_load_seed,
addr_mode_i => p1_tg_addr_mode,
instr_mode_i => p1_tg_instr_mode ,
bl_mode_i => p1_tg_bl_mode ,
data_mode_i => p1_tg_data_mode ,
mode_load_i => p1_tg_mode_load ,
-- fixed pattern inputs interface
fixed_bl_i => p1_tg_fixed_bl,
fixed_instr_i => p1_tg_fixed_instr,
fixed_addr_i => p1_tg_fixed_addr,
fixed_data_i => (others => '0'),
-- BRAM interface.
bram_cmd_i => (others => '0'),
bram_valid_i => '0',
bram_rdy_o => open,
-- MCB INTERFACE
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
mcb_cmd_full_i => p1_mcb_cmd_full_i,
mcb_wr_en_o => p1_mcb_wr_en_o_int,
mcb_wr_mask_o => p1_mcb_wr_mask_o,
mcb_wr_data_o => p1_mcb_wr_data_o,
mcb_wr_data_end_o => open,
mcb_wr_full_i => p1_mcb_wr_full_i,
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
mcb_rd_en_o => p1_mcb_rd_en_o,
mcb_rd_data_i => p1_mcb_rd_data_i,
mcb_rd_empty_i => p1_mcb_rd_empty_i,
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
-- status feedback
counts_rst => rst0,
wr_data_counts => open,
rd_data_counts => open,
cmp_data => p1_cmp_data,
cmp_data_valid => p1_cmp_data_valid,
cmp_error => p1_cmp_error,
error => p1_error,
error_status => p1_error_status,
mem_rd_data => open,
dq_error_bytelane_cmp => open,
cumlative_dq_lane_error => open
);
end architecture;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter3 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter3;
ARCHITECTURE SYN OF lpm_counter3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter3 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END lpm_counter3;
ARCHITECTURE SYN OF lpm_counter3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(1 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 2
)
PORT MAP (
aclr => aclr,
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- Tesbench for testing the AXI handshaking wrapper for NI
-- Copyright (C) 2016 Karl Janson
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NI_AXI_handshake_wrapper_tb is
generic (
DATA_WIDTH : integer := 32;
NI_DEPTH : integer := 4
);
end NI_AXI_handshake_wrapper_tb;
architecture Behavioral of NI_AXI_handshake_wrapper_tb is
component AXI_handshake_wrapper is
generic (
DATA_WIDTH : integer := DATA_WIDTH;
NI_DEPTH : integer := NI_DEPTH
);
port (
reset : in std_logic;
clk : in std_logic;
--Router connection
R_RX : in std_logic_vector(DATA_WIDTH-1 downto 0);
R_TX : out std_logic_vector(DATA_WIDTH-1 downto 0);
R_DRTS : in std_logic;
R_DCTS : in std_logic;
R_RTS : out std_logic;
R_CTS : out std_logic;
-- Abstraction signals for AXI
AXI_RX_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_RX_IRQ_out : out std_logic;
AXI_data_read_in : in std_logic;
AXI_TX_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
AXI_send_en : in std_logic
);
end component;
signal reset : std_logic := '0';
signal clk : std_logic := '0';
--Router connection
signal R_RX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal R_TX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal R_DRTS : std_logic;
signal R_DCTS : std_logic;
signal R_RTS : std_logic;
signal R_CTS : std_logic;
-- Abstraction signals for AXI
signal AXI_RX_out : std_logic_vector(DATA_WIDTH-1 downto 0);
signal AXI_RX_IRQ_out : std_logic;
signal AXI_data_read_in : std_logic;
signal AXI_TX : std_logic_vector(DATA_WIDTH-1 downto 0);
signal AXI_send_en : std_logic;
signal counter: integer := 0;
signal counter_data_read: integer := 0;
begin
AXI_Network_interface: AXI_handshake_wrapper
port map (
reset => reset,
clk => clk,
--Router connection
R_RX => R_RX,
R_TX => R_TX,
R_DRTS => R_DRTS,
R_DCTS => R_DCTS,
R_RTS => R_RTS,
R_CTS => R_CTS,
-- Abstraction signals for AXI
AXI_RX_out => AXI_RX_out,
AXI_RX_IRQ_out => AXI_RX_IRQ_out,
AXI_data_read_in => AXI_data_read_in,
AXI_TX_in => AXI_TX,
AXI_send_en => AXI_send_en
);
clk <= not clk after 10 ns;
process (clk)
begin
if clk'event and clk = '1' then
if counter = 1 then
reset <= '1';
elsif counter = 3 then
AXI_TX <= x"11111111";
elsif counter = 8 then
AXI_send_en <= '1';
elsif counter = 9 then
AXI_send_en <= '0';
elsif counter = 13 then
AXI_TX <= x"22222222";
elsif counter = 14 then
AXI_send_en <= '1';
elsif counter = 15 then
AXI_send_en <= '0';
elsif counter = 19 then
AXI_TX <= x"33333333";
elsif counter = 20 then
AXI_send_en <= '1';
elsif counter = 21 then
AXI_send_en <= '0';
elsif counter = 25 then
AXI_TX <= x"44444444";
elsif counter = 26 then
AXI_send_en <= '1';
elsif counter = 27 then
AXI_send_en <= '0';
elsif counter = 33 then
AXI_TX <= x"55555555";
elsif counter = 34 then
AXI_send_en <= '1';
elsif counter = 35 then
AXI_send_en <= '0';
-- elsif counter = 40 then
-- AXI_data_read <= '1';
-- elsif counter = 41 then
-- AXI_data_read <= '0';
-- elsif counter = 44 then
-- AXI_data_read <= '1';
-- elsif counter = 45 then
-- AXI_data_read <= '0';
-- elsif counter = 50 then
-- AXI_data_read <= '1';
-- elsif counter = 51 then
-- AXI_data_read <= '0';
-- elsif counter = 55 then
-- AXI_data_read <= '1';
-- elsif counter = 56 then
-- AXI_data_read <= '0';
-- elsif counter = 60 then
-- AXI_data_read <= '1';
-- elsif counter = 61 then
-- AXI_data_read <= '0';
end if;
counter <= counter + 1;
end if;
end process;
AXI_read_data:process(clk)
begin
if clk'event and clk = '1' then
if (AXI_data_read_in = '1') then
AXI_data_read_in <= '0';
elsif (AXI_RX_IRQ_out = '1') then
counter_data_read <= counter_data_read + 1;
if (counter_data_read = 20) then
AXI_data_read_in <= '1';
counter_data_read <= 0;
end if;
end if;
end if;
end process;
R_RX <= R_TX;
R_DRTS <= R_RTS;
R_DCTS <= R_CTS;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sumador is
Port ( value1 : in STD_LOGIC_VECTOR (31 downto 0);
value2 : in STD_LOGIC_VECTOR (31 downto 0);
result : out STD_LOGIC_VECTOR (31 downto 0));
end sumador;
architecture Behavioral of sumador is
begin
process (value1, value2)
begin
result <= value2 + value1;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- Title : Event Hold Stage
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.V.
-- Platform : Xilinx Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- Extends and stores an event.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity event_hold_stage is
port(
dout_p : out std_logic; -- Data output
din_p : in std_logic; -- Data input
period_p : in std_logic; -- Next period
clk : in std_logic -- Clock input
);
end event_hold_stage;
-------------------------------------------------------------------------------
architecture behavioral of event_hold_stage is
type event_hold_stage_type is record
found : std_logic;
output : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : event_hold_stage_type := (found => '0',
output => '0');
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(r, din_p, period_p)
variable v : event_hold_stage_type;
begin
v := r;
if din_p = '1' then
v.found := '1';
end if;
if period_p = '1' then
v.output := v.found;
v.found := din_p;
end if;
rin <= v;
end process comb_proc;
dout_p <= r.output;
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : Event Hold Stage
-- Project : Loa
-------------------------------------------------------------------------------
-- Author : Fabian Greif <fabian.greif@rwth-aachen.de>
-- Company : Roboterclub Aachen e.V.
-- Platform : Xilinx Spartan 3
-------------------------------------------------------------------------------
-- Description:
--
-- Extends and stores an event.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity event_hold_stage is
port(
dout_p : out std_logic; -- Data output
din_p : in std_logic; -- Data input
period_p : in std_logic; -- Next period
clk : in std_logic -- Clock input
);
end event_hold_stage;
-------------------------------------------------------------------------------
architecture behavioral of event_hold_stage is
type event_hold_stage_type is record
found : std_logic;
output : std_logic;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : event_hold_stage_type := (found => '0',
output => '0');
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(r, din_p, period_p)
variable v : event_hold_stage_type;
begin
v := r;
if din_p = '1' then
v.found := '1';
end if;
if period_p = '1' then
v.output := v.found;
v.found := din_p;
end if;
rin <= v;
end process comb_proc;
dout_p <= r.output;
end behavioral;
|
-- $Id: sys_w11a_as7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_as7 - syn
-- Description: w11a design for as7 (with dram via mig)
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- bplib/artys7/sramif_mig_artys7
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_artys7
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x2mux
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_as7
--
-- Target Devices: generic
-- Tool versions: viv 2018.3-2022.1; ghdl 0.35-2.0.0
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7s50 6843 9162 878 17.5 3184
-- 2019-05-19 1150 2018.3 xc7s50 6843 10554 926 17.5 3425 +dz11
-- 2019-01-12 1105 2018.3 xc7s50 6585 9837 806 17.0 3250
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.0.1 use bufg_unisim
-- 2019-01-12 1105 1.0 Initial version (derived from sys_w11a_arty/br_as7)
------------------------------------------------------------------------------
--
-- w11a design for artys7 (using DDR3 memory via MIG)
-- w11a + rlink + serport
--
-- Usage of Arty S7 switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows bit 7:4, RGB bit 1:0 of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (1) kernel mode, non-wait
-- (0) user or supervisor mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (1:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR( 9:08)
-- RGB_G DR( 5:04)
-- RGB_R DR( 1:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib.all;
use work.miglib_artys7.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_as7 is -- top level
-- implements artys7_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3; -- artys7 rgb-led 1
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_w11a_as7;
architecture syn of sys_w11a_as7 is
signal CLK100_BUF : slbit := '0';
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLK : slbit := '0'; -- sync'ed to CLK
signal GBL_RESET : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal PERFEXT : slv8 := (others=>'0');
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal MIG_MONI : sramif2migui_moni_type := sramif2migui_moni_init;
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv2 := (others=>'0');
signal RGB_G : slv2 := (others=>'0');
signal RGB_B : slv2 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"0a"; -- artys7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 16, -- vco 1600 MHz
CLK2_OUTDIV => 10, -- mig sys 160.0 MHz
CLK3_OUTDIV => 8, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => CLK,
CE0_USEC => CE_USEC,
CE0_MSEC => CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
CDC_CLK_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_CLK
);
GBL_RESET <= not LOCKED_CLK;
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 9, -- 512 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
PERFEXT(0) <= MIG_MONI.rdrhit; -- ext_rdrhit
PERFEXT(1) <= MIG_MONI.wrrhit; -- ext_wrrhit
PERFEXT(2) <= MIG_MONI.wrflush; -- ext_wrflush
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
PERFEXT => PERFEXT,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_EXP => DM_STAT_EXP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
MEMCTL: sramif_mig_artys7 -- SRAM to MIG iface -----------------
port map (
CLK => CLK,
RESET => GBL_RESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO,
CLKMIG => CLKMIG,
CLKREF => CLKREF,
TEMP => XADC_TEMP,
MONI => MIG_MONI,
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_EXP => DM_STAT_EXP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x2mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1
);
SMRB : sysmonx_rbus_base -- always instantiated, needed for mig
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DESync is
port (
D, E, CLK : in std_logic;
Q : out std_logic
);
end DESync;
architecture Beh of DESync is
signal data : std_logic;
begin
process (E, CLK)
begin
if (E = '1') then
if (rising_edge(CLK)) then
data <= D;
end if;
end if;
end process;
Q <= data;
end Beh; |
entity issue521 is
end entity;
architecture test of issue521 is
signal i : natural;
signal j : natural;
begin
p1: process is
begin
i <= i + 1;
wait for 0 ns;
end process;
p2: process (i) is
begin
j <= i;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dw_mul_61x61
-- File: mul_dw_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: DW 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library DW02;
use DW02.DW02_components.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
u0 : DW02_mult_2_stage
generic map ( A_width => A'length, B_width => B'length )
port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dw_mul_61x61
-- File: mul_dw_gen.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: DW 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library DW02;
use DW02.DW02_components.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
u0 : DW02_mult_2_stage
generic map ( A_width => A'length, B_width => B'length )
port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i8255 is
port (
CLK : in std_logic;
RESET : in std_logic;
A : in std_logic_vector(1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WR : in std_logic;
PAI : in std_logic_vector(7 downto 0);
PAO : out std_logic_vector(7 downto 0);
PBI : in std_logic_vector(7 downto 0);
PBO : out std_logic_vector(7 downto 0);
PCI : in std_logic_vector(7 downto 0);
PCO : out std_logic_vector(7 downto 0));
end i8255;
architecture Behavioral of i8255 is
signal PORTA : std_logic_vector(7 downto 0);
signal PORTB : std_logic_vector(7 downto 0);
signal PORTC : std_logic_vector(7 downto 0);
signal CONTROL : std_logic_vector(7 downto 0);
begin
DO <= PAI when A = "00" and CONTROL(4) = '1' else
PORTA when A = "00" and CONTROL(4) = '0' else
PBI when A = "01" and CONTROL(1) = '1' else
PORTB when A = "01" and CONTROL(1) = '0' else
PCI when A = "10" and CONTROL(0) = '1' and CONTROL(3) = '1' else
PORTC when A = "10" and CONTROL(0) = '0' and CONTROL(3) = '0' else
PCI(7 downto 4) & PORTC(3 downto 0) when A = "10" and CONTROL(0) = '1' and CONTROL(3) = '0' else
PORTC(7 downto 4) & PCI(3 downto 0) when A = "10" and CONTROL(0) = '0' and CONTROL(3) = '1' else
CONTROL;
PAO <= PORTA;
PBO <= PORTB;
PCO <= PORTC;
registers_write : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
CONTROL <= "10011011";
PORTA <= "00000000";
PORTB <= "00000000";
PORTC <= "00000000";
else
if WR = '1' then
case A is
when "00" => PORTA <= DI;
when "01" => PORTB <= DI;
when "10" => PORTC <= DI;
when others => CONTROL <= DI;
if DI(7) = '0' then -- Bit set/reset
case DI(3 downto 1) is
when "000" => PORTC(0) <= DI(0);
when "001" => PORTC(1) <= DI(0);
when "010" => PORTC(2) <= DI(0);
when "011" => PORTC(3) <= DI(0);
when "100" => PORTC(4) <= DI(0);
when "101" => PORTC(5) <= DI(0);
when "110" => PORTC(6) <= DI(0);
when others => PORTC(7) <= DI(0);
end case;
end if;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1924.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01924ent IS
END c07s02b01x00p01n01i01924ent;
ARCHITECTURE c07s02b01x00p01n01i01924arch OF c07s02b01x00p01n01i01924ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 xor b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01924"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01924 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01924arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1924.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01924ent IS
END c07s02b01x00p01n01i01924ent;
ARCHITECTURE c07s02b01x00p01n01i01924arch OF c07s02b01x00p01n01i01924ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 xor b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01924"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01924 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01924arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1924.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01924ent IS
END c07s02b01x00p01n01i01924ent;
ARCHITECTURE c07s02b01x00p01n01i01924arch OF c07s02b01x00p01n01i01924ent IS
BEGIN
TESTING: PROCESS
variable b1 : Boolean := TRUE;
BEGIN
b1 := b1 xor b1;
assert NOT(b1 = FALSE)
report "***PASSED TEST: c07s02b01x00p01n01i01924"
severity NOTE;
assert (b1 = FALSE)
report "***FAILED TEST: c07s02b01x00p01n01i01924 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01924arch;
|
architecture RTL of FIFO is
begin
-- These are passing
a <= '0' when c = '0' else '1';
a <= '0' when c = '0' else-- Comment
'1' when c = '1' else -- comment
'0' when d = '1' else
'1';
-- Violations below
a <= '0' when c = '0' else '1' when c = '1' else '0' when d = '1' else '1';
a <= '0' when c = '0' else '1' when c = '1' else '0' when d =
'1' else '1';
a <= '0' when c = '0' else '1' when c =
'1' else '0' when d = '1' else '1';
end architecture RTL;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_scaler_mul_lbW_DSP48_0 is
port (
a: in std_logic_vector(20 - 1 downto 0);
b: in std_logic_vector(8 - 1 downto 0);
p: out std_logic_vector(28 - 1 downto 0));
end entity;
architecture behav of video_scaler_mul_lbW_DSP48_0 is
signal a_cvt: signed(20 - 1 downto 0);
signal b_cvt: unsigned(8 - 1 downto 0);
signal p_cvt: signed(28 - 1 downto 0);
begin
a_cvt <= signed(a);
b_cvt <= unsigned(b);
p_cvt <= signed (resize(unsigned (signed (a_cvt) * signed ('0' & b_cvt)), 28));
p <= std_logic_vector(p_cvt);
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity video_scaler_mul_lbW is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of video_scaler_mul_lbW is
component video_scaler_mul_lbW_DSP48_0 is
port (
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
video_scaler_mul_lbW_DSP48_0_U : component video_scaler_mul_lbW_DSP48_0
port map (
a => din0,
b => din1,
p => dout);
end architecture;
|
---------------------------------------------------------------------------
-- This file is part of lt24ctrl, a video controler IP core for Terrasic
-- LT24 LCD display
-- Copyright (C) 2017 Ludovic Noury <ludovic.noury@esiee.fr>
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
---------------------------------------------------------------------------
entity top is
port (
clock_50 : in std_logic;
key : in std_logic_vector(1 downto 0);
lt24_reset_n : out std_logic;
lt24_cs_n : out std_logic;
lt24_rs : out std_logic;
lt24_rd_n : out std_logic;
lt24_wr_n : out std_logic;
lt24_d : out std_logic_vector(15 downto 0);
lt24_lcd_on : out std_logic);
-- attribute useioff : boolean;
-- attribute useioff of lt24_reset_n : signal is true;
-- attribute useioff of lt24_cs_n : signal is true;
-- attribute useioff of lt24_rs : signal is true;
-- --attribute useioff of lt24_rd_n : signal is true;
-- attribute useioff of lt24_wr_n : signal is true;
-- attribute useioff of lt24_d : signal is true;
-- --attribute useioff of lt24_lcd_on : signal is true;
--
end entity top;
---------------------------------------------------------------------------
architecture inst of top is
signal x : std_logic_vector(7 downto 0); -- 0 .. 319 => 9 bits
signal y : std_logic_vector(8 downto 0); -- 0 .. 239 => 8 bits
signal c, c_rom, c_rom_reg, c_pat: std_logic_vector(15 downto 0); -- 16 bits colors
signal clk, resetn_pad, resetn_pad_reg1, resetn_sync : std_logic;
signal xy_to_address : std_logic_vector(17 downto 0);
-- Registers key(1) to exclude key(1) from critical path
signal selected_input : std_logic;
begin
--------------------------------------------------------------------
-- Synchronize reset (synchronous reset_sync assertion, but synchronous
-- reset_sync removal)
resetn_pad <= key(0);
clk <= clock_50;
sync_reset:process(resetn_pad, clk)
variable resetn_pad_reg0 : std_logic;
begin
if resetn_pad = '0' then
resetn_pad_reg0 := '0';
resetn_pad_reg1 <= '0';
elsif rising_edge(clk) then
resetn_pad_reg1 <= resetn_pad_reg0;
resetn_pad_reg0 := '1';
end if;
end process;
resetn_sync <= resetn_pad_reg1;
--------------------------------------------------------------------
-- registers used to split some critical paths
update_regs: process(resetn_sync, clk)
begin
if (resetn_sync = '0') then
selected_input <= '0';
c_rom_reg <= (others => '0');
xy_to_address<= (others => '0');
elsif rising_edge(clk) then
selected_input <= key(1);
c_rom_reg <= c_rom;
xy_to_address <= std_logic_vector(unsigned(x) +
unsigned(y)*to_unsigned(240,9)
-- -1 -- to compensate c_reg delay
);
end if;
end process;
--------------------------------------------------------------------
-- LT24 controller
-- Remark : LT24_RD_N and LR24_LCD_ON are always set.
lt24ctrl_0:entity work.lt24ctrl
generic map (
system_frequency => 50_000_000.0,
tmin_cycles => 1)
port map (
clk => clock_50,
resetn => resetn_sync,
x => x,
y => y,
c => c,
lt24_reset_n => lt24_reset_n,
lt24_cs_n => lt24_cs_n,
lt24_rs => lt24_rs,
lt24_rd_n => lt24_rd_n,
lt24_wr_n => lt24_wr_n,
lt24_d => lt24_d,
lt24_lcd_on => lt24_lcd_on);
--------------------------------------------------------------------
-- Select LCD screen input depending on key(1)
c <= c_rom_reg when selected_input = '1' else
c_pat;
-- Input 1 : static picture stored into a ROM
rom_img: entity work.rom_img
port map(
addr => xy_to_address(16 downto 0),
q => c_rom,
clk => clk);
-- Input 2 : pattern generator
genpix0: entity work.genpix
port map(
x => x,
y => y,
c => c_pat,
resetn => resetn_sync,
clk => clock_50);
end architecture inst;
---------------------------------------------------------------------------
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl
-- Design : ip_design_zed_audio_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WVALID_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
\DataTx_R_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
s_axi_rvalid_i_reg_0 : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
s_axi_bvalid_i_reg_1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^datatx_r_reg[0]\ : STD_LOGIC;
signal \^datatx_r_reg[0]_0\ : STD_LOGIC;
signal \^datatx_r_reg[0]_1\ : STD_LOGIC;
signal \^datatx_r_reg[0]_2\ : STD_LOGIC;
signal \^datatx_r_reg[0]_3\ : STD_LOGIC;
signal \^datatx_r_reg[0]_4\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\ : STD_LOGIC;
signal S_AXI_ARREADY_INST_0_i_1_n_0 : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_4 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal s_axi_bvalid_i0 : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[10]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[11]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[12]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[13]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[14]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[15]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[16]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[17]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[18]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[19]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[20]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[21]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[22]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[8]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_2_n_0\ : STD_LOGIC;
signal s_axi_rvalid_i0 : STD_LOGIC;
signal start : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of S_AXI_ARREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of S_AXI_AWREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of data_rdy_bit_i_2 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of s_axi_bvalid_i_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_rvalid_i_i_2 : label is "soft_lutpair0";
begin
\DataTx_R_reg[0]\ <= \^datatx_r_reg[0]\;
\DataTx_R_reg[0]_0\ <= \^datatx_r_reg[0]_0\;
\DataTx_R_reg[0]_1\ <= \^datatx_r_reg[0]_1\;
\DataTx_R_reg[0]_2\ <= \^datatx_r_reg[0]_2\;
\DataTx_R_reg[0]_3\ <= \^datatx_r_reg[0]_3\;
\DataTx_R_reg[0]_4\ <= \^datatx_r_reg[0]_4\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFF02020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
I5 => \^datatx_r_reg[0]_4\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^datatx_r_reg[0]_4\,
R => '0'
);
\DataTx_L[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_0\,
I1 => \^datatx_r_reg[0]_1\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => \DataTx_L_reg[0]\(0)
);
\DataTx_R[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_1\,
I1 => \^datatx_r_reg[0]_0\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => E(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202020202FF02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_4
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_4,
Q => \^datatx_r_reg[0]_3\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_3,
Q => \^datatx_r_reg[0]_2\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(1),
I2 => S_AXI_ARADDR(0),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(1),
I5 => S_AXI_AWADDR(0),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_2,
Q => \^datatx_r_reg[0]_1\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_ARADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_WVALID,
I2 => S_AXI_AWVALID,
I3 => Q(1),
I4 => Q(0),
I5 => S_AXI_AWADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_1,
Q => \^datatx_r_reg[0]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => S_AXI_ARESETN,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I2 => S_AXI_ARREADY_INST_0_i_1_n_0,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
O => start
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\,
I2 => S_AXI_AWADDR(1),
I3 => S_AXI_AWADDR(2),
I4 => S_AXI_AWADDR(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => S_AXI_ARADDR(0),
I1 => S_AXI_ARADDR(2),
I2 => S_AXI_ARADDR(1),
I3 => S_AXI_ARVALID,
I4 => Q(0),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_AWVALID,
I3 => S_AXI_WVALID,
I4 => S_AXI_ARVALID,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_0,
Q => \^datatx_r_reg[0]\,
R => cs_ce_clr
);
S_AXI_ARREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_ARREADY
);
S_AXI_ARREADY_INST_0_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]_1\,
O => S_AXI_ARREADY_INST_0_i_1_n_0
);
S_AXI_AWREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_AWREADY
);
data_rdy_bit_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg_0
);
data_rdy_bit_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \^datatx_r_reg[0]_3\,
I1 => \^datatx_r_reg[0]_2\,
I2 => \^datatx_r_reg[0]_1\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]\,
I5 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_bvalid_i0,
I1 => S_AXI_BREADY,
I2 => s_axi_bvalid_i_reg_1,
O => s_axi_bvalid_i_reg
);
s_axi_bvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(1),
I4 => Q(0),
O => s_axi_bvalid_i0
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAAEAAAEAAAEAAA"
)
port map (
I0 => \s_axi_rdata_i[0]_i_2_n_0\,
I1 => data_rdy_bit,
I2 => \^datatx_r_reg[0]\,
I3 => \s_axi_rdata_i[0]_i_3_n_0\,
I4 => \^datatx_r_reg[0]_0\,
I5 => \DataTx_R_reg[31]\(0),
O => \s_axi_rdata_i_reg[31]\(0)
);
\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \s_axi_rdata_i[0]_i_4_n_0\,
I1 => \DataTx_L_reg[31]\(0),
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(0),
I4 => \DataRx_L_reg[23]\(0),
I5 => \s_axi_rdata_i[23]_i_2_n_0\,
O => \s_axi_rdata_i[0]_i_2_n_0\
);
\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
O => \s_axi_rdata_i[0]_i_3_n_0\
);
\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_1\,
O => \s_axi_rdata_i[0]_i_4_n_0\
);
\s_axi_rdata_i[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(10),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(10),
I4 => \s_axi_rdata_i[10]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(10)
);
\s_axi_rdata_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(10),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(10),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[10]_i_2_n_0\
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(11),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(11),
I4 => \s_axi_rdata_i[11]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(11)
);
\s_axi_rdata_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(11),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(11),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[11]_i_2_n_0\
);
\s_axi_rdata_i[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(12),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(12),
I4 => \s_axi_rdata_i[12]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(12)
);
\s_axi_rdata_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(12),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(12),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[12]_i_2_n_0\
);
\s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(13),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(13),
I4 => \s_axi_rdata_i[13]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(13)
);
\s_axi_rdata_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(13),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(13),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[13]_i_2_n_0\
);
\s_axi_rdata_i[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(14),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(14),
I4 => \s_axi_rdata_i[14]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(14)
);
\s_axi_rdata_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(14),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(14),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[14]_i_2_n_0\
);
\s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(15),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(15),
I4 => \s_axi_rdata_i[15]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(15)
);
\s_axi_rdata_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(15),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(15),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[15]_i_2_n_0\
);
\s_axi_rdata_i[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(16),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(16),
I4 => \s_axi_rdata_i[16]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(16)
);
\s_axi_rdata_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(16),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(16),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[16]_i_2_n_0\
);
\s_axi_rdata_i[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(17),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(17),
I4 => \s_axi_rdata_i[17]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(17)
);
\s_axi_rdata_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(17),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(17),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[17]_i_2_n_0\
);
\s_axi_rdata_i[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(18),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(18),
I4 => \s_axi_rdata_i[18]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(18)
);
\s_axi_rdata_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(18),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(18),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[18]_i_2_n_0\
);
\s_axi_rdata_i[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(19),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(19),
I4 => \s_axi_rdata_i[19]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(19)
);
\s_axi_rdata_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(19),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(19),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[19]_i_2_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(1),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(1),
I4 => \s_axi_rdata_i[1]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(1)
);
\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(1),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[1]_i_2_n_0\
);
\s_axi_rdata_i[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(20),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(20),
I4 => \s_axi_rdata_i[20]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(20)
);
\s_axi_rdata_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(20),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(20),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[20]_i_2_n_0\
);
\s_axi_rdata_i[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(21),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(21),
I4 => \s_axi_rdata_i[21]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(21)
);
\s_axi_rdata_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(21),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(21),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[21]_i_2_n_0\
);
\s_axi_rdata_i[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(22),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(22),
I4 => \s_axi_rdata_i[22]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(22)
);
\s_axi_rdata_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(22),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(22),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[22]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(23),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(23),
I4 => \s_axi_rdata_i[23]_i_4_n_0\,
O => \s_axi_rdata_i_reg[31]\(23)
);
\s_axi_rdata_i[23]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_3\,
O => \s_axi_rdata_i[23]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_2\,
O => \s_axi_rdata_i[23]_i_3_n_0\
);
\s_axi_rdata_i[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(23),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(23),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[23]_i_4_n_0\
);
\s_axi_rdata_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(24),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(24),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(24)
);
\s_axi_rdata_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(25),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(25),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(25)
);
\s_axi_rdata_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(26),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(26),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(26)
);
\s_axi_rdata_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(27),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(27),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(27)
);
\s_axi_rdata_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(28),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(28),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(28)
);
\s_axi_rdata_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(29),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(29),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(29)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(2),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(2),
I4 => \s_axi_rdata_i[2]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(2)
);
\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(2),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(2),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[2]_i_2_n_0\
);
\s_axi_rdata_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(30),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(30),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(30)
);
\s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(31),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(31),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(31)
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(3),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(3),
I4 => \s_axi_rdata_i[3]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(3)
);
\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(3),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(3),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[3]_i_2_n_0\
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(4),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(4),
I4 => \s_axi_rdata_i[4]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(4)
);
\s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(4),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(4),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[4]_i_2_n_0\
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(5),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(5),
I4 => \s_axi_rdata_i[5]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(5)
);
\s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(5),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(5),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[5]_i_2_n_0\
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(6),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(6),
I4 => \s_axi_rdata_i[6]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(6)
);
\s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(6),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(6),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[6]_i_2_n_0\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(7),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(7),
I4 => \s_axi_rdata_i[7]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(7)
);
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(7),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(7),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[7]_i_2_n_0\
);
\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(8),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(8),
I4 => \s_axi_rdata_i[8]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(8)
);
\s_axi_rdata_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(8),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(8),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[8]_i_2_n_0\
);
\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(9),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(9),
I4 => \s_axi_rdata_i[9]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(9)
);
\s_axi_rdata_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(9),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(9),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[9]_i_2_n_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_rvalid_i0,
I1 => S_AXI_RREADY,
I2 => s_axi_rvalid_i_reg_0,
O => s_axi_rvalid_i_reg
);
s_axi_rvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EA00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(0),
I4 => Q(1),
O => s_axi_rvalid_i0
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF4"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARVALID,
I2 => s_axi_bvalid_i0,
I3 => s_axi_bvalid_i_reg_0,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF4454"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_WVALID_0,
I3 => S_AXI_ARVALID,
I4 => \state_reg[1]\,
I5 => s_axi_rvalid_i0,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser is
port (
lrclk_d1 : out STD_LOGIC;
sclk_d1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\rdata_reg_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\bit_cntr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sdata_reg_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]_0\ : out STD_LOGIC;
\DataRx_L_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_R_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
data_rdy_bit : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
SDATA_I : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser is
signal \^datarx_l_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^datarx_r_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_sequential_iis_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_4_n_0\ : STD_LOGIC;
signal \bit_cntr[4]_i_1_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal bit_rdy : STD_LOGIC;
signal data_rdy_bit_i_4_n_0 : STD_LOGIC;
signal eqOp : STD_LOGIC;
signal iis_state : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of iis_state : signal is "yes";
signal ldata_reg : STD_LOGIC;
signal ldata_reg0 : STD_LOGIC;
signal \^lrclk_d1\ : STD_LOGIC;
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rdata_reg0 : STD_LOGIC;
signal \^sclk_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DataRx_L[23]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \FSM_sequential_iis_state[2]_i_4\ : label is "soft_lutpair8";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[0]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[1]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[2]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_2__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of sdata_reg_i_2 : label is "soft_lutpair10";
begin
\DataRx_L_reg[23]\(23 downto 0) <= \^datarx_l_reg[23]\(23 downto 0);
\DataRx_R_reg[23]\(23 downto 0) <= \^datarx_r_reg[23]\(23 downto 0);
E(0) <= \^e\(0);
lrclk_d1 <= \^lrclk_d1\;
sclk_d1 <= \^sclk_d1\;
\DataRx_L[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => eqOp,
I1 => iis_state(2),
I2 => iis_state(1),
I3 => iis_state(0),
O => \^e\(0)
);
\DataRx_L[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(2),
O => eqOp
);
\FSM_onehot_iis_state[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(1),
O => \FSM_onehot_iis_state_reg[0]_0\
);
\FSM_onehot_iis_state[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(0),
O => \FSM_onehot_iis_state_reg[0]\
);
\FSM_sequential_iis_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75777F7745444044"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(0),
O => \FSM_sequential_iis_state[0]_i_1_n_0\
);
\FSM_sequential_iis_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3A7B3F7B0A480048"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(1),
O => \FSM_sequential_iis_state[1]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FB33FB30F800080"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(2),
O => \FSM_sequential_iis_state[2]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFA33FF000A330F"
)
port map (
I0 => bit_rdy,
I1 => \FSM_sequential_iis_state[2]_i_4_n_0\,
I2 => iis_state(2),
I3 => iis_state(0),
I4 => iis_state(1),
I5 => eqOp,
O => \FSM_sequential_iis_state[2]_i_2_n_0\
);
\FSM_sequential_iis_state[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22A222A2EEAE22A2"
)
port map (
I0 => bit_rdy,
I1 => iis_state(2),
I2 => iis_state(0),
I3 => iis_state(1),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_3_n_0\
);
\FSM_sequential_iis_state[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(1),
I1 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_4_n_0\
);
\FSM_sequential_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[0]_i_1_n_0\,
Q => iis_state(0),
R => '0'
);
\FSM_sequential_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[1]_i_1_n_0\,
Q => iis_state(1),
R => '0'
);
\FSM_sequential_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[2]_i_1_n_0\,
Q => iis_state(2),
R => '0'
);
\bit_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(0)
);
\bit_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__1\(1)
);
\bit_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(2)
);
\bit_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(3),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(3)
);
\bit_cntr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D7"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => bit_rdy
);
\bit_cntr[4]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^sclk_d1\,
I1 => Q(0),
O => \bit_cntr_reg[4]_0\(0)
);
\bit_cntr[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"78F0F0F0"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(2),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1_n_0\
);
data_rdy_bit_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC00EA0000000000"
)
port map (
I0 => data_rdy_bit,
I1 => \^e\(0),
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I4 => data_rdy_bit_i_4_n_0,
I5 => S_AXI_ARESETN,
O => data_rdy_bit_reg
);
data_rdy_bit_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000090000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => eqOp,
I3 => iis_state(2),
I4 => iis_state(1),
I5 => iis_state(0),
O => data_rdy_bit_i_4_n_0
);
\ldata_reg[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => ldata_reg
);
\ldata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(2),
I1 => iis_state(0),
I2 => iis_state(1),
I3 => Q(0),
I4 => \^sclk_d1\,
O => ldata_reg0
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => SDATA_I,
Q => \^datarx_l_reg[23]\(0),
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(9),
Q => \^datarx_l_reg[23]\(10),
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(10),
Q => \^datarx_l_reg[23]\(11),
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(11),
Q => \^datarx_l_reg[23]\(12),
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(12),
Q => \^datarx_l_reg[23]\(13),
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(13),
Q => \^datarx_l_reg[23]\(14),
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(14),
Q => \^datarx_l_reg[23]\(15),
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(15),
Q => \^datarx_l_reg[23]\(16),
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(16),
Q => \^datarx_l_reg[23]\(17),
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(17),
Q => \^datarx_l_reg[23]\(18),
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(18),
Q => \^datarx_l_reg[23]\(19),
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(0),
Q => \^datarx_l_reg[23]\(1),
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(19),
Q => \^datarx_l_reg[23]\(20),
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(20),
Q => \^datarx_l_reg[23]\(21),
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(21),
Q => \^datarx_l_reg[23]\(22),
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(22),
Q => \^datarx_l_reg[23]\(23),
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(1),
Q => \^datarx_l_reg[23]\(2),
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(2),
Q => \^datarx_l_reg[23]\(3),
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(3),
Q => \^datarx_l_reg[23]\(4),
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(4),
Q => \^datarx_l_reg[23]\(5),
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(5),
Q => \^datarx_l_reg[23]\(6),
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(6),
Q => \^datarx_l_reg[23]\(7),
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(7),
Q => \^datarx_l_reg[23]\(8),
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(8),
Q => \^datarx_l_reg[23]\(9),
R => ldata_reg
);
lrclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(1),
Q => \^lrclk_d1\,
R => '0'
);
\rdata_reg[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(0),
I1 => iis_state(1),
I2 => iis_state(2),
I3 => Q(0),
I4 => \^sclk_d1\,
O => rdata_reg0
);
\rdata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
I2 => \out\(2),
I3 => \out\(0),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \rdata_reg_reg[23]_0\(0)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => SDATA_I,
Q => \^datarx_r_reg[23]\(0),
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(9),
Q => \^datarx_r_reg[23]\(10),
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(10),
Q => \^datarx_r_reg[23]\(11),
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(11),
Q => \^datarx_r_reg[23]\(12),
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(12),
Q => \^datarx_r_reg[23]\(13),
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(13),
Q => \^datarx_r_reg[23]\(14),
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(14),
Q => \^datarx_r_reg[23]\(15),
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(15),
Q => \^datarx_r_reg[23]\(16),
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(16),
Q => \^datarx_r_reg[23]\(17),
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(17),
Q => \^datarx_r_reg[23]\(18),
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(18),
Q => \^datarx_r_reg[23]\(19),
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(0),
Q => \^datarx_r_reg[23]\(1),
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(19),
Q => \^datarx_r_reg[23]\(20),
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(20),
Q => \^datarx_r_reg[23]\(21),
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(21),
Q => \^datarx_r_reg[23]\(22),
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(22),
Q => \^datarx_r_reg[23]\(23),
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(1),
Q => \^datarx_r_reg[23]\(2),
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(2),
Q => \^datarx_r_reg[23]\(3),
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(3),
Q => \^datarx_r_reg[23]\(4),
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(4),
Q => \^datarx_r_reg[23]\(5),
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(5),
Q => \^datarx_r_reg[23]\(6),
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(6),
Q => \^datarx_r_reg[23]\(7),
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(7),
Q => \^datarx_r_reg[23]\(8),
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(8),
Q => \^datarx_r_reg[23]\(9),
R => ldata_reg
);
sclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(0),
Q => \^sclk_d1\,
R => '0'
);
sdata_reg_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => sdata_reg_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser is
port (
SDATA_O : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
sclk_d1 : in STD_LOGIC;
lrclk_d1 : in STD_LOGIC;
\DataTx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataTx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\clk_cntr_reg[4]\ : in STD_LOGIC;
lrclk_d1_reg : in STD_LOGIC;
lrclk_d1_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
sclk_d1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser is
signal \FSM_onehot_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_2_n_0\ : STD_LOGIC;
signal \^sdata_o\ : STD_LOGIC;
signal \bit_cntr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal eqOp : STD_LOGIC;
signal ldata_reg : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of ldata_reg : signal is "yes";
signal \ldata_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[17]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[18]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[21]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[22]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_1__0_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_2__0_n_0\ : STD_LOGIC;
signal \ldata_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_0_in2_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in2_in : signal is "yes";
signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 0 );
signal p_2_in : STD_LOGIC;
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \rdata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[23]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal sdata_reg_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_4\ : label is "soft_lutpair11";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[0]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[1]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[2]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[3]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[3]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[4]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3__0\ : label is "soft_lutpair11";
begin
SDATA_O <= \^sdata_o\;
\out\(2 downto 0) <= \^out\(2 downto 0);
\FSM_onehot_iis_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAABA"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(2),
I3 => \^out\(1),
I4 => \^out\(0),
O => \FSM_onehot_iis_state[1]_i_1_n_0\
);
\FSM_onehot_iis_state[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0ACA"
)
port map (
I0 => p_0_in2_in,
I1 => \^out\(0),
I2 => \FSM_onehot_iis_state[4]_i_1_n_0\,
I3 => ldata_reg,
O => \FSM_onehot_iis_state[2]_i_1_n_0\
);
\FSM_onehot_iis_state[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_0_in2_in,
I1 => ldata_reg,
I2 => \^out\(0),
O => \FSM_onehot_iis_state[3]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEEFFFFFEEEFFFF"
)
port map (
I0 => ldata_reg,
I1 => lrclk_d1_reg,
I2 => \^out\(2),
I3 => eqOp,
I4 => lrclk_d1_reg_0,
I5 => p_0_in2_in,
O => \FSM_onehot_iis_state[4]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(1),
I3 => \^out\(0),
O => \FSM_onehot_iis_state[4]_i_2_n_0\
);
\FSM_onehot_iis_state[4]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(2),
I3 => \bit_cntr_reg__0\(4),
I4 => \bit_cntr_reg__0\(3),
O => eqOp
);
\FSM_onehot_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => '0',
Q => ldata_reg,
R => '0'
);
\FSM_onehot_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[1]_i_1_n_0\,
Q => \^out\(0),
R => '0'
);
\FSM_onehot_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_onehot_iis_state[2]_i_1_n_0\,
Q => p_0_in2_in,
R => '0'
);
\FSM_onehot_iis_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[3]_i_1_n_0\,
Q => \^out\(1),
R => '0'
);
\FSM_onehot_iis_state_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[4]_i_2_n_0\,
Q => \^out\(2),
R => '0'
);
\bit_cntr[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__2\(0)
);
\bit_cntr[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__2\(1)
);
\bit_cntr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__2\(2)
);
\bit_cntr[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \bit_cntr_reg__0\(2),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(1),
I3 => \bit_cntr_reg__0\(3),
O => \plusOp__2\(3)
);
\bit_cntr[4]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^out\(2),
I1 => p_0_in2_in,
O => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr[4]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
I4 => \bit_cntr_reg__0\(4),
O => \plusOp__2\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1__0_n_0\
);
\ldata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_L_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => \ldata_reg[0]_i_1_n_0\
);
\ldata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(10),
O => \ldata_reg[10]_i_1_n_0\
);
\ldata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(11),
O => \ldata_reg[11]_i_1_n_0\
);
\ldata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(12),
O => \ldata_reg[12]_i_1_n_0\
);
\ldata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(13),
O => \ldata_reg[13]_i_1_n_0\
);
\ldata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(14),
O => \ldata_reg[14]_i_1_n_0\
);
\ldata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(15),
O => \ldata_reg[15]_i_1_n_0\
);
\ldata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(16),
O => \ldata_reg[16]_i_1_n_0\
);
\ldata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(17),
O => \ldata_reg[17]_i_1_n_0\
);
\ldata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(18),
O => \ldata_reg[18]_i_1_n_0\
);
\ldata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(19),
O => \ldata_reg[19]_i_1_n_0\
);
\ldata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(1),
O => \ldata_reg[1]_i_1_n_0\
);
\ldata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(20),
O => \ldata_reg[20]_i_1_n_0\
);
\ldata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(21),
O => \ldata_reg[21]_i_1_n_0\
);
\ldata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(22),
O => \ldata_reg[22]_i_1_n_0\
);
\ldata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => p_0_in2_in,
I1 => Q(0),
I2 => sclk_d1,
I3 => \^out\(0),
I4 => Q(1),
I5 => lrclk_d1,
O => \ldata_reg[23]_i_1__0_n_0\
);
\ldata_reg[23]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(23),
O => \ldata_reg[23]_i_2__0_n_0\
);
\ldata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(2),
O => \ldata_reg[2]_i_1_n_0\
);
\ldata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(3),
O => \ldata_reg[3]_i_1_n_0\
);
\ldata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(4),
O => \ldata_reg[4]_i_1_n_0\
);
\ldata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(5),
O => \ldata_reg[5]_i_1_n_0\
);
\ldata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(6),
O => \ldata_reg[6]_i_1_n_0\
);
\ldata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(7),
O => \ldata_reg[7]_i_1_n_0\
);
\ldata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(8),
O => \ldata_reg[8]_i_1_n_0\
);
\ldata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(9),
O => \ldata_reg[9]_i_1_n_0\
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[0]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[10]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[11]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[12]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[13]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[14]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[15]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[16]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[17]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[18]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[19]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[1]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[20]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[21]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[22]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[23]_i_2__0_n_0\,
Q => p_2_in,
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[2]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[3]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[4]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[5]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[6]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[7]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[8]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[9]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[9]\,
R => ldata_reg
);
\rdata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_R_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => p_1_in(0)
);
\rdata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(10),
O => p_1_in(10)
);
\rdata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(11),
O => p_1_in(11)
);
\rdata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(12),
O => p_1_in(12)
);
\rdata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(13),
O => p_1_in(13)
);
\rdata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(14),
O => p_1_in(14)
);
\rdata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(15),
O => p_1_in(15)
);
\rdata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(16),
O => p_1_in(16)
);
\rdata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(17),
O => p_1_in(17)
);
\rdata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(18),
O => p_1_in(18)
);
\rdata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(19),
O => p_1_in(19)
);
\rdata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(1),
O => p_1_in(1)
);
\rdata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(20),
O => p_1_in(20)
);
\rdata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(21),
O => p_1_in(21)
);
\rdata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(22),
O => p_1_in(22)
);
\rdata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(23),
O => p_1_in(23)
);
\rdata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(2),
O => p_1_in(2)
);
\rdata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(3),
O => p_1_in(3)
);
\rdata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(4),
O => p_1_in(4)
);
\rdata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(5),
O => p_1_in(5)
);
\rdata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(6),
O => p_1_in(6)
);
\rdata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(7),
O => p_1_in(7)
);
\rdata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(8),
O => p_1_in(8)
);
\rdata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(9),
O => p_1_in(9)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(0),
Q => \rdata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(10),
Q => \rdata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(11),
Q => \rdata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(12),
Q => \rdata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(13),
Q => \rdata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(14),
Q => \rdata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(15),
Q => \rdata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(16),
Q => \rdata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(17),
Q => \rdata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(18),
Q => \rdata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(19),
Q => \rdata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(1),
Q => \rdata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(20),
Q => \rdata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(21),
Q => \rdata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(22),
Q => \rdata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(23),
Q => \rdata_reg_reg_n_0_[23]\,
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(2),
Q => \rdata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(3),
Q => \rdata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(4),
Q => \rdata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(5),
Q => \rdata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(6),
Q => \rdata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(7),
Q => \rdata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(8),
Q => \rdata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(9),
Q => \rdata_reg_reg_n_0_[9]\,
R => ldata_reg
);
sdata_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCCAF0000CCA0"
)
port map (
I0 => \rdata_reg_reg_n_0_[23]\,
I1 => p_2_in,
I2 => \^out\(2),
I3 => p_0_in2_in,
I4 => \clk_cntr_reg[4]\,
I5 => \^sdata_o\,
O => sdata_reg_i_1_n_0
);
sdata_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => sdata_reg_i_1_n_0,
Q => \^sdata_o\,
R => ldata_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal I_DECODER_n_46 : STD_LOGIC;
signal I_DECODER_n_47 : STD_LOGIC;
signal I_DECODER_n_7 : STD_LOGIC;
signal I_DECODER_n_8 : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal timeout : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair4";
begin
S_AXI_BVALID <= \^s_axi_bvalid\;
S_AXI_RVALID <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I3 => timeout,
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(3),
Q => timeout,
R => p_2_out
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(1) => I_DECODER_n_7,
D(0) => I_DECODER_n_8,
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \DataTx_R_reg[0]\,
\DataTx_R_reg[0]_0\ => \DataTx_R_reg[0]_0\,
\DataTx_R_reg[0]_1\ => \DataTx_R_reg[0]_1\,
\DataTx_R_reg[0]_2\ => \DataTx_R_reg[0]_2\,
\DataTx_R_reg[0]_3\ => \DataTx_R_reg[0]_3\,
\DataTx_R_reg[0]_4\ => \DataTx_R_reg[0]_4\,
\DataTx_R_reg[31]\(31 downto 0) => Q(31 downto 0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0) => timeout,
Q(1 downto 0) => state(1 downto 0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WVALID_0 => \state[1]_i_2_n_0\,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0,
s_axi_bvalid_i_reg => I_DECODER_n_47,
s_axi_bvalid_i_reg_0 => \state[0]_i_2_n_0\,
s_axi_bvalid_i_reg_1 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[31]\(31 downto 0) => IP2Bus_Data(31 downto 0),
s_axi_rvalid_i_reg => I_DECODER_n_46,
s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
\state_reg[1]\ => \state[1]_i_3_n_0\
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => SR(0),
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_47,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(0),
Q => S_AXI_RDATA(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(10),
Q => S_AXI_RDATA(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(11),
Q => S_AXI_RDATA(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(12),
Q => S_AXI_RDATA(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(13),
Q => S_AXI_RDATA(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(14),
Q => S_AXI_RDATA(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(15),
Q => S_AXI_RDATA(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(16),
Q => S_AXI_RDATA(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(17),
Q => S_AXI_RDATA(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(18),
Q => S_AXI_RDATA(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(19),
Q => S_AXI_RDATA(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(1),
Q => S_AXI_RDATA(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(20),
Q => S_AXI_RDATA(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(21),
Q => S_AXI_RDATA(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(22),
Q => S_AXI_RDATA(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(23),
Q => S_AXI_RDATA(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(24),
Q => S_AXI_RDATA(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(25),
Q => S_AXI_RDATA(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(26),
Q => S_AXI_RDATA(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(27),
Q => S_AXI_RDATA(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(28),
Q => S_AXI_RDATA(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(29),
Q => S_AXI_RDATA(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(2),
Q => S_AXI_RDATA(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(30),
Q => S_AXI_RDATA(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(31),
Q => S_AXI_RDATA(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(3),
Q => S_AXI_RDATA(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(4),
Q => S_AXI_RDATA(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(5),
Q => S_AXI_RDATA(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(6),
Q => S_AXI_RDATA(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(7),
Q => S_AXI_RDATA(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(8),
Q => S_AXI_RDATA(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(9),
Q => S_AXI_RDATA(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_46,
Q => \^s_axi_rvalid\,
R => rst
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"07770000FFFF0000"
)
port map (
I0 => \^s_axi_bvalid\,
I1 => S_AXI_BREADY,
I2 => S_AXI_RREADY,
I3 => \^s_axi_rvalid\,
I4 => state(0),
I5 => state(1),
O => \state[0]_i_2_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(1),
I1 => \^s_axi_rvalid\,
I2 => S_AXI_RREADY,
I3 => S_AXI_BREADY,
I4 => \^s_axi_bvalid\,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_8,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_7,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic is
port (
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
data_rdy_bit : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic is
signal Inst_iis_deser_n_3 : STD_LOGIC;
signal Inst_iis_deser_n_33 : STD_LOGIC;
signal Inst_iis_deser_n_34 : STD_LOGIC;
signal Inst_iis_deser_n_35 : STD_LOGIC;
signal Inst_iis_deser_n_36 : STD_LOGIC;
signal Inst_iis_deser_n_37 : STD_LOGIC;
signal Inst_iis_deser_n_38 : STD_LOGIC;
signal Inst_iis_deser_n_39 : STD_LOGIC;
signal Inst_iis_deser_n_40 : STD_LOGIC;
signal Inst_iis_deser_n_41 : STD_LOGIC;
signal Inst_iis_deser_n_42 : STD_LOGIC;
signal Inst_iis_deser_n_43 : STD_LOGIC;
signal Inst_iis_deser_n_44 : STD_LOGIC;
signal Inst_iis_deser_n_45 : STD_LOGIC;
signal Inst_iis_deser_n_46 : STD_LOGIC;
signal Inst_iis_deser_n_47 : STD_LOGIC;
signal Inst_iis_deser_n_48 : STD_LOGIC;
signal Inst_iis_deser_n_49 : STD_LOGIC;
signal Inst_iis_deser_n_5 : STD_LOGIC;
signal Inst_iis_deser_n_50 : STD_LOGIC;
signal Inst_iis_deser_n_51 : STD_LOGIC;
signal Inst_iis_deser_n_52 : STD_LOGIC;
signal Inst_iis_deser_n_53 : STD_LOGIC;
signal Inst_iis_deser_n_54 : STD_LOGIC;
signal Inst_iis_deser_n_55 : STD_LOGIC;
signal Inst_iis_deser_n_56 : STD_LOGIC;
signal Inst_iis_deser_n_6 : STD_LOGIC;
signal Inst_iis_deser_n_7 : STD_LOGIC;
signal Inst_iis_deser_n_8 : STD_LOGIC;
signal Inst_iis_ser_n_1 : STD_LOGIC;
signal Inst_iis_ser_n_2 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \clk_cntr[10]_i_2_n_0\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[0]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[1]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[2]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[3]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[5]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[6]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[7]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[8]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[9]\ : STD_LOGIC;
signal data_rdy : STD_LOGIC;
signal \^data_rdy_bit\ : STD_LOGIC;
signal ldata_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal lrclk_d1 : STD_LOGIC;
signal p_0_in4_in : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^s_axi_rdata_i_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rdata_i_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal sclk_d1 : STD_LOGIC;
signal write_bit : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \clk_cntr[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[7]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[8]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \clk_cntr[9]_i_1\ : label is "soft_lutpair15";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
SR(0) <= \^sr\(0);
data_rdy_bit <= \^data_rdy_bit\;
\s_axi_rdata_i_reg[31]\(31 downto 0) <= \^s_axi_rdata_i_reg[31]\(31 downto 0);
\s_axi_rdata_i_reg[31]_0\(31 downto 0) <= \^s_axi_rdata_i_reg[31]_0\(31 downto 0);
\DataRx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(0),
Q => \s_axi_rdata_i_reg[23]\(0),
R => '0'
);
\DataRx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(10),
Q => \s_axi_rdata_i_reg[23]\(10),
R => '0'
);
\DataRx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(11),
Q => \s_axi_rdata_i_reg[23]\(11),
R => '0'
);
\DataRx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(12),
Q => \s_axi_rdata_i_reg[23]\(12),
R => '0'
);
\DataRx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(13),
Q => \s_axi_rdata_i_reg[23]\(13),
R => '0'
);
\DataRx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(14),
Q => \s_axi_rdata_i_reg[23]\(14),
R => '0'
);
\DataRx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(15),
Q => \s_axi_rdata_i_reg[23]\(15),
R => '0'
);
\DataRx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(16),
Q => \s_axi_rdata_i_reg[23]\(16),
R => '0'
);
\DataRx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(17),
Q => \s_axi_rdata_i_reg[23]\(17),
R => '0'
);
\DataRx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(18),
Q => \s_axi_rdata_i_reg[23]\(18),
R => '0'
);
\DataRx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(19),
Q => \s_axi_rdata_i_reg[23]\(19),
R => '0'
);
\DataRx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(1),
Q => \s_axi_rdata_i_reg[23]\(1),
R => '0'
);
\DataRx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(20),
Q => \s_axi_rdata_i_reg[23]\(20),
R => '0'
);
\DataRx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(21),
Q => \s_axi_rdata_i_reg[23]\(21),
R => '0'
);
\DataRx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(22),
Q => \s_axi_rdata_i_reg[23]\(22),
R => '0'
);
\DataRx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(23),
Q => \s_axi_rdata_i_reg[23]\(23),
R => '0'
);
\DataRx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(2),
Q => \s_axi_rdata_i_reg[23]\(2),
R => '0'
);
\DataRx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(3),
Q => \s_axi_rdata_i_reg[23]\(3),
R => '0'
);
\DataRx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(4),
Q => \s_axi_rdata_i_reg[23]\(4),
R => '0'
);
\DataRx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(5),
Q => \s_axi_rdata_i_reg[23]\(5),
R => '0'
);
\DataRx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(6),
Q => \s_axi_rdata_i_reg[23]\(6),
R => '0'
);
\DataRx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(7),
Q => \s_axi_rdata_i_reg[23]\(7),
R => '0'
);
\DataRx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(8),
Q => \s_axi_rdata_i_reg[23]\(8),
R => '0'
);
\DataRx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(9),
Q => \s_axi_rdata_i_reg[23]\(9),
R => '0'
);
\DataRx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_56,
Q => \s_axi_rdata_i_reg[23]_0\(0),
R => '0'
);
\DataRx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_46,
Q => \s_axi_rdata_i_reg[23]_0\(10),
R => '0'
);
\DataRx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_45,
Q => \s_axi_rdata_i_reg[23]_0\(11),
R => '0'
);
\DataRx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_44,
Q => \s_axi_rdata_i_reg[23]_0\(12),
R => '0'
);
\DataRx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_43,
Q => \s_axi_rdata_i_reg[23]_0\(13),
R => '0'
);
\DataRx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_42,
Q => \s_axi_rdata_i_reg[23]_0\(14),
R => '0'
);
\DataRx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_41,
Q => \s_axi_rdata_i_reg[23]_0\(15),
R => '0'
);
\DataRx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_40,
Q => \s_axi_rdata_i_reg[23]_0\(16),
R => '0'
);
\DataRx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_39,
Q => \s_axi_rdata_i_reg[23]_0\(17),
R => '0'
);
\DataRx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_38,
Q => \s_axi_rdata_i_reg[23]_0\(18),
R => '0'
);
\DataRx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_37,
Q => \s_axi_rdata_i_reg[23]_0\(19),
R => '0'
);
\DataRx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_55,
Q => \s_axi_rdata_i_reg[23]_0\(1),
R => '0'
);
\DataRx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_36,
Q => \s_axi_rdata_i_reg[23]_0\(20),
R => '0'
);
\DataRx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_35,
Q => \s_axi_rdata_i_reg[23]_0\(21),
R => '0'
);
\DataRx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_34,
Q => \s_axi_rdata_i_reg[23]_0\(22),
R => '0'
);
\DataRx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_33,
Q => \s_axi_rdata_i_reg[23]_0\(23),
R => '0'
);
\DataRx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_54,
Q => \s_axi_rdata_i_reg[23]_0\(2),
R => '0'
);
\DataRx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_53,
Q => \s_axi_rdata_i_reg[23]_0\(3),
R => '0'
);
\DataRx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_52,
Q => \s_axi_rdata_i_reg[23]_0\(4),
R => '0'
);
\DataRx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_51,
Q => \s_axi_rdata_i_reg[23]_0\(5),
R => '0'
);
\DataRx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_50,
Q => \s_axi_rdata_i_reg[23]_0\(6),
R => '0'
);
\DataRx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_49,
Q => \s_axi_rdata_i_reg[23]_0\(7),
R => '0'
);
\DataRx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_48,
Q => \s_axi_rdata_i_reg[23]_0\(8),
R => '0'
);
\DataRx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_47,
Q => \s_axi_rdata_i_reg[23]_0\(9),
R => '0'
);
\DataTx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]\(0),
R => \^sr\(0)
);
\DataTx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]\(10),
R => \^sr\(0)
);
\DataTx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]\(11),
R => \^sr\(0)
);
\DataTx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]\(12),
R => \^sr\(0)
);
\DataTx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]\(13),
R => \^sr\(0)
);
\DataTx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]\(14),
R => \^sr\(0)
);
\DataTx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]\(15),
R => \^sr\(0)
);
\DataTx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]\(16),
R => \^sr\(0)
);
\DataTx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]\(17),
R => \^sr\(0)
);
\DataTx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]\(18),
R => \^sr\(0)
);
\DataTx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]\(19),
R => \^sr\(0)
);
\DataTx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]\(1),
R => \^sr\(0)
);
\DataTx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]\(20),
R => \^sr\(0)
);
\DataTx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]\(21),
R => \^sr\(0)
);
\DataTx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]\(22),
R => \^sr\(0)
);
\DataTx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]\(23),
R => \^sr\(0)
);
\DataTx_L_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]\(24),
R => \^sr\(0)
);
\DataTx_L_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]\(25),
R => \^sr\(0)
);
\DataTx_L_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]\(26),
R => \^sr\(0)
);
\DataTx_L_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]\(27),
R => \^sr\(0)
);
\DataTx_L_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]\(28),
R => \^sr\(0)
);
\DataTx_L_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]\(29),
R => \^sr\(0)
);
\DataTx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]\(2),
R => \^sr\(0)
);
\DataTx_L_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]\(30),
R => \^sr\(0)
);
\DataTx_L_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]\(31),
R => \^sr\(0)
);
\DataTx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]\(3),
R => \^sr\(0)
);
\DataTx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]\(4),
R => \^sr\(0)
);
\DataTx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]\(5),
R => \^sr\(0)
);
\DataTx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]\(6),
R => \^sr\(0)
);
\DataTx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]\(7),
R => \^sr\(0)
);
\DataTx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]\(8),
R => \^sr\(0)
);
\DataTx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]\(9),
R => \^sr\(0)
);
\DataTx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]_0\(0),
R => \^sr\(0)
);
\DataTx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]_0\(10),
R => \^sr\(0)
);
\DataTx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]_0\(11),
R => \^sr\(0)
);
\DataTx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]_0\(12),
R => \^sr\(0)
);
\DataTx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]_0\(13),
R => \^sr\(0)
);
\DataTx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]_0\(14),
R => \^sr\(0)
);
\DataTx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]_0\(15),
R => \^sr\(0)
);
\DataTx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]_0\(16),
R => \^sr\(0)
);
\DataTx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]_0\(17),
R => \^sr\(0)
);
\DataTx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]_0\(18),
R => \^sr\(0)
);
\DataTx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]_0\(19),
R => \^sr\(0)
);
\DataTx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]_0\(1),
R => \^sr\(0)
);
\DataTx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]_0\(20),
R => \^sr\(0)
);
\DataTx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]_0\(21),
R => \^sr\(0)
);
\DataTx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]_0\(22),
R => \^sr\(0)
);
\DataTx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]_0\(23),
R => \^sr\(0)
);
\DataTx_R_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]_0\(24),
R => \^sr\(0)
);
\DataTx_R_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]_0\(25),
R => \^sr\(0)
);
\DataTx_R_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]_0\(26),
R => \^sr\(0)
);
\DataTx_R_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]_0\(27),
R => \^sr\(0)
);
\DataTx_R_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]_0\(28),
R => \^sr\(0)
);
\DataTx_R_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]_0\(29),
R => \^sr\(0)
);
\DataTx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]_0\(2),
R => \^sr\(0)
);
\DataTx_R_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]_0\(30),
R => \^sr\(0)
);
\DataTx_R_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]_0\(31),
R => \^sr\(0)
);
\DataTx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]_0\(3),
R => \^sr\(0)
);
\DataTx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]_0\(4),
R => \^sr\(0)
);
\DataTx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]_0\(5),
R => \^sr\(0)
);
\DataTx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]_0\(6),
R => \^sr\(0)
);
\DataTx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]_0\(7),
R => \^sr\(0)
);
\DataTx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]_0\(8),
R => \^sr\(0)
);
\DataTx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]_0\(9),
R => \^sr\(0)
);
Inst_iis_deser: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser
port map (
\DataRx_L_reg[23]\(23 downto 0) => ldata_reg(23 downto 0),
\DataRx_R_reg[23]\(23) => Inst_iis_deser_n_33,
\DataRx_R_reg[23]\(22) => Inst_iis_deser_n_34,
\DataRx_R_reg[23]\(21) => Inst_iis_deser_n_35,
\DataRx_R_reg[23]\(20) => Inst_iis_deser_n_36,
\DataRx_R_reg[23]\(19) => Inst_iis_deser_n_37,
\DataRx_R_reg[23]\(18) => Inst_iis_deser_n_38,
\DataRx_R_reg[23]\(17) => Inst_iis_deser_n_39,
\DataRx_R_reg[23]\(16) => Inst_iis_deser_n_40,
\DataRx_R_reg[23]\(15) => Inst_iis_deser_n_41,
\DataRx_R_reg[23]\(14) => Inst_iis_deser_n_42,
\DataRx_R_reg[23]\(13) => Inst_iis_deser_n_43,
\DataRx_R_reg[23]\(12) => Inst_iis_deser_n_44,
\DataRx_R_reg[23]\(11) => Inst_iis_deser_n_45,
\DataRx_R_reg[23]\(10) => Inst_iis_deser_n_46,
\DataRx_R_reg[23]\(9) => Inst_iis_deser_n_47,
\DataRx_R_reg[23]\(8) => Inst_iis_deser_n_48,
\DataRx_R_reg[23]\(7) => Inst_iis_deser_n_49,
\DataRx_R_reg[23]\(6) => Inst_iis_deser_n_50,
\DataRx_R_reg[23]\(5) => Inst_iis_deser_n_51,
\DataRx_R_reg[23]\(4) => Inst_iis_deser_n_52,
\DataRx_R_reg[23]\(3) => Inst_iis_deser_n_53,
\DataRx_R_reg[23]\(2) => Inst_iis_deser_n_54,
\DataRx_R_reg[23]\(1) => Inst_iis_deser_n_55,
\DataRx_R_reg[23]\(0) => Inst_iis_deser_n_56,
E(0) => data_rdy,
\FSM_onehot_iis_state_reg[0]\ => Inst_iis_deser_n_6,
\FSM_onehot_iis_state_reg[0]_0\ => Inst_iis_deser_n_8,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_I => SDATA_I,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
\bit_cntr_reg[4]_0\(0) => write_bit,
data_rdy_bit => \^data_rdy_bit\,
data_rdy_bit_reg => Inst_iis_deser_n_7,
lrclk_d1 => lrclk_d1,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
\rdata_reg_reg[23]_0\(0) => Inst_iis_deser_n_3,
sclk_d1 => sclk_d1,
sdata_reg_reg => Inst_iis_deser_n_5
);
Inst_iis_ser: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser
port map (
\DataTx_L_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]\(23 downto 0),
\DataTx_R_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]_0\(23 downto 0),
E(0) => Inst_iis_deser_n_3,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
\clk_cntr_reg[4]\ => Inst_iis_deser_n_5,
lrclk_d1 => lrclk_d1,
lrclk_d1_reg => Inst_iis_deser_n_8,
lrclk_d1_reg_0 => Inst_iis_deser_n_6,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
sclk_d1 => sclk_d1,
sclk_d1_reg(0) => write_bit
);
\clk_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
O => \plusOp__0\(0)
);
\clk_cntr[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFF08000000"
)
port map (
I0 => \clk_cntr_reg_n_0_[9]\,
I1 => \clk_cntr_reg_n_0_[7]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[6]\,
I4 => \clk_cntr_reg_n_0_[8]\,
I5 => \^q\(1),
O => \plusOp__0\(10)
);
\clk_cntr[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \clk_cntr[10]_i_2_n_0\
);
\clk_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
I1 => \clk_cntr_reg_n_0_[1]\,
O => \plusOp__0\(1)
);
\clk_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \clk_cntr_reg_n_0_[1]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[2]\,
O => \plusOp__0\(2)
);
\clk_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \clk_cntr_reg_n_0_[2]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[1]\,
I3 => \clk_cntr_reg_n_0_[3]\,
O => \plusOp__0\(3)
);
\clk_cntr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \clk_cntr_reg_n_0_[3]\,
I1 => \clk_cntr_reg_n_0_[1]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[2]\,
I4 => \^q\(0),
O => \plusOp__0\(4)
);
\clk_cntr[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \plusOp__0\(5)
);
\clk_cntr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \clk_cntr[10]_i_2_n_0\,
I1 => \clk_cntr_reg_n_0_[6]\,
O => \plusOp__0\(6)
);
\clk_cntr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \clk_cntr_reg_n_0_[6]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[7]\,
O => \plusOp__0\(7)
);
\clk_cntr[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \clk_cntr_reg_n_0_[7]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[6]\,
I3 => \clk_cntr_reg_n_0_[8]\,
O => \plusOp__0\(8)
);
\clk_cntr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \clk_cntr_reg_n_0_[8]\,
I1 => \clk_cntr_reg_n_0_[6]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[7]\,
I4 => \clk_cntr_reg_n_0_[9]\,
O => \plusOp__0\(9)
);
\clk_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(0),
Q => \clk_cntr_reg_n_0_[0]\,
R => '0'
);
\clk_cntr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(10),
Q => \^q\(1),
R => '0'
);
\clk_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(1),
Q => \clk_cntr_reg_n_0_[1]\,
R => '0'
);
\clk_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(2),
Q => \clk_cntr_reg_n_0_[2]\,
R => '0'
);
\clk_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(3),
Q => \clk_cntr_reg_n_0_[3]\,
R => '0'
);
\clk_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(4),
Q => \^q\(0),
R => '0'
);
\clk_cntr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(5),
Q => \clk_cntr_reg_n_0_[5]\,
R => '0'
);
\clk_cntr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(6),
Q => \clk_cntr_reg_n_0_[6]\,
R => '0'
);
\clk_cntr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(7),
Q => \clk_cntr_reg_n_0_[7]\,
R => '0'
);
\clk_cntr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(8),
Q => \clk_cntr_reg_n_0_[8]\,
R => '0'
);
\clk_cntr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(9),
Q => \clk_cntr_reg_n_0_[9]\,
R => '0'
);
data_rdy_bit_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Inst_iis_deser_n_7,
Q => \^data_rdy_bit\,
R => '0'
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => S_AXI_ARESETN,
O => \^sr\(0)
);
slv_ip2bus_data: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000400040448"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I5 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => \s_axi_rdata_i_reg[24]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\DataTx_R_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\DataTx_R_reg[0]_1\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\DataTx_R_reg[0]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\DataTx_R_reg[0]_3\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\DataTx_R_reg[0]_4\ => Bus_RNW_reg,
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(31 downto 0) => Q(31 downto 0),
SR(0) => SR(0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl is
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal DataRx_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataRx_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataTx_L : STD_LOGIC_VECTOR ( 31 downto 0 );
signal DataTx_R : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal USER_LOGIC_I_n_0 : STD_LOGIC;
signal USER_LOGIC_I_n_69 : STD_LOGIC;
signal data_rdy_bit : STD_LOGIC;
begin
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\DataRx_L_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => DataRx_R(23 downto 0),
\DataTx_L_reg[0]\(0) => AXI_LITE_IPIF_I_n_12,
\DataTx_L_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
E(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => USER_LOGIC_I_n_0,
Q(31 downto 0) => DataTx_R(31 downto 0),
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => AXI_LITE_IPIF_I_n_8,
data_rdy_bit_reg_0 => AXI_LITE_IPIF_I_n_13
);
USER_LOGIC_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_8,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI_LITE_IPIF_I_n_13,
Q(1 downto 0) => \out\(1 downto 0),
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
data_rdy_bit => data_rdy_bit,
\s_axi_rdata_i_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\s_axi_rdata_i_reg[23]_0\(23 downto 0) => DataRx_R(23 downto 0),
\s_axi_rdata_i_reg[24]\ => USER_LOGIC_I_n_0,
\s_axi_rdata_i_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
\s_axi_rdata_i_reg[31]_0\(31 downto 0) => DataTx_R(31 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_zed_audio_ctrl_0_0,i2s_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "i2s_ctrl,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
attribute max_fanout : string;
attribute max_fanout of S_AXI_ACLK : signal is "10000";
attribute sigis : string;
attribute sigis of S_AXI_ACLK : signal is "Clk";
attribute x_interface_info : string;
attribute x_interface_info of S_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of S_AXI_ACLK : signal is "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute max_fanout of S_AXI_ARESETN : signal is "10000";
attribute sigis of S_AXI_ARESETN : signal is "Rst";
attribute x_interface_info of S_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST";
attribute x_interface_parameter of S_AXI_ARESETN : signal is "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of S_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of S_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of S_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of S_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of S_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of S_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of S_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of S_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of S_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of S_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of S_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of S_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of S_AXI_AWADDR : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of S_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of S_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of S_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of S_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of S_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_BRESP(1) <= \<const0>\;
S_AXI_BRESP(0) <= \<const0>\;
S_AXI_RRESP(1) <= \<const0>\;
S_AXI_RRESP(0) <= \<const0>\;
S_AXI_WREADY <= \^s_axi_awready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl
port map (
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(4 downto 2),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(4 downto 2),
S_AXI_AWREADY => \^s_axi_awready\,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
S_AXI_WVALID => S_AXI_WVALID,
\out\(1) => LRCLK,
\out\(0) => BCLK
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:52:28 06/27/2015
-- Design Name:
-- Module Name: hea_tb.vhd
-- Project Name: adder
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: hea
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY hea_tb IS
END hea_tb;
ARCHITECTURE behavior OF hea_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hea
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
s : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
signal b : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal s : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hea PORT MAP (
a => a,
b => b,
s => s
);
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
a<="1010";
b<="0110";
wait for 10 ns;
a<="0011";
b<="1000";
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:17:26 05/29/2011
-- Design Name:
-- Module Name: miner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity miner is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
data : in STD_LOGIC_VECTOR (95 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
nonce : in STD_LOGIC_VECTOR (31 downto 0);
hit : out STD_LOGIC);
end miner;
architecture Behavioral of miner is
COMPONENT sha256_pipeline
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : IN std_logic_vector(255 downto 0);
input : IN std_logic_vector(511 downto 0);
hash : OUT std_logic_vector(255 downto 0)
);
END COMPONENT;
constant innerprefix : std_logic_vector(383 downto 0) := x"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000";
constant outerprefix : std_logic_vector(255 downto 0) := x"0000010000000000000000000000000000000000000000000000000080000000";
constant outerstate : std_logic_vector(255 downto 0) := x"5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667";
signal innerdata : std_logic_vector(511 downto 0);
signal outerdata : std_logic_vector(511 downto 0);
signal innerhash : std_logic_vector(255 downto 0);
signal outerhash : std_logic_vector(255 downto 0);
begin
innerdata <= innerprefix & nonce & data;
outerdata <= outerprefix & innerhash;
hit <= '1' when outerhash(255 downto 224) = x"00000000" and step = "000000" else '0';
inner: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => state,
input => innerdata,
hash => innerhash
);
outer: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => outerstate,
input => outerdata,
hash => outerhash
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:17:26 05/29/2011
-- Design Name:
-- Module Name: miner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity miner is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
data : in STD_LOGIC_VECTOR (95 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
nonce : in STD_LOGIC_VECTOR (31 downto 0);
hit : out STD_LOGIC);
end miner;
architecture Behavioral of miner is
COMPONENT sha256_pipeline
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : IN std_logic_vector(255 downto 0);
input : IN std_logic_vector(511 downto 0);
hash : OUT std_logic_vector(255 downto 0)
);
END COMPONENT;
constant innerprefix : std_logic_vector(383 downto 0) := x"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000";
constant outerprefix : std_logic_vector(255 downto 0) := x"0000010000000000000000000000000000000000000000000000000080000000";
constant outerstate : std_logic_vector(255 downto 0) := x"5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667";
signal innerdata : std_logic_vector(511 downto 0);
signal outerdata : std_logic_vector(511 downto 0);
signal innerhash : std_logic_vector(255 downto 0);
signal outerhash : std_logic_vector(255 downto 0);
begin
innerdata <= innerprefix & nonce & data;
outerdata <= outerprefix & innerhash;
hit <= '1' when outerhash(255 downto 224) = x"00000000" and step = "000000" else '0';
inner: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => state,
input => innerdata,
hash => innerhash
);
outer: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => outerstate,
input => outerdata,
hash => outerhash
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:17:26 05/29/2011
-- Design Name:
-- Module Name: miner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity miner is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
data : in STD_LOGIC_VECTOR (95 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
nonce : in STD_LOGIC_VECTOR (31 downto 0);
hit : out STD_LOGIC);
end miner;
architecture Behavioral of miner is
COMPONENT sha256_pipeline
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : IN std_logic_vector(255 downto 0);
input : IN std_logic_vector(511 downto 0);
hash : OUT std_logic_vector(255 downto 0)
);
END COMPONENT;
constant innerprefix : std_logic_vector(383 downto 0) := x"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000";
constant outerprefix : std_logic_vector(255 downto 0) := x"0000010000000000000000000000000000000000000000000000000080000000";
constant outerstate : std_logic_vector(255 downto 0) := x"5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667";
signal innerdata : std_logic_vector(511 downto 0);
signal outerdata : std_logic_vector(511 downto 0);
signal innerhash : std_logic_vector(255 downto 0);
signal outerhash : std_logic_vector(255 downto 0);
begin
innerdata <= innerprefix & nonce & data;
outerdata <= outerprefix & innerhash;
hit <= '1' when outerhash(255 downto 224) = x"00000000" and step = "000000" else '0';
inner: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => state,
input => innerdata,
hash => innerhash
);
outer: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => outerstate,
input => outerdata,
hash => outerhash
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:17:26 05/29/2011
-- Design Name:
-- Module Name: miner - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity miner is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
data : in STD_LOGIC_VECTOR (95 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
nonce : in STD_LOGIC_VECTOR (31 downto 0);
hit : out STD_LOGIC);
end miner;
architecture Behavioral of miner is
COMPONENT sha256_pipeline
generic ( DEPTH : integer );
PORT(
clk : IN std_logic;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : IN std_logic_vector(255 downto 0);
input : IN std_logic_vector(511 downto 0);
hash : OUT std_logic_vector(255 downto 0)
);
END COMPONENT;
constant innerprefix : std_logic_vector(383 downto 0) := x"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000";
constant outerprefix : std_logic_vector(255 downto 0) := x"0000010000000000000000000000000000000000000000000000000080000000";
constant outerstate : std_logic_vector(255 downto 0) := x"5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667";
signal innerdata : std_logic_vector(511 downto 0);
signal outerdata : std_logic_vector(511 downto 0);
signal innerhash : std_logic_vector(255 downto 0);
signal outerhash : std_logic_vector(255 downto 0);
begin
innerdata <= innerprefix & nonce & data;
outerdata <= outerprefix & innerhash;
hit <= '1' when outerhash(255 downto 224) = x"00000000" and step = "000000" else '0';
inner: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => state,
input => innerdata,
hash => innerhash
);
outer: sha256_pipeline
generic map ( DEPTH => DEPTH )
port map (
clk => clk,
step => step,
state => outerstate,
input => outerdata,
hash => outerhash
);
end Behavioral;
|
--------------------------------------------------------------------------------
-- Title : RX module v2
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : rx_module.vhd
-- Author : Susanne Reinfelder
-- Email : susanne.reinfelder@men.de
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2013-01-23
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6d / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- combines modules rx_get_data.vhd, rx_ctrl.vhd and 2 FIFO's
-- to calculate valid values for RX_FIFO_DEPTH refer to ug_fifo.pdf page 9
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- * rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity rx_module is
generic(
DEVICE_FAMILY : string := "unused";
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
RX_FIFO_DEPTH : natural := 1024; -- valid values are: 2^(RX_LPM_WIDTHU-1) < RX_FIFO_DEPTH <= 2^(RX_LPM_WIDTHU)
RX_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
rst : in std_logic;
-- IP Core
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
-- FIFO
rx_fifo_c_rd_enable : in std_logic;
rx_fifo_wr_rd_enable : in std_logic;
rx_fifo_c_empty : out std_logic;
rx_fifo_wr_empty : out std_logic;
rx_fifo_c_out : out std_logic_vector(31 downto 0);
rx_fifo_wr_out : out std_logic_vector(31 downto 0);
-- Tx Module
rx_tag_nbr : out std_logic_vector(7 downto 0);
rx_tag_rcvd : out std_logic;
-- error
rx_type_fmt_err : out std_logic_vector(1 downto 0);
rx_ecrc_err : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end entity rx_module;
architecture rx_module_arch of rx_module is
-- +----------------------------------------------------------------------------
-- | functions or procedures
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component rx_ctrl
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
tlp_type_i : in std_logic_vector(4 downto 0);
tlp_fmt_i : in std_logic_vector(2 downto 0);
-- FIFO
rx_fifo_c_enable_o : out std_logic;
rx_fifo_wr_enable_o : out std_logic;
-- rx_sig_manage
sop_q_i : in std_logic;
fifo_action_done_o : out std_logic;
-- rx_get_data
len_cntr_val_i : in std_logic_vector(9 downto 0)
);
end component;
component rx_get_data
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_valid0 : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_sop0 : in std_logic;
-- FIFO
rx_fifo_in_o : out std_logic_vector(63 downto 0);
-- tx_ctrl
tag_nbr_o : out std_logic_vector(7 downto 0);
tag_rcvd_o : out std_logic;
-- rx_ctrl
len_cntr_val_o : out std_logic_vector(9 downto 0);
-- error
type_fmt_err_o : out std_logic_vector(1 downto 0);
-- rx_sig_manage
sop_q_i : in std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
-- rx_ctrl and rx_get_data connection signals
signal int_len_cntr_val : std_logic_vector(9 downto 0);
signal int_fifo_action_done : std_logic;
-- FIFO signals
signal int_c_wr_enable : std_logic;
signal int_c_wr_full : std_logic;
signal int_rx_wrusedw_c : std_logic_vector(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_wrusedw_c_temp : std_logic_vector(9 downto 0);
signal int_rx_fifo_c_usedw : std_logic_vector(9 downto 0);
signal int_wr_wr_enable : std_logic;
signal int_wr_wr_full : std_logic;
signal int_rx_wrusedw_wr : std_logic_vector(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_wrusedw_wr_temp : std_logic_vector(9 downto 0);
signal int_rx_fifo_wr_usedw : std_logic_vector(9 downto 0);
signal int_rx_fifo_data : std_logic_vector(63 downto 0);
-- signals for signal management process
signal int_ready : std_logic;
signal int_sop : std_logic;
signal int_err : std_logic;
signal int_sop_q : std_logic;
signal int_tlp_type : std_logic_vector(4 downto 0);
signal int_tlp_fmt : std_logic_vector(2 downto 0);
-- define some aliases for easier handling
alias rx_data0_type is rx_st_data0(28 downto 24);
alias rx_data0_fmt is rx_st_data0(31 downto 29);
-- debug signals: none
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
rx_st_mask0 <= '0';
rx_st_ready0 <= int_ready;
int_rx_wrusedw_c_temp <= std_logic_vector(to_unsigned(to_integer(unsigned(int_rx_wrusedw_c)),10));
int_rx_wrusedw_wr_temp <= std_logic_vector(to_unsigned(to_integer(unsigned(int_rx_wrusedw_wr)),10));
int_rx_fifo_c_usedw <= int_rx_wrusedw_c_temp;
int_rx_fifo_wr_usedw <= int_rx_wrusedw_wr_temp;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
-- registers to remembe the type and fmt for the last received TLP
process(rst, clk)
begin
if rising_edge(clk) then
if rst = '1' then
int_tlp_type <= (others=>'0');
elsif (rx_st_valid0 = '1' and rx_st_sop0 = '1') then
int_tlp_type <= rx_data0_type;
end if;
end if;
end process;
process(rst, clk)
begin
if rising_edge(clk) then
if rst = '1' then
int_tlp_fmt <= (others=>'0');
elsif (rx_st_valid0 = '1' and rx_st_sop0 = '1') then
int_tlp_fmt <= rx_data0_fmt;
end if;
end if;
end process;
rx_sig_manage : process(rst, clk)
begin
if rst = '1' then
int_ready <= '0';
int_sop <= '0';
int_err <= '0';
int_sop_q <= '0';
elsif clk'event and clk = '1' then
------------------------------
-- manage registered signals
------------------------------
int_sop_q <= rx_st_sop0;
--------------------------------------
-- signal ECRC error to error module
--------------------------------------
if rx_st_err0 = '1' and int_err = '0' then
rx_ecrc_err <= '1';
else
rx_ecrc_err <= '0';
end if;
-------------------------------------------------------
-- if an error state occured reset ready signal
-- until rx_ctrl has finished processing the error
-- if the FIFOs are not full assert ready
-- else deassert it until the FIFOs are not full
-------------------------------------------------------
if ((int_err = '1' or rx_st_err0 = '1') and rx_st_eop0 = '1' and rx_st_valid0 = '1') or
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw >= FIFO_MAX_USEDW) or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw >= FIFO_MAX_USEDW) then
int_ready <= '0';
elsif int_err = '0' and (
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw < FIFO_MAX_USEDW and int_c_wr_full = '0') or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw < FIFO_MAX_USEDW and int_wr_wr_full = '0')
) then
int_ready <= '1';
end if;
-----------------------------------------------------------------
-- reset error flag if rx_ctrl has finished working on the fifo
-- set error flag if error ocurs during transmission
-- otherwise keep error flag value
-----------------------------------------------------------------
if int_fifo_action_done = '1' then
int_err <= '0';
elsif rx_st_err0 = '1' and rx_st_valid0 = '1' then
int_err <= '1';
else
int_err <= int_err;
end if;
if rx_st_valid0 = '1' and rx_st_eop0 = '1' then
int_sop <= '0';
elsif rx_st_valid0 = '1' and rx_st_sop0 = '1' then
int_sop <= '1';
else
int_sop <= int_sop;
end if;
end if;
end process rx_sig_manage;
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
rx_ctrl_comp : rx_ctrl
port map(
clk_i => clk,
rst_i => rst,
-- Hard IP
rx_st_err0 => rx_st_err0,
rx_st_valid0 => rx_st_valid0,
rx_st_sop0 => rx_st_sop0,
rx_st_eop0 => rx_st_eop0,
rx_st_be0 => rx_st_be0,
tlp_type_i => rx_data0_type,
tlp_fmt_i => rx_data0_fmt,
-- FIFO
rx_fifo_c_enable_o => int_c_wr_enable,
rx_fifo_wr_enable_o => int_wr_wr_enable,
-- rx_sig_manage
sop_q_i => int_sop_q,
fifo_action_done_o => int_fifo_action_done,
-- rx_get_data
len_cntr_val_i => int_len_cntr_val
);
rx_get_data_comp : rx_get_data
port map(
clk_i => clk,
rst_i => rst,
-- Hard IP
rx_st_valid0 => rx_st_valid0,
rx_st_data0 => rx_st_data0,
rx_st_bardec0 => rx_st_bardec0,
rx_st_sop0 => rx_st_sop0,
-- FIFO
rx_fifo_in_o => int_rx_fifo_data,
-- tx_ctrl
tag_nbr_o => rx_tag_nbr,
tag_rcvd_o => rx_tag_rcvd,
-- rx_ctrl
len_cntr_val_o => int_len_cntr_val,
-- error
type_fmt_err_o => rx_type_fmt_err,
-- rx_sig_manage
sop_q_i => int_sop_q
);
c_fifo_comp : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "ON")
port map (
aclr => rst,
data => int_rx_fifo_data,
rdclk => wb_clk,
rdreq => rx_fifo_c_rd_enable,
wrclk => clk,
wrreq => int_c_wr_enable,
q => rx_fifo_c_out,
rdempty => rx_fifo_c_empty,
wrfull => int_c_wr_full,
wrusedw => int_rx_wrusedw_c);
wr_fifo_comp : generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
g_data_width => 64,
g_data_widthu => RX_LPM_WIDTHU,
g_q_width => 32,
g_q_widthu => RX_LPM_WIDTHU+1,
g_showahead => "OFF")
port map (
aclr => rst,
data => int_rx_fifo_data,
rdclk => wb_clk,
rdreq => rx_fifo_wr_rd_enable,
wrclk => clk,
wrreq => int_wr_wr_enable,
q => rx_fifo_wr_out,
rdempty => rx_fifo_wr_empty,
wrfull => int_wr_wr_full,
wrusedw => int_rx_wrusedw_wr);
-------------------------
-- manage debug signals
-------------------------
rx_debug_out <= (others => '0');
-------------------------------------------------------------------------------
end architecture rx_module_arch;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.std_logic_arith.all;
package variable_Caos is
constant numBit : integer :=32;
constant Val_init: real:= 0.5;
constant UNO: real:= 1.0;
constant Param: real:= 1.8;
--constant Param: real:= 0.125;
constant Nint: integer := 2;
constant scalamento:integer := numBit-Nint;
function convtosigned (val : real) return std_logic_vector ;
function mult(k : signed;
x : signed
) return integer;
end variable_Caos;
package body variable_Caos is
function convtosigned (val : real) return std_logic_vector is
variable temp : integer;
variable uscita : std_logic_vector(numBit-1 downto 0) := (others=>'0');
begin
temp:=integer(val * real(2**(scalamento)));
if temp = 0 then
for i in 0 to numBit-1 loop
uscita(i) := '0';
end loop;
else
for i in 0 to (scalamento) loop
if( (temp -(2**((scalamento)- i))) > 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
elsif( (temp -(2**((scalamento)- i))) = 0 )then
temp := temp -(2**((scalamento)- i));
uscita((scalamento)- i) := '1' ;
else
uscita((scalamento)- i) := '0' ;
end if;
end loop;
end if;
return uscita;
end function;
function mult(k : signed;
x : signed
) return integer is
variable res: integer;
variable res1: integer;
begin
res := ((2**(numBit-2))/(2**(numBit/2)))* (conv_integer(x)/(2**(numBit/2)));
res1 := (2 * (2**(numBit - Nint - 3)))/( (2**(numBit/2)) ) * (conv_integer(x)/(2**(numBit/2)));
res :=2*res-res1/2;
res := (2**Nint) * res;
return res;
end function;
end variable_Caos;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 15:49:39 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_processing_system7_0_0_stub.vhdl
-- Design : gcd_block_design_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity gen_OR_bit is
generic
(
width : integer := 4
);
port
(
input : std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end gen_OR_bit;
architecture Behavior of gen_OR_bit is
begin
P0 : process (input)
variable result : std_logic;
begin
result := '0';
L1 : for n in width - 1 downto 0 loop
if input(n) = '1' then
result := '1';
exit L1;
end if;
end loop L1;
output <= result;
end process P0;
end Behavior; |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dotop is
end bench_dotop;
--=----------------------------------------------------------------------------
architecture archi_bench_dotop of bench_dotop is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_dotop
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "sigl1.mif")
-- init_file => "Ones.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "sigl1.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "000000", "000110" after 131 ns, "000100" after 141 ns, "000010" after 151 ns, "000111" after 161 ns, "001000" after 171 ns,
-- "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000100" after 8741 ns, "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000001" after 11321 ns,
"000010" after 11341 ns, "000100" after 11351 ns, "000111" after 11361 ns, "001000" after 11371 ns,
"000100" after 19861 ns, "000010" after 19871 ns, "000111" after 19881 ns, "001000" after 19891 ns,
"000010" after 22341 ns, "000100" after 22351 ns, "000111" after 22361 ns, "001000" after 22371 ns,
"000100" after 30861 ns, "000010" after 30871 ns, "000111" after 30881 ns, "001000" after 30891 ns;
--s_data_in_cmdreg <= x"0000", x"004F" after 141 ns, x"0040" after 151 ns, x"02D7" after 161 ns, x"0002" after 171 ns, -- dotop, muladd m0,1>m0
s_data_in_cmdreg <= x"0000", x"0040" after 131 ns, x"004F" after 141 ns, x"0040" after 151 ns, x"02E7" after 161 ns, x"0002" after 171 ns, -- dotop, mul m0,1>m0
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
x"0072" after 8741 ns, x"0080" after 8751 ns, x"0026" after 8761 ns, x"0002" after 8771 ns, -- sigshift bitrev
x"0080" after 11321 ns,
x"0040" after 11341 ns, x"000F" after 11351 ns, x"000C" after 11361 ns, x"0002" after 11371 ns, -- fft
x"0040" after 19861 ns, x"0040" after 19871 ns, x"000D" after 19881 ns, x"0002" after 19891 ns, -- dotcmul
x"0040" after 22341 ns, x"000A" after 22351 ns, x"003C" after 22361 ns, x"0002" after 22371 ns, -- ifft bitrev
x"0040" after 30861 ns, x"0040" after 30871 ns, x"002D" after 30881 ns, x"0002" after 30891 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 131 ns, '0' after 181 ns,
'1' after 8741 ns, '0' after 8781 ns,
'1' after 11321 ns, '0' after 11331 ns,
'1' after 11341 ns, '0' after 11381 ns,
'1' after 19861 ns, '0' after 19901 ns,
'1' after 22341 ns, '0' after 22381 ns,
'1' after 30861 ns, '0' after 30901 ns;
end archi_bench_dotop;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=5000ns
-->SIMSAVFILE=dotop.sav
-------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity bench_dotop is
end bench_dotop;
--=----------------------------------------------------------------------------
architecture archi_bench_dotop of bench_dotop is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dspunit
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
data_in_m0 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m0 : out std_logic_vector((sig_width - 1) downto 0);
addr_r_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
addr_w_m0 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m0 : out std_logic;
c_en_m0 : out std_logic;
data_in_m1 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m1 : out std_logic_vector((sig_width - 1) downto 0);
addr_m1 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m1 : out std_logic;
c_en_m1 : out std_logic;
data_in_m2 : in std_logic_vector((sig_width - 1) downto 0);
data_out_m2 : out std_logic_vector((sig_width - 1) downto 0);
addr_m2 : out std_logic_vector((cmdreg_width - 1) downto 0);
wr_en_m2 : out std_logic;
c_en_m2 : out std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
debug : out std_logic_vector(15 downto 0);
irq : out std_logic;
op_done : out std_logic
);
end component;
component gen_memoryf
generic (
addr_width : natural;
data_width : natural;
init_file : string
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component gen_memory
generic (
addr_width : natural;
data_width : natural
);
port (
address_a : in std_logic_vector((addr_width - 1) downto 0);
address_b : in std_logic_vector((addr_width - 1) downto 0);
clock_a : in std_logic;
clock_b : in std_logic;
data_a : in std_logic_vector((data_width - 1) downto 0);
data_b : in std_logic_vector((data_width - 1) downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
q_a : out std_logic_vector((data_width - 1) downto 0);
q_b : out std_logic_vector((data_width - 1) downto 0)
);
end component;
component clock_gen
generic (
tpw : time;
tps : time
);
port (
clk : out std_logic;
reset : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_clk : std_logic;
signal s_reset : std_logic;
signal s_data_in_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m0 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_r_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_addr_w_m0 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m0 : std_logic;
signal s_c_en_m0 : std_logic;
signal s_data_in_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m1 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m1 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m1 : std_logic;
signal s_c_en_m1 : std_logic;
signal s_data_in_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_data_out_m2 : std_logic_vector((sig_width - 1) downto 0);
signal s_addr_m2 : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_wr_en_m2 : std_logic;
signal s_c_en_m2 : std_logic;
signal s_addr_cmdreg : std_logic_vector((cmdreg_addr_width - 1) downto 0);
signal s_data_in_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_wr_en_cmdreg : std_logic;
signal s_data_out_cmdreg : std_logic_vector((cmdreg_data_width - 1) downto 0);
signal s_op_done : std_logic;
signal s_debug_dsp : std_logic_vector(15 downto 0);
signal s_irq : std_logic;
begin -- archs_bench_dotop
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dspunit_1 : dspunit
port map (
clk => s_clk,
clk_cpu => s_clk,
reset => s_reset,
data_in_m0 => s_data_in_m0,
data_out_m0 => s_data_out_m0,
addr_r_m0 => s_addr_r_m0,
addr_w_m0 => s_addr_w_m0,
wr_en_m0 => s_wr_en_m0,
c_en_m0 => s_c_en_m0,
data_in_m1 => s_data_in_m1,
data_out_m1 => s_data_out_m1,
addr_m1 => s_addr_m1,
wr_en_m1 => s_wr_en_m1,
c_en_m1 => s_c_en_m1,
data_in_m2 => s_data_in_m2,
data_out_m2 => s_data_out_m2,
addr_m2 => s_addr_m2,
wr_en_m2 => s_wr_en_m2,
c_en_m2 => s_c_en_m2,
addr_cmdreg => s_addr_cmdreg,
data_in_cmdreg => s_data_in_cmdreg,
wr_en_cmdreg => s_wr_en_cmdreg,
data_out_cmdreg => s_data_out_cmdreg,
debug => s_debug_dsp,
irq => s_irq,
op_done => s_op_done);
gen_memory_1 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "sigl1.mif")
-- init_file => "Ones.mif")
port map (
address_a => s_addr_r_m0,
address_b => s_addr_w_m0,
clock_a => s_clk,
clock_b => s_clk,
data_a => (others => '0'),
data_b => s_data_out_m0,
wren_a => '0',
wren_b => s_wr_en_m0,
q_a => s_data_in_m0,
q_b => open);
gen_memory_2 : gen_memoryf
generic map (
addr_width => 16,
data_width => 16,
init_file => "sigl1.mif")
port map (
address_a => s_addr_m1,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m1,
data_b => (others => '0'),
wren_a => s_wr_en_m1,
wren_b => '0',
q_a => s_data_in_m1,
q_b => open);
gen_memory_3 : gen_memory
generic map (
addr_width => 16,
data_width => 16)
port map (
address_a => s_addr_m2,
address_b => (others => '0'),
clock_a => s_clk,
clock_b => s_clk,
data_a => s_data_out_m2,
data_b => (others => '0'),
wren_a => s_wr_en_m2,
wren_b => '0',
q_a => s_data_in_m2,
q_b => open);
clock_gen_1 : clock_gen
generic map (
tpw => 5 ns,
tps => 0 ns)
port map (
clk => s_clk,
reset => s_reset);
--=---------------------------------------------------------------------------
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
s_addr_cmdreg <= "000000", "000110" after 131 ns, "000100" after 141 ns, "000010" after 151 ns, "000111" after 161 ns, "001000" after 171 ns,
-- "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000100" after 8741 ns, "000010" after 8751 ns, "000111" after 8761 ns, "001000" after 8771 ns,
"000001" after 11321 ns,
"000010" after 11341 ns, "000100" after 11351 ns, "000111" after 11361 ns, "001000" after 11371 ns,
"000100" after 19861 ns, "000010" after 19871 ns, "000111" after 19881 ns, "001000" after 19891 ns,
"000010" after 22341 ns, "000100" after 22351 ns, "000111" after 22361 ns, "001000" after 22371 ns,
"000100" after 30861 ns, "000010" after 30871 ns, "000111" after 30881 ns, "001000" after 30891 ns;
--s_data_in_cmdreg <= x"0000", x"004F" after 141 ns, x"0040" after 151 ns, x"02D7" after 161 ns, x"0002" after 171 ns, -- dotop, muladd m0,1>m0
s_data_in_cmdreg <= x"0000", x"0040" after 131 ns, x"004F" after 141 ns, x"0040" after 151 ns, x"02E7" after 161 ns, x"0002" after 171 ns, -- dotop, mul m0,1>m0
-- x"003F" after 8751 ns, x"002D" after 8761 ns, x"0002" after 8771 ns, -- dotcmul bitrev
x"0072" after 8741 ns, x"0080" after 8751 ns, x"0026" after 8761 ns, x"0002" after 8771 ns, -- sigshift bitrev
x"0080" after 11321 ns,
x"0040" after 11341 ns, x"000F" after 11351 ns, x"000C" after 11361 ns, x"0002" after 11371 ns, -- fft
x"0040" after 19861 ns, x"0040" after 19871 ns, x"000D" after 19881 ns, x"0002" after 19891 ns, -- dotcmul
x"0040" after 22341 ns, x"000A" after 22351 ns, x"003C" after 22361 ns, x"0002" after 22371 ns, -- ifft bitrev
x"0040" after 30861 ns, x"0040" after 30871 ns, x"002D" after 30881 ns, x"0002" after 30891 ns; -- dotcmul bitrev
s_wr_en_cmdreg <= '0', '1' after 131 ns, '0' after 181 ns,
'1' after 8741 ns, '0' after 8781 ns,
'1' after 11321 ns, '0' after 11331 ns,
'1' after 11341 ns, '0' after 11381 ns,
'1' after 19861 ns, '0' after 19901 ns,
'1' after 22341 ns, '0' after 22381 ns,
'1' after 30861 ns, '0' after 30901 ns;
end archi_bench_dotop;
-------------------------------------------------------------------------------
-- Simulation parameters
-->SIMSTOPTIME=5000ns
-->SIMSAVFILE=dotop.sav
-------------------------------------------------------------------------------
|
architecture RTL of FIFO is
begin
process
begin
loop
a <= b;
end loop;
c <= d;
-- Violations below
loop
a <= b;
end loop;
c <= d;
end process;
end;
|
entity sub is
port (
i : in integer;
o : out integer );
end entity;
architecture test of sub is
procedure function_that_dies_with_this(x : in integer; y : out integer) is
procedure read_val(val: out integer) is
begin
val := x;
end procedure;
begin
read_val(y); -- Would crash during cgen here
end procedure;
begin
process (i) is
variable tmp : integer;
begin
function_that_dies_with_this(i, tmp);
o <= tmp;
end process;
end architecture;
-------------------------------------------------------------------------------
entity issue429 is
end entity;
architecture test of issue429 is
signal i1, i2, i3, o : integer;
begin
a: entity work.sub port map (i1, i2);
b: entity work.sub port map (i2, i3);
c: entity work.sub port map (i3, o);
p1: process is
begin
i1 <= 1;
wait for 1 ns;
assert o = 1;
wait;
end process;
end architecture;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY dctslowout IS
PORT(
clk : IN std_logic ;
doutput : IN std_logic_vector (15 DOWNTO 0) ;
read : IN std_logic ;
reset : IN std_logic ;
dout : OUT std_logic ;
start : OUT std_logic
);
-- Declarations
END dctslowout ;
--
--
ARCHITECTURE beh3 OF dctslowout IS
signal inreg : std_logic_vector(15 downto 0);
signal start_int : std_logic;
BEGIN
process(reset,clk)
variable done : std_logic;
begin
if rising_edge(clk) then
if reset = '1' then
inreg <= "0000000000000000";
start_int <= '0';
start <= '0';
done := '0';
else
start <= start_int;
if read = '1' then
if done = '0' then
done := '1';
start_int <= '1';
else
start_int <= '0';
end if;
else
done := '0';
end if;
if start_int = '0' then
inreg <= '0'&inreg(15 downto 1);
else
inreg <= doutput;
end if;
end if;
end if;
end process;
dout <= inreg(0);
END beh3;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity audio_select is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
select_left : out std_logic_vector(3 downto 0);
select_right : out std_logic_vector(3 downto 0) );
end audio_select;
architecture gideon of audio_select is
signal left_select : std_logic_vector(3 downto 0);
signal right_select : std_logic_vector(3 downto 0);
begin
select_left <= left_select;
select_right <= right_select;
process(clock)
begin
if rising_edge(clock) then
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
left_select <= req.data(3 downto 0);
when X"1" =>
right_select <= req.data(3 downto 0);
when others =>
null;
end case;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(3 downto 0) <= left_select;
when X"1" =>
resp.data(3 downto 0) <= right_select;
when others =>
null;
end case;
end if;
if reset='1' then
left_select <= "0000";
right_select <= "0000";
end if;
end if;
end process;
end gideon;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:39 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_quad_spi_flash_0/system_axi_quad_spi_flash_0_stub.vhdl
-- Design : system_axi_quad_spi_flash_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_quad_spi_flash_0 is
Port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_i : in STD_LOGIC;
io2_o : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_i : in STD_LOGIC;
io3_o : out STD_LOGIC;
io3_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end system_axi_quad_spi_flash_0;
architecture stub of system_axi_quad_spi_flash_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[6:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[6:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,io2_i,io2_o,io2_t,io3_i,io3_o,io3_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2016.4";
begin
end;
|
entity call9 is
end;
use std.textio.all;
architecture behav of call9 is
procedure check_acc (l1, l2 : inout line) is
begin
assert l1 = null;
assert l2 = null;
l1 := new string'("Hello world");
assert l1 /= null;
assert l2 = null report "incorrect aliasing";
l2 := new string'("second");
assert l2 /= null;
assert l2 /= l1 report "incorrect aliasing";
end check_acc;
begin
process
variable l : line;
begin
check_acc (l, l);
report "SUCCESS" severity note;
wait;
end process;
end behav;
|
entity call9 is
end;
use std.textio.all;
architecture behav of call9 is
procedure check_acc (l1, l2 : inout line) is
begin
assert l1 = null;
assert l2 = null;
l1 := new string'("Hello world");
assert l1 /= null;
assert l2 = null report "incorrect aliasing";
l2 := new string'("second");
assert l2 /= null;
assert l2 /= l1 report "incorrect aliasing";
end check_acc;
begin
process
variable l : line;
begin
check_acc (l, l);
report "SUCCESS" severity note;
wait;
end process;
end behav;
|
-- NEED RESULT: ENT00005: Formal generic clause absent passed
-- NEED RESULT: ENT00005_1: Formal generic clause present passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00005
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00005(ARCH00005)
-- ENT00005_1(ARCH00005_1)
-- ENT00005_Test_Bench(ARCH00005_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00005 is
end ENT00005 ;
architecture ARCH00005 of ENT00005 is
begin
process
begin
test_report ( "ENT00005" ,
"Formal generic clause absent" ,
true ) ;
wait ;
end process ;
end ARCH00005 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00005_1 is
generic ( dummy : boolean := True ) ;
end ENT00005_1 ;
architecture ARCH00005_1 of ENT00005_1 is
begin
process
begin
test_report ( "ENT00005_1" ,
"Formal generic clause present" ,
dummy ) ;
wait ;
end process ;
end ARCH00005_1 ;
entity ENT00005_Test_Bench is
end ENT00005_Test_Bench ;
architecture ARCH00005_Test_Bench of ENT00005_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00005 ( ARCH00005 ) ;
for CIS2 : UUT use entity WORK.ENT00005_1 ( ARCH00005_1 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
end block L1 ;
end ARCH00005_Test_Bench ;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
iLOC/zM7Joxw/7u1/3kvLPf/gE0DI9AX05I+qEOauE/7yu3hZQ/vW/F3DMobAlAfRXjv3r131UI4
xp3jO78wPg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
KVI7kykeCSUX5fBocqQpSGyifzzNp8Wh49gB3SY5aCkcF70ujPDG/9hKzVEDulBUoOtbOqYXhoJ6
cDn5xn6BYki3kuRcj1mZItS4T8QaSDgMTEM9Aijj4k0hN6ZLETGBDBJKg2OZZ79WIQrCLm+Yp+jA
b9eXqd54dvp4eMuMoF8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qYUG6c35gMmWOmJ0+Jjb5OdGb2PCL0JkqR78MmUYY5UoyvL3BwaxAiIKYYVkJX7CEXshqD+eBNI0
9W+MVH7wRTJDBCk6PMcmsu3NeQu2XZMDibSGlfuAGYgFFKMmAwU1iWlGD7S5ZAszDxIG7Hsub1G3
cGB12cyCQuhcHZlpZtY3OJmIyOR7T+UzJNJFbx6M7i6pUZFQbBnvjcLm+HX6NInXcmNM9wltRgWc
QA08ofalBcb/79RDwtVfdkQDfNV2q+E28Pw28JJ8iQGzaRuMeSskaCSFhD8B7An5FogQZOgaxqEO
j5vMiNlwpZqnSG9tOie5RYD0VydWTxnYXBO0Gw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A+EeNDHsLpmHCom+HasfIuBBRE0S3bFCigDt49+x3CEwcjYWjxIx0qCtRtVq7CI9wSm/Gin+WWfG
91dfuXZp+eucmiP6CHPUMHYExivhUTYpZBeDxxcPgEBLzUE6gaaPNLKU7gnB+L6RM/V+crK209sI
xnRl4bgcMqLIseSvXtU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
AzEbyYz2+7QSiim7WpYfcDPoQjw6mNgDWG2fArz05h3/f9vy7U+kvSbnU76BD0mI/hcdrW+NdM0u
WayqP6k9VHNoaeVq03RU2UxLJGfLG1pGdUvSG5M3AoP6lKe0tGtU/8OU2ukN7RIIxnFPT5zhqDZ1
bz7Mq+GC7cYzUWbYi8FRC96SdwHeUzfAf5SEfMfH+YvrY9MFrF/8eVGfIgzjjI3MYGgC8EkgyuWQ
D6m2kYJukFy0EcVvneNXMtGT5lTBe7PkgvpUw8UjK2OEv+w607nnaO5HDvgeARyB5d1AhXWLn1mj
1Kn9vGxKm9guwUGKwthrvkUy4jU1ZgFIlTeLrg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19104)
`protect data_block
U2sqQ5Qkdfcwvu9O2/bTBoNh51zIYpjS8j7C3+fMQ7h0wN0JOPdBtyrCfdE2QfLKv85tSc1BegVo
KBVgvvg903b+N8RMX6uz+ksO1DPK0Bc/G7dtSY1RFMIuhlsZ0eGDXGOOVLLlLPpqcbIR732iHkNc
ei+L8oALEVwIpf7+Qyuk6wz0ALJ0rUD+vqp5hfVGyYRf7zEnD4pweTWN/5IJ5K8cUlnddKFLIupP
mqyWRXQjL2LI0oXpyGrtiKCxgC/iwu6a7l//KqBavg9ZdpB3KYc7ss1Z6GnDCoDwwnAeOZAJbQpL
TM2Ygooepikxl3TS+SX8B6yHp/EmeLN4AbbYyuj4cEKbIDpjSNgq3cNueoypY28/Cw91Dr+g0sk0
m5COCkkhSaXJoIkDP8M3ien6i5uCbQ+edkb72Xpo/uw9LwWe2WgIOHHl2q42fANP4pBi8kI5GUzY
Ow+VZbdwHDCcu/+EGN/wnD4E2bzMF3YvipqRZ4+dlNd1CqAV4zaz9jngH4lQi9DgsER7IrhdISKI
+BkphY7K4mDDXoFmwUCalW0/mK14Krq6D6OAgPOupHgQM9gWSCK4NbCl/BHbMYhETWBXKSwhEevf
0ouMElCCDzTQPABImhtXqp0+Ln+EUi5+ZiyhaScNOArUaRSg2A70bOnkwZkpKWuIJ6ekYvdCLEFx
WtpqhxsBj5L+w6eDX3cQZNoaTePPN/dvunXBNYRioVdg121U9CfggaZu5m03/zO9Nr4S1mRfPH7J
MQ9omi6giypyGXiNukrIpYo5tO1sezgM7Blafx+9qKOrTcQaeUS8KpQXXlwupNB+m7Ons2HmzO+F
zv0fetMTignnAw0uvTpX1odtI17TGBLg2kmb3vbEZKMXibkQRWWKGwXaLoVaOZuRpMY+PDj1VKUO
VVmboN8Jq+rm9yFAaPITFpCgz8tCBrT1iufL/yHSqCau3cdHHzNB4gCY57dHeIxBaGHBVz8KITj4
DLp2qbT1iRzRPqWD+2cqojGL35hsk+McJh/8WAshX2O0ECwWRrQbsXSI+xjLn4krEqWEA0pIfZWB
mrZ+lw5/INBGw7JPEozScLYfUvV4NKT769e44SZ6N1ho1aHDI05k15/sozEOhZLYNAnliyrQBkUf
ir0deJGlPH2XyOITsVckllAOzwUdAQPqceyTMjL1OsYwe6uMe02izKLensA22wrwVKH9n2aclzu3
Kdog5Xju0HxfHqeWWTFsD0bJs5TFYI5lKKmnNMscBKhOiKt7UpFTIX3wUZWHOUQcMPBudHswP1Rz
XD9dXP4vUYviG8STMAt72hjJgHPqkM7rN2Mt8Lj+6pXTkLWVNMC7IcdNmSl9GFwBnTvv/7sjJKnD
QOvKabzUW/boM5vdcPU8iOXd5wev5EiEv19KrozoWB0H4gEK2nlym78UJ7yWvXZvV4CBpupp+ujY
V78ViKjXIvIaFLvnEhQtgb/4RiGerkSqnveTYPLk7He+2H3Sq83zT6lIO0L0Nc21I2Uknrg/gGsN
WdDFnsFWheAVTj20SWOBFtd2Gl8Dp/JVlpCX/3jvSKgF5AGAHUhS0gJZGLZZiymY7Q1AHbZr63sj
QqWvXavs0xlIJAjDlCEE3iJ7sE+C0F96O1ek9EgE9Y4V+UbuSqnx2AIYHVy/nD6Qd7k+JsFoxhhq
pXxJRybnHDrVks36jKM9SCAgPX2B7nGfXnR2UuCU9f5dBeCxzpyLTO/Cv/Iwcg/C8Z6E0X164Usr
T0a8As85XgTJ7SvhXSKyzoX+6ASCtmjgUdR+MmnN2LaDeFQBzdjKlq42ulUAN7hLBEoqFzYAnJBA
7AkonwxuWY6GK31wy/tatnbwcaB9Wg3MFlDfRQakcGMRB5+4UqudfEwzHFW7zY9sBxDQOVi3cVxY
lMj0stJmRZVg/jh47vWLkb6nPfGL01tShHouP/JmBUHO0ib5JVGGsxPI/w5ZkS012uA52WWe4AqR
aNhXBT/Wj7xly1nvj0d1USAfNDiHDeISRI61MXMw5vbg85KGPdwmz5E+iJGZydtlaPn4NGX3klxG
NZTqj/PHYizcH5jxsyeLEPUwnlPHvVFAgXl08dpCagKsPCRGGtLUNhvsc9eqBLvOouwpZL2+zEYT
cgA4BRcznT2Jm//EZGihHc/TS6ZZjihHBNH+ZGbu+wWcTgtrodj4qEf6TyCoR0jvgMX9RmQn3if4
Q/NyETOSjRzVrQWVuPmJnKs9etxfSlESgwxhJ8Ba6sAag2nWQw6QCyJ8iSe2Uau5pYhtJjwAxCQ2
zEVnw1i66UUOpKAY4w4kXg1hvi6hdcEfN2NcH1tm2oZMB0BZVRlAEMEw2WLQR5/tTkOWMdC9GzNg
vX3NkkZAiq7peuNRFkq9+K3TvrZI0tEkcKtpDYbyexU3cC0WzWj18ES5qfohi+0pNXS9Zq15VPmP
snqeR0mD8usuuj0+03rfnxzki8CfJFRhMT5zAhpHjoDhZ+gPp030Yet+gAqRvjX08iGKNOXUy/So
0kuzLpOY2V4idoOcmlcrwkX7z8vj3NFOQrr8taKkA9yjvFJ8qWaBK2+8H40YZ6pNNgfytS9uadvK
iiBNTmpWkWYfbTJGw+gniuLQSXyzrm8WkbGc/tDr9gygDQvCZT3fRlSdQMCwqo69sIYM6gkSBZSP
cah3ClpcUoUkss0hrwiKKYUpzT1PuicD2lVIDOlAV+Nt7aVw5mElDXwwV8Vb/hpRVx8EqbbpeIW0
kUHdZc3HgPsfbNg1N71zRZgHYTEJvidEWkh+PZ469qRm0XbO/G5YzUxc3FA0cnucG4vT5n1PiKpd
15MHzsd2exRokmMpLb0k3q8xP/Xr9mokDnFT1hu8eNNL18QrPNIWrntez7ZBJLcX6MmgXSLgBjEy
zj8rbDLpVPIDLb7zFB8sgbJtjUa+9bWFQY3AIEouuU0VY6ByqgG/EpzEbfE0riAFKnwNLdgZt7yh
VU5UhDItVDgqacV/QCMriSLeQj4ScWRRf3GUfQb9m3rg2X52W+uV9kKofy9Ecwbvrf56qMRxf5So
BS4G3WMWB3FW2dvXZc3vdU23MzKP3gW513Bwr9QkYZt9sbQMCVtCLt2DkugERw9mnh0814ew5KB3
Idql4GPyW+/LvSky5sdZhXgmFEv7y7E4k0DCMBS6L3qxEysEl/SBpW3bsTqw5QNuauTqfeU07NeO
iwk2L1xfiBv2NY5fD1cGw1jkdH2E99KKjNSvW7em4LARB3Q5J/uoXDOM4zuYAHBzlbgNDJHkNjF3
BpKXxO3IMFUq/39LcJnIa4ZTI5ScvfKtn8QucLyDcB4QDXXGLg9uArcgLSkX2H8csW3AByOe2DKV
ORIwFbDEf/2cqKkPjXWUgllCmGRnKYJgmu/5oH3zBFFG91P3MTHV54zZqiKjvcUfuXisgVim32fJ
3QMmlHHDE8UhxLlI7CSl3tZWpMwVNvHipqSXfHfyrt7YGGE72Lb3ncTeSZfxOsd00+1JPqEsYIxq
uUFnRxMTIpBybedLpvUTth+f9qv5Y7p5i8FS2BDDzqAx+Jjg/vj56kz1Z6um2sjM07zZqG5XVxUm
qZhIhpo8iqGbgYJ1qz5yALxVSKNwegz0Z9HV5486yvXuIsXVUJhakMemKN7YSm891UcO3Z4aVxlf
PXN6ug5JQJJvQIhuhZjaYWEyN8zWSZHWR9+LkbX+ZP88dA2+hAK88T03OEtNbUxTdnsbTNSA4gRA
LClvGXqNaIzTKrMWkY5Q1GG2FRL5ZDGtqHNjgmeIApCXbvJaJPmOhYSULr5hWVTA8sPHDVAyZQ44
KHlf/kYd2vH4CCndKgZ8NPmH5MOA+X9wV8cG1yVULrkysoVc4FMw9PYNTsKJx1YQQhErw6hgYTgb
oJNm7dyNCn5OB3i/s5DgxFEN85C0gSjjPe7YK9s8wgM8EFIjjdjlrgqFeWEhWsUhPiVsMisRmXGt
Zww/aqeNXbmuKPg9rQzf2dxYb1u6BvZAZwGEj/QXCpouYHA/+sqV9nrLS6P1O7vzl1ykZjvciCRW
piT190KlFkTmrQPA8XyM6YmLLGQ77OL//RfHCKh1MqBZ+XIT7E7dgezchbdggf3dqhCUn865meWG
4smMmUSw2zPjh2a1dQtMj/TJshXb7GWVPLWEXkqyIbeajDTa9PxoBrk+xJl2XSOaafzLG2/AyYTX
daD7xWK9iRYcrf5qb/nEnBr/jzPwagIL9/YIAmhFBHrU3c+O3wA0DPGbe5LNuve9RFYsznRdRJ67
TdeU1C1zDEB8UwjEISHF5A3sunKHdHAvd/+4WmWS+eZ6begy/Gmkmh3ySlPvHDlliokxb5IZb0RZ
GDRSFBw9IZYmfaq1e6VpE1kzqsyzVhD1c+X4OUp63FT5sZEowoMG+b6JgTlJCdVjIyaIBVP+w4ja
lR78lcf0mjRHSuMS+/78XsViz/S+dYOGzS6EBdpaUoGKzPFUBMiL+fKfZ9/E7OQvFDWWo0q79pPR
89S8YN6Cirw7+Q5e0VehaiLY7Gz1vCtFi5bwjdRarfIwYZ7lxLE18lBxvITbvJ4MRVprrHMNhWKB
H58XpB4xYsIk9OFG/q08w4ZyiYKgfH2D+Byjt6B/PnmSb/p4NX+mrFsXyhDkIEj+Z7sGhkG90myz
MmJiURPA4XhVWdSNpF/YqCr0Ap0qiD1Y2TwUb3I8DRaa8kw4JK162FvcZUykoIMOlNVrNsYNilGN
uFrQJJ0faDBuQ4NYjFcpfsGJKGItzVo2f9Ypgto/S2QKBpoFchVV06iW0HLpfHcTb1RSrS830Ge4
kPoRxqCaUA4c1wxz+FILYM/qzVoaqfEEsj2dggXIgWtXPfXkXtMudaKnGNK2jT2ffBFRkKQ+L4kP
zP8Cn0GmGJr1wROF38GUMbdYr8rAbzzG0Lx1d6wltxUD34fZIV1nsR25jdeVG452aH6RhbS8KZZz
HGthRYwKBnHxwhAel9K24H1jIvxT47UOwm1qNczd5fu1sef8kvTY5CRlsa+wAPrxZdbYGW/5YFBu
P6njcMwx8qqfbqr0Ieox3+0VxVXwVivS5ILZhLlyUnimvenItNJl8o17+0L6oh473HKBcnb9ixSW
EseEXfFF1Pj/tB4nNip5oRorcM09jHWq9wUzL/5Ckz1NgcARMmvPCK+DWpvpl1kPwQkjyOKc3weO
WotioMQadHnnUQres32HHBi2Cf+O+yyZWurVzZkFrbUD+zGVHVd1vXUvCNpn+JfzXW3nu+/eU5ls
iYJKPwBOjc+kW5AryeaXTdo71wXYuaEu5QnNsy9+bJfzj9wUyIfQ+D7qIbtICO68jqh0rXyE4Yyf
cxYRpRkIdxRC/c0PRUTj5htOAC8AP0F7GHDpGRXNNbc8hPVkSF6NzqDJc92r+o1L/XIFC0cgrAOb
FDobTZTOGk6a//0DkvqV0pxKjVA6n8yM7yuADO9MWgOEcJmJ08vPNwn30f2gzyt0GAd4GcT2lLLc
VUf4MFW4LqpYe7W46sGFSTqBkqB9crzIZAhlGc+WzZ9bYzSPg2ekS+qb04As7o6Rx98FtP5SOWsO
IcE4xGqZnvNbfQyQ8H4Wp5/IETwbdaAX6ymY2Ad4nB6Ap6SHvMHjgs87bAvDx7vziNPOrFmyMr1c
hn/x08yPI3Uq3KSq/u8WgDAABBcUB0l5HpcjnANctnqsesnBPzNOA2onI+Yl9hzh7TOvuMneYiMx
wXlk11q/3kehxlbqvsv5wjn0Es+wCAtNpM+DkthYuNvpGkY7DS1z3+8KhxH923wrJt2UvycyQVBd
VYGsNfoiHmdqjPCDpfuGywEVa9Am3fLN4DJR7tMbVChg1Inzo3meUhMA9QrYPbTrMO8614hVAwRW
5DqEqYSXXBkGEdgaOP9vqdA1Xan5VR6UuXvWdXk2lSPs4aplZyjn4M6swkdNe7SotNjD0aiqKaSV
ckOTH+r16DFVGPovX/Xkk4CFBxXX5J6Wp4noWMHcXA1L9mExBp9eKz1RtQbnr4pdcgG8dlgz+HAd
vKHQr1ZplfHJyTJpxge5PUCyMiDNHT1IE6jNxX6FexO0Qe0I1FvyDRNiMFiohUglhlagrK7iOfZT
QqsTR7cG5trwC5GwlIjHpK44zC2m+2/6niHegQNVCKYJj56jaEDiONRj0c74jyOaV30b2e1sYbh0
tKSIPaQaAvf5HJGoDVE9mMW8vHDSdMUylodKDBZkG93o9Ry71KFTNs3fpfxvJM1fV71+556jdIq3
9PFPr9d2KASHco04biATGA68QVFQrrAtul1zTnjyGQl7dOCI6WJCm227O5nJ0+AyAj1zWWU7a7FG
lNl0BbFCl3d4qm3TOejuQcJSoiK5iWhOrQrLfMlLTLoBeeiiVETvEhrn6ZzmJus5lrB6JzrGFg6a
0hJDEKyigFgLccLVaW+R7OFdL19Q45cWagAAfG7uxnDTgM+he1akgruDnQ+Ddeu3fXubS1pZvO9C
jAqEC1tWhuTLpmUx6xN1QQu7EPOyAxKDOCZrl78M3w4dyyZXUgirxODO3qK1ZnlZoF9XMAV4kK9g
aTtwpHTQTDrRdAc5ZqWqc2rb9Ari3d8qSkn7vtqDUK+OQstvyT7grdzRhUQ1gQa1NHtaCrEklgx9
9DRvEN7IIQVPPot9VLN8Trk5S5gSiCr1w0W/LYWS5QQfH0+BYAY+0CrruoOMNrsuwo9kmi7uaUIM
ylWpz5b5+Aw8sbCeWjyvToPGn5z/X/TsblxVIDhZzozJOSxP1KdBBpKI1j99ZOk9yXcYx6rGme9i
6rCtD0qWMXek2nHjFZOGXvttWIe1WPJIbo1eYfwXk6eZHAZ7G8ljBbB5A7SkCuITyzU/CTpi/EgO
lQSxzWlUcvO2tXcAnp8HKYtVDv58hH62Ddp02SUrHjqjo3sUIRnJHvJTa9kZUM2Qg5zjrCK0LdE6
RL53OYsSIN9e36YjoGijt+R+ynGSGaLp14jJ/DnHF1JKC8RALi6y1r3Yht3OtgnoF3XM/ScEt8DJ
09lrFJHf45zHzH3T3HEEicN+XOgxEOc/6kUFpUxQNoCIFlAe63YBkdz9RWF9gI0fVQklPMU27Oq+
JnW1qfDs5NGErcwTR+reqkAC8v14OfhBAaGUydkBVIFhvKWWiDy9yqqtv74dAmBAn9MU0b6Dg0pl
ysUjH1UOn7d+Rx6/vMroNAEobL6T6IkOEuyTxZ2s/DsENZRj5PXUQK/kURRoKfrAHORm4zkR46Od
WDhVawnq+XJhzgsE0ITvnd0vGuo+1yCpAjgdyG63b3a+eLgBBdbbAKhxo0GI4deQa9w8o9+aQSw1
cfCjP3hH2UoJmqjcW4EZm+QheRyjayZEHAxJV3CSZgCSbj9qJgUo6i4E/FyRUwPR7rVC0TLvPbpZ
AI+MoWLIRKWlltidIp7PrK+v0VOcZ3VO//utzJ1I87dIQQ9lhB3ADDb2DrxAoZxFtnomeJ0+RlKd
7nSQ9O5L6oUQ1kB18g9INDJqjhWpFYUySzEHDQk4IVZs6/WKhK5h5/k/FWEpLbkK3fGfvbWNiFl+
rCusdyG7f010/xb29XL7f8eKcrYAGhtQRX6gM6x8XR1yT747n1mpJo4rhNJhOd7Sxmo47KFUvb5M
qgbsqkIaCGjYW4mD7/zBnJ/vlS/OWWS6jldXD4ZIYGn9OUM/1BOEU9oYASHTNMtPfQkE7n4yda2g
IztwvQ7q7xYcl0ZyESe6Sv+wFGIXX5bMAb37D+Kt4fvo+iZS/RjeppLMpYksBn7UMvtPKHiy3VIK
2XcCKWp902qw+BNSdYxe70AwFoIGVdAWw8t7JSdfTQejsdTxZaBjrPROvykAvhSMb70g84HB5Ucu
FfB85LsOCo+7QQqBrMJM+zvPWtxbp22TFFb5MOnwQVZS3ZrlO9YA1jpygBV0rYfnrww1ZGoYDIf+
z3qvKD+twwF5A7X/uHCX0Wvw7TFP+zbUT/TtgJllk57Ub01ECl47kljgt9l2lpcjNLBdYTohzMxD
eAuglFSjzWfpMBcBWcF3LpVol3HISGj8uBYIsk4yYLzlmnlhD7KHb5S2urHgYG0Hz4uIcGd0GT1V
rXnGefrdaFVDAlQw607Yt54zRWKD5yskUc2FkHXj8z9t+nEEGRYEAauWbTS3OXGxNRQ47fkNls3b
85g+97hscqMW1Mvmv+8M5eyFvqRTgJ2QVRDHaw/VoR/ep+sh5rgWkJ2umJGXnPHZPU5dA8JtBiPT
1KmZKzulQQr4a4ID00XXppeYDNWhf2CU2gTqiCtYIxwi6nk/4ogA+IqZsMqdeV2c7cCTNRZgF0hy
vRFR8rlMf6rhHEOnUqCl2yySQNiXyrKMymWCN1VyLA5FRqiVS2c15RjSGOWEU07tEYnvLoD4piwO
+Nw8Fw6YA8TLkxty0Lm0gjGjyLiEBcRQupTLihAvvO4CUG4cL8kB9AsAP/OWjvDU7x7dMm1SKdKO
ZTeHMCkoMLYEzEyzCmZBiE836TolW0g3Qx2KK8y/Nd7gNBCLAZoGDFgtuz6Um+C7ImBITmU8ek+Y
STcenRX48m4DUJ2dHm6DKkDdm7b+P0eGGskPINl0NJe44OPfzFo6CTHHAH3FVAXsP97h6cWqGY0P
u9ghfbiQG4A0KZ4y5I8yenaYdcjDpDpN8oGaVI9pYgK1XbW0ndS4518QBWDw78gSoW+Joudb+8EJ
f7vSvUTuQM+/HxFasNrNx64WWFJSwlSOG1ELplUYAhuvmfOWS8//gEj5HGI22GDl+k8XHJHfU6lY
wP4gmVs+scyjwiVjeB4QcQxO3llQk8NbNkzGx3C7kEvAOD0r1CgXCUtsaLa+AwBLKyRLXOLTgfHd
2pT6JHjdvbYSZuEiIiA4y3rnjlJwExhDTl2nPbOkNsLKheOSCzRzMWxlyECMp9Q3SssOyeO/aK1x
M+v4HhuJNr58VyifyngjJvAG2HLRIRynvxW2d89CTnth/4UxmEAOH7+2vzZ7vrrydII35ELZcivw
EMH9X1ISdEYfZ3gwqWRgcos4qvPwh7PlqbCBwborXS6MO4wzs9Y/YLE7OpBpAjCqRSqtQQdwHyAA
kgTfm8MVHSegTcSda5g7zl5tgWj50efCyplSwLe1geoY8gfx2GMZbf250elPnxVhqt80hiNUwhyj
kJ+GSAezRmi2waeaCDr6JZ4d6k9xIjn6OAXpKYgJE+NBIt/svDNglZFM6/hFuKGnO0oLAXK7iVWv
F74Yh33SCV7BC4I1AK9fs9vZxPo8gvkDFdA4RMvFhzhyYJnwhQTO6/gU+g+so83zvKz1oPcW36cw
azkIs8lH3hDDFmsXZmpCl9qyI9qDPVWMoaT8dxfGukIfuh7ZQ9LtqsH1m+A58Xqvx20/tHHVxIR5
c9Jq1ukVzY7EwRgURJlpbhnbfxGy4XubyqHCRNPV2Jl2mbonHkYrLL0kCaJUFBmy6LTjkjU6c1Wb
TCcHBXxAC69G9QaOnpTCwLPfFzQ/j7+Li8mQPM3N26DGpKAGNl/0snIvlUoQUQdsUcjkkYU0shop
tXGtYGq+0k3LyWTlihNOaQKcv9DAIeFZ3S1rXNDW7Vlnp9HvpliTGOnR4PCzGIrGp7baxqp5Sqdd
laUgvhE4KGJZevmHW2iW5RSThM+k5iab8fKkcXKBPrPtWHfmMcLpecpM00xak8Bl4ZB9T5RiIYUO
YbxaBpbAjojzFHOn5QPTP49EUqvIIZ3YMFSRRN4UYa+ExFh1zZ+08cYtrrWTX2pMvvdJPBRara6m
V+BubeCG/WLWbMZ4mrRGfLd6hDt7R/J/CZvzhwFrm2P3zEgUaHnT3uGu/MkFVldeLiC3nWak7SS9
NVZcHQY/SYe/HYFFIpkZd5nE9UCv76UsZAcdnIwmZoSmliY6MN17dOs/0X1MNrGwxmSzqDN4MSb7
fO39fvcHsTmU3QP42pUE9UGxmZBIy0/8K9OqZFcYP+rY8cZGoH+B16+rihjDMSJ2Zf+5ER345PYB
P1jTHRb3LMlW4I28zU+xC4mzcRL0MYTe2qG9anE1VQyEoAcJei/OgjeHq1/rMMTJYE5kd4k6Xs1L
wFGFTjBych7wLlmRaBwkDd8mI0cu0mDXDqA5BGWFh11lEoMy6PrvgHsexRYG8EX4UOmqF92CccYW
XO4O/LnrJAwpavhTERZn/530cHEgP850YbpkLXw7h3ByBVY0YuZKvc7g/ipaQaXnYvasBbfoI9H3
oXBNHPmxhKKnQle0DPLvELysFcnE+/zBwcKmk87PJ0x1rUBzhwQgBtXXzhY0k6MPNXynV7Xk6QMT
4eY0vWhBKrq1mOC6vFGYrBGOaA27rN1Qurid9oFdahfWljXbjcie4oLdErgIG4MSa/mtnu2N+TJx
v/VynE5a344O/hqspF6+utaWrEgxPQ/PW2/2FA981qdEyjFwXcm93TEZ5BeTXSK56tROFvLglLmR
mJZwOZuVM3yFkm8WK+Qw1WmiC0sbwpbbMWQMvNoEefbM1reFxeCkemEX1xhwMrAefNsTKEnLPgCg
YqV06fKx56Ram6wZOd7mN8h6SmNkJLcGDZ67u4XtvGiJXnHCktWUqevauoMsmbd2bLSJOGB+nRFy
LbqqqdqM8wB/5Pcc3gTiYjypST+g1meZ0jfyHvUWcf98h17herdvmdxOc/ZImrotgsqzvIIa5rC9
7ev6QSHLK3s0xdgjhxApP/jLLFFK0JZ2itTOVMr/w06WmawtMcYh34xlC79VvDrc2oig0Y51vzlm
5f4hIm7rKxCE5CFCeU0jcjDlFVv94uWKoNB8akqFp9yAQA2Yctti7u1CYm2C8V8RUAZ0QweBLy68
h51Iw3P9bBAg07Kz+/+bjLsTJZueCUnTBT/fwc56kUFjQblF7obVhCy0cUCPeVaeb238MmBZqZk2
9nWOr9Bc7VNbJtWcVOLVZhpG7BrQUc+T9bAl6OYKqJRiOcZYaQDSWuJnfSVugvX9/iU8j9yaoMrD
o0YlxwLLe0D9D1Wykg1kcrFY55Ld/gCuB47gkPs8ePyyqreE4hQyn+8xhrrgAjne4QsKxPnpYsT2
uX3PpCKz7lOol7B/veUfWWgG84rsjwiaNa5Mq1MLunRQF4Ed+SD+NW6ziVC1ytAQzWart9QJiH3p
8RdmKvHrEyrXRW9r1vEJV56KbXKqFXbq95DkJMYJPTKDO2SeljWPjjybpkNsOwUUcEJgEytKz98t
VTiznEKLE3sd/MIB6BnDmTF4CCKZxegtQzuQh9jWvCCEplXvk3z1ukTZVgTNKsQO67Kwck734Xo8
r+RDwEIowVpzE6sM2SUV8Z9ulbIMb7LtdAUqibQeDQ6oQn5Cn2YxomfcHvBnG+lyMAcPn2EhcKTi
Jvq2Z9JMi3G5rpHbKUssJfL061pmCH8m4xncC9jmCGspmp7ME9Nd+D/PBwwpiEDV7Nby9FrFFQO/
vIJpEJ56Skql3aon0wWGBK9ToORm8DxMII3do75bY6Vc7fr50LWaf1ekSopa1ofWSxXX+LKVfcJd
MU4yLAjOwLnjYKCLoOzwyzB/rdmhpQX/MtsKK/7PaPNQFKjhg/CedzhM9IZznWkZb3nXhn3NaRwt
XCO6zPxBkuuwywP4dOxu9nRmvmfld0KuUrA2u8CAGCpA55sYyphLvN+wq1r+/36DAYdpnCo7bgfR
l0ygMje6CzymRdOxqJqrQR/mc6V4pW/n0N2MJ8pjuR8uKBrAZGt/T2oK4dHSTeKNdwQa9BRlQ7s1
Uz0VSAwQH6nXOmj2H7eGpMTCiw6JlSz9wFjC7FNpsoUYZtKXPuXMChaycii+6fXM0FR147IFdqOA
g2OQ9v/pBZEdZ0gD86vXCPkSBEcgToJZyg7VwICLpCwYgGzaFm7M2OKNYfWPqjtfOwI49TomtOiS
dxO1b8htFVIACM+Z97d70/uAqvMpy0xkgboumSGFNGBRkWLKtOgwf72ihd/qICMmkR7RAHEOQtY1
3Bmes423D3JaTOtsQuJJqCbUpQI8LtQSQbKVsELkCl+CKRg0kGwjTJwZ/Dezq6C4BDb28DMq5gX1
s5wT6C+DhwhyC1dVvae11ZbQtQTz7IsCEUHezQeDoEtKse8znUYF7RwoQ1BKIDxxUboIJSKKCAlU
7PI2RwRFyNAVB79eHrVGdfGWObL4pBMlHwOvAfIgQAGkv3ity6Mdx6TgILt3XXxi6HhnlXrMG8Zz
uqSx8rk+UhfCHBFOy0OANQPIBt8X1u+ehrEHUhgXl0iTIl+6zfuYJrHRaHZCmdsnEnB4rJWXHxJ7
XP63rQ6Yl15Td1q/TrrFvGuL7u6no677XQUZ7dXP8I+WDqxHbXFD2g9XgfheNOvzooT5lm7tcNzN
R696oI11xbZw8oxzcmqszHltGWQYdkvyqBmXNbBwnAWFGiEWAgnrR5t1GZQguY1djM4P9suTsvrc
HAI10LrAndkcdHhLP/5B+4/OpC2WuLoVwNfglcVfTo2kyJFAcXBtxKDfuNy8yqL4RVjpsZe1hPdU
R1+DD2lNNfuhE29leoicDqE+8sXfAYVTtXwOOMC8ymLrUPD/RRY3nTGIVpONtNP4ITYUchj+GqCx
Mo6ksHpBBqhnpsuTbfoEQyEmKjNC0YXFhqPau/VhXGQ/EELrEQ27KhpvAmF8yTBEeFqqsOR168qt
OjGmg/c6iLVSPJCR6b12Lo1+7ROQEvDl/UcLsYalhNFl0QwSkQpkSpQWzzExbaAiAHmczRXLkS6a
Qgq1QE8t4d+1FFFifz8mpvwrss+812YCVsn3CvWOSnrQOFL/lVHS9I1cbXYvNv0ADKFlePhBz8Qu
6wPD5ZZkS9kcDAgwTdb+cXA5QEQyJP0lIbRSkmX+e0ewpo5HR1C2I6nAjFRo5Og9owie+CconGez
adARJ8WvRpoqy9jOM5XnLu/u7VxAWAbi8QBe2PacoavDTyadzBgSR8YfgevzXy5VZOTFS/pF4tib
mVT8IE/9RBE8esWUt2KeyBa3OuLINw6iqnl6wTnezYGJLprNIAxoBwspmmprm+aFaeuJ4V0RnWlM
TlTBA4O/KxLrCjVFOcuaCTmjMajT57viUZZAVwFkKc32gCNCKNNIfLQ/n6IvZ2GNt1tI8TVoBd63
s/JTl+t2KfdDx7DmTpJiSF4YgQ+r3i/o8SvuIy3b8IFwSdCBg+8xVe2QWY5eTXdg8BbdrGMEmcKA
XCIFr8YULmEJWNCA8j6tu83xPfsym7EQwQmwHK4F5YjZam7VQ+jpZ2RPsxNHWZfR7EDvYsP6+CRs
MILuhQZ54QpU3ZVG+nfDtpJ7g2k+aMCx95Rw9yQIubr1NGjn4h78HacBmA/YrUd59tJFY+rGE4s6
+qyJr2SwTDPOo45yHd5F5Tr4851/LmjAGIgLtCF8aBsd7Sz3IdasIOSs3EMsshd/kVV81DRfF7X2
pSbkXk/xfjr2XU+Mjhsq9ah2E87MhgcAoRZbTDkWe04vqALjMcx1ubxi58fPyl9LZXjo7VAuGCCn
LzMVM9Z1C6q/TtlnoQpLGksgTIXHfJDsV1IY7RVJaJ/BwNOQH/kT/yoXLcyVawPEZEserJ6EkXv/
uSCrf+QRgMQQmKwoBFD13ib153LH7Z3UNXKtgXRmwMNrblRhDZq13nD6zIIeUVOaU0YBWtE+XP4W
yb2UwImAKksyvMf0Nn/HXZgi4wzskGVSubjZtHMPTYfQU8PjT91eV2b1dwLqriKqO9u2WaGInayS
day7tbU8bjSZgJyyj4J1SYFRlUVfPg6qy4lc/WV50msIE0GU/WBSotDen/57COk/RQGbmAiLzGVN
7hG/xQnyCjV3jrlPzsF4UekrQNldFxZasneipES271lE5PWic1ZVxdE8bIOghSvz5WILI/Nqz1sF
a4A7zefxm5+H/2QCE9tyDbQiQwUJ3e/P6vM+Cf3kSCOgYrSxJc/VNWcuNuDeos8eIy/itIv4gL+9
JENnQ1xlSvNQdhvL7siPbHPek2ouDCEiFwUpI28HTQ2rD19ryXNoDBcG9yl9bryhgxv3C18Qm9eT
vOhvFZJdcXMlX50//DbjWVrcKIapuk0mdYj7BG5X3jaXagDifnnaID2muL9Sc5qdmSDtbpLO10Ep
lefhsiQa3OL5MM3t6KLzITvlWO+/EoGQsRF/u+WFKBFpwZUpobPUhkgLducYIXZX6ACVjfQBw6oE
QgV5DAuB56a5/4cFPIgm0+BI5DtgP7s5kGSb9xk5f8Qj4kjxe4cEfqht1hw6lfB5VLHCxTr3tXEP
92A3RC2cODkcr1uydYV+iWV4x/IWmxU3rfbLwxw+gOvbOr0AnU5YEDlc/Z7mOAWj/Qlo5mwiKsJu
lCbwFu33h8Eby3b5X9Tbpt7Vr0pQbWrqigaLwg73ViYh8oDDhxf7i9qwbzFusqJtxqoKNIJ/3uNW
5SDWtv9yZE7vYjMZRtXyjNKhwIft5aIVGAXicsNm2imHgGED83SJkYzH1MdRju89at5u7FIf9oRq
yDyxK09CSXO82b1a106nkm2sr4nhBBLD2M0OUUW2TQHAyw/WYuOZToyaEkbYFlbMJ+RPb0+DEIz0
NOF/e1XbpwZFPyljhuSRzlNHVoUfmWIfo3+9PM2dMOJHJxwjdKDmXF7nISKFf6imgmNOyLEIcvl4
kNzWkUvmY+LsE3zwInN/thrIbO9XrmrbIODdXefU9iWYqd0/2eXU+IuSuVD2/LZ2G2bxca0hvKbt
NsJOfj3akAZzuSMgR9IRriLs9NTzFB7BqG+kchgn37lESHObVaVtcHaxf5GXCuhVuu9ZQqwQg1bX
QH+lBrFahbaKhYW4CHBluWMawH7HBW2dQEhX3MyH6MHVylYk8UtyiU4BHzBckFp4NGRm99Wkrlsp
YpoCqbbeH/Wmnkc3U/8unS7oNZNjhgBaylxQF4ySkMu/E1QjIdV7pIkvyeP9ccm0CeZfFeuNg4uA
qBxKk3VuJlFUzeoJSBwSzw83WrIxlu8x11wY2LQU8G/tNETTDT5qVPiWfJ7IvyrmHcs+m4JAaDM4
p0W4fFIjYerAslgSWPyHq5i47kDwZwt1VML8Bf8SqGrWnpdPCGMt6n82HHRlJE9LL3T35+Vg8Vuu
STtQ6P/zYb6wFziqXzxdjhg6DndzRIqT4m/0B91LFidp/lZFxiPiqRPONEMZSVUVFqPGcDhTXYpk
TXCuvhtclfDAM3bZKUmfNyVkBuFWYZMcSBL4Qy1A+oF0SNcqQiTbzImpsue7sJcC1ptqnQtS/N7d
Jjv73ovOa+dpKZbxp2Rs/iPZfRLGBEwaKQVeBl9/uOriL7ZC6LsZ6KSXhnPRRua5dOuajmWv7WSl
bYl17ErG1GfoMGpC02kzp8yQPsnXKykNMiaAjjbN/2WzQsACIGJ8Vl3cqPGtPKugrinOuBSOyjGQ
0K6WF4gvxYYeySjoLLfeoD2smKvT9tmcFtEYBjMjiggvfCKrbgYDW0s09ySpRAs1gZOrfnjav8yL
ZvYpdAHRL1V00+W100PPzXLjE2VaP/hVgAr1XtfsX+p7MFZLhNUycDCPN1enXGNdvfq6NP+ZHJ7I
vB1X5QGwL/5F0DXzrT/wmHXM/FQ1TyxYiL0TwxQy+EYc0fjgb4qg+KLyV7YbXEcyWlcP4viICiNn
Bim4vdwJVrfkwS+dpPIMMj8xvp/cEXABwkA7j0CUft69NYbC//BSya7UnstkjlG9RcuqtOyuzLxC
x/hk/qLtJ5QqvpK4a879YHfYoNu3i8EzdUldGjXSjwTfhK4BaW89oPjUKDYta445VCrrruXnFA4O
CvlVpEA5tA3O0T4TLiYfSEGEMJ5Klq0WA2aqtmzwsgLelO4RRx8g7VtIYrhPVHGVSBQRuTxmoXef
LR4U0jWhsXSRVi5rVnA1AJJ5CJ1/WgwaTm9pcHv9H56pblrGk1dJu+SKpp01tw/ElBG4SnbxTzjM
6wA4/JSkYcluJ8RJ36eKKCUzGeesk4RpdicS1niiGhBcQ+IdKObTuKVtdpB6kdBGkC6IpO8r+hry
w8mKer0dkKR4qet3wYIMC4ahWCBelQeH5oKUCmC6ut4HBXxL0IhHMn0kSmFai1RAopcMPjY37Br+
fAzRzVEQVCBPRn6l/x0awoF+T53l85Fpp3Y0tG0IrD1HO2vK5ClfFiRFNG9sWD7wSVVcli2aS1yJ
UpxtZ3GlJMbsDU16gPxDN8R0Q5OgR3+EaNkRrGG2/uss8aC6hbRMzk39yV2i1fWZ19PMbc9Z2gHl
9exsUh0FUeCorWkizn86OuhpyUW5GQifjiIm6aIC4y71ox0r3zbToZOx9gIFsSIRYHc48eI9eYNY
+Upqum3eNXelc3/o0iFcXZikiYaZl6eF2uJU2F2syilmhjhJ50pGA+7g2ocDKsmkA6Vd2fR5rM2Y
wG22sxoree5riCVAIZdyfhMoJxDgqYyX4Sx3vRSYIeTYCtDXZ84YkR0TPB65QgFO2nl+zIHHNO1S
vwMZxZTlGEN5HvBJqkwGTbHNA5K0xrbb6/BcoScpyt6HgieSHds8mSXDGR/B4pwupcy3BZYFP3xZ
5OajzAxGcB0KnUi9mFis78cPyU2T3aMfk6oHXNGaeGoFTCiFIK2yZ7Jwnp2zUiR/y8n+4bWQfxjx
oUkjBICVNz25fsxvX3K+qctpC2ZarOwD10IrRyzsUAtx7LXuI0nxBE4lDJRe80m/l2ORWuI5KFVh
9CNw/0xrk5iyjLie1PR44d2+ldazQ8Y4MexkMp1JmlN+luF2RMH1I9VHY+k4pa/VGU7rPEO13ePI
lQIY4SA0Tkg2Vpstw8Dg68fVup3cXz0bBBOX1f5bUrSq4z6jAMA28iv4Z85jdaidXzkHNoaR11BK
wYvA3kJoadmnVJGCcp/2TeQLXm7YIw5buO8FjFOg1e+PhKZo6AVXQtlbRicUPD/t8H4O1B0ljpb1
Xzqy6VAxG0cbwoSR8LIAuv/OIevLGNWJ1HtNJe581YlBltSj7AMY0znAp0jFlZgA7u5gwsdCYBS1
fCxaeKFiUpDmbpObbSG2iqyx00qXCpDWKF7aM72IofkiroTffejDhZi0TXG4ZpDEzFetTfRbnekH
GucwFFNAzq5oHURtoK/f11NkePSJ9Fjtc/Mqum4TVhNCaTEvbXHMW5Qu/0LtVBUNjPQBxBrL9r6m
AVCfH4lYtDGC6+jEWL5wctv/awX3+PZ7Z6e6EXT5qfi0kjpFbE61P36BwY6vCzMFobhZXJTyucDE
psF3kY8zyKcPoyawChNpZIapNIlicmFzOAlZnYbM6J8fEvqgXfF1r2DDaVS85wCyiDJprIoF5wY1
QnEncJViC+6Hyrr+2Gh3DF5p2efCgwN0Cx+Au6bLrINj6fyP5jZmdLOPWGO9Qc18iw2mPvmS+7UV
yvyznwIheyA5qwgNt+Ad1HBwJCamnfLsoLm3Gmr+oabI7PInJHqDDq5+p3vcTbqbGwU1cI3OrJyi
9OoRmIiA0bcbZppKx3A9ogki9PkJSJNTSIjA2KaDZMevNqsCajnnyc8d7CATpX0m1YEyDEQW/qaG
Cp23VJnWPS5l58hFtTF2qgyBpQJkePd5mGFuEP/3suBphJIHpuvJiXMcoVg9hap6yYAr7jsyRHg8
M5JJgOk/OoJEXZmZqGgsss0eerhdQ38XThm7hR7N1JhlOBi2zh299Lo7Cc24qufb3VYvKsiDowUB
1/hUDsQQ0L7ISPktKOBQKf28m/VZDH8+1Q1d6wYadHnzJAOgFul+6BZobOKyUPmQm4H5VUvTLmbn
gqTgFU4xwIR/1IrXFRGe2P1OHDqENT1vGHhgFP/CqGCQAMQVbDHCKEulNs5Xh7ZTNnGf+xJTZwuK
MostmZK6L11bsD+pb2rx9R4nHfNtgaFiOhkbGGwO3XkC7eK6+ybZkMXIWjRlJtKJ27mj/cfxmRPH
f5FzVH841Ba3LwgWeKhWL1/zQfLlWQCTwG5dqYniQXWaKdPIxwtd8ZbqGmGJZBNjhU/unuBp6DlG
UIQ/pX42ch/w0Wrf5GSNwKiNF4MSV3mdiyPt7H9aRQTjHc6LgqW82GoIC1Ugkk1WZsXQwAQtZYkE
+is52Ie3P2U3oXA3JRzuk1ymVVwMSOfv/P+JuOwVMFLxZxFeASPoa9/1kFJSdxI+iDec0Xgt6+/t
tukPeFdmlPn5AHwuuXuZIdv1znEbTY7jEMvtqqTsxaboZagAKlKx7BQsshmRUhFrJQL3IRVDW4G2
RErUDw2vPRewl4OMC7CNqdyqw1l0R9v0//CiN/cOf7/1vXuIAvHvRCzuPmfyH9k+UdsMCy6ERtak
bjcepoZH0RKgOy4GxN/tD+8P3QYRfTvzQ6X108gcJqR3dg2TW20zjS7HBK/xWLYQ0/RSY2jQvhgF
O3fbGPLoZ9y6etJI4qTaVRDkZn5xldeWag3lo00UbT3E1RKm9xcJnmE5bbRxj5xfAv8uk3/ypH11
sfuKeiDwM8CK0qWH2lC7xBdmuC8e8NPO6D3OycNY4p8T4+6JdSiH1eSqXYHANuKpUCFTaVOHjI6M
qs9FjuFYEswEpsasp+7wQaeuqkNJDof445IKsDTv9MJCeOlQD05pi6AUZBftUr4z+kRFIQONUOa+
z6omAiAktYKQkL2FGgwIp9pEMNI8kshr2imJHNKzKEvt4ko1cWcDSTs7XJfxgQ8j5E5zNGqxDiHc
rTIqWeyFGXCWTkT7uVreeXjJSiJIFcu0qA99GHT2rxdXm4zstSNQR/snKQfOulgtlrELwk5KG6+Q
C7IXkq83YtfCUYlA0BVvSNzqTG59QIo0jpt9V5znrfOaYEWhanCIkssgm2VyknH35kAkhvtB+F+s
wOARh4uXO1SeBbcs3CqCVJf3AMsNU4fuch3dJtbAz82NHIH9pNLz3HW2rq9K766oUikvU6WzU9k0
UWquTsD651IBHqDkm8/E6FmN5FxH6UgmYeXwaSxNrejy/lTo3/npQksLTatFDCAMCKzF21nFiGVB
C8CnVQ4KXD651TmLSbx0itfexL2oMkD66bPwjcQq9lqmUizL94GNNQ3I9nHAGx2IZaJm1S+0XHcE
/1BBXc5w9BffnCFJlYEK0CJWWewMp/rTbskrHW+521aHcbD0SyPG1g3K5M8AuxxcceD0sduPq9dv
P6w9t60mzok7eNU15eBJzYWbm9fHqkgYu1ob2OLRNmOK9/v02kEKkRzr46N6vMXF2hkkYpOgj8SX
kwLqjdKN9U5alj8+a65b4GreGmgnBqUpF3YKY5gTc8of7ZQPKkgWMZiB4fayvBmoQGOJTs4TlxMT
lKrVClnfeRHf0MvqK7huSVWzl14aIgJp63HcJU9P/2Rlu+BLE24LzyKp6fW5RluLPgO8WdQQCBwr
5HWQ2Ktj0K8qPuWgHTCY1EEz2IZXvzys6eaiAYZ3Oc7rc0ZR60U/MSZuJJdxyTZHJoKG6xs3cBJ2
WWre9WtS32rH62YRsTeFCmTe6yarVndFyEm1j8BxtAsDBQU4W9bkkSOmYFCSrnk57qhqoXELeTwk
F6wbsLGdwQrGEH3t1ldDsJ1qOa74gpTwLD3wIoi2Pn8Z5HNdWQFFOLYifmvdrLhS7VIKHkWcCtgB
4DNGF1R11YOipzMdkq59WQUQ3DPEOvFzthjibO3T98A4grLJRYSA1ahdcls0Q3urPTMIZ4qBWHm9
kkUFMtxZFRKtdkmy6ZI72cMfj/vvg+zWYgd4k7lco7UKta58wDItfm3Axx42iFW3V79p5nibUD6x
3PMyiGScx3GYqRXVUAC1akldgIYICATt+zsQpEQ0a1JCaFD2uhQj8dxkRjRYdFyILY4A9RQDfALN
RmQ0D58eo9vBiSx98+yXMX+/RjEfl3427XyHflwGrfFdscUgRcKAEPhpKD+k9xC04eBc9WLp8VoG
lkWjaRxSt2uD1dVx4VSEqeZtM7vUN2S1XKzA5Wa9vWW805FilrElMbcEhHZIQvJ9bLcFfXgObJIR
qaVIt1tm2u4p3L7uFDtYaPZ/+vw+N8wAWcLcoq7qczHT/TmgSFtj7nVdW7rILH4Th/GrNLZXz/9t
tOpcF2aEg4rXtcbhWoqBOZJo1jG6svB9doP26Yp5nB3jjMdllMY0uASkLwLYzIX9Yj10Y8+gOvUi
9pBfWYYnDf9v1J7lDDyCYl7jHX+zU4fLRlkMNJOj5auVaX3sAtT+OEsIX4gNmEndm+I0zJl3ivUo
IgOZ4inU1TABiGktZvP4SxTElGnzY3dj6EbU7czn2Y/w5MiLpAF0vhvvdquqQ0ycy7szxIKAIvU1
kZ2ms+kJp3qbcJFxlRKKyB9jFec6UOquvXs/RV3WUc5O5z+xoiV8YtWGjOGWjlR79Xlna+G/An1r
1vO/eK/cgTdh7LK57g/Y6ZFHag3aGN4n7nsXvbm2LMhuFORyV6avSY5zJcT5uZAg8t5z6IXhMmRL
dZXjZ2cIFTCz2SKk/BseMuxXvFv+dnwzLZNJUTnWPczuJmcgbeTHkNo/oBnRm3d4rbZhbarfsISq
SkjqN5/ZIwDgeAzebw9QJ/JUkP/tuNvUuGsvPLCjpWLsy3VYkGTplAYwXESchwnCr0gKqO4C5TVQ
RAAiB4/BkY/eL6C86n3xTK2GMdFnhpwk4wDTniWZ+yhkxldOvQAeDfVZ8K4C7FVzkawV/uN5KPRQ
9TxLiHXAFKbevHa+89qBhUmElulnsiyzXq0qtPtHThapLmfsNsLgS+ozAFLmjrwvBG9tL0sD5lLO
8egrb/k1hX+tTdOcpVKJvdFrlix5J/k0kOKN/YAUC4k98+pr3qi2OQztLyEk0UXFKEbQGae/jJ6A
7ZbNu0OxAZPfnHUZhSCqkHHHlV/wGJ89btVqMdVtQMBuISMf2b6z5+yUdpIIWEynQ5jDfGVCe6JE
da8919ncx0Wc2CARaHT8KAVOysO8J3G3zpwBcPeCZm1p65YEs0G2GmITqHtx8zE4lpiXZcuaZLEc
0DrE+t5bqgAlEL4R6+4qMvrS+f9Uucs/qZ4XmQLesgbuFCfwths4jQaClu+R9hJaxNlmscNdboqv
kPaKKrHJwi8VwlLjgr3NhtjvTMuIDST2vFzNA813Bj2TwdUQtb6bBIBtuMsQvJXgvYT+pKz5Nm3d
n9dhzDYxr5a8yhJSogftnXj8YWA+lB5AzO4eJWKpsBbr18mwR0ubJaujPbDjrUgGrWgmyfjmEofH
K8EolgBMgR5bnVPJN81UjkqpjHi1fbnZukjniFVyu2PPKPawqy8wKzoSQ3cp2klVnBlAIjtDpnru
2L51Im7w2f1hGxrVAIJBHbDAEKBfxI//iq5tMmhbVMorCWJNOxQcheyMX9NzylCSGplzWPLeRVuo
XjrUpZFi0FwZ2/dNVZ8AXwTtHw1lv1lfVQLAq+/wXcDcHcW0b96DHu1mTkLMeyeP36i+veXOBtH4
BRyzCTKJhK5MAjuVHJ7xAVPgsYEOWT/FJ+fUWtXGI0rQJLrIFWTT43QIJxuqPJyJRxs8IFGt/S84
G8d0SHKaU2zGx47Q8c/P+W44McRz5+7NwYIH8heru2cKoruIyIcCMLmBm+YlPeMmj0D9QFwwuBK/
yqVRtsjk9sHjNvyCUXrLY40nMWqQJ0K38QvrhFtDKT9WD6cRNrd1ESNMEafQ4016W4bBdRf71Ci6
4vIv+ZGWBeKObmyCQAakg0KJiL2GvlRnnQkq1IG5auqSKbTPoWV+ceZ39lyXzoik15Lbd+qOgwlx
1zCCjgBvenlaprQUXhImbpx5qVMmqUowNlhSlyr4zGjhiuk2VufosBpHbRQkuPVAdMsPAn8YijfE
M8nZVgcq1VdYhTN58CRP0WlZeZTxiOFXHzdcxEeN5IPUav2h6WKLImlLpPtroIxQ/9Pconts0rJi
P8SwM2hRcBABXq5Tk2VHe2eBPrLkRkzyuFHUSasnG+tXHWda/HHy/sDd17M2TWb2kHQSRyY1bYu7
hOFtCLJ9MX6BiKCvkIHtbO6MzIvaD1w8k/TS88Uxl9NeMHtGwxWe41wHpr3ABLiGdt60+hcfPBj7
eChnNUGmku48l8NUXmjxZIgrp1KDch5z7RGQUICNZPA/LJlLBjXxebE/T2HTuoHuWaPmF6g4FokV
v1DmiB1p/Wo+kz/kmhhyNgh2c3nhKaQcZ8nAkIFObEmOqqpoMw8JilnE1wD3IeW4rjQZXTCv4TWY
HrGLAXiYAnMDgl4qSeTrmztT3/MM8mNuzIiZZWuM/oDj004Pg8OKRYCXbPtu5PbL/IcDCzP0HmDC
fzCYZ7oaEg8LLbxL5dHrvXAYoQWEOkirpWV7LSOJwweNKwtYGOn8ZCpoa3YdKdhM8uBhvCJI0dnY
8YwEKT/Zhq4BBXdGbVeMWnTEZVFVmB0uqHuOUUZfDMTsHHO4m6z8idGjbsL6GqfnhVZMCk+vF6re
UZnEJ0KyLqdLkgozOe7LMgsogSWgAeEJpEnRVEATL0D0E1JjasAM4OaPCMjcMCZWLRzrnrr6+X0U
6C9G9ViE0xrzlYhpzZaGHXho1NHYCVxcp+hjVBhiPLSv8TIv/7ssdROz1u6kNSnMH1pc2OvEKf2b
PVPH4EicSIOTosnYhLSVT+fkDXm1YkCaoZ4i9D2dIk9cnXRtizT+lLtjRqO54dshxkeiSzDfpSOR
acQtMBE9IRh5/3DwlRqD2eZb+s+XnZUdCZ3qeaNsK8A/GnNAbQtpZevNWW5kDJgoPyfnmhU3Pme2
UVzwnjaZHCciGsZ+qKOA2oa0CJvCJFDkZbxdUz/bTLA8GNrUTqfILOFWs0NuvEGkI+VjtQZ5is5i
8LQpZhyMLOhViO1f9hood3tcYv40z1nzZJ5LCk0Nf+eQg++pTsldKqY3/vKdhykmRc3ybEStmUYu
tzK2G4OevLJJvf3l9xNL1irooO8YcF6UnI6QxWMIWbaisR2pr6cys8CmdnBDmxxCQ5FLzpfiQq5q
JBNUYFCsYGzP3nLHt6tJy1Tj+LbTnXj09LPvnaY6X3irQ3EHeBciHBb89tI0g5bKtCTqaPYtVkZi
uD0FHrqtPMxaMm8zTbG4P9m9xoNIcL/CjGDrYOVdLRGfqnB7776Qs0j6GLo/LR7Q2CVeFCFRtM9p
5O3SmtjvNPru7GBPJoGeiwK02q4yQg1wIsS1RqME/bG6yS/98p4cjM4gJbv54bT7ENOH2koat/Hf
VgKUMcONqGhf/2D2hs2NydT2sebX9qIAvmGd+kYM3ZXYPDz5gmSgPdSGqd34Ch61qtSPrFI7zYVF
dACZVCxBuqoW96vjS0MGRvDzfVnrg6SoqZqSV9Y7DSTQSikGRpiehuw+3tjp+4LA4QGy4p96YraB
3MiIwEaTQ2P5PrJlsPz3ecSkbsunqL0RHD8CBdCQkun/1KuY5ZHpEW1UJ78DkGUHa1dBjCw4MrDJ
vWTQQuOU/MkoaiaH+CxvYyEOeGMfBr52NJevjTrRQCdrgTA0ju4I0g9s0tV8nlhLELAtGH1J9gQD
UYifk0d0iOXgbD1w3M4FP1B4PsUWz+ZqiIYhllG5ZT0xySZAO9ORG8ottIjHR2ia9BL3ak29G2it
nYclN8bEv1s43Y5gzhFALIwWjm3GkXXYvhed8vlh8PgJWaEvWPE0YL9MeURjYLqiWFQvtuoyYuhg
gwiVaOn70L7+xvrcg5oc0cjNfgcohGBv/TB3ybUTXJwC4WHIcZqMZUSvCzH5M1yBmRqE89Vr2PaB
lEAIGww22Xb3qNRDaUyaBZNFkiRmOT0aR2KXU+pelRH2d8vqltKZr/B2H2+ukuTb7s+2OohDZnIF
84gpUSw3w1A7POmvxELtPz/A1KS1Aq5bAxVyQNFdAb/DNKFI/1FQWfMaC7Iit4drADKfOgPpuIXY
CysMvvxN+/KC0qeg062fIGiKPzw3iNAeQT2NziS2hkxvKJ6oF2kEL5z+Tr2eTTRA7jcZWx/rlRpk
rz6V771/L5KlxY6rPtAAmIZicu4MPYasdxMEXDh6dkSUytkzt/fcJ6H7hwP4T0ekNMFkyYATSZpd
4Cp46w+JREx6aIwNoiFL1q6ng3CLS88Vu7aAm6Gu9Lef11BOF892Hc8A0xwi/DmuzrmwFoAd+NVA
ifvU2LO2fcs02+VTuUisVfgphCA+KvXjF81EU7ErtiwMEv0TsKdyPkOBbOxWhtzvUDHSB3znNwdc
yDG41fw/f0cio4OULTiwNeAJJZsvy0W6NifXNv4LJl563Vu2ecFbpWpeZyLi/qObfVcvt6bHDE+X
IN6l7mcDZlZRQYlzWmTrTRfaGzAUxUwuHtBR+FOkjIGYRR/5eiIBAKkBe3AFJIedAcKEo/+jr44g
YzdXxZ8Eg2PE4lSHKKwHWpcOVYEdAHA+BtandPnNV4KNEbzWLrtrIsM83ZiN7nz2C9gz6IxaPn8p
ES1LLdMBqrXNpdiHzvdsuu4OrxRwCj4UGEe56kou4aez/sS87p1SZKL4czyf5xwvmkSL8WFIhfiS
5SrETCfUmCrIW3Ind1aK1SFTRKiVSyNfTldEM/dECNjIhtGM70J8WvwqomhSirL2h5Nc1SNuCotx
meRH1Tis8lwylMYAAP5QrpiQLnPGaur/ulYXQ5koY6MGg+38CS87q9+CZNQh4ItqjccS5rMafM19
PYKcAJQvsF6oNGWzrMwdb41GD6QnhI/XjpvUH3aeGzjzp/enEU0i5V1id5Pbv7F9fI1U97mE0Agq
c3Ac81Pf7mG8RbAuWl1TKyUY5XC996W6PyjBZYcvnzhOu4hO8igZGw/uEF42MaPfczEkr6/EdM9h
dgtMv/OT8EJ3LjNYrAlbShRdFnph/mMZ3XOlG1lQwWgXl2t8tEDuuTXexvNFRoHSfIDeV0p0zyMN
DczdhUPIojyKhCQYFQNXvYpkBs/iBLRJIZ0r2SaFh9UaiHFwp6fmJlOPqERY4hEjKIzgM7XmEW5a
LRUrxzgh9zHvNEIQ/0yM2ONbLXXeAblm4mjvae/za17D9Jgx8dBD2Gb4BmJXgbhT1f/aC2Xt1GKl
Qggmv9/3zvSk9anRnu9UMZAFDO+PiTUK3Q6ltMxcPdHo3vNpTjQ08K+z62MiY4qjy70etW2uVj54
wv2F7pxBqEPO6d62YMrSE8MvYXG+BqZFDZI0Yr6n3exc3h0MgppvTJN6jKLz2txYlnxW/P51KieG
I9DPUoQBCTvXrEemwF+DjB4dGn2QeSJTiCrhs0j6PKHwd1dKDPmV+dvjhAYvzjr/UcNb0OhHX+4e
egu5rV74VhFtalU8aMQ9M7pjhR0Xee//NrgfzWP0DHfXOPxeSuK5FV9DLVfxPeB30Tl5y15JlVkg
oM22r0wZL98xCz4U2GhZ+YPi6uC7mGCgHJDnA9KadYxVV1cyg7kTaiiVc/KL0iZqY0RyYOk/bztt
jH5LmmhBHkUtnajVU+K9YngbJqaIi6y+7wnGrPCHBLf1EWMJyT4gQnVdIMBjMxgl1q7vDVrPLU+s
VKvWT0ngm8Ur3IGSkEeGdNTk8Ck+YNtAmd2tcRrrh5lUbGIDIf6U1hKilZKcgOizj3zaIiTjI8m2
exckQwfKzPc7
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
iLOC/zM7Joxw/7u1/3kvLPf/gE0DI9AX05I+qEOauE/7yu3hZQ/vW/F3DMobAlAfRXjv3r131UI4
xp3jO78wPg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
KVI7kykeCSUX5fBocqQpSGyifzzNp8Wh49gB3SY5aCkcF70ujPDG/9hKzVEDulBUoOtbOqYXhoJ6
cDn5xn6BYki3kuRcj1mZItS4T8QaSDgMTEM9Aijj4k0hN6ZLETGBDBJKg2OZZ79WIQrCLm+Yp+jA
b9eXqd54dvp4eMuMoF8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qYUG6c35gMmWOmJ0+Jjb5OdGb2PCL0JkqR78MmUYY5UoyvL3BwaxAiIKYYVkJX7CEXshqD+eBNI0
9W+MVH7wRTJDBCk6PMcmsu3NeQu2XZMDibSGlfuAGYgFFKMmAwU1iWlGD7S5ZAszDxIG7Hsub1G3
cGB12cyCQuhcHZlpZtY3OJmIyOR7T+UzJNJFbx6M7i6pUZFQbBnvjcLm+HX6NInXcmNM9wltRgWc
QA08ofalBcb/79RDwtVfdkQDfNV2q+E28Pw28JJ8iQGzaRuMeSskaCSFhD8B7An5FogQZOgaxqEO
j5vMiNlwpZqnSG9tOie5RYD0VydWTxnYXBO0Gw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A+EeNDHsLpmHCom+HasfIuBBRE0S3bFCigDt49+x3CEwcjYWjxIx0qCtRtVq7CI9wSm/Gin+WWfG
91dfuXZp+eucmiP6CHPUMHYExivhUTYpZBeDxxcPgEBLzUE6gaaPNLKU7gnB+L6RM/V+crK209sI
xnRl4bgcMqLIseSvXtU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
AzEbyYz2+7QSiim7WpYfcDPoQjw6mNgDWG2fArz05h3/f9vy7U+kvSbnU76BD0mI/hcdrW+NdM0u
WayqP6k9VHNoaeVq03RU2UxLJGfLG1pGdUvSG5M3AoP6lKe0tGtU/8OU2ukN7RIIxnFPT5zhqDZ1
bz7Mq+GC7cYzUWbYi8FRC96SdwHeUzfAf5SEfMfH+YvrY9MFrF/8eVGfIgzjjI3MYGgC8EkgyuWQ
D6m2kYJukFy0EcVvneNXMtGT5lTBe7PkgvpUw8UjK2OEv+w607nnaO5HDvgeARyB5d1AhXWLn1mj
1Kn9vGxKm9guwUGKwthrvkUy4jU1ZgFIlTeLrg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19104)
`protect data_block
U2sqQ5Qkdfcwvu9O2/bTBoNh51zIYpjS8j7C3+fMQ7h0wN0JOPdBtyrCfdE2QfLKv85tSc1BegVo
KBVgvvg903b+N8RMX6uz+ksO1DPK0Bc/G7dtSY1RFMIuhlsZ0eGDXGOOVLLlLPpqcbIR732iHkNc
ei+L8oALEVwIpf7+Qyuk6wz0ALJ0rUD+vqp5hfVGyYRf7zEnD4pweTWN/5IJ5K8cUlnddKFLIupP
mqyWRXQjL2LI0oXpyGrtiKCxgC/iwu6a7l//KqBavg9ZdpB3KYc7ss1Z6GnDCoDwwnAeOZAJbQpL
TM2Ygooepikxl3TS+SX8B6yHp/EmeLN4AbbYyuj4cEKbIDpjSNgq3cNueoypY28/Cw91Dr+g0sk0
m5COCkkhSaXJoIkDP8M3ien6i5uCbQ+edkb72Xpo/uw9LwWe2WgIOHHl2q42fANP4pBi8kI5GUzY
Ow+VZbdwHDCcu/+EGN/wnD4E2bzMF3YvipqRZ4+dlNd1CqAV4zaz9jngH4lQi9DgsER7IrhdISKI
+BkphY7K4mDDXoFmwUCalW0/mK14Krq6D6OAgPOupHgQM9gWSCK4NbCl/BHbMYhETWBXKSwhEevf
0ouMElCCDzTQPABImhtXqp0+Ln+EUi5+ZiyhaScNOArUaRSg2A70bOnkwZkpKWuIJ6ekYvdCLEFx
WtpqhxsBj5L+w6eDX3cQZNoaTePPN/dvunXBNYRioVdg121U9CfggaZu5m03/zO9Nr4S1mRfPH7J
MQ9omi6giypyGXiNukrIpYo5tO1sezgM7Blafx+9qKOrTcQaeUS8KpQXXlwupNB+m7Ons2HmzO+F
zv0fetMTignnAw0uvTpX1odtI17TGBLg2kmb3vbEZKMXibkQRWWKGwXaLoVaOZuRpMY+PDj1VKUO
VVmboN8Jq+rm9yFAaPITFpCgz8tCBrT1iufL/yHSqCau3cdHHzNB4gCY57dHeIxBaGHBVz8KITj4
DLp2qbT1iRzRPqWD+2cqojGL35hsk+McJh/8WAshX2O0ECwWRrQbsXSI+xjLn4krEqWEA0pIfZWB
mrZ+lw5/INBGw7JPEozScLYfUvV4NKT769e44SZ6N1ho1aHDI05k15/sozEOhZLYNAnliyrQBkUf
ir0deJGlPH2XyOITsVckllAOzwUdAQPqceyTMjL1OsYwe6uMe02izKLensA22wrwVKH9n2aclzu3
Kdog5Xju0HxfHqeWWTFsD0bJs5TFYI5lKKmnNMscBKhOiKt7UpFTIX3wUZWHOUQcMPBudHswP1Rz
XD9dXP4vUYviG8STMAt72hjJgHPqkM7rN2Mt8Lj+6pXTkLWVNMC7IcdNmSl9GFwBnTvv/7sjJKnD
QOvKabzUW/boM5vdcPU8iOXd5wev5EiEv19KrozoWB0H4gEK2nlym78UJ7yWvXZvV4CBpupp+ujY
V78ViKjXIvIaFLvnEhQtgb/4RiGerkSqnveTYPLk7He+2H3Sq83zT6lIO0L0Nc21I2Uknrg/gGsN
WdDFnsFWheAVTj20SWOBFtd2Gl8Dp/JVlpCX/3jvSKgF5AGAHUhS0gJZGLZZiymY7Q1AHbZr63sj
QqWvXavs0xlIJAjDlCEE3iJ7sE+C0F96O1ek9EgE9Y4V+UbuSqnx2AIYHVy/nD6Qd7k+JsFoxhhq
pXxJRybnHDrVks36jKM9SCAgPX2B7nGfXnR2UuCU9f5dBeCxzpyLTO/Cv/Iwcg/C8Z6E0X164Usr
T0a8As85XgTJ7SvhXSKyzoX+6ASCtmjgUdR+MmnN2LaDeFQBzdjKlq42ulUAN7hLBEoqFzYAnJBA
7AkonwxuWY6GK31wy/tatnbwcaB9Wg3MFlDfRQakcGMRB5+4UqudfEwzHFW7zY9sBxDQOVi3cVxY
lMj0stJmRZVg/jh47vWLkb6nPfGL01tShHouP/JmBUHO0ib5JVGGsxPI/w5ZkS012uA52WWe4AqR
aNhXBT/Wj7xly1nvj0d1USAfNDiHDeISRI61MXMw5vbg85KGPdwmz5E+iJGZydtlaPn4NGX3klxG
NZTqj/PHYizcH5jxsyeLEPUwnlPHvVFAgXl08dpCagKsPCRGGtLUNhvsc9eqBLvOouwpZL2+zEYT
cgA4BRcznT2Jm//EZGihHc/TS6ZZjihHBNH+ZGbu+wWcTgtrodj4qEf6TyCoR0jvgMX9RmQn3if4
Q/NyETOSjRzVrQWVuPmJnKs9etxfSlESgwxhJ8Ba6sAag2nWQw6QCyJ8iSe2Uau5pYhtJjwAxCQ2
zEVnw1i66UUOpKAY4w4kXg1hvi6hdcEfN2NcH1tm2oZMB0BZVRlAEMEw2WLQR5/tTkOWMdC9GzNg
vX3NkkZAiq7peuNRFkq9+K3TvrZI0tEkcKtpDYbyexU3cC0WzWj18ES5qfohi+0pNXS9Zq15VPmP
snqeR0mD8usuuj0+03rfnxzki8CfJFRhMT5zAhpHjoDhZ+gPp030Yet+gAqRvjX08iGKNOXUy/So
0kuzLpOY2V4idoOcmlcrwkX7z8vj3NFOQrr8taKkA9yjvFJ8qWaBK2+8H40YZ6pNNgfytS9uadvK
iiBNTmpWkWYfbTJGw+gniuLQSXyzrm8WkbGc/tDr9gygDQvCZT3fRlSdQMCwqo69sIYM6gkSBZSP
cah3ClpcUoUkss0hrwiKKYUpzT1PuicD2lVIDOlAV+Nt7aVw5mElDXwwV8Vb/hpRVx8EqbbpeIW0
kUHdZc3HgPsfbNg1N71zRZgHYTEJvidEWkh+PZ469qRm0XbO/G5YzUxc3FA0cnucG4vT5n1PiKpd
15MHzsd2exRokmMpLb0k3q8xP/Xr9mokDnFT1hu8eNNL18QrPNIWrntez7ZBJLcX6MmgXSLgBjEy
zj8rbDLpVPIDLb7zFB8sgbJtjUa+9bWFQY3AIEouuU0VY6ByqgG/EpzEbfE0riAFKnwNLdgZt7yh
VU5UhDItVDgqacV/QCMriSLeQj4ScWRRf3GUfQb9m3rg2X52W+uV9kKofy9Ecwbvrf56qMRxf5So
BS4G3WMWB3FW2dvXZc3vdU23MzKP3gW513Bwr9QkYZt9sbQMCVtCLt2DkugERw9mnh0814ew5KB3
Idql4GPyW+/LvSky5sdZhXgmFEv7y7E4k0DCMBS6L3qxEysEl/SBpW3bsTqw5QNuauTqfeU07NeO
iwk2L1xfiBv2NY5fD1cGw1jkdH2E99KKjNSvW7em4LARB3Q5J/uoXDOM4zuYAHBzlbgNDJHkNjF3
BpKXxO3IMFUq/39LcJnIa4ZTI5ScvfKtn8QucLyDcB4QDXXGLg9uArcgLSkX2H8csW3AByOe2DKV
ORIwFbDEf/2cqKkPjXWUgllCmGRnKYJgmu/5oH3zBFFG91P3MTHV54zZqiKjvcUfuXisgVim32fJ
3QMmlHHDE8UhxLlI7CSl3tZWpMwVNvHipqSXfHfyrt7YGGE72Lb3ncTeSZfxOsd00+1JPqEsYIxq
uUFnRxMTIpBybedLpvUTth+f9qv5Y7p5i8FS2BDDzqAx+Jjg/vj56kz1Z6um2sjM07zZqG5XVxUm
qZhIhpo8iqGbgYJ1qz5yALxVSKNwegz0Z9HV5486yvXuIsXVUJhakMemKN7YSm891UcO3Z4aVxlf
PXN6ug5JQJJvQIhuhZjaYWEyN8zWSZHWR9+LkbX+ZP88dA2+hAK88T03OEtNbUxTdnsbTNSA4gRA
LClvGXqNaIzTKrMWkY5Q1GG2FRL5ZDGtqHNjgmeIApCXbvJaJPmOhYSULr5hWVTA8sPHDVAyZQ44
KHlf/kYd2vH4CCndKgZ8NPmH5MOA+X9wV8cG1yVULrkysoVc4FMw9PYNTsKJx1YQQhErw6hgYTgb
oJNm7dyNCn5OB3i/s5DgxFEN85C0gSjjPe7YK9s8wgM8EFIjjdjlrgqFeWEhWsUhPiVsMisRmXGt
Zww/aqeNXbmuKPg9rQzf2dxYb1u6BvZAZwGEj/QXCpouYHA/+sqV9nrLS6P1O7vzl1ykZjvciCRW
piT190KlFkTmrQPA8XyM6YmLLGQ77OL//RfHCKh1MqBZ+XIT7E7dgezchbdggf3dqhCUn865meWG
4smMmUSw2zPjh2a1dQtMj/TJshXb7GWVPLWEXkqyIbeajDTa9PxoBrk+xJl2XSOaafzLG2/AyYTX
daD7xWK9iRYcrf5qb/nEnBr/jzPwagIL9/YIAmhFBHrU3c+O3wA0DPGbe5LNuve9RFYsznRdRJ67
TdeU1C1zDEB8UwjEISHF5A3sunKHdHAvd/+4WmWS+eZ6begy/Gmkmh3ySlPvHDlliokxb5IZb0RZ
GDRSFBw9IZYmfaq1e6VpE1kzqsyzVhD1c+X4OUp63FT5sZEowoMG+b6JgTlJCdVjIyaIBVP+w4ja
lR78lcf0mjRHSuMS+/78XsViz/S+dYOGzS6EBdpaUoGKzPFUBMiL+fKfZ9/E7OQvFDWWo0q79pPR
89S8YN6Cirw7+Q5e0VehaiLY7Gz1vCtFi5bwjdRarfIwYZ7lxLE18lBxvITbvJ4MRVprrHMNhWKB
H58XpB4xYsIk9OFG/q08w4ZyiYKgfH2D+Byjt6B/PnmSb/p4NX+mrFsXyhDkIEj+Z7sGhkG90myz
MmJiURPA4XhVWdSNpF/YqCr0Ap0qiD1Y2TwUb3I8DRaa8kw4JK162FvcZUykoIMOlNVrNsYNilGN
uFrQJJ0faDBuQ4NYjFcpfsGJKGItzVo2f9Ypgto/S2QKBpoFchVV06iW0HLpfHcTb1RSrS830Ge4
kPoRxqCaUA4c1wxz+FILYM/qzVoaqfEEsj2dggXIgWtXPfXkXtMudaKnGNK2jT2ffBFRkKQ+L4kP
zP8Cn0GmGJr1wROF38GUMbdYr8rAbzzG0Lx1d6wltxUD34fZIV1nsR25jdeVG452aH6RhbS8KZZz
HGthRYwKBnHxwhAel9K24H1jIvxT47UOwm1qNczd5fu1sef8kvTY5CRlsa+wAPrxZdbYGW/5YFBu
P6njcMwx8qqfbqr0Ieox3+0VxVXwVivS5ILZhLlyUnimvenItNJl8o17+0L6oh473HKBcnb9ixSW
EseEXfFF1Pj/tB4nNip5oRorcM09jHWq9wUzL/5Ckz1NgcARMmvPCK+DWpvpl1kPwQkjyOKc3weO
WotioMQadHnnUQres32HHBi2Cf+O+yyZWurVzZkFrbUD+zGVHVd1vXUvCNpn+JfzXW3nu+/eU5ls
iYJKPwBOjc+kW5AryeaXTdo71wXYuaEu5QnNsy9+bJfzj9wUyIfQ+D7qIbtICO68jqh0rXyE4Yyf
cxYRpRkIdxRC/c0PRUTj5htOAC8AP0F7GHDpGRXNNbc8hPVkSF6NzqDJc92r+o1L/XIFC0cgrAOb
FDobTZTOGk6a//0DkvqV0pxKjVA6n8yM7yuADO9MWgOEcJmJ08vPNwn30f2gzyt0GAd4GcT2lLLc
VUf4MFW4LqpYe7W46sGFSTqBkqB9crzIZAhlGc+WzZ9bYzSPg2ekS+qb04As7o6Rx98FtP5SOWsO
IcE4xGqZnvNbfQyQ8H4Wp5/IETwbdaAX6ymY2Ad4nB6Ap6SHvMHjgs87bAvDx7vziNPOrFmyMr1c
hn/x08yPI3Uq3KSq/u8WgDAABBcUB0l5HpcjnANctnqsesnBPzNOA2onI+Yl9hzh7TOvuMneYiMx
wXlk11q/3kehxlbqvsv5wjn0Es+wCAtNpM+DkthYuNvpGkY7DS1z3+8KhxH923wrJt2UvycyQVBd
VYGsNfoiHmdqjPCDpfuGywEVa9Am3fLN4DJR7tMbVChg1Inzo3meUhMA9QrYPbTrMO8614hVAwRW
5DqEqYSXXBkGEdgaOP9vqdA1Xan5VR6UuXvWdXk2lSPs4aplZyjn4M6swkdNe7SotNjD0aiqKaSV
ckOTH+r16DFVGPovX/Xkk4CFBxXX5J6Wp4noWMHcXA1L9mExBp9eKz1RtQbnr4pdcgG8dlgz+HAd
vKHQr1ZplfHJyTJpxge5PUCyMiDNHT1IE6jNxX6FexO0Qe0I1FvyDRNiMFiohUglhlagrK7iOfZT
QqsTR7cG5trwC5GwlIjHpK44zC2m+2/6niHegQNVCKYJj56jaEDiONRj0c74jyOaV30b2e1sYbh0
tKSIPaQaAvf5HJGoDVE9mMW8vHDSdMUylodKDBZkG93o9Ry71KFTNs3fpfxvJM1fV71+556jdIq3
9PFPr9d2KASHco04biATGA68QVFQrrAtul1zTnjyGQl7dOCI6WJCm227O5nJ0+AyAj1zWWU7a7FG
lNl0BbFCl3d4qm3TOejuQcJSoiK5iWhOrQrLfMlLTLoBeeiiVETvEhrn6ZzmJus5lrB6JzrGFg6a
0hJDEKyigFgLccLVaW+R7OFdL19Q45cWagAAfG7uxnDTgM+he1akgruDnQ+Ddeu3fXubS1pZvO9C
jAqEC1tWhuTLpmUx6xN1QQu7EPOyAxKDOCZrl78M3w4dyyZXUgirxODO3qK1ZnlZoF9XMAV4kK9g
aTtwpHTQTDrRdAc5ZqWqc2rb9Ari3d8qSkn7vtqDUK+OQstvyT7grdzRhUQ1gQa1NHtaCrEklgx9
9DRvEN7IIQVPPot9VLN8Trk5S5gSiCr1w0W/LYWS5QQfH0+BYAY+0CrruoOMNrsuwo9kmi7uaUIM
ylWpz5b5+Aw8sbCeWjyvToPGn5z/X/TsblxVIDhZzozJOSxP1KdBBpKI1j99ZOk9yXcYx6rGme9i
6rCtD0qWMXek2nHjFZOGXvttWIe1WPJIbo1eYfwXk6eZHAZ7G8ljBbB5A7SkCuITyzU/CTpi/EgO
lQSxzWlUcvO2tXcAnp8HKYtVDv58hH62Ddp02SUrHjqjo3sUIRnJHvJTa9kZUM2Qg5zjrCK0LdE6
RL53OYsSIN9e36YjoGijt+R+ynGSGaLp14jJ/DnHF1JKC8RALi6y1r3Yht3OtgnoF3XM/ScEt8DJ
09lrFJHf45zHzH3T3HEEicN+XOgxEOc/6kUFpUxQNoCIFlAe63YBkdz9RWF9gI0fVQklPMU27Oq+
JnW1qfDs5NGErcwTR+reqkAC8v14OfhBAaGUydkBVIFhvKWWiDy9yqqtv74dAmBAn9MU0b6Dg0pl
ysUjH1UOn7d+Rx6/vMroNAEobL6T6IkOEuyTxZ2s/DsENZRj5PXUQK/kURRoKfrAHORm4zkR46Od
WDhVawnq+XJhzgsE0ITvnd0vGuo+1yCpAjgdyG63b3a+eLgBBdbbAKhxo0GI4deQa9w8o9+aQSw1
cfCjP3hH2UoJmqjcW4EZm+QheRyjayZEHAxJV3CSZgCSbj9qJgUo6i4E/FyRUwPR7rVC0TLvPbpZ
AI+MoWLIRKWlltidIp7PrK+v0VOcZ3VO//utzJ1I87dIQQ9lhB3ADDb2DrxAoZxFtnomeJ0+RlKd
7nSQ9O5L6oUQ1kB18g9INDJqjhWpFYUySzEHDQk4IVZs6/WKhK5h5/k/FWEpLbkK3fGfvbWNiFl+
rCusdyG7f010/xb29XL7f8eKcrYAGhtQRX6gM6x8XR1yT747n1mpJo4rhNJhOd7Sxmo47KFUvb5M
qgbsqkIaCGjYW4mD7/zBnJ/vlS/OWWS6jldXD4ZIYGn9OUM/1BOEU9oYASHTNMtPfQkE7n4yda2g
IztwvQ7q7xYcl0ZyESe6Sv+wFGIXX5bMAb37D+Kt4fvo+iZS/RjeppLMpYksBn7UMvtPKHiy3VIK
2XcCKWp902qw+BNSdYxe70AwFoIGVdAWw8t7JSdfTQejsdTxZaBjrPROvykAvhSMb70g84HB5Ucu
FfB85LsOCo+7QQqBrMJM+zvPWtxbp22TFFb5MOnwQVZS3ZrlO9YA1jpygBV0rYfnrww1ZGoYDIf+
z3qvKD+twwF5A7X/uHCX0Wvw7TFP+zbUT/TtgJllk57Ub01ECl47kljgt9l2lpcjNLBdYTohzMxD
eAuglFSjzWfpMBcBWcF3LpVol3HISGj8uBYIsk4yYLzlmnlhD7KHb5S2urHgYG0Hz4uIcGd0GT1V
rXnGefrdaFVDAlQw607Yt54zRWKD5yskUc2FkHXj8z9t+nEEGRYEAauWbTS3OXGxNRQ47fkNls3b
85g+97hscqMW1Mvmv+8M5eyFvqRTgJ2QVRDHaw/VoR/ep+sh5rgWkJ2umJGXnPHZPU5dA8JtBiPT
1KmZKzulQQr4a4ID00XXppeYDNWhf2CU2gTqiCtYIxwi6nk/4ogA+IqZsMqdeV2c7cCTNRZgF0hy
vRFR8rlMf6rhHEOnUqCl2yySQNiXyrKMymWCN1VyLA5FRqiVS2c15RjSGOWEU07tEYnvLoD4piwO
+Nw8Fw6YA8TLkxty0Lm0gjGjyLiEBcRQupTLihAvvO4CUG4cL8kB9AsAP/OWjvDU7x7dMm1SKdKO
ZTeHMCkoMLYEzEyzCmZBiE836TolW0g3Qx2KK8y/Nd7gNBCLAZoGDFgtuz6Um+C7ImBITmU8ek+Y
STcenRX48m4DUJ2dHm6DKkDdm7b+P0eGGskPINl0NJe44OPfzFo6CTHHAH3FVAXsP97h6cWqGY0P
u9ghfbiQG4A0KZ4y5I8yenaYdcjDpDpN8oGaVI9pYgK1XbW0ndS4518QBWDw78gSoW+Joudb+8EJ
f7vSvUTuQM+/HxFasNrNx64WWFJSwlSOG1ELplUYAhuvmfOWS8//gEj5HGI22GDl+k8XHJHfU6lY
wP4gmVs+scyjwiVjeB4QcQxO3llQk8NbNkzGx3C7kEvAOD0r1CgXCUtsaLa+AwBLKyRLXOLTgfHd
2pT6JHjdvbYSZuEiIiA4y3rnjlJwExhDTl2nPbOkNsLKheOSCzRzMWxlyECMp9Q3SssOyeO/aK1x
M+v4HhuJNr58VyifyngjJvAG2HLRIRynvxW2d89CTnth/4UxmEAOH7+2vzZ7vrrydII35ELZcivw
EMH9X1ISdEYfZ3gwqWRgcos4qvPwh7PlqbCBwborXS6MO4wzs9Y/YLE7OpBpAjCqRSqtQQdwHyAA
kgTfm8MVHSegTcSda5g7zl5tgWj50efCyplSwLe1geoY8gfx2GMZbf250elPnxVhqt80hiNUwhyj
kJ+GSAezRmi2waeaCDr6JZ4d6k9xIjn6OAXpKYgJE+NBIt/svDNglZFM6/hFuKGnO0oLAXK7iVWv
F74Yh33SCV7BC4I1AK9fs9vZxPo8gvkDFdA4RMvFhzhyYJnwhQTO6/gU+g+so83zvKz1oPcW36cw
azkIs8lH3hDDFmsXZmpCl9qyI9qDPVWMoaT8dxfGukIfuh7ZQ9LtqsH1m+A58Xqvx20/tHHVxIR5
c9Jq1ukVzY7EwRgURJlpbhnbfxGy4XubyqHCRNPV2Jl2mbonHkYrLL0kCaJUFBmy6LTjkjU6c1Wb
TCcHBXxAC69G9QaOnpTCwLPfFzQ/j7+Li8mQPM3N26DGpKAGNl/0snIvlUoQUQdsUcjkkYU0shop
tXGtYGq+0k3LyWTlihNOaQKcv9DAIeFZ3S1rXNDW7Vlnp9HvpliTGOnR4PCzGIrGp7baxqp5Sqdd
laUgvhE4KGJZevmHW2iW5RSThM+k5iab8fKkcXKBPrPtWHfmMcLpecpM00xak8Bl4ZB9T5RiIYUO
YbxaBpbAjojzFHOn5QPTP49EUqvIIZ3YMFSRRN4UYa+ExFh1zZ+08cYtrrWTX2pMvvdJPBRara6m
V+BubeCG/WLWbMZ4mrRGfLd6hDt7R/J/CZvzhwFrm2P3zEgUaHnT3uGu/MkFVldeLiC3nWak7SS9
NVZcHQY/SYe/HYFFIpkZd5nE9UCv76UsZAcdnIwmZoSmliY6MN17dOs/0X1MNrGwxmSzqDN4MSb7
fO39fvcHsTmU3QP42pUE9UGxmZBIy0/8K9OqZFcYP+rY8cZGoH+B16+rihjDMSJ2Zf+5ER345PYB
P1jTHRb3LMlW4I28zU+xC4mzcRL0MYTe2qG9anE1VQyEoAcJei/OgjeHq1/rMMTJYE5kd4k6Xs1L
wFGFTjBych7wLlmRaBwkDd8mI0cu0mDXDqA5BGWFh11lEoMy6PrvgHsexRYG8EX4UOmqF92CccYW
XO4O/LnrJAwpavhTERZn/530cHEgP850YbpkLXw7h3ByBVY0YuZKvc7g/ipaQaXnYvasBbfoI9H3
oXBNHPmxhKKnQle0DPLvELysFcnE+/zBwcKmk87PJ0x1rUBzhwQgBtXXzhY0k6MPNXynV7Xk6QMT
4eY0vWhBKrq1mOC6vFGYrBGOaA27rN1Qurid9oFdahfWljXbjcie4oLdErgIG4MSa/mtnu2N+TJx
v/VynE5a344O/hqspF6+utaWrEgxPQ/PW2/2FA981qdEyjFwXcm93TEZ5BeTXSK56tROFvLglLmR
mJZwOZuVM3yFkm8WK+Qw1WmiC0sbwpbbMWQMvNoEefbM1reFxeCkemEX1xhwMrAefNsTKEnLPgCg
YqV06fKx56Ram6wZOd7mN8h6SmNkJLcGDZ67u4XtvGiJXnHCktWUqevauoMsmbd2bLSJOGB+nRFy
LbqqqdqM8wB/5Pcc3gTiYjypST+g1meZ0jfyHvUWcf98h17herdvmdxOc/ZImrotgsqzvIIa5rC9
7ev6QSHLK3s0xdgjhxApP/jLLFFK0JZ2itTOVMr/w06WmawtMcYh34xlC79VvDrc2oig0Y51vzlm
5f4hIm7rKxCE5CFCeU0jcjDlFVv94uWKoNB8akqFp9yAQA2Yctti7u1CYm2C8V8RUAZ0QweBLy68
h51Iw3P9bBAg07Kz+/+bjLsTJZueCUnTBT/fwc56kUFjQblF7obVhCy0cUCPeVaeb238MmBZqZk2
9nWOr9Bc7VNbJtWcVOLVZhpG7BrQUc+T9bAl6OYKqJRiOcZYaQDSWuJnfSVugvX9/iU8j9yaoMrD
o0YlxwLLe0D9D1Wykg1kcrFY55Ld/gCuB47gkPs8ePyyqreE4hQyn+8xhrrgAjne4QsKxPnpYsT2
uX3PpCKz7lOol7B/veUfWWgG84rsjwiaNa5Mq1MLunRQF4Ed+SD+NW6ziVC1ytAQzWart9QJiH3p
8RdmKvHrEyrXRW9r1vEJV56KbXKqFXbq95DkJMYJPTKDO2SeljWPjjybpkNsOwUUcEJgEytKz98t
VTiznEKLE3sd/MIB6BnDmTF4CCKZxegtQzuQh9jWvCCEplXvk3z1ukTZVgTNKsQO67Kwck734Xo8
r+RDwEIowVpzE6sM2SUV8Z9ulbIMb7LtdAUqibQeDQ6oQn5Cn2YxomfcHvBnG+lyMAcPn2EhcKTi
Jvq2Z9JMi3G5rpHbKUssJfL061pmCH8m4xncC9jmCGspmp7ME9Nd+D/PBwwpiEDV7Nby9FrFFQO/
vIJpEJ56Skql3aon0wWGBK9ToORm8DxMII3do75bY6Vc7fr50LWaf1ekSopa1ofWSxXX+LKVfcJd
MU4yLAjOwLnjYKCLoOzwyzB/rdmhpQX/MtsKK/7PaPNQFKjhg/CedzhM9IZznWkZb3nXhn3NaRwt
XCO6zPxBkuuwywP4dOxu9nRmvmfld0KuUrA2u8CAGCpA55sYyphLvN+wq1r+/36DAYdpnCo7bgfR
l0ygMje6CzymRdOxqJqrQR/mc6V4pW/n0N2MJ8pjuR8uKBrAZGt/T2oK4dHSTeKNdwQa9BRlQ7s1
Uz0VSAwQH6nXOmj2H7eGpMTCiw6JlSz9wFjC7FNpsoUYZtKXPuXMChaycii+6fXM0FR147IFdqOA
g2OQ9v/pBZEdZ0gD86vXCPkSBEcgToJZyg7VwICLpCwYgGzaFm7M2OKNYfWPqjtfOwI49TomtOiS
dxO1b8htFVIACM+Z97d70/uAqvMpy0xkgboumSGFNGBRkWLKtOgwf72ihd/qICMmkR7RAHEOQtY1
3Bmes423D3JaTOtsQuJJqCbUpQI8LtQSQbKVsELkCl+CKRg0kGwjTJwZ/Dezq6C4BDb28DMq5gX1
s5wT6C+DhwhyC1dVvae11ZbQtQTz7IsCEUHezQeDoEtKse8znUYF7RwoQ1BKIDxxUboIJSKKCAlU
7PI2RwRFyNAVB79eHrVGdfGWObL4pBMlHwOvAfIgQAGkv3ity6Mdx6TgILt3XXxi6HhnlXrMG8Zz
uqSx8rk+UhfCHBFOy0OANQPIBt8X1u+ehrEHUhgXl0iTIl+6zfuYJrHRaHZCmdsnEnB4rJWXHxJ7
XP63rQ6Yl15Td1q/TrrFvGuL7u6no677XQUZ7dXP8I+WDqxHbXFD2g9XgfheNOvzooT5lm7tcNzN
R696oI11xbZw8oxzcmqszHltGWQYdkvyqBmXNbBwnAWFGiEWAgnrR5t1GZQguY1djM4P9suTsvrc
HAI10LrAndkcdHhLP/5B+4/OpC2WuLoVwNfglcVfTo2kyJFAcXBtxKDfuNy8yqL4RVjpsZe1hPdU
R1+DD2lNNfuhE29leoicDqE+8sXfAYVTtXwOOMC8ymLrUPD/RRY3nTGIVpONtNP4ITYUchj+GqCx
Mo6ksHpBBqhnpsuTbfoEQyEmKjNC0YXFhqPau/VhXGQ/EELrEQ27KhpvAmF8yTBEeFqqsOR168qt
OjGmg/c6iLVSPJCR6b12Lo1+7ROQEvDl/UcLsYalhNFl0QwSkQpkSpQWzzExbaAiAHmczRXLkS6a
Qgq1QE8t4d+1FFFifz8mpvwrss+812YCVsn3CvWOSnrQOFL/lVHS9I1cbXYvNv0ADKFlePhBz8Qu
6wPD5ZZkS9kcDAgwTdb+cXA5QEQyJP0lIbRSkmX+e0ewpo5HR1C2I6nAjFRo5Og9owie+CconGez
adARJ8WvRpoqy9jOM5XnLu/u7VxAWAbi8QBe2PacoavDTyadzBgSR8YfgevzXy5VZOTFS/pF4tib
mVT8IE/9RBE8esWUt2KeyBa3OuLINw6iqnl6wTnezYGJLprNIAxoBwspmmprm+aFaeuJ4V0RnWlM
TlTBA4O/KxLrCjVFOcuaCTmjMajT57viUZZAVwFkKc32gCNCKNNIfLQ/n6IvZ2GNt1tI8TVoBd63
s/JTl+t2KfdDx7DmTpJiSF4YgQ+r3i/o8SvuIy3b8IFwSdCBg+8xVe2QWY5eTXdg8BbdrGMEmcKA
XCIFr8YULmEJWNCA8j6tu83xPfsym7EQwQmwHK4F5YjZam7VQ+jpZ2RPsxNHWZfR7EDvYsP6+CRs
MILuhQZ54QpU3ZVG+nfDtpJ7g2k+aMCx95Rw9yQIubr1NGjn4h78HacBmA/YrUd59tJFY+rGE4s6
+qyJr2SwTDPOo45yHd5F5Tr4851/LmjAGIgLtCF8aBsd7Sz3IdasIOSs3EMsshd/kVV81DRfF7X2
pSbkXk/xfjr2XU+Mjhsq9ah2E87MhgcAoRZbTDkWe04vqALjMcx1ubxi58fPyl9LZXjo7VAuGCCn
LzMVM9Z1C6q/TtlnoQpLGksgTIXHfJDsV1IY7RVJaJ/BwNOQH/kT/yoXLcyVawPEZEserJ6EkXv/
uSCrf+QRgMQQmKwoBFD13ib153LH7Z3UNXKtgXRmwMNrblRhDZq13nD6zIIeUVOaU0YBWtE+XP4W
yb2UwImAKksyvMf0Nn/HXZgi4wzskGVSubjZtHMPTYfQU8PjT91eV2b1dwLqriKqO9u2WaGInayS
day7tbU8bjSZgJyyj4J1SYFRlUVfPg6qy4lc/WV50msIE0GU/WBSotDen/57COk/RQGbmAiLzGVN
7hG/xQnyCjV3jrlPzsF4UekrQNldFxZasneipES271lE5PWic1ZVxdE8bIOghSvz5WILI/Nqz1sF
a4A7zefxm5+H/2QCE9tyDbQiQwUJ3e/P6vM+Cf3kSCOgYrSxJc/VNWcuNuDeos8eIy/itIv4gL+9
JENnQ1xlSvNQdhvL7siPbHPek2ouDCEiFwUpI28HTQ2rD19ryXNoDBcG9yl9bryhgxv3C18Qm9eT
vOhvFZJdcXMlX50//DbjWVrcKIapuk0mdYj7BG5X3jaXagDifnnaID2muL9Sc5qdmSDtbpLO10Ep
lefhsiQa3OL5MM3t6KLzITvlWO+/EoGQsRF/u+WFKBFpwZUpobPUhkgLducYIXZX6ACVjfQBw6oE
QgV5DAuB56a5/4cFPIgm0+BI5DtgP7s5kGSb9xk5f8Qj4kjxe4cEfqht1hw6lfB5VLHCxTr3tXEP
92A3RC2cODkcr1uydYV+iWV4x/IWmxU3rfbLwxw+gOvbOr0AnU5YEDlc/Z7mOAWj/Qlo5mwiKsJu
lCbwFu33h8Eby3b5X9Tbpt7Vr0pQbWrqigaLwg73ViYh8oDDhxf7i9qwbzFusqJtxqoKNIJ/3uNW
5SDWtv9yZE7vYjMZRtXyjNKhwIft5aIVGAXicsNm2imHgGED83SJkYzH1MdRju89at5u7FIf9oRq
yDyxK09CSXO82b1a106nkm2sr4nhBBLD2M0OUUW2TQHAyw/WYuOZToyaEkbYFlbMJ+RPb0+DEIz0
NOF/e1XbpwZFPyljhuSRzlNHVoUfmWIfo3+9PM2dMOJHJxwjdKDmXF7nISKFf6imgmNOyLEIcvl4
kNzWkUvmY+LsE3zwInN/thrIbO9XrmrbIODdXefU9iWYqd0/2eXU+IuSuVD2/LZ2G2bxca0hvKbt
NsJOfj3akAZzuSMgR9IRriLs9NTzFB7BqG+kchgn37lESHObVaVtcHaxf5GXCuhVuu9ZQqwQg1bX
QH+lBrFahbaKhYW4CHBluWMawH7HBW2dQEhX3MyH6MHVylYk8UtyiU4BHzBckFp4NGRm99Wkrlsp
YpoCqbbeH/Wmnkc3U/8unS7oNZNjhgBaylxQF4ySkMu/E1QjIdV7pIkvyeP9ccm0CeZfFeuNg4uA
qBxKk3VuJlFUzeoJSBwSzw83WrIxlu8x11wY2LQU8G/tNETTDT5qVPiWfJ7IvyrmHcs+m4JAaDM4
p0W4fFIjYerAslgSWPyHq5i47kDwZwt1VML8Bf8SqGrWnpdPCGMt6n82HHRlJE9LL3T35+Vg8Vuu
STtQ6P/zYb6wFziqXzxdjhg6DndzRIqT4m/0B91LFidp/lZFxiPiqRPONEMZSVUVFqPGcDhTXYpk
TXCuvhtclfDAM3bZKUmfNyVkBuFWYZMcSBL4Qy1A+oF0SNcqQiTbzImpsue7sJcC1ptqnQtS/N7d
Jjv73ovOa+dpKZbxp2Rs/iPZfRLGBEwaKQVeBl9/uOriL7ZC6LsZ6KSXhnPRRua5dOuajmWv7WSl
bYl17ErG1GfoMGpC02kzp8yQPsnXKykNMiaAjjbN/2WzQsACIGJ8Vl3cqPGtPKugrinOuBSOyjGQ
0K6WF4gvxYYeySjoLLfeoD2smKvT9tmcFtEYBjMjiggvfCKrbgYDW0s09ySpRAs1gZOrfnjav8yL
ZvYpdAHRL1V00+W100PPzXLjE2VaP/hVgAr1XtfsX+p7MFZLhNUycDCPN1enXGNdvfq6NP+ZHJ7I
vB1X5QGwL/5F0DXzrT/wmHXM/FQ1TyxYiL0TwxQy+EYc0fjgb4qg+KLyV7YbXEcyWlcP4viICiNn
Bim4vdwJVrfkwS+dpPIMMj8xvp/cEXABwkA7j0CUft69NYbC//BSya7UnstkjlG9RcuqtOyuzLxC
x/hk/qLtJ5QqvpK4a879YHfYoNu3i8EzdUldGjXSjwTfhK4BaW89oPjUKDYta445VCrrruXnFA4O
CvlVpEA5tA3O0T4TLiYfSEGEMJ5Klq0WA2aqtmzwsgLelO4RRx8g7VtIYrhPVHGVSBQRuTxmoXef
LR4U0jWhsXSRVi5rVnA1AJJ5CJ1/WgwaTm9pcHv9H56pblrGk1dJu+SKpp01tw/ElBG4SnbxTzjM
6wA4/JSkYcluJ8RJ36eKKCUzGeesk4RpdicS1niiGhBcQ+IdKObTuKVtdpB6kdBGkC6IpO8r+hry
w8mKer0dkKR4qet3wYIMC4ahWCBelQeH5oKUCmC6ut4HBXxL0IhHMn0kSmFai1RAopcMPjY37Br+
fAzRzVEQVCBPRn6l/x0awoF+T53l85Fpp3Y0tG0IrD1HO2vK5ClfFiRFNG9sWD7wSVVcli2aS1yJ
UpxtZ3GlJMbsDU16gPxDN8R0Q5OgR3+EaNkRrGG2/uss8aC6hbRMzk39yV2i1fWZ19PMbc9Z2gHl
9exsUh0FUeCorWkizn86OuhpyUW5GQifjiIm6aIC4y71ox0r3zbToZOx9gIFsSIRYHc48eI9eYNY
+Upqum3eNXelc3/o0iFcXZikiYaZl6eF2uJU2F2syilmhjhJ50pGA+7g2ocDKsmkA6Vd2fR5rM2Y
wG22sxoree5riCVAIZdyfhMoJxDgqYyX4Sx3vRSYIeTYCtDXZ84YkR0TPB65QgFO2nl+zIHHNO1S
vwMZxZTlGEN5HvBJqkwGTbHNA5K0xrbb6/BcoScpyt6HgieSHds8mSXDGR/B4pwupcy3BZYFP3xZ
5OajzAxGcB0KnUi9mFis78cPyU2T3aMfk6oHXNGaeGoFTCiFIK2yZ7Jwnp2zUiR/y8n+4bWQfxjx
oUkjBICVNz25fsxvX3K+qctpC2ZarOwD10IrRyzsUAtx7LXuI0nxBE4lDJRe80m/l2ORWuI5KFVh
9CNw/0xrk5iyjLie1PR44d2+ldazQ8Y4MexkMp1JmlN+luF2RMH1I9VHY+k4pa/VGU7rPEO13ePI
lQIY4SA0Tkg2Vpstw8Dg68fVup3cXz0bBBOX1f5bUrSq4z6jAMA28iv4Z85jdaidXzkHNoaR11BK
wYvA3kJoadmnVJGCcp/2TeQLXm7YIw5buO8FjFOg1e+PhKZo6AVXQtlbRicUPD/t8H4O1B0ljpb1
Xzqy6VAxG0cbwoSR8LIAuv/OIevLGNWJ1HtNJe581YlBltSj7AMY0znAp0jFlZgA7u5gwsdCYBS1
fCxaeKFiUpDmbpObbSG2iqyx00qXCpDWKF7aM72IofkiroTffejDhZi0TXG4ZpDEzFetTfRbnekH
GucwFFNAzq5oHURtoK/f11NkePSJ9Fjtc/Mqum4TVhNCaTEvbXHMW5Qu/0LtVBUNjPQBxBrL9r6m
AVCfH4lYtDGC6+jEWL5wctv/awX3+PZ7Z6e6EXT5qfi0kjpFbE61P36BwY6vCzMFobhZXJTyucDE
psF3kY8zyKcPoyawChNpZIapNIlicmFzOAlZnYbM6J8fEvqgXfF1r2DDaVS85wCyiDJprIoF5wY1
QnEncJViC+6Hyrr+2Gh3DF5p2efCgwN0Cx+Au6bLrINj6fyP5jZmdLOPWGO9Qc18iw2mPvmS+7UV
yvyznwIheyA5qwgNt+Ad1HBwJCamnfLsoLm3Gmr+oabI7PInJHqDDq5+p3vcTbqbGwU1cI3OrJyi
9OoRmIiA0bcbZppKx3A9ogki9PkJSJNTSIjA2KaDZMevNqsCajnnyc8d7CATpX0m1YEyDEQW/qaG
Cp23VJnWPS5l58hFtTF2qgyBpQJkePd5mGFuEP/3suBphJIHpuvJiXMcoVg9hap6yYAr7jsyRHg8
M5JJgOk/OoJEXZmZqGgsss0eerhdQ38XThm7hR7N1JhlOBi2zh299Lo7Cc24qufb3VYvKsiDowUB
1/hUDsQQ0L7ISPktKOBQKf28m/VZDH8+1Q1d6wYadHnzJAOgFul+6BZobOKyUPmQm4H5VUvTLmbn
gqTgFU4xwIR/1IrXFRGe2P1OHDqENT1vGHhgFP/CqGCQAMQVbDHCKEulNs5Xh7ZTNnGf+xJTZwuK
MostmZK6L11bsD+pb2rx9R4nHfNtgaFiOhkbGGwO3XkC7eK6+ybZkMXIWjRlJtKJ27mj/cfxmRPH
f5FzVH841Ba3LwgWeKhWL1/zQfLlWQCTwG5dqYniQXWaKdPIxwtd8ZbqGmGJZBNjhU/unuBp6DlG
UIQ/pX42ch/w0Wrf5GSNwKiNF4MSV3mdiyPt7H9aRQTjHc6LgqW82GoIC1Ugkk1WZsXQwAQtZYkE
+is52Ie3P2U3oXA3JRzuk1ymVVwMSOfv/P+JuOwVMFLxZxFeASPoa9/1kFJSdxI+iDec0Xgt6+/t
tukPeFdmlPn5AHwuuXuZIdv1znEbTY7jEMvtqqTsxaboZagAKlKx7BQsshmRUhFrJQL3IRVDW4G2
RErUDw2vPRewl4OMC7CNqdyqw1l0R9v0//CiN/cOf7/1vXuIAvHvRCzuPmfyH9k+UdsMCy6ERtak
bjcepoZH0RKgOy4GxN/tD+8P3QYRfTvzQ6X108gcJqR3dg2TW20zjS7HBK/xWLYQ0/RSY2jQvhgF
O3fbGPLoZ9y6etJI4qTaVRDkZn5xldeWag3lo00UbT3E1RKm9xcJnmE5bbRxj5xfAv8uk3/ypH11
sfuKeiDwM8CK0qWH2lC7xBdmuC8e8NPO6D3OycNY4p8T4+6JdSiH1eSqXYHANuKpUCFTaVOHjI6M
qs9FjuFYEswEpsasp+7wQaeuqkNJDof445IKsDTv9MJCeOlQD05pi6AUZBftUr4z+kRFIQONUOa+
z6omAiAktYKQkL2FGgwIp9pEMNI8kshr2imJHNKzKEvt4ko1cWcDSTs7XJfxgQ8j5E5zNGqxDiHc
rTIqWeyFGXCWTkT7uVreeXjJSiJIFcu0qA99GHT2rxdXm4zstSNQR/snKQfOulgtlrELwk5KG6+Q
C7IXkq83YtfCUYlA0BVvSNzqTG59QIo0jpt9V5znrfOaYEWhanCIkssgm2VyknH35kAkhvtB+F+s
wOARh4uXO1SeBbcs3CqCVJf3AMsNU4fuch3dJtbAz82NHIH9pNLz3HW2rq9K766oUikvU6WzU9k0
UWquTsD651IBHqDkm8/E6FmN5FxH6UgmYeXwaSxNrejy/lTo3/npQksLTatFDCAMCKzF21nFiGVB
C8CnVQ4KXD651TmLSbx0itfexL2oMkD66bPwjcQq9lqmUizL94GNNQ3I9nHAGx2IZaJm1S+0XHcE
/1BBXc5w9BffnCFJlYEK0CJWWewMp/rTbskrHW+521aHcbD0SyPG1g3K5M8AuxxcceD0sduPq9dv
P6w9t60mzok7eNU15eBJzYWbm9fHqkgYu1ob2OLRNmOK9/v02kEKkRzr46N6vMXF2hkkYpOgj8SX
kwLqjdKN9U5alj8+a65b4GreGmgnBqUpF3YKY5gTc8of7ZQPKkgWMZiB4fayvBmoQGOJTs4TlxMT
lKrVClnfeRHf0MvqK7huSVWzl14aIgJp63HcJU9P/2Rlu+BLE24LzyKp6fW5RluLPgO8WdQQCBwr
5HWQ2Ktj0K8qPuWgHTCY1EEz2IZXvzys6eaiAYZ3Oc7rc0ZR60U/MSZuJJdxyTZHJoKG6xs3cBJ2
WWre9WtS32rH62YRsTeFCmTe6yarVndFyEm1j8BxtAsDBQU4W9bkkSOmYFCSrnk57qhqoXELeTwk
F6wbsLGdwQrGEH3t1ldDsJ1qOa74gpTwLD3wIoi2Pn8Z5HNdWQFFOLYifmvdrLhS7VIKHkWcCtgB
4DNGF1R11YOipzMdkq59WQUQ3DPEOvFzthjibO3T98A4grLJRYSA1ahdcls0Q3urPTMIZ4qBWHm9
kkUFMtxZFRKtdkmy6ZI72cMfj/vvg+zWYgd4k7lco7UKta58wDItfm3Axx42iFW3V79p5nibUD6x
3PMyiGScx3GYqRXVUAC1akldgIYICATt+zsQpEQ0a1JCaFD2uhQj8dxkRjRYdFyILY4A9RQDfALN
RmQ0D58eo9vBiSx98+yXMX+/RjEfl3427XyHflwGrfFdscUgRcKAEPhpKD+k9xC04eBc9WLp8VoG
lkWjaRxSt2uD1dVx4VSEqeZtM7vUN2S1XKzA5Wa9vWW805FilrElMbcEhHZIQvJ9bLcFfXgObJIR
qaVIt1tm2u4p3L7uFDtYaPZ/+vw+N8wAWcLcoq7qczHT/TmgSFtj7nVdW7rILH4Th/GrNLZXz/9t
tOpcF2aEg4rXtcbhWoqBOZJo1jG6svB9doP26Yp5nB3jjMdllMY0uASkLwLYzIX9Yj10Y8+gOvUi
9pBfWYYnDf9v1J7lDDyCYl7jHX+zU4fLRlkMNJOj5auVaX3sAtT+OEsIX4gNmEndm+I0zJl3ivUo
IgOZ4inU1TABiGktZvP4SxTElGnzY3dj6EbU7czn2Y/w5MiLpAF0vhvvdquqQ0ycy7szxIKAIvU1
kZ2ms+kJp3qbcJFxlRKKyB9jFec6UOquvXs/RV3WUc5O5z+xoiV8YtWGjOGWjlR79Xlna+G/An1r
1vO/eK/cgTdh7LK57g/Y6ZFHag3aGN4n7nsXvbm2LMhuFORyV6avSY5zJcT5uZAg8t5z6IXhMmRL
dZXjZ2cIFTCz2SKk/BseMuxXvFv+dnwzLZNJUTnWPczuJmcgbeTHkNo/oBnRm3d4rbZhbarfsISq
SkjqN5/ZIwDgeAzebw9QJ/JUkP/tuNvUuGsvPLCjpWLsy3VYkGTplAYwXESchwnCr0gKqO4C5TVQ
RAAiB4/BkY/eL6C86n3xTK2GMdFnhpwk4wDTniWZ+yhkxldOvQAeDfVZ8K4C7FVzkawV/uN5KPRQ
9TxLiHXAFKbevHa+89qBhUmElulnsiyzXq0qtPtHThapLmfsNsLgS+ozAFLmjrwvBG9tL0sD5lLO
8egrb/k1hX+tTdOcpVKJvdFrlix5J/k0kOKN/YAUC4k98+pr3qi2OQztLyEk0UXFKEbQGae/jJ6A
7ZbNu0OxAZPfnHUZhSCqkHHHlV/wGJ89btVqMdVtQMBuISMf2b6z5+yUdpIIWEynQ5jDfGVCe6JE
da8919ncx0Wc2CARaHT8KAVOysO8J3G3zpwBcPeCZm1p65YEs0G2GmITqHtx8zE4lpiXZcuaZLEc
0DrE+t5bqgAlEL4R6+4qMvrS+f9Uucs/qZ4XmQLesgbuFCfwths4jQaClu+R9hJaxNlmscNdboqv
kPaKKrHJwi8VwlLjgr3NhtjvTMuIDST2vFzNA813Bj2TwdUQtb6bBIBtuMsQvJXgvYT+pKz5Nm3d
n9dhzDYxr5a8yhJSogftnXj8YWA+lB5AzO4eJWKpsBbr18mwR0ubJaujPbDjrUgGrWgmyfjmEofH
K8EolgBMgR5bnVPJN81UjkqpjHi1fbnZukjniFVyu2PPKPawqy8wKzoSQ3cp2klVnBlAIjtDpnru
2L51Im7w2f1hGxrVAIJBHbDAEKBfxI//iq5tMmhbVMorCWJNOxQcheyMX9NzylCSGplzWPLeRVuo
XjrUpZFi0FwZ2/dNVZ8AXwTtHw1lv1lfVQLAq+/wXcDcHcW0b96DHu1mTkLMeyeP36i+veXOBtH4
BRyzCTKJhK5MAjuVHJ7xAVPgsYEOWT/FJ+fUWtXGI0rQJLrIFWTT43QIJxuqPJyJRxs8IFGt/S84
G8d0SHKaU2zGx47Q8c/P+W44McRz5+7NwYIH8heru2cKoruIyIcCMLmBm+YlPeMmj0D9QFwwuBK/
yqVRtsjk9sHjNvyCUXrLY40nMWqQJ0K38QvrhFtDKT9WD6cRNrd1ESNMEafQ4016W4bBdRf71Ci6
4vIv+ZGWBeKObmyCQAakg0KJiL2GvlRnnQkq1IG5auqSKbTPoWV+ceZ39lyXzoik15Lbd+qOgwlx
1zCCjgBvenlaprQUXhImbpx5qVMmqUowNlhSlyr4zGjhiuk2VufosBpHbRQkuPVAdMsPAn8YijfE
M8nZVgcq1VdYhTN58CRP0WlZeZTxiOFXHzdcxEeN5IPUav2h6WKLImlLpPtroIxQ/9Pconts0rJi
P8SwM2hRcBABXq5Tk2VHe2eBPrLkRkzyuFHUSasnG+tXHWda/HHy/sDd17M2TWb2kHQSRyY1bYu7
hOFtCLJ9MX6BiKCvkIHtbO6MzIvaD1w8k/TS88Uxl9NeMHtGwxWe41wHpr3ABLiGdt60+hcfPBj7
eChnNUGmku48l8NUXmjxZIgrp1KDch5z7RGQUICNZPA/LJlLBjXxebE/T2HTuoHuWaPmF6g4FokV
v1DmiB1p/Wo+kz/kmhhyNgh2c3nhKaQcZ8nAkIFObEmOqqpoMw8JilnE1wD3IeW4rjQZXTCv4TWY
HrGLAXiYAnMDgl4qSeTrmztT3/MM8mNuzIiZZWuM/oDj004Pg8OKRYCXbPtu5PbL/IcDCzP0HmDC
fzCYZ7oaEg8LLbxL5dHrvXAYoQWEOkirpWV7LSOJwweNKwtYGOn8ZCpoa3YdKdhM8uBhvCJI0dnY
8YwEKT/Zhq4BBXdGbVeMWnTEZVFVmB0uqHuOUUZfDMTsHHO4m6z8idGjbsL6GqfnhVZMCk+vF6re
UZnEJ0KyLqdLkgozOe7LMgsogSWgAeEJpEnRVEATL0D0E1JjasAM4OaPCMjcMCZWLRzrnrr6+X0U
6C9G9ViE0xrzlYhpzZaGHXho1NHYCVxcp+hjVBhiPLSv8TIv/7ssdROz1u6kNSnMH1pc2OvEKf2b
PVPH4EicSIOTosnYhLSVT+fkDXm1YkCaoZ4i9D2dIk9cnXRtizT+lLtjRqO54dshxkeiSzDfpSOR
acQtMBE9IRh5/3DwlRqD2eZb+s+XnZUdCZ3qeaNsK8A/GnNAbQtpZevNWW5kDJgoPyfnmhU3Pme2
UVzwnjaZHCciGsZ+qKOA2oa0CJvCJFDkZbxdUz/bTLA8GNrUTqfILOFWs0NuvEGkI+VjtQZ5is5i
8LQpZhyMLOhViO1f9hood3tcYv40z1nzZJ5LCk0Nf+eQg++pTsldKqY3/vKdhykmRc3ybEStmUYu
tzK2G4OevLJJvf3l9xNL1irooO8YcF6UnI6QxWMIWbaisR2pr6cys8CmdnBDmxxCQ5FLzpfiQq5q
JBNUYFCsYGzP3nLHt6tJy1Tj+LbTnXj09LPvnaY6X3irQ3EHeBciHBb89tI0g5bKtCTqaPYtVkZi
uD0FHrqtPMxaMm8zTbG4P9m9xoNIcL/CjGDrYOVdLRGfqnB7776Qs0j6GLo/LR7Q2CVeFCFRtM9p
5O3SmtjvNPru7GBPJoGeiwK02q4yQg1wIsS1RqME/bG6yS/98p4cjM4gJbv54bT7ENOH2koat/Hf
VgKUMcONqGhf/2D2hs2NydT2sebX9qIAvmGd+kYM3ZXYPDz5gmSgPdSGqd34Ch61qtSPrFI7zYVF
dACZVCxBuqoW96vjS0MGRvDzfVnrg6SoqZqSV9Y7DSTQSikGRpiehuw+3tjp+4LA4QGy4p96YraB
3MiIwEaTQ2P5PrJlsPz3ecSkbsunqL0RHD8CBdCQkun/1KuY5ZHpEW1UJ78DkGUHa1dBjCw4MrDJ
vWTQQuOU/MkoaiaH+CxvYyEOeGMfBr52NJevjTrRQCdrgTA0ju4I0g9s0tV8nlhLELAtGH1J9gQD
UYifk0d0iOXgbD1w3M4FP1B4PsUWz+ZqiIYhllG5ZT0xySZAO9ORG8ottIjHR2ia9BL3ak29G2it
nYclN8bEv1s43Y5gzhFALIwWjm3GkXXYvhed8vlh8PgJWaEvWPE0YL9MeURjYLqiWFQvtuoyYuhg
gwiVaOn70L7+xvrcg5oc0cjNfgcohGBv/TB3ybUTXJwC4WHIcZqMZUSvCzH5M1yBmRqE89Vr2PaB
lEAIGww22Xb3qNRDaUyaBZNFkiRmOT0aR2KXU+pelRH2d8vqltKZr/B2H2+ukuTb7s+2OohDZnIF
84gpUSw3w1A7POmvxELtPz/A1KS1Aq5bAxVyQNFdAb/DNKFI/1FQWfMaC7Iit4drADKfOgPpuIXY
CysMvvxN+/KC0qeg062fIGiKPzw3iNAeQT2NziS2hkxvKJ6oF2kEL5z+Tr2eTTRA7jcZWx/rlRpk
rz6V771/L5KlxY6rPtAAmIZicu4MPYasdxMEXDh6dkSUytkzt/fcJ6H7hwP4T0ekNMFkyYATSZpd
4Cp46w+JREx6aIwNoiFL1q6ng3CLS88Vu7aAm6Gu9Lef11BOF892Hc8A0xwi/DmuzrmwFoAd+NVA
ifvU2LO2fcs02+VTuUisVfgphCA+KvXjF81EU7ErtiwMEv0TsKdyPkOBbOxWhtzvUDHSB3znNwdc
yDG41fw/f0cio4OULTiwNeAJJZsvy0W6NifXNv4LJl563Vu2ecFbpWpeZyLi/qObfVcvt6bHDE+X
IN6l7mcDZlZRQYlzWmTrTRfaGzAUxUwuHtBR+FOkjIGYRR/5eiIBAKkBe3AFJIedAcKEo/+jr44g
YzdXxZ8Eg2PE4lSHKKwHWpcOVYEdAHA+BtandPnNV4KNEbzWLrtrIsM83ZiN7nz2C9gz6IxaPn8p
ES1LLdMBqrXNpdiHzvdsuu4OrxRwCj4UGEe56kou4aez/sS87p1SZKL4czyf5xwvmkSL8WFIhfiS
5SrETCfUmCrIW3Ind1aK1SFTRKiVSyNfTldEM/dECNjIhtGM70J8WvwqomhSirL2h5Nc1SNuCotx
meRH1Tis8lwylMYAAP5QrpiQLnPGaur/ulYXQ5koY6MGg+38CS87q9+CZNQh4ItqjccS5rMafM19
PYKcAJQvsF6oNGWzrMwdb41GD6QnhI/XjpvUH3aeGzjzp/enEU0i5V1id5Pbv7F9fI1U97mE0Agq
c3Ac81Pf7mG8RbAuWl1TKyUY5XC996W6PyjBZYcvnzhOu4hO8igZGw/uEF42MaPfczEkr6/EdM9h
dgtMv/OT8EJ3LjNYrAlbShRdFnph/mMZ3XOlG1lQwWgXl2t8tEDuuTXexvNFRoHSfIDeV0p0zyMN
DczdhUPIojyKhCQYFQNXvYpkBs/iBLRJIZ0r2SaFh9UaiHFwp6fmJlOPqERY4hEjKIzgM7XmEW5a
LRUrxzgh9zHvNEIQ/0yM2ONbLXXeAblm4mjvae/za17D9Jgx8dBD2Gb4BmJXgbhT1f/aC2Xt1GKl
Qggmv9/3zvSk9anRnu9UMZAFDO+PiTUK3Q6ltMxcPdHo3vNpTjQ08K+z62MiY4qjy70etW2uVj54
wv2F7pxBqEPO6d62YMrSE8MvYXG+BqZFDZI0Yr6n3exc3h0MgppvTJN6jKLz2txYlnxW/P51KieG
I9DPUoQBCTvXrEemwF+DjB4dGn2QeSJTiCrhs0j6PKHwd1dKDPmV+dvjhAYvzjr/UcNb0OhHX+4e
egu5rV74VhFtalU8aMQ9M7pjhR0Xee//NrgfzWP0DHfXOPxeSuK5FV9DLVfxPeB30Tl5y15JlVkg
oM22r0wZL98xCz4U2GhZ+YPi6uC7mGCgHJDnA9KadYxVV1cyg7kTaiiVc/KL0iZqY0RyYOk/bztt
jH5LmmhBHkUtnajVU+K9YngbJqaIi6y+7wnGrPCHBLf1EWMJyT4gQnVdIMBjMxgl1q7vDVrPLU+s
VKvWT0ngm8Ur3IGSkEeGdNTk8Ck+YNtAmd2tcRrrh5lUbGIDIf6U1hKilZKcgOizj3zaIiTjI8m2
exckQwfKzPc7
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
iLOC/zM7Joxw/7u1/3kvLPf/gE0DI9AX05I+qEOauE/7yu3hZQ/vW/F3DMobAlAfRXjv3r131UI4
xp3jO78wPg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
KVI7kykeCSUX5fBocqQpSGyifzzNp8Wh49gB3SY5aCkcF70ujPDG/9hKzVEDulBUoOtbOqYXhoJ6
cDn5xn6BYki3kuRcj1mZItS4T8QaSDgMTEM9Aijj4k0hN6ZLETGBDBJKg2OZZ79WIQrCLm+Yp+jA
b9eXqd54dvp4eMuMoF8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
qYUG6c35gMmWOmJ0+Jjb5OdGb2PCL0JkqR78MmUYY5UoyvL3BwaxAiIKYYVkJX7CEXshqD+eBNI0
9W+MVH7wRTJDBCk6PMcmsu3NeQu2XZMDibSGlfuAGYgFFKMmAwU1iWlGD7S5ZAszDxIG7Hsub1G3
cGB12cyCQuhcHZlpZtY3OJmIyOR7T+UzJNJFbx6M7i6pUZFQbBnvjcLm+HX6NInXcmNM9wltRgWc
QA08ofalBcb/79RDwtVfdkQDfNV2q+E28Pw28JJ8iQGzaRuMeSskaCSFhD8B7An5FogQZOgaxqEO
j5vMiNlwpZqnSG9tOie5RYD0VydWTxnYXBO0Gw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A+EeNDHsLpmHCom+HasfIuBBRE0S3bFCigDt49+x3CEwcjYWjxIx0qCtRtVq7CI9wSm/Gin+WWfG
91dfuXZp+eucmiP6CHPUMHYExivhUTYpZBeDxxcPgEBLzUE6gaaPNLKU7gnB+L6RM/V+crK209sI
xnRl4bgcMqLIseSvXtU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
AzEbyYz2+7QSiim7WpYfcDPoQjw6mNgDWG2fArz05h3/f9vy7U+kvSbnU76BD0mI/hcdrW+NdM0u
WayqP6k9VHNoaeVq03RU2UxLJGfLG1pGdUvSG5M3AoP6lKe0tGtU/8OU2ukN7RIIxnFPT5zhqDZ1
bz7Mq+GC7cYzUWbYi8FRC96SdwHeUzfAf5SEfMfH+YvrY9MFrF/8eVGfIgzjjI3MYGgC8EkgyuWQ
D6m2kYJukFy0EcVvneNXMtGT5lTBe7PkgvpUw8UjK2OEv+w607nnaO5HDvgeARyB5d1AhXWLn1mj
1Kn9vGxKm9guwUGKwthrvkUy4jU1ZgFIlTeLrg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19104)
`protect data_block
U2sqQ5Qkdfcwvu9O2/bTBoNh51zIYpjS8j7C3+fMQ7h0wN0JOPdBtyrCfdE2QfLKv85tSc1BegVo
KBVgvvg903b+N8RMX6uz+ksO1DPK0Bc/G7dtSY1RFMIuhlsZ0eGDXGOOVLLlLPpqcbIR732iHkNc
ei+L8oALEVwIpf7+Qyuk6wz0ALJ0rUD+vqp5hfVGyYRf7zEnD4pweTWN/5IJ5K8cUlnddKFLIupP
mqyWRXQjL2LI0oXpyGrtiKCxgC/iwu6a7l//KqBavg9ZdpB3KYc7ss1Z6GnDCoDwwnAeOZAJbQpL
TM2Ygooepikxl3TS+SX8B6yHp/EmeLN4AbbYyuj4cEKbIDpjSNgq3cNueoypY28/Cw91Dr+g0sk0
m5COCkkhSaXJoIkDP8M3ien6i5uCbQ+edkb72Xpo/uw9LwWe2WgIOHHl2q42fANP4pBi8kI5GUzY
Ow+VZbdwHDCcu/+EGN/wnD4E2bzMF3YvipqRZ4+dlNd1CqAV4zaz9jngH4lQi9DgsER7IrhdISKI
+BkphY7K4mDDXoFmwUCalW0/mK14Krq6D6OAgPOupHgQM9gWSCK4NbCl/BHbMYhETWBXKSwhEevf
0ouMElCCDzTQPABImhtXqp0+Ln+EUi5+ZiyhaScNOArUaRSg2A70bOnkwZkpKWuIJ6ekYvdCLEFx
WtpqhxsBj5L+w6eDX3cQZNoaTePPN/dvunXBNYRioVdg121U9CfggaZu5m03/zO9Nr4S1mRfPH7J
MQ9omi6giypyGXiNukrIpYo5tO1sezgM7Blafx+9qKOrTcQaeUS8KpQXXlwupNB+m7Ons2HmzO+F
zv0fetMTignnAw0uvTpX1odtI17TGBLg2kmb3vbEZKMXibkQRWWKGwXaLoVaOZuRpMY+PDj1VKUO
VVmboN8Jq+rm9yFAaPITFpCgz8tCBrT1iufL/yHSqCau3cdHHzNB4gCY57dHeIxBaGHBVz8KITj4
DLp2qbT1iRzRPqWD+2cqojGL35hsk+McJh/8WAshX2O0ECwWRrQbsXSI+xjLn4krEqWEA0pIfZWB
mrZ+lw5/INBGw7JPEozScLYfUvV4NKT769e44SZ6N1ho1aHDI05k15/sozEOhZLYNAnliyrQBkUf
ir0deJGlPH2XyOITsVckllAOzwUdAQPqceyTMjL1OsYwe6uMe02izKLensA22wrwVKH9n2aclzu3
Kdog5Xju0HxfHqeWWTFsD0bJs5TFYI5lKKmnNMscBKhOiKt7UpFTIX3wUZWHOUQcMPBudHswP1Rz
XD9dXP4vUYviG8STMAt72hjJgHPqkM7rN2Mt8Lj+6pXTkLWVNMC7IcdNmSl9GFwBnTvv/7sjJKnD
QOvKabzUW/boM5vdcPU8iOXd5wev5EiEv19KrozoWB0H4gEK2nlym78UJ7yWvXZvV4CBpupp+ujY
V78ViKjXIvIaFLvnEhQtgb/4RiGerkSqnveTYPLk7He+2H3Sq83zT6lIO0L0Nc21I2Uknrg/gGsN
WdDFnsFWheAVTj20SWOBFtd2Gl8Dp/JVlpCX/3jvSKgF5AGAHUhS0gJZGLZZiymY7Q1AHbZr63sj
QqWvXavs0xlIJAjDlCEE3iJ7sE+C0F96O1ek9EgE9Y4V+UbuSqnx2AIYHVy/nD6Qd7k+JsFoxhhq
pXxJRybnHDrVks36jKM9SCAgPX2B7nGfXnR2UuCU9f5dBeCxzpyLTO/Cv/Iwcg/C8Z6E0X164Usr
T0a8As85XgTJ7SvhXSKyzoX+6ASCtmjgUdR+MmnN2LaDeFQBzdjKlq42ulUAN7hLBEoqFzYAnJBA
7AkonwxuWY6GK31wy/tatnbwcaB9Wg3MFlDfRQakcGMRB5+4UqudfEwzHFW7zY9sBxDQOVi3cVxY
lMj0stJmRZVg/jh47vWLkb6nPfGL01tShHouP/JmBUHO0ib5JVGGsxPI/w5ZkS012uA52WWe4AqR
aNhXBT/Wj7xly1nvj0d1USAfNDiHDeISRI61MXMw5vbg85KGPdwmz5E+iJGZydtlaPn4NGX3klxG
NZTqj/PHYizcH5jxsyeLEPUwnlPHvVFAgXl08dpCagKsPCRGGtLUNhvsc9eqBLvOouwpZL2+zEYT
cgA4BRcznT2Jm//EZGihHc/TS6ZZjihHBNH+ZGbu+wWcTgtrodj4qEf6TyCoR0jvgMX9RmQn3if4
Q/NyETOSjRzVrQWVuPmJnKs9etxfSlESgwxhJ8Ba6sAag2nWQw6QCyJ8iSe2Uau5pYhtJjwAxCQ2
zEVnw1i66UUOpKAY4w4kXg1hvi6hdcEfN2NcH1tm2oZMB0BZVRlAEMEw2WLQR5/tTkOWMdC9GzNg
vX3NkkZAiq7peuNRFkq9+K3TvrZI0tEkcKtpDYbyexU3cC0WzWj18ES5qfohi+0pNXS9Zq15VPmP
snqeR0mD8usuuj0+03rfnxzki8CfJFRhMT5zAhpHjoDhZ+gPp030Yet+gAqRvjX08iGKNOXUy/So
0kuzLpOY2V4idoOcmlcrwkX7z8vj3NFOQrr8taKkA9yjvFJ8qWaBK2+8H40YZ6pNNgfytS9uadvK
iiBNTmpWkWYfbTJGw+gniuLQSXyzrm8WkbGc/tDr9gygDQvCZT3fRlSdQMCwqo69sIYM6gkSBZSP
cah3ClpcUoUkss0hrwiKKYUpzT1PuicD2lVIDOlAV+Nt7aVw5mElDXwwV8Vb/hpRVx8EqbbpeIW0
kUHdZc3HgPsfbNg1N71zRZgHYTEJvidEWkh+PZ469qRm0XbO/G5YzUxc3FA0cnucG4vT5n1PiKpd
15MHzsd2exRokmMpLb0k3q8xP/Xr9mokDnFT1hu8eNNL18QrPNIWrntez7ZBJLcX6MmgXSLgBjEy
zj8rbDLpVPIDLb7zFB8sgbJtjUa+9bWFQY3AIEouuU0VY6ByqgG/EpzEbfE0riAFKnwNLdgZt7yh
VU5UhDItVDgqacV/QCMriSLeQj4ScWRRf3GUfQb9m3rg2X52W+uV9kKofy9Ecwbvrf56qMRxf5So
BS4G3WMWB3FW2dvXZc3vdU23MzKP3gW513Bwr9QkYZt9sbQMCVtCLt2DkugERw9mnh0814ew5KB3
Idql4GPyW+/LvSky5sdZhXgmFEv7y7E4k0DCMBS6L3qxEysEl/SBpW3bsTqw5QNuauTqfeU07NeO
iwk2L1xfiBv2NY5fD1cGw1jkdH2E99KKjNSvW7em4LARB3Q5J/uoXDOM4zuYAHBzlbgNDJHkNjF3
BpKXxO3IMFUq/39LcJnIa4ZTI5ScvfKtn8QucLyDcB4QDXXGLg9uArcgLSkX2H8csW3AByOe2DKV
ORIwFbDEf/2cqKkPjXWUgllCmGRnKYJgmu/5oH3zBFFG91P3MTHV54zZqiKjvcUfuXisgVim32fJ
3QMmlHHDE8UhxLlI7CSl3tZWpMwVNvHipqSXfHfyrt7YGGE72Lb3ncTeSZfxOsd00+1JPqEsYIxq
uUFnRxMTIpBybedLpvUTth+f9qv5Y7p5i8FS2BDDzqAx+Jjg/vj56kz1Z6um2sjM07zZqG5XVxUm
qZhIhpo8iqGbgYJ1qz5yALxVSKNwegz0Z9HV5486yvXuIsXVUJhakMemKN7YSm891UcO3Z4aVxlf
PXN6ug5JQJJvQIhuhZjaYWEyN8zWSZHWR9+LkbX+ZP88dA2+hAK88T03OEtNbUxTdnsbTNSA4gRA
LClvGXqNaIzTKrMWkY5Q1GG2FRL5ZDGtqHNjgmeIApCXbvJaJPmOhYSULr5hWVTA8sPHDVAyZQ44
KHlf/kYd2vH4CCndKgZ8NPmH5MOA+X9wV8cG1yVULrkysoVc4FMw9PYNTsKJx1YQQhErw6hgYTgb
oJNm7dyNCn5OB3i/s5DgxFEN85C0gSjjPe7YK9s8wgM8EFIjjdjlrgqFeWEhWsUhPiVsMisRmXGt
Zww/aqeNXbmuKPg9rQzf2dxYb1u6BvZAZwGEj/QXCpouYHA/+sqV9nrLS6P1O7vzl1ykZjvciCRW
piT190KlFkTmrQPA8XyM6YmLLGQ77OL//RfHCKh1MqBZ+XIT7E7dgezchbdggf3dqhCUn865meWG
4smMmUSw2zPjh2a1dQtMj/TJshXb7GWVPLWEXkqyIbeajDTa9PxoBrk+xJl2XSOaafzLG2/AyYTX
daD7xWK9iRYcrf5qb/nEnBr/jzPwagIL9/YIAmhFBHrU3c+O3wA0DPGbe5LNuve9RFYsznRdRJ67
TdeU1C1zDEB8UwjEISHF5A3sunKHdHAvd/+4WmWS+eZ6begy/Gmkmh3ySlPvHDlliokxb5IZb0RZ
GDRSFBw9IZYmfaq1e6VpE1kzqsyzVhD1c+X4OUp63FT5sZEowoMG+b6JgTlJCdVjIyaIBVP+w4ja
lR78lcf0mjRHSuMS+/78XsViz/S+dYOGzS6EBdpaUoGKzPFUBMiL+fKfZ9/E7OQvFDWWo0q79pPR
89S8YN6Cirw7+Q5e0VehaiLY7Gz1vCtFi5bwjdRarfIwYZ7lxLE18lBxvITbvJ4MRVprrHMNhWKB
H58XpB4xYsIk9OFG/q08w4ZyiYKgfH2D+Byjt6B/PnmSb/p4NX+mrFsXyhDkIEj+Z7sGhkG90myz
MmJiURPA4XhVWdSNpF/YqCr0Ap0qiD1Y2TwUb3I8DRaa8kw4JK162FvcZUykoIMOlNVrNsYNilGN
uFrQJJ0faDBuQ4NYjFcpfsGJKGItzVo2f9Ypgto/S2QKBpoFchVV06iW0HLpfHcTb1RSrS830Ge4
kPoRxqCaUA4c1wxz+FILYM/qzVoaqfEEsj2dggXIgWtXPfXkXtMudaKnGNK2jT2ffBFRkKQ+L4kP
zP8Cn0GmGJr1wROF38GUMbdYr8rAbzzG0Lx1d6wltxUD34fZIV1nsR25jdeVG452aH6RhbS8KZZz
HGthRYwKBnHxwhAel9K24H1jIvxT47UOwm1qNczd5fu1sef8kvTY5CRlsa+wAPrxZdbYGW/5YFBu
P6njcMwx8qqfbqr0Ieox3+0VxVXwVivS5ILZhLlyUnimvenItNJl8o17+0L6oh473HKBcnb9ixSW
EseEXfFF1Pj/tB4nNip5oRorcM09jHWq9wUzL/5Ckz1NgcARMmvPCK+DWpvpl1kPwQkjyOKc3weO
WotioMQadHnnUQres32HHBi2Cf+O+yyZWurVzZkFrbUD+zGVHVd1vXUvCNpn+JfzXW3nu+/eU5ls
iYJKPwBOjc+kW5AryeaXTdo71wXYuaEu5QnNsy9+bJfzj9wUyIfQ+D7qIbtICO68jqh0rXyE4Yyf
cxYRpRkIdxRC/c0PRUTj5htOAC8AP0F7GHDpGRXNNbc8hPVkSF6NzqDJc92r+o1L/XIFC0cgrAOb
FDobTZTOGk6a//0DkvqV0pxKjVA6n8yM7yuADO9MWgOEcJmJ08vPNwn30f2gzyt0GAd4GcT2lLLc
VUf4MFW4LqpYe7W46sGFSTqBkqB9crzIZAhlGc+WzZ9bYzSPg2ekS+qb04As7o6Rx98FtP5SOWsO
IcE4xGqZnvNbfQyQ8H4Wp5/IETwbdaAX6ymY2Ad4nB6Ap6SHvMHjgs87bAvDx7vziNPOrFmyMr1c
hn/x08yPI3Uq3KSq/u8WgDAABBcUB0l5HpcjnANctnqsesnBPzNOA2onI+Yl9hzh7TOvuMneYiMx
wXlk11q/3kehxlbqvsv5wjn0Es+wCAtNpM+DkthYuNvpGkY7DS1z3+8KhxH923wrJt2UvycyQVBd
VYGsNfoiHmdqjPCDpfuGywEVa9Am3fLN4DJR7tMbVChg1Inzo3meUhMA9QrYPbTrMO8614hVAwRW
5DqEqYSXXBkGEdgaOP9vqdA1Xan5VR6UuXvWdXk2lSPs4aplZyjn4M6swkdNe7SotNjD0aiqKaSV
ckOTH+r16DFVGPovX/Xkk4CFBxXX5J6Wp4noWMHcXA1L9mExBp9eKz1RtQbnr4pdcgG8dlgz+HAd
vKHQr1ZplfHJyTJpxge5PUCyMiDNHT1IE6jNxX6FexO0Qe0I1FvyDRNiMFiohUglhlagrK7iOfZT
QqsTR7cG5trwC5GwlIjHpK44zC2m+2/6niHegQNVCKYJj56jaEDiONRj0c74jyOaV30b2e1sYbh0
tKSIPaQaAvf5HJGoDVE9mMW8vHDSdMUylodKDBZkG93o9Ry71KFTNs3fpfxvJM1fV71+556jdIq3
9PFPr9d2KASHco04biATGA68QVFQrrAtul1zTnjyGQl7dOCI6WJCm227O5nJ0+AyAj1zWWU7a7FG
lNl0BbFCl3d4qm3TOejuQcJSoiK5iWhOrQrLfMlLTLoBeeiiVETvEhrn6ZzmJus5lrB6JzrGFg6a
0hJDEKyigFgLccLVaW+R7OFdL19Q45cWagAAfG7uxnDTgM+he1akgruDnQ+Ddeu3fXubS1pZvO9C
jAqEC1tWhuTLpmUx6xN1QQu7EPOyAxKDOCZrl78M3w4dyyZXUgirxODO3qK1ZnlZoF9XMAV4kK9g
aTtwpHTQTDrRdAc5ZqWqc2rb9Ari3d8qSkn7vtqDUK+OQstvyT7grdzRhUQ1gQa1NHtaCrEklgx9
9DRvEN7IIQVPPot9VLN8Trk5S5gSiCr1w0W/LYWS5QQfH0+BYAY+0CrruoOMNrsuwo9kmi7uaUIM
ylWpz5b5+Aw8sbCeWjyvToPGn5z/X/TsblxVIDhZzozJOSxP1KdBBpKI1j99ZOk9yXcYx6rGme9i
6rCtD0qWMXek2nHjFZOGXvttWIe1WPJIbo1eYfwXk6eZHAZ7G8ljBbB5A7SkCuITyzU/CTpi/EgO
lQSxzWlUcvO2tXcAnp8HKYtVDv58hH62Ddp02SUrHjqjo3sUIRnJHvJTa9kZUM2Qg5zjrCK0LdE6
RL53OYsSIN9e36YjoGijt+R+ynGSGaLp14jJ/DnHF1JKC8RALi6y1r3Yht3OtgnoF3XM/ScEt8DJ
09lrFJHf45zHzH3T3HEEicN+XOgxEOc/6kUFpUxQNoCIFlAe63YBkdz9RWF9gI0fVQklPMU27Oq+
JnW1qfDs5NGErcwTR+reqkAC8v14OfhBAaGUydkBVIFhvKWWiDy9yqqtv74dAmBAn9MU0b6Dg0pl
ysUjH1UOn7d+Rx6/vMroNAEobL6T6IkOEuyTxZ2s/DsENZRj5PXUQK/kURRoKfrAHORm4zkR46Od
WDhVawnq+XJhzgsE0ITvnd0vGuo+1yCpAjgdyG63b3a+eLgBBdbbAKhxo0GI4deQa9w8o9+aQSw1
cfCjP3hH2UoJmqjcW4EZm+QheRyjayZEHAxJV3CSZgCSbj9qJgUo6i4E/FyRUwPR7rVC0TLvPbpZ
AI+MoWLIRKWlltidIp7PrK+v0VOcZ3VO//utzJ1I87dIQQ9lhB3ADDb2DrxAoZxFtnomeJ0+RlKd
7nSQ9O5L6oUQ1kB18g9INDJqjhWpFYUySzEHDQk4IVZs6/WKhK5h5/k/FWEpLbkK3fGfvbWNiFl+
rCusdyG7f010/xb29XL7f8eKcrYAGhtQRX6gM6x8XR1yT747n1mpJo4rhNJhOd7Sxmo47KFUvb5M
qgbsqkIaCGjYW4mD7/zBnJ/vlS/OWWS6jldXD4ZIYGn9OUM/1BOEU9oYASHTNMtPfQkE7n4yda2g
IztwvQ7q7xYcl0ZyESe6Sv+wFGIXX5bMAb37D+Kt4fvo+iZS/RjeppLMpYksBn7UMvtPKHiy3VIK
2XcCKWp902qw+BNSdYxe70AwFoIGVdAWw8t7JSdfTQejsdTxZaBjrPROvykAvhSMb70g84HB5Ucu
FfB85LsOCo+7QQqBrMJM+zvPWtxbp22TFFb5MOnwQVZS3ZrlO9YA1jpygBV0rYfnrww1ZGoYDIf+
z3qvKD+twwF5A7X/uHCX0Wvw7TFP+zbUT/TtgJllk57Ub01ECl47kljgt9l2lpcjNLBdYTohzMxD
eAuglFSjzWfpMBcBWcF3LpVol3HISGj8uBYIsk4yYLzlmnlhD7KHb5S2urHgYG0Hz4uIcGd0GT1V
rXnGefrdaFVDAlQw607Yt54zRWKD5yskUc2FkHXj8z9t+nEEGRYEAauWbTS3OXGxNRQ47fkNls3b
85g+97hscqMW1Mvmv+8M5eyFvqRTgJ2QVRDHaw/VoR/ep+sh5rgWkJ2umJGXnPHZPU5dA8JtBiPT
1KmZKzulQQr4a4ID00XXppeYDNWhf2CU2gTqiCtYIxwi6nk/4ogA+IqZsMqdeV2c7cCTNRZgF0hy
vRFR8rlMf6rhHEOnUqCl2yySQNiXyrKMymWCN1VyLA5FRqiVS2c15RjSGOWEU07tEYnvLoD4piwO
+Nw8Fw6YA8TLkxty0Lm0gjGjyLiEBcRQupTLihAvvO4CUG4cL8kB9AsAP/OWjvDU7x7dMm1SKdKO
ZTeHMCkoMLYEzEyzCmZBiE836TolW0g3Qx2KK8y/Nd7gNBCLAZoGDFgtuz6Um+C7ImBITmU8ek+Y
STcenRX48m4DUJ2dHm6DKkDdm7b+P0eGGskPINl0NJe44OPfzFo6CTHHAH3FVAXsP97h6cWqGY0P
u9ghfbiQG4A0KZ4y5I8yenaYdcjDpDpN8oGaVI9pYgK1XbW0ndS4518QBWDw78gSoW+Joudb+8EJ
f7vSvUTuQM+/HxFasNrNx64WWFJSwlSOG1ELplUYAhuvmfOWS8//gEj5HGI22GDl+k8XHJHfU6lY
wP4gmVs+scyjwiVjeB4QcQxO3llQk8NbNkzGx3C7kEvAOD0r1CgXCUtsaLa+AwBLKyRLXOLTgfHd
2pT6JHjdvbYSZuEiIiA4y3rnjlJwExhDTl2nPbOkNsLKheOSCzRzMWxlyECMp9Q3SssOyeO/aK1x
M+v4HhuJNr58VyifyngjJvAG2HLRIRynvxW2d89CTnth/4UxmEAOH7+2vzZ7vrrydII35ELZcivw
EMH9X1ISdEYfZ3gwqWRgcos4qvPwh7PlqbCBwborXS6MO4wzs9Y/YLE7OpBpAjCqRSqtQQdwHyAA
kgTfm8MVHSegTcSda5g7zl5tgWj50efCyplSwLe1geoY8gfx2GMZbf250elPnxVhqt80hiNUwhyj
kJ+GSAezRmi2waeaCDr6JZ4d6k9xIjn6OAXpKYgJE+NBIt/svDNglZFM6/hFuKGnO0oLAXK7iVWv
F74Yh33SCV7BC4I1AK9fs9vZxPo8gvkDFdA4RMvFhzhyYJnwhQTO6/gU+g+so83zvKz1oPcW36cw
azkIs8lH3hDDFmsXZmpCl9qyI9qDPVWMoaT8dxfGukIfuh7ZQ9LtqsH1m+A58Xqvx20/tHHVxIR5
c9Jq1ukVzY7EwRgURJlpbhnbfxGy4XubyqHCRNPV2Jl2mbonHkYrLL0kCaJUFBmy6LTjkjU6c1Wb
TCcHBXxAC69G9QaOnpTCwLPfFzQ/j7+Li8mQPM3N26DGpKAGNl/0snIvlUoQUQdsUcjkkYU0shop
tXGtYGq+0k3LyWTlihNOaQKcv9DAIeFZ3S1rXNDW7Vlnp9HvpliTGOnR4PCzGIrGp7baxqp5Sqdd
laUgvhE4KGJZevmHW2iW5RSThM+k5iab8fKkcXKBPrPtWHfmMcLpecpM00xak8Bl4ZB9T5RiIYUO
YbxaBpbAjojzFHOn5QPTP49EUqvIIZ3YMFSRRN4UYa+ExFh1zZ+08cYtrrWTX2pMvvdJPBRara6m
V+BubeCG/WLWbMZ4mrRGfLd6hDt7R/J/CZvzhwFrm2P3zEgUaHnT3uGu/MkFVldeLiC3nWak7SS9
NVZcHQY/SYe/HYFFIpkZd5nE9UCv76UsZAcdnIwmZoSmliY6MN17dOs/0X1MNrGwxmSzqDN4MSb7
fO39fvcHsTmU3QP42pUE9UGxmZBIy0/8K9OqZFcYP+rY8cZGoH+B16+rihjDMSJ2Zf+5ER345PYB
P1jTHRb3LMlW4I28zU+xC4mzcRL0MYTe2qG9anE1VQyEoAcJei/OgjeHq1/rMMTJYE5kd4k6Xs1L
wFGFTjBych7wLlmRaBwkDd8mI0cu0mDXDqA5BGWFh11lEoMy6PrvgHsexRYG8EX4UOmqF92CccYW
XO4O/LnrJAwpavhTERZn/530cHEgP850YbpkLXw7h3ByBVY0YuZKvc7g/ipaQaXnYvasBbfoI9H3
oXBNHPmxhKKnQle0DPLvELysFcnE+/zBwcKmk87PJ0x1rUBzhwQgBtXXzhY0k6MPNXynV7Xk6QMT
4eY0vWhBKrq1mOC6vFGYrBGOaA27rN1Qurid9oFdahfWljXbjcie4oLdErgIG4MSa/mtnu2N+TJx
v/VynE5a344O/hqspF6+utaWrEgxPQ/PW2/2FA981qdEyjFwXcm93TEZ5BeTXSK56tROFvLglLmR
mJZwOZuVM3yFkm8WK+Qw1WmiC0sbwpbbMWQMvNoEefbM1reFxeCkemEX1xhwMrAefNsTKEnLPgCg
YqV06fKx56Ram6wZOd7mN8h6SmNkJLcGDZ67u4XtvGiJXnHCktWUqevauoMsmbd2bLSJOGB+nRFy
LbqqqdqM8wB/5Pcc3gTiYjypST+g1meZ0jfyHvUWcf98h17herdvmdxOc/ZImrotgsqzvIIa5rC9
7ev6QSHLK3s0xdgjhxApP/jLLFFK0JZ2itTOVMr/w06WmawtMcYh34xlC79VvDrc2oig0Y51vzlm
5f4hIm7rKxCE5CFCeU0jcjDlFVv94uWKoNB8akqFp9yAQA2Yctti7u1CYm2C8V8RUAZ0QweBLy68
h51Iw3P9bBAg07Kz+/+bjLsTJZueCUnTBT/fwc56kUFjQblF7obVhCy0cUCPeVaeb238MmBZqZk2
9nWOr9Bc7VNbJtWcVOLVZhpG7BrQUc+T9bAl6OYKqJRiOcZYaQDSWuJnfSVugvX9/iU8j9yaoMrD
o0YlxwLLe0D9D1Wykg1kcrFY55Ld/gCuB47gkPs8ePyyqreE4hQyn+8xhrrgAjne4QsKxPnpYsT2
uX3PpCKz7lOol7B/veUfWWgG84rsjwiaNa5Mq1MLunRQF4Ed+SD+NW6ziVC1ytAQzWart9QJiH3p
8RdmKvHrEyrXRW9r1vEJV56KbXKqFXbq95DkJMYJPTKDO2SeljWPjjybpkNsOwUUcEJgEytKz98t
VTiznEKLE3sd/MIB6BnDmTF4CCKZxegtQzuQh9jWvCCEplXvk3z1ukTZVgTNKsQO67Kwck734Xo8
r+RDwEIowVpzE6sM2SUV8Z9ulbIMb7LtdAUqibQeDQ6oQn5Cn2YxomfcHvBnG+lyMAcPn2EhcKTi
Jvq2Z9JMi3G5rpHbKUssJfL061pmCH8m4xncC9jmCGspmp7ME9Nd+D/PBwwpiEDV7Nby9FrFFQO/
vIJpEJ56Skql3aon0wWGBK9ToORm8DxMII3do75bY6Vc7fr50LWaf1ekSopa1ofWSxXX+LKVfcJd
MU4yLAjOwLnjYKCLoOzwyzB/rdmhpQX/MtsKK/7PaPNQFKjhg/CedzhM9IZznWkZb3nXhn3NaRwt
XCO6zPxBkuuwywP4dOxu9nRmvmfld0KuUrA2u8CAGCpA55sYyphLvN+wq1r+/36DAYdpnCo7bgfR
l0ygMje6CzymRdOxqJqrQR/mc6V4pW/n0N2MJ8pjuR8uKBrAZGt/T2oK4dHSTeKNdwQa9BRlQ7s1
Uz0VSAwQH6nXOmj2H7eGpMTCiw6JlSz9wFjC7FNpsoUYZtKXPuXMChaycii+6fXM0FR147IFdqOA
g2OQ9v/pBZEdZ0gD86vXCPkSBEcgToJZyg7VwICLpCwYgGzaFm7M2OKNYfWPqjtfOwI49TomtOiS
dxO1b8htFVIACM+Z97d70/uAqvMpy0xkgboumSGFNGBRkWLKtOgwf72ihd/qICMmkR7RAHEOQtY1
3Bmes423D3JaTOtsQuJJqCbUpQI8LtQSQbKVsELkCl+CKRg0kGwjTJwZ/Dezq6C4BDb28DMq5gX1
s5wT6C+DhwhyC1dVvae11ZbQtQTz7IsCEUHezQeDoEtKse8znUYF7RwoQ1BKIDxxUboIJSKKCAlU
7PI2RwRFyNAVB79eHrVGdfGWObL4pBMlHwOvAfIgQAGkv3ity6Mdx6TgILt3XXxi6HhnlXrMG8Zz
uqSx8rk+UhfCHBFOy0OANQPIBt8X1u+ehrEHUhgXl0iTIl+6zfuYJrHRaHZCmdsnEnB4rJWXHxJ7
XP63rQ6Yl15Td1q/TrrFvGuL7u6no677XQUZ7dXP8I+WDqxHbXFD2g9XgfheNOvzooT5lm7tcNzN
R696oI11xbZw8oxzcmqszHltGWQYdkvyqBmXNbBwnAWFGiEWAgnrR5t1GZQguY1djM4P9suTsvrc
HAI10LrAndkcdHhLP/5B+4/OpC2WuLoVwNfglcVfTo2kyJFAcXBtxKDfuNy8yqL4RVjpsZe1hPdU
R1+DD2lNNfuhE29leoicDqE+8sXfAYVTtXwOOMC8ymLrUPD/RRY3nTGIVpONtNP4ITYUchj+GqCx
Mo6ksHpBBqhnpsuTbfoEQyEmKjNC0YXFhqPau/VhXGQ/EELrEQ27KhpvAmF8yTBEeFqqsOR168qt
OjGmg/c6iLVSPJCR6b12Lo1+7ROQEvDl/UcLsYalhNFl0QwSkQpkSpQWzzExbaAiAHmczRXLkS6a
Qgq1QE8t4d+1FFFifz8mpvwrss+812YCVsn3CvWOSnrQOFL/lVHS9I1cbXYvNv0ADKFlePhBz8Qu
6wPD5ZZkS9kcDAgwTdb+cXA5QEQyJP0lIbRSkmX+e0ewpo5HR1C2I6nAjFRo5Og9owie+CconGez
adARJ8WvRpoqy9jOM5XnLu/u7VxAWAbi8QBe2PacoavDTyadzBgSR8YfgevzXy5VZOTFS/pF4tib
mVT8IE/9RBE8esWUt2KeyBa3OuLINw6iqnl6wTnezYGJLprNIAxoBwspmmprm+aFaeuJ4V0RnWlM
TlTBA4O/KxLrCjVFOcuaCTmjMajT57viUZZAVwFkKc32gCNCKNNIfLQ/n6IvZ2GNt1tI8TVoBd63
s/JTl+t2KfdDx7DmTpJiSF4YgQ+r3i/o8SvuIy3b8IFwSdCBg+8xVe2QWY5eTXdg8BbdrGMEmcKA
XCIFr8YULmEJWNCA8j6tu83xPfsym7EQwQmwHK4F5YjZam7VQ+jpZ2RPsxNHWZfR7EDvYsP6+CRs
MILuhQZ54QpU3ZVG+nfDtpJ7g2k+aMCx95Rw9yQIubr1NGjn4h78HacBmA/YrUd59tJFY+rGE4s6
+qyJr2SwTDPOo45yHd5F5Tr4851/LmjAGIgLtCF8aBsd7Sz3IdasIOSs3EMsshd/kVV81DRfF7X2
pSbkXk/xfjr2XU+Mjhsq9ah2E87MhgcAoRZbTDkWe04vqALjMcx1ubxi58fPyl9LZXjo7VAuGCCn
LzMVM9Z1C6q/TtlnoQpLGksgTIXHfJDsV1IY7RVJaJ/BwNOQH/kT/yoXLcyVawPEZEserJ6EkXv/
uSCrf+QRgMQQmKwoBFD13ib153LH7Z3UNXKtgXRmwMNrblRhDZq13nD6zIIeUVOaU0YBWtE+XP4W
yb2UwImAKksyvMf0Nn/HXZgi4wzskGVSubjZtHMPTYfQU8PjT91eV2b1dwLqriKqO9u2WaGInayS
day7tbU8bjSZgJyyj4J1SYFRlUVfPg6qy4lc/WV50msIE0GU/WBSotDen/57COk/RQGbmAiLzGVN
7hG/xQnyCjV3jrlPzsF4UekrQNldFxZasneipES271lE5PWic1ZVxdE8bIOghSvz5WILI/Nqz1sF
a4A7zefxm5+H/2QCE9tyDbQiQwUJ3e/P6vM+Cf3kSCOgYrSxJc/VNWcuNuDeos8eIy/itIv4gL+9
JENnQ1xlSvNQdhvL7siPbHPek2ouDCEiFwUpI28HTQ2rD19ryXNoDBcG9yl9bryhgxv3C18Qm9eT
vOhvFZJdcXMlX50//DbjWVrcKIapuk0mdYj7BG5X3jaXagDifnnaID2muL9Sc5qdmSDtbpLO10Ep
lefhsiQa3OL5MM3t6KLzITvlWO+/EoGQsRF/u+WFKBFpwZUpobPUhkgLducYIXZX6ACVjfQBw6oE
QgV5DAuB56a5/4cFPIgm0+BI5DtgP7s5kGSb9xk5f8Qj4kjxe4cEfqht1hw6lfB5VLHCxTr3tXEP
92A3RC2cODkcr1uydYV+iWV4x/IWmxU3rfbLwxw+gOvbOr0AnU5YEDlc/Z7mOAWj/Qlo5mwiKsJu
lCbwFu33h8Eby3b5X9Tbpt7Vr0pQbWrqigaLwg73ViYh8oDDhxf7i9qwbzFusqJtxqoKNIJ/3uNW
5SDWtv9yZE7vYjMZRtXyjNKhwIft5aIVGAXicsNm2imHgGED83SJkYzH1MdRju89at5u7FIf9oRq
yDyxK09CSXO82b1a106nkm2sr4nhBBLD2M0OUUW2TQHAyw/WYuOZToyaEkbYFlbMJ+RPb0+DEIz0
NOF/e1XbpwZFPyljhuSRzlNHVoUfmWIfo3+9PM2dMOJHJxwjdKDmXF7nISKFf6imgmNOyLEIcvl4
kNzWkUvmY+LsE3zwInN/thrIbO9XrmrbIODdXefU9iWYqd0/2eXU+IuSuVD2/LZ2G2bxca0hvKbt
NsJOfj3akAZzuSMgR9IRriLs9NTzFB7BqG+kchgn37lESHObVaVtcHaxf5GXCuhVuu9ZQqwQg1bX
QH+lBrFahbaKhYW4CHBluWMawH7HBW2dQEhX3MyH6MHVylYk8UtyiU4BHzBckFp4NGRm99Wkrlsp
YpoCqbbeH/Wmnkc3U/8unS7oNZNjhgBaylxQF4ySkMu/E1QjIdV7pIkvyeP9ccm0CeZfFeuNg4uA
qBxKk3VuJlFUzeoJSBwSzw83WrIxlu8x11wY2LQU8G/tNETTDT5qVPiWfJ7IvyrmHcs+m4JAaDM4
p0W4fFIjYerAslgSWPyHq5i47kDwZwt1VML8Bf8SqGrWnpdPCGMt6n82HHRlJE9LL3T35+Vg8Vuu
STtQ6P/zYb6wFziqXzxdjhg6DndzRIqT4m/0B91LFidp/lZFxiPiqRPONEMZSVUVFqPGcDhTXYpk
TXCuvhtclfDAM3bZKUmfNyVkBuFWYZMcSBL4Qy1A+oF0SNcqQiTbzImpsue7sJcC1ptqnQtS/N7d
Jjv73ovOa+dpKZbxp2Rs/iPZfRLGBEwaKQVeBl9/uOriL7ZC6LsZ6KSXhnPRRua5dOuajmWv7WSl
bYl17ErG1GfoMGpC02kzp8yQPsnXKykNMiaAjjbN/2WzQsACIGJ8Vl3cqPGtPKugrinOuBSOyjGQ
0K6WF4gvxYYeySjoLLfeoD2smKvT9tmcFtEYBjMjiggvfCKrbgYDW0s09ySpRAs1gZOrfnjav8yL
ZvYpdAHRL1V00+W100PPzXLjE2VaP/hVgAr1XtfsX+p7MFZLhNUycDCPN1enXGNdvfq6NP+ZHJ7I
vB1X5QGwL/5F0DXzrT/wmHXM/FQ1TyxYiL0TwxQy+EYc0fjgb4qg+KLyV7YbXEcyWlcP4viICiNn
Bim4vdwJVrfkwS+dpPIMMj8xvp/cEXABwkA7j0CUft69NYbC//BSya7UnstkjlG9RcuqtOyuzLxC
x/hk/qLtJ5QqvpK4a879YHfYoNu3i8EzdUldGjXSjwTfhK4BaW89oPjUKDYta445VCrrruXnFA4O
CvlVpEA5tA3O0T4TLiYfSEGEMJ5Klq0WA2aqtmzwsgLelO4RRx8g7VtIYrhPVHGVSBQRuTxmoXef
LR4U0jWhsXSRVi5rVnA1AJJ5CJ1/WgwaTm9pcHv9H56pblrGk1dJu+SKpp01tw/ElBG4SnbxTzjM
6wA4/JSkYcluJ8RJ36eKKCUzGeesk4RpdicS1niiGhBcQ+IdKObTuKVtdpB6kdBGkC6IpO8r+hry
w8mKer0dkKR4qet3wYIMC4ahWCBelQeH5oKUCmC6ut4HBXxL0IhHMn0kSmFai1RAopcMPjY37Br+
fAzRzVEQVCBPRn6l/x0awoF+T53l85Fpp3Y0tG0IrD1HO2vK5ClfFiRFNG9sWD7wSVVcli2aS1yJ
UpxtZ3GlJMbsDU16gPxDN8R0Q5OgR3+EaNkRrGG2/uss8aC6hbRMzk39yV2i1fWZ19PMbc9Z2gHl
9exsUh0FUeCorWkizn86OuhpyUW5GQifjiIm6aIC4y71ox0r3zbToZOx9gIFsSIRYHc48eI9eYNY
+Upqum3eNXelc3/o0iFcXZikiYaZl6eF2uJU2F2syilmhjhJ50pGA+7g2ocDKsmkA6Vd2fR5rM2Y
wG22sxoree5riCVAIZdyfhMoJxDgqYyX4Sx3vRSYIeTYCtDXZ84YkR0TPB65QgFO2nl+zIHHNO1S
vwMZxZTlGEN5HvBJqkwGTbHNA5K0xrbb6/BcoScpyt6HgieSHds8mSXDGR/B4pwupcy3BZYFP3xZ
5OajzAxGcB0KnUi9mFis78cPyU2T3aMfk6oHXNGaeGoFTCiFIK2yZ7Jwnp2zUiR/y8n+4bWQfxjx
oUkjBICVNz25fsxvX3K+qctpC2ZarOwD10IrRyzsUAtx7LXuI0nxBE4lDJRe80m/l2ORWuI5KFVh
9CNw/0xrk5iyjLie1PR44d2+ldazQ8Y4MexkMp1JmlN+luF2RMH1I9VHY+k4pa/VGU7rPEO13ePI
lQIY4SA0Tkg2Vpstw8Dg68fVup3cXz0bBBOX1f5bUrSq4z6jAMA28iv4Z85jdaidXzkHNoaR11BK
wYvA3kJoadmnVJGCcp/2TeQLXm7YIw5buO8FjFOg1e+PhKZo6AVXQtlbRicUPD/t8H4O1B0ljpb1
Xzqy6VAxG0cbwoSR8LIAuv/OIevLGNWJ1HtNJe581YlBltSj7AMY0znAp0jFlZgA7u5gwsdCYBS1
fCxaeKFiUpDmbpObbSG2iqyx00qXCpDWKF7aM72IofkiroTffejDhZi0TXG4ZpDEzFetTfRbnekH
GucwFFNAzq5oHURtoK/f11NkePSJ9Fjtc/Mqum4TVhNCaTEvbXHMW5Qu/0LtVBUNjPQBxBrL9r6m
AVCfH4lYtDGC6+jEWL5wctv/awX3+PZ7Z6e6EXT5qfi0kjpFbE61P36BwY6vCzMFobhZXJTyucDE
psF3kY8zyKcPoyawChNpZIapNIlicmFzOAlZnYbM6J8fEvqgXfF1r2DDaVS85wCyiDJprIoF5wY1
QnEncJViC+6Hyrr+2Gh3DF5p2efCgwN0Cx+Au6bLrINj6fyP5jZmdLOPWGO9Qc18iw2mPvmS+7UV
yvyznwIheyA5qwgNt+Ad1HBwJCamnfLsoLm3Gmr+oabI7PInJHqDDq5+p3vcTbqbGwU1cI3OrJyi
9OoRmIiA0bcbZppKx3A9ogki9PkJSJNTSIjA2KaDZMevNqsCajnnyc8d7CATpX0m1YEyDEQW/qaG
Cp23VJnWPS5l58hFtTF2qgyBpQJkePd5mGFuEP/3suBphJIHpuvJiXMcoVg9hap6yYAr7jsyRHg8
M5JJgOk/OoJEXZmZqGgsss0eerhdQ38XThm7hR7N1JhlOBi2zh299Lo7Cc24qufb3VYvKsiDowUB
1/hUDsQQ0L7ISPktKOBQKf28m/VZDH8+1Q1d6wYadHnzJAOgFul+6BZobOKyUPmQm4H5VUvTLmbn
gqTgFU4xwIR/1IrXFRGe2P1OHDqENT1vGHhgFP/CqGCQAMQVbDHCKEulNs5Xh7ZTNnGf+xJTZwuK
MostmZK6L11bsD+pb2rx9R4nHfNtgaFiOhkbGGwO3XkC7eK6+ybZkMXIWjRlJtKJ27mj/cfxmRPH
f5FzVH841Ba3LwgWeKhWL1/zQfLlWQCTwG5dqYniQXWaKdPIxwtd8ZbqGmGJZBNjhU/unuBp6DlG
UIQ/pX42ch/w0Wrf5GSNwKiNF4MSV3mdiyPt7H9aRQTjHc6LgqW82GoIC1Ugkk1WZsXQwAQtZYkE
+is52Ie3P2U3oXA3JRzuk1ymVVwMSOfv/P+JuOwVMFLxZxFeASPoa9/1kFJSdxI+iDec0Xgt6+/t
tukPeFdmlPn5AHwuuXuZIdv1znEbTY7jEMvtqqTsxaboZagAKlKx7BQsshmRUhFrJQL3IRVDW4G2
RErUDw2vPRewl4OMC7CNqdyqw1l0R9v0//CiN/cOf7/1vXuIAvHvRCzuPmfyH9k+UdsMCy6ERtak
bjcepoZH0RKgOy4GxN/tD+8P3QYRfTvzQ6X108gcJqR3dg2TW20zjS7HBK/xWLYQ0/RSY2jQvhgF
O3fbGPLoZ9y6etJI4qTaVRDkZn5xldeWag3lo00UbT3E1RKm9xcJnmE5bbRxj5xfAv8uk3/ypH11
sfuKeiDwM8CK0qWH2lC7xBdmuC8e8NPO6D3OycNY4p8T4+6JdSiH1eSqXYHANuKpUCFTaVOHjI6M
qs9FjuFYEswEpsasp+7wQaeuqkNJDof445IKsDTv9MJCeOlQD05pi6AUZBftUr4z+kRFIQONUOa+
z6omAiAktYKQkL2FGgwIp9pEMNI8kshr2imJHNKzKEvt4ko1cWcDSTs7XJfxgQ8j5E5zNGqxDiHc
rTIqWeyFGXCWTkT7uVreeXjJSiJIFcu0qA99GHT2rxdXm4zstSNQR/snKQfOulgtlrELwk5KG6+Q
C7IXkq83YtfCUYlA0BVvSNzqTG59QIo0jpt9V5znrfOaYEWhanCIkssgm2VyknH35kAkhvtB+F+s
wOARh4uXO1SeBbcs3CqCVJf3AMsNU4fuch3dJtbAz82NHIH9pNLz3HW2rq9K766oUikvU6WzU9k0
UWquTsD651IBHqDkm8/E6FmN5FxH6UgmYeXwaSxNrejy/lTo3/npQksLTatFDCAMCKzF21nFiGVB
C8CnVQ4KXD651TmLSbx0itfexL2oMkD66bPwjcQq9lqmUizL94GNNQ3I9nHAGx2IZaJm1S+0XHcE
/1BBXc5w9BffnCFJlYEK0CJWWewMp/rTbskrHW+521aHcbD0SyPG1g3K5M8AuxxcceD0sduPq9dv
P6w9t60mzok7eNU15eBJzYWbm9fHqkgYu1ob2OLRNmOK9/v02kEKkRzr46N6vMXF2hkkYpOgj8SX
kwLqjdKN9U5alj8+a65b4GreGmgnBqUpF3YKY5gTc8of7ZQPKkgWMZiB4fayvBmoQGOJTs4TlxMT
lKrVClnfeRHf0MvqK7huSVWzl14aIgJp63HcJU9P/2Rlu+BLE24LzyKp6fW5RluLPgO8WdQQCBwr
5HWQ2Ktj0K8qPuWgHTCY1EEz2IZXvzys6eaiAYZ3Oc7rc0ZR60U/MSZuJJdxyTZHJoKG6xs3cBJ2
WWre9WtS32rH62YRsTeFCmTe6yarVndFyEm1j8BxtAsDBQU4W9bkkSOmYFCSrnk57qhqoXELeTwk
F6wbsLGdwQrGEH3t1ldDsJ1qOa74gpTwLD3wIoi2Pn8Z5HNdWQFFOLYifmvdrLhS7VIKHkWcCtgB
4DNGF1R11YOipzMdkq59WQUQ3DPEOvFzthjibO3T98A4grLJRYSA1ahdcls0Q3urPTMIZ4qBWHm9
kkUFMtxZFRKtdkmy6ZI72cMfj/vvg+zWYgd4k7lco7UKta58wDItfm3Axx42iFW3V79p5nibUD6x
3PMyiGScx3GYqRXVUAC1akldgIYICATt+zsQpEQ0a1JCaFD2uhQj8dxkRjRYdFyILY4A9RQDfALN
RmQ0D58eo9vBiSx98+yXMX+/RjEfl3427XyHflwGrfFdscUgRcKAEPhpKD+k9xC04eBc9WLp8VoG
lkWjaRxSt2uD1dVx4VSEqeZtM7vUN2S1XKzA5Wa9vWW805FilrElMbcEhHZIQvJ9bLcFfXgObJIR
qaVIt1tm2u4p3L7uFDtYaPZ/+vw+N8wAWcLcoq7qczHT/TmgSFtj7nVdW7rILH4Th/GrNLZXz/9t
tOpcF2aEg4rXtcbhWoqBOZJo1jG6svB9doP26Yp5nB3jjMdllMY0uASkLwLYzIX9Yj10Y8+gOvUi
9pBfWYYnDf9v1J7lDDyCYl7jHX+zU4fLRlkMNJOj5auVaX3sAtT+OEsIX4gNmEndm+I0zJl3ivUo
IgOZ4inU1TABiGktZvP4SxTElGnzY3dj6EbU7czn2Y/w5MiLpAF0vhvvdquqQ0ycy7szxIKAIvU1
kZ2ms+kJp3qbcJFxlRKKyB9jFec6UOquvXs/RV3WUc5O5z+xoiV8YtWGjOGWjlR79Xlna+G/An1r
1vO/eK/cgTdh7LK57g/Y6ZFHag3aGN4n7nsXvbm2LMhuFORyV6avSY5zJcT5uZAg8t5z6IXhMmRL
dZXjZ2cIFTCz2SKk/BseMuxXvFv+dnwzLZNJUTnWPczuJmcgbeTHkNo/oBnRm3d4rbZhbarfsISq
SkjqN5/ZIwDgeAzebw9QJ/JUkP/tuNvUuGsvPLCjpWLsy3VYkGTplAYwXESchwnCr0gKqO4C5TVQ
RAAiB4/BkY/eL6C86n3xTK2GMdFnhpwk4wDTniWZ+yhkxldOvQAeDfVZ8K4C7FVzkawV/uN5KPRQ
9TxLiHXAFKbevHa+89qBhUmElulnsiyzXq0qtPtHThapLmfsNsLgS+ozAFLmjrwvBG9tL0sD5lLO
8egrb/k1hX+tTdOcpVKJvdFrlix5J/k0kOKN/YAUC4k98+pr3qi2OQztLyEk0UXFKEbQGae/jJ6A
7ZbNu0OxAZPfnHUZhSCqkHHHlV/wGJ89btVqMdVtQMBuISMf2b6z5+yUdpIIWEynQ5jDfGVCe6JE
da8919ncx0Wc2CARaHT8KAVOysO8J3G3zpwBcPeCZm1p65YEs0G2GmITqHtx8zE4lpiXZcuaZLEc
0DrE+t5bqgAlEL4R6+4qMvrS+f9Uucs/qZ4XmQLesgbuFCfwths4jQaClu+R9hJaxNlmscNdboqv
kPaKKrHJwi8VwlLjgr3NhtjvTMuIDST2vFzNA813Bj2TwdUQtb6bBIBtuMsQvJXgvYT+pKz5Nm3d
n9dhzDYxr5a8yhJSogftnXj8YWA+lB5AzO4eJWKpsBbr18mwR0ubJaujPbDjrUgGrWgmyfjmEofH
K8EolgBMgR5bnVPJN81UjkqpjHi1fbnZukjniFVyu2PPKPawqy8wKzoSQ3cp2klVnBlAIjtDpnru
2L51Im7w2f1hGxrVAIJBHbDAEKBfxI//iq5tMmhbVMorCWJNOxQcheyMX9NzylCSGplzWPLeRVuo
XjrUpZFi0FwZ2/dNVZ8AXwTtHw1lv1lfVQLAq+/wXcDcHcW0b96DHu1mTkLMeyeP36i+veXOBtH4
BRyzCTKJhK5MAjuVHJ7xAVPgsYEOWT/FJ+fUWtXGI0rQJLrIFWTT43QIJxuqPJyJRxs8IFGt/S84
G8d0SHKaU2zGx47Q8c/P+W44McRz5+7NwYIH8heru2cKoruIyIcCMLmBm+YlPeMmj0D9QFwwuBK/
yqVRtsjk9sHjNvyCUXrLY40nMWqQJ0K38QvrhFtDKT9WD6cRNrd1ESNMEafQ4016W4bBdRf71Ci6
4vIv+ZGWBeKObmyCQAakg0KJiL2GvlRnnQkq1IG5auqSKbTPoWV+ceZ39lyXzoik15Lbd+qOgwlx
1zCCjgBvenlaprQUXhImbpx5qVMmqUowNlhSlyr4zGjhiuk2VufosBpHbRQkuPVAdMsPAn8YijfE
M8nZVgcq1VdYhTN58CRP0WlZeZTxiOFXHzdcxEeN5IPUav2h6WKLImlLpPtroIxQ/9Pconts0rJi
P8SwM2hRcBABXq5Tk2VHe2eBPrLkRkzyuFHUSasnG+tXHWda/HHy/sDd17M2TWb2kHQSRyY1bYu7
hOFtCLJ9MX6BiKCvkIHtbO6MzIvaD1w8k/TS88Uxl9NeMHtGwxWe41wHpr3ABLiGdt60+hcfPBj7
eChnNUGmku48l8NUXmjxZIgrp1KDch5z7RGQUICNZPA/LJlLBjXxebE/T2HTuoHuWaPmF6g4FokV
v1DmiB1p/Wo+kz/kmhhyNgh2c3nhKaQcZ8nAkIFObEmOqqpoMw8JilnE1wD3IeW4rjQZXTCv4TWY
HrGLAXiYAnMDgl4qSeTrmztT3/MM8mNuzIiZZWuM/oDj004Pg8OKRYCXbPtu5PbL/IcDCzP0HmDC
fzCYZ7oaEg8LLbxL5dHrvXAYoQWEOkirpWV7LSOJwweNKwtYGOn8ZCpoa3YdKdhM8uBhvCJI0dnY
8YwEKT/Zhq4BBXdGbVeMWnTEZVFVmB0uqHuOUUZfDMTsHHO4m6z8idGjbsL6GqfnhVZMCk+vF6re
UZnEJ0KyLqdLkgozOe7LMgsogSWgAeEJpEnRVEATL0D0E1JjasAM4OaPCMjcMCZWLRzrnrr6+X0U
6C9G9ViE0xrzlYhpzZaGHXho1NHYCVxcp+hjVBhiPLSv8TIv/7ssdROz1u6kNSnMH1pc2OvEKf2b
PVPH4EicSIOTosnYhLSVT+fkDXm1YkCaoZ4i9D2dIk9cnXRtizT+lLtjRqO54dshxkeiSzDfpSOR
acQtMBE9IRh5/3DwlRqD2eZb+s+XnZUdCZ3qeaNsK8A/GnNAbQtpZevNWW5kDJgoPyfnmhU3Pme2
UVzwnjaZHCciGsZ+qKOA2oa0CJvCJFDkZbxdUz/bTLA8GNrUTqfILOFWs0NuvEGkI+VjtQZ5is5i
8LQpZhyMLOhViO1f9hood3tcYv40z1nzZJ5LCk0Nf+eQg++pTsldKqY3/vKdhykmRc3ybEStmUYu
tzK2G4OevLJJvf3l9xNL1irooO8YcF6UnI6QxWMIWbaisR2pr6cys8CmdnBDmxxCQ5FLzpfiQq5q
JBNUYFCsYGzP3nLHt6tJy1Tj+LbTnXj09LPvnaY6X3irQ3EHeBciHBb89tI0g5bKtCTqaPYtVkZi
uD0FHrqtPMxaMm8zTbG4P9m9xoNIcL/CjGDrYOVdLRGfqnB7776Qs0j6GLo/LR7Q2CVeFCFRtM9p
5O3SmtjvNPru7GBPJoGeiwK02q4yQg1wIsS1RqME/bG6yS/98p4cjM4gJbv54bT7ENOH2koat/Hf
VgKUMcONqGhf/2D2hs2NydT2sebX9qIAvmGd+kYM3ZXYPDz5gmSgPdSGqd34Ch61qtSPrFI7zYVF
dACZVCxBuqoW96vjS0MGRvDzfVnrg6SoqZqSV9Y7DSTQSikGRpiehuw+3tjp+4LA4QGy4p96YraB
3MiIwEaTQ2P5PrJlsPz3ecSkbsunqL0RHD8CBdCQkun/1KuY5ZHpEW1UJ78DkGUHa1dBjCw4MrDJ
vWTQQuOU/MkoaiaH+CxvYyEOeGMfBr52NJevjTrRQCdrgTA0ju4I0g9s0tV8nlhLELAtGH1J9gQD
UYifk0d0iOXgbD1w3M4FP1B4PsUWz+ZqiIYhllG5ZT0xySZAO9ORG8ottIjHR2ia9BL3ak29G2it
nYclN8bEv1s43Y5gzhFALIwWjm3GkXXYvhed8vlh8PgJWaEvWPE0YL9MeURjYLqiWFQvtuoyYuhg
gwiVaOn70L7+xvrcg5oc0cjNfgcohGBv/TB3ybUTXJwC4WHIcZqMZUSvCzH5M1yBmRqE89Vr2PaB
lEAIGww22Xb3qNRDaUyaBZNFkiRmOT0aR2KXU+pelRH2d8vqltKZr/B2H2+ukuTb7s+2OohDZnIF
84gpUSw3w1A7POmvxELtPz/A1KS1Aq5bAxVyQNFdAb/DNKFI/1FQWfMaC7Iit4drADKfOgPpuIXY
CysMvvxN+/KC0qeg062fIGiKPzw3iNAeQT2NziS2hkxvKJ6oF2kEL5z+Tr2eTTRA7jcZWx/rlRpk
rz6V771/L5KlxY6rPtAAmIZicu4MPYasdxMEXDh6dkSUytkzt/fcJ6H7hwP4T0ekNMFkyYATSZpd
4Cp46w+JREx6aIwNoiFL1q6ng3CLS88Vu7aAm6Gu9Lef11BOF892Hc8A0xwi/DmuzrmwFoAd+NVA
ifvU2LO2fcs02+VTuUisVfgphCA+KvXjF81EU7ErtiwMEv0TsKdyPkOBbOxWhtzvUDHSB3znNwdc
yDG41fw/f0cio4OULTiwNeAJJZsvy0W6NifXNv4LJl563Vu2ecFbpWpeZyLi/qObfVcvt6bHDE+X
IN6l7mcDZlZRQYlzWmTrTRfaGzAUxUwuHtBR+FOkjIGYRR/5eiIBAKkBe3AFJIedAcKEo/+jr44g
YzdXxZ8Eg2PE4lSHKKwHWpcOVYEdAHA+BtandPnNV4KNEbzWLrtrIsM83ZiN7nz2C9gz6IxaPn8p
ES1LLdMBqrXNpdiHzvdsuu4OrxRwCj4UGEe56kou4aez/sS87p1SZKL4czyf5xwvmkSL8WFIhfiS
5SrETCfUmCrIW3Ind1aK1SFTRKiVSyNfTldEM/dECNjIhtGM70J8WvwqomhSirL2h5Nc1SNuCotx
meRH1Tis8lwylMYAAP5QrpiQLnPGaur/ulYXQ5koY6MGg+38CS87q9+CZNQh4ItqjccS5rMafM19
PYKcAJQvsF6oNGWzrMwdb41GD6QnhI/XjpvUH3aeGzjzp/enEU0i5V1id5Pbv7F9fI1U97mE0Agq
c3Ac81Pf7mG8RbAuWl1TKyUY5XC996W6PyjBZYcvnzhOu4hO8igZGw/uEF42MaPfczEkr6/EdM9h
dgtMv/OT8EJ3LjNYrAlbShRdFnph/mMZ3XOlG1lQwWgXl2t8tEDuuTXexvNFRoHSfIDeV0p0zyMN
DczdhUPIojyKhCQYFQNXvYpkBs/iBLRJIZ0r2SaFh9UaiHFwp6fmJlOPqERY4hEjKIzgM7XmEW5a
LRUrxzgh9zHvNEIQ/0yM2ONbLXXeAblm4mjvae/za17D9Jgx8dBD2Gb4BmJXgbhT1f/aC2Xt1GKl
Qggmv9/3zvSk9anRnu9UMZAFDO+PiTUK3Q6ltMxcPdHo3vNpTjQ08K+z62MiY4qjy70etW2uVj54
wv2F7pxBqEPO6d62YMrSE8MvYXG+BqZFDZI0Yr6n3exc3h0MgppvTJN6jKLz2txYlnxW/P51KieG
I9DPUoQBCTvXrEemwF+DjB4dGn2QeSJTiCrhs0j6PKHwd1dKDPmV+dvjhAYvzjr/UcNb0OhHX+4e
egu5rV74VhFtalU8aMQ9M7pjhR0Xee//NrgfzWP0DHfXOPxeSuK5FV9DLVfxPeB30Tl5y15JlVkg
oM22r0wZL98xCz4U2GhZ+YPi6uC7mGCgHJDnA9KadYxVV1cyg7kTaiiVc/KL0iZqY0RyYOk/bztt
jH5LmmhBHkUtnajVU+K9YngbJqaIi6y+7wnGrPCHBLf1EWMJyT4gQnVdIMBjMxgl1q7vDVrPLU+s
VKvWT0ngm8Ur3IGSkEeGdNTk8Ck+YNtAmd2tcRrrh5lUbGIDIf6U1hKilZKcgOizj3zaIiTjI8m2
exckQwfKzPc7
`protect end_protected
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.