content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
use work.iface.all;
use work.amba.all;
-- Version with stereo and 16 bits on each channel
-- Record function disabled
-- 20.02.02 LA
entity ddm is
port (
rst : in std_logic;
clk : in clk_type;... |
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
var... |
library ieee;
use ieee.std_logic_1164.all;
entity var01b is
port (clk : std_logic;
mask : std_logic_vector (1 downto 0);
val : std_logic_vector (3 downto 0);
res : out std_logic_vector (3 downto 0));
end var01b;
architecture behav of var01b is
begin
process (clk)
variable hi, lo : natu... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use unisim.vcomponents.all;
use work.sampling.all;
entity jtag_access is
generic (
num_samplers : integer;
num_observers : natural
);
port (
clk, reset : in std_ulogic;
joint_counters : in joint_counter_array_t(1 to num_observers);
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity #entity# is
port(
clk, resetn: in std_logic;
#inputs#
#outputs#
);
end entity;
architecture #architecture# of #entity# is
type state is (#states#);
signal current_state, next_state : state;
begin
evolution : process(current_state,#inpu... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:37:34 09/26/2017
-- Design Name:
-- Module Name: IM - Arqim
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Rev... |
--
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, eith... |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
entity test is
end test;
architecture only of test is
subtype small is integer range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'base'left = integer'left report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
subtype small is integer range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'base'left = integer'left report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
entity test is
end test;
architecture only of test is
subtype small is integer range 1 to 3;
begin -- only
p: process
begin -- process p
assert small'base'left = integer'left report "TEST FAILED" severity FAILURE;
report "TEST PASSED" severity NOTE;
wait;
end process p;
end only;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
begin
end architecture RTL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
---------------------------------------------------------------------------------
-- Title : Command Interpreter
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : CommandInterpreter.vhd
-- Author : Kurtis Nishimura... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY binaryto4hex IS
PORT (
binary : IN STD_LOGIC_VECTOR(15 downto 0);
output0, output1, output2, output3 : OUT STD_LOGIC_VECTOR(6 downto 0)
);
END binaryto4hex;
ARCHITECTURE Behavioural OF binaryto4hex IS
COMPONENT binary_to_sevenSeg
... |
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use work.Constants.all;
package DefTypes is
-----------------------------TYPES-----------------------------
--Type used for easier access to the NPCTag table data
type MemoTableTNPCTagEntry is record
Valid: std_logic;
Tag: std_logic_vector(MemoT... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity color_generator is Port (
clk : in std_logic;
overflow_bits : in STD_LOGIC_VECTOR (19 downto 0);
color_rgb : out STD_LOGIC_VECTOR (11 downto 0));
end color_generator;
architecture Behavioral of color_generator is
signal count : uns... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Wed Apr 30 22:30:36 2014
-- Host : macbook running 64-bit Arch Linux
-- ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb is
port(
--Clock and Reset
clk : in std_logic;
reset_n : in std_logic;
-- USB Conduit interface to DE2 (Export)
USB_DATA : inout std_logic_vector(15 downto 0);
USB_ADDR : out std_logic_vector(1 downto 0);
USB_WR_N : out st... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Reorder Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-----------------------------------------------------------... |
-- $Id: serportlib_tb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: serportlib_tb
-- Description: serial por... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Xilinx clock buffered output.
------------------------------------------------------------------------------
library... |
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use work.std_ovl_procs.all;
architecture rtl of ovl_never is
constant assert_name : string := "OVL_NEVER";
constant path ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity divisor_line is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
trans_andamento : in std_logic;
transmite_dado : out std_logic;
fim : out std_logic;
dado_trans : out st... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sun Jun 5 17:42:57 2016
-- Host : Dries007-Arch running 64-bit unknown... |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sun Jun 5 17:42:57 2016
-- Host : Dries007-Arch running 64-bit unknown... |
-- file: design_1_clk_wiz_1_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This... |
-- file: design_1_clk_wiz_1_0_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
library ieee;
use ieee.std_logic_1164.all;
entity adder is
port (x, y : in std_logic;
sum, carry : out std_logic);
end adder;
architecture behavioural of adder is
begin
sum <= x xor y;
carry <= x and y;
end behavioural;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ea_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
architecture RTL of FIFO is
begin
process
begin
if (rst = c_asserted) then
elsif (clk'event and clk = '1') then
end if;
if (rst = c_asserted) then
elsif (clk'event and clk = '0') then
end if;
if (rst = c_asserted) then
elsif (rising_edge(clk)) then
end if;
if (rst = c_... |
-------------------------------------------------------------------------------
--
-- File: DataPathModel.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodAWG1411_Controller
-- Date: 20 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incor... |
-- System timer for MARK-II
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: v.mlejnecky@seznam.cz
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity systim is
generic(
BASE_ADDRE... |
library verilog;
use verilog.vl_types.all;
entity Small_Alu is
port(
clk : in vl_logic;
res : in vl_logic;
a : in vl_logic_vector(31 downto 0);
b : in vl_logic_vector(31 downto 0);
outp : out vl... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package Eth_TestSig_Cfg is
signal g_Test_EthRec_CRCFlag : std_logic; -- ethrx_input; DFE_TR
end package;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans_inv is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans_inv;
-- Architecture of the Component
architecture a_aff_trans_inv of aff_trans_inv is
... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity aff_trans_inv is port (
a : in std_logic_vector (7 downto 0);
b_out : out std_logic_vector (7 downto 0) );
end aff_trans_inv;
-- Architecture of the Component
architecture a_aff_trans_inv of aff_trans_inv is
... |
entity repro is
end entity repro;
architecture TB of repro is
begin
DM: process
type t_ram is array(natural range <>) of bit_vector;
type p_ram is access t_ram;
variable myram : p_ram;
begin
myram := new t_ram(0 to 31)(15 downto 0);
wait;
end process DM;
end a... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:54 10/31/2011
-- Design Name:
-- Module Name: generadorAleatorio - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:40 2019
-- Host : varun-laptop running 64-bit Service ... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
--
-- Module Name: arp_resolver - Behavioral
--
-- Description:
--
-- Dependencies:
--
------------------------------------------------------------------------------------
-- F... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- TEST
-- /TEST
entity latch is
port (
data : inout std_logic_vector(2 downto 0);
mem : out std_logic_vector(2 downto 0);
clk : in std_logic;
we : in std_logic
);
end latch;
archite... |
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: WC16C_Control.vhd
-- // Date: 12/9/2004
-- // Description: WC16 Core
-- // Class: CSE 378
-- ==============================================... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity dk14_nov is
port(
clock: in std_logic;
input: in std_logic_vector(2 downto 0);
output: out std_logic_vector(4 downto 0)
);
end dk14_nov;
architecture behaviour of dk14_nov is
constant state_1: std_logic_vector(2 downto 0) ... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ae_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published b... |
--************************************************************************************************
-- 32Kx8(32 KB) DM RAM for AVR Core(Xilinx)
-- Version 0.1
-- Designed by Ruslan Lepetenok
-- Modified 29.10.2005
--************************************************************************************************
... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Jul 6 05:51:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../autoopen.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author... |
-- #############################################################################
-- DE1_SoC_TRDB_D5M_LT24_top_level.vhd
-- ===================================
--
-- BOARD : DE1-SoC from Terasic
-- Author : Sahand Kashani-Akhavan from Terasic documentation
-- Revision : 1.8
-- Last updated : 2017-06-11 12:48:26 UTC
--
-... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:01:06 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- ... |
-- idf_encoding.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity idf_encoding is
port (
RED : in std_logic_vector(7 downto 0);
GREEN : in std_logic_vector(7 d... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- S... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- S... |
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- S... |
library verilog;
use verilog.vl_types.all;
entity mem_reg is
port(
clk : in vl_logic;
reset : in vl_logic;
\out\ : in vl_logic_vector(31 downto 0);
miss_align : in vl_logic;
stall : in vl_logic;
flush ... |
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Fernando García Redondo, fgarcia@die.upm.es
----------------------------------------------------------------------------
---------------------------------... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confi... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype Ale... |
-- VOLTIMETRO
-- Librerias necesarias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Definimos la entidad
ENTITY Voltimetro IS
PORT(
-- FPGA
reloj : IN STD_LOGIC; -- Reloj interno de la placa
unidadesDisplay : OUT STD_LOGIC_VEC... |
--------------------------------------------------------------------------
--
-- Copyright (C) 1993, Peter J. Ashenden
-- Mail: Dept. Computer Science
-- University of Adelaide, SA 5005, Australia
-- e-mail: petera@cs.adelaide.edu.au
--
-- This program is free software; you can redistribute it and/or modify
-- it... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:04:29 02/20/2011
-- Design Name:
-- Module Name: hamming_decoder_26bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: ... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.