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-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0'; elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
-- Source: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl.html
-- Listing 4.10
-- modified: added port "clk_en", Sept 5, 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity univ_bin_counter is
generic(N: integer := 8);
port(
clk, reset : in std_logic;
syn_clr, load, en, up : in std_logic;
clk_en : in std_logic ;
d : in std_logic_vector(N-1 downto 0);
max : in unsigned(N-1 downto 0);
min : in unsigned(N-1 downto 0);
q : out std_logic_vector(N-1 downto 0)
);
end univ_bin_counter;
architecture arch of univ_bin_counter is
signal r_reg : unsigned(N-1 downto 0) := min;
signal r_next : unsigned(N-1 downto 0);
signal max_tick : std_logic;
signal min_tick : std_logic;
begin
-- register
process(clk,reset,clk_en,syn_clr,min,r_next)
begin
if (reset='1' or syn_clr = '1') then
r_reg <= min;
elsif rising_edge(clk) and clk_en = '1' then
r_reg <= r_next;
end if;
end process;
process (en,up,r_reg,min,max)
begin
if (en = '1') then
if (up = '1') then
if (r_reg = max) then
r_next <= min;
elsif (r_reg /= max) then
r_next <= r_reg +1;
end if;
elsif (up = '0') then
if (r_reg = min) then
r_next <= max;
elsif (r_reg /= min) then
r_next <= r_reg -1;
end if;
end if;
elsif (en = '0') then
r_next <= r_reg;
end if;
end process;
q <= std_logic_vector(r_reg);
end arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity shifter is
port( serial_in, cp : in std_logic;
q0 : out std_logic);
end entity;
architecture arc of shifter is
signal aux3, aux2, aux1 : std_logic;
component dflipflop
port( d, clk : in std_logic;
q : out std_logic );
end component;
begin
ff3: dflipflop port map (d=>serial_in, clk=>cp, q=> aux3);
ff2: dflipflop port map (d=>aux3, clk=>cp, q=> aux2);
ff1: dflipflop port map (d=>aux2, clk=>cp, q=> aux1);
ff0: dflipflop port map (d=>aux1, clk=>cp, q=> q0);
end architecture;
|
package sigpack is
generic (width : positive);
signal s : bit_vector(1 to width);
signal t : integer;
end package;
entity genpack12 is
end entity;
package p1 is new work.sigpack generic map (3);
use work.p1.all;
architecture test of genpack12 is
package p2 is new work.sigpack generic map (4);
package p3 is new work.sigpack generic map (5);
begin
s <= "110";
t <= 5;
p2.s <= "1010";
p2.t <= 7;
p3.s <= "11001";
p3.t <= 3;
check: process is
begin
wait for 1 ns;
assert s = "110";
assert p2.s = "1010";
assert p3.s = "11001";
assert t = 5;
assert p2.t = 7;
assert p3.t = 3;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_unsigned.all;
entity i2c_test is
port (
pi_base_clk : in std_logic;
pi_reset_n : in std_logic;
pi_key : in std_logic_vector(3 downto 0);
pi_sw : in std_logic_vector(9 downto 0);
po_led : out std_logic_vector(9 downto 0);
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
-- pi_phi2 : in std_logic;
-- pi_prg_ce_n : in std_logic;
-- pi_prg_r_nw : in std_logic;
-- pi_prg_addr : in std_logic_vector(14 downto 0);
-- po_prg_data : out std_logic_vector(7 downto 0);
-- pi_chr_ce_n : in std_logic;
-- pi_chr_oe_n : in std_logic;
-- pi_chr_we_n : in std_logic;
-- pi_chr_addr : in std_logic_vector(12 downto 0);
-- po_chr_data : out std_logic_vector(7 downto 0);
po_dbg_cnt : out std_logic_vector (63 downto 0)
);
end i2c_test;
architecture rtl of i2c_test is
component i2c_slave
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
---i2c bus lines...
pi_slave_addr : in std_logic_vector (6 downto 0);
pi_i2c_scl : in std_logic;
pio_i2c_sda : inout std_logic;
---i2c bus contoler internal lines...
po_i2c_status : out std_logic_vector (2 downto 0);
po_slave_in_data : out std_logic_vector (7 downto 0);
pi_slave_out_data : in std_logic_vector (7 downto 0)
);
end component;
component i2c_eeprom
generic (abus_size : integer := 16);
port (
pi_rst_n : in std_logic;
pi_base_clk : in std_logic;
pi_bus_xfer : in std_logic;
pi_r_nw : in std_logic;
pi_bus_ack : in std_logic;
po_bus_ack : out std_logic;
pi_data : in std_logic_vector (7 downto 0);
po_data : out std_logic_vector (7 downto 0)
);
end component;
signal reg_dbg_cnt : std_logic_vector (63 downto 0);
signal reg_slave_in_data : std_logic_vector (7 downto 0);
signal reg_slave_out_data : std_logic_vector (7 downto 0);
signal reg_slave_status : std_logic_vector (2 downto 0);
signal reg_slave_addr_ack : std_logic;
begin
po_led <= reg_dbg_cnt(32 downto 23);
po_dbg_cnt <= reg_dbg_cnt;
--reg_slave_out_data <= conv_std_logic_vector(16#c3#, 8);
i2c_slave_inst : i2c_slave
port map (
pi_reset_n,
pi_base_clk,
conv_std_logic_vector(16#44#, 7),
pi_i2c_scl,
pio_i2c_sda,
reg_slave_status,
reg_slave_in_data,
reg_slave_out_data
);
i2c_eeprom_inst : i2c_eeprom generic map (4)
port map (
pi_reset_n,
pi_base_clk,
reg_slave_status(0),
reg_slave_status(2),
reg_slave_status(1),
reg_slave_addr_ack,
reg_slave_in_data,
reg_slave_out_data
);
deb_cnt_p : process (pi_base_clk, pi_reset_n)
use ieee.std_logic_unsigned.all;
variable cnt : integer;
begin
if (pi_reset_n = '0') then
reg_dbg_cnt <= (others => '0');
cnt := 0;
elsif (rising_edge(pi_base_clk)) then
if (cnt = 0) then
if (pi_sw(0) = '1') then
--debug count is half cycle because too fast to capture in st ii.
reg_dbg_cnt <= reg_dbg_cnt + 1;
cnt := 1;
end if;
else
cnt := 0;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
address : in unsigned(depth - 1 downto 0);
data_in : in std_logic_vector(width - 1 downto 0);
data_out : out std_logic_vector(width - 1 downto 0)
);
end ram;
architecture logic of ram is
type mem_type is array ((2 ** depth) - 1 downto 0) of std_logic_vector(width - 1 downto 0);
begin
-- read new data
w_r : if wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
if put then
mem(idx(address)) := data_in;
end if;
data_out <= mem(idx(address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
data_out <= mem(idx(address));
if put then
mem(idx(address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram_unsigned is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
address : in unsigned(depth - 1 downto 0);
data_in : in unsigned(width - 1 downto 0);
data_out : out unsigned(width - 1 downto 0)
);
end ram_unsigned;
architecture logic of ram_unsigned is
type mem_type is array ((2 ** depth) - 1 downto 0) of unsigned(width - 1 downto 0);
begin
-- read new data
w_r : if wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
if put then
mem(idx(address)) := data_in;
end if;
data_out <= mem(idx(address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
variable mem : mem_type := (others => (others => '0'));
begin
if rising_edge(clk) then
data_out <= mem(idx(address));
if put then
mem(idx(address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram_dual is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
write_address : in unsigned(depth - 1 downto 0);
data_in : in std_logic_vector(width - 1 downto 0);
read_address : in unsigned(depth - 1 downto 0);
data_out : out std_logic_vector(width - 1 downto 0)
);
end ram_dual;
architecture logic of ram_dual is
type mem_type is array ((2 ** depth) - 1 downto 0) of std_logic_vector(width - 1 downto 0);
shared variable mem : mem_type := (others => (others => '0'));
begin
-- read new data
w_r : if wr generate
process(clk)
begin
if rising_edge(clk) then
if put then
mem(idx(write_address)) := data_in;
end if;
data_out <= mem(idx(read_address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
begin
if rising_edge(clk) then
data_out <= mem(idx(read_address));
if put then
mem(idx(write_address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.functions.idx;
entity ram_dual_unsigned is
generic (
width : integer := 1;
depth : integer := 1;
wr : std_logic := '0'
);
port (
clk : in std_logic;
put : in std_logic;
write_address : in unsigned(depth - 1 downto 0);
data_in : in unsigned(width - 1 downto 0);
read_address : in unsigned(depth - 1 downto 0);
data_out : out unsigned(width - 1 downto 0)
);
end ram_dual_unsigned;
architecture logic of ram_dual_unsigned is
type mem_type is array ((2 ** depth) - 1 downto 0) of unsigned(width - 1 downto 0);
shared variable mem : mem_type := (others => (others => '0'));
begin
-- read new data
w_r : if wr generate
process(clk)
begin
if rising_edge(clk) then
if put then
mem(idx(write_address)) := data_in;
end if;
data_out <= mem(idx(read_address));
end if;
end process;
end generate w_r;
-- read old data
r_w : if not wr generate
process(clk)
begin
if rising_edge(clk) then
data_out <= mem(idx(read_address));
if put then
mem(idx(write_address)) := data_in;
end if;
end if;
end process;
end generate r_w;
end architecture logic;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity example_C_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 6;
mem_size : integer := 50
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of example_C_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array := (others=>(others=>'0'));
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity example_C is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 50;
AddressWidth : INTEGER := 6);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of example_C is
component example_C_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR);
end component;
begin
example_C_ram_U : component example_C_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 2;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_3_max_dsp_32_u : component convolve_kernel_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
entity repro is
port (clk : bit;
rst : bit;
d : bit_vector (7 downto 0);
q : out bit_vector (7 downto 0));
end repro;
architecture behav of repro is
constant c : bit_vector (7 downto 0) := x"7e";
signal s : bit_vector (7 downto 0) := c;
begin
process (clk)
begin
if rst = '1' then
s <= c;
elsif clk = '1' and clk'event then
s <= d;
end if;
end process;
q <= s;
end behav;
-- For this design:
-- %3:$o[8]{n7w8} := 8'uh7e
-- \s:$o[8]{n8w8} := $isignal{i7} (
-- .$i: %8:$o[8]{n12w8} := $mux2{i11} (
-- .$s: \rst{n2w1},
-- .$i0: %7:$o[8]{n11w8} := $mux2{i10} (
-- .$s: %6:$o{n10w1} := $edge{i9} (
-- .$i: \clk{n1w1}),
-- .$i0: \s:$o{n8w8},
-- .$i1: \d{n3w8}),
-- .$i1: %3:$o{n7w8}),
-- .$init: %3:$o{n7w8})
-- \q := \s:$o{n8w8}
-- For repro2:
-- \s:$o{n8w1} := $isignal{i7} (
-- .$i: %9:$o{n13w1} := $mux2{i12} (
-- .$s: \rst{n2w1},
-- .$i0: %8:$o{n12w1} := $mux2{i11} (
-- .$s: %7:$o{n11w1} := $edge{i10} (
-- .$i: \clk{n1w1}),
-- .$i0: \s:$o{n8w1},
-- .$i1: \d{n3w1}),
-- .$i1: %6:$o{n10w1} := 1'uh1),
-- .$init: %3:$o{n7w1} := 1'uh1)
-- \q := \s:$o{n8w1}
-->
-- %3:$o{n7w1} := 1'uh1
-- \s:$o{n8w1} := $isignal{i7} (
-- .$i: %10:$q{n14w1} := $iadff{i13} (
-- .$clk: \clk{n1w1},
-- .$d: \d{n3w1},
-- .$rst: \rst{n2w1},
-- .$rst_val: %6:$o{n10w1} := 1'uh1,
-- .$init: %3:$o{n7w1}),
-- .$init: %3:$o{n7w1})
-- \q := \s:$o{n8w1}
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:39:23 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_1_stub.vhdl
-- Design : fifo_generator_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_generator_1 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 93 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 93 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
end fifo_generator_1;
architecture stub of fifo_generator_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,din[93:0],wr_en,rd_en,dout[93:0],full,empty";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2014.1";
begin
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
component prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end component;
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
prg : prgmem
generic map (
INIT_FILE_NAME => "prom.hex",
PRGM_MEM => abits,
MEM_WIDTH => 32
) port map (
clk => clk,
addr => romdata,
data => addr
);
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate --won't really work
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
--will be clocked in prgmem already
--ahbso.hrdata <= romdata;
end if;
end process;
ahbso.hrdata <= romdata;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
component prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end component;
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
prg : prgmem
generic map (
INIT_FILE_NAME => "prom.hex",
PRGM_MEM => abits,
MEM_WIDTH => 32
) port map (
clk => clk,
addr => romdata,
data => addr
);
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate --won't really work
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
--will be clocked in prgmem already
--ahbso.hrdata <= romdata;
end if;
end process;
ahbso.hrdata <= romdata;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
component prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end component;
constant abits : integer := 9;
constant bytes : integer := 288;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
prg : prgmem
generic map (
INIT_FILE_NAME => "prom.hex",
PRGM_MEM => abits,
MEM_WIDTH => 32
) port map (
clk => clk,
addr => romdata,
data => addr
);
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate --won't really work
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
--will be clocked in prgmem already
--ahbso.hrdata <= romdata;
end if;
end process;
ahbso.hrdata <= romdata;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_6.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_6 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_6;
ARCHITECTURE SYN OF ram_6 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_6.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_6.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_6.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_6_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic Fan Controller
--
-- Description:
-- ------------------------------------
-- This module generates a PWM signal for a 3-pin (transistor controlled) or
-- 4-pin fan header. The FPGAs temperature is read from device specific system
-- monitors (normal, user temperature, over temperature).
--
-- For example the Xilinx System Monitors are configured as follows:
--
-- | /-----\
-- Temp_ov on=80 | - - - - - - /-------/ \
-- | / | \
-- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\
-- | / | \
-- | / | | \
-- Temp_us on=35 | - /---/ | | \
-- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\
-- | / | | | \
-- ----------------|--------|------------|--------------|----------|---------
-- pwm = | min | medium | max | medium | min
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.physical.all;
use PoC.components.all;
use PoC.xil.all;
entity io_FanControl is
generic (
CLOCK_FREQ : FREQ;
ADD_INPUT_SYNCHRONIZERS : BOOLEAN := TRUE;
ENABLE_TACHO : BOOLEAN := FALSE
);
port (
-- Global Control
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
-- Fan Control derived from internal System Health Monitor
Fan_PWM : out STD_LOGIC;
-- Decoding of Speed Sensor (Requires ENABLE_TACHO)
Fan_Tacho : in std_logic := 'X';
TachoFrequency : out std_logic_vector(15 downto 0)
);
end;
architecture rtl of io_FanControl is
-- constant TIME_STARTUP : TIME := 500 ms; -- StartUp time
-- Use frequencies only to make Vivado work.
constant TIME_STARTUP_INVERSE : FREQ := 2 Hz; -- StartUp time
constant PWM_RESOLUTION : POSITIVE := 4; -- 4 Bit resolution => 0 to 15 steps
constant PWM_FREQ : FREQ := 10 Hz; --
constant TACHO_RESOLUTION : POSITIVE := 8;
signal PWM_PWMIn : STD_LOGIC_VECTOR(PWM_RESOLUTION - 1 downto 0);
signal PWM_PWMOut : STD_LOGIC := '0';
begin
-- System Monitor and temperature to PWM ratio calculation for Virtex6
-- ==========================================================================================================================================================
genXilinx : if (VENDOR = VENDOR_XILINX) generate
signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genML605 : if (BOARD = BOARD_ML605) generate
SystemMonitor : xil_SystemMonitor_Virtex6
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
genSeries7Board : if ((BOARD = BOARD_KC705) or (BOARD = BOARD_VC707)) generate
SystemMonitor : xil_SystemMonitor_Series7
port map (
Reset => Reset, -- Reset signal for the System Monitor control logic
Alarm_UserTemp => UserTemperature_async, -- Temperature-sensor alarm output
Alarm_OverTemp => OverTemperature_async, -- Over-Temperature alarm output
Alarm => open, -- OR'ed output of all the Alarms
VP => '0', -- Dedicated Analog Input Pair
VN => '0'
);
end generate;
sync : entity PoC.sync_Bits
generic map (
BITS => 2
)
port map (
Clock => Clock,
Input(0) => OverTemperature_async,
Input(1) => UserTemperature_async,
Output(0) => OverTemperature_sync,
Output(1) => UserTemperature_sync
);
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => CLOCK_FREQ/TIME_STARTUP_INVERSE) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
genAltera : if (VENDOR = VENDOR_ALTERA) generate
-- signal OverTemperature_async : STD_LOGIC;
signal OverTemperature_sync : STD_LOGIC;
-- signal UserTemperature_async : STD_LOGIC;
signal UserTemperature_sync : STD_LOGIC;
signal TC_Timeout : STD_LOGIC;
signal StartUp : STD_LOGIC;
begin
genDE4 : if (BOARD = BOARD_DE4) generate
OverTemperature_sync <= '0';
UserTemperature_sync <= '1';
end generate;
-- timer for warm-up control
-- ==========================================================================================================================================================
TC : entity PoC.io_TimingCounter
generic map (
TIMING_TABLE => (0 => CLOCK_FREQ/TIME_STARTUP_INVERSE) -- timing table
)
port map (
Clock => Clock, -- clock
Enable => StartUp, -- enable counter
Load => '0', -- load Timing Value from TIMING_TABLE selected by slot
Slot => 0, --
Timeout => TC_Timeout -- timing reached
);
StartUp <= not TC_Timeout;
process(StartUp, UserTemperature_sync, OverTemperature_sync)
begin
if (StartUp = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%; start up
elsif (OverTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION) - 1, PWM_RESOLUTION); -- 100%
elsif (UserTemperature_sync = '1') then PWM_PWMIn <= to_slv(2**(PWM_RESOLUTION - 1), PWM_RESOLUTION); -- 50%
else PWM_PWMIn <= to_slv(4, PWM_RESOLUTION); -- 13%
end if;
end process;
end generate;
-- PWM signal modulator
-- ==========================================================================================================================================================
PWM : entity PoC.io_PulseWidthModulation
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
PWM_FREQ => PWM_FREQ, --
PWM_RESOLUTION => PWM_RESOLUTION --
)
port map (
Clock => Clock,
Reset => Reset,
PWMIn => PWM_PWMIn,
PWMOut => PWM_PWMOut
);
-- registered output
Fan_PWM <= PWM_PWMOut when rising_edge(Clock);
-- tacho signal interpretation -> convert to RPM
-- ==========================================================================================================================================================
genNoTacho : if (ENABLE_TACHO = FALSE) generate
TachoFrequency <= (TachoFrequency'range => 'X');
end generate;
genTacho : if (ENABLE_TACHO = TRUE) generate
signal Tacho_sync : STD_LOGIC;
signal Tacho_Freq : STD_LOGIC_VECTOR(TACHO_RESOLUTION - 1 downto 0);
begin
-- Input Synchronization
genNoSync : if (ADD_INPUT_SYNCHRONIZERS = FALSE) generate
Tacho_sync <= Fan_Tacho;
end generate;
genSync : if (ADD_INPUT_SYNCHRONIZERS = TRUE) generate
sync_i : entity PoC.sync_Bits
port map (
Clock => Clock, -- Clock to be synchronized to
Input(0) => Fan_Tacho, -- Data to be synchronized
Output(0) => Tacho_sync -- synchronised data
);
end generate;
Tacho : entity PoC.io_FrequencyCounter
generic map (
CLOCK_FREQ => CLOCK_FREQ, --
TIMEBASE => (60 sec / 64), -- ca. 1 second
RESOLUTION => 8 -- max. ca. 256 RPS -> max. ca. 16k RPM
)
port map (
Clock => Clock,
Reset => Reset,
FreqIn => Tacho_sync,
FreqOut => Tacho_Freq
);
-- multiply by 64; divide by 2 for RPMs (2 impulses per revolution) => append 5x '0'
TachoFrequency <= resize(Tacho_Freq & "00000", TachoFrequency'length); -- resizing to 16 bit
end generate;
end;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity f_fun is
port(clk : in std_logic;
r_in : in std_logic_vector(31 downto 0);
k_in : in std_logic_vector(47 downto 0);
r_out : out std_logic_vector(31 downto 0));
end f_fun;
architecture Behavioral of f_fun is
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(31 downto 0);
op_2 : in std_logic_vector(31 downto 0);
op_3 : out std_logic_vector(31 downto 0));
end component;
component dsp_xor_48 is
port (clk : in std_logic;
op_1 : in std_logic_vector(47 downto 0);
op_2 : in std_logic_vector(47 downto 0);
op_3 : out std_logic_vector(47 downto 0));
end component;
COMPONENT s_box_dram_1
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_2
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_3
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_4
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_5
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_6
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_7
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_8
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_l_dual_dram
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
signal blk_exp_s : std_logic_vector(47 downto 0);
signal post_exp_key_add_s : std_logic_vector(47 downto 0);
signal post_s_box_s : std_logic_vector(31 downto 0);
begin
-- E
blk_exp_s <= r_in(0) & r_in(31) & r_in(30) & r_in(29) & r_in(28) & r_in(27) &
r_in(28) & r_in(27) & r_in(26) & r_in(25) & r_in(24) & r_in(23) &
r_in(24) & r_in(23) & r_in(22) & r_in(21) & r_in(20) & r_in(19) &
r_in(20) & r_in(19) & r_in(18) & r_in(17) & r_in(16) & r_in(15) &
r_in(16) & r_in(15) & r_in(14) & r_in(13) & r_in(12) & r_in(11) &
r_in(12) & r_in(11) & r_in(10) & r_in(9) & r_in(8) & r_in(7) &
r_in(8) & r_in(7) & r_in(6) & r_in(5) & r_in(4) & r_in(3) &
r_in(4) & r_in(3) & r_in(2) & r_in(1) & r_in(0) & r_in(31);
post_exp_key_add_s <= blk_exp_s xor k_in;
S_BOX_0 : s_box_l_dual_dram port map (post_exp_key_add_s(47 downto 42),
(others => '0'),
post_exp_key_add_s(41 downto 36),
clk,
'0',
post_s_box_s(31 downto 28),
post_s_box_s(27 downto 24));
S_BOX_1 : s_box_l_dual_dram port map (post_exp_key_add_s(35 downto 30),
(others => '0'),
post_exp_key_add_s(29 downto 24),
clk,
'0',
post_s_box_s(23 downto 20),
post_s_box_s(19 downto 16));
S_BOX_2 : s_box_l_dual_dram port map (post_exp_key_add_s(23 downto 18),
(others => '0'),
post_exp_key_add_s(17 downto 12),
clk,
'0',
post_s_box_s(15 downto 12),
post_s_box_s(11 downto 8));
S_BOX_3 : s_box_l_dual_dram port map (post_exp_key_add_s(11 downto 6),
(others => '0'),
post_exp_key_add_s(5 downto 0),
clk,
'0',
post_s_box_s(7 downto 4),
post_s_box_s(3 downto 0));
r_out <= post_s_box_s(16) & post_s_box_s(25) & post_s_box_s(12) & post_s_box_s(11) & post_s_box_s(3) & post_s_box_s(20) & post_s_box_s(4) & post_s_box_s(15) &
post_s_box_s(31) & post_s_box_s(17) & post_s_box_s(9) & post_s_box_s(6) & post_s_box_s(27) & post_s_box_s(14) & post_s_box_s(1) & post_s_box_s(22) &
post_s_box_s(30) & post_s_box_s(24) & post_s_box_s(8) & post_s_box_s(18) & post_s_box_s(0) & post_s_box_s(5) & post_s_box_s(29) & post_s_box_s(23) &
post_s_box_s(13) & post_s_box_s(19) & post_s_box_s(2) & post_s_box_s(26) & post_s_box_s(10) & post_s_box_s(21) & post_s_box_s(28) & post_s_box_s(7);
end Behavioral;
|
-- This is the implementation of a constant delay
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
package const_delay_pkg is
component const_delay
generic(
data_width : integer;
delay_in_clks : integer
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end component;
end const_delay_pkg;
package body const_delay_pkg is
end const_delay_pkg;
-- Entity Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity const_delay is
generic(
data_width : integer := 16;
delay_in_clks : integer := 10
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
data_i : in std_logic_vector(data_width-1 downto 0);
data_str_i : in std_logic;
data_o : out std_logic_vector(data_width-1 downto 0);
data_str_o : out std_logic
);
end const_delay;
architecture const_delay_arch of const_delay is
type register_line is array(0 to delay_in_clks-1) of std_logic_vector(data_width-1 downto 0);
type data_str_line is array(0 to delay_in_clks-1) of std_logic;
signal data_int : register_line;
signal data_str_int : data_str_line;
begin
process (clk_i, rst_i)
begin
if rst_i = '1' then
for i in 0 to delay_in_clks-1 loop
data_int(i) <= (others => '0');
data_str_int(i) <= '0';
end loop;
elsif clk_i'EVENT and clk_i = '1' then
data_int(0) <= data_i;
data_str_int(0) <= data_str_i;
for i in 0 to delay_in_clks-2 loop
data_int(i+1) <= data_int(i);
data_str_int(i+1) <= data_str_int(i);
end loop;
end if;
end process;
data_o <= data_int(delay_in_clks-1);
data_str_o <= data_str_int(delay_in_clks-1);
end const_delay_arch; |
library verilog;
use verilog.vl_types.all;
entity proc_vlg_check_tst is
port(
BusWires : in vl_logic_vector(15 downto 0);
Done : in vl_logic;
sampler_rx : in vl_logic
);
end proc_vlg_check_tst;
|
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|
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|
`protect begin_protected
`protect version = 1
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`protect end_protected
|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect key_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1794.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s07b00x00p06n02i01794ent IS
END c09s07b00x00p06n02i01794ent;
ARCHITECTURE c09s07b00x00p06n02i01794arch OF c09s07b00x00p06n02i01794ent IS
procedure i_proof_1 (x : real) is
begin
end i_proof_1;
BEGIN
glabel1 : FOR i in 0.0 to 8.0 generate
i_proof_1(i);
end generate glabel1;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s07b00x00p06n02i01794 - The generate parameter type should be the base type of the discrete range of the generate parameter specification."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s07b00x00p06n02i01794arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1794.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s07b00x00p06n02i01794ent IS
END c09s07b00x00p06n02i01794ent;
ARCHITECTURE c09s07b00x00p06n02i01794arch OF c09s07b00x00p06n02i01794ent IS
procedure i_proof_1 (x : real) is
begin
end i_proof_1;
BEGIN
glabel1 : FOR i in 0.0 to 8.0 generate
i_proof_1(i);
end generate glabel1;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s07b00x00p06n02i01794 - The generate parameter type should be the base type of the discrete range of the generate parameter specification."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s07b00x00p06n02i01794arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1794.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s07b00x00p06n02i01794ent IS
END c09s07b00x00p06n02i01794ent;
ARCHITECTURE c09s07b00x00p06n02i01794arch OF c09s07b00x00p06n02i01794ent IS
procedure i_proof_1 (x : real) is
begin
end i_proof_1;
BEGIN
glabel1 : FOR i in 0.0 to 8.0 generate
i_proof_1(i);
end generate glabel1;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s07b00x00p06n02i01794 - The generate parameter type should be the base type of the discrete range of the generate parameter specification."
severity NOTE;
wait;
END PROCESS TESTING;
END c09s07b00x00p06n02i01794arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity dut_dmul_64ns_64ns_64_6_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of dut_dmul_64ns_64ns_64_6_max_dsp is
--------------------- Component ---------------------
component dut_ap_dmul_4_max_dsp is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
dut_ap_dmul_4_max_dsp_u : component dut_ap_dmul_4_max_dsp
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.2
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity dut_dmul_64ns_64ns_64_6_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of dut_dmul_64ns_64ns_64_6_max_dsp is
--------------------- Component ---------------------
component dut_ap_dmul_4_max_dsp is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
dut_ap_dmul_4_max_dsp_u : component dut_ap_dmul_4_max_dsp
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: word_aligner
-- File: word_aligner.vhd
-- Author: Pascal Trotta
-- Description: generic SGMII comma detector and word aligner for serdes
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity word_aligner is
generic(
comma : std_logic_vector(9 downto 3) := "0011111");
port(
clk : in std_logic; -- rx clock
rstn : in std_logic; -- asynchronous reset
rx_in : in std_logic_vector(9 downto 0); -- Data in
val_in : in std_logic; -- Data in valid
rx_out : out std_logic_vector(9 downto 0); -- Data out
val_out : out std_logic; -- Data out valid
aligned : out std_logic); -- Data aligned
end entity;
architecture word_arch of word_aligner is
type state_type is (idle, fill_second, find_align, fix_align);
type mux_sel is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
type reg is record
val : std_logic;
state : state_type;
alignment_sel : mux_sel;
q0 : std_logic_vector(9 downto 0);
q1 : std_logic_vector(9 downto 0);
end record;
type out_sig is record
rx_out : std_logic_vector(9 downto 0);
val_out : std_logic;
aligned : std_logic;
end record;
signal regs, regin : reg;
begin
combp: process(regs, rx_in, val_in)
variable regv : reg;
variable outv : out_sig;
variable q1q0 : std_logic_vector(19 downto 0);
begin
regv := regs;
outv.aligned := '0';
outv.rx_out := rx_in;--(9 downto 0);
q1q0 := regv.q1 & regv.q0;
case regv.state is
when idle =>
if val_in = '1' then
regv.state := fill_second; --when first data valid wait another clock cycle to fill the second register q1
end if;
when fill_second =>
regv.state := find_align;
when find_align =>
regv.state := fix_align;
if q1q0(18 downto 12) = comma then
regv.alignment_sel:=S0;
elsif q1q0(17 downto 11) = comma then
regv.alignment_sel:=S1;
elsif q1q0(16 downto 10) = comma then
regv.alignment_sel:=S2;
elsif q1q0(15 downto 9) = comma then
regv.alignment_sel:=S3;
elsif q1q0(14 downto 8) = comma then
regv.alignment_sel:=S4;
elsif q1q0(13 downto 7) = comma then
regv.alignment_sel:=S5;
elsif q1q0(12 downto 6) = comma then
regv.alignment_sel:=S6;
elsif q1q0(11 downto 5) = comma then
regv.alignment_sel:=S7;
elsif q1q0(10 downto 4) = comma then
regv.alignment_sel:=S8;
elsif q1q0(9 downto 3) = comma then
regv.alignment_sel:=S9;
else
regv.state := find_align; -- comma not found and still not aligned
end if;
when fix_align => -- fix the alignment until rstn
regv.state := fix_align;
outv.aligned := '1';
case regv.alignment_sel is
when S0 =>
outv.rx_out := q1q0(18 downto 9);
when S1 =>
outv.rx_out := q1q0(17 downto 8);
when S2 =>
outv.rx_out := q1q0(16 downto 7);
when S3 =>
outv.rx_out := q1q0(15 downto 6);
when S4 =>
outv.rx_out := q1q0(14 downto 5);
when S5 =>
outv.rx_out := q1q0(13 downto 4);
when S6 =>
outv.rx_out := q1q0(12 downto 3);
when S7 =>
outv.rx_out := q1q0(11 downto 2);
when S8 =>
outv.rx_out := q1q0(10 downto 1);
when S9 =>
outv.rx_out := q1q0(9 downto 0);
end case;
end case;
outv.val_out := outv.aligned and regv.val;
regv.val := val_in;
regv.q1 := regv.q0;
regv.q0 := rx_in;
-- internal registers and outputs assignments
regin <= regv;
aligned <= outv.aligned;
val_out <= outv.val_out;
rx_out <= outv.rx_out;
end process;
regp: process(clk, rstn)
begin
if rstn = '0' then
regs.val <= '0';
regs.state <= idle;
regs.alignment_sel <= S0;
regs.q0 <= (others =>'0');
regs.q1 <= (others =>'0');
elsif rising_edge(clk) then
regs <= regin;
end if;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_15 is
generic ( extended_reset : boolean := false );
end entity inline_15;
----------------------------------------------------------------
architecture test of inline_15 is
signal functional_reset, equivalent_reset : bit := '0';
begin
block_3_r : block is
port ( reset : out bit );
port map ( reset => functional_reset );
begin
-- code from book:
reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
'1', '0' after 50 ns;
-- end of code from book
end block block_3_r;
----------------
block_3_s : block is
port ( reset : out bit );
port map ( reset => equivalent_reset );
begin
-- code from book:
reset_gen : process is
begin
if extended_reset then
reset <= '1', '0' after 200 ns;
else
reset <= '1', '0' after 50 ns;
end if;
wait;
end process reset_gen;
-- end of code from book
end block block_3_s;
----------------
verifier :
assert functional_reset = equivalent_reset
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_15 is
generic ( extended_reset : boolean := false );
end entity inline_15;
----------------------------------------------------------------
architecture test of inline_15 is
signal functional_reset, equivalent_reset : bit := '0';
begin
block_3_r : block is
port ( reset : out bit );
port map ( reset => functional_reset );
begin
-- code from book:
reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
'1', '0' after 50 ns;
-- end of code from book
end block block_3_r;
----------------
block_3_s : block is
port ( reset : out bit );
port map ( reset => equivalent_reset );
begin
-- code from book:
reset_gen : process is
begin
if extended_reset then
reset <= '1', '0' after 200 ns;
else
reset <= '1', '0' after 50 ns;
end if;
wait;
end process reset_gen;
-- end of code from book
end block block_3_s;
----------------
verifier :
assert functional_reset = equivalent_reset
report "Functional and equivalent models give different results";
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_15 is
generic ( extended_reset : boolean := false );
end entity inline_15;
----------------------------------------------------------------
architecture test of inline_15 is
signal functional_reset, equivalent_reset : bit := '0';
begin
block_3_r : block is
port ( reset : out bit );
port map ( reset => functional_reset );
begin
-- code from book:
reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
'1', '0' after 50 ns;
-- end of code from book
end block block_3_r;
----------------
block_3_s : block is
port ( reset : out bit );
port map ( reset => equivalent_reset );
begin
-- code from book:
reset_gen : process is
begin
if extended_reset then
reset <= '1', '0' after 200 ns;
else
reset <= '1', '0' after 50 ns;
end if;
wait;
end process reset_gen;
-- end of code from book
end block block_3_s;
----------------
verifier :
assert functional_reset = equivalent_reset
report "Functional and equivalent models give different results";
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_214 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_214;
architecture augh of sub_214 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_214 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_214;
architecture augh of sub_214 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
------------------------------------------------------------------------------
-- Title : Wishbone Ethernet MAC Wrapper
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-26-08
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone Wrapper for RS232 Master
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-26-08 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
entity xwb_rs232_syscon is
generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rstn_i : in std_logic;
-- External ports
rs232_rxd_i : in std_logic;
rs232_txd_o : out std_logic;
-- Reset to FPGA logic
rstn_o : out std_logic;
-- WISHBONE master
wb_master_i : in t_wishbone_master_in;
wb_master_o : out t_wishbone_master_out
);
end xwb_rs232_syscon;
architecture rtl of xwb_rs232_syscon is
begin
cmp_wb_rs232_syscon : wb_rs232_syscon
generic map (
g_ma_interface_mode => g_ma_interface_mode,
g_ma_address_granularity => g_ma_address_granularity
)
port map(
-- WISHBONE common
wb_clk_i => wb_clk_i,
wb_rstn_i => wb_rstn_i,
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rstn_o,
-- WISHBONE master
m_wb_adr_o => wb_master_o.adr,
m_wb_sel_o => wb_master_o.sel,
m_wb_we_o => wb_master_o.we,
m_wb_dat_o => wb_master_o.dat,
m_wb_dat_i => wb_master_i.dat,
m_wb_cyc_o => wb_master_o.cyc,
m_wb_stb_o => wb_master_o.stb,
m_wb_ack_i => wb_master_i.ack,
m_wb_err_i => wb_master_i.err,
m_wb_stall_i => wb_master_i.stall,
m_wb_rty_i => wb_master_i.rty
);
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2473.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n02i02473ent IS
END c07s03b02x02p13n02i02473ent;
ARCHITECTURE c07s03b02x02p13n02i02473arch OF c07s03b02x02p13n02i02473ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_UP is UNCONSTRAINED_ARRAY ( 1 to 10 );
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
function F_bad (C : CA_UP) return CA_DOWN is
begin
return CA_DOWN'((1 to 15 => 'B')); -- failure_here
end F_bad;
BEGIN
TESTING: PROCESS
BEGIN
F_bad("niuniuniun");
assert FALSE
report "***FAILED TEST: c07s03b02x02p13n02i02473 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n02i02473arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2473.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n02i02473ent IS
END c07s03b02x02p13n02i02473ent;
ARCHITECTURE c07s03b02x02p13n02i02473arch OF c07s03b02x02p13n02i02473ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_UP is UNCONSTRAINED_ARRAY ( 1 to 10 );
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
function F_bad (C : CA_UP) return CA_DOWN is
begin
return CA_DOWN'((1 to 15 => 'B')); -- failure_here
end F_bad;
BEGIN
TESTING: PROCESS
BEGIN
F_bad("niuniuniun");
assert FALSE
report "***FAILED TEST: c07s03b02x02p13n02i02473 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n02i02473arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2473.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p13n02i02473ent IS
END c07s03b02x02p13n02i02473ent;
ARCHITECTURE c07s03b02x02p13n02i02473arch OF c07s03b02x02p13n02i02473ent IS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CA_UP is UNCONSTRAINED_ARRAY ( 1 to 10 );
subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
function F_bad (C : CA_UP) return CA_DOWN is
begin
return CA_DOWN'((1 to 15 => 'B')); -- failure_here
end F_bad;
BEGIN
TESTING: PROCESS
BEGIN
F_bad("niuniuniun");
assert FALSE
report "***FAILED TEST: c07s03b02x02p13n02i02473 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p13n02i02473arch;
|
---------------------------------------------------------
-- MC613 - UNICAMP
--
-- Minesweeper
--
-- Caian Benedicto
-- Brunno Rodrigues Arangues
---------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.all;
entity game_ctrlunit is
port(
-- Comum
clock, rstn : in std_logic;
-- Conexao com a memoria principal
ram_data_out : in std_logic_vector(7 downto 0);
ram_wren : out std_logic;
ram_data_in : out std_logic_vector(7 downto 0);
ram_addr : buffer std_logic_vector(10 downto 0);
-- Conexao com a pilha
stack_data_out : in std_logic_vector(13 downto 0);
stack_empty : in std_logic;
stack_mode : out std_logic_vector(1 downto 0);
stack_data_in : buffer std_logic_vector(13 downto 0);
-- Conexao com o RNG
rng_x, rng_y : in std_logic_vector(4 downto 0);
rng_enable : out std_logic;
-- Conexao com o contador de tempo
timer_enable : out std_logic;
-- Conexao com o contador de minas
-- minecnt_enable : out std_logic;
-- minecnt_mode : out std_logic;
flagcnt : buffer std_logic_vector(10 downto 0);
num_mines : in std_logic_vector(8 downto 0);
-- Estado do jogo
game_state : buffer std_logic_vector(1 downto 0);
-- Estado do mouse
mouse_pos_x, mouse_pos_y : in std_logic_vector(9 downto 0);
mouse_click_l, mouse_click_r : in std_logic
);
end entity;
architecture game_ctrlunit_logic of game_ctrlunit is
type State_type IS (
S_0, -- Estado inicial
S_IClr, S_IRng, S_IRdM, S_IChkM, S_IWrM, -- Geracao de minas
S_IRdN, S_IChkN, S_IIncN, S_IWrN, -- Geracao de vizinhos
S_MW, S_MHL, S_MHR, S_MR, S_ML, S_MOpen, -- Botoes do mouse
S_SAmPush, S_SAmProc, S_SAmUpdate, S_SAmOpen, -- SAm
S_GameOver -- Fim de jogo
);
signal st : State_type;
signal buttons_state : std_logic_vector(1 downto 0);
--constant num_mines : natural := 20;
constant num_field : natural := 672;
begin
process(clock, rstn)
variable lin : std_logic_vector(4 downto 0);
variable col : std_logic_vector(5 downto 0);
variable mines : integer range 0 to num_field;
variable free : integer range 0 to num_field;
variable cnt : natural range 0 to 7;
begin
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
if rstn = '0' then
st <= S_0;
ram_wren <= '0';
ram_addr <= (others => '0');
ram_data_in <= (others => '0');
stack_mode <= "00";
stack_data_in <= (others => '0');
buttons_state <= "00";
game_state <= "00";
rng_enable <= '0';
timer_enable <= '0';
-- minecnt_enable <= '0';
-- minecnt_mode <= '0';
flagcnt <= "00" & num_mines;
lin := "00111";
col := "000100";
mines := to_integer(unsigned(num_mines));
free := num_field;
cnt := 0;
---------------------------------------------------------------------------
-- Clock
---------------------------------------------------------------------------
elsif rising_edge(clock) then
ram_wren <= '0';
ram_data_in <= (others => '0');
stack_mode <= "00";
stack_data_in <= (others => '0');
-- minecnt_enable <= '0';
-- minecnt_mode <= '0';
case st is
---------------------------------------------------------------------------
-- Estado inicial
---------------------------------------------------------------------------
when S_0 =>
st <= S_IClr;
---------------------------------------------------------------------------
--
--
-- Inicializacao do Campo
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Limpa o campo
---------------------------------------------------------------------------
when S_IClr =>
st <= S_IClr;
ram_wren <= '1';
ram_addr <= lin & col;
ram_data_in <= "01000000";
if col = 35 then
if lin = 27 then
st <= S_IRng;
rng_enable <= '1';
else
lin := lin + 1;
end if;
col := "000100";
else
col := col + 1;
end if;
---------------------------------------------------------------------------
-- Gera posicoes aleatorias (ou quase)
---------------------------------------------------------------------------
when S_IRng =>
st <= S_IRdM;
if free = (num_field - mines) then
st <= S_MW;
else
if rng_y > 20 then
st <= S_IRng;
else
ram_addr <= (rng_y + 7) & (('0' & rng_x) + 4);
end if;
end if;
---------------------------------------------------------------------------
-- Le a posicao da memoria
---------------------------------------------------------------------------
when S_IRdM =>
st <= S_IChkM;
---------------------------------------------------------------------------
-- Verifica se ja nao eh uma mina
---------------------------------------------------------------------------
when S_IChkM =>
st <= S_IWrM;
if ram_data_out(7 downto 6) = "01" and
ram_data_out(3 downto 0) /= "1111" then
--mines := mines - 1;
free := free - 1;
cnt := 0;
ram_data_in <= "01001111";
ram_wren <= '1';
else
st <= S_IRng;
end if;
---------------------------------------------------------------------------
-- Escreve posicao de memoria
---------------------------------------------------------------------------
when S_IWrM =>
st <= S_IChkN;
---------------------------------------------------------------------------
-- Calcula endereco do vizinho
---------------------------------------------------------------------------
when S_IChkN =>
case cnt is
when 0 => ram_addr <= (ram_addr(10 downto 6) + 1) &
(ram_addr( 5 downto 0) );
when 1 => ram_addr <= (ram_addr(10 downto 6) ) &
(ram_addr( 5 downto 0) + 1);
when 2 => ram_addr <= (ram_addr(10 downto 6) - 1) &
(ram_addr( 5 downto 0) );
when 3 => ram_addr <= (ram_addr(10 downto 6) - 1) &
(ram_addr( 5 downto 0) );
when 4 => ram_addr <= (ram_addr(10 downto 6) ) &
(ram_addr( 5 downto 0) - 1);
when 5 => ram_addr <= (ram_addr(10 downto 6) ) &
(ram_addr( 5 downto 0) - 1);
when 6 => ram_addr <= (ram_addr(10 downto 6) + 1) &
(ram_addr( 5 downto 0) );
when 7 => ram_addr <= (ram_addr(10 downto 6) + 1) &
(ram_addr( 5 downto 0) );
end case;
cnt := cnt + 1;
st <= S_IRdN;
---------------------------------------------------------------------------
-- Le o vizinho
---------------------------------------------------------------------------
when S_IRdN =>
st <= S_IIncN;
---------------------------------------------------------------------------
-- Verifica se eh um quadrado normal e incrementa o contador de minas
---------------------------------------------------------------------------
when S_IIncN =>
st <= S_IWrN;
if ram_data_out(7 downto 6) = "01" and
ram_data_out(3 downto 0) /= "1111" then
ram_wren <= '1';
ram_data_in <= ram_data_out(7 downto 4) &
(ram_data_out(3 downto 0) + 1);
end if;
---------------------------------------------------------------------------
-- Escreve o novo numero de minas vistas pelo campo
---------------------------------------------------------------------------
when S_IWrN =>
if cnt = 0 then
st <= S_IRng;
else
st <= S_IChkN;
end if;
---------------------------------------------------------------------------
--
--
-- Tratamento de Botoes
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Aguarda botoes
---------------------------------------------------------------------------
when S_MW =>
if free = 0 then
game_state <= "11";
st <= s_GameOver;
else
buttons_state(1) <= mouse_click_l;
buttons_state(0) <= mouse_click_r;
--ram_addr <= (others => '0');
ram_addr <= mouse_pos_y(8 downto 4) & mouse_pos_x(9 downto 4);
if (buttons_state(1) = '1') then
st <= S_MHL;
elsif (buttons_state(0) = '1') then
st <= S_MHR;
end if;
-- if (buttons_state(1) or buttons_state(0)) = '1' then
-- st <= S_MH;
-- else
-- st <= S_MW;
-- end if;
end if;
---------------------------------------------------------------------------
-- Load and Wait
---------------------------------------------------------------------------
when S_MHL =>
ram_addr <= mouse_pos_y(8 downto 4) &
mouse_pos_x(9 downto 4);
if (not mouse_click_l) = '1' then
st <= S_ML;
else
st <= S_MHL;
end if;
---------------------------------------------------------------------------
-- Load and Wait
---------------------------------------------------------------------------
when S_MHR =>
ram_addr <= mouse_pos_y(8 downto 4) &
mouse_pos_x(9 downto 4);
if (not mouse_click_r) = '1' then
st <= S_MR;
else
st <= S_MHR;
end if;
---------------------------------------------------------------------------
-- Right Mouse
---------------------------------------------------------------------------
when S_MR =>
st <= S_MW;
buttons_state(0) <= '0';
if ram_data_out(7 downto 6) = "01" and
ram_data_out(5) = '0' then
if (ram_data_out(4) = '1') then
flagcnt <= flagcnt + 1;
elsif (ram_data_out(4) = '0') then
flagcnt <= flagcnt - 1;
end if;
ram_wren <= '1';
ram_data_in(4) <= not ram_data_out(4);
ram_data_in(7 downto 5) <= ram_data_out(7 downto 5);
ram_data_in(3 downto 0) <= ram_data_out(3 downto 0);
end if;
---------------------------------------------------------------------------
-- Left Mouse
---------------------------------------------------------------------------
when S_ML =>
st <= S_MOpen;
---------------------------------------------------------------------------
-- Left Mouse
---------------------------------------------------------------------------
when S_MOpen =>
st <= S_MW;
buttons_state(1) <= '0';
if ram_data_out(7 downto 6) = "01" and
ram_data_out(5 downto 4) = "00" then
-- Inicia a contagem de tempo
timer_enable <= '1';
-- Atualiza a memoria principal
ram_wren <= '1';
ram_data_in(5) <= '1';
ram_data_in(7 downto 6) <= ram_data_out(7 downto 6);
ram_data_in(4 downto 0) <= ram_data_out(4 downto 0);
if ram_data_out(3 downto 0) = "1111" then
-- Fim do jogo
game_state <= "10";
st <= S_GameOver;
else
-- Decrementar contador de campos
free := free - 1;
if ram_data_out(3 downto 0) = "0000" then
-- Inicializa o SAm
stack_mode <= "01";
stack_data_in <= "000" & ram_addr;
st <= S_SAmPush;
end if;
end if;
end if;
---------------------------------------------------------------------------
--
--
-- SAm
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- SAm Push
---------------------------------------------------------------------------
when S_SAmPush =>
-- Aguarda a atualizacao da pilha
st <= S_SAmProc;
---------------------------------------------------------------------------
-- SAm Process
---------------------------------------------------------------------------
when S_SAmProc =>
if stack_empty = '1' then
-- Fim do processo de abertura recursiva
st <= S_MW;
else
st <= S_SAmUpdate;
-- Calcula o endereco do proximo elemento a ser empilhado
-- relativo ao elemento atual e seu contador na pilha
case stack_data_out(13 downto 11) is
when "000" => ram_addr <= (stack_data_out(10 downto 6) + 1) &
(stack_data_out(5 downto 0));
when "001" => ram_addr <= (stack_data_out(10 downto 6) + 1) &
(stack_data_out(5 downto 0) + 1);
when "010" => ram_addr <= (stack_data_out(10 downto 6)) &
(stack_data_out(5 downto 0) + 1);
when "011" => ram_addr <= (stack_data_out(10 downto 6) - 1) &
(stack_data_out(5 downto 0) + 1);
when "100" => ram_addr <= (stack_data_out(10 downto 6) - 1) &
(stack_data_out(5 downto 0));
when "101" => ram_addr <= (stack_data_out(10 downto 6) - 1) &
(stack_data_out(5 downto 0) - 1);
when "110" => ram_addr <= (stack_data_out(10 downto 6)) &
(stack_data_out(5 downto 0) - 1);
when "111" => ram_addr <= (stack_data_out(10 downto 6) + 1) &
(stack_data_out(5 downto 0) - 1);
end case;
if stack_data_out(13 downto 11) = "111" then
-- Remove o elemento atual da pilha ao percorrer todos
-- os elementos a sua volta
stack_mode <= "10";
else
-- Sobrescreve o elemento atual na pilha com o novo
-- contador de direcao
stack_mode <= "11";
stack_data_in <= (stack_data_out(13 downto 11) + 1) &
stack_data_out(10 downto 0);
end if;
end if;
---------------------------------------------------------------------------
-- SAm Update
---------------------------------------------------------------------------
when S_SAmUpdate =>
-- Aguarda a atualizacao da pilha (contador atual)
-- e a RAM (informacao sobre o elemento vizinho)
st <= S_SAmOpen;
---------------------------------------------------------------------------
-- SAm Open and Stack
---------------------------------------------------------------------------
when S_SAmOpen =>
st <= S_SAmPush;
if ram_data_out(7 downto 6) = "01" and
ram_data_out(5 downto 4) = "00" then
-- Decrementa contador de campos
free := free - 1;
-- Abre o elemento vizinho se for valido
ram_wren <= '1';
ram_data_in(5) <= '1';
ram_data_in(7 downto 6) <= ram_data_out(7 downto 6);
ram_data_in(4 downto 0) <= ram_data_out(4 downto 0);
if ram_data_out(3 downto 0) = "0000" then
-- Empilha o elemento vizinho se for vazio para
-- continuar a abrir os vizinhos dos outros
-- elementos vazios
stack_mode <= "01";
stack_data_in <= "000" & ram_addr;
end if;
end if;
---------------------------------------------------------------------------
--
--
-- Estado Final
--
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Fim do jogo
---------------------------------------------------------------------------
when S_GameOver =>
st <= S_GameOver;
-- Para a contagem de pontos
if game_state = "11" then
flagcnt <= (others => '0');
end if;
timer_enable <= '0';
---------------------------------------------------------------------------
-- ?
---------------------------------------------------------------------------
when others =>
st <= S_0;
end case;
end if;
end process;
end;
|
--
-- GPIOs on ml605
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(7 downto 0);
pbs_i : in std_logic_vector(4 downto 0);
leds_o : out std_logic_vector(12 downto 0)
);
end entity Top;
architecture RTL of Top is
begin
leds_o(4 downto 0) <= pbs_i;
leds_o(12 downto 5) <= dips_i;
end architecture RTL;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ad
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-rtl-conf-c.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ent_ad-rtl-conf-c.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ad_rtl_conf / ent_ad
--
configuration ent_ad_rtl_conf of ent_ad is
for rtl
-- Generated Configuration
end for;
end ent_ad_rtl_conf;
--
-- End of Generated Configuration ent_ad_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:29:16 01/17/2015
-- Design Name:
-- Module Name: D:/Docs/Xilinx/ConwayFinal/ConwayFinal_tb.vhd
-- Project Name: ConwayFinal
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ConwayFinal
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ConwayFinal_tb IS
END ConwayFinal_tb;
ARCHITECTURE behavior OF ConwayFinal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ConwayFinal
PORT(
clkin : IN std_logic;
dout : OUT std_logic_vector(7 downto 0);
hsync : OUT std_logic;
vsync : OUT std_logic
);
END COMPONENT;
--Inputs
signal clkin : std_logic := '0';
--Outputs
signal dout : std_logic_vector(7 downto 0);
signal hsync : std_logic;
signal vsync : std_logic;
-- Clock period definitions
constant clkin_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ConwayFinal PORT MAP (
clkin => clkin,
dout => dout,
hsync => hsync,
vsync => vsync
);
-- Clock process definitions
clkin_process :process
begin
clkin <= '0';
wait for clkin_period/2;
clkin <= '1';
wait for clkin_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clkin_period*10;
-- insert stimulus here
wait;
end process;
process (clkin)
file file_pointer: text is out "write.txt";
variable line_el: line;
begin
if rising_edge(clkin) then
-- Write the time
write(line_el, now); -- write the line.
write(line_el, ":"); -- write the line.
-- Write the hsync
write(line_el, " ");
write(line_el, hsync); -- write the line.
-- Write the vsync
write(line_el, " ");
write(line_el, vsync); -- write the line.
-- Write the red
write(line_el, " ");
write(line_el, dout(7 downto 5)); -- write the line.
-- Write the green
write(line_el, " ");
write(line_el, dout(5 downto 2)); -- write the line.
-- Write the blue
write(line_el, " ");
write(line_el, dout(2 downto 0)); -- write the line.
writeline(file_pointer, line_el); -- write the contents into the file.
end if;
end process;
END;
|
-------------------------------------------------------------------------------
--
-- $Id: vdp18_pack-p.vhd,v 1.14 2006/02/22 23:07:05 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package vdp18_pack is
-----------------------------------------------------------------------------
-- Subtype for horizontal/vertical counters/positions.
--
subtype hv_t is signed(0 to 8);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constants for first and last vertical line of NTSC and PAL mode.
--
constant hv_first_line_ntsc_c : hv_t := to_signed(-40, hv_t'length);
constant hv_last_line_ntsc_c : hv_t := to_signed(221, hv_t'length);
--
constant hv_first_line_pal_c : hv_t := to_signed(-65, hv_t'length);
constant hv_last_line_pal_c : hv_t := to_signed(247, hv_t'length);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constants for first and last horizontal pixel in text and graphics.
--
constant hv_first_pix_text_c : hv_t := to_signed(-102, hv_t'length); -- 342
constant hv_last_pix_text_c : hv_t := to_signed(239, hv_t'length);
--
constant hv_first_pix_graph_c : hv_t := to_signed(-86, hv_t'length); -- 342
constant hv_last_pix_graph_c : hv_t := to_signed(255, hv_t'length);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Miscellaneous constants for horizontal phases.
--
constant hv_vertical_inc_c : hv_t := to_signed(-32, hv_t'length);
constant hv_sprite_start_c : hv_t := to_signed(247, hv_t'length);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Operating modes of the VDP18 core.
--
type opmode_t is (OPMODE_GRAPH1, OPMODE_GRAPH2,
OPMODE_MULTIC, OPMODE_TEXTM);
--
constant opmode_graph1_c : std_logic_vector(0 to 2) := "000";
constant opmode_graph2_c : std_logic_vector(0 to 2) := "001";
constant opmode_multic_c : std_logic_vector(0 to 2) := "010";
constant opmode_textm_c : std_logic_vector(0 to 2) := "100";
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Access types.
--
type access_t is (-- pattern access
-- read Pattern Name Table
AC_PNT,
-- read Pattern Generator Table
AC_PGT,
-- read Pattern Color Table
AC_PCT,
-- sprite access
-- sprite test read (y coordinate)
AC_STST,
-- read Sprite Attribute Table/Y
AC_SATY,
-- read Sprite Attribute Table/X
AC_SATX,
-- read Sprite Attribute Table/N
AC_SATN,
-- read Sprite Attribute Table/C
AC_SATC,
-- read Sprite Pattern Table/high quadrant
AC_SPTH,
-- read Sprite Pattern Table/low quadrant
AC_SPTL,
--
-- CPU access
AC_CPU,
--
-- no access at all
AC_NONE
);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function enum_to_vec_f
--
-- Purpose:
-- Translate access_t enumeration type to std_logic_vector.
--
function enum_to_vec_f(enum : in access_t) return
std_logic_vector;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_boolean_f
--
-- Purpose:
-- Converts a std_logic value to boolean.
--
function to_boolean_f(val : in std_logic) return boolean;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_std_logic_f
--
-- Purpose:
-- Converts a boolean value to std_logic.
--
function to_std_logic_f(val : in boolean) return std_logic;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function mod_6_f
--
-- Purpose:
-- Calculate the modulo of 6.
-- Only the positive part is considered.
--
function mod_6_f(val : in hv_t) return hv_t;
--
-----------------------------------------------------------------------------
end vdp18_pack;
package body vdp18_pack is
-----------------------------------------------------------------------------
-- Function enum_to_vec_f
--
-- Purpose:
-- Translate access_t enumeration type to std_logic_vector.
--
function enum_to_vec_f(enum : in access_t) return
std_logic_vector is
variable result_v : std_logic_vector(3 downto 0);
begin
case enum is
when AC_NONE =>
result_v := "0000";
when AC_PNT =>
result_v := "0001";
when AC_PGT =>
result_v := "0010";
when AC_PCT =>
result_v := "0011";
when AC_STST =>
result_v := "0100";
when AC_SATY =>
result_v := "0101";
when AC_SATX =>
result_v := "0110";
when AC_SATN =>
result_v := "0111";
when AC_SATC =>
result_v := "1000";
when AC_SPTL =>
result_v := "1001";
when AC_SPTH =>
result_v := "1010";
when AC_CPU =>
result_v := "1111";
when others =>
result_v := "UUUU";
end case;
return result_v;
end;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_boolean_f
--
-- Purpose:
-- Converts a std_logic value to boolean.
--
function to_boolean_f(val : in std_logic) return boolean is
variable result_v : boolean;
begin
case to_X01(val) is
when '1' =>
result_v := true;
when '0' =>
result_v := false;
when others =>
result_v := false;
end case;
return result_v;
end;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_std_logic_f
--
-- Purpose:
-- Converts a boolean value to std_logic.
--
function to_std_logic_f(val : in boolean) return std_logic is
variable result_v : std_logic;
begin
case val is
when true =>
result_v := '1';
when false =>
result_v := '0';
end case;
return result_v;
end;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function mod_6_f
--
-- Purpose:
-- Calculate the modulo of 6.
-- Only the positive part is considered.
--
function mod_6_f(val : in hv_t) return hv_t is
variable mod_v : natural;
variable result_v : hv_t;
begin
if val(0) = '0' then
result_v := (others => '0');
mod_v := 0;
for idx in 0 to 255 loop
if val = idx then
result_v := to_signed(mod_v, hv_t'length);
end if;
if mod_v < 5 then
mod_v := mod_v + 1;
else
mod_v := 0;
end if;
end loop;
else
result_v := (others => '-');
end if;
return result_v;
end;
--
-----------------------------------------------------------------------------
end vdp18_pack;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_pipe_misc_v6.vhd
-- Description: Misc PIPE module for Virtex6 PCIe Block
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_pipe_misc_v6 is
generic (
PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
);
port (
pipe_tx_rcvr_det_i : in std_logic;
pipe_tx_reset_i : in std_logic;
pipe_tx_rate_i : in std_logic;
pipe_tx_deemph_i : in std_logic;
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
pipe_tx_swing_i : in std_logic;
pipe_tx_rcvr_det_o : out std_logic;
pipe_tx_reset_o : out std_logic;
pipe_tx_rate_o : out std_logic;
pipe_tx_deemph_o : out std_logic;
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
pipe_tx_swing_o : out std_logic;
pipe_clk : in std_logic;
rst_n : in std_logic
);
end pcie_pipe_misc_v6;
architecture v6_pcie of pcie_pipe_misc_v6 is
--******************************************************************//
-- Reality check. //
--******************************************************************//
constant TCQ : integer := 1; -- clock to out delay model
signal pipe_tx_rcvr_det_q : std_logic;
signal pipe_tx_reset_q : std_logic;
signal pipe_tx_rate_q : std_logic;
signal pipe_tx_deemph_q : std_logic;
signal pipe_tx_margin_q : std_logic_vector(2 downto 0);
signal pipe_tx_swing_q : std_logic;
signal pipe_tx_rcvr_det_qq : std_logic;
signal pipe_tx_reset_qq : std_logic;
signal pipe_tx_rate_qq : std_logic;
signal pipe_tx_deemph_qq : std_logic;
signal pipe_tx_margin_qq : std_logic_vector(2 downto 0);
signal pipe_tx_swing_qq : std_logic;
begin
v6pcie0 : if (PIPE_PIPELINE_STAGES = 0) generate
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_i;
pipe_tx_reset_o <= pipe_tx_reset_i;
pipe_tx_rate_o <= pipe_tx_rate_i;
pipe_tx_deemph_o <= pipe_tx_deemph_i;
pipe_tx_margin_o <= pipe_tx_margin_i;
pipe_tx_swing_o <= pipe_tx_swing_i;
end generate;
v6pcie1 : if (PIPE_PIPELINE_STAGES = 1) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
else
pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_q;
pipe_tx_reset_o <= pipe_tx_reset_q;
pipe_tx_rate_o <= pipe_tx_rate_q;
pipe_tx_deemph_o <= pipe_tx_deemph_q;
pipe_tx_margin_o <= pipe_tx_margin_q;
pipe_tx_swing_o <= pipe_tx_swing_q;
end generate;
v6pcie2 : if (PIPE_PIPELINE_STAGES = 2) generate
process (pipe_clk)
begin
if (pipe_clk'event and pipe_clk = '1') then
if (rst_n = '1') then
pipe_tx_rcvr_det_q <= '0' after (TCQ)*1 ps;
pipe_tx_reset_q <= '1' after (TCQ)*1 ps;
pipe_tx_rate_q <= '0' after (TCQ)*1 ps;
pipe_tx_deemph_q <= '1' after (TCQ)*1 ps;
pipe_tx_margin_q <= "000" after (TCQ)*1 ps;
pipe_tx_swing_q <= '0' after (TCQ)*1 ps;
pipe_tx_rcvr_det_qq <= '0' after (TCQ)*1 ps;
pipe_tx_reset_qq <= '1' after (TCQ)*1 ps;
pipe_tx_rate_qq <= '0' after (TCQ)*1 ps;
pipe_tx_deemph_qq <= '1' after (TCQ)*1 ps;
pipe_tx_margin_qq <= "000" after (TCQ)*1 ps;
pipe_tx_swing_qq <= '0' after (TCQ)*1 ps;
else
pipe_tx_rcvr_det_q <= pipe_tx_rcvr_det_i after (TCQ)*1 ps;
pipe_tx_reset_q <= pipe_tx_reset_i after (TCQ)*1 ps;
pipe_tx_rate_q <= pipe_tx_rate_i after (TCQ)*1 ps;
pipe_tx_deemph_q <= pipe_tx_deemph_i after (TCQ)*1 ps;
pipe_tx_margin_q <= pipe_tx_margin_i after (TCQ)*1 ps;
pipe_tx_swing_q <= pipe_tx_swing_i after (TCQ)*1 ps;
pipe_tx_rcvr_det_qq <= pipe_tx_rcvr_det_q after (TCQ)*1 ps;
pipe_tx_reset_qq <= pipe_tx_reset_q after (TCQ)*1 ps;
pipe_tx_rate_qq <= pipe_tx_rate_q after (TCQ)*1 ps;
pipe_tx_deemph_qq <= pipe_tx_deemph_q after (TCQ)*1 ps;
pipe_tx_margin_qq <= pipe_tx_margin_q after (TCQ)*1 ps;
pipe_tx_swing_qq <= pipe_tx_swing_q after (TCQ)*1 ps;
end if;
end if;
end process;
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_qq;
pipe_tx_reset_o <= pipe_tx_reset_qq;
pipe_tx_rate_o <= pipe_tx_rate_qq;
pipe_tx_deemph_o <= pipe_tx_deemph_qq;
pipe_tx_margin_o <= pipe_tx_margin_qq;
pipe_tx_swing_o <= pipe_tx_swing_qq;
end generate;
end v6_pcie;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myDemux2 is
port(a: in std_logic; sel: in std_logic; s: out std_logic; s2: out std_logic);
end myDemux2;
architecture behavioral of myDemux2 is
component myAnd2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
component myNot
port(a: in std_logic; s: out std_logic);
end component;
signal selNot: std_logic;
begin
myNot_1: myNot port map(a => sel, s => selNot);
myAnd2_1: myAnd2 port map(a => a, b => selNot, s => s);
myAnd2_2: myAnd2 port map(a => a, b => sel, s => s2);
end behavioral;
|
entity test is
end entity test;
architecture atest of test is
signal clk : integer;
begin
-- doesn't fire
main: process(clk)
begin
report "signal active";
end process;
clk <= clk after 1 us;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml50x is
constant BANK_WIDTH : integer := 2; -- # of memory bank addr bits.
constant CKE_WIDTH : integer := 2; -- # of memory clock enable outputs.
constant CLK_WIDTH : integer := 2; -- # of clock outputs.
constant COL_WIDTH : integer := 10; -- # of memory column bits.
constant CS_NUM : integer := 1; --2; -- # of separate memory chip selects.
constant CS_WIDTH : integer := 1; --2; -- # of total memory chip selects.
constant CS_BITS : integer := 0; --1; -- set to log2(CS_NUM) (rounded up).
constant DM_WIDTH : integer := 8; -- # of data mask bits.
constant DQ_WIDTH : integer := 64; -- # of data width.
constant DQ_PER_DQS : integer := 8; -- # of DQ data bits per strobe.
constant DQS_WIDTH : integer := 8; -- # of DQS strobes.
constant DQ_BITS : integer := 6; -- set to log2(DQS_WIDTH*DQ_PER_DQS).
constant DQS_BITS : integer := 3; -- set to log2(DQS_WIDTH).
constant ODT_WIDTH : integer := 1; -- # of memory on-die term enables.
constant ROW_WIDTH : integer := 13; -- # of memory row and # of addr bits.
constant APPDATA_WIDTH : integer := 128; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 31; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#F00#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component mig_36_1
generic(
BANK_WIDTH : integer := 2;
-- # of memory bank addr bits.
CKE_WIDTH : integer := 1;
-- # of memory clock enable outputs.
CLK_WIDTH : integer := 2;
-- # of clock outputs.
COL_WIDTH : integer := 10;
-- # of memory column bits.
CS_NUM : integer := 1;
-- # of separate memory chip selects.
CS_WIDTH : integer := 1;
-- # of total memory chip selects.
CS_BITS : integer := 0;
-- set to log2(CS_NUM) (rounded up).
DM_WIDTH : integer := 8;
-- # of data mask bits.
DQ_WIDTH : integer := 64;
-- # of data width.
DQ_PER_DQS : integer := 8;
-- # of DQ data bits per strobe.
DQS_WIDTH : integer := 8;
-- # of DQS strobes.
DQ_BITS : integer := 6;
-- set to log2(DQS_WIDTH*DQ_PER_DQS).
DQS_BITS : integer := 3;
-- set to log2(DQS_WIDTH).
ODT_WIDTH : integer := 1;
-- # of memory on-die term enables.
ROW_WIDTH : integer := 13;
-- # of memory row and # of addr bits.
ADDITIVE_LAT : integer := 0;
-- additive write latency.
BURST_LEN : integer := 4;
-- burst length (in double words).
BURST_TYPE : integer := 0;
-- burst type (=0 seq; =1 interleaved).
CAS_LAT : integer := 3;
-- CAS latency.
ECC_ENABLE : integer := 0;
-- enable ECC (=1 enable).
APPDATA_WIDTH : integer := 128;
-- # of usr read/write data bus bits.
MULTI_BANK_EN : integer := 1;
-- Keeps multiple banks open. (= 1 enable).
TWO_T_TIME_EN : integer := 1;
-- 2t timing for unbuffered dimms.
ODT_TYPE : integer := 1;
-- ODT (=0(none),=1(75),=2(150),=3(50)).
REDUCE_DRV : integer := 0;
-- reduced strength mem I/O (=1 yes).
REG_ENABLE : integer := 0;
-- registered addr/ctrl (=1 yes).
TREFI_NS : integer := 7800;
-- auto refresh interval (ns).
TRAS : integer := 40000;
-- active->precharge delay.
TRCD : integer := 15000;
-- active->read/write delay.
TRFC : integer := 105000;
-- refresh->refresh, refresh->active delay.
TRP : integer := 15000;
-- precharge->command delay.
TRTP : integer := 7500;
-- read->precharge delay.
TWR : integer := 15000;
-- used to determine write->precharge.
TWTR : integer := 10000;
-- write->read delay.
HIGH_PERFORMANCE_MODE : boolean := TRUE;
-- # = TRUE, the IODELAY performance mode is set
-- to high.
-- # = FALSE, the IODELAY performance mode is set
-- to low.
SIM_ONLY : integer := 0;
-- = 1 to skip SDRAM power up delay.
DEBUG_EN : integer := 0;
-- Enable debug signals/controls.
-- When this parameter is changed from 0 to 1,
-- make sure to uncomment the coregen commands
-- in ise_flow.bat or create_ise.bat files in
-- par folder.
CLK_PERIOD : integer := 5000;
-- Core/Memory clock period (in ps).
DLL_FREQ_MODE : string := "HIGH";
-- DCM Frequency range.
CLK_TYPE : string := "SINGLE_ENDED";
-- # = "DIFFERENTIAL " ->; Differential input clocks ,
-- # = "SINGLE_ENDED" -> Single ended input clocks.
NOCLK200 : boolean := FALSE;
-- clk200 enable and disable
RST_ACT_LOW : integer := 1
-- =1 for active low reset, =0 for active high.
);
port(
ddr2_dq : inout std_logic_vector((DQ_WIDTH-1) downto 0);
ddr2_a : out std_logic_vector((ROW_WIDTH-1) downto 0);
ddr2_ba : out std_logic_vector((BANK_WIDTH-1) downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_cs_n : out std_logic_vector((CS_WIDTH-1) downto 0);
ddr2_odt : out std_logic_vector((ODT_WIDTH-1) downto 0);
ddr2_cke : out std_logic_vector((CKE_WIDTH-1) downto 0);
ddr2_dm : out std_logic_vector((DM_WIDTH-1) downto 0);
sys_clk : in std_logic;
idly_clk_200 : in std_logic;
sys_rst_n : in std_logic;
phy_init_done : out std_logic;
rst0_tb : out std_logic;
clk0_tb : out std_logic;
app_wdf_afull : out std_logic;
app_af_afull : out std_logic;
rd_data_valid : out std_logic;
app_wdf_wren : in std_logic;
app_af_wren : in std_logic;
app_af_addr : in std_logic_vector(30 downto 0);
app_af_cmd : in std_logic_vector(2 downto 0);
rd_data_fifo_out : out std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_data : in std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_mask_data : in std_logic_vector((APPDATA_WIDTH/8-1) downto 0);
ddr2_dqs : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_dqs_n : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0)
);
end component ;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml50x.all;
entity ahb2mig_ml50x is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml50x is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(63 downto 0) & rdata(127 downto 64);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "01" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "10" => va.hrdata(31 downto 0) := rdata(127 downto 96);
when others => va.hrdata(31 downto 0) := rdata(95 downto 64);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
migi.app_addr <= "00000" & ra.acc.haddr(28 downto 5) & "00";
ddr_ctrl : process(rst_ddr, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask(15 downto 0) := ra.write(2) & ra.write(3) & ra.write(0) & ra.write(1);
app_wdf_data := (others => '0');
app_wdf_data(127 downto 0) := ra.hwdata(2) & ra.hwdata(3) & ra.hwdata(0) & ra.hwdata(1);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if (startsd = '1') and (migo.app_af_afull = '0') then
if ra.acc.hwrite = '0' then
v.dstate := dread; app_en := '1';
elsif migo.app_wdf_afull = '0' then
v.dstate := dwrite; app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 0) := migo.app_rd_data(127 downto 0);
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(255 downto 128) := migo.app_rd_data(127 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
app_wdf_mask(15 downto 0) := ra.write(6) & ra.write(7) & ra.write(4) & ra.write(5);
app_wdf_data(127 downto 0) := ra.hwdata(6) & ra.hwdata(7) & ra.hwdata(4) & ra.hwdata(5);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2mig
-- File: ahb2mig.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: AHB wrapper for Xilinx Virtex5 DDR2/3 MIG
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package ml50x is
constant BANK_WIDTH : integer := 2; -- # of memory bank addr bits.
constant CKE_WIDTH : integer := 2; -- # of memory clock enable outputs.
constant CLK_WIDTH : integer := 2; -- # of clock outputs.
constant COL_WIDTH : integer := 10; -- # of memory column bits.
constant CS_NUM : integer := 1; --2; -- # of separate memory chip selects.
constant CS_WIDTH : integer := 1; --2; -- # of total memory chip selects.
constant CS_BITS : integer := 0; --1; -- set to log2(CS_NUM) (rounded up).
constant DM_WIDTH : integer := 8; -- # of data mask bits.
constant DQ_WIDTH : integer := 64; -- # of data width.
constant DQ_PER_DQS : integer := 8; -- # of DQ data bits per strobe.
constant DQS_WIDTH : integer := 8; -- # of DQS strobes.
constant DQ_BITS : integer := 6; -- set to log2(DQS_WIDTH*DQ_PER_DQS).
constant DQS_BITS : integer := 3; -- set to log2(DQS_WIDTH).
constant ODT_WIDTH : integer := 1; -- # of memory on-die term enables.
constant ROW_WIDTH : integer := 13; -- # of memory row and # of addr bits.
constant APPDATA_WIDTH : integer := 128; -- # of usr read/write data bus bits.
constant ADDR_WIDTH : integer := 31; -- # of memory row and # of addr bits.
constant MIGHMASK : integer := 16#F00#; -- AHB mask for 256 Mbyte memory
-- constant MIGHMASK : integer := 16#E00#; -- AHB mask for 512 Mbyte memory
-- constant MIGHMASK : integer := 16#C00#; -- AHB mask for 1024 Mbyte memory
type mig_app_in_type is record
app_wdf_wren : std_logic;
app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : std_logic_vector(2 downto 0);
app_en : std_logic;
end record;
type mig_app_out_type is record
app_af_afull : std_logic;
app_wdf_afull : std_logic;
app_rd_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
app_rd_data_valid : std_logic;
end record;
component mig_36_1
generic(
BANK_WIDTH : integer := 2;
-- # of memory bank addr bits.
CKE_WIDTH : integer := 1;
-- # of memory clock enable outputs.
CLK_WIDTH : integer := 2;
-- # of clock outputs.
COL_WIDTH : integer := 10;
-- # of memory column bits.
CS_NUM : integer := 1;
-- # of separate memory chip selects.
CS_WIDTH : integer := 1;
-- # of total memory chip selects.
CS_BITS : integer := 0;
-- set to log2(CS_NUM) (rounded up).
DM_WIDTH : integer := 8;
-- # of data mask bits.
DQ_WIDTH : integer := 64;
-- # of data width.
DQ_PER_DQS : integer := 8;
-- # of DQ data bits per strobe.
DQS_WIDTH : integer := 8;
-- # of DQS strobes.
DQ_BITS : integer := 6;
-- set to log2(DQS_WIDTH*DQ_PER_DQS).
DQS_BITS : integer := 3;
-- set to log2(DQS_WIDTH).
ODT_WIDTH : integer := 1;
-- # of memory on-die term enables.
ROW_WIDTH : integer := 13;
-- # of memory row and # of addr bits.
ADDITIVE_LAT : integer := 0;
-- additive write latency.
BURST_LEN : integer := 4;
-- burst length (in double words).
BURST_TYPE : integer := 0;
-- burst type (=0 seq; =1 interleaved).
CAS_LAT : integer := 3;
-- CAS latency.
ECC_ENABLE : integer := 0;
-- enable ECC (=1 enable).
APPDATA_WIDTH : integer := 128;
-- # of usr read/write data bus bits.
MULTI_BANK_EN : integer := 1;
-- Keeps multiple banks open. (= 1 enable).
TWO_T_TIME_EN : integer := 1;
-- 2t timing for unbuffered dimms.
ODT_TYPE : integer := 1;
-- ODT (=0(none),=1(75),=2(150),=3(50)).
REDUCE_DRV : integer := 0;
-- reduced strength mem I/O (=1 yes).
REG_ENABLE : integer := 0;
-- registered addr/ctrl (=1 yes).
TREFI_NS : integer := 7800;
-- auto refresh interval (ns).
TRAS : integer := 40000;
-- active->precharge delay.
TRCD : integer := 15000;
-- active->read/write delay.
TRFC : integer := 105000;
-- refresh->refresh, refresh->active delay.
TRP : integer := 15000;
-- precharge->command delay.
TRTP : integer := 7500;
-- read->precharge delay.
TWR : integer := 15000;
-- used to determine write->precharge.
TWTR : integer := 10000;
-- write->read delay.
HIGH_PERFORMANCE_MODE : boolean := TRUE;
-- # = TRUE, the IODELAY performance mode is set
-- to high.
-- # = FALSE, the IODELAY performance mode is set
-- to low.
SIM_ONLY : integer := 0;
-- = 1 to skip SDRAM power up delay.
DEBUG_EN : integer := 0;
-- Enable debug signals/controls.
-- When this parameter is changed from 0 to 1,
-- make sure to uncomment the coregen commands
-- in ise_flow.bat or create_ise.bat files in
-- par folder.
CLK_PERIOD : integer := 5000;
-- Core/Memory clock period (in ps).
DLL_FREQ_MODE : string := "HIGH";
-- DCM Frequency range.
CLK_TYPE : string := "SINGLE_ENDED";
-- # = "DIFFERENTIAL " ->; Differential input clocks ,
-- # = "SINGLE_ENDED" -> Single ended input clocks.
NOCLK200 : boolean := FALSE;
-- clk200 enable and disable
RST_ACT_LOW : integer := 1
-- =1 for active low reset, =0 for active high.
);
port(
ddr2_dq : inout std_logic_vector((DQ_WIDTH-1) downto 0);
ddr2_a : out std_logic_vector((ROW_WIDTH-1) downto 0);
ddr2_ba : out std_logic_vector((BANK_WIDTH-1) downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_cs_n : out std_logic_vector((CS_WIDTH-1) downto 0);
ddr2_odt : out std_logic_vector((ODT_WIDTH-1) downto 0);
ddr2_cke : out std_logic_vector((CKE_WIDTH-1) downto 0);
ddr2_dm : out std_logic_vector((DM_WIDTH-1) downto 0);
sys_clk : in std_logic;
idly_clk_200 : in std_logic;
sys_rst_n : in std_logic;
phy_init_done : out std_logic;
rst0_tb : out std_logic;
clk0_tb : out std_logic;
app_wdf_afull : out std_logic;
app_af_afull : out std_logic;
rd_data_valid : out std_logic;
app_wdf_wren : in std_logic;
app_af_wren : in std_logic;
app_af_addr : in std_logic_vector(30 downto 0);
app_af_cmd : in std_logic_vector(2 downto 0);
rd_data_fifo_out : out std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_data : in std_logic_vector((APPDATA_WIDTH-1) downto 0);
app_wdf_mask_data : in std_logic_vector((APPDATA_WIDTH/8-1) downto 0);
ddr2_dqs : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_dqs_n : inout std_logic_vector((DQS_WIDTH-1) downto 0);
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0)
);
end component ;
end package;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
use work.ml50x.all;
entity ahb2mig_ml50x is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#e00#;
MHz : integer := 100;
Mbyte : integer := 512;
nosync : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
migi : out mig_app_in_type;
migo : in mig_app_out_type
);
end;
architecture rtl of ahb2mig_ml50x is
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type ddr_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
constant abuf : integer := 6;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(2 downto 0);
hwrite : std_ulogic;
end record;
-- local registers
type mem is array(0 to 7) of std_logic_vector(31 downto 0);
type wrm is array(0 to 7) of std_logic_vector(3 downto 0);
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
startsd : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(127 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(2 downto 0);
acc : access_param;
sync : std_ulogic;
hwdata : mem;
write : wrm;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
hrdata : std_logic_vector(255 downto 0);
sync : std_ulogic;
dstate : ahb_state_type;
end record;
signal vcc, clk_ahb1, clk_ahb2 : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal hwdata, hwdatab : std_logic_vector(127 downto 0);
begin
vcc <= '1';
ahb_ctrl : process(rst_ahb, ahbsi, r, ra, migo, hwdata)
variable va : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable ready : std_logic;
variable tmp : std_logic_vector(3 downto 0);
variable waddr : integer;
variable rdata : std_logic_vector(127 downto 0);
begin
va := ra; va.hresp := HRESP_OKAY;
tmp := (others => '0');
case ra.raddr(2 downto 2) is
when "0" => rdata := r.hrdata(127 downto 0);
when others => rdata := r.hrdata(255 downto 128);
end case;
if AHBDW > 64 and ra.size = HSIZE_4WORD then
va.hrdata := rdata(63 downto 0) & rdata(127 downto 64);
elsif AHBDW > 32 and ra.size = HSIZE_DWORD then
if ra.raddr(1) = '1' then va.hrdata(63 downto 0) := rdata(127 downto 64);
else va.hrdata(63 downto 0) := rdata(63 downto 0); end if;
va.hrdata(127 downto 64) := va.hrdata(63 downto 0);
else
case ra.raddr(1 downto 0) is
when "00" => va.hrdata(31 downto 0) := rdata(63 downto 32);
when "01" => va.hrdata(31 downto 0) := rdata(31 downto 0);
when "10" => va.hrdata(31 downto 0) := rdata(127 downto 96);
when others => va.hrdata(31 downto 0) := rdata(95 downto 64);
end case;
va.hrdata(127 downto 32) := va.hrdata(31 downto 0) &
va.hrdata(31 downto 0) &
va.hrdata(31 downto 0);
end if;
if nosync = 0 then
va.sync := r.startsd;
if ra.startsd = ra.sync then ready := '1';
else ready := '0'; end if;
else
if ra.startsd = r.startsd then ready := '1';
else ready := '0'; end if;
end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.htrans := ahbsi.htrans; va.haddr := ahbsi.haddr;
va.size := ahbsi.hsize(2 downto 0); va.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
va.hsel := '1'; va.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then va.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
va.write := (others => "0000");
if ((va.hsel and va.htrans(1)) = '1') then
if va.hwrite = '0' then
va.state := rhold; va.startsd := not ra.startsd;
else
va.state := dwrite; va.hready := '1';
end if;
end if;
va.raddr := ra.haddr(7 downto 2);
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
va.acc := (va.haddr, va.size, va.hwrite);
end if;
when rhold =>
va.raddr := ra.haddr(7 downto 2);
if ready = '1' then
va.state := dread; va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
end if;
when dread =>
va.hready := '1';
if AHBDW > 64 and ra.size(2) = '1' then va.raddr := ra.raddr + 4;
elsif AHBDW > 32 and andv(ra.size(1 downto 0)) = '1' then va.raddr := ra.raddr + 2;
else va.raddr := ra.raddr + 1; end if;
if ((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
va.state := midle; va.hready := '0';
end if;
va.acc := (va.haddr, va.size, va.hwrite);
when dwrite =>
va.raddr := ra.haddr(7 downto 2); va.hready := '1';
if (((va.hsel and va.htrans(1) and va.htrans(0)) = '0')
or (ra.haddr(4 downto 2) = "111")
or (AHBDW > 32 and ra.haddr(5 downto 2) = "1110" and andv(ra.size(1 downto 0)) = '1')
or (AHBDW > 64 and ra.haddr(5 downto 2) = "1100" and ra.size(2) = '1')) then
va.startsd := not ra.startsd; va.state := whold1;
va.hready := '0';
end if;
tmp := decode(ra.haddr(1 downto 0));
waddr := conv_integer(ra.haddr(4 downto 2));
va.hwdata(waddr) := hwdata(31 downto 0);
case ra.size is
when "000" => va.write(waddr) := tmp(0) & tmp(1) & tmp(2) & tmp(3);
when "001" => va.write(waddr) := tmp(0) & tmp(0) & tmp(2) & tmp(2);
when "010" => va.write(waddr) := "1111";
when "011" => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
when others => va.write(waddr) := "1111"; va.write(waddr+1) := "1111";
va.write(waddr+2) := "1111"; va.write(waddr+3) := "1111";
va.hwdata(waddr+1) := hwdata((63 mod AHBDW) downto (32 mod AHBDW));
va.hwdata(waddr+2) := hwdata((95 mod AHBDW) downto (64 mod AHBDW));
va.hwdata(waddr+3) := hwdata((127 mod AHBDW) downto (96 mod AHBDW));
end case;
when whold1 =>
va.state := whold2;
when whold2 =>
if ready = '1' then
va.state := midle; va.acc := (va.haddr, va.size, va.hwrite);
end if;
end case;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then va.hready := '1'; end if;
end if;
if rst_ahb = '0' then
va.hsel := '0';
va.hready := '1';
va.state := midle;
va.startsd := '0';
va.acc.hwrite := '0';
va.acc.haddr := (others => '0');
end if;
rai <= va;
end process;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= ahbdrivedata(ra.hrdata);
-- migi.app_addr <= '0' & ra.acc.haddr(28 downto 6) & "000";
migi.app_addr <= "00000" & ra.acc.haddr(28 downto 5) & "00";
ddr_ctrl : process(rst_ddr, r, ra, migo)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable app_en : std_ulogic;
variable app_cmd : std_logic_vector(2 downto 0);
variable app_wdf_mask : std_logic_vector(APPDATA_WIDTH/8-1 downto 0);
variable app_wdf_wren : std_ulogic;
variable app_wdf_data : std_logic_vector(APPDATA_WIDTH-1 downto 0);
begin
-- Variable default settings to avoid latches
v := r; app_en := '0'; app_cmd := "000"; app_wdf_wren := '0';
app_wdf_mask := (others => '0');
app_wdf_mask(15 downto 0) := ra.write(2) & ra.write(3) & ra.write(0) & ra.write(1);
app_wdf_data := (others => '0');
app_wdf_data(127 downto 0) := ra.hwdata(2) & ra.hwdata(3) & ra.hwdata(0) & ra.hwdata(1);
if ra.acc.hwrite = '0' then app_cmd(0) := '1'; else app_cmd(0) := '0'; end if;
v.sync := ra.startsd;
if nosync = 0 then
if r.startsd /= r.sync then startsd := '1';
else startsd := '0'; end if;
else
if ra.startsd /= r.startsd then startsd := '1';
else startsd := '0'; end if;
end if;
case r.dstate is
when midle =>
if (startsd = '1') and (migo.app_af_afull = '0') then
if ra.acc.hwrite = '0' then
v.dstate := dread; app_en := '1';
elsif migo.app_wdf_afull = '0' then
v.dstate := dwrite; app_en := '1'; app_wdf_wren := '1';
end if;
end if;
when dread =>
if migo.app_rd_data_valid = '1' then
v.hrdata(127 downto 0) := migo.app_rd_data(127 downto 0);
v.dstate := rhold;
end if;
when rhold =>
v.hrdata(255 downto 128) := migo.app_rd_data(127 downto 0);
v.dstate := midle;
v.startsd := not r.startsd;
when dwrite =>
app_wdf_wren := '1';
app_wdf_mask(15 downto 0) := ra.write(6) & ra.write(7) & ra.write(4) & ra.write(5);
app_wdf_data(127 downto 0) := ra.hwdata(6) & ra.hwdata(7) & ra.hwdata(4) & ra.hwdata(5);
v.startsd := not r.startsd;
v.dstate := midle;
when others =>
end case;
-- reset
if rst_ddr = '0' then
v.startsd := '0';
app_en := '0';
v.dstate := midle;
end if;
ri <= v;
migi.app_cmd <= app_cmd;
migi.app_en <= app_en;
migi.app_wdf_wren <= app_wdf_wren;
migi.app_wdf_mask <= not app_wdf_mask;
migi.app_wdf_data <= app_wdf_data;
end process;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
clk_ahb1 <= clk_ahb; clk_ahb2 <= clk_ahb1; -- sync clock deltas
ahbregs : process(clk_ahb2) begin
if rising_edge(clk_ahb2) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr) begin
if rising_edge(clk_ddr) then
r <= ri;
end if;
end process;
-- Write data selection.
AHB32: if AHBDW = 32 generate
hwdata <= ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) &
ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0);
end generate AHB32;
AHB64: if AHBDW = 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(63 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab(63 downto 0) <= ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(1 downto 0) = "11") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(31 downto 0) & hwdatab(63 downto 32);
end generate AHB64;
AHBWIDE: if AHBDW > 64 generate
-- With CORE_ACDM set to 0 hwdata will always be ahbsi.hwdata(127 downto 0)
-- otherwise the valid data slice will be selected, and possibly uplicated,
-- from ahbsi.hwdata.
hwdatab <= ahbread4word(ahbsi.hwdata, ra.haddr(4 downto 2)) when (CORE_ACDM = 0 or ra.size(2) = '1') else
(ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreaddword(ahbsi.hwdata, ra.haddr(4 downto 2))) when (ra.size = "011") else
(ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)) &
ahbreadword(ahbsi.hwdata, ra.haddr(4 downto 2)));
hwdata <= hwdatab(31 downto 0) & hwdatab(63 downto 32) &
hwdatab(95 downto 64) & hwdatab(127 downto 96);
end generate AHBWIDE;
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ahb2mig" & tost(hindex) & ": 64-bit DDR2/3 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------------------------------------------------
-- Processor core pipeline registers
-------------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- IF-RF
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_IF_RF is
port(clk, rst, ld: in std_logic;
PCincd_d: in reg32;
PCincd_q: out reg32;
instr: in reg32;
RF_instr: out reg32);
end reg_IF_RF;
architecture funcional of reg_IF_RF is
begin
process(clk, rst)
begin
if rst = '0' then
PCincd_q <= x"00000000";
RF_instr <= x"00000000";
elsif rising_edge(clk) then
if ld = '0' then
PCincd_q <= PCincd_d ;
RF_instr <= instr ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RF-EX
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_RF_EX is
port(clk, rst, ld: in std_logic;
selB: in std_logic;
EX_selB: out std_logic;
oper: in t_alu_fun;
EX_oper: out t_alu_fun;
a_rs: in reg5;
EX_a_rs: out reg5;
a_rt: in reg5;
EX_a_rt: out reg5;
a_c: in reg5;
EX_a_c: out reg5;
wreg: in std_logic;
EX_wreg: out std_logic;
muxC: in reg3;
EX_muxC: out reg3;
move: in std_logic;
EX_move: out std_logic;
postn: in reg5;
EX_postn: out reg5;
shamt: in reg5;
EX_shamt: out reg5;
aVal: in std_logic;
EX_aVal: out std_logic;
wrmem: in std_logic;
EX_wrmem: out std_logic;
mem_t: in reg4;
EX_mem_t: out reg4;
is_load: in boolean;
EX_is_load: out boolean;
A: in reg32;
EX_A: out reg32;
B: in reg32;
EX_B: out reg32;
displ32: in reg32;
EX_displ32: out reg32;
pc_p8: in reg32;
EX_pc_p8: out reg32);
end reg_RF_EX;
architecture funcional of reg_RF_EX is
begin
process(clk, rst)
begin
if rst = '0' then
EX_wreg <= '1';
EX_wrmem <= '1';
EX_aVal <= '1';
elsif rising_edge(clk) then
if ld = '0' then
EX_selB <= selB ;
EX_oper <= oper ;
EX_a_rs <= a_rs ;
EX_a_rt <= a_rt ;
EX_a_c <= a_c ;
EX_wreg <= wreg ;
EX_muxC <= muxC ;
EX_move <= move ;
EX_postn <= postn ;
EX_shamt <= shamt ;
EX_aVal <= aVal ;
EX_wrmem <= wrmem ;
EX_mem_t <= mem_t ;
EX_is_load <= is_load ;
EX_A <= A ;
EX_B <= B ;
EX_displ32 <= displ32 ;
EX_pc_p8 <= pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- EX-MEM
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_EX_MM is
port(clk, rst, ld: in std_logic;
EX_a_rt: in reg5;
MM_a_rt: out reg5;
EX_a_c: in reg5;
MM_a_c: out reg5;
EX_wreg: in std_logic;
MM_wreg: out std_logic;
EX_muxC: in reg3;
MM_muxC: out reg3;
EX_aVal: in std_logic;
MM_aVal: out std_logic;
EX_wrmem: in std_logic;
MM_wrmem: out std_logic;
EX_mem_t: in reg4;
MM_mem_t: out reg4;
EX_is_load: in boolean;
MM_is_load: out boolean;
EX_A: in reg32;
MM_A: out reg32;
EX_B: in reg32;
MM_B: out reg32;
EX_result: in reg32;
MM_result: out reg32;
EX_addr: in reg32;
MM_addr: out reg32;
HI: in reg32;
MM_HI: out reg32;
LO: in reg32;
MM_LO: out reg32;
EX_alu_move_ok: in std_logic;
MM_alu_move_ok: out std_logic;
EX_move: in std_logic;
MM_move: out std_logic;
EX_pc_p8: in reg32;
MM_pc_p8: out reg32);
end reg_EX_MM;
architecture funcional of reg_EX_MM is
begin
process(clk, rst)
begin
if rst = '0' then
MM_wreg <= '1';
MM_wrmem <= '1';
MM_aVal <= '1';
elsif rising_edge(clk) then
if ld = '0' then
MM_a_rt <= EX_a_rt ;
MM_a_c <= EX_a_c ;
MM_wreg <= EX_wreg ;
MM_muxC <= EX_muxC ;
MM_aVal <= EX_aVal ;
MM_wrmem <= EX_wrmem ;
MM_mem_t <= EX_mem_t ;
MM_is_load <= EX_is_load ;
MM_A <= EX_A ;
MM_B <= EX_B ;
MM_result <= EX_result ;
MM_addr <= EX_addr ;
MM_HI <= HI ;
MM_LO <= LO ;
MM_alu_move_ok <= EX_alu_move_ok ;
MM_move <= EX_move ;
MM_pc_p8 <= EX_pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- MEM-WB
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_MM_WB is
port(clk, rst, ld: in std_logic;
MM_a_c: in reg5;
WB_a_c: out reg5;
MM_wreg: in std_logic;
WB_wreg: out std_logic;
MM_muxC: in reg3;
WB_muxC: out reg3;
MM_A: in reg32;
WB_A: out reg32;
MM_result: in reg32;
WB_result: out reg32;
MM_HI: in reg32;
WB_HI: out reg32;
MM_LO: in reg32;
WB_LO: out reg32;
rd_data: in reg32;
WB_rd_data: out reg32;
MM_B_data: in reg32;
WB_B_data: out reg32;
MM_addr2: in reg2;
WB_addr2: out reg2;
MM_oper: in reg2;
WB_oper: out reg2;
MM_pc_p8: in reg32;
WB_pc_p8: out reg32);
end reg_MM_WB;
architecture funcional of reg_MM_WB is
begin
process(clk, rst)
begin
if rst = '0' then
WB_wreg <= '1';
elsif rising_edge(clk) then
if ld = '0' then
WB_a_c <= MM_a_c ;
WB_wreg <= MM_wreg ;
WB_muxC <= MM_muxC ;
WB_A <= MM_A ;
WB_result <= MM_result ;
WB_HI <= MM_HI ;
WB_LO <= MM_LO ;
WB_rd_data <= rd_data ;
WB_B_data <= MM_B_data ;
WB_addr2 <= MM_addr2 ;
WB_oper <= MM_oper ;
WB_pc_p8 <= MM_pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-------------------------------------------------------------------------
-- Processor core pipeline registers
-------------------------------------------------------------------------
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- IF-RF
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_IF_RF is
port(clk, rst, ld: in std_logic;
PCincd_d: in reg32;
PCincd_q: out reg32;
instr: in reg32;
RF_instr: out reg32);
end reg_IF_RF;
architecture funcional of reg_IF_RF is
begin
process(clk, rst)
begin
if rst = '0' then
PCincd_q <= x"00000000";
RF_instr <= x"00000000";
elsif rising_edge(clk) then
if ld = '0' then
PCincd_q <= PCincd_d ;
RF_instr <= instr ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- RF-EX
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_RF_EX is
port(clk, rst, ld: in std_logic;
selB: in std_logic;
EX_selB: out std_logic;
oper: in t_alu_fun;
EX_oper: out t_alu_fun;
a_rs: in reg5;
EX_a_rs: out reg5;
a_rt: in reg5;
EX_a_rt: out reg5;
a_c: in reg5;
EX_a_c: out reg5;
wreg: in std_logic;
EX_wreg: out std_logic;
muxC: in reg3;
EX_muxC: out reg3;
move: in std_logic;
EX_move: out std_logic;
postn: in reg5;
EX_postn: out reg5;
shamt: in reg5;
EX_shamt: out reg5;
aVal: in std_logic;
EX_aVal: out std_logic;
wrmem: in std_logic;
EX_wrmem: out std_logic;
mem_t: in reg4;
EX_mem_t: out reg4;
is_load: in boolean;
EX_is_load: out boolean;
A: in reg32;
EX_A: out reg32;
B: in reg32;
EX_B: out reg32;
displ32: in reg32;
EX_displ32: out reg32;
pc_p8: in reg32;
EX_pc_p8: out reg32);
end reg_RF_EX;
architecture funcional of reg_RF_EX is
begin
process(clk, rst)
begin
if rst = '0' then
EX_wreg <= '1';
EX_wrmem <= '1';
EX_aVal <= '1';
elsif rising_edge(clk) then
if ld = '0' then
EX_selB <= selB ;
EX_oper <= oper ;
EX_a_rs <= a_rs ;
EX_a_rt <= a_rt ;
EX_a_c <= a_c ;
EX_wreg <= wreg ;
EX_muxC <= muxC ;
EX_move <= move ;
EX_postn <= postn ;
EX_shamt <= shamt ;
EX_aVal <= aVal ;
EX_wrmem <= wrmem ;
EX_mem_t <= mem_t ;
EX_is_load <= is_load ;
EX_A <= A ;
EX_B <= B ;
EX_displ32 <= displ32 ;
EX_pc_p8 <= pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- EX-MEM
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_EX_MM is
port(clk, rst, ld: in std_logic;
EX_a_rt: in reg5;
MM_a_rt: out reg5;
EX_a_c: in reg5;
MM_a_c: out reg5;
EX_wreg: in std_logic;
MM_wreg: out std_logic;
EX_muxC: in reg3;
MM_muxC: out reg3;
EX_aVal: in std_logic;
MM_aVal: out std_logic;
EX_wrmem: in std_logic;
MM_wrmem: out std_logic;
EX_mem_t: in reg4;
MM_mem_t: out reg4;
EX_is_load: in boolean;
MM_is_load: out boolean;
EX_A: in reg32;
MM_A: out reg32;
EX_B: in reg32;
MM_B: out reg32;
EX_result: in reg32;
MM_result: out reg32;
EX_addr: in reg32;
MM_addr: out reg32;
HI: in reg32;
MM_HI: out reg32;
LO: in reg32;
MM_LO: out reg32;
EX_alu_move_ok: in std_logic;
MM_alu_move_ok: out std_logic;
EX_move: in std_logic;
MM_move: out std_logic;
EX_pc_p8: in reg32;
MM_pc_p8: out reg32);
end reg_EX_MM;
architecture funcional of reg_EX_MM is
begin
process(clk, rst)
begin
if rst = '0' then
MM_wreg <= '1';
MM_wrmem <= '1';
MM_aVal <= '1';
elsif rising_edge(clk) then
if ld = '0' then
MM_a_rt <= EX_a_rt ;
MM_a_c <= EX_a_c ;
MM_wreg <= EX_wreg ;
MM_muxC <= EX_muxC ;
MM_aVal <= EX_aVal ;
MM_wrmem <= EX_wrmem ;
MM_mem_t <= EX_mem_t ;
MM_is_load <= EX_is_load ;
MM_A <= EX_A ;
MM_B <= EX_B ;
MM_result <= EX_result ;
MM_addr <= EX_addr ;
MM_HI <= HI ;
MM_LO <= LO ;
MM_alu_move_ok <= EX_alu_move_ok ;
MM_move <= EX_move ;
MM_pc_p8 <= EX_pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- MEM-WB
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_WIRES.all;
entity reg_MM_WB is
port(clk, rst, ld: in std_logic;
MM_a_c: in reg5;
WB_a_c: out reg5;
MM_wreg: in std_logic;
WB_wreg: out std_logic;
MM_muxC: in reg3;
WB_muxC: out reg3;
MM_A: in reg32;
WB_A: out reg32;
MM_result: in reg32;
WB_result: out reg32;
MM_HI: in reg32;
WB_HI: out reg32;
MM_LO: in reg32;
WB_LO: out reg32;
rd_data: in reg32;
WB_rd_data: out reg32;
MM_B_data: in reg32;
WB_B_data: out reg32;
MM_addr2: in reg2;
WB_addr2: out reg2;
MM_oper: in reg2;
WB_oper: out reg2;
MM_pc_p8: in reg32;
WB_pc_p8: out reg32);
end reg_MM_WB;
architecture funcional of reg_MM_WB is
begin
process(clk, rst)
begin
if rst = '0' then
WB_wreg <= '1';
elsif rising_edge(clk) then
if ld = '0' then
WB_a_c <= MM_a_c ;
WB_wreg <= MM_wreg ;
WB_muxC <= MM_muxC ;
WB_A <= MM_A ;
WB_result <= MM_result ;
WB_HI <= MM_HI ;
WB_LO <= MM_LO ;
WB_rd_data <= rd_data ;
WB_B_data <= MM_B_data ;
WB_addr2 <= MM_addr2 ;
WB_oper <= MM_oper ;
WB_pc_p8 <= MM_pc_p8 ;
end if;
end if;
end process;
end funcional;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
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|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_parity is
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 60;
Cx_rst : integer := 10;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
DCTS_N, DCTS_E, DCTS_w, DCTS_S, DCTS_L: in std_logic;
DRTS_N, DRTS_E, DRTS_W, DRTS_S, DRTS_L: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
RTS_N, RTS_E, RTS_W, RTS_S, RTS_L: out std_logic;
CTS_N, CTS_E, CTS_w, CTS_S, CTS_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
fault_out_N, fault_out_E, fault_out_W, fault_out_S, fault_out_L:out std_logic
);
end router_parity;
architecture behavior of router_parity is
COMPONENT parity_checker is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
fault_out: out std_logic
);
end COMPONENT;
COMPONENT FIFO
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector (DATA_WIDTH-1 downto 0);
DRTS: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
CTS: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
COMPONENT Arbiter
port ( reset: in std_logic;
clk: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:in std_logic;
DCTS: in std_logic;
Grant_N, Grant_E, Grant_W, Grant_S, Grant_L:out std_logic;
Xbar_sel : out std_logic_vector(4 downto 0);
RTS: out std_logic
);
end COMPONENT;
COMPONENT LBDR is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 60;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
begin
------------------------------------------------------------------------------------------------------------------------------
-- block diagram of one channel
--
-- .____________grant_________
-- | ▲
-- | _______ __|_______
-- | | | | |
-- | | LBDR |---req--->| Arbiter | <--handshake-->
-- | |_______| |__________| signals
-- | ▲ |
-- __▼___ | flit ___▼__
-- RX ----->| | | type | |
-- <-handshake->| FIFO |---o------------->| |-----> TX
-- signals |______| ------>| |
-- ------>| XBAR |
-- ------>| |
-- ------>| |
-- |______|
--
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the parity_checkers
PC_N: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_N, DRTS =>DRTS_N, fault_out => fault_out_N);
PC_E: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_E, DRTS =>DRTS_E, fault_out => fault_out_E);
PC_W: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_W, DRTS =>DRTS_W, fault_out => fault_out_W);
PC_S: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_S, DRTS =>DRTS_S, fault_out => fault_out_S);
PC_L: parity_checker generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP(RX => RX_L, DRTS =>DRTS_L, fault_out => fault_out_L);
-- all the FIFOs
FIFO_N: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_N, DRTS => DRTS_N,
read_en_N => '0', read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
CTS => CTS_N, empty_out => empty_N, Data_out => FIFO_D_out_N);
FIFO_E: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_E, DRTS => DRTS_E,
read_en_N => Grant_NE, read_en_E =>'0', read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
CTS => CTS_E, empty_out => empty_E, Data_out => FIFO_D_out_E);
FIFO_W: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_W, DRTS => DRTS_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>'0', read_en_S =>Grant_SW, read_en_L =>Grant_LW,
CTS => CTS_W, empty_out => empty_W, Data_out => FIFO_D_out_W);
FIFO_S: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_S, DRTS => DRTS_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>'0', read_en_L =>Grant_LS,
CTS => CTS_S, empty_out => empty_S, Data_out => FIFO_D_out_S);
FIFO_L: FIFO generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (reset => reset, clk => clk, RX => RX_L, DRTS => DRTS_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>'0',
CTS => CTS_L, empty_out => empty_L, Data_out => FIFO_D_out_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the LBDRs
LBDR_N: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N, flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL);
LBDR_E: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E, flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL);
LBDR_W: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W, flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL);
LBDR_S: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S, flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL);
LBDR_L: LBDR generic map (cur_addr_rst => current_address, Rxy_rst => Rxy_rst, Cx_rst => Cx_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L, flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Arbiters
Arbiter_N: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => '0' , Req_E => Req_EN, Req_W => Req_WN, Req_S => Req_SN, Req_L => Req_LN,
DCTS => DCTS_N, Grant_N => Grant_NN, Grant_E => Grant_NE, Grant_W => Grant_NW, Grant_S => Grant_NS, Grant_L => Grant_NL,
Xbar_sel => Xbar_sel_N,
RTS => RTS_N
);
Arbiter_E: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NE , Req_E => '0', Req_W => Req_WE, Req_S => Req_SE, Req_L => Req_LE,
DCTS => DCTS_E, Grant_N => Grant_EN, Grant_E => Grant_EE, Grant_W => Grant_EW, Grant_S => Grant_ES, Grant_L => Grant_EL,
Xbar_sel => Xbar_sel_E,
RTS => RTS_E
);
Arbiter_W: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NW , Req_E => Req_EW, Req_W => '0', Req_S => Req_SW, Req_L => Req_LW,
DCTS => DCTS_W, Grant_N => Grant_WN, Grant_E => Grant_WE, Grant_W => Grant_WW, Grant_S => Grant_WS, Grant_L => Grant_WL,
Xbar_sel => Xbar_sel_W,
RTS => RTS_W
);
Arbiter_S: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NS , Req_E => Req_ES, Req_W => Req_WS, Req_S => '0', Req_L => Req_LS,
DCTS => DCTS_S, Grant_N => Grant_SN, Grant_E => Grant_SE, Grant_W => Grant_SW, Grant_S => Grant_SS, Grant_L => Grant_SL,
Xbar_sel => Xbar_sel_S,
RTS => RTS_S
);
Arbiter_L: Arbiter
PORT MAP (reset => reset, clk => clk,
Req_N => Req_NL , Req_E => Req_EL, Req_W => Req_WL, Req_S => Req_SL, Req_L => '0',
DCTS => DCTS_L, Grant_N => Grant_LN, Grant_E => Grant_LE, Grant_W => Grant_LW, Grant_S => Grant_LS, Grant_L => Grant_LL,
Xbar_sel => Xbar_sel_L,
RTS => RTS_L
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
port(
clk : in std_ulogic;
reset_n : in std_ulogic
);
end bug;
architecture behav of bug is
component comp is
port (
data : in std_ulogic_vector
);
end component;
type fifo_rdata_t is array (0 to 0) of std_ulogic_vector(4*8-1 downto 0);
signal fifo_rdata : fifo_rdata_t;
begin
c : comp
port map(
data => fifo_rdata(0)
);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 15:00:30 11/14/2015
-- Design Name:
-- Module Name: FourInMuxer_16bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FourInMuxer_16bit is
Port ( input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
input3 : in STD_LOGIC_VECTOR (15 downto 0);
input4 : in STD_LOGIC_VECTOR (15 downto 0);
opcode : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end FourInMuxer_16bit;
architecture Behavioral of FourInMuxer_16bit is
begin
with opcode select
output <= input1 when "00",
input2 when "01",
input3 when "10",
input4 when "11",
input1 when others; --Is it appropriate?
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "DualPort_Cache"
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : DualPort_Cache_tb.vhd
-- Author : Robert Jarzmik <robert.jarzmik@free.fr>
-- Company :
-- Created : 2016-11-19
-- Last update: 2016-11-19
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-19 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity DualPort_Cache_tb is
end entity DualPort_Cache_tb;
-------------------------------------------------------------------------------
architecture passthrough of DualPort_Cache_tb is
-- component generics
constant ADDR_WIDTH : integer := 32;
constant DATA_WIDTH : integer := 32;
-- component ports
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal i_porta_req : std_logic;
signal i_porta_we : std_logic;
signal i_porta_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i_porta_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_porta_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_porta_valid : std_logic;
signal i_portb_req : std_logic;
signal i_portb_we : std_logic;
signal i_portb_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i_portb_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_portb_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal o_portb_valid : std_logic;
signal o_memory_req : std_logic;
signal o_memory_we : std_logic;
signal o_memory_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_memory_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal i_memory_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal i_memory_valid : std_logic;
-- memory simulator
type memory is array(0 to 7) of std_logic_vector(DATA_WIDTH - 1 downto 0);
constant rom : memory := (
x"00000000",
x"20050004",
x"00000008",
x"0000000c",
x"00000010",
x"00000014",
x"00000018",
x"0000001c"
);
begin -- architecture passthrough
-- component instantiation
DUT : entity work.DualPort_Cache
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk,
rst => rst,
i_porta_req => i_porta_req,
i_porta_we => i_porta_we,
i_porta_addr => i_porta_addr,
i_porta_write_data => i_porta_write_data,
o_porta_read_data => o_porta_read_data,
o_porta_valid => o_porta_valid,
i_portb_req => i_portb_req,
i_portb_we => i_portb_we,
i_portb_addr => i_portb_addr,
i_portb_write_data => i_portb_write_data,
o_portb_read_data => o_portb_read_data,
o_portb_valid => o_portb_valid,
o_memory_req => o_memory_req,
o_memory_we => o_memory_we,
o_memory_addr => o_memory_addr,
o_memory_write_data => o_memory_write_data,
i_memory_read_data => i_memory_read_data,
i_memory_valid => i_memory_valid);
-- reset
rst <= '0' after 24 ps;
-- clock generation
clk <= not clk after 10 ps;
-- waveform generation
WaveGen_Proc : process
variable nb_clk : natural := 0;
begin
-- insert signal assignments here
wait until Clk = '1';
nb_clk := nb_clk + 1;
case nb_clk is
when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 | 22 =>
i_porta_we <= '0';
i_porta_addr <= std_logic_vector(to_unsigned(2 * nb_clk, ADDR_WIDTH));
i_porta_req <= '1';
when others =>
i_porta_req <= '0';
i_porta_addr <= (others => 'X');
end case;
end process WaveGen_Proc;
-- memory simulator
--InstantaneousMemorySim : process(clk, rst, o_memory_req)
--begin
-- if rst = '0' and o_memory_req = '1' then
-- if rising_edge(clk) then
-- i_memory_read_data <= rom((to_integer(unsigned(o_memory_addr)) / 4) mod 8);
-- i_memory_valid <= '1';
-- end if;
-- end if;
--end process InstantaneousMemorySim;
-- memory simulator
OneCycleMemorySim : process(clk, rst, o_memory_req)
variable clk_req : natural := 0;
begin
if rst = '0' then
if rising_edge(clk) then
if o_memory_req = '0' then
i_memory_valid <= '0';
i_memory_read_data <= (others => 'X');
end if;
if o_memory_req = '1' then
clk_req := clk_req + 1;
end if;
if clk_req > 0 then
clk_req := 0;
i_memory_read_data <= rom((to_integer(unsigned(o_memory_addr)) / 4) mod 8);
i_memory_valid <= '1';
end if;
end if;
end if;
end process OneCycleMemorySim;
end architecture passthrough;
-------------------------------------------------------------------------------
configuration DualPort_Cache_tb_passthrough_cfg of DualPort_Cache_tb is
for passthrough
end for;
end DualPort_Cache_tb_passthrough_cfg;
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
package siphash_package is
constant BYTES_WIDTH : integer := 4;
constant BLOCK_WIDTH : integer := 2**(BYTES_WIDTH-1)*8;
constant V_WIDTH : integer := BLOCK_WIDTH;
constant HASH_WIDTH : integer := BLOCK_WIDTH;
constant KEY_WIDTH : integer := 2*BLOCK_WIDTH;
constant COUNT_WIDTH : integer := 8-(BYTES_WIDTH-1);
constant LENGTH_WIDTH : integer := COUNT_WIDTH + BYTES_WIDTH - 1;
constant V0_INIT : std_logic_vector := x"736f6d6570736575";
constant V1_INIT : std_logic_vector := x"646f72616e646f6d";
constant V2_INIT : std_logic_vector := x"6c7967656e657261";
constant V3_INIT : std_logic_vector := x"7465646279746573";
constant V2_FINAL : std_logic_vector := x"00000000000000ff";
type v_array is array (integer range <>) of std_logic_vector(V_WIDTH-1 downto 0);
component sipround is
port (
v0_in, v1_in, v2_in, v3_in : in std_logic_vector(V_WIDTH-1 downto 0);
v0_out, v1_out, v2_out, v3_out : out std_logic_vector(V_WIDTH-1 downto 0)
);
end component;
component siphash is
generic (c : integer := 2);
port (
m : in std_logic_vector (BLOCK_WIDTH-1 downto 0);
b : in std_logic_vector (BYTES_WIDTH-1 downto 0);
rst_n : in std_logic;
clk : in std_logic;
init : in std_logic;
load_k : in std_logic;
init_ready, hash_ready : buffer std_logic;
hash : out std_logic_vector(HASH_WIDTH-1 downto 0)
);
end component;
end package;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Description: Controller for the OV760 camera - transferes registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
Port ( clk : in STD_LOGIC;
resend :in STD_LOGIC;
config_finished : out std_logic;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end ov7670_controller;
architecture Behavioral of ov7670_controller is
COMPONENT ov7670_registers
PORT(
clk : IN std_logic;
advance : IN std_logic;
resend : in STD_LOGIC;
command : OUT std_logic_vector(15 downto 0);
finished : OUT std_logic
);
END COMPONENT;
COMPONENT i2c_sender
PORT(
clk : IN std_logic;
send : IN std_logic;
taken : out std_logic;
id : IN std_logic_vector(7 downto 0);
reg : IN std_logic_vector(7 downto 0);
value : IN std_logic_vector(7 downto 0);
siod : INOUT std_logic;
sioc : OUT std_logic
);
END COMPONENT;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers PORT MAP(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY bd_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END bd_proc_sys_reset_1_0;
ARCHITECTURE bd_proc_sys_reset_1_0_arch OF bd_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bd_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END bd_proc_sys_reset_1_0_arch;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s1494_hot is
port(
clock: in std_logic;
input: in std_logic_vector(7 downto 0);
output: out std_logic_vector(18 downto 0)
);
end s1494_hot;
architecture behaviour of s1494_hot is
constant s000000: std_logic_vector(47 downto 0) := "100000000000000000000000000000000000000000000000";
constant s001110: std_logic_vector(47 downto 0) := "010000000000000000000000000000000000000000000000";
constant s011000: std_logic_vector(47 downto 0) := "001000000000000000000000000000000000000000000000";
constant s010000: std_logic_vector(47 downto 0) := "000100000000000000000000000000000000000000000000";
constant s010100: std_logic_vector(47 downto 0) := "000010000000000000000000000000000000000000000000";
constant s110011: std_logic_vector(47 downto 0) := "000001000000000000000000000000000000000000000000";
constant s010011: std_logic_vector(47 downto 0) := "000000100000000000000000000000000000000000000000";
constant s000100: std_logic_vector(47 downto 0) := "000000010000000000000000000000000000000000000000";
constant s010111: std_logic_vector(47 downto 0) := "000000001000000000000000000000000000000000000000";
constant s010110: std_logic_vector(47 downto 0) := "000000000100000000000000000000000000000000000000";
constant s100011: std_logic_vector(47 downto 0) := "000000000010000000000000000000000000000000000000";
constant s001100: std_logic_vector(47 downto 0) := "000000000001000000000000000000000000000000000000";
constant s011011: std_logic_vector(47 downto 0) := "000000000000100000000000000000000000000000000000";
constant s010001: std_logic_vector(47 downto 0) := "000000000000010000000000000000000000000000000000";
constant s100110: std_logic_vector(47 downto 0) := "000000000000001000000000000000000000000000000000";
constant s011101: std_logic_vector(47 downto 0) := "000000000000000100000000000000000000000000000000";
constant s101110: std_logic_vector(47 downto 0) := "000000000000000010000000000000000000000000000000";
constant s010101: std_logic_vector(47 downto 0) := "000000000000000001000000000000000000000000000000";
constant s111110: std_logic_vector(47 downto 0) := "000000000000000000100000000000000000000000000000";
constant s000011: std_logic_vector(47 downto 0) := "000000000000000000010000000000000000000000000000";
constant s111011: std_logic_vector(47 downto 0) := "000000000000000000001000000000000000000000000000";
constant s011010: std_logic_vector(47 downto 0) := "000000000000000000000100000000000000000000000000";
constant s111010: std_logic_vector(47 downto 0) := "000000000000000000000010000000000000000000000000";
constant s100111: std_logic_vector(47 downto 0) := "000000000000000000000001000000000000000000000000";
constant s110010: std_logic_vector(47 downto 0) := "000000000000000000000000100000000000000000000000";
constant s100000: std_logic_vector(47 downto 0) := "000000000000000000000000010000000000000000000000";
constant s011100: std_logic_vector(47 downto 0) := "000000000000000000000000001000000000000000000000";
constant s101010: std_logic_vector(47 downto 0) := "000000000000000000000000000100000000000000000000";
constant s100010: std_logic_vector(47 downto 0) := "000000000000000000000000000010000000000000000000";
constant s101000: std_logic_vector(47 downto 0) := "000000000000000000000000000001000000000000000000";
constant s011110: std_logic_vector(47 downto 0) := "000000000000000000000000000000100000000000000000";
constant s110000: std_logic_vector(47 downto 0) := "000000000000000000000000000000010000000000000000";
constant s010010: std_logic_vector(47 downto 0) := "000000000000000000000000000000001000000000000000";
constant s001010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000100000000000000";
constant s100100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000010000000000000";
constant s111000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000001000000000000";
constant s001011: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000100000000000";
constant s110100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000010000000000";
constant s001000: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000001000000000";
constant s000010: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000100000000";
constant s000111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000010000000";
constant s101011: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000001000000";
constant s001111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000100000";
constant s000110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000010000";
constant s110110: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000001000";
constant s011111: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000100";
constant s111100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000010";
constant s101100: std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(47 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------------------------"; output <= "-------------------";
case current_state is
when s000000 =>
if std_match(input, "0-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "0-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "0-10----") then next_state <= s000000; output <= "0000000000000000000";
elsif std_match(input, "0-11----") then next_state <= s000000; output <= "0001001100111110001";
elsif std_match(input, "1-01----") then next_state <= s000000; output <= "1000000001000000001";
elsif std_match(input, "1-00----") then next_state <= s000000; output <= "1000000000100000001";
elsif std_match(input, "1-11----") then next_state <= s001110; output <= "0001001100111110001";
elsif std_match(input, "1-10----") then next_state <= s000000; output <= "0000000000000000000";
end if;
when s001110 =>
if std_match(input, "1---0---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "11--1---") then next_state <= s010000; output <= "1000010010100000101";
elsif std_match(input, "10--1---") then next_state <= s011000; output <= "0000000000100100101";
elsif std_match(input, "00------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "01--1---") then next_state <= s000000; output <= "1000010010100000101";
elsif std_match(input, "01--0---") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011000 =>
if std_match(input, "0-00-000") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-00-010") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-110") then next_state <= s000000; output <= "1000000100100000110";
elsif std_match(input, "0-00-100") then next_state <= s000000; output <= "1000000100110000110";
elsif std_match(input, "0-01-100") then next_state <= s000000; output <= "1000001101010000110";
elsif std_match(input, "0-01-110") then next_state <= s000000; output <= "1000001101000000110";
elsif std_match(input, "0-01-010") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-01-000") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-0---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-0---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "0-10-000") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-10-010") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0-0") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-110") then next_state <= s000000; output <= "0000001100000000000";
elsif std_match(input, "0-10-100") then next_state <= s000000; output <= "0000001100010000000";
elsif std_match(input, "0-11-1-0") then next_state <= s000000; output <= "0000001100110110110";
elsif std_match(input, "0-1---01") then next_state <= s000000; output <= "0100000000111111100";
elsif std_match(input, "0-1---11") then next_state <= s000000; output <= "0100000000101111100";
elsif std_match(input, "1--1--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1--1--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1-11-0-0") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-11-1-0") then next_state <= s110011; output <= "0000001100110110110";
elsif std_match(input, "1-01-110") then next_state <= s010100; output <= "1000001101000000110";
elsif std_match(input, "1-01-100") then next_state <= s010100; output <= "1000001101010000110";
elsif std_match(input, "1-01-010") then next_state <= s010100; output <= "1000001001000000110";
elsif std_match(input, "1-01-000") then next_state <= s010100; output <= "1000001001010000110";
elsif std_match(input, "1--0--11") then next_state <= s010100; output <= "0100000000101111100";
elsif std_match(input, "1--0--01") then next_state <= s010100; output <= "0100000000111111100";
elsif std_match(input, "1-10-100") then next_state <= s010100; output <= "0000001100010000000";
elsif std_match(input, "1-10-110") then next_state <= s010100; output <= "0000001100000000000";
elsif std_match(input, "1-10-000") then next_state <= s010100; output <= "0000001000010000000";
elsif std_match(input, "1-10-010") then next_state <= s010100; output <= "0000001000000000000";
elsif std_match(input, "1-00-110") then next_state <= s010100; output <= "1000000100100000110";
elsif std_match(input, "1-00-100") then next_state <= s010100; output <= "1000000100110000110";
elsif std_match(input, "1-00-000") then next_state <= s010100; output <= "1000000000110000110";
elsif std_match(input, "1-00-010") then next_state <= s010100; output <= "1000000000100000110";
end if;
when s010100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010011; output <= "0000000000100100101";
end if;
when s010011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111100001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111100001";
elsif std_match(input, "1----1--") then next_state <= s000100; output <= "1000000100111100001";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "1000000000111100001";
end if;
when s000100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "10---11-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--011-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "11--111-") then next_state <= s010110; output <= "0000000000100100101";
elsif std_match(input, "11---01-") then next_state <= s100011; output <= "0000000000100100101";
elsif std_match(input, "10---01-") then next_state <= s010111; output <= "0000000000100100101";
elsif std_match(input, "1-----0-") then next_state <= s010111; output <= "0000000000100100101";
end if;
when s010111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101011000";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101011000";
elsif std_match(input, "1----0--") then next_state <= s001100; output <= "0000000000101011000";
elsif std_match(input, "1----1--") then next_state <= s001100; output <= "0000000100101011000";
end if;
when s001100 =>
if std_match(input, "1----1--") then next_state <= s011011; output <= "0000000000100100101";
elsif std_match(input, "1----0--") then next_state <= s010001; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011011 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100101110100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100111110100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000101110100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000111110100";
elsif std_match(input, "1----11-") then next_state <= s100110; output <= "0000000100101110100";
elsif std_match(input, "1----10-") then next_state <= s100110; output <= "0000000100111110100";
elsif std_match(input, "1----01-") then next_state <= s100110; output <= "0000000000101110100";
elsif std_match(input, "1----00-") then next_state <= s100110; output <= "0000000000111110100";
end if;
when s100110 =>
if std_match(input, "1-------") then next_state <= s011101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s011101 =>
if std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000110011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000100011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100100011010";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100110011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "0000000100110011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "0000000100100011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "0000000000110011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "0000000000100011010";
end if;
when s101110 =>
if std_match(input, "1-------") then next_state <= s010101; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010101 =>
if std_match(input, "1----0--") then next_state <= s111110; output <= "1000000000110100110";
elsif std_match(input, "1----1--") then next_state <= s111110; output <= "1000000100110100110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100110100110";
end if;
when s111110 =>
if std_match(input, "01----0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1-0-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "00--0-0-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "11----01") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--0-00") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "11--1-00") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "10--0-0-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "10--1-00") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "10--1-01") then next_state <= s111010; output <= "0000100000100100101";
elsif std_match(input, "0---1-1-") then next_state <= s000000; output <= "0000100000100100101";
elsif std_match(input, "0---0-1-") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---0-1-") then next_state <= s000011; output <= "0000000000100100101";
elsif std_match(input, "1---1-10") then next_state <= s011010; output <= "0000100000100100101";
elsif std_match(input, "1---1-11") then next_state <= s111010; output <= "0000100000100100101";
end if;
when s000011 =>
if std_match(input, "0----0-1") then next_state <= s000000; output <= "0000000000111110001";
elsif std_match(input, "0----1-1") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0----0-0") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "0----1-0") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "1----0-1") then next_state <= s001110; output <= "0000000000111110001";
elsif std_match(input, "1----1-1") then next_state <= s001110; output <= "0000000100111110001";
elsif std_match(input, "1----0-0") then next_state <= s001110; output <= "1000000000111110001";
elsif std_match(input, "1----1-0") then next_state <= s001110; output <= "0000000100111110001";
end if;
when s111011 =>
if std_match(input, "1----0--") then next_state <= s100111; output <= "1000000000111110001";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110001";
elsif std_match(input, "1----1--") then next_state <= s010000; output <= "0000010110111110001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000010110111110001";
end if;
when s100111 =>
if std_match(input, "1-------") then next_state <= s111011; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010000 =>
if std_match(input, "--------") then next_state <= s000000; output <= "0000000000101110100";
end if;
when s011010 =>
if std_match(input, "1----01-") then next_state <= s110010; output <= "0000000000100101001";
elsif std_match(input, "1----00-") then next_state <= s110010; output <= "0000000000110101001";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000100101001";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
end if;
when s110010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1----00-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----01-") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "1----11-") then next_state <= s011100; output <= "0000000000100100101";
elsif std_match(input, "1----10-") then next_state <= s011010; output <= "0000000000100100101";
end if;
when s011100 =>
if std_match(input, "1----10-") then next_state <= s101010; output <= "0000000100101111100";
elsif std_match(input, "1----11-") then next_state <= s101010; output <= "0000000100111111100";
elsif std_match(input, "1----00-") then next_state <= s100010; output <= "0000000000101111100";
elsif std_match(input, "1----01-") then next_state <= s100010; output <= "0000000000111111100";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "0000000100101111100";
elsif std_match(input, "0----11-") then next_state <= s000000; output <= "0000000100111111100";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "0000000000101111100";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "0000000000111111100";
end if;
when s101010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s111010; output <= "0000000000100100101";
end if;
when s111010 =>
if std_match(input, "1-------") then next_state <= s100000; output <= "0000000000111110001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000111110001";
end if;
when s100000 =>
if std_match(input, "11------") then next_state <= s101000; output <= "0100000000100100101";
elsif std_match(input, "01------") then next_state <= s000000; output <= "0100000000100100101";
elsif std_match(input, "00--0---") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "00--1---") then next_state <= s000000; output <= "0000010000100100101";
elsif std_match(input, "10--0---") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "10--1---") then next_state <= s110000; output <= "0000010000100100101";
end if;
when s101000 =>
if std_match(input, "1-------") then next_state <= s010010; output <= "1000000000111100001";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "1000000000111100001";
end if;
when s010010 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1---1---") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "1---0---") then next_state <= s011110; output <= "0000000000100100101";
end if;
when s001010 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s111000; output <= "0000000000110101001";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110101001";
end if;
when s100100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s001011; output <= "0010000000100100101";
end if;
when s001011 =>
if std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s110100; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s110100; output <= "0000000100101110110";
end if;
when s110100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "1-------") then next_state <= s011011; output <= "0010000000100100101";
end if;
when s111000 =>
if std_match(input, "1----0--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---11--") then next_state <= s001000; output <= "0000000000100100101";
elsif std_match(input, "1---01--") then next_state <= s001010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s001000 =>
if std_match(input, "1----1--") then next_state <= s100100; output <= "0000000100110110110";
elsif std_match(input, "1----0--") then next_state <= s100100; output <= "0000000000110110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100110110110";
end if;
when s011110 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100111110001";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
elsif std_match(input, "0-10-00-") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-10-01-") then next_state <= s000000; output <= "0000001000010000000";
elsif std_match(input, "0-00-00-") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-00-01-") then next_state <= s000000; output <= "1000000000110000110";
elsif std_match(input, "0-01-01-") then next_state <= s000000; output <= "1000001001010000110";
elsif std_match(input, "0-01-00-") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "1----1--") then next_state <= s100000; output <= "0000000100111110001";
elsif std_match(input, "1-00-00-") then next_state <= s000010; output <= "1000000000100000110";
elsif std_match(input, "1-00-01-") then next_state <= s000010; output <= "1000000000110000110";
elsif std_match(input, "1-01-01-") then next_state <= s000010; output <= "1000001001010000110";
elsif std_match(input, "1-01-00-") then next_state <= s000010; output <= "1000001001000000110";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "1-10-00-") then next_state <= s000010; output <= "0000001000000000000";
elsif std_match(input, "1-10-01-") then next_state <= s000010; output <= "0000001000010000000";
end if;
when s000010 =>
if std_match(input, "1----0--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1----1--") then next_state <= s011110; output <= "0000000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s110011 =>
if std_match(input, "1-------") then next_state <= s000111; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s000111 =>
if std_match(input, "0----1--") then next_state <= s000000; output <= "0000000100101110110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0000000000101110110";
elsif std_match(input, "1----1--") then next_state <= s101011; output <= "0000000100101110110";
elsif std_match(input, "1----0--") then next_state <= s101011; output <= "0000000000101110110";
end if;
when s101011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s001111; output <= "0000000000100100101";
end if;
when s001111 =>
if std_match(input, "1----1--") then next_state <= s000100; output <= "0010000100111001110";
elsif std_match(input, "1----0--") then next_state <= s000100; output <= "0010000000111001110";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0010000100111001110";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000111001110";
end if;
when s110000 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "1000000000110100110";
elsif std_match(input, "1-------") then next_state <= s000110; output <= "1000000000110100110";
end if;
when s000110 =>
if std_match(input, "1---01--") then next_state <= s011000; output <= "0001000000100100101";
elsif std_match(input, "1---00--") then next_state <= s011000; output <= "0010000000100100101";
elsif std_match(input, "1---10--") then next_state <= s011110; output <= "0010000000100100101";
elsif std_match(input, "1---11--") then next_state <= s011110; output <= "0001000000100100101";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "0010000000100100101";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "0001000000100100101";
end if;
when s100010 =>
if std_match(input, "1-------") then next_state <= s011010; output <= "0000000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
end if;
when s010001 =>
if std_match(input, "1----0--") then next_state <= s110110; output <= "1000000000111110100";
elsif std_match(input, "1----1--") then next_state <= s110110; output <= "1000000100111110100";
elsif std_match(input, "0----1--") then next_state <= s000000; output <= "1000000100111110100";
elsif std_match(input, "0----0--") then next_state <= s000000; output <= "1000000000111110100";
end if;
when s110110 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s011111; output <= "0000000000100100101";
end if;
when s011111 =>
if std_match(input, "0----11-") then next_state <= s000000; output <= "1000000100111011010";
elsif std_match(input, "0----10-") then next_state <= s000000; output <= "1000000100101011010";
elsif std_match(input, "0----00-") then next_state <= s000000; output <= "1000000000101011010";
elsif std_match(input, "0----01-") then next_state <= s000000; output <= "1000000000111011010";
elsif std_match(input, "1----10-") then next_state <= s101110; output <= "1000000100101011010";
elsif std_match(input, "1----11-") then next_state <= s101110; output <= "1000000100111011010";
elsif std_match(input, "1----00-") then next_state <= s101110; output <= "1000000000101011010";
elsif std_match(input, "1----01-") then next_state <= s101110; output <= "1000000000111011010";
end if;
when s010110 =>
if std_match(input, "1----1--") then next_state <= s111100; output <= "0001000100111110001";
elsif std_match(input, "1-00-0--") then next_state <= s101100; output <= "1000000000100000110";
elsif std_match(input, "1-01-0--") then next_state <= s101100; output <= "1000001001000000110";
elsif std_match(input, "1-10-0--") then next_state <= s101100; output <= "0000001000000000000";
elsif std_match(input, "1-11-0--") then next_state <= s110011; output <= "0000001000110110110";
elsif std_match(input, "0-00-0--") then next_state <= s000000; output <= "1000000000100000110";
elsif std_match(input, "0-01-0--") then next_state <= s000000; output <= "1000001001000000110";
elsif std_match(input, "0-0--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-1--1--") then next_state <= s000000; output <= "0001000100111110001";
elsif std_match(input, "0-10-0--") then next_state <= s000000; output <= "0000001000000000000";
elsif std_match(input, "0-11-0--") then next_state <= s000000; output <= "0000001000110110110";
end if;
when s111100 =>
if std_match(input, "1-------") then next_state <= s100011; output <= "0100000000100100101";
elsif std_match(input, "0-------") then next_state <= s000000; output <= "0100000000100100101";
end if;
when s100011 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000110110110";
elsif std_match(input, "1-------") then next_state <= s110011; output <= "0000000000110110110";
end if;
when s101100 =>
if std_match(input, "0-------") then next_state <= s000000; output <= "0000000000100100101";
elsif std_match(input, "1-------") then next_state <= s010110; output <= "0000000000100100101";
end if;
when others => next_state <= "------------------------------------------------"; output <= "-------------------";
end case;
end process;
end behaviour;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_fwft_64x1024_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: pad_xilinx_gen
-- File: pad_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Xilinx pads wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
entity virtex_inpad is
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_inpad is
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_I") port map (O => o, I => pad);
end generate;
sstl2y : if level = sstl2_ii generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos)
and (level /= sstl2_i)and (level /= sstl2_ii) generate
ip : IBUF port map (O => o, I => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUF;
-- pragma translate_on
entity virtex_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of virtex_iopad is
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_5")
port map (O => o, IO => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_3")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl2y : if level = sstl2_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18i : if level = sstl18_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18ii : if level = sstl18_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and (level /= sstl18_i) and (level /= sstl18_ii) generate
op : IOBUF port map (O => o, IO => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
-- pragma translate_on
entity virtex_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => i);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => i);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => i);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => i);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFT;
-- pragma translate_on
entity virtex_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end ;
architecture rtl of virtex_toutpad is
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
op : OBUFT port map (O => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
entity virtex_skew_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end ;
architecture rtl of virtex_skew_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal reset, clk0, clk0b, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
reset <= not rst;
dll0 : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => skew)
port map ( CLKIN => i, CLKFB => clk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => reset, CLK0 => clk0);
bufg0 : BUFG port map (I => clk0, O => clk0b);
o <= clk0b; -- output before pad
--x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, clk0b);
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => clk0b);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => clk0b);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => clk0b);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => clk0b);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => clk0b);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => clk0b);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => clk0b);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFG;
use unisim.IBUF;
use unisim.BUFGMUX;
use unisim.BUFG;
use unisim.BUFGDLL;
-- pragma translate_on
entity virtex_clkpad is
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1');
end;
architecture rtl of virtex_clkpad is
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component CLKDLL port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLK270 : out std_ulogic;
CLK2X : out std_ulogic; CLK90 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic; RST : in std_ulogic);
end component;
signal gnd, ol, ol2, ol3 : std_ulogic;
signal rst : std_ulogic;
begin
gnd <= '0'; rst <= not rstn;
g0 : if arch = 0 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
end generate;
sstl2 : if level = sstl2_ii generate
ip : IBUFG generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and (level /= sstl2_ii) generate
ip : IBUFG port map (O => o, I => pad);
end generate;
end generate;
g1 : if arch = 1 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
cmos0 : if level = cmos generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
g2 : if arch = 2 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos0 : if level = cmos generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUFG port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
g3 : if arch = 3 generate
ip : IBUFG port map (O => ol, I => pad);
hf0 : if hf = 0 generate
dll: CLKDLL port map(
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK90 => open,
CLKDV => open,
LOCKED => open,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
hf1 : if hf = 1 generate
dll : CLKDLLHF
port map(
CLK0 => ol2,
CLK180 => open,
CLKDV => open,
LOCKED => open,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
bf : BUFG port map (O => ol3, I => ol2);
o <= ol3;
end generate g3;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS_LVDS_25;
use unisim.OBUFDS_LVDS_33;
-- pragma translate_on
entity virtex_outpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex_outpad_ds is
component OBUFDS_LVDS_25
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS_LVDS_33 port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS_LVDS_25 port map (O => padp, OB => padn, I => i);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS_LVDS_25;
use unisim.IBUFDS_LVDS_33;
-- pragma translate_on
entity virtex_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_inpad_ds is
component IBUFDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS_LVDS_25;
use unisim.IBUFGDS_LVDS_33;
-- pragma translate_on
entity virtex_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_clkpad_ds is
component IBUFGDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFGDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS;
-- pragma translate_on
entity virtex4_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_inpad_ds is
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
-- pragma translate_on
entity virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUFDS;
-- pragma translate_on
entity virtex5_iopad_ds is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of virtex5_iopad_ds is
component IOBUFDS generic (
CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end component;
begin
iop : IOBUFDS generic map (IOSTANDARD => "DEFAULT")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS;
-- pragma translate_on
entity virtex5_outpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex5_outpad_ds is
component OBUFDS generic( IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "SSTL18_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "SSTL18_II")
port map (O => padp, OB => padn, I => i);
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: pad_xilinx_gen
-- File: pad_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Xilinx pads wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUF;
-- pragma translate_on
entity virtex_inpad is
generic (level : integer := 0; voltage : integer := x33v);
port (pad : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_inpad is
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_I") port map (O => o, I => pad);
end generate;
sstl2y : if level = sstl2_ii generate
ip : IBUF generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos)
and (level /= sstl2_i)and (level /= sstl2_ii) generate
ip : IBUF port map (O => o, I => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUF;
-- pragma translate_on
entity virtex_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of virtex_iopad is
component IOBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_5")
port map (O => o, IO => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : IOBUF generic map (IOSTANDARD => "PCI33_3")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => o, IO => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => o, IO => pad, I => i, T => en);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl2y : if level = sstl2_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18i : if level = sstl18_i generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => o, IO => pad, I => i, T => en);
end generate;
sstl18ii : if level = sstl18_ii generate
op : IOBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => o, IO => pad, I => i, T => en);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and (level /= sstl18_i) and (level /= sstl18_ii) generate
op : IOBUF port map (O => o, IO => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
-- pragma translate_on
entity virtex_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => i);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => i);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => i);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => i);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFT;
-- pragma translate_on
entity virtex_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12);
port (pad : out std_ulogic; i, en : in std_ulogic);
end ;
architecture rtl of virtex_toutpad is
component OBUFT generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I, T : in std_ulogic); end component;
begin
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => i, T => en);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => i, T => en);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => i, T => en);
end generate;
fast0 : if slew /= 0 generate
op : OBUFT generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => i, T => en);
end generate;
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
op : OBUFT port map (O => pad, I => i, T => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUF;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
entity virtex_skew_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end ;
architecture rtl of virtex_skew_outpad is
component OBUF generic (
CAPACITANCE : string := "DONT_CARE"; DRIVE : integer := 12;
IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW");
port (O : out std_ulogic; I : in std_ulogic); end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
signal reset, clk0, clk0b, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
reset <= not rst;
dll0 : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => skew)
port map ( CLKIN => i, CLKFB => clk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => reset, CLK0 => clk0);
bufg0 : BUFG port map (I => clk0, O => clk0b);
o <= clk0b; -- output before pad
--x0 : virtex_outpad generic map (level, slew, voltage, strength) port map (pad, clk0b);
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_5")
port map (O => pad, I => clk0b);
end generate;
pci_3 : if voltage /= x50v generate
op : OBUF generic map (drive => strength, IOSTANDARD => "PCI33_3")
port map (O => pad, I => clk0b);
end generate;
end generate;
ttl0 : if level = ttl generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVTTL", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
cmos0 : if level = cmos generate
slow0 : if slew = 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33")
port map (O => pad, I => clk0b);
end generate;
fast0 : if slew /= 0 generate
op : OBUF generic map (drive => strength, IOSTANDARD => "LVCMOS33", SLEW => "FAST")
port map (O => pad, I => clk0b);
end generate;
end generate;
sstl2x : if level = sstl2_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_I")
port map (O => pad, I => clk0b);
end generate;
sstl2y : if level = sstl2_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL2_II")
port map (O => pad, I => clk0b);
end generate;
sstl18i : if level = sstl18_i generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_I")
port map (O => pad, I => clk0b);
end generate;
sstl18ii : if level = sstl18_ii generate
op : OBUF generic map (drive => strength, IOSTANDARD => "SSTL18_II")
port map (O => pad, I => clk0b);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and
(level /= sstl2_i) and (level /= sstl2_ii) and
(level /= sstl18_i) and (level /= sstl18_ii) generate
op : OBUF port map (O => pad, I => clk0b);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFG;
use unisim.IBUF;
use unisim.BUFGMUX;
use unisim.BUFG;
use unisim.BUFGDLL;
-- pragma translate_on
entity virtex_clkpad is
generic (level : integer := 0; voltage : integer := x33v; arch : integer := 0; hf : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1');
end;
architecture rtl of virtex_clkpad is
component IBUFG generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_logic; I : in std_logic); end component;
component IBUF generic(
CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25");
port (O : out std_ulogic; I : in std_ulogic); end component;
component BUFGMUX port (O : out std_logic; I0, I1, S : in std_logic); end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--component BUFGDLL port (O : out std_logic; I : in std_logic); end component;
component CLKDLL port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLK270 : out std_ulogic;
CLK2X : out std_ulogic; CLK90 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic;
RST : in std_ulogic);
end component;
component CLKDLLHF port ( CLK0 : out std_ulogic; CLK180 : out std_ulogic; CLKDV : out std_ulogic;
LOCKED : out std_ulogic; CLKFB : in std_ulogic; CLKIN : in std_ulogic; RST : in std_ulogic);
end component;
signal gnd, ol, ol2, ol3 : std_ulogic;
signal rst : std_ulogic;
begin
gnd <= '0'; rst <= not rstn;
g0 : if arch = 0 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => o, I => pad);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => o, I => pad);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => o, I => pad);
end generate;
cmos0 : if level = cmos generate
cmos_33 : if voltage = x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => o, I => pad);
end generate;
cmos_25 : if voltage /= x33v generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS25") port map (O => o, I => pad);
end generate;
end generate;
sstl2 : if level = sstl2_ii generate
ip : IBUFG generic map (IOSTANDARD => "SSTL2_II") port map (O => o, I => pad);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) and (level /= sstl2_ii) generate
ip : IBUFG port map (O => o, I => pad);
end generate;
end generate;
g1 : if arch = 1 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUF generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUF generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
cmos0 : if level = cmos generate
ip : IBUF generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUF port map (O => ol, I => pad);
bf : BUFGMUX port map (O => o, I0 => ol, I1 => gnd, S => gnd);
end generate;
end generate;
g2 : if arch = 2 generate
pci0 : if level = pci33 generate
pci_5 : if voltage = x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_5") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
pci_3 : if voltage /= x50v generate
ip : IBUFG generic map (IOSTANDARD => "PCI33_3") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
ttl0 : if level = ttl generate
ip : IBUFG generic map (IOSTANDARD => "LVTTL") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
cmos0 : if level = cmos generate
ip : IBUFG generic map (IOSTANDARD => "LVCMOS33") port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
gen0 : if (level /= pci33) and (level /= ttl) and (level /= cmos) generate
ip : IBUFG port map (O => ol, I => pad);
bf : BUFG port map (O => o, I => ol);
end generate;
end generate;
g3 : if arch = 3 generate
ip : IBUFG port map (O => ol, I => pad);
hf0 : if hf = 0 generate
dll: CLKDLL port map(
CLK0 => ol2,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK90 => open,
CLKDV => open,
LOCKED => open,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
hf1 : if hf = 1 generate
dll : CLKDLLHF
port map(
CLK0 => ol2,
CLK180 => open,
CLKDV => open,
LOCKED => open,
CLKFB => ol3,
CLKIN => ol,
RST => rst);
end generate;
bf : BUFG port map (O => ol3, I => ol2);
o <= ol3;
end generate g3;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS_LVDS_25;
use unisim.OBUFDS_LVDS_33;
-- pragma translate_on
entity virtex_outpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex_outpad_ds is
component OBUFDS_LVDS_25
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
component OBUFDS_LVDS_33
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS_LVDS_33 port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS_LVDS_25 port map (O => padp, OB => padn, I => i);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS_LVDS_25;
use unisim.IBUFDS_LVDS_33;
-- pragma translate_on
entity virtex_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_inpad_ds is
component IBUFDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS_LVDS_25;
use unisim.IBUFGDS_LVDS_33;
-- pragma translate_on
entity virtex_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex_clkpad_ds is
component IBUFGDS_LVDS_25
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
component IBUFGDS_LVDS_33
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS_LVDS_33 port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFGDS_LVDS_25 port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFDS;
-- pragma translate_on
entity virtex4_inpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_inpad_ds is
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IBUFGDS;
-- pragma translate_on
entity virtex4_clkpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of virtex4_clkpad_ds is
component IBUFGDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_33")
port map (O => o, I => padp, IB => padn);
end generate;
lvds_25 : if voltage /= x33v generate
ip : IBUFGDS generic map (DIFF_TERM => true, IOSTANDARD =>"LVDS_25")
port map (O => o, I => padp, IB => padn);
end generate;
end generate;
beh : if level /= lvds generate
o <= padp after 1 ns;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.IOBUFDS;
-- pragma translate_on
entity virtex5_iopad_ds is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end ;
architecture rtl of virtex5_iopad_ds is
component IOBUFDS generic (
CAPACITANCE : string := "DONT_CARE"; IBUF_DELAY_VALUE : string := "0";
IOSTANDARD : string := "DEFAULT"; IFD_DELAY_VALUE : string := "AUTO");
port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); end component;
begin
iop : IOBUFDS generic map (IOSTANDARD => "DEFAULT")
port map (O => o, IO => padp, IOB => padn, I => i, T => en);
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library unisim;
use unisim.OBUFDS;
-- pragma translate_on
entity virtex5_outpad_ds is
generic (level : integer := lvds; voltage : integer := x33v);
port (padp, padn : out std_ulogic; i : in std_ulogic);
end ;
architecture rtl of virtex5_outpad_ds is
component OBUFDS generic( IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic);
end component;
begin
xlvds : if level = lvds generate
lvds_33 : if voltage = x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_33")
port map (O => padp, OB => padn, I => i);
end generate;
lvds_25 : if voltage /= x33v generate
op : OBUFDS generic map(IOSTANDARD => "LVDS_25")
port map (O => padp, OB => padn, I => i);
end generate;
end generate;
xsstl18_i : if level = sstl18_i generate
op : OBUFDS generic map(IOSTANDARD => "SSTL18_I")
port map (O => padp, OB => padn, I => i);
end generate;
xsstl18_ii : if level = sstl18_ii generate
op : OBUFDS generic map(IOSTANDARD => "SSTL18_II")
port map (O => padp, OB => padn, I => i);
end generate;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1472.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p03n01i01472ent IS
END c08s08b00x00p03n01i01472ent;
ARCHITECTURE c08s08b00x00p03n01i01472arch OF c08s08b00x00p03n01i01472ent IS
type primary is (blue, red, yellow);
--
-- Test that the '<=' can not be used
--
function color_to_int ( constant color : primary
) return integer is
begin
case color is
when others <= -- should be '=>'
return primary'pos(color);
end case;
end color_to_int;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s08b00x00p03n01i01472 - Signal assignment operator can not be used as case alternative delimiter."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p03n01i01472arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1472.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p03n01i01472ent IS
END c08s08b00x00p03n01i01472ent;
ARCHITECTURE c08s08b00x00p03n01i01472arch OF c08s08b00x00p03n01i01472ent IS
type primary is (blue, red, yellow);
--
-- Test that the '<=' can not be used
--
function color_to_int ( constant color : primary
) return integer is
begin
case color is
when others <= -- should be '=>'
return primary'pos(color);
end case;
end color_to_int;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s08b00x00p03n01i01472 - Signal assignment operator can not be used as case alternative delimiter."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p03n01i01472arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1472.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p03n01i01472ent IS
END c08s08b00x00p03n01i01472ent;
ARCHITECTURE c08s08b00x00p03n01i01472arch OF c08s08b00x00p03n01i01472ent IS
type primary is (blue, red, yellow);
--
-- Test that the '<=' can not be used
--
function color_to_int ( constant color : primary
) return integer is
begin
case color is
when others <= -- should be '=>'
return primary'pos(color);
end case;
end color_to_int;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s08b00x00p03n01i01472 - Signal assignment operator can not be used as case alternative delimiter."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p03n01i01472arch;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- Clock divider (clock enable generator)
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
|
--
-- UART for ZPUINO - Majority voting filter
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end entity uart_mv_filter;
architecture behave of uart_mv_filter is
signal count_q: unsigned(bits-1 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
count_q <= (others => '0');
sout <= '0';
else
if clear='1' then
count_q <= (others => '0');
sout <= '0';
else
if enable='1' then
if sin='1' then
count_q <= count_q + 1;
end if;
end if;
if (count_q >= threshold) then
sout<='1';
end if;
end if;
end if;
end if;
end process;
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc640.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00640ent IS
END c03s04b01x00p01n01i00640ent;
ARCHITECTURE c03s04b01x00p01n01i00640arch OF c03s04b01x00p01n01i00640ent IS
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_file is file of primary_memory;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
BEGIN
TESTING: PROCESS
file filein : primary_memory_file open write_mode is "iofile.42";
BEGIN
for i in 1 to 100 loop
write(filein, C44);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00640 - The output file will be verified by test s010286.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00640arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc640.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00640ent IS
END c03s04b01x00p01n01i00640ent;
ARCHITECTURE c03s04b01x00p01n01i00640arch OF c03s04b01x00p01n01i00640ent IS
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_file is file of primary_memory;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
BEGIN
TESTING: PROCESS
file filein : primary_memory_file open write_mode is "iofile.42";
BEGIN
for i in 1 to 100 loop
write(filein, C44);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00640 - The output file will be verified by test s010286.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00640arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc640.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:51 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00640ent IS
END c03s04b01x00p01n01i00640ent;
ARCHITECTURE c03s04b01x00p01n01i00640arch OF c03s04b01x00p01n01i00640ent IS
subtype word is bit_vector(0 to 15);
constant size : integer := 7;
type primary_memory is array(0 to size) of word;
type primary_memory_file is file of primary_memory;
constant C38 : word := (others => '1');
constant C44 : primary_memory := (others => C38);
BEGIN
TESTING: PROCESS
file filein : primary_memory_file open write_mode is "iofile.42";
BEGIN
for i in 1 to 100 loop
write(filein, C44);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00640 - The output file will be verified by test s010286.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00640arch;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (5 downto 0);
rs2 : in STD_LOGIC_VECTOR (5 downto 0);
rd : in STD_LOGIC_VECTOR (5 downto 0);
dwr : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
wre : in STD_LOGIC;
cRd : out STD_LOGIC_VECTOR (31 downto 0);
crs1 : out STD_LOGIC_VECTOR (31 downto 0);
crs2 : out STD_LOGIC_VECTOR (31 downto 0));
end RF;
architecture Behavioral of RF is
type ram_type is array (39 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type;
begin
RAM(0)<= "00000000000000000000000000000000";--serciora g0
process (rst,rd,rs1,rs2,dwr,RAM,wre)
begin
if rst = '1' then
RAM <= (others=>"00000000000000000000000000000000");
crs1 <="00000000000000000000000000000000";
crs2 <="00000000000000000000000000000000";
cRd <= "00000000000000000000000000000000";
RAM(15)<= "00000000000000000000000000001101";--por el jmpl para que lea el main
elsif rd /= "000000" and wre='1' then
RAM(conv_integer(rd)) <= dwr;
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
cRd <= RAM(conv_integer(rd));
else
crs1 <= RAM(conv_integer(rs1));
crs2 <= RAM(conv_integer(rs2));
cRd <= RAM(conv_integer(rd));
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file cam_control_unit.vhd
--! @brief Control Unit for the camera interface
--! @author Benjamin Bässler
--! @email ccl@xunit.de
--! @date 2014-04-25
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.types.all;
use work.utils.all;
library pccl_lib;
use pccl_lib.common.all;
entity cam_control_unit is
generic(
G_MAX_DATA_SIZE : natural := C_MAX_SEND_DATA;
--! Number of Comparators
G_COMP_INST : NATURAL := C_COMP_INST;
--! Image width
-- value from ccl_dut common.vhd
G_IMG_WIDTH : NATURAL := C_IMAGE_WIDTH;
--! Image height
-- value from ccl_dut common.vhd
G_IMG_HEIGHT : NATURAL := C_IMAGE_HEIGHT;
--! Error Storage
G_ERR_SIZE : NATURAL := C_ERR_BUF_SIZE
);
port (
-- System signals
------------------
rst_in : in std_logic; -- asynchronous reset
rx_clk_in : in std_logic;
clk_dut_in : in std_logic;
-- Decoded data
-- read/write command
dec_valid_in : in std_logic;
write_in : in std_logic;
type_in : in unsigned(15 downto 0);
id_in : in unsigned(15 downto 0);
length_in : in unsigned(15 downto 0);
data_in : in unsigned(G_MAX_DATA_SIZE - 1 downto 0);
header_error_in : in std_logic;
-- Encoder data
enc_valid_out : out std_logic;
type_out : out unsigned(15 downto 0);
id_out : out unsigned(15 downto 0);
length_out : out unsigned(15 downto 0);
data_out : out unsigned(G_MAX_DATA_SIZE - 1 downto 0);
run_out : out std_logic
);
end cam_control_unit;
architecture cam_control_unit_arc of cam_control_unit is
CONSTANT C_RESTART_WAIT : natural := 3;
CONSTANT C_STIM_SIZE : natural := G_IMG_WIDTH*G_IMG_HEIGHT;
CONSTANT C_STIM_SIZE_BYTE : natural := div_ceil(C_STIM_SIZE, 8);
CONSTANT C_BOX_SIZE : natural := 2*(log2_ceil(G_IMG_WIDTH)+log2_ceil(G_IMG_HEIGHT));
--log2_ceil(C_MAX_IMAGE_HEIGHT)+1+log2_ceil(C_MAX_IMAGE_WIDTH)+1
CONSTANT C_BOX_SIZE_BYTE : natural := div_ceil(C_BOX_SIZE, 8);
CONSTANT C_ERR_FIFO_WIDTH : natural := 6;
CONSTANT C_ERR_FI_LV_SIZE : natural := log2_ceil(G_ERR_SIZE)+1;
CONSTANT C_ERR_FI_LV_BYTE : natural := div_ceil(C_ERR_FI_LV_SIZE, 8);
--! length of error injection package
CONSTANT C_ERR_PKG_LEN : natural := div_ceil(T_CAM_ERR'length * (log2_ceil(C_MAX_IMAGE_HEIGHT+1)+log2_ceil(C_MAX_IMAGE_WIDTH+1)+1),8);
CONSTANT C_TYP_ACK : unsigned(15 downto 0) := x"0001";
CONSTANT C_TYP_NACK : unsigned(15 downto 0) := x"0002";
CONSTANT C_TYP_HW_CFG : unsigned(15 downto 0) := x"0003";
CONSTANT C_TYP_STATUS : unsigned(15 downto 0) := x"0004";
CONSTANT C_TYP_RESET : unsigned(15 downto 0) := x"0007";
CONSTANT C_TYP_SEND_PX : unsigned(15 downto 0) := x"000E";
CONSTANT C_TYP_SEND_BOX : unsigned(15 downto 0) := x"000F";
CONSTANT C_TYP_SET_FLL_LVL : unsigned(15 downto 0) := x"0010";
CONSTANT C_TYP_SET_ACT_ERR : unsigned(15 downto 0) := x"0011";
CONSTANT C_TYP_SET_HSY_ERR : unsigned(15 downto 0) := x"0012";
CONSTANT C_TYP_SET_VSY_ERR : unsigned(15 downto 0) := x"0013";
type T_RX_STATE is (NOP, ACK, NACK, HEAD_ERR, HW_CFG, STATUS,
RESET, SEND_PX, SET_FLL_LVL,
SET_ACT_ERR, SET_HSY_ERR, SET_VSY_ERR, SEND_OUT,
SEND_OUT_LAST, UNKNOWN);
signal rx_state_s : T_RX_STATE;
--! verifier state
type T_INT_STATE is (RESTART, PROCESSING, DONE);
signal int_state_s : T_INT_STATE;
--! internal signals
signal rst_exec_s : std_logic := '0';
signal rst_prepare_s : std_logic := '0';
signal restart_cnt_s : unsigned(log2_ceil(C_RESTART_WAIT+1)-1 downto 0);
--! camif signals
Signal cam_rst_s : STD_LOGIC;
Signal cam_min_fll_lvl_s : UNSIGNED(15 downto 0);
Signal cam_di_s : UNSIGNED(G_MAX_DATA_SIZE+16 - 1 downto 0);
Signal cam_di_vl_s : STD_LOGIC;
Signal cam_di_ry_s : STD_LOGIC;
Signal cam_do_s : UNSIGNED(63 downto 0);
Signal cam_do_ry_s : STD_LOGIC;
Signal cam_do_vl_s : STD_LOGIC;
Signal cam_err_s : UNSIGNED(5 downto 0);
Signal cam_done_s : STD_LOGIC;
--! Error injection registers
signal active_err_s : T_CAM_ERR;
signal hsync_err_s : T_CAM_ERR;
signal vsync_err_s : T_CAM_ERR;
--! Signals for output fifo
signal out_fifo_rst_s : STD_LOGIC;
signal out_fifo_full_s : STD_LOGIC;
signal out_fifo_fill_s : UNSIGNED(6 downto 0);
signal out_fifo_di_s : UNSIGNED(63 downto 0) := (others => '0');
signal out_fifo_do_s : UNSIGNED(1023 downto 0);
signal out_fifo_do_vl_s : STD_LOGIC;
signal out_fifo_ack_s : STD_LOGIC;
--! Is the output fifo flushed?
signal out_fifo_flu_s : STD_LOGIC;
signal pkg_cnt_s : unsigned(id_out'range);
procedure str_unsigned
(str : string;
signal data : out unsigned;
signal data_valid : out unsigned) is
begin
for i in str'range loop
data(data'high-(i-1)*8 downto data'high-(i-1)*8-7) <=
to_unsigned(character'pos(str(i)), 8);
end loop;
data_valid <= to_unsigned(str'length, data_valid'length);
end procedure str_unsigned;
procedure hw_cfg_status(
signal hw_cfg_out : out unsigned(G_MAX_DATA_SIZE-1 downto 0);
signal hw_cfg_len_out : out unsigned(15 downto 0);
instances : in natural)
is
variable hw_cfg : unsigned(G_MAX_DATA_SIZE-1 downto 0);
variable hw_cfg_len : natural := 0;
variable pos : natural := G_MAX_DATA_SIZE-1;
variable tmp : natural;
begin
--HW-Version (4 Bytes -> hg revision)
hw_cfg(pos downto pos - (4*8-1)) := to_unsigned(C_VERSION, 4*8);
hw_cfg_len := hw_cfg_len + 4;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- MAX_DATA_LENGTH (2 Bytes)
hw_cfg(pos downto pos - (2*8-1)) := to_unsigned(G_MAX_DATA_SIZE, 2*8);
hw_cfg_len := hw_cfg_len + 2;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of max img_width (1 byte)
tmp := div_ceil(log2_ceil(G_IMG_WIDTH), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- max img_width
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_MAX_IMAGE_WIDTH, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- img_width
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_IMAGE_WIDTH, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of max img_height (1 byte)
tmp := div_ceil(log2_ceil(C_MAX_IMAGE_HEIGHT), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--max img_height
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_MAX_IMAGE_HEIGHT, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--img_height
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(C_IMAGE_HEIGHT, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of box_size (1 byte)
tmp := div_ceil(log2_ceil(log2_ceil(C_MAX_IMAGE_HEIGHT)+1+log2_ceil(C_MAX_IMAGE_WIDTH)+1), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--box_size
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(log2_ceil(C_MAX_IMAGE_HEIGHT)+1+log2_ceil(C_MAX_IMAGE_WIDTH)+1, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of stimuli_length (log2(stimuli length))
--tmp := div_ceil(log2_ceil(2*C_MAX_IMAGE_HEIGHT * 2*C_MAX_IMAGE_WIDTH), 8);
tmp := 1;
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--stimuli_length
--hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(2**C_MAX_IMAGE_HEIGHT * 2**C_MAX_IMAGE_WIDTH, tmp*8);
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(0, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
--length of instances (ceil(log2(instances)))
tmp := div_ceil(log2_ceil(1), 8);
hw_cfg(pos downto pos - (1*8-1)) := to_unsigned(tmp, 1*8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- instances
hw_cfg(pos downto pos - (tmp*8-1)) := to_unsigned(0, tmp*8);
hw_cfg_len := hw_cfg_len + tmp;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- comparator error_type length
hw_cfg(pos downto pos - (8-1)) := to_unsigned(cam_err_s'high-cam_err_s'low+1, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- rev error_type length
hw_cfg(pos downto pos - (8-1)) := to_unsigned(0, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- dut error_type length
hw_cfg(pos downto pos - (8-1)) := to_unsigned(0, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- magic number for camera simulation mode
hw_cfg(pos downto pos - (8-1)) := to_unsigned(42, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
-- T_CAM_ERR_ARY_LENGTH
hw_cfg(pos downto pos - (8-1)) := to_unsigned(T_CAM_ERR'length, 8);
hw_cfg_len := hw_cfg_len + 1;
pos := G_MAX_DATA_SIZE-1 - hw_cfg_len*8;
hw_cfg_len_out <= to_unsigned(hw_cfg_len, 2*8);
hw_cfg_out <= hw_cfg;
end procedure hw_cfg_status;
procedure read_err(
signal length_in : in unsigned(15 downto 0);
signal data_in : in unsigned(G_MAX_DATA_SIZE - 1 downto 0);
signal err_s : out T_CAM_ERR)
is
constant c_word_len : natural := (err_s(0).row'length + err_s(0).col'length + 1);
begin
-- data vector:
-- row size: log2_ceil(C_MAX_IMAGE_HEIGHT+1)
-- col size: log2_ceil(C_MAX_IMAGE_WIDTH+1)
-- data size: 1bit
-- | row(0), col(0), data(0) | row(1), col(1), data(1) | ...
for i in err_s'range loop
err_s(i).row <= data_in(
data_in'high - i*c_word_len downto
data_in'high - i*c_word_len - err_s(0).row'length +1);
err_s(i).col <= data_in(
data_in'high - i*c_word_len - err_s(0).row'length downto
data_in'high - i*c_word_len
- err_s(0).row'length - err_s(0).col'length +1);
err_s(i).val <= data_in(
data_in'high - i*c_word_len
- err_s(0).row'length - err_s(0).col'length);
end loop;
end procedure read_err;
begin
run_out <= '1' when int_state_s = PROCESSING else '0';
--! @brief This process generates the states of the incoming commands
p_rx_decode : process (rst_in, rx_clk_in) is
variable tmp : natural;
begin
if rst_in = '1' then
rx_state_s <= NOP;
cam_min_fll_lvl_s <= to_unsigned(1, cam_min_fll_lvl_s'length);
active_err_s <= (others => (row => (others => '1'), col => (others => '1'), val => '0'));
hsync_err_s <= (others => (row => (others => '1'), col => (others => '1'), val => '0'));
vsync_err_s <= (others => (row => (others => '1'), col => (others => '1'), val => '0'));
pkg_cnt_s <= (others => '0');
out_fifo_flu_s <= '0';
elsif rising_edge(rx_clk_in) then
rx_state_s <= NOP;
if int_state_s = DONE and out_fifo_fill_s*64/8 < G_MAX_DATA_SIZE/8 and
out_fifo_fill_s > 0 and out_fifo_flu_s = '0'
then
rx_state_s <= SEND_OUT_LAST;
out_fifo_flu_s<= '1';
elsif out_fifo_do_vl_s = '1' then
rx_state_s <= SEND_OUT;
pkg_cnt_s <= pkg_cnt_s + 1;
end if;
cam_di_vl_s <= '0';
if dec_valid_in = '1' then
--! default
if header_error_in = '1' then
rx_state_s <= HEAD_ERR;
else
case type_in is
when C_TYP_ACK =>
rx_state_s <= ACK;
when C_TYP_NACK =>
rx_state_s <= NACK;
when C_TYP_HW_CFG =>
rx_state_s <= HW_CFG;
when C_TYP_STATUS =>
rx_state_s <= STATUS;
when C_TYP_RESET =>
rx_state_s <= RESET;
when C_TYP_SEND_PX =>
rx_state_s <= SEND_PX;
out_fifo_flu_s <= '0';
if cam_di_ry_s = '1' then
cam_di_s <= length_in & data_in(data_in'high downto data_in'high+1-G_MAX_DATA_SIZE);
cam_di_vl_s <= '1';
end if;
when C_TYP_SET_FLL_LVL =>
rx_state_s <= SET_FLL_LVL;
cam_min_fll_lvl_s <= data_in(data_in'high downto data_in'high-15);
when C_TYP_SET_ACT_ERR =>
rx_state_s <= SET_ACT_ERR;
if length_in = C_ERR_PKG_LEN then
read_err(length_in, data_in, active_err_s);
end if;
when C_TYP_SET_HSY_ERR =>
rx_state_s <= SET_HSY_ERR;
if length_in = C_ERR_PKG_LEN then
read_err(length_in, data_in, hsync_err_s);
end if;
when C_TYP_SET_VSY_ERR =>
rx_state_s <= SET_VSY_ERR;
if length_in = C_ERR_PKG_LEN then
read_err(length_in, data_in, vsync_err_s);
end if;
when others =>
rx_state_s <= UNKNOWN;
end case;
end if; --header_error
end if; -- dec_valid
end if; --rst/clk
end process p_rx_decode;
--! @brief This process generates the answers on rx messages according to
--! udp_protocol.txt
p_tx_answer : process (
rst_in, rx_state_s, id_in, int_state_s, length_in, cam_di_ry_s,
out_fifo_fill_s, pkg_cnt_s, out_fifo_do_s
) is
variable tmp : natural;
begin
if rst_in = '1' then
--reset
rst_prepare_s <= '0';
type_out <= (others => '-');
id_out <= (others => '-');
length_out <= (others => '0');
data_out <= (others => '-');
enc_valid_out <= '0';
out_fifo_ack_s <= '0';
else
-- default values
enc_valid_out <= '0';
type_out <= (others => '-');
id_out <= (others => '-');
length_out <= (others => '0');
data_out <= (others => '-');
rst_prepare_s <= '0';
out_fifo_ack_s <= '0';
case rx_state_s is
when NOP =>
null;
when SEND_OUT_LAST =>
--image processed completed flushing buffer
--the C_TYP_SEND_BOX uses the length_out as number of valid bits
--instead of bytes
enc_valid_out <= '1';
type_out <= C_TYP_SEND_BOX;
id_out <= pkg_cnt_s;
length_out <= resize(out_fifo_fill_s*64/8, length_out'length);
data_out <= out_fifo_do_s;
when SEND_OUT =>
--enough data stored to fill one complet package
enc_valid_out <= '1';
type_out <= C_TYP_SEND_BOX;
id_out <= pkg_cnt_s;
length_out <= to_unsigned(G_MAX_DATA_SIZE/8, length_out'length);
data_out <= out_fifo_do_s;
out_fifo_ack_s <= '1';
when ACK =>
-- This case is ignored
-- TODO: implement send queue. The queue stores all send commands
-- until a ACK for this id is received. After a timeout do resend
null;
when NACK =>
-- Ignore NACK
-- TODO: remove from queue or resend
null;
when HEAD_ERR =>
enc_valid_out <= '1';
type_out <= C_TYP_NACK;
id_out <= id_in;
str_unsigned("corrupt header", data_out, length_out);
--length_out <= x"0e";
--data_out(G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(14*8))
--<= x"636f727275707420686561646572"; --corrupt header in ASCII
when HW_CFG =>
enc_valid_out <= '1';
type_out <= C_TYP_ACK;
id_out <= id_in;
hw_cfg_status(data_out, length_out, G_COMP_INST);
when STATUS =>
enc_valid_out <= '1';
type_out <= C_TYP_ACK;
id_out <= id_in;
--constant tmp
length_out <= to_unsigned(1, 16);
case int_state_s is
when RESTART =>
data_out (G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(1*8))
<= x"80";
when PROCESSING =>
data_out (G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(1*8))
<= x"81";
when DONE =>
data_out (G_MAX_DATA_SIZE-1 downto G_MAX_DATA_SIZE-(1*8))
<= x"82";
end case;
--add stimuli with alignment to the lsb
tmp := data_out'high-8+1;
when RESET =>
rst_prepare_s <= '1';
enc_valid_out <= '1';
type_out <= C_TYP_ACK;
id_out <= id_in;
when SEND_PX =>
enc_valid_out <= '1';
id_out <= id_in;
if cam_di_ry_s = '1' then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
str_unsigned("fifo full", data_out, length_out);
end if;
when SET_FLL_LVL =>
enc_valid_out <= '1';
id_out <= id_in;
type_out <= C_TYP_ACK;
when SET_ACT_ERR =>
enc_valid_out <= '1';
id_out <= id_in;
if length_in = C_ERR_PKG_LEN then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
end if;
when SET_HSY_ERR =>
enc_valid_out <= '1';
id_out <= id_in;
if length_in = C_ERR_PKG_LEN then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
end if;
when SET_VSY_ERR =>
enc_valid_out <= '1';
id_out <= id_in;
if length_in = C_ERR_PKG_LEN then
type_out <= C_TYP_ACK;
else
type_out <= C_TYP_NACK;
end if;
when UNKNOWN =>
enc_valid_out <= '1';
id_out <= id_in;
type_out <= C_TYP_NACK;
str_unsigned("cmd unknown", data_out, length_out);
--when others =>
-- enc_valid_out <= '1';
-- id_out <= id_in;
-- type_out <= C_TYP_NACK;
-- str_unsigned("unexpected", data_out, length_out);
end case;
end if; --rst
end process p_tx_answer;
--! Statemachine for internal state
--! States:
--! IDLE just resetted nothing to do
--! RESTART do a restart of camif
--! PROCESSING pixel receive in progress
--! DONE image processed
p_int_state : process (rst_in, rx_clk_in) is
begin
if rst_in = '1' then
int_state_s <= RESTART;
rst_exec_s <= '0';
restart_cnt_s <= to_unsigned(C_RESTART_WAIT, restart_cnt_s'length);
elsif rising_edge(rx_clk_in) then
--! default Values
if rst_prepare_s = '1' then
rst_exec_s <= '1';
end if;
case int_state_s is
when RESTART =>
rst_exec_s <= '0';
restart_cnt_s <= restart_cnt_s - 1;
-- restart wait at least C_RESTART_WAIT clock cycles
-- and set reset signals
if restart_cnt_s = 0 then
int_state_s <= PROCESSING;
restart_cnt_s <= to_unsigned(C_RESTART_WAIT, restart_cnt_s'length);
end if;
when PROCESSING =>
if cam_done_s = '1' then
int_state_s <= DONE;
end if;
if rst_exec_s = '1' then
int_state_s <= RESTART;
end if;
when DONE =>
if rst_exec_s = '1' then
int_state_s <= RESTART;
end if;
end case;
end if;
end process p_int_state;
--! @brief Process for controling internal signals
p_ctrl : process (int_state_s, rst_in) is
begin
--default values
cam_rst_s <= '0';
out_fifo_rst_s <= '0';
if rst_in = '1' then
cam_rst_s <= '1';
else
case int_state_s is
when RESTART =>
-- reset the counter and the verifier
cam_rst_s <= '1';
out_fifo_rst_s <= '1';
when PROCESSING =>
null;
when DONE =>
null;
end case;
end if;
end process p_ctrl;
-- send ready to data_out of camif if fifo has space to store value
cam_do_ry_s <= not out_fifo_full_s;
out_fifo_di_s <= cam_do_s;
out_fifo: entity work.box_out_storage
port map(
rst_in => out_fifo_rst_s,
clk_in => rx_clk_in,
full_out => out_fifo_full_s,
fill_lvl_out => out_fifo_fill_s,
data_in => out_fifo_di_s,
data_vl_in => cam_do_vl_s,
data_out => out_fifo_do_s,
data_vl_out => out_fifo_do_vl_s,
data_ack_in => out_fifo_ack_s
);
camif : entity work.camif
generic map(
--! Image width
-- value from ccl_dut common.vhd
G_IMG_WIDTH => C_IMAGE_WIDTH,
--! Image height
-- value from ccl_dut common.vhd
G_IMG_HEIGHT => C_IMAGE_HEIGHT,
--! Number of parallel pixels
G_NO_PX => no_pixels,
--! Input width in bits
G_IN_WIDTH => G_MAX_DATA_SIZE,
G_FIFO_SIZE => 256
)
port map(
clk_in => rx_clk_in,
clk_cam_in => clk_dut_in,
rst_in => cam_rst_s,
min_fll_lvl_in => cam_min_fll_lvl_s,
-- input of image data
-- 16 MSB bits are used to save the number of valid pixels
-- only the last package of pixels can be smaller than 1024
data_in => cam_di_s, --: in UNSIGNED(G_IN_WIDTH+16 - 1 downto 0);
data_vl_in => cam_di_vl_s, -- : in STD_LOGIC;
data_in_rdy_out => cam_di_ry_s,
--! output data out
data_out => cam_do_s,
data_rdy_in => cam_do_ry_s,
data_vl_out => cam_do_vl_s,
--! error value
error_out => cam_err_s,
--! high if image processing is completed
done_out => cam_done_s,
--vsync error injection
vsync_err_in => vsync_err_s,
--hsync error injection
hsync_err_in => hsync_err_s,
--px active error injection
-- if value = 1 inserts a additional pixel before the given coordinate
-- if value = 0 forces the active signal to zero for the given coordinate
active_err_in => active_err_s
);
end architecture cam_control_unit_arc;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SCMUL3236.VHD ***
--*** ***
--*** Function: Scale (normalized for overflow ***
--*** only) a 32 or 36 bit mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_scmul3236 IS
GENERIC (mantissa : positive := 32);
PORT (
frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1)
);
END hcc_scmul3236;
ARCHITECTURE rtl OF hcc_scmul3236 IS
signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1);
BEGIN
-- for single 32 bit mantissa input
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..].....
-- output
-- [S ][1 ][M...M]
-- [32][31][30..1], count is shift
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- shift 0 if "01XX" or "10XX"
scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1)));
-- shift 1 if "001XX" or "110XX"
scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR
(frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2)));
-- shift 2 if "0001XX" or "1110XX"
scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3)));
-- shift 3 if "00001XX" or "11110XX"
scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND NOT(frac(mantissa-4)));
-- shift 4 if "00000XX" or "11111XX"
scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND
NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR
(frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND
frac(mantissa-3) AND frac(mantissa-4));
scaled(mantissa) <= frac(mantissa);
gsa: FOR k IN 1 TO mantissa-5 GENERATE
scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR
(frac(mantissa-k-3) AND scale(2)) OR
(frac(mantissa-k-2) AND scale(3)) OR
(frac(mantissa-k-1) AND scale(4)) OR
(frac(mantissa-k) AND scale(5));
END GENERATE;
scaled(4) <= (frac(1) AND scale(2)) OR
(frac(2) AND scale(3)) OR
(frac(3) AND scale(4)) OR
(frac(4) AND scale(5));
scaled(3) <= (frac(1) AND scale(3)) OR
(frac(2) AND scale(4)) OR
(frac(3) AND scale(5));
scaled(2) <= (frac(1) AND scale(4)) OR
(frac(2) AND scale(5));
scaled(1) <= (frac(1) AND scale(5));
-- shifts everything to SSSSS1XXXXX
-- if '1' is in a position greater than 27,add to exponent
count(3) <= scale(5);
count(2) <= scale(4) OR scale(3);
count(1) <= scale(4) OR scale(2);
END rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
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