content stringlengths 1 1.04M ⌀ |
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package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
|
package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
|
package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
|
package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myNot is
port(a: in std_logic; s: out std_logic);
end myNot;
architecture behavioral of myNot is
component myNand2
port(a: in std_logic; b: in std_logic; s: out std_logic);
end component;
signal one: std_logic;
begin
one <= '1';
myNand2_1: myNand2 port map(a => a, b => '1', s => s);
end behavioral;
|
-- **********************************************************
-- Corso di Reti Logiche - "Mp3 Recorder" Project
-- Andrea Carrer - 729101
-- Module RegistratorePortatile.vhd
-- Version 1.02 - 18.03.2013
-- **********************************************************
-- **********************************************************
-- Main Module, written in VHDL.
-- Definisce la logica e le connessioni tra i diversi moduli:
-- - PlayRecord: gestione comandi registratore
-- - Display: gestione segnali grafica
-- - Audio_Controller: interfaccia con il chip WM8731
-- - VGA_Adapter: interfaccia con l'uscita VGA
-- - SDRAM: interfaccia con la SDRAM
-- E gestisce i componenti I/O della scheda Altera DE1
-- **********************************************************
-- --------------------------------------------------------------------------------------------
-- --------------------------------------------------------------------- Main Module definition
-- --------------------------------------------------------------------------------------------
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity RegistratorePortatile is port(
DRAM_DQ: inout std_logic_vector(15 downto 0); -- SDRAM Data bus 16 Bits
DRAM_ADDR: out std_logic_vector(11 downto 0); -- SDRAM Address bus 12 Bits
DRAM_LDQM: buffer std_logic; -- SDRAM Low-byte Data Mask
DRAM_UDQM: buffer std_logic; -- SDRAM High-byte Data Mask
DRAM_WE_N: out std_logic; -- SDRAM Write Enable
DRAM_CAS_N: out std_logic; -- SDRAM Column Address Strobe
DRAM_RAS_N: out std_logic; -- SDRAM Row Address Strobe
DRAM_CS_N: out std_logic; -- SDRAM Chip Select
DRAM_BA_0: buffer std_logic; -- SDRAM Bank Address 0
DRAM_BA_1: buffer std_logic; -- SDRAM Bank Address 1
DRAM_CLK: out std_logic; -- SDRAM Clock
DRAM_CKE: out std_logic; -- SDRAM Clock Enable
CLOCK_50: in std_logic; -- On Board 50 MHz
KEY: in std_logic_vector(3 downto 0); -- Pushbutton[3:0]
SW: in std_logic_vector(9 downto 0); -- Toggle Switch[9:0]
HEX0: out std_logic_vector(6 downto 0); -- Seven Segment Digit 0
HEX1: out std_logic_vector(6 downto 0); -- Seven Segment Digit 1
HEX2: out std_logic_vector(6 downto 0); -- Seven Segment Digit 2
HEX3: out std_logic_vector(6 downto 0); -- Seven Segment Digit 3
LEDG: out std_logic_vector(7 downto 0); -- LED Green[7:0]
LEDR: out std_logic_vector(9 downto 0); -- LED Red[9:0]
AUD_ADCLRCK:inout std_logic; -- Audio CODEC ADC LR Clock
AUD_ADCDAT: in std_logic; -- Audio CODEC ADC Data
AUD_DACLRCK:inout std_logic; -- Audio CODEC DAC LR Clock
AUD_DACDAT: out std_logic; -- Audio CODEC DAC Data
AUD_BCLK: inout std_logic; -- Audio CODEC Bit-Stream Clock
AUD_XCK: out std_logic; -- Audio CODEC Chip Clock
I2C_SDAT: inout std_logic; -- I2C Data
I2C_SCLK: out std_logic; -- I2C Clock
VGA_CLK: inout std_logic; -- VGA Clock
VGA_HS: out std_logic; -- VGA H_SYNC
VGA_VS: out std_logic; -- VGA V_SYNC
VGA_BLANK: out std_logic; -- VGA BLANK
VGA_SYNC: out std_logic; -- VGA SYNC
VGA_R: out std_logic_vector(9 downto 0); -- VGA Red[9:0]
VGA_G: out std_logic_vector(9 downto 0); -- VGA Green[9:0]
VGA_B: out std_logic_vector(9 downto 0) -- VGA Blue[9:0]
);
end RegistratorePortatile;
-- --------------------------------------------------------------------------------------------
-- ------------------------------------------------------------------------ Definizione segnali
-- --------------------------------------------------------------------------------------------
architecture behaviour of RegistratorePortatile is
-------------------------------------------------------------------------------------------
-------------------------------------------------------------------------- Componenti usati
-------------------------------------------------------------------------------------------
component SDRAM_pll is port(
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic
);
end component;
component sdram is port(
az_addr: in std_logic_vector(21 downto 0);
az_be_n: in std_logic_vector(1 downto 0);
az_cs: in std_logic;
az_data: in std_logic_vector(15 downto 0);
az_rd_n: in std_logic;
az_wr_n: in std_logic;
clk: in std_logic;
reset_n: in std_logic;
za_data: out std_logic_vector(15 downto 0);
za_valid: out std_logic;
za_waitrequest: out std_logic;
zs_addr: out std_logic_vector(11 downto 0);
zs_ba: out std_logic_vector(1 downto 0);
zs_cas_n: out std_logic;
zs_cke: out std_logic;
zs_cs_n: out std_logic;
zs_dq: inout std_logic_vector(15 downto 0);
zs_dqm: out std_logic_vector(1 downto 0);
zs_ras_n: out std_logic;
zs_we_n: out std_logic
);
end component;
component Audio_Controller is port(
clk: in std_logic;
reset: in std_logic;
clear_audio_in_memory: in std_logic;
read_audio_in: in std_logic;
clear_audio_out_memory: in std_logic;
left_channel_audio_out: in std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
right_channel_audio_out: in std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
write_audio_out: in std_logic;
AUD_ADCDAT: in std_logic;
AUD_BCLK: inout std_logic;
AUD_ADCLRCK: inout std_logic;
AUD_DACLRCK: inout std_logic;
I2C_SDAT: inout std_logic;
audio_in_available: out std_logic;
left_channel_audio_in: buffer std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
right_channel_audio_in: out std_logic_vector(32 downto 1); -- TODO parametrizzare con AUDIO_DATA_WIDTH
audio_out_allowed: out std_logic;
AUD_XCK: out std_logic;
AUD_DACDAT: out std_logic;
I2C_SCLK: out std_logic;
useMicInput: in std_logic
);
end component;
component PlayRecord is port (
CLOCK_50 : in std_logic;
CLOCK_1S : in std_logic;
reset : in std_logic;
ram_addr : out std_logic_vector(21 downto 0);
ram_data_in : out std_logic_vector(15 downto 0);
ram_read : out std_logic;
ram_write : out std_logic;
ram_data_out : in std_logic_vector(15 downto 0);
ram_valid : in std_logic;
ram_waitrq : in std_logic;
audio_out : out std_logic_vector(15 downto 0);
audio_in : in std_logic_vector(15 downto 0);
audio_out_allowed : in std_logic;
audio_in_available : in std_logic;
write_audio_out : out std_logic;
read_audio_in : out std_logic;
play : in std_logic;
rec : in std_logic;
pause : in std_logic;
speed : in std_logic_vector(1 downto 0);
ram_addr_max : in std_logic_vector(21 downto 0);
playLimitReached : inout std_logic;
secondsCounter : inout std_logic_vector(7 downto 0)
);
end component;
component VGA_Adapter is port(
resetn: in std_logic;
clock: in std_logic;
clock_25: in std_logic;
colour: in std_logic;
x: in std_logic_vector(8 downto 0); -- x coordinate
y: in std_logic_vector(7 downto 0); -- y coordinate
plot: in std_logic; -- Quando e'=1, il pixel (x,y) cambiera' colore (bisogna plottare)
-- Segnali per il DAC per pilotare the monitor.
VGA_R: out std_logic_vector(9 downto 0);
VGA_G: out std_logic_vector(9 downto 0);
VGA_B: out std_logic_vector(9 downto 0);
VGA_HS: out std_logic;
VGA_VS: out std_logic;
VGA_BLANK: out std_logic;
VGA_SYNC: out std_logic
);
end component;
component Display is port (
clock : in std_logic;
reset : in std_logic;
freeze : in std_logic;
data : in std_logic_vector(15 downto 0);
x : inout std_logic_vector(8 downto 0);
y : inout std_logic_vector(7 downto 0);
color : inout std_logic;
plot : inout std_logic
);
end component;
component BinaryToBcd is port (
A : in std_logic_vector(7 downto 0);
ONES : out std_logic_vector(3 downto 0);
TENS : out std_logic_vector(3 downto 0);
HUNDREDS : out std_logic_vector(1 downto 0)
);
end component;
component hex2seg is port (
hex: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(6 downto 0)
);
end component;
-- Segnali usati per leggere e scrivere dalla RAM
signal ram_addr: std_logic_vector(21 downto 0); -- Indirizzamento a 22 bit
signal ram_data_in, ram_data_out: std_logic_vector(15 downto 0); -- Bus dati a 16 bit I/O
signal ram_valid, ram_waitrq, ram_read, ram_write: std_logic; -- Segnali di abilitazione per lettura/scrittura
signal ram_addr_max: std_logic_vector(21 downto 0); -- Memorizza l'ultimo banco di RAM memorizzato
signal playLimitReached: std_logic; -- A 1 se durante il play si raggiunge la fine della registrazione
-- Segnali per gestione lettura/scrittura audio
signal audio_out, audio_in: std_logic_vector(15 downto 0); -- Bus a 16 bit
signal audio_out_allowed, audio_in_available: std_logic; -- Segnali di controllo abilitazione lettura/scrittura audio
signal write_audio_out, read_audio_in: std_logic;
-- Segnali per interfaccia con VGA
signal vga_color: std_logic; -- Colore (monocromatico, pixel acceso/spento)
signal vga_x: std_logic_vector(8 downto 0); -- x massimo = 319 (9 bit)
signal vga_y: std_logic_vector(7 downto 0); -- y massimo = 239 (8 bit)
signal vga_plot: std_logic; -- Abilitazione a scrittura pixel
-- Visualizzo l'uscita se sono in Play, altrimenti visualizzo l'ingresso del microfono
signal display_data: std_logic_vector(15 downto 0);
signal display_data_scaled: std_logic_vector(15 downto 0); -- Dati in scala usati per VGA e led rossi (volume)
signal useMicInput: std_logic; -- Quando e' a 1 usa il microfono, altrimenti il LineIn
signal blink_cnt: std_logic_vector(25 downto 0); -- Usato per blink pausa
-- Contatore di secondi
signal secondsCounter: std_logic_vector(7 downto 0); -- Contatore di secondi durante Play & Rec
signal secondsCounter0, secondsCounter1: std_logic_vector(3 downto 0); -- BCD
signal secondsCounter2: std_logic_vector(1 downto 0); -- BCD
signal seconds_max: std_logic_vector(7 downto 0); -- Memorizza i secondi memorizzati con l'ultima registrazione
signal seconds_max0, seconds_max1: std_logic_vector(3 downto 0); -- BCD
signal seconds_max2: std_logic_vector(1 downto 0); -- BCD
signal cnt_clock: integer;
signal CLOCK_1S: std_logic;
-----------------------------------------------------------------------------------------------
------------------------------------------------------------ Definizione input dalla Altera DE1
-----------------------------------------------------------------------------------------------
-- Tasti e switch per comandi
signal reset: std_logic := not KEY(0); -- Reset del sistema
signal AudioInChanged: std_logic := not KEY(1); -- Gestione del soft reset del chip audio
signal DisplayRamAddr: std_logic := not KEY(2); -- Se premuto visualizza l'indirizzo RAM anziche' i secondi
signal play_Cmd: std_logic := SW(0); -- Riproduce l'audio
signal pause_Cmd: std_logic := SW(1); -- Mette in pausa
signal record_Cmd: std_logic := SW(2); -- Registra
signal speed: std_logic_vector(1 downto 0) := SW(4 downto 3); -- Settaggi di velocita riproduzione
signal scale: std_logic_vector(1 downto 0) := SW(6 downto 5); -- Scala di visualizzazione dell'onda
signal showMaxAddr: std_logic := SW(7); -- Visualizzazione del limite dell'ultima registrazione
-----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------- Segnali di buffer
-----------------------------------------------------------------------------------------------
-- Segnali per display a 7 segmenti
signal h0_sig: std_logic_vector(3 downto 0);
signal h1_sig: std_logic_vector(3 downto 0);
signal h2_sig: std_logic_vector(3 downto 0);
signal h3_sig: std_logic_vector(3 downto 0);
signal ramMaxAddr_sig: std_logic_vector(1 downto 0); -- Serve per assegnare h0 e h1
signal zs_ba_sig: std_logic_vector(1 downto 0);
signal zs_dqm_sig: std_logic_vector(1 downto 0);
signal left_channel_audio_in_sig: std_logic_vector(32 downto 1);
begin
display_data <= audio_out when play_Cmd='1' else audio_in;
-----------------------------------------------------------------------------------------------
--------------------------------------------------- Definizione output diretti sulla Altera DE1
-----------------------------------------------------------------------------------------------
-- Spie per livello audio (volume) sui led rossi
LEDR(0) <= '0' when display_data_scaled(15)='1' else display_data_scaled(0);
LEDR(1) <= '0' when display_data_scaled(15)='1' else display_data_scaled(2);
LEDR(2) <= '0' when display_data_scaled(15)='1' else display_data_scaled(4);
LEDR(3) <= '0' when display_data_scaled(15)='1' else display_data_scaled(6);
LEDR(4) <= '0' when display_data_scaled(15)='1' else display_data_scaled(8);
LEDR(5) <= '0' when display_data_scaled(15)='1' else display_data_scaled(10);
LEDR(6) <= '0' when display_data_scaled(15)='1' else display_data_scaled(12);
LEDR(7) <= '0' when display_data_scaled(15)='1' else display_data_scaled(14);
-- Spia per la pausa
LEDG(7) <= blink_cnt(25) when pause_Cmd='1' and (play_Cmd='1' or record_Cmd='1') else '0';
LEDG(6) <= play_Cmd and playLimitReached;
-- Spia per reset
LEDG(0) <= reset;
-- Spia per input audio
LEDG(1) <= useMicInput;
-- Clock 1S (debug)
LEDG(2) <=
CLOCK_1S
and (play_Cmd or record_Cmd)
and (not pause_Cmd)
and (not playLimitReached);
-- Led non usati
LEDR(9 downto 8) <= "00";
LEDG(5 downto 3) <= "000";
-----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------- Segnali di buffer
-----------------------------------------------------------------------------------------------
-- Visualizzo l'uscita se sono in Play, altrimenti visualizzo l'ingresso del microfono
display_data <= audio_out when play_Cmd='1' else audio_in;
ramMaxAddr_sig <= DisplayRamAddr & showMaxAddr;
with ramMaxAddr_sig select
h0_sig <=
ram_addr_max(17 downto 14) when "11", -- Mostra Max Ram Address
ram_addr(17 downto 14) when "10", -- Mostra Ram Address
seconds_max0 when "01", -- Mostra Max Secondi
secondsCounter0 when "00", -- Mostra secondi
"0000" when others;
with ramMaxAddr_sig select
h1_sig <=
ram_addr_max(21 downto 18) when "11", -- Mostra Max Ram Address
ram_addr(21 downto 18) when "10", -- Mostra Ram Address
seconds_max1 when "01", -- Mostra Max Secondi
secondsCounter1 when "00", -- Mostra secondi
"0000" when others;
h2_sig <= "00" & scale;
h3_sig <= "00" & speed;
zs_ba_sig <= DRAM_BA_1 & DRAM_BA_0;
zs_dqm_sig <= DRAM_UDQM & DRAM_LDQM;
left_channel_audio_in_sig <= audio_in & "XXXXXXXXXXXXXXXX";
-----------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------- Processi
-----------------------------------------------------------------------------------------------
-- Intercetto il cambio di input per generare un "soft reset" del codec
-- Visto che il settaggio della periferica deve essere fatto allo startup del CODEC
process (AudioInChanged)
begin
if rising_edge(AudioInChanged) then
useMicInput <= not useMicInput;
end if;
end process;
-- Calcolo dei dati in base alla scala scelta: piu' e' alto il valore di scala piu'
-- Viene ridotta l'altezza della forma d'onda visualizzata
process (all)
begin
case(scale) is
when "00" => display_data_scaled <= display_data;
when "01" => display_data_scaled <= display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(14 downto 4);
when "10" => display_data_scaled <= display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(14 downto 8);
when "11" => display_data_scaled <= display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(15)
& display_data(14 downto 12);
end case;
end process;
-- Blinking della pausa
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
blink_cnt <= blink_cnt + 1;
end if;
end process;
-- Memorizzazione dell'ultimo indirizzo registrato
process (record_Cmd)
begin
if falling_edge(record_Cmd) then
ram_addr_max <= ram_addr;
seconds_max <= secondsCounter;
end if;
end process;
-- Generazione clock a 2 Hz per contare i secondi
process (CLOCK_50)
begin
if rising_edge(CLOCK_50) then
if (cnt_clock = 25000000) then
CLOCK_1S <= not CLOCK_1S;
cnt_clock <= 0;
else
cnt_clock <= cnt_clock + 1;
end if;
end if;
end process;
-----------------------------------------------------------------------------------------------
----------------------------------------------------------------------- Collegamento Componenti
-----------------------------------------------------------------------------------------------
-- Modulo PLL generato con la megafunction ALTPLL
SDRAM_PLL_Entity: SDRAM_PLL port map(
inclk0 => CLOCK_50,
c0 => DRAM_CLK,
c1 => VGA_CLK,
c2 => AUD_XCK
);
-- Modulo generato dal SOPC builder
SDRAM_Entity: sdram port map(
az_addr => ram_addr,
az_be_n => "00",
az_cs => '1',
az_data => ram_data_in,
az_rd_n => not ram_read,
az_wr_n => not ram_write,
clk => CLOCK_50,
reset_n => not reset,
za_data => ram_data_out,
za_valid => ram_valid,
za_waitrequest => ram_waitrq,
zs_addr => DRAM_ADDR,
zs_ba => zs_ba_sig,
zs_cas_n => DRAM_CAS_N,
zs_cke => DRAM_CKE,
zs_cs_n => DRAM_CS_N,
zs_dq => DRAM_DQ,
zs_dqm => zs_dqm_sig,
zs_ras_n => DRAM_RAS_N,
zs_we_n => DRAM_WE_N
);
-- Lettura e scrittura sul chip audio
Audio_Controller_Entity: Audio_Controller port map (
clk => CLOCK_50,
reset => reset or AudioInChanged,
clear_audio_in_memory => '0',
read_audio_in => read_audio_in,
clear_audio_out_memory => '0',
left_channel_audio_out => audio_out & "0000000000000000",
right_channel_audio_out => audio_out & "0000000000000000",
write_audio_out => write_audio_out,
AUD_ADCDAT => AUD_ADCDAT,
AUD_BCLK => AUD_BCLK,
AUD_ADCLRCK => AUD_ADCLRCK,
AUD_DACLRCK => AUD_DACLRCK,
I2C_SDAT => I2C_SDAT,
audio_in_available => audio_in_available,
left_channel_audio_in => left_channel_audio_in_sig,
right_channel_audio_in => OPEN,
audio_out_allowed => audio_out_allowed,
AUD_XCK => OPEN,
AUD_DACDAT => AUD_DACDAT,
I2C_SCLK => I2C_SCLK,
useMicInput => useMicInput
);
-- Gestisce registrazione su RAM e riproduzione da RM dell'audio
PlayRecord_Entity: PlayRecord port map(
CLOCK_50,
CLOCK_1S,
reset,
ram_addr,
ram_data_in,
ram_read,
ram_write,
ram_data_out,
ram_valid,
ram_waitrq,
audio_out,
audio_in,
audio_out_allowed,
audio_in_available,
write_audio_out,
read_audio_in,
play_Cmd,
record_Cmd,
pause_Cmd,
speed,
ram_addr_max,
playLimitReached,
secondsCounter
);
-- Inizializzazione adattatore monitor VGA
VGA_Adapter_Entity: VGA_Adapter port map(
NOT reset,
CLOCK_50,
VGA_CLK,
vga_color,
vga_x,
vga_y,
vga_plot,
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC
);
-- Modulo che gestisce il display su monitor VGA
Display_Entity: Display port map(
CLOCK_50,
reset,
pause_Cmd,
display_data_scaled,
vga_x,
vga_y,
vga_color,
vga_plot
);
-- Convertitori da Binario a BCD
SecondsCounter_Entity: BinaryToBcd port map(secondsCounter, secondsCounter0, secondsCounter1, secondsCounter2);
SecondsMax_Entity: BinaryToBcd port map(seconds_max, seconds_max0, seconds_max1, seconds_max2);
-- I display a 7 segmenti 0 e 1 sono usati per visualizzare l'indirizzo della RAM o dei secondi (in rec o play)
h0_Entity: hex2seg port map(h0_sig, HEX0);
h1_Entity: hex2seg port map(h1_sig, HEX1);
-- Il display a 7 segmenti 2 e' usato per visualizzare il fattore di scala dell'onda sul monitor VGA
h4_Entity: hex2seg port map(h2_sig,HEX2);
-- Il display a 7 segmenti 3 viene usato per visualizzare la velocita di riproduzione
h3_Entity: hex2seg port map(h3_sig,HEX3);
end behaviour;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Design unit : Simple UART (receiver) --
-------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY uartrx IS
PORT(
clk : IN std_logic;
enable : IN std_logic; -- 16 x bit_rate receive clock enable
resetn : IN std_logic;
dbus : OUT std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic;
rdrf : OUT std_logic;
ferror : OUT std_logic;
rx : IN std_logic
);
END uartrx ;
architecture rtl of uartrx is
type states is (s0,s1,s2,s3);
signal state,nextstate : states;
signal rxreg_s : std_logic_vector(7 downto 0); -- Receive Holding Register
signal rxshift_s : std_logic_vector(8 downto 0); -- Receive Shift Register (9 bits!)
signal sample_s : std_logic; -- Sample rx input
signal rsrl_s : std_logic; -- Receive Shift Register Latch (rxpulse_s)
signal synccnt_s : std_logic_vector(3 downto 0); -- 0..15
signal bitcount_s : std_logic_vector(3 downto 0); -- 0..9
type state_type is (st0,st1,st2,st3); -- RDRF flag FSM
signal current_state,next_state : state_type ;
begin
-------------------------------------------------------------------------------
-- Receive Data Register
-------------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn='0') then
rxreg_s <= (others => '1');
elsif (rising_edge(clk)) then
if (enable='1' and rsrl_s='1') then
rxreg_s <= rxshift_s(8 downto 1); -- connect to outside world
end if;
end if;
end process;
dbus <= rxreg_s; -- Connect to outside world
----------------------------------------------------------------------------
-- FSM1, sample input data
----------------------------------------------------------------------------
process (clk,resetn)
begin
if (resetn = '0') then -- Reset State
state <= s0;
elsif rising_edge(clk) then
if enable='1' then
state <= nextstate; -- Set Current state
end if;
end if;
end process;
process(state,rx,sample_s,bitcount_s)
begin
case state is
when s0 =>
if rx='1' then nextstate <= s1;
else nextstate <= s0; -- Wait
end if;
when s1 =>
if rx='0' then nextstate <= s2; -- falling edge
else nextstate <= s1; -- or s0??? Wait
end if;
when s2 => -- Falling edge detected, valid start bit? RXCLK=0,1
if (rx='0' and sample_s='1') then nextstate <= s3; -- so good so far
elsif (rx='1') then nextstate <= s1; -- oops 1 detected, must be noise
else nextstate <= s2; -- wait for sample pulse
end if;
when s3 => -- Start bit detected
if (sample_s='1' and bitcount_s="1000") -- Changed !!! from 1001
then nextstate <= s0;
else nextstate <= s3; -- wait
end if;
when others => nextstate <= s0;
end case;
end process;
-------------------------------------------------------------------------------
-- Sample clock
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn='0') then
synccnt_s <= "1000"; -- sample clock
elsif (rising_edge(clk)) then
if enable='1' then
if (state=s0 or state=s1) then
synccnt_s <= "1000";
else
synccnt_s <= synccnt_s+'1';
end if;
end if;
end if;
end process;
sample_s <= '1' when synccnt_s="0000" else '0';
-------------------------------------------------------------------------------
-- Bit counter
-------------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn='0') then
bitcount_s <= (others => '0');
elsif rising_edge(clk) then
if enable='1' then
if (state=s0 or state=s1) then
bitcount_s <= (others => '1');
elsif (sample_s='1') then
bitcount_s <= bitcount_s + '1';
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Receive Shift Register
----------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn='0') then
rxshift_s <= (others => '1');
elsif rising_edge(clk) then
if enable='1' then
if (sample_s='1') then
rxshift_s <= rx & rxshift_s(8 downto 1);
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- RSRL strobe
----------------------------------------------------------------------------
rsrl_s <= '1' when (sample_s='1' and bitcount_s="1000" and rx='1') else '0';
----------------------------------------------------------------------------
-- Framing Error, low stop bit detected
----------------------------------------------------------------------------
ferror <= '1' when (sample_s='1' and bitcount_s="1000" and rx='0') else '0';
----------------------------------------------------------------------------
-- FSM2, if rsrl='1' then assert rdrf until rd strobe
----------------------------------------------------------------------------
process(clk,resetn)
begin
if (resetn = '0') then
current_state <= st0;
elsif (clk'event and clk = '1') then
current_state <= next_state;
end if;
end process;
process (current_state,rdn,rsrl_s,enable)
begin
case current_state is
when st0 =>
rdrf <= '0';
if (enable='1' and rsrl_s='1') then next_state <= st1;
else next_state <= st0;
end if;
when st1 =>
rdrf<='1';
if (rdn='0') then next_state <= st2;
else next_state <= st1;
end if;
when st2 =>
rdrf <= '1';
if (rdn='1') then next_state <= st0;
else next_state <= st2;
end if;
when others =>
rdrf <= '0';
next_state <= st0;
end case;
end process;
end rtl;
|
-------------------------------------
-- 32 BIT PARALLEL REGISTER --
-- PORT MAPPING --
-- D : 32 bit input data --
-- EN : 1 bit input enable --
-- CLK: 1 bit input clock --
-------------------------------------
-- Q:32g bit output data --
-------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY parallel_register IS
GENERIC
(
g_data_width : POSITIVE := 32
);
PORT
(
in_d : IN STD_LOGIC_VECTOR(g_data_width - 1 DOWNTO 0);
in_en : IN STD_LOGIC;
in_clk : IN STD_LOGIC;
------------------------------------------
out_q : OUT STD_LOGIC_VECTOR(g_data_width - 1 DOWNTO 0)
);
END parallel_register;
ARCHITECTURE behavioral OF parallel_register IS
-- Register memory signal
SIGNAL s_memory : STD_LOGIC_VECTOR(g_data_width - 1 DOWNTO 0);
BEGIN
-- Wire output data to register memory
out_q <= s_memory;
PROCESS(in_en, in_clk)
BEGIN
-- Write to memory in rising edge if register is enabled
IF(in_en = '1' AND (in_clk'EVENT AND in_clk = '1')) THEN
s_memory <= in_d;
END IF;
END PROCESS;
END behavioral; |
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`protect end_protected
|
----------------------------------------------------
-------CODE FOR INRAM(COMMENTED TO WORK AS A ROM)-----
----------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------
entity INPUT_MEM is
port (CLK ,reset : in std_logic;
--CLR : in std_logic;
--WE : in std_logic;
--EN : in std_logic;
--INPUT_DI : in std_logic_vector(1 downto 0);
INPUT_DO : out std_logic_vector(1 downto 0));
end INPUT_MEM;
----------------------------------------------------
architecture inp_memarch of INPUT_MEM is
type INRAM_type is array (0 TO 15) of std_logic_vector (1 downto 0);
signal INADDR: std_logic_vector (3 downto 0);
signal INRAM: INRAM_type:= ("11",
"10",
"11",
"11",
"01",
"01",
"11",
"11",
"10",
"11",
"11",
"01",
"01",
"11",
"00",
"00");
----------------------------------------------------
component MOD16UP is
port(CLK:in std_logic;
reset :in std_logic;
Q_UP : out std_logic_vector(3 downto 0));
end component;
----------------------------------------------------
begin
counter: MOD16UP port map (CLK,reset,INADDR);----GIVE CLR IN SENSITIVITY LIST IF IT IS USED IN THE CIRCUIT
process (CLK,reset)
begin
if (reset='1') then
INPUT_DO <= "00" ;
elsif CLK'event and CLK = '1' then
--if EN = '1' then
--- if WE = '1' then
-- INRAM(conv_integer(INADDR)) <= INPUT_DI;----(uncomment id used as INRAM)
--end if;
INPUT_DO <= INRAM(conv_integer(INADDR+1)) ;
--- end if;
--end if;
end if;
end process;
end inp_memarch;
----------------------------------------------------
----------------------------------------------------
---------------------------------------------------- |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth
B_BURST_SIZE : positive := 4;
A_BURST_SIZE : positive := 4;
SYNC_LOGIC_INTERFACE : boolean := false;
AUTO_INC : boolean := false
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
wrB, rdA : in std_logic ; --! logic side fifo control signal
inputB: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
outputA : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
emptyA, fullA, emptyB, fullB, burst_available_B, burst_available_A : out std_logic; --! fifo state signals
fifoA_reset, fifoB_reset : out std_logic
);
end wishbone_fifo;
architecture RTL of wishbone_fifo is
constant address_space_nbit : integer := MAX((nbit(B_BURST_SIZE)+1), 3);
signal fifoA_wr, fifoB_rd, srazA, srazB : std_logic ;
signal fifoA_in, fifoB_out : std_logic_vector((WIDTH - 1) downto 0 );
signal nb_availableA, nb_availableB : unsigned((WIDTH - 1) downto 0 );
signal nb_availableA_latched, nb_availableB_latched : std_logic_vector((WIDTH - 1) downto 0 );
signal data_bus_out_t : std_logic_vector((WIDTH - 1) downto 0);
signal access_addr, access_addr_old : std_logic ;
signal addr_inc : std_logic ;
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
begin
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
fifo_A : dp_fifo -- write from bus, read from logic
generic map(N => SIZE , W => WIDTH, SYNC_RD => SYNC_LOGIC_INTERFACE, SYNC_WR => false)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => srazA ,
wr => fifoA_wr, rd => rdA,
empty => emptyA,
full => fullA ,
data_out => outputA ,
data_in => fifoA_in ,
nb_available => nb_availableA(nbit(SIZE) downto 0)
);
fifo_B : dp_fifo -- read from bus, write from logic
generic map(N => SIZE , W => WIDTH, SYNC_WR => SYNC_LOGIC_INTERFACE, SYNC_RD => AUTO_INC)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => srazB ,
wr => wrB, rd => fifoB_rd,
empty => emptyB,
full => fullB ,
data_out => fifoB_out ,
data_in => inputB ,
nb_available => nb_availableB(nbit(SIZE) downto 0)
);
nb_availableB_latched <= std_logic_vector(nb_availableB) ;
nb_availableA_latched <= std_logic_vector(nb_availableA) ;
nb_availableB((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
nb_availableA((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
control_data <= std_logic_vector(to_unsigned(SIZE, 16)) when wbs_address(1 downto 0)= "00" else
( nb_availableA_latched) when wbs_address(1 downto 0)= "01" else
( nb_availableB_latched) when wbs_address(1 downto 0)= "10" else
fifoB_out when wbs_address((address_space_nbit-1)) = '1' and wbs_address(1 downto 0)= "11" else -- peek !
(others => '0');
fifo_data <= fifoB_out ;
--wbs_readdata <= control_latched when wbs_address((address_space_nbit-1)) = '1' else
-- fifo_data ;
--
--
--fifoB_rd <= addr_inc when wbs_address((address_space_nbit-1)) = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
-- '0' ;
wbs_readdata <= control_latched when wbs_address((address_space_nbit-1)) = '1' else --data_access = '0' else
fifo_data ;
gen_auto_inc : if AUTO_INC = true generate
fifoB_rd <= addr_inc when data_access = '1' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
end generate ;
gen_no_auto_inc : if AUTO_INC = false generate
fifoB_rd <= '1' when wbs_address((address_space_nbit-1)) = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
end generate ;
fifoA_wr <= '1' when wbs_address((address_space_nbit-1)) = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
srazA <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and wbs_address(address_space_nbit-1) = '1' and wbs_address(1 downto 0) = "01" else
'0' ;
srazB <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and wbs_address(address_space_nbit-1) = '1' and wbs_address(1 downto 0) = "10" else
'0' ;
fifoA_reset <= srazA ;
fifoB_reset <= srazB ;
fifoA_in <= wbs_writedata ;
burst_available_B <= '1' when nb_availableB_latched > B_BURST_SIZE else
'0' ;
burst_available_A <= '1' when nb_availableA_latched > A_BURST_SIZE else
'0' ;
-- Following block takes care of generating reads when the wishbone bus generates burst
access_addr <= wbs_address(0) ;
process(gls_reset, gls_clk)
begin
if gls_reset = '1' then
access_addr_old <= '0';
elsif gls_clk'event and gls_clk = '1' then
access_addr_old <= access_addr ;
end if ;
end process ;
addr_inc <= '1' when access_addr /= access_addr_old and read_ack = '1' else
'0' ;
-- Following block takes care of correctly addressing fifo in burst mode.
-- Address can be increase up to the control memory area without losing 2bytes on last read
-- Following block is a RS latch to latch current addressing mode control/data
process(gls_reset, gls_clk)
begin
if gls_reset = '1' then
data_access <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
if( wbs_strobe = '1' and wbs_cycle = '1' and wbs_address((address_space_nbit-1)) = '0') then
data_access <= '1' ;
elsif (wbs_strobe = '0' or wbs_cycle = '0') then
data_access <= '0' ;
end if ;
end if ;
end process ;
end RTL;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <piat.jonathan@gmail.com>
--
-- Create Date: 10:54:36 06/19/2012
-- Design Name:
-- Module Name: fifo_peripheral - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.utils_pack.all ;
--! peripheral with fifo interface to the logic
--! fifo B can be written from logic and read from bus
--! fifo A can be written from bus and read from logic
entity wishbone_fifo is
generic( ADDR_WIDTH: positive := 16; --! width of the address bus
WIDTH : positive := 16; --! width of the data bus
SIZE : positive := 128; --! fifo depth
B_BURST_SIZE : positive := 4;
A_BURST_SIZE : positive := 4;
SYNC_LOGIC_INTERFACE : boolean := false;
AUTO_INC : boolean := false
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(ADDR_WIDTH-1 downto 0) ;
wbs_writedata : in std_logic_vector( WIDTH-1 downto 0);
wbs_readdata : out std_logic_vector( WIDTH-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- logic signals
wrB, rdA : in std_logic ; --! logic side fifo control signal
inputB: in std_logic_vector((WIDTH - 1) downto 0); --! data input of fifo B
outputA : out std_logic_vector((WIDTH - 1) downto 0); --! data output of fifo A
emptyA, fullA, emptyB, fullB, burst_available_B, burst_available_A : out std_logic; --! fifo state signals
fifoA_reset, fifoB_reset : out std_logic
);
end wishbone_fifo;
architecture RTL of wishbone_fifo is
constant address_space_nbit : integer := MAX((nbit(B_BURST_SIZE)+1), 3);
signal fifoA_wr, fifoB_rd, srazA, srazB : std_logic ;
signal fifoA_in, fifoB_out : std_logic_vector((WIDTH - 1) downto 0 );
signal nb_availableA, nb_availableB : unsigned((WIDTH - 1) downto 0 );
signal nb_availableA_latched, nb_availableB_latched : std_logic_vector((WIDTH - 1) downto 0 );
signal data_bus_out_t : std_logic_vector((WIDTH - 1) downto 0);
signal access_addr, access_addr_old : std_logic ;
signal addr_inc : std_logic ;
signal write_ack, read_ack : std_logic ;
signal gls_resetn : std_logic ;
signal control_latched : std_logic_vector(15 downto 0) ;
signal control_data : std_logic_vector(15 downto 0) ;
signal fifo_data : std_logic_vector(15 downto 0) ;
signal data_access : std_logic ;
begin
gls_resetn <= NOT gls_reset ;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
control_latched <= control_data ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
wbs_ack <= read_ack or write_ack;
fifo_A : dp_fifo -- write from bus, read from logic
generic map(N => SIZE , W => WIDTH, SYNC_RD => SYNC_LOGIC_INTERFACE, SYNC_WR => false)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => srazA ,
wr => fifoA_wr, rd => rdA,
empty => emptyA,
full => fullA ,
data_out => outputA ,
data_in => fifoA_in ,
nb_available => nb_availableA(nbit(SIZE) downto 0)
);
fifo_B : dp_fifo -- read from bus, write from logic
generic map(N => SIZE , W => WIDTH, SYNC_WR => SYNC_LOGIC_INTERFACE, SYNC_RD => AUTO_INC)
port map(
clk => gls_clk, resetn => gls_resetn , sraz => srazB ,
wr => wrB, rd => fifoB_rd,
empty => emptyB,
full => fullB ,
data_out => fifoB_out ,
data_in => inputB ,
nb_available => nb_availableB(nbit(SIZE) downto 0)
);
nb_availableB_latched <= std_logic_vector(nb_availableB) ;
nb_availableA_latched <= std_logic_vector(nb_availableA) ;
nb_availableB((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
nb_availableA((WIDTH - 1) downto (nbit(SIZE) + 1)) <= (others => '0') ;
control_data <= std_logic_vector(to_unsigned(SIZE, 16)) when wbs_address(1 downto 0)= "00" else
( nb_availableA_latched) when wbs_address(1 downto 0)= "01" else
( nb_availableB_latched) when wbs_address(1 downto 0)= "10" else
fifoB_out when wbs_address((address_space_nbit-1)) = '1' and wbs_address(1 downto 0)= "11" else -- peek !
(others => '0');
fifo_data <= fifoB_out ;
--wbs_readdata <= control_latched when wbs_address((address_space_nbit-1)) = '1' else
-- fifo_data ;
--
--
--fifoB_rd <= addr_inc when wbs_address((address_space_nbit-1)) = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
-- '0' ;
wbs_readdata <= control_latched when wbs_address((address_space_nbit-1)) = '1' else --data_access = '0' else
fifo_data ;
gen_auto_inc : if AUTO_INC = true generate
fifoB_rd <= addr_inc when data_access = '1' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
end generate ;
gen_no_auto_inc : if AUTO_INC = false generate
fifoB_rd <= '1' when wbs_address((address_space_nbit-1)) = '0' and wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' else
'0' ;
end generate ;
fifoA_wr <= '1' when wbs_address((address_space_nbit-1)) = '0' and (wbs_strobe and wbs_write and wbs_cycle)= '1' else
'0' ;
srazA <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and wbs_address(address_space_nbit-1) = '1' and wbs_address(1 downto 0) = "01" else
'0' ;
srazB <= '1' when wbs_strobe = '1' and wbs_write = '1' and wbs_cycle = '1' and wbs_address(address_space_nbit-1) = '1' and wbs_address(1 downto 0) = "10" else
'0' ;
fifoA_reset <= srazA ;
fifoB_reset <= srazB ;
fifoA_in <= wbs_writedata ;
burst_available_B <= '1' when nb_availableB_latched > B_BURST_SIZE else
'0' ;
burst_available_A <= '1' when nb_availableA_latched > A_BURST_SIZE else
'0' ;
-- Following block takes care of generating reads when the wishbone bus generates burst
access_addr <= wbs_address(0) ;
process(gls_reset, gls_clk)
begin
if gls_reset = '1' then
access_addr_old <= '0';
elsif gls_clk'event and gls_clk = '1' then
access_addr_old <= access_addr ;
end if ;
end process ;
addr_inc <= '1' when access_addr /= access_addr_old and read_ack = '1' else
'0' ;
-- Following block takes care of correctly addressing fifo in burst mode.
-- Address can be increase up to the control memory area without losing 2bytes on last read
-- Following block is a RS latch to latch current addressing mode control/data
process(gls_reset, gls_clk)
begin
if gls_reset = '1' then
data_access <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
if( wbs_strobe = '1' and wbs_cycle = '1' and wbs_address((address_space_nbit-1)) = '0') then
data_access <= '1' ;
elsif (wbs_strobe = '0' or wbs_cycle = '0') then
data_access <= '0' ;
end if ;
end if ;
end process ;
end RTL;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: RegMultiplexer
-- Date:2011-11-14
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity RegMultiplexer is
generic (
ADDR_WIDTH : integer := 15
);
port (
strobe_read : in std_logic;
strobe_write : in std_logic;
data_in : in std_logic_vector (15 downto 0);
data_out : out std_logic_vector (15 downto 0);
--------------------------------------------------------
reg_addr : in std_logic_vector((ADDR_WIDTH-1) downto 0);
--------------------------------------------------------
reg_strobe_0 : out std_logic;
reg_in_0 : out std_logic_vector (15 downto 0);
reg_out_0 : in std_logic_vector (15 downto 0);
reg_strobe_1 : out std_logic;
reg_in_1 : out std_logic_vector (15 downto 0);
reg_out_1 : in std_logic_vector (15 downto 0);
reg_strobe_2 : out std_logic;
reg_in_2 : out std_logic_vector (15 downto 0);
reg_out_2 : in std_logic_vector (15 downto 0);
reg_strobe_3 : out std_logic;
reg_in_3 : out std_logic_vector (15 downto 0);
reg_out_3 : in std_logic_vector (15 downto 0);
reg_strobe_4 : out std_logic;
reg_in_4 : out std_logic_vector (15 downto 0);
reg_out_4 : in std_logic_vector (15 downto 0);
reg_strobe_5 : out std_logic;
reg_in_5 : out std_logic_vector (15 downto 0);
reg_out_5 : in std_logic_vector (15 downto 0);
reg_strobe_6 : out std_logic;
reg_in_6 : out std_logic_vector (15 downto 0);
reg_out_6 : in std_logic_vector (15 downto 0);
reg_strobe_7 : out std_logic;
reg_in_7 : out std_logic_vector (15 downto 0);
reg_out_7 : in std_logic_vector (15 downto 0);
reg_strobe_8 : out std_logic;
reg_in_8 : out std_logic_vector (15 downto 0);
reg_out_8 : in std_logic_vector (15 downto 0);
reg_strobe_9 : out std_logic;
reg_in_9 : out std_logic_vector (15 downto 0);
reg_out_9 : in std_logic_vector (15 downto 0);
reg_strobe_10 : out std_logic;
reg_in_10 : out std_logic_vector (15 downto 0);
reg_out_10 : in std_logic_vector (15 downto 0);
reg_strobe_11 : out std_logic;
reg_in_11 : out std_logic_vector (15 downto 0);
reg_out_11 : in std_logic_vector (15 downto 0);
reg_strobe_other0 : out std_logic;
reg_in_other0 : out std_logic_vector (15 downto 0);
reg_out_other0 : in std_logic_vector (15 downto 0);
reg_strobe_other1 : out std_logic;
reg_in_other1 : out std_logic_vector (15 downto 0);
reg_out_other1 : in std_logic_vector (15 downto 0)
);
end RegMultiplexer;
architecture arch of RegMultiplexer is
constant REG_COUNT : integer := 14;
constant MAX_ADDR : integer := (2**ADDR_WIDTH - 1);
type SIGNAL_VECTOR is array ((REG_COUNT-1) downto 0) of std_logic;
type BUS_VECTOR is array ((REG_COUNT-1) downto 0) of
std_logic_vector (15 downto 0);
signal cur_reg_num : integer range 0 to 13;
signal dec_addr : integer range MAX_ADDR downto 0;
signal inputs : BUS_VECTOR;
signal outputs : BUS_VECTOR;
signal strobes : SIGNAL_VECTOR;
begin
(reg_strobe_other1, reg_strobe_other0, reg_strobe_11, reg_strobe_10,
reg_strobe_9, reg_strobe_8, reg_strobe_7, reg_strobe_6, reg_strobe_5,
reg_strobe_4, reg_strobe_3, reg_strobe_2, reg_strobe_1,
reg_strobe_0) <= strobes;
(reg_in_other1, reg_in_other0, reg_in_11, reg_in_10, reg_in_9, reg_in_8,
reg_in_7, reg_in_6, reg_in_5, reg_in_4, reg_in_3, reg_in_2, reg_in_1,
reg_in_0) <= inputs;
outputs <= (reg_out_other1, reg_out_other0, reg_out_11, reg_out_10,
reg_out_9, reg_out_8, reg_out_7, reg_out_6, reg_out_5, reg_out_4,
reg_out_3, reg_out_2, reg_out_1, reg_out_0);
dec_addr <= conv_integer(reg_addr);
process (dec_addr) begin
if dec_addr >= 0 and dec_addr < (REG_COUNT-2) then
cur_reg_num <= dec_addr;
elsif dec_addr = (REG_COUNT-2) then
cur_reg_num <= 12;
else
cur_reg_num <= 13;
end if;
end process;
process (strobe_read, strobe_write, data_in, outputs, cur_reg_num) begin
strobes <= (others => '0');
inputs <= (others => (others => '0'));
data_out <= (others => '0');
if cur_reg_num < REG_COUNT then
if cur_reg_num = 12 then
strobes(cur_reg_num) <= strobe_read;
else
strobes(cur_reg_num) <= strobe_write;
end if;
inputs(cur_reg_num) <= data_in;
data_out <= outputs(cur_reg_num);
end if;
end process;
end arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ULA is
Port (A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (1 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end ULA;
architecture Behavioral of ULA is
signal and_link : STD_LOGIC_VECTOR (7 downto 0);
signal or_link : STD_LOGIC_VECTOR (7 downto 0);
signal add_link : STD_LOGIC_VECTOR (7 downto 0);
signal sub_link : STD_LOGIC_VECTOR (7 downto 0);
begin
AND_P : entity work.AND_PROCESS
port map (A, B, and_link);
OR_P : entity work.OR_PROCESS
port map (A, B, or_link);
ADDER_P : entity work.ADDER_PROCESS
port map (A, B, add_link);
SUBTRACTER_P : entity work.SUBTRACTER_PROCESS
port map (A, B, sub_link);
MUX_P : entity work.MUX_PROCESS
port map (and_link, or_link, add_link, sub_link, S, O);
end Behavioral;
|
-- $Id: sys_tst_rlink_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_b3 - syn
-- Description: rlink tester design for basys3
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- bplib/bpgen/sn_humanio_rbus
-- vlib/rlink/rlink_sp1c
-- rbd_tst_rlink
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_4
--
-- Test bench: tb/tb_tst_rlink_b3
--
-- Target Devices: generic
-- Tool versions: viv 2014.4-2022.1; ghdl 0.31-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1 1039 1492 34 3.0 527
-- 2019-02-02 1108 2018.3 xc7a35t-1 1040 1594 36 3.0 546
-- 2019-02-02 1108 2017.2 xc7a35t-1 1040 1682 36 3.0 587
-- 2016-03-27 753 2015.4 xc7a35t-1 986 1352 36 3.0 473 meminf
-- 2016-03-13 743 2015.4 xc7a35t-1 988 1372 64 4.5 503 +XADC
-- 2015-01-30 636 2014.4 xc7a35t-1 946 1319 64 4.5 476
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-04-02 758 1.1.3 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-19 748 1.1.2 define rlink SYSID
-- 2016-03-18 745 1.1.1 hardwire XON=1
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2016-02-26 735 1.0.2 use s7_cmt_sfs
-- 2015-04-11 666 1.0.1 rearrange XON handling
-- 2015-01-16 636 1.0 Initial version (derived from sys_tst_rlink_n3)
------------------------------------------------------------------------------
-- Usage of Basys 3 Switches, Buttons, LEDs:
--
-- SWI(7:2): no function (only connected to sn_humanio_rbus)
-- SWI(1): -unused-
-- SWI(0): -unused-
--
-- LED(7): SER_MONI.abact
-- LED(6:2): no function (only connected to sn_humanio_rbus)
-- LED(1): timer 1 busy
-- LED(0): timer 0 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- DP(3): not SER_MONI.txok (shows tx back pressure)
-- DP(2): SER_MONI.txact (shows tx activity)
-- DP(1): not SER_MONI.rxok (shows rx back pressure)
-- DP(0): SER_MONI.rxact (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.bpgenrbuslib.all;
use work.sysmonrbuslib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_b3 is -- top level
-- implements basys3_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv16; -- b3 switches
I_BTN : in slv5; -- b3 buttons
O_LED : out slv16; -- b3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end sys_tst_rlink_b3;
architecture syn of sys_tst_rlink_b3 is
signal CLK : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal STAT : slv8 := (others=>'0');
constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0101"; -- tst_rlink
constant sysid_board : slv8 := x"06"; -- basys3
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
RESET <= '0'; -- so far not used
GEN_CLKSYS : s7_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLK,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
HIO : sn_humanio_rbus
generic map (
SWIDTH => 16,
BWIDTH => 5,
LWIDTH => 16,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RLINK : rlink_sp1c
generic map (
BTOWIDTH => 6,
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5,
OFAWIDTH => 5,
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
RBMON_RBADDR => (others=>'0'))
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
RBDTST : entity work.rbd_tst_rlink
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RB_SRES_TOP => RB_SRES,
RXSD => RXD,
RXACT => SER_MONI.rxact,
STAT => STAT
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR1 : rb_sres_or_4
port map (
RB_SRES_1 => RB_SRES_HIO,
RB_SRES_2 => RB_SRES_TST,
RB_SRES_3 => RB_SRES_SYSMON,
RB_SRES_4 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
DSP_DAT <= SER_MONI.abclkdiv;
DSP_DP(3) <= not SER_MONI.txok;
DSP_DP(2) <= SER_MONI.txact;
DSP_DP(1) <= not SER_MONI.rxok;
DSP_DP(0) <= SER_MONI.rxact;
LED(15 downto 8) <= SWI(15 downto 8);
LED(7) <= SER_MONI.abact;
LED(6 downto 2) <= (others=>'0');
LED(1) <= STAT(1);
LED(0) <= STAT(0);
end syn;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:33:18 11/21/2013
-- Design Name:
-- Module Name: RiskChecker - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RiskChecker is
Port(
PCWrite : out STD_LOGIC;
IFIDWrite : out STD_LOGIC;
ControlRst : out STD_LOGIC;
IDEX_MemWrite : in STD_LOGIC;
IDEX_W : in Int4;
IFID_R1 : in Int4;
IFID_R2 : in Int4;
op : in Int5;
forwardBEQZ: out std_logic_vector(1 downto 0);
EXMEM_W : in Int4
);
end RiskChecker;
architecture Behavioral of RiskChecker is
begin
-- TODO
PCWrite <= '1';
IFIDWrite <= '1';
ControlRst <= '1';
process(op, IDEX_W, IFID_R1)
begin
forwardBEQZ <= "00";
if ((op = "11010" or op = "11011") and IDEX_W /= Zero_reg and IDEX_W = IFID_R1) then
forwardBEQZ <= "01";
elsif ((op = "11010" or op = "11011") and EXMEM_W /= Zero_reg and EXMEM_W = IFID_R1) then
forwardBEQZ <= "10";
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for padframe
--
-- Generated
-- by: wig
-- on: Thu Jul 6 16:43:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: padframe-e.vhd,v 1.3 2006/07/10 07:30:09 wig Exp $
-- $Date: 2006/07/10 07:30:09 $
-- $Log: padframe-e.vhd,v $
-- Revision 1.3 2006/07/10 07:30:09 wig
-- Updated more testcasess.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity padframe
--
entity padframe is
-- Generics:
-- No Generated Generics for Entity padframe
-- Generated Port Declaration:
port(
-- Generated Port for Entity padframe
mix_logic0_0 : in std_ulogic; -- padin
mix_logic0_bus_4 : in std_ulogic_vector(31 downto 0); -- padin
ramd_i : in std_ulogic_vector(31 downto 0); -- padin
ramd_i2 : in std_ulogic_vector(31 downto 0); -- padin
ramd_o : out std_ulogic_vector(31 downto 0); -- padout
ramd_o2 : out std_ulogic_vector(31 downto 0); -- padout
ramd_o3 : out std_ulogic_vector(31 downto 0)
-- End of Generated Port for Entity padframe
);
end padframe;
--
-- End of Generated Entity padframe
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_1_0 IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_1_0;
ARCHITECTURE system_ov7670_vga_1_0_arch OF system_ov7670_vga_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
BEGIN
U0 : ov7670_vga
PORT MAP (
pclk => pclk,
data => data,
rgb => rgb
);
END system_ov7670_vga_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_1_0 IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_1_0;
ARCHITECTURE system_ov7670_vga_1_0_arch OF system_ov7670_vga_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
BEGIN
U0 : ov7670_vga
PORT MAP (
pclk => pclk,
data => data,
rgb => rgb
);
END system_ov7670_vga_1_0_arch;
|
-------------------------------------------------------------------------------
-- File : bmp_pkg.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Low level access to bitmap files
--
-- Target: Simulator
-- Dependencies: none
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package bmp_pkg is
constant BMP_MAX_WIDTH : integer := 700;
constant BMP_MAX_HEIGHT : integer := 640;
subtype bmp_slv8_t is std_logic_vector(7 downto 0);
subtype bmp_slv16_t is std_logic_vector(15 downto 0);
subtype bmp_slv32_t is std_logic_vector(31 downto 0);
type bmp_meta is
record
width : integer;
height : integer;
end record;
type bmp_pix is
record
r: bmp_slv8_t;
g: bmp_slv8_t;
b: bmp_slv8_t;
end record;
type bmp_line is array (0 to BMP_MAX_WIDTH-1) of bmp_pix;
type bmp_data is array (0 to BMP_MAX_HEIGHT-1) of bmp_line;
type bmp is
record
meta : bmp_meta;
data: bmp_data;
end record;
type bmp_ptr is access bmp;
----------------------------------------------------------------------------
-- Public procedures and functions
----------------------------------------------------------------------------
procedure bmp_open ( ptr : inout bmp_ptr; filename : in string );
procedure bmp_save ( ptr : inout bmp_ptr; filename : in string );
procedure bmp_get_width ( ptr : inout bmp_ptr; width : out integer);
procedure bmp_get_height ( ptr : inout bmp_ptr; height : out integer);
procedure bmp_get_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : out bmp_pix );
procedure bmp_set_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : in bmp_pix );
end package bmp_pkg;
package body bmp_pkg is
----------------------------------------------------------------------------
-- Types
----------------------------------------------------------------------------
type bmp_file is file of character;
type bmp_header_array is array (0 to 53) of bmp_slv8_t;
----------------------------------------------------------------------------
-- Constants
----------------------------------------------------------------------------
constant BMP_STD_HEADER_ARRAY : bmp_header_array := (
"01000010", "01001101", "00110110", "00000000", "00001100", "00000000",
"00000000", "00000000", "00000000", "00000000", "00110110", "00000000",
"00000000", "00000000", "00101000", "00000000", "00000000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000", "00000000",
"00000000", "00000000", "00000001", "00000000", "00011000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000", "00000000",
"00000000", "00000000", "11000100", "00001110", "00000000", "00000000",
"11000100", "00001110", "00000000", "00000000", "00000000", "00000000",
"00000000", "00000000", "00000000", "00000000", "00000000", "00000000"
);
----------------------------------------------------------------------------
-- Procedures
----------------------------------------------------------------------------
procedure bmp_open ( ptr : inout bmp_ptr; filename : in string ) is
file fp : bmp_file open read_mode is filename;
variable header_array : bmp_header_array;
variable byte : character;
variable val : integer;
variable tmp_slv32 : bmp_slv32_t; -- Temporary variable
variable file_pos : integer := 0;
variable data_offset : integer;
begin
-- Read bitmap header into array
for i in 0 to 53 loop
read( fp, byte );
val := character'pos( byte );
header_array(i) := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
file_pos := file_pos + 1;
end loop;
-- TODO: Validate bitmap
-- Extract image width from array
tmp_slv32 := header_array(21) & header_array(20) & header_array(19) & header_array(18);
ptr.meta.width := to_integer(signed(tmp_slv32));
-- Extract image height from array
tmp_slv32 := header_array(25) & header_array(24) & header_array(23) & header_array(22);
ptr.meta.height := to_integer(signed(tmp_slv32));
-- Extract offset of image data from array
tmp_slv32 := header_array(13) & header_array(12) & header_array(11) & header_array(10);
data_offset := to_integer(signed(tmp_slv32)); -- HACK: actually the data offset is not signed
assert ptr.meta.width <= BMP_MAX_WIDTH report "Image height too big. Increase BMP_MAX_WIDTH!" severity error;
assert ptr.meta.height <= BMP_MAX_HEIGHT report "Image width too big. Increase BMP_MAX_HEIGHT!" severity error;
-- Fast forward to image data
while file_pos < data_offset loop
read( fp, byte );
file_pos := file_pos + 1;
end loop;
-- Extract image data
line : for y in ptr.meta.height-1 downto 0 loop
pix : for x in 0 to ptr.meta.width -1 loop
-- Blue pixel
read( fp, byte );
val := character'pos( byte );
ptr.data(y)(x).b := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
-- Green pixel
read( fp, byte );
val := character'pos( byte );
ptr.data(y)(x).g := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
-- Red pixel
read( fp, byte );
val := character'pos( byte );
ptr.data(y)(x).r := bmp_slv8_t(to_unsigned(val, bmp_slv8_t'length));
end loop;
end loop;
end bmp_open;
procedure bmp_save ( ptr : inout bmp_ptr; filename : in string ) is
file fp : bmp_file open write_mode is filename;
variable header_array : bmp_header_array := BMP_STD_HEADER_ARRAY;
variable byte : character;
variable val : integer;
variable tmp_slv32 : bmp_slv32_t; -- Temporary variable
begin
--Inject image width into bitmap header
tmp_slv32 := bmp_slv32_t(to_signed(ptr.meta.width, bmp_slv32_t'length));
header_array(21) := tmp_slv32(31 downto 24);
header_array(20) := tmp_slv32(23 downto 16);
header_array(19) := tmp_slv32(15 downto 8);
header_array(18) := tmp_slv32(7 downto 0);
--Inject image height into bitmap header
tmp_slv32 := bmp_slv32_t(to_signed(ptr.meta.height, bmp_slv32_t'length));
header_array(25) := tmp_slv32(31 downto 24);
header_array(24) := tmp_slv32(23 downto 16);
header_array(23) := tmp_slv32(15 downto 8);
header_array(22) := tmp_slv32(7 downto 0);
-- Write array into bitmap header
for i in 0 to 53 loop
val := to_integer(unsigned(header_array(i)));
byte := character'val(val);
write( fp, byte );
end loop;
-- Write image data
line : for y in ptr.meta.height-1 downto 0 loop
pix : for x in 0 to ptr.meta.width -1 loop
-- Blue pixel
val := to_integer(unsigned(ptr.data(y)(x).b));
byte := character'val(val);
write( fp, byte );
-- Green pixel
val := to_integer(unsigned(ptr.data(y)(x).g));
byte := character'val(val);
write( fp, byte );
-- Red pixel
val := to_integer(unsigned(ptr.data(y)(x).r));
byte := character'val(val);
write( fp, byte );
end loop;
end loop;
end bmp_save;
procedure bmp_get_width ( ptr : inout bmp_ptr; width : out integer) is
begin
width := ptr.meta.width;
end bmp_get_width;
procedure bmp_get_height ( ptr : inout bmp_ptr; height : out integer) is
begin
height := ptr.meta.height;
end bmp_get_height;
procedure bmp_get_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : out bmp_pix ) is
begin
pix := ptr.data(y)(x);
end bmp_get_pix;
procedure bmp_set_pix ( ptr : inout bmp_ptr; x: in natural; y : in natural; pix : in bmp_pix ) is
begin
ptr.data(y)(x) := pix;
-- Increase image size if nessecary
if x+1 > ptr.meta.width then
ptr.meta.width := x+1;
end if;
if y+1 > ptr.meta.height then
ptr.meta.height := y+1;
end if;
end bmp_set_pix;
end bmp_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity k7_prime_fifo_plain_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end k7_prime_fifo_plain_exdes;
architecture xilinx of k7_prime_fifo_plain_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component k7_prime_fifo_plain is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : k7_prime_fifo_plain
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
--library ieee;
--use ieee.std_logic_1164.all;
package dosomething is
type dosomething_t is record
dummy1 : integer;
dummy2 : integer;
dummy3 : integer;
end record;
procedure dosomething_hello (
variable r : inout dosomething_t);
end dosomething;
|
--library ieee;
--use ieee.std_logic_1164.all;
package dosomething is
type dosomething_t is record
dummy1 : integer;
dummy2 : integer;
dummy3 : integer;
end record;
procedure dosomething_hello (
variable r : inout dosomething_t);
end dosomething;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:57 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_util_vector_logic_0_0 -prefix
-- system_util_vector_logic_0_0_ system_util_vector_logic_0_0_stub.vhdl
-- Design : system_util_vector_logic_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_util_vector_logic_0_0 is
Port (
Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Res : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_util_vector_logic_0_0;
architecture stub of system_util_vector_logic_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Op1[0:0],Op2[0:0],Res[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "util_vector_logic,Vivado 2016.4";
begin
end;
|
---------------------------------------------------------------------------------
--Receiver------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--CLASS DESCRIPTION------------------------------------------------------------
--2--Detect a start of Frame whose pattern is 10101011----------------------------
--3--After frame detect take every 8 bits and store them in a ram----------------
----------------Define Libraries to be used--------------------------------------
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
USE IEEE.std_logic_unsigned.all;
-----------------ENTITY FOR RECEIVER------------------------------------------
ENTITY receiver is
GENERIC ( bits : INTEGER := 8); -- # of bits per word
PORT ( reset : IN STD_Logic;
clock : IN STD_LOGIC;
rec_in : IN STD_LOGIC;
enable : OUT STD_LOGIC;
rec_out : OUT STD_LOGIC_VECTOR (bits -1 DOWNTO 0)
);
END receiver;
-----------------BEHAVIOR OF RECEIVER-----------------------------------------
ARCHITECTURE receiver of receiver IS
-------------------VARIABLE DECLARATION----------------------------------------
SIGNAL bit_counter : INTEGER;
SIGNAL S_enable : STD_LOGIC;
SIGNAL shiftreg : STD_LOGIC_VECTOR((bits-1) downto 0);
-------------------PROCEDURE------------------------------
BEGIN
enable <= S_enable;
SHIFTIN: PROCESS(clock, reset)
BEGIN
IF(reset = '0')THEN
shiftreg <= (others => '0');
ELSIF rising_edge(CLOCK)THEN
shiftreg <= shiftreg((bits-2) downto 0) & rec_in;
END IF;
END PROCESS shiftin;
Output: PROCESS(clock, reset)
BEGIN
IF (reset = '0') THEN
rec_out <= (others => '0');
ELSIF rising_edge (clock)THEN
------COMPRESS LOOK AT THIS SECTION!!!
IF(bit_counter = (bits-1) AND S_enable='1')THEN
rec_out <= shiftreg;
END IF;
END IF;
END PROCESS Output;
CheckAndEnable:PROCESS(clock, reset)
BEGIN
IF (reset = '0')THEN
S_enable <= '0';
ELSIF rising_edge (clock)THEN
IF (shiftreg = "10101011")THEN
S_enable <= '1';
END IF;
END IF;
END PROCESS CheckAndEnable;
COUNT_BITS:PROCESS(clock, reset)
BEGIN
IF (reset = '0')THEN
bit_counter <= 0;
ELSIF rising_edge (clock)THEN
IF (bit_counter = bits - 1)THEN
bit_counter <= 0;
ELSE
bit_counter <= bit_counter + 1;
END IF;
END IF;
END PROCESS COUNT_BITS;
END receiver; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2727.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p07n01i02727ent IS
END c13s04b02x00p07n01i02727ent;
ARCHITECTURE c13s04b02x00p07n01i02727arch OF c13s04b02x00p07n01i02727ent IS
BEGIN
TESTING: PROCESS
variable total_time : real;
BEGIN
total_time := 6#6589.55#; --Failure_here
assert FALSE
report "***FAILED TEST: c13s04b02x00p07n01i02727 - The value of each digit in a based literal must be less than that of the base."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p07n01i02727arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2727.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p07n01i02727ent IS
END c13s04b02x00p07n01i02727ent;
ARCHITECTURE c13s04b02x00p07n01i02727arch OF c13s04b02x00p07n01i02727ent IS
BEGIN
TESTING: PROCESS
variable total_time : real;
BEGIN
total_time := 6#6589.55#; --Failure_here
assert FALSE
report "***FAILED TEST: c13s04b02x00p07n01i02727 - The value of each digit in a based literal must be less than that of the base."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p07n01i02727arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2727.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p07n01i02727ent IS
END c13s04b02x00p07n01i02727ent;
ARCHITECTURE c13s04b02x00p07n01i02727arch OF c13s04b02x00p07n01i02727ent IS
BEGIN
TESTING: PROCESS
variable total_time : real;
BEGIN
total_time := 6#6589.55#; --Failure_here
assert FALSE
report "***FAILED TEST: c13s04b02x00p07n01i02727 - The value of each digit in a based literal must be less than that of the base."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p07n01i02727arch;
|
----------------------------------------------------------------------------------
-- Create Date: 21:40:57 04/10/2017
-- Module Name: OR_BitABit - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OR_BitABit is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0)); -- Saida
end OR_BitABit;
architecture Behavioral of OR_BitABit is
signal Zout : STD_LOGIC_VECTOR(3 downto 0);
begin
Zout(0) <= A(0) OR B(0);
Zout(1) <= A(1) OR B(1);
Zout(2) <= A(2) OR B(2);
Zout(3) <= A(3) OR B(3);
Z <= Zout;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity FsmRead is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOR : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end FsmRead;
architecture simple of FsmRead is
signal Qp, Qn : std_logic_vector(3 downto 0);
begin
combinacional: process(Qp,STR,FBaud)
begin
case Qp is
when "0000" => -- State 0
if (STR='1') then
Qn <= Qp;
else
Qn <= "0001";
end if;
CTRL <= "01";
EOR <= "1";
when "0001" => -- State 1
Qn <= "0010"
CTRL <= "10";
EOR <= "0";
when "0010" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0011"
end if;
CTRL <= "00";
EOR <= "0";
when "0011" => -- State 2
Qn <= "0100"
CTRL <= "10";
EOR <= "0";
when "0100" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0101"
end if;
CTRL <= "00";
EOR <= "0";
when "0101" => -- State 3
Qn <= "0110"
CTRL <= "10";
EOR <= "0";
when "0110" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0111"
end if;
CTRL <= "00";
EOR <= "0";
when "0111" => -- State 4
Qn <= "1000"
CTRL <= "10";
EOR <= "0";
when "1000" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1001"
end if;
CTRL <= "00";
EOR <= "0";
when "1001" => -- State 5
Qn <= "1010"
CTRL <= "10";
EOR <= "0";
when "1010" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1011"
end if;
CTRL <= "00";
EOR <= "0";
when "1011" => -- State 6
Qn <= "1100"
CTRL <= "10";
EOR <= "0";
when "1100" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1101"
end if;
CTRL <= "00";
EOR <= "0";
when "1101" => -- State 7
Qn <= "1110"
CTRL <= "10";
EOR <= "0";
when others =>
CTRL<= "0000";
EOR<= '1';
Qn<= "0000";
end case;
end process combinacional;
secuencial: process(RST,CLK)
begin
if(RST='0')then
Qp<= "0000";
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process secuencial;
end simple;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity FsmRead is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOR : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end FsmRead;
architecture simple of FsmRead is
signal Qp, Qn : std_logic_vector(3 downto 0);
begin
combinacional: process(Qp,STR,FBaud)
begin
case Qp is
when "0000" => -- State 0
if (STR='1') then
Qn <= Qp;
else
Qn <= "0001";
end if;
CTRL <= "01";
EOR <= "1";
when "0001" => -- State 1
Qn <= "0010"
CTRL <= "10";
EOR <= "0";
when "0010" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0011"
end if;
CTRL <= "00";
EOR <= "0";
when "0011" => -- State 2
Qn <= "0100"
CTRL <= "10";
EOR <= "0";
when "0100" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0101"
end if;
CTRL <= "00";
EOR <= "0";
when "0101" => -- State 3
Qn <= "0110"
CTRL <= "10";
EOR <= "0";
when "0110" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0111"
end if;
CTRL <= "00";
EOR <= "0";
when "0111" => -- State 4
Qn <= "1000"
CTRL <= "10";
EOR <= "0";
when "1000" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1001"
end if;
CTRL <= "00";
EOR <= "0";
when "1001" => -- State 5
Qn <= "1010"
CTRL <= "10";
EOR <= "0";
when "1010" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1011"
end if;
CTRL <= "00";
EOR <= "0";
when "1011" => -- State 6
Qn <= "1100"
CTRL <= "10";
EOR <= "0";
when "1100" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1101"
end if;
CTRL <= "00";
EOR <= "0";
when "1101" => -- State 7
Qn <= "1110"
CTRL <= "10";
EOR <= "0";
when others =>
CTRL<= "0000";
EOR<= '1';
Qn<= "0000";
end case;
end process combinacional;
secuencial: process(RST,CLK)
begin
if(RST='0')then
Qp<= "0000";
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process secuencial;
end simple;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:50 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_stub.vhdl
-- Design : system_axi_gpio_led_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_axi_gpio_led_0 is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
end system_axi_gpio_led_0;
architecture stub of system_axi_gpio_led_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0],gpio2_io_i[11:0],gpio2_io_o[11:0],gpio2_io_t[11:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2016.4";
begin
end;
|
divisor_inst : divisor PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
divisor_inst : divisor PORT MAP (
clock => clock_sig,
cout => cout_sig,
q => q_sig
);
|
entity bounds11 is
end entity;
architecture test of bounds11 is
type my_int is range 0 to 100;
signal i : my_int;
begin
p1: i <= i + 1 after 10 ns;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc27.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p10n04i00027ent IS
END c04s02b00x00p10n04i00027ent;
ARCHITECTURE c04s02b00x00p10n04i00027arch OF c04s02b00x00p10n04i00027ent IS
subtype s1 is integer range 1 to 10; -- No_failure_here
subtype s2 is integer range 10 downto 1; -- No_failure_here
-- the following are null ranges
subtype s3 is integer range 1 downto 10; -- No_failure_here
subtype s4 is integer range 10 to 1; -- No_failure_here
BEGIN
TESTING: PROCESS
variable k1 : s1 := 1;
variable k2 : s2 := 10;
variable k : integer := 0;
BEGIN
for i in s1 loop
if (i /= k1) then
k := 1;
end if;
if (k1 < 10) then
k1 := k1 + 1;
end if;
end loop;
for i in s2 loop
if (i /= k2) then
k := 1;
end if;
if (k2 > 1) then
k2 := k2 - 1;
end if;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c04s02b00x00p10n04i00027"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c04s02b00x00p10n04i00027 - The direction of a discrete subtype is the same as the direction of its subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p10n04i00027arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc27.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p10n04i00027ent IS
END c04s02b00x00p10n04i00027ent;
ARCHITECTURE c04s02b00x00p10n04i00027arch OF c04s02b00x00p10n04i00027ent IS
subtype s1 is integer range 1 to 10; -- No_failure_here
subtype s2 is integer range 10 downto 1; -- No_failure_here
-- the following are null ranges
subtype s3 is integer range 1 downto 10; -- No_failure_here
subtype s4 is integer range 10 to 1; -- No_failure_here
BEGIN
TESTING: PROCESS
variable k1 : s1 := 1;
variable k2 : s2 := 10;
variable k : integer := 0;
BEGIN
for i in s1 loop
if (i /= k1) then
k := 1;
end if;
if (k1 < 10) then
k1 := k1 + 1;
end if;
end loop;
for i in s2 loop
if (i /= k2) then
k := 1;
end if;
if (k2 > 1) then
k2 := k2 - 1;
end if;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c04s02b00x00p10n04i00027"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c04s02b00x00p10n04i00027 - The direction of a discrete subtype is the same as the direction of its subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p10n04i00027arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc27.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s02b00x00p10n04i00027ent IS
END c04s02b00x00p10n04i00027ent;
ARCHITECTURE c04s02b00x00p10n04i00027arch OF c04s02b00x00p10n04i00027ent IS
subtype s1 is integer range 1 to 10; -- No_failure_here
subtype s2 is integer range 10 downto 1; -- No_failure_here
-- the following are null ranges
subtype s3 is integer range 1 downto 10; -- No_failure_here
subtype s4 is integer range 10 to 1; -- No_failure_here
BEGIN
TESTING: PROCESS
variable k1 : s1 := 1;
variable k2 : s2 := 10;
variable k : integer := 0;
BEGIN
for i in s1 loop
if (i /= k1) then
k := 1;
end if;
if (k1 < 10) then
k1 := k1 + 1;
end if;
end loop;
for i in s2 loop
if (i /= k2) then
k := 1;
end if;
if (k2 > 1) then
k2 := k2 - 1;
end if;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c04s02b00x00p10n04i00027"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c04s02b00x00p10n04i00027 - The direction of a discrete subtype is the same as the direction of its subtype indication."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s02b00x00p10n04i00027arch;
|
entity call10 is
end;
architecture behav of call10 is
procedure check2 (msg : string) is
begin
assert msg = "checking: abcedfghijklmnopqrstuvwxyz"
severity failure;
report "SUCCESS" severity note;
end check2;
procedure check1 (msg : string) is
begin
check2 ("checking: " & msg);
end check1;
begin
process
begin
check1 ("abcedfghijklmnopqrstuvwxyz");
wait;
end process;
end behav;
|
entity call10 is
end;
architecture behav of call10 is
procedure check2 (msg : string) is
begin
assert msg = "checking: abcedfghijklmnopqrstuvwxyz"
severity failure;
report "SUCCESS" severity note;
end check2;
procedure check1 (msg : string) is
begin
check2 ("checking: " & msg);
end check1;
begin
process
begin
check1 ("abcedfghijklmnopqrstuvwxyz");
wait;
end process;
end behav;
|
-- Dmemory module (implements the data memory for the MIPS computer)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY dmemory IS
PORT( read_data : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
address : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
alu_result : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
MemRead, Memwrite,MemtoReg : IN STD_LOGIC;
clock,reset : IN STD_LOGIC );
END dmemory;
ARCHITECTURE behavior OF dmemory IS
SIGNAL write_clock : STD_LOGIC;
SIGNAL read_data_from_memory : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
BEGIN
data_memory : altsyncram
GENERIC MAP (
operation_mode => "SINGLE_PORT",
width_a => 32,
widthad_a => 8,
lpm_type => "altsyncram",
outdata_reg_a => "UNREGISTERED",
--init_file => "testPipeM.mif",
init_file => "MLCS.mif",
intended_device_family => "Cyclone"
)
PORT MAP (
wren_a => memwrite,
clock0 => write_clock,
address_a => address,
data_a => write_data,
q_a => read_data_from_memory );
-- Load memory address register with write clock
--write_clock <= NOT clock;
write_clock <= clock;
read_data <= alu_result WHEN ( MemtoReg = '0' )
ELSE read_data_from_memory;
END behavior;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_0;
ARCHITECTURE design_1_cic_compiler_0_0_arch OF design_1_cic_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "cic_compiler_v4_0_10,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_cic_compiler_0_0_arch : ARCHITECTURE IS "design_1_cic_compiler_0_0,cic_compiler_v4_0_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "design_1_cic_compiler_0_0,cic_compiler_v4_0_10,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMPONENT_NAME=design_1_cic_compiler_0_0,C_FILTER_TYPE=1,C_NUM_STAGES=4,C_DIFF_DELAY=1,C_RATE=25,C_INPUT_WIDTH=16,C_OUTPUT_WIDTH=35,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=25,C_MAX_RATE=25,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMILY=" &
"zynq,C_XDEVICEFAMILY=zynq,C_C1=35,C_C2=35,C_C3=35,C_C4=35,C_C5=0,C_C6=0,C_I1=35,C_I2=35,C_I3=35,C_I4=35,C_I5=0,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=16,C_M_AXIS_DATA_TDATA_WIDTH=40,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_0",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 25,
C_INPUT_WIDTH => 16,
C_OUTPUT_WIDTH => 35,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 25,
C_MAX_RATE => 25,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 35,
C_C2 => 35,
C_C3 => 35,
C_C4 => 35,
C_C5 => 0,
C_C6 => 0,
C_I1 => 35,
C_I2 => 35,
C_I3 => 35,
C_I4 => 35,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 40,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0_10;
USE cic_compiler_v4_0_10.cic_compiler_v4_0_10;
ENTITY design_1_cic_compiler_0_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END design_1_cic_compiler_0_0;
ARCHITECTURE design_1_cic_compiler_0_0_arch OF design_1_cic_compiler_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0_10 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0_10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "cic_compiler_v4_0_10,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_cic_compiler_0_0_arch : ARCHITECTURE IS "design_1_cic_compiler_0_0,cic_compiler_v4_0_10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_cic_compiler_0_0_arch: ARCHITECTURE IS "design_1_cic_compiler_0_0,cic_compiler_v4_0_10,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMPONENT_NAME=design_1_cic_compiler_0_0,C_FILTER_TYPE=1,C_NUM_STAGES=4,C_DIFF_DELAY=1,C_RATE=25,C_INPUT_WIDTH=16,C_OUTPUT_WIDTH=35,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=25,C_MAX_RATE=25,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMILY=" &
"zynq,C_XDEVICEFAMILY=zynq,C_C1=35,C_C2=35,C_C3=35,C_C4=35,C_C5=0,C_C6=0,C_I1=35,C_I2=35,C_I3=35,C_I4=35,C_I5=0,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=16,C_M_AXIS_DATA_TDATA_WIDTH=40,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0_10
GENERIC MAP (
C_COMPONENT_NAME => "design_1_cic_compiler_0_0",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 4,
C_DIFF_DELAY => 1,
C_RATE => 25,
C_INPUT_WIDTH => 16,
C_OUTPUT_WIDTH => 35,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 25,
C_MAX_RATE => 25,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_C1 => 35,
C_C2 => 35,
C_C3 => 35,
C_C4 => 35,
C_C5 => 0,
C_C6 => 0,
C_I1 => 35,
C_I2 => 35,
C_I3 => 35,
C_I4 => 35,
C_I5 => 0,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 16,
C_M_AXIS_DATA_TDATA_WIDTH => 40,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END design_1_cic_compiler_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity Branch is
port (
clk : in std_logic;
d : in branch_in_t;
q : out branch_out_t := (
emit_tag => (others => '0'),
emit_link => (others => '0'),
emit_target => (others => '0')));
end Branch;
architecture twoproc of Branch is
signal c : std_logic_vector(2 downto 0) := "000";
signal a : value_t := (others => '0');
signal b : value_t := (others => '0');
signal target : blkram_addr := (others => '0');
signal link : blkram_addr := (others => '0');
begin
sequential : process(clk)
begin
if rising_edge(clk) then
c <= d.code; -- eliminating redundant bit
a <= d.val_a;
b <= d.val_b;
q.emit_tag <= d.tag_l;
q.emit_link <= d.val_l;
target <= d.val_t;
link <= d.val_l;
end if;
end process;
combinatorial : process(c, a, b, target, link)
variable ieq, ilt, feq, flt : boolean;
variable tmp_lt, tmp_z_a, tmp_z_b : boolean;
variable result : boolean;
constant z31 : std_logic_vector(30 downto 0) := (others => '0');
begin
tmp_lt := unsigned(a(30 downto 0)) < unsigned(b(30 downto 0));
tmp_z_a := a(30 downto 0) = z31;
tmp_z_b := b(30 downto 0) = z31;
ieq := a = b;
ilt := (a(31) = '1' and b(31) = '0') or
((a(31) = b(31)) and tmp_lt);
feq := ieq or (tmp_z_a and tmp_z_b);
flt := (a(31) = '1' and b(31) = '0') or
(a(31) = '0' and b(31) = '0' and tmp_lt) or
(a(31) = '1' and b(31) = '1' and not tmp_lt);
case c is
when "000" => result := ieq;
when "001" => result := not ieq;
when "010" => result := ilt;
when "011" => result := not ilt and not ieq;
when "100" => result := feq;
when "101" => result := not feq;
when "110" => result := flt and not feq;
when "111" => result := not flt and not feq;
when others => assert false;
end case;
if result then
q.emit_target <= target;
else
q.emit_target <= link;
end if;
end process;
end twoproc;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:42:54 07/12/05
-- Design Name:
-- Module Name: compare - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity compare is
Port ( Dhor : in std_logic_vector(10 downto 0);
Dver : in std_logic_vector(10 downto 0);
choose : out std_logic );
end compare;
architecture Behavioral of compare is
signal sub : std_logic_vector(10 downto 0);
begin
sub <= Dver(10 downto 0) + ((not Dhor(10 downto 0)) + '1');
choose <= sub(10);
end Behavioral;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DIGDUG_ROM IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DIGDUG_ROM;
ARCHITECTURE DIGDUG_ROM_arch OF DIGDUG_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DIGDUG_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DIGDUG_ROM_arch : ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=DIGDUG_ROM.mif,C_INIT_FILE=DIGDUG_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "DIGDUG_ROM.mif",
C_INIT_FILE => "DIGDUG_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DIGDUG_ROM_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.hw_type_pkg.all;
package board_pkg is
constant c_FW_IDENT : std_logic_vector(31 downto 0) := c_HW_IDENT & x"030241";
constant c_TX_ENCODING : string := "OSERDES";
constant c_TX_CHANNELS : integer := 4;
constant c_RX_CHANNELS : integer := 4;
constant c_FE_TYPE : string := "RD53";
constant c_RX_NUM_LANES : integer := 4;
constant c_RX_SPEED : string := "1280";
constant c_TX_IDLE_WORD : std_logic_vector(31 downto 0) := x"AAAAAAAA";
constant c_TX_SYNC_WORD : std_logic_vector(31 downto 0) := x"817e817e";
constant c_TX_SYNC_INTERVAL : unsigned(7 downto 0) := to_unsigned(16,8);
constant c_TX_AZ_WORD : std_logic_vector(31 downto 0) := x"00000000";
constant c_TX_AZ_INTERVAL : unsigned(15 downto 0) := to_unsigned(500,16);
constant c_TX_40_DIVIDER : unsigned(3 downto 0) := to_unsigned(4,4);
end board_pkg;
|
-- *** 2_bit_predictor.vhd *** --
-- this block is a simple 2 bit predictor.
-- it implements the canonical FSM for 2 bit preditcors
-- look at the scheme on Hennessy Patterson 5th Ed., figure C-18
-- this needs to be implemented for each line of the BTB cache
-- Future improvements: integrate this into the BTB in order to instatiate only one
library ieee;
use ieee.std_logic_1164.all;
entity predictor_2 is
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic; -- if 1 FSM advances, 0 is frozen
taken_i : in std_logic; -- input bit -> 1 taken, 0 not taken
prediction_o : out std_logic -- output but -> 1 taken, 0 not taken
);
end predictor_2;
architecture bhe of predictor_2 is
-- state is on 2 bits
-- 00 strong NT
-- 01 weak NT
-- 10 weak T
-- 11 strong T
signal STATE : std_logic_vector(1 downto 0);
signal next_STATE : std_logic_vector(1 downto 0);
begin
-- output of the circuit is the MSB of the state
prediction_o <= STATE(1);
-- sequential process for state update
process(clock,reset)
begin
if reset='1' then
STATE <= "00";
elsif clock = '1' and clock'event and enable = '1' then
STATE <= next_STATE;
end if;
end process;
-- combinatorial process for next_STATE computation
-- Future improvements : do this by hand
process(taken_i, enable)
begin
if enable = '1' then
if taken_i = '1' then
case STATE is
when "00" => next_STATE <= "01";
when "01" => next_STATE <= "10";
when "10" => next_STATE <= "11";
when "11" => next_STATE <= "11";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
else
case STATE is
when "00" => next_STATE <= "00";
when "01" => next_STATE <= "00";
when "10" => next_STATE <= "01";
when "11" => next_STATE <= "10";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
end if;
end if;
end process;
end bhe;
|
-- *** 2_bit_predictor.vhd *** --
-- this block is a simple 2 bit predictor.
-- it implements the canonical FSM for 2 bit preditcors
-- look at the scheme on Hennessy Patterson 5th Ed., figure C-18
-- this needs to be implemented for each line of the BTB cache
-- Future improvements: integrate this into the BTB in order to instatiate only one
library ieee;
use ieee.std_logic_1164.all;
entity predictor_2 is
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic; -- if 1 FSM advances, 0 is frozen
taken_i : in std_logic; -- input bit -> 1 taken, 0 not taken
prediction_o : out std_logic -- output but -> 1 taken, 0 not taken
);
end predictor_2;
architecture bhe of predictor_2 is
-- state is on 2 bits
-- 00 strong NT
-- 01 weak NT
-- 10 weak T
-- 11 strong T
signal STATE : std_logic_vector(1 downto 0);
signal next_STATE : std_logic_vector(1 downto 0);
begin
-- output of the circuit is the MSB of the state
prediction_o <= STATE(1);
-- sequential process for state update
process(clock,reset)
begin
if reset='1' then
STATE <= "00";
elsif clock = '1' and clock'event and enable = '1' then
STATE <= next_STATE;
end if;
end process;
-- combinatorial process for next_STATE computation
-- Future improvements : do this by hand
process(taken_i, enable)
begin
if enable = '1' then
if taken_i = '1' then
case STATE is
when "00" => next_STATE <= "01";
when "01" => next_STATE <= "10";
when "10" => next_STATE <= "11";
when "11" => next_STATE <= "11";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
else
case STATE is
when "00" => next_STATE <= "00";
when "01" => next_STATE <= "00";
when "10" => next_STATE <= "01";
when "11" => next_STATE <= "10";
when others => next_STATE <= "00"; -- might not be synthesizable
end case;
end if;
end if;
end process;
end bhe;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_dma_0_wrapper_fifo_generator_v9_3_1_pkg.ALL;
ENTITY system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_dma_0_wrapper_fifo_generator_v9_3_1_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_dma_0_wrapper_fifo_generator_v9_3_1_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_jtag_uart_scfifo_w is
port(
clk : in vl_logic;
fifo_clear : in vl_logic;
fifo_wdata : in vl_logic_vector(7 downto 0);
fifo_wr : in vl_logic;
rd_wfifo : in vl_logic;
fifo_FF : out vl_logic;
r_dat : out vl_logic_vector(7 downto 0);
wfifo_empty : out vl_logic;
wfifo_used : out vl_logic_vector(5 downto 0)
);
end finalproject_jtag_uart_scfifo_w;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity erode_process is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_value : in std_logic_vector(15 downto 0);
heigtimg_reg_value : in std_logic_vector(15 downto 0);
er00_reg_m00 : in std_logic_vector(7 downto 0);
er01_reg_m01 : in std_logic_vector(7 downto 0);
er02_reg_m02 : in std_logic_vector(7 downto 0);
er10_reg_m10 : in std_logic_vector(7 downto 0);
er11_reg_m11 : in std_logic_vector(7 downto 0);
er12_reg_m12 : in std_logic_vector(7 downto 0);
er20_reg_m20 : in std_logic_vector(7 downto 0);
er21_reg_m21 : in std_logic_vector(7 downto 0);
er22_reg_m22 : in std_logic_vector(7 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end erode_process;
architecture rtl of erode_process is
component matrix_extractor
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00, p01, p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10, p11, p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20, p21, p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end component;
-- neighbors extraction
signal p00, p01, p02 : std_logic_vector((IN_SIZE-1) downto 0);
signal p10, p11, p12 : std_logic_vector((IN_SIZE-1) downto 0);
signal p20, p21, p22 : std_logic_vector((IN_SIZE-1) downto 0);
signal matrix_dv : std_logic;
-- Erosion matrix
-- 0 1 0 e00 e01 e02
-- 1 1 1 e10 e11 e12
-- 0 1 0 e20 e21 e22
signal e00, e01, e02 : unsigned((IN_SIZE-1) downto 0);
signal e10, e11, e12 : unsigned((IN_SIZE-1) downto 0);
signal e20, e21, e22 : unsigned((IN_SIZE-1) downto 0);
-- parsing back from value to flow
signal value_data : std_logic_vector((IN_SIZE-1) downto 0);
signal value_dv : std_logic;
signal out_fv_s : std_logic;
signal enable_s : std_logic;
signal erode_dv : std_logic;
begin
matrix_extractor_inst : matrix_extractor
generic map (
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
PIX_WIDTH => IN_SIZE,
OUTVALUE_WIDTH => IN_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
p00 => p00, p01 => p01, p02 => p02,
p10 => p10, p11 => p11, p12 => p12,
p20 => p20, p21 => p21, p22 => p22,
matrix_dv => matrix_dv,
value_data => value_data,
value_dv => value_dv,
out_data => out_data,
out_fv => out_fv_s,
out_dv => out_dv,
enable_i => status_reg_enable_bit,
widthimg_i => widthimg_reg_value
);
data_process : process (clk_proc, reset_n, matrix_dv)
variable val : unsigned((IN_SIZE-1) downto 0);
begin
if(reset_n='0') then
enable_s <= '0';
erode_dv <= '0';
value_dv <= '0';
elsif(rising_edge(clk_proc)) then
-- Waiting for an image flow
if(in_fv = '0') then
-- Update params here, between two images processing
enable_s <= status_reg_enable_bit;
e00 <= unsigned(er00_reg_m00);
e01 <= unsigned(er01_reg_m01);
e02 <= unsigned(er02_reg_m02);
e10 <= unsigned(er10_reg_m10);
e11 <= unsigned(er11_reg_m11);
e12 <= unsigned(er12_reg_m12);
e20 <= unsigned(er20_reg_m20);
e21 <= unsigned(er21_reg_m21);
e22 <= unsigned(er22_reg_m22);
value_dv <= '0';
end if;
-- A matrix is available to process
erode_dv <= '0';
if(matrix_dv = '1' and enable_s = '1') then
val := (others => '1');
--
if(e00 /=0) then
if(val>unsigned(p00)) then
val := unsigned(p00);
end if;
end if;
--
if(e01 /=0) then
if(val>unsigned(p01)) then
val := unsigned(p01);
end if;
end if;
--
if(e02 /=0) then
if(val>unsigned(p02)) then
val := unsigned(p02);
end if;
end if;
--
if(e10 /=0) then
if(val>unsigned(p10)) then
val := unsigned(p10);
end if;
end if;
--
if(e11 /=0) then
if(val>unsigned(p11)) then
val := unsigned(p11);
end if;
end if;
--
if(e12 /=0) then
if(val>unsigned(p12)) then
val := unsigned(p12);
end if;
end if;
--
if(e20 /=0) then
if(val>unsigned(p20)) then
val := unsigned(p20);
end if;
end if;
--
if(e21 /=0) then
if(val>unsigned(p21)) then
val := unsigned(p21);
end if;
end if;
--
if(e22 /=0) then
if(val>unsigned(p22)) then
val := unsigned(p22);
end if;
end if;
erode_dv <= '1';
end if;
-- Matrix process has ended
if(enable_s = '1' and erode_dv = '1') then
value_data <= std_logic_vector(val)(OUT_SIZE -1 downto 0);
value_dv <= '1';
else
value_dv <= '0';
end if;
end if;
end process;
out_fv <= enable_s and out_fv_s;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Paris Moschovakos & Panagiotis Gkountoumis
--
-- Create Date:
-- Design Name:
-- Module Name:
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity mmfe8_top is
port(
-- Trigger pins
-- CTF 1.0 External Trigger
EXT_TRIGGER_P : in std_logic;
EXT_TRIGGER_N : in std_logic;
-- Arizona Board for External Trigger
-- EXT_TRIG_IN : in std_logic;
TRIGGER_LOOP_P : out std_logic;
TRIGGER_LOOP_N : out std_logic;
-- LED's
LED_BANK_13 : out std_logic;
LED_BANK_14 : out std_logic;
LED_BANK_15 : out std_logic;
LED_BANK_16 : out std_logic;
LED_BANK_34 : out std_logic;
LED_BANK_35 : out std_logic;
-- 200.0359MHz from bank 14
X_2V5_DIFF_CLK_P : in std_logic;
X_2V5_DIFF_CLK_N : in std_logic;
-- glbl_rst : in std_logic;
-- Tranceiver Interface
-----------------------
gtrefclk_p : in std_logic; -- Differential +ve of reference clock for tranceiver: 125MHz, very high quality
gtrefclk_n : in std_logic; -- Differential -ve of reference clock for tranceiver: 125MHz, very high quality
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
phy_int : out std_logic;
phy_rstn_out : out std_logic;
DATA0_1_P, DATA0_1_N : IN STD_LOGIC;
DATA0_2_P, DATA0_2_N : IN STD_LOGIC;
DATA0_3_P, DATA0_3_N : IN STD_LOGIC;
DATA0_4_P, DATA0_4_N : IN STD_LOGIC;
DATA0_5_P, DATA0_5_N : IN STD_LOGIC;
DATA0_6_P, DATA0_6_N : IN STD_LOGIC;
DATA0_7_P, DATA0_7_N : IN STD_LOGIC;
DATA0_8_P, DATA0_8_N : IN STD_LOGIC;
DATA1_1_P, DATA1_1_N : IN STD_LOGIC;
DATA1_2_P, DATA1_2_N : IN STD_LOGIC;
DATA1_3_P, DATA1_3_N : IN STD_LOGIC;
DATA1_4_P, DATA1_4_N : IN STD_LOGIC;
DATA1_5_P, DATA1_5_N : IN STD_LOGIC;
DATA1_6_P, DATA1_6_N : IN STD_LOGIC;
DATA1_7_P, DATA1_7_N : IN STD_LOGIC;
DATA1_8_P, DATA1_8_N : IN STD_LOGIC;
DO_1_P, DO_1_N : IN STD_LOGIC;
DO_2_P, DO_2_N : IN STD_LOGIC;
DO_3_P, DO_3_N : IN STD_LOGIC;
DO_4_P, DO_4_N : IN STD_LOGIC;
DO_5_P, DO_5_N : IN STD_LOGIC;
DO_6_P, DO_6_N : IN STD_LOGIC;
DO_7_P, DO_7_N : IN STD_LOGIC;
DO_8_P, DO_8_N : IN STD_LOGIC;
DI_1_P, DI_1_N : OUT STD_LOGIC;
DI_2_P, DI_2_N : OUT STD_LOGIC;
DI_3_P, DI_3_N : OUT STD_LOGIC;
DI_4_P, DI_4_N : OUT STD_LOGIC;
DI_5_P, DI_5_N : OUT STD_LOGIC;
DI_6_P, DI_6_N : OUT STD_LOGIC;
DI_7_P, DI_7_N : OUT STD_LOGIC;
DI_8_P, DI_8_N : OUT STD_LOGIC;
WEN_1_P, WEN_1_N : OUT STD_LOGIC;
WEN_2_P, WEN_2_N : OUT STD_LOGIC;
WEN_3_P, WEN_3_N : OUT STD_LOGIC;
WEN_4_P, WEN_4_N : OUT STD_LOGIC;
WEN_5_P, WEN_5_N : OUT STD_LOGIC;
WEN_6_P, WEN_6_N : OUT STD_LOGIC;
WEN_7_P, WEN_7_N : OUT STD_LOGIC;
WEN_8_P, WEN_8_N : OUT STD_LOGIC;
ENA_1_P, ENA_1_N : OUT STD_LOGIC;
ENA_2_P, ENA_2_N : OUT STD_LOGIC;
ENA_3_P, ENA_3_N : OUT STD_LOGIC;
ENA_4_P, ENA_4_N : OUT STD_LOGIC;
ENA_5_P, ENA_5_N : OUT STD_LOGIC;
ENA_6_P, ENA_6_N : OUT STD_LOGIC;
ENA_7_P, ENA_7_N : OUT STD_LOGIC;
ENA_8_P, ENA_8_N : OUT STD_LOGIC;
CKTK_1_P, CKTK_1_N : OUT STD_LOGIC;
CKTK_2_P, CKTK_2_N : OUT STD_LOGIC;
CKTK_3_P, CKTK_3_N : OUT STD_LOGIC;
CKTK_4_P, CKTK_4_N : OUT STD_LOGIC;
CKTK_5_P, CKTK_5_N : OUT STD_LOGIC;
CKTK_6_P, CKTK_6_N : OUT STD_LOGIC;
CKTK_7_P, CKTK_7_N : OUT STD_LOGIC;
CKTK_8_P, CKTK_8_N : OUT STD_LOGIC;
CKTP_1_P, CKTP_1_N : OUT STD_LOGIC;
CKTP_2_P, CKTP_2_N : OUT STD_LOGIC;
CKTP_3_P, CKTP_3_N : OUT STD_LOGIC;
CKTP_4_P, CKTP_4_N : OUT STD_LOGIC;
CKTP_5_P, CKTP_5_N : OUT STD_LOGIC;
CKTP_6_P, CKTP_6_N : OUT STD_LOGIC;
CKTP_7_P, CKTP_7_N : OUT STD_LOGIC;
CKTP_8_P, CKTP_8_N : OUT STD_LOGIC;
CKBC_1_P, CKBC_1_N : OUT STD_LOGIC;
CKBC_2_P, CKBC_2_N : OUT STD_LOGIC;
CKBC_3_P, CKBC_3_N : OUT STD_LOGIC;
CKBC_4_P, CKBC_4_N : OUT STD_LOGIC;
CKBC_5_P, CKBC_5_N : OUT STD_LOGIC;
CKBC_6_P, CKBC_6_N : OUT STD_LOGIC;
CKBC_7_P, CKBC_7_N : OUT STD_LOGIC;
CKBC_8_P, CKBC_8_N : OUT STD_LOGIC;
CKDT_1_P, CKDT_1_N : OUT STD_LOGIC;
CKDT_2_P, CKDT_2_N : OUT STD_LOGIC;
CKDT_3_P, CKDT_3_N : OUT STD_LOGIC;
CKDT_4_P, CKDT_4_N : OUT STD_LOGIC;
CKDT_5_P, CKDT_5_N : OUT STD_LOGIC;
CKDT_6_P, CKDT_6_N : OUT STD_LOGIC;
CKDT_7_P, CKDT_7_N : OUT STD_LOGIC;
CKDT_8_P, CKDT_8_N : OUT STD_LOGIC
);
end mmfe8_top;
architecture Behavioral of mmfe8_top is
-- IP and MAC address of the MMFE8
constant myIP : std_logic_vector(31 downto 0) := x"c0a80003";
constant myMAC : std_logic_vector(47 downto 0) := x"002320212224";
-- clock generation signals for tranceiver
signal gtrefclkp, gtrefclkn : std_logic; -- Route gtrefclk through an IBUFG.
signal txoutclk : std_logic; -- txoutclk from GT transceiver
signal resetdone : std_logic; -- To indicate that the GT transceiver has completed its reset cycle
signal mmcm_locked : std_logic; -- MMCM locked signal.
signal mmcm_reset : std_logic; -- MMCM reset signal.
signal clkfbout : std_logic; -- MMCM feedback clock
signal userclk : std_logic; -- 62.5MHz clock for GT transceiver Tx/Rx user clocks
signal userclk2 : std_logic; -- 125MHz clock for core reference clock.
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0); -- flip-flop pipeline for reset duration stretch
signal pma_reset : std_logic; -- Synchronous transcevier PMA reset
-- An independent clock source used as the reference clock for an
-- IDELAYCTRL (if present) and for the main GT transceiver reset logic.
signal independent_clock_bufg: std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to rising edge DDR).
signal sgmii_clk_f : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to falling edge DDR).
-- GMII signals
signal gmii_isolate : std_logic; -- Internal gmii_isolate signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal (between core and SGMII adaptation module).
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal (between core and SGMII adaptation module).
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal (between core and SGMII adaptation module).
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- Internal gmii_rxd signal (between core and SGMII adaptation module).
signal gmii_rx_dv_int : std_logic; -- Internal gmii_rx_dv signal (between core and SGMII adaptation module).
signal gmii_rx_er_int : std_logic; -- Internal gmii_rx_er signal (between core and SGMII adaptation module).
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
----------------------------panos---------------------------------
signal gmii_txd_emac : std_logic_vector(7 downto 0);
signal gmii_tx_en_emac : std_logic;
signal gmii_tx_er_emac : std_logic;
signal gmii_rxd_emac : std_logic_vector(7 downto 0);
signal gmii_rx_dv_emac : std_logic;
signal gmii_rx_er_emac : std_logic;
signal sgmii_clk_int : std_logic;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal tx_axis_mac_tready_int : std_logic;
signal rx_axis_mac_tuser_int : std_logic;
signal rx_axis_mac_tlast_int : std_logic;
signal rx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid_int : std_logic;
signal local_gtx_reset : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal gtx_pre_resetn : std_logic := '0';
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid_int : std_logic;
signal tx_axis_mac_tlast_int : std_logic;
signal gtx_resetn : std_logic;
signal glbl_rstn : std_logic;
signal glbl_rst_i : std_logic;
signal gtx_clk_reset_int : std_logic;
signal an_restart_config_int : std_logic;
signal rx_axis_mac_tready_int : std_logic;
signal rx_configuration_vector_int : std_logic_vector(79 downto 0);
signal tx_configuration_vector_int : std_logic_vector(79 downto 0);
signal vector_resetn : std_logic := '0';
signal vector_pre_resetn : std_logic := '0';
signal vector_reset_int : std_logic;
signal independent_clock_int : std_logic;
signal rst_gtclk_int : std_logic;
signal clk_enable_int : std_logic;
signal sgmii_clk_int_oddr : std_logic;
signal udp_txi_int : udp_tx_type;
signal control : udp_control_type;
signal udp_rx_int : udp_rx_type;
signal ip_rx_hdr_int : ipv4_rx_header_type;
signal udp_tx_data_out_ready_int : std_logic;
signal udp_tx_start_int : std_logic;
signal rxp_int : std_logic;
signal rxn_int : std_logic;
signal clkfbout2, clkfbout1 : std_logic;
signal tx_axis_mac_tuser_int : std_logic := '1';
signal test_data : std_logic_vector(7 downto 0);
signal test_valid, test_last : std_logic;
signal test_data_out : std_logic_vector(7 downto 0);
signal test_valid_out, test_last_out : std_logic;
signal user_data_out_i : std_logic_vector(63 downto 0);
signal sig_out200 : std_logic_vector(127 downto 0);
signal user_conf_i : std_logic := '0';
signal send_error_int : std_logic := '0';
signal send_error_done_int : std_logic := '0';
signal resp_data_int : resp_data;
signal user_wr_en_int : std_logic := '0';
signal reset : std_logic := '0';
signal end_packet_i : std_logic := '0';
signal conf_done_int_synced : std_logic := '0';
signal we_conf_int : std_logic := '0';
signal conf_packet_length_int : integer := 0;
signal packet_length_int : integer := 0;
signal daq_data_out_i : std_logic_vector(63 downto 0);
signal conf_data_out_i : std_logic_vector(63 downto 0);
signal daq_wr_en_i : std_logic := '0';
signal end_packet_daq : std_logic := '0';
signal start_conf_proc_int : std_logic := '0';
signal status_int_old : std_logic_vector(3 downto 0);
------------------------------VMM configuration------------------------------
signal vmm_do_vec_i : std_logic_vector(8 downto 1);
signal conf_cktk_out_i : std_logic := '0';
signal trig_mode_int : std_logic := '0';
------------------------------ Select VMM ------------------------------
signal cktk_out_vec_i : std_logic_vector(8 downto 1);
signal vmm_wen_i : std_logic := '0';
signal vmm_ena_i : std_logic := '0';
-------------------------------------------------
-- Configuration Signals
-------------------------------------------------
signal configuring_i : std_logic;
signal reading_i_200 : std_logic;
signal conf_done_i_200 : std_logic;
signal cntr, cntr2 : integer := 0;
signal vmm_cnt, counter : integer := 0;
signal reset_done : std_logic := '0';
signal vmm_data0_1_syn : std_logic;
signal vmm_data1_1_syn : std_logic;
signal vmm_data0_ii_d : std_logic;
signal vmm_data0_ii : std_logic;
signal vmm_data0_i : std_logic;
signal vmm_do_fde_sync : std_logic;
signal vmm_do_fde : std_logic;
signal vmm_do_fde_i : std_logic;
signal delay_wen : integer := 0;
signal w : integer := 0;
signal data_fifo_wr_en : std_logic;
signal data_fifo_wr_en_i : std_logic;
signal data_fifo_din_i : std_logic_vector(7 DOWNTO 0);
signal data_fifo_rd_en : std_logic;
signal data_fifo_rd_en_i : std_logic;
-- signal data_fifo_dout_i : std_logic_vector(0 DOWNTO 0);
signal data_fifo_empty : std_logic;
signal data_fifo_rd_count : std_logic_vector(14 DOWNTO 0);
signal data_fifo_wr_count : std_logic_vector(14 DOWNTO 0);
signal vmm_cfg_sel_i : std_logic_vector(31 downto 0);
signal turn_counter_i : std_logic_vector(15 downto 0);
signal conf_data_in_i : std_logic_vector (7 downto 0);
signal udp_response_int : udp_response;
signal clk_400_noclean : std_logic;
signal clk_400_clean : std_logic;
signal clk_200 : std_logic;
signal clk_800 : std_logic;
signal clk_10_phase45 : std_logic;
signal clk_50 : std_logic;
signal clk_40 : std_logic;
signal clk_10 : std_logic;
signal gbl_rst : std_logic; --coming from UDP
signal acq_rst : std_logic; --coming from UDP
signal vmm_ena_gbl_rst : std_logic := '0';
signal vmm_wen_gbl_rst : std_logic := '0';
signal vmm_ena_acq_rst : std_logic := '0';
signal vmm_wen_acq_rst : std_logic := '0';
-- signal conf_data_out_i : std_logic_vector(7 downto 0);
signal vmm_data_buf_i : std_logic_vector(37 downto 0);
-- vmm signals
signal conf_di_i : std_logic;
signal conf_do_i : std_logic;
signal conf_ena_i : std_logic := '0';
signal conf_wen_i : std_logic;
signal conf_cktk_i : std_logic;
signal vmm_do_1_i : std_logic := '0';
signal vmm_di_en : std_logic;
signal vmm_di_r : std_logic;
signal vmm_wen_en : std_logic;
signal vmm_wen_R : std_logic;
signal vmm_ena_en : std_logic;
signal vmm_ena_r : std_logic;
signal vmm_cktk_en : std_logic;
signal vmm_cktk_r : std_logic;
signal vmm_cktp : std_logic;
signal vmm_cktp_en : std_logic;
signal vmm_cktp_r : std_logic;
signal vmm_ckbc : std_logic;
signal vmm_ckbc_en : std_logic;
signal vmm_ckbc_R : std_logic;
signal dt_cntr_intg0_i : integer;
signal ckdt_cntr, timeout : integer := 0;
signal dt_cntr_intg1_i : integer;
signal conf_cnt : integer := 0;
signal cnt_vmm : integer := 0;
-- signal timeout : integer := 0;
signal vmm_2cfg_i : std_logic_vector( 2 DOWNTO 0);
signal mmfeID_i : std_logic_vector( 3 DOWNTO 0);
signal clk_dt_out : std_logic;
signal vmm_ckart : std_logic;
signal vmm_ckart_en : std_logic;
signal vmm_ckart_r : std_logic;
signal clk_tk_out : std_logic;
signal clk_bc_out : std_logic;
signal testX, reading_i : std_logic := '0';
signal clk_tp_out : std_logic ;
signal write_done_i : std_logic;
signal fifo_writing_i : std_logic;
signal global_reset : std_logic := '0';
signal conf_done_i : std_logic;
signal cktp_send : std_logic := '0';
signal conf_wait : std_logic := '0';
signal udp_tx_start_reply : std_logic := '0';
signal udp_tx_start_daq : std_logic := '0';
signal re_out_int : std_logic := '0';
signal fifo_data_out_int : std_logic_vector(7 downto 0) := x"00";
signal fifo_data : std_logic_vector(7 downto 0) := x"00";
signal re_out : std_logic := '0';
signal status_int : std_logic_vector(3 downto 0) := "0000";
signal status_int_synced : std_logic_vector(3 downto 0) := "0000";
signal cnt_reset : integer := 0;
signal set_reset : std_logic := '0';
signal conf_done_int : std_logic := '0';
signal udp_header_int : std_logic := '0';
signal cnt_reply : integer := 0;
signal end_packet_conf_int : std_logic := '0';
signal end_packet_daq_int : std_logic := '0';
signal is_state : std_logic_vector(3 downto 0) := "1010";
signal ACQ_sync_int : std_logic_vector(15 downto 0) := x"0000";
signal udp_busy : std_logic := '0';
-------------------------------------------------
-- VMM2 Signals
-------------------------------------------------
signal vmm_wen_vec : std_logic_vector(8 downto 1);
signal vmm_ena_vec : std_logic_vector(8 downto 1);
signal cktk_out_vec : std_logic_vector(8 downto 1);
signal ckdt_out_vec : std_logic_vector(8 downto 1);
signal vmm_do_vec : std_logic_vector(8 downto 1);
signal vmm_di_vec_i : std_logic_vector(8 downto 1);
signal cktk_out_i : std_logic;
signal vmm_id : std_logic_vector(15 downto 0) := x"0000";
signal vmm_id_int : std_logic_vector(15 downto 0) := x"0000";
signal vmm_id_synced : std_logic_vector(15 downto 0) := x"0000";
signal vmm_id_old : std_logic_vector(15 downto 0) := x"0000";
signal vmm_do_1 : std_logic;
signal vmm_cktp_1 : std_logic;
signal vmm_data0_1 : std_logic;
signal vmm_data1_1 : std_logic;
signal vmm_art_1 : std_logic;
-- signal vmm_ckart_1 : std_logic;
signal vmm_do_2 : std_logic;
signal vmm_cktp_2 : std_logic;
signal vmm_data0_2 : std_logic;
signal vmm_data1_2 : std_logic;
signal vmm_art_2 : std_logic;
-- signal vmm_ckart_2 : std_logic;
signal vmm_do_3 : std_logic;
signal vmm_cktp_3 : std_logic;
signal vmm_data0_3 : std_logic;
signal vmm_data1_3 : std_logic;
signal vmm_art_3 : std_logic;
-- signal vmm_ckart_3 : std_logic;
signal vmm_do_4 : std_logic;
signal vmm_cktp_4 : std_logic;
signal vmm_data0_4 : std_logic;
signal vmm_data1_4 : std_logic;
signal vmm_art_4 : std_logic;
-- signal vmm_ckart_4 : std_logic;
signal vmm_do_5 : std_logic;
signal vmm_cktp_5 : std_logic;
signal vmm_data0_5 : std_logic;
signal vmm_data1_5 : std_logic;
signal vmm_art_5 : std_logic;
-- signal vmm_ckart_5 : std_logic;
signal vmm_do_6 : std_logic;
signal vmm_cktp_6 : std_logic;
signal vmm_data0_6 : std_logic;
signal vmm_data1_6 : std_logic;
signal vmm_art_6 : std_logic;
-- signal vmm_ckart_6 : std_logic;
signal vmm_do_7 : std_logic;
signal vmm_cktp_7 : std_logic;
signal vmm_data0_7 : std_logic;
signal vmm_data1_7 : std_logic;
signal vmm_art_7 : std_logic;
-- signal vmm_ckart_7 : std_logic;
signal vmm_do_8 : std_logic;
signal vmm_cktp_8 : std_logic;
signal vmm_data0_8 : std_logic;
signal vmm_data1_8 : std_logic;
signal vmm_art_8 : std_logic;
-- signal vmm_ckart_8 : std_logic;
-------------------------------------------------
-- Readout Signals
-------------------------------------------------
signal daq_enable_i : std_logic;
signal daq_done : std_logic;
signal cktp_state : integer := 0;
signal ro_cktk_8 : std_logic;
signal ro_ckdt_8 : std_logic;
signal ro_vmm_wen_8 : std_logic := '0';
signal ro_vmm_ena_8 : std_logic := '0';
signal ro_cktk_5 : std_logic;
signal ro_ckdt_5 : std_logic;
signal ro_vmm_wen_5 : std_logic := '0';
signal ro_vmm_ena_5 : std_logic := '0';
signal daqFIFO_wr_en_i : std_logic := '0';
signal daqFIFO_din_i : std_logic_vector(63 downto 0);
signal daqFIFO_dout_i : std_logic_vector(7 downto 0);
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(63 downto 0);
signal vmmEventDone_i : std_logic := '0';
signal daqFIFO_reset : std_logic := '0';
signal daq_vmm_ena_enable : std_logic := '0';
signal daq_vmm_wen_enable : std_logic := '0';
-------------------------------------------------
-- Trigger Signals
-------------------------------------------------
signal tren : std_logic := '0';
signal tr_hold : std_logic := '0';
signal trmode : std_logic := '0';
signal ext_trigger_in : std_logic := '0';
signal trint : std_logic := '0';
signal tr_reset : std_logic := '0';
signal event_counter_i : std_logic_vector(31 downto 0);
signal event_counter_ila : std_logic_vector(31 downto 0);
signal tr_out_i : std_logic;
signal trigger_loop : std_logic;
signal trigger_loop_i : std_logic;
signal ext_trigger_i : std_logic;
signal internalTrigger_state : integer := 0;
-------------------------------------------------
-- Packet Formation Signals
-------------------------------------------------
signal pf_datain_i : std_logic_vector(63 downto 0);
signal pf_newCycle : std_logic;
signal pf_dataout : std_logic_vector(63 downto 0);
signal pf_wren : std_logic;
signal pf_packLen : integer;
signal pf_trigVmmRo : std_logic := '0';
-------------------------------------------------
-- Flow FSM signals
-------------------------------------------------
type state_t is (IDLE, CONFIGURE, CONF_DONE, SEND_CONF_REPLY, DAQ_INIT, DAQ, TRIG);
signal state : state_t;
-------------------------------------------------------------------
-- COMPONENTS --
-------------------------------------------------------------------
-- 1. clk_wiz_200_to_400
-- 2. clk_wiz_low_jitter
-- 3. clk_wiz_0
-- 4. vmm_global_reset
-- 5. event_timing_reset
-- 6. select_vmm
-- 7. configuration_block
-- 8. vmm_readout
-- 9. FIFO2UDP
-- 10. trigger
-- 11. ila_top
-- 12. FIFO2Elink
-- 13. Elink2FIFO
-- 14. Please add the components
-- ...
-- 21.
-------------------------------------------------------------------
-- 1
component clk_wiz_200_to_400
port(
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
clk_out_400 : out std_logic
);
end component;
-- 2
component clk_wiz_low_jitter
port(
clk_in1 : in std_logic;
clk_out1 : out std_logic
);
end component;
-- 3
component clk_wiz_0
port(
clk_in1 : in std_logic;
reset : in std_logic;
clk_200_o : out std_logic;
clk_800_o : out std_logic;
clk_10_phase45_o: out std_logic;
clk_50_o : out std_logic;
clk_40_o : out std_logic;
clk_10_o : out std_logic
);
end component;
-- 4
component vmm_global_reset
port(
clk : in std_logic;
rst : in std_logic; -- reset
gbl_rst : in std_logic; -- from control register. a pulse
vmm_ena : out std_logic; -- these will be ored with same from other sm
vmm_wen : out std_logic -- these will be ored with same from other sm
);
end component;
-- 5
component event_timing_reset
port(
hp_clk : in std_logic;
bc_clk : in std_logic;
trigger : in std_logic;
readout_done : in std_logic;
reset : in std_logic;
bcid : out std_logic_vector(12 downto 0);
prec_cnt : out std_logic_vector(4 downto 0);
vmm_ena : out std_logic;
vmm_wen : out std_logic
);
end component;
-- 6
component select_vmm
port (
clk_in : in std_logic;
vmm_id : in std_logic_vector(15 downto 0);
conf_di : in std_logic;
conf_di_vec : out std_logic_vector(8 downto 1);
conf_do : out std_logic;
conf_do_vec : in std_logic_vector(8 downto 1);
cktk_out : in std_logic;
cktk_out_vec : out std_logic_vector(8 downto 1);
conf_wen : in std_logic;
conf_wen_vec : out std_logic_vector(8 downto 1);
conf_ena : in std_logic;
conf_ena_vec : out std_logic_vector(8 downto 1)
);
end component;
-- 7
component configuration_block
port
(
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
cfg_bit_in : in std_logic ;
cfg_bit_out : out std_logic ;
vmm_cktk : out std_logic ;
configuring : in std_logic;
conf_done : out std_logic;
data_fifo_wr_en : in std_logic := '0'; -- signal cannot be driven from top module !!!
data_fifo_din : in std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
-- data_fifo_rd_en : in std_logic;-- := '0';
data_fifo_empty : out std_logic := '0';
data_fifo_rd_count : out std_logic_vector(14 DOWNTO 0) := (OTHERS => '0');
data_fifo_wr_count : out std_logic_vector(14 DOWNTO 0) := (OTHERS => '0');
conf_data_in : in STD_LOGIC_VECTOR(7 downto 0);
conf_data_out : out STD_LOGIC_VECTOR(7 downto 0);
vmm_cfg_sel : in STD_LOGIC_VECTOR(31 downto 0));
end component;
-- 8
component vmm_readout is
port (
vmm_data0 : in std_logic; -- Single-ended data0 from VMM
vmm_data1 : in std_logic; -- Single-ended data1 from VMM
clk_10_phase45 : in std_logic; -- Used to clock checking for data process
clk_50 : in std_logic; -- Used to clock word readout process
clk_200 : in std_logic;
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- To be used trigger
ethernet_fifo_wr_en : out std_logic; -- To be used to for ethernet to software readout
latency : in std_logic_vector(15 downto 0);
vmm_ckdt : out std_logic; -- Strobe to VMM CKDT
vmm_cktk : out std_logic; -- Strobe to VMM CKTK
acq_rst_from_data0 : out std_logic; -- Send a soft reset when done
vmm_data_buf : buffer std_logic_vector(37 downto 0);
vmm_wen : out std_logic;
vmm_ena : out std_logic;
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(63 downto 0);
vmmEventDone : out std_logic
);
end component;
-- 9
component FIFO2UDP
port (
clk_200 : in std_logic;
clk_125 : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
control : out std_logic;
re_out : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in integer;
reset_DAQ_FIFO : in std_logic;
sending_o : out std_logic
);
end component;
-- 10
component trigger is
port (
clk_200 : in std_logic;
tren : in std_logic;
tr_hold : in std_logic;
trmode : in std_logic;
trext : in std_logic;
trint : in std_logic;
reset : in std_logic;
event_counter : out std_logic_vector(31 DOWNTO 0);
tr_out : out std_logic
);
end component;
-- 11
component packet_formation is
port (
clk_200 : in std_logic;
newCycle : in std_logic;
eventCounter : in std_logic_vector(31 downto 0);
trigVmmRo : out std_logic;
vmmWord : in std_logic_vector(63 downto 0);
vmmWordReady : in std_logic;
vmmEventDone : in std_logic;
packLen : out integer;
dataout : out std_logic_vector(63 downto 0);
wrenable : out std_logic;
end_packet : out std_logic;
udp_busy : in std_logic;
tr_hold : out std_logic
);
end component;
-- 12
component gig_ethernet_pcs_pma_0
port(
-- Transceiver Interface
---------------------
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
gtrefclk_out : out std_logic; -- Very high quality clock for GT transceiver.
gtrefclk_bufg_out : out std_logic;
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
userclk_out : out std_logic;
userclk2_out : out std_logic;
rxuserclk_out : out std_logic;
rxuserclk2_out : out std_logic;
pma_reset_out : out std_logic; -- transceiver PMA reset signal
mmcm_locked_out : out std_logic; -- MMCM Locked
independent_clock_bufg : in std_logic;
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic;
sgmii_clk_f : out std_logic;
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: Alternative to MDIO Interface
--------------------------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_pll0outclk_out : out std_logic;
gt0_pll0outrefclk_out : out std_logic;
gt0_pll1outclk_out : out std_logic;
gt0_pll1outrefclk_out : out std_logic;
gt0_pll0refclklost_out : out std_logic;
gt0_pll0lock_out : out std_logic);
end component;
-- 13
component UDP_Complete_nomac
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic); -- indicates last byte of the trame
end component;
-- 14
component temac_10_100_1000_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Configuration Vector
-------------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0));
end component;
-- 15
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic); -- "Synchronised" reset signal
end component;
-- 16
component temac_10_100_1000_config_vector_sm is
port(
gtx_clk : in std_logic;
gtx_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
rx_configuration_vector : out std_logic_vector(79 downto 0);
tx_configuration_vector : out std_logic_vector(79 downto 0));
end component;
-- 17
component i2c_top is
port(
clk_in : in std_logic;
phy_rstn_out : out std_logic
-- SCL_out : out std_logic;
-- SDA_inout : inout std_logic
);
end component;
-- 18
component config_logic is
Port (
clk125 : in std_logic;
clk200 : in std_logic;
clk_in : in std_logic;
reset : in std_logic;
user_data_in : in std_logic_vector (7 downto 0);
user_data_out : out std_logic_vector (63 downto 0);
-- user_sn_out : out std_logic_vector (31 downto 0);
udp_rx : in udp_rx_type;
resp_data : out udp_response;
send_error : out std_logic;
user_conf : out std_logic;
user_wr_en : in std_logic;
user_last : in std_logic;
configuring : in std_logic;
we_conf : out std_logic;
conf_packet_length : out integer;
vmm_id : out std_logic_vector(15 downto 0);
cfg_bit_out : out std_logic ;
vmm_cktk : out std_logic ;
status : out std_logic_vector(3 downto 0);
start_vmm_conf : in std_logic;
conf_done : out std_logic;
ext_trigger : out std_logic;
ACQ_sync : out std_logic_vector(15 downto 0);
-- vmm_we : in std_logic;
udp_header : in std_logic;
packet_length : in std_logic_vector (15 downto 0));
end component;
-- 21
component select_data
port(
clk_in : in std_logic;
configuring : in std_logic;
data_acq : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
daq_data_in : in std_logic_vector(63 downto 0);
conf_data_in : in std_logic_vector(63 downto 0);
data_packet_length : in integer;
conf_packet_length : in integer;
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
data_out : out std_logic_vector(63 downto 0);
packet_length : out integer;
we : out std_logic;
end_packet : out std_logic
);
end component;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
begin
-- glbl_rst_i <= '0';
glbl_rstn <= not glbl_rst_i;
phy_int <= '1';
gen_vector_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if vector_reset_int = '1' then
vector_pre_resetn <= '0';
vector_resetn <= '0';
else
vector_pre_resetn <= '1';
vector_resetn <= vector_pre_resetn;
end if;
end if;
end process gen_vector_reset;
mmcm_reset <= glbl_rst_i; -- reset;
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(glbl_rst_i, clk_200)
begin
if (glbl_rst_i = '1') then
pma_reset_pipe <= "1111";
elsif clk_200'event and clk_200 = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & glbl_rst_i;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
core_wrapper: gig_ethernet_pcs_pma_0
-- generic map ( EXAMPLE_SIMULATION => 0)
port map (
gtrefclk_p => gtrefclk_p,
gtrefclk_n => gtrefclk_n,
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
gtrefclk_out => open,
gtrefclk_bufg_out => txoutclk,
rxuserclk_out => open,
rxuserclk2_out => open,
-- txoutclk => txoutclk,
resetdone => resetdone,
mmcm_locked_out => mmcm_locked,
userclk_out => userclk,
userclk2_out => userclk2,
independent_clock_bufg => clk_200,
pma_reset_out => pma_reset,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => clk_enable_int,
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => "10000", -- configuration_vector,
status_vector => status_vector_int, -- status_vector_int,
reset => glbl_rst_i,
signal_detect => '1', -- signal_detect
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
an_interrupt => open, -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector => "1111111000000001",-- Alternate interface to program REG4 (AN ADV)
an_restart_config => an_restart_config_int, -- Alternate signal to modify AN restart bit in REG0
gt0_pll0outclk_out => open,
gt0_pll0outrefclk_out => open,
gt0_pll1outclk_out => open,
gt0_pll1outrefclk_out => open,
gt0_pll0refclklost_out => open,
gt0_pll0lock_out => open);
process(userclk2)
begin
if (local_gtx_reset = '1') then
an_restart_config_int <= '1';
else
an_restart_config_int <= '0';
end if;
end process;
tri_fifo: temac_10_100_1000_fifo_block
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Receiver Statistics Interface
-----------------------------------------
rx_reset => rx_reset,
rx_statistics_vector => open,
rx_statistics_valid => open,
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock => userclk2,
rx_fifo_resetn => gtx_resetn,
rx_axis_fifo_tdata => rx_axis_mac_tdata_int,
rx_axis_fifo_tvalid => rx_axis_mac_tvalid_int,
rx_axis_fifo_tready => rx_axis_mac_tready_int,
rx_axis_fifo_tlast => rx_axis_mac_tlast_int,
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset => tx_reset,
tx_ifg_delay => x"00",
tx_statistics_vector => open,
tx_statistics_valid => open,
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock => userclk2,
tx_fifo_resetn => gtx_resetn,
tx_axis_fifo_tdata => tx_axis_mac_tdata_int,
tx_axis_fifo_tvalid => tx_axis_mac_tvalid_int,
tx_axis_fifo_tready => tx_axis_mac_tready_int,
tx_axis_fifo_tlast => tx_axis_mac_tlast_int,
-- MAC Control Interface
--------------------------
pause_req => '0',
pause_val => x"0000",
-- GMII Interface
-------------------
gmii_txd => gmii_txd_emac,
gmii_tx_en => gmii_tx_en_emac,
gmii_tx_er => gmii_tx_er_emac,
gmii_rxd => gmii_rxd_emac,
gmii_rx_dv => gmii_rx_dv_emac,
gmii_rx_er => gmii_rx_er_emac,
clk_enable => clk_enable_int,
speedis100 => speed_is_100,
speedis10100 => speed_is_10_100,
-- Configuration Vector
-------------------------
rx_configuration_vector => rx_configuration_vector_int, -- x"0605_0403_02da_0000_2022",
tx_configuration_vector => tx_configuration_vector_int); -- x"0605_0403_02da_0000_2022"
-- Control vector reset
axi_lite_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => glbl_rst_i,
reset_out => vector_reset_int);
config_vector: temac_10_100_1000_config_vector_sm
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
gtx_resetn => vector_resetn,
mac_speed => status_vector_int(11 downto 10), -- "10",
update_speed => '1',
rx_configuration_vector => rx_configuration_vector_int,
tx_configuration_vector => tx_configuration_vector_int);
-----------------------------------------------------------------------------
-- GMII transmitter data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB input flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_txd_int <= gmii_txd_emac;
gmii_tx_en_int <= gmii_tx_en_emac;
gmii_tx_er_int <= gmii_tx_er_emac;
end if;
end process;
local_gtx_reset <= glbl_rst_i or rx_reset or tx_reset;
gtx_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => local_gtx_reset,
reset_out => gtx_clk_reset_int);
gen_gtx_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if gtx_clk_reset_int = '1' then
gtx_pre_resetn <= '0';
gtx_resetn <= '0';
else
gtx_pre_resetn <= '1';
gtx_resetn <= gtx_pre_resetn;
end if;
end if;
end process gen_gtx_reset;
-- Drive input GMII signals through IOB output flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_rxd_emac <= gmii_rxd_int;
gmii_rx_dv_emac <= gmii_rx_dv_int;
gmii_rx_er_emac <= gmii_rx_er_int;
end if;
end process;
UDP_block: UDP_Complete_nomac
Port map(
udp_tx_start => udp_tx_start_int,
udp_txi => udp_txi_int,
udp_tx_result => open,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
udp_rx_start => udp_header_int, -- indicates receipt of udp header
udp_rxo => udp_rx_int,
ip_rx_hdr => ip_rx_hdr_int,
rx_clk => userclk2,
tx_clk => userclk2,
reset => glbl_rst_i,
our_ip_address => myIP,
our_mac_address => myMAC,
control => control,
arp_pkt_count => open,
ip_pkt_count => open,
mac_tx_tdata => tx_axis_mac_tdata_int,
mac_tx_tvalid => tx_axis_mac_tvalid_int,
mac_tx_tready => tx_axis_mac_tready_int,
mac_tx_tfirst => open,
mac_tx_tlast => tx_axis_mac_tlast_int,
mac_rx_tdata => rx_axis_mac_tdata_int,
mac_rx_tvalid => rx_axis_mac_tvalid_int,
mac_rx_tready => rx_axis_mac_tready_int,
mac_rx_tlast => rx_axis_mac_tlast_int);
i2c_module: i2c_top
port map( clk_in => clk_200,
phy_rstn_out => phy_rstn_out);
configuration_logic: config_logic
Port map(
clk125 => userclk2,
clk200 => clk_200,
clk_in => clk_40,
reset => reset,
user_data_in => udp_rx_int.data.data_in,
user_data_out => conf_data_out_i,
udp_rx => udp_rx_int,
resp_data => udp_response_int,
send_error => send_error_int,
user_conf => user_conf_i,
user_wr_en => udp_rx_int.data.data_in_valid,
user_last => udp_rx_int.data.data_in_last,
configuring => '0', --configuring_i,
we_conf => open, --we_conf_int,
conf_packet_length => conf_packet_length_int,
vmm_id => vmm_id,
cfg_bit_out => conf_di_i,
status => status_int,
start_vmm_conf => conf_wen_i, --start_conf_proc_int, --configuring_i,
conf_done => conf_done_int,
ext_trigger => trig_mode_int,
ACQ_sync => ACQ_sync_int,
udp_header => udp_header_int,
vmm_cktk => conf_cktk_out_i,
packet_length => udp_rx_int.hdr.data_length);
clk_200_to_400_inst: clk_wiz_200_to_400
port map(
clk_in1_p => X_2V5_DIFF_CLK_P,
clk_in1_n => X_2V5_DIFF_CLK_N,
clk_out_400 => clk_400_noclean
);
clk_400_low_jitter_inst: clk_wiz_low_jitter
port map(
clk_in1 => clk_400_noclean,
clk_out1 => clk_400_clean
);
clk_user_inst: clk_wiz_0
port map(
clk_in1 => clk_400_clean,
reset => '0',
clk_200_o => clk_200,
clk_800_o => clk_800,
clk_10_phase45_o => clk_10_phase45,
clk_50_o => clk_50,
clk_40_o => clk_40,
clk_10_o => clk_10
);
vmm_global_reset_inst: vmm_global_reset
port map(
clk => clk_200, -- main clock
rst => reset, -- reset
gbl_rst => gbl_rst, -- input
vmm_ena => vmm_ena_gbl_rst, --
vmm_wen => vmm_wen_gbl_rst --
);
event_timing_reset_instance: event_timing_reset
port map(
hp_clk => clk_800,
bc_clk => clk_10,
trigger => tr_out_i,
readout_done => '0',
reset => '0',
bcid => open,
prec_cnt => open,
vmm_ena => open,
vmm_wen => open
);
readout_vmm: vmm_readout
port map(
vmm_data0 => vmm_data0_5,
vmm_data1 => vmm_data1_5,
clk_10_phase45 => clk_10_phase45,
clk_50 => clk_50,
clk_200 => clk_200,
daq_enable => daq_enable_i,
trigger_pulse => pf_trigVmmRo,
ethernet_fifo_wr_en => open,
latency => ACQ_sync_int,
vmm_ckdt => ckdt_out_vec(5),
vmm_cktk => ro_cktk_5,
acq_rst_from_data0 => open,
vmm_data_buf => open,
vmm_wen => ro_vmm_wen_5,
vmm_ena => ro_vmm_ena_5,
vmmWordReady => vmmWordReady_i,
vmmWord => vmmWord_i,
vmmEventDone => vmmEventDone_i
);
trigger_instance: trigger
port map(
clk_200 => clk_200,
tren => tren, -- Trigger module enabled
tr_hold => tr_hold, -- Prevents trigger while high
trmode => trig_mode_int, -- Mode 0: internal / Mode 1: external
trext => ext_trigger_in, -- External trigger is to be driven to this port
trint => trint, -- Internal trigger is to be driven to this port (CKTP)
reset => tr_reset,
event_counter => event_counter_i,
tr_out => tr_out_i
);
pf_newCycle <= tr_out_i;
select_vmm_block: select_vmm
Port map (
clk_in => clk_200,
vmm_id => vmm_id_int,
conf_di => conf_di_i,
conf_di_vec => vmm_di_vec_i,
conf_do => conf_do_i,
conf_do_vec => vmm_do_vec_i,
cktk_out => cktk_out_i,
cktk_out_vec => cktk_out_vec_i,
conf_wen => vmm_wen_i,
conf_wen_vec => vmm_wen_vec,
conf_ena => vmm_ena_i,
conf_ena_vec => vmm_ena_vec
);
FIFO2UDP_instance: FIFO2UDP
Port map(
clk_200 => clk_200,
clk_125 => userclk2,
daq_data_in => daqFIFO_din_i,
fifo_data_out => fifo_data_out_int,
udp_txi => udp_txi_int,
udp_tx_start => udp_tx_start_int,
control => control.ip_controls.arp_controls.clear_cache,
re_out => re_out_int,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
wr_en => daqFIFO_wr_en_i,
end_packet => end_packet_i,
global_reset => glbl_rst_i,
packet_length_in => packet_length_int,
reset_DAQ_FIFO => daqFIFO_reset,
sending_o => udp_busy
);
packet_formation_instance: packet_formation
port map(
clk_200 => clk_200,
newCycle => pf_newCycle,
eventCounter => event_counter_i,
trigVmmRo => pf_trigVmmRo,
vmmWord => vmmWord_i,
vmmWordReady => vmmWordReady_i,
vmmEventDone => vmmEventDone_i,
packLen => pf_packLen,
dataout => daq_data_out_i,
wrenable => daq_wr_en_i,
end_packet => end_packet_daq_int,
udp_busy => udp_busy,
tr_hold => tr_hold
);
data_selection: select_data
port map(
clk_in => clk_200,
configuring => start_conf_proc_int,
data_acq => daq_vmm_ena_enable,
we_data => daq_wr_en_i,
we_conf => we_conf_int,
daq_data_in => daq_data_out_i,
conf_data_in => user_data_out_i,
data_packet_length => pf_packLen,
conf_packet_length => conf_packet_length_int,
data_out => daqFIFO_din_i,
packet_length => packet_length_int,
end_packet_conf => end_packet_conf_int,
end_packet_daq => end_packet_daq_int,
we => daqFIFO_wr_en_i,
end_packet => end_packet_i
);
----------------------------------------------------SET ENA--------------------------------------------------------------
vmm_ena_i <= conf_ena_i or (ro_vmm_ena_5 and daq_vmm_ena_enable);
ena_diff_1 : OBUFDS port map ( O => ENA_1_P, OB => ENA_1_N, I => vmm_ena_vec(1));
ena_diff_2 : OBUFDS port map ( O => ENA_2_P, OB => ENA_2_N, I => vmm_ena_vec(2));
ena_diff_3 : OBUFDS port map ( O => ENA_3_P, OB => ENA_3_N, I => vmm_ena_vec(3));
ena_diff_4 : OBUFDS port map ( O => ENA_4_P, OB => ENA_4_N, I => vmm_ena_vec(4));
ena_diff_5 : OBUFDS port map ( O => ENA_5_P, OB => ENA_5_N, I => vmm_ena_vec(5));
ena_diff_6 : OBUFDS port map ( O => ENA_6_P, OB => ENA_6_N, I => vmm_ena_vec(6));
ena_diff_7 : OBUFDS port map ( O => ENA_7_P, OB => ENA_7_N, I => vmm_ena_vec(7));
ena_diff_8 : OBUFDS port map ( O => ENA_8_P, OB => ENA_8_N, I => vmm_ena_vec(8));
----------------------------------------------------SET WEN--------------------------------------------------------------
vmm_wen_i <= conf_wen_i or (ro_vmm_wen_5 and daq_vmm_wen_enable);
wen_diff_1 : OBUFDS port map ( O => WEN_1_P, OB => WEN_1_N, I => vmm_wen_vec(1));
wen_diff_2 : OBUFDS port map ( O => WEN_2_P, OB => WEN_2_N, I => vmm_wen_vec(2));
wen_diff_3 : OBUFDS port map ( O => WEN_3_P, OB => WEN_3_N, I => vmm_wen_vec(3));
wen_diff_4 : OBUFDS port map ( O => WEN_4_P, OB => WEN_4_N, I => vmm_wen_vec(4));
wen_diff_5 : OBUFDS port map ( O => WEN_5_P, OB => WEN_5_N, I => vmm_wen_vec(5));
wen_diff_6 : OBUFDS port map ( O => WEN_6_P, OB => WEN_6_N, I => vmm_wen_vec(6));
wen_diff_7 : OBUFDS port map ( O => WEN_7_P, OB => WEN_7_N, I => vmm_wen_vec(7));
wen_diff_8 : OBUFDS port map ( O => WEN_8_P, OB => WEN_8_N, I => vmm_wen_vec(8));
----------------------------------------------------SET DI--------------------------------------------------------------
di_diff_1 : OBUFDS port map ( O => DI_1_P, OB => DI_1_N, I => vmm_di_vec_i(1));
di_diff_2 : OBUFDS port map ( O => DI_2_P, OB => DI_2_N, I => vmm_di_vec_i(2));
di_diff_3 : OBUFDS port map ( O => DI_3_P, OB => DI_3_N, I => vmm_di_vec_i(3));
di_diff_4 : OBUFDS port map ( O => DI_4_P, OB => DI_4_N, I => vmm_di_vec_i(4));
di_diff_5 : OBUFDS port map ( O => DI_5_P, OB => DI_5_N, I => vmm_di_vec_i(5));
di_diff_6 : OBUFDS port map ( O => DI_6_P, OB => DI_6_N, I => vmm_di_vec_i(6));
di_diff_7 : OBUFDS port map ( O => DI_7_P, OB => DI_7_N, I => vmm_di_vec_i(7));
di_diff_8 : OBUFDS port map ( O => DI_8_P, OB => DI_8_N, I => vmm_di_vec_i(8));
----------------------------------------------------SET CKBC--------------------------------------------------------------
vmm_ckbc <= clk_10;
ckbc_diff_1 : OBUFDS port map ( O => CKBC_1_P, OB => CKBC_1_N, I => vmm_ckbc);
ckbc_diff_2 : OBUFDS port map ( O => CKBC_2_P, OB => CKBC_2_N, I => vmm_ckbc);
ckbc_diff_3 : OBUFDS port map ( O => CKBC_3_P, OB => CKBC_3_N, I => vmm_ckbc);
ckbc_diff_4 : OBUFDS port map ( O => CKBC_4_P, OB => CKBC_4_N, I => vmm_ckbc);
ckbc_diff_5 : OBUFDS port map ( O => CKBC_5_P, OB => CKBC_5_N, I => vmm_ckbc);
ckbc_diff_6 : OBUFDS port map ( O => CKBC_6_P, OB => CKBC_6_N, I => vmm_ckbc);
ckbc_diff_7 : OBUFDS port map ( O => CKBC_7_P, OB => CKBC_7_N, I => vmm_ckbc);
ckbc_diff_8 : OBUFDS port map ( O => CKBC_8_P, OB => CKBC_8_N, I => vmm_ckbc);
----------------------------------------------------SET CKTK--------------------------------------------------------------
cktk_out_i <= conf_cktk_out_i or ro_cktk_5;
cktk_diff_1 : OBUFDS port map ( O => CKTK_1_P, OB => CKTK_1_N, I => cktk_out_vec_i(1));
cktk_diff_2 : OBUFDS port map ( O => CKTK_2_P, OB => CKTK_2_N, I => cktk_out_vec_i(2));
cktk_diff_3 : OBUFDS port map ( O => CKTK_3_P, OB => CKTK_3_N, I => cktk_out_vec_i(3));
cktk_diff_4 : OBUFDS port map ( O => CKTK_4_P, OB => CKTK_4_N, I => cktk_out_vec_i(4));
cktk_diff_5 : OBUFDS port map ( O => CKTK_5_P, OB => CKTK_5_N, I => cktk_out_vec_i(5));
cktk_diff_6 : OBUFDS port map ( O => CKTK_6_P, OB => CKTK_6_N, I => cktk_out_vec_i(6));
cktk_diff_7 : OBUFDS port map ( O => CKTK_7_P, OB => CKTK_7_N, I => cktk_out_vec_i(7));
cktk_diff_8 : OBUFDS port map ( O => CKTK_8_P, OB => CKTK_8_N, I => cktk_out_vec_i(8));
----------------------------------------------------SET CKTP--------------------------------------------------------------
cktp_diff_1 : OBUFDS port map ( O => CKTP_1_P, OB => CKTP_1_N, I => vmm_cktp);
cktp_diff_2 : OBUFDS port map ( O => CKTP_2_P, OB => CKTP_2_N, I => vmm_cktp);
cktp_diff_3 : OBUFDS port map ( O => CKTP_3_P, OB => CKTP_3_N, I => vmm_cktp);
cktp_diff_4 : OBUFDS port map ( O => CKTP_4_P, OB => CKTP_4_N, I => vmm_cktp);
cktp_diff_5 : OBUFDS port map ( O => CKTP_5_P, OB => CKTP_5_N, I => vmm_cktp);
cktp_diff_6 : OBUFDS port map ( O => CKTP_6_P, OB => CKTP_6_N, I => vmm_cktp);
cktp_diff_7 : OBUFDS port map ( O => CKTP_7_P, OB => CKTP_7_N, I => vmm_cktp);
cktp_diff_8 : OBUFDS port map ( O => CKTP_8_P, OB => CKTP_8_N, I => vmm_cktp);
----------------------------------------------------SET CKDT--------------------------------------------------------------
ckdt_diff_1 : OBUFDS port map ( O => ckdt_1_P, OB => ckdt_1_N, I => ckdt_out_vec(1));
ckdt_diff_2 : OBUFDS port map ( O => ckdt_2_P, OB => ckdt_2_N, I => ckdt_out_vec(2));
ckdt_diff_3 : OBUFDS port map ( O => ckdt_3_P, OB => ckdt_3_N, I => ckdt_out_vec(3));
ckdt_diff_4 : OBUFDS port map ( O => ckdt_4_P, OB => ckdt_4_N, I => ckdt_out_vec(4));
ckdt_diff_5 : OBUFDS port map ( O => ckdt_5_P, OB => ckdt_5_N, I => ckdt_out_vec(5));
ckdt_diff_6 : OBUFDS port map ( O => ckdt_6_P, OB => ckdt_6_N, I => ckdt_out_vec(6));
ckdt_diff_7 : OBUFDS port map ( O => ckdt_7_P, OB => ckdt_7_N, I => ckdt_out_vec(7));
ckdt_diff_8 : OBUFDS port map ( O => ckdt_8_P, OB => ckdt_8_N, I => ckdt_out_vec(8));
----------------------------------------------------DO--------------------------------------------------------------
do_diff_1 : IBUFDS port map ( O => vmm_do_1, I => DO_1_P, IB => DO_1_N);
do_diff_2 : IBUFDS port map ( O => vmm_do_2, I => DO_2_P, IB => DO_2_N);
do_diff_3 : IBUFDS port map ( O => vmm_do_3, I => DO_3_P, IB => DO_3_N);
do_diff_4 : IBUFDS port map ( O => vmm_do_4, I => DO_4_P, IB => DO_4_N);
do_diff_5 : IBUFDS port map ( O => vmm_do_5, I => DO_5_P, IB => DO_5_N);
do_diff_6 : IBUFDS port map ( O => vmm_do_6, I => DO_6_P, IB => DO_6_N);
do_diff_7 : IBUFDS port map ( O => vmm_do_7, I => DO_7_P, IB => DO_7_N);
do_diff_8 : IBUFDS port map ( O => vmm_do_8, I => DO_8_P, IB => DO_8_N);
----------------------------------------------------DATA 0--------------------------------------------------------------
data0_diff_1 : IBUFDS port map ( O => vmm_data0_1, I => DATA0_1_P, IB => DATA0_1_N);
data0_diff_2 : IBUFDS port map ( O => vmm_data0_2, I => DATA0_2_P, IB => DATA0_2_N);
data0_diff_3 : IBUFDS port map ( O => vmm_data0_3, I => DATA0_3_P, IB => DATA0_3_N);
data0_diff_4 : IBUFDS port map ( O => vmm_data0_4, I => DATA0_4_P, IB => DATA0_4_N);
data0_diff_5 : IBUFDS port map ( O => vmm_data0_5, I => DATA0_5_P, IB => DATA0_5_N);
data0_diff_6 : IBUFDS port map ( O => vmm_data0_6, I => DATA0_6_P, IB => DATA0_6_N);
data0_diff_7 : IBUFDS port map ( O => vmm_data0_7, I => DATA0_7_P, IB => DATA0_7_N);
data0_diff_8 : IBUFDS port map ( O => vmm_data0_8, I => DATA0_8_P, IB => DATA0_8_N);
----------------------------------------------------DATA 1--------------------------------------------------------------
data1_diff_1 : IBUFDS port map ( O => vmm_data1_1, I => DATA1_1_P, IB => DATA1_1_N);
data1_diff_2 : IBUFDS port map ( O => vmm_data1_2, I => DATA1_2_P, IB => DATA1_2_N);
data1_diff_3 : IBUFDS port map ( O => vmm_data1_3, I => DATA1_3_P, IB => DATA1_3_N);
data1_diff_4 : IBUFDS port map ( O => vmm_data1_4, I => DATA1_4_P, IB => DATA1_4_N);
data1_diff_5 : IBUFDS port map ( O => vmm_data1_5, I => DATA1_5_P, IB => DATA1_5_N);
data1_diff_6 : IBUFDS port map ( O => vmm_data1_6, I => DATA1_6_P, IB => DATA1_6_N);
data1_diff_7 : IBUFDS port map ( O => vmm_data1_7, I => DATA1_7_P, IB => DATA1_7_N);
data1_diff_8 : IBUFDS port map ( O => vmm_data1_8, I => DATA1_8_P, IB => DATA1_8_N);
---------------------------------------------------TRIGGERS--------------------------------------------------------------
ext_trigger : IBUFDS port map ( O => ext_trigger_in, I => EXT_TRIGGER_P, IB => EXT_TRIGGER_N);
-------------------------------------------------------------------
-- Processes --
-------------------------------------------------------------------
-- 1. internalTrigger_proc
-- 2. testPulse_proc
-- 3. synced_to_200
-- 4. FPGA_global_reset
-- 5. flow_fsm
-------------------------------------------------------------------
internalTrigger_proc: process(clk_10_phase45) -- 10MHz/#states.
begin
if rising_edge(clk_10_phase45) then
if state = DAQ and trig_mode_int = '0' then
case internalTrigger_state is
when 0 to 9979 =>
internalTrigger_state <= internalTrigger_state + 1;
trint <= '0';
when 9980 to 10000 =>
internalTrigger_state <= internalTrigger_state + 1;
trint <= '1';
when others =>
internalTrigger_state <= 0;
end case;
else
trint <= '0';
end if;
end if;
end process;
testPulse_proc: process(clk_10_phase45) -- 10MHz/#states.
begin
if rising_edge(clk_10_phase45) then
if state = DAQ and trig_mode_int = '0' then
case cktp_state is
when 0 to 9979 =>
cktp_state <= cktp_state + 1;
vmm_cktp <= '0';
when 9980 to 10000 =>
cktp_state <= cktp_state + 1;
vmm_cktp <= '1';
when others =>
cktp_state <= 0;
end case;
else
vmm_cktp <= '0';
end if;
end if;
end process;
synced_to_200: process(clk_200)
begin
if rising_edge(clk_200) then
status_int_old <= status_int;
if status_int_old = status_int then
status_int_synced <= status_int_old;
end if;
vmm_id_old <= vmm_id;
if vmm_id_old = vmm_id then
vmm_id_synced <= vmm_id_old;
end if;
conf_done_int_synced <= conf_done_int;
end if;
end process;
FPGA_global_reset: process(clk_200, status_int_synced)
begin
if rising_edge(clk_200) then
if status_int_synced = "0011" then
glbl_rst_i <= '1';
else
glbl_rst_i <= '0';
end if;
end if;
end process;
flow_fsm: process(clk_200, counter, status_int, status_int_synced, state, vmm_id, write_done_i, conf_done_i, reading_i)
begin
if rising_edge(clk_200) then
if glbl_rst_i = '1' then
state <= IDLE;
elsif is_state = "0000" then
state <= IDLE;
else
case state is
when IDLE =>
is_state <= "1111";
configuring_i <= '0';
daq_vmm_ena_enable <= '0';
daq_vmm_wen_enable <= '0';
daqFIFO_reset <= '0';
tren <= '0';
conf_wen_i <= '0';
conf_ena_i <= '0';
we_conf_int <= '0';
end_packet_conf_int <= '0';
start_conf_proc_int <= '0';
if status_int_synced = "0010" then
cnt_vmm <= 8;
vmm_id_int <= std_logic_vector(to_unsigned(cnt_vmm, vmm_id_int'length));
state <= CONFIGURE;
elsif status_int_synced = "0001" then
cnt_vmm <= 1;
vmm_id_int <= vmm_id_synced;
state <= CONFIGURE;
elsif status_int_synced = "1111" then
state <= DAQ_INIT;
end if;
when CONFIGURE =>
is_state <= "0001";
if status_int_synced = "1011" then
state <= CONF_DONE;
end if;
configuring_i <= '1';
conf_wen_i <= '1';
start_conf_proc_int <= '1';
when CONF_DONE =>
is_state <= "0010";
if w = 40 then
cnt_vmm <= cnt_vmm - 1;
if cnt_vmm = 1 then --1 VMM conf done
state <= SEND_CONF_REPLY;
we_conf_int <= '1';
else
state <= CONFIGURE after 100ns;
end if;
w <= 0;
else
w <= w + 1;
end if;
conf_wen_i <= '0';
when SEND_CONF_REPLY =>
is_state <= "1010";
if cnt_reply = 0 then
user_data_out_i <= conf_data_out_i;
cnt_reply <= cnt_reply + 1;
elsif cnt_reply = 1 then
user_data_out_i <= (others => '0');
cnt_reply <= cnt_reply + 1;
end_packet_conf_int <= '1';
we_conf_int <= '0';
elsif cnt_reply > 1 and cnt_reply < 100 then
cnt_reply <= cnt_reply + 1;
else
cnt_reply <= 0;
state <= IDLE;
end_packet_conf_int <= '1';
end if;
when DAQ_INIT =>
is_state <= "0011";
tren <= '0';
daq_vmm_ena_enable <= '1';
daq_vmm_wen_enable <= '1';
daqFIFO_reset <= '1';
if status_int_synced = "0000" or status_int_synced = "1000" then
daq_vmm_ena_enable <= '0';
daq_vmm_wen_enable <= '0';
state <= IDLE;
else
state <= TRIG;
end if;
when TRIG =>
is_state <= "0100";
daqFIFO_reset <= '0';
tren <= '1';
daq_enable_i <= '1';
state <= DAQ;
when DAQ =>
is_state <= "0101";
if status_int_synced = "1000" then -- Reset came
daq_enable_i <= '0';
state <= DAQ_INIT;
end if;
when others =>
state <= IDLE;
is_state <= "0110";
end case;
end if;
end if;
end process;
test_data <= udp_rx_int.data.data_in;
test_valid <= udp_rx_int.data.data_in_valid;
test_last <= udp_rx_int.data.data_in_last;
test_data_out <= udp_txi_int.data.data_out;
test_valid_out <= udp_txi_int.data.data_out_valid;
test_last_out <= udp_txi_int.data.data_out_last;
fifo_data <= fifo_data_out_int;
re_out <= re_out_int;
end Behavioral; |
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
use work.methods_pkg.all;
use work.string_methods_pkg.all;
package data_queue_pkg is
-- Declaration of storage
subtype t_data_buffer is std_logic_vector(C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1 downto 0);
shared variable shared_data_buffer : t_data_buffer;
type t_buffer_natural_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of natural;
type t_buffer_boolean_array is array (C_NUMBER_OF_DATA_BUFFERS-1 downto 0) of boolean;
type t_data_queue is protected
------------------------------------------
-- init_queue
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the queue.
--
-- - Parameters:
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
-- - Returns: The index of the initiated queue (natural).
-- Returns 0 on error.
--
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural;
------------------------------------------
-- init_queue
------------------------------------------
-- This procedure allocates space in the buffer at the given queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be initialized.
-- - queue_size_in_bits (natural) - The size of the queue
-- - scope - Log scope for all alerts/logs
--
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
);
------------------------------------------
-- flush
------------------------------------------
-- This procedure empties the queue given
-- by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be flushed.
--
procedure flush(
queue_idx : natural
);
------------------------------------------
-- push_back
------------------------------------------
-- This procedure pushes data to the end of a queue.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the queue size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure push_back(
queue_idx : natural;
data : std_logic_vector
);
------------------------------------------
-- peek_front
------------------------------------------
-- This function returns the data from the front
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- peek_back
------------------------------------------
-- This function returns the data from the back
-- of the queue without popping it.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the queue size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_back
------------------------------------------
-- This function returns the data from the back
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the back of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- pop_front
------------------------------------------
-- This function returns the data from the front
-- and removes the returned data from the queue.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: The data from the front of the queue (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty queue is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the queue size is allowed
-- but triggers a TB_WARNING.
--
--
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The number of elements occupying the queue (natural).
--
--
impure function get_count(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_count_max
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the buffer given by queue_idx.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the queue (natural).
--
--
impure function get_queue_count_max(
queue_idx : natural
) return natural;
------------------------------------------
-- get_queue_is_full
------------------------------------------
-- This function returns a boolean indicating if the
-- queue is full or not.
--
-- - Parameters:
-- - queue_idx - The index of the queue (natural)
--
-- - Returns: TRUE if queue is full, FALSE if not.
--
--
impure function get_queue_is_full(
queue_idx : natural
) return boolean;
------------------------------------------
-- deallocate_buffer
------------------------------------------
-- This procedure resets the entire std_logic_vector and all
-- variable arrays related to the buffer, effectively removing all queues.
--
-- - Parameters:
-- - dummy - VOID
--
--
procedure deallocate_buffer(
dummy : t_void
);
end protected;
end package data_queue_pkg;
package body data_queue_pkg is
type t_data_queue is protected body
-- Internal variables for the data queue
-- The buffer is one large std_logic_vector of size C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER.
-- There are several queues that can be instantiated in the slv.
-- There is one set of variables per queue.
variable v_queue_initialized : t_buffer_boolean_array := (others => false);
variable v_queue_size_in_bits : t_buffer_natural_array := (others => 0);
variable v_count : t_buffer_natural_array := (others => 0);
-- min_idx/max idx: These variables set the upper and lower limit of each queue in the buffer.
-- This is how the large slv buffer is divided into several smaller queues.
-- After a queue has been instantiated, all queue operations in the buffer
-- for a given idx will happen within the v_min_idx and v_max_idx boundary.
-- These variables will be set when a queue is instantiated, and will not
-- change afterwards.
variable v_min_idx : t_buffer_natural_array := (others => 0);
variable v_max_idx : t_buffer_natural_array := (others => 0);
variable v_next_available_idx : natural := 0; -- Where the v_min_idx of the next queue initialized shall be set.
-- first_idx/last_idx: These variables set the current indices within a queue, i.e., within
-- the min_idx/max_idx boundary. These variables will change every time
-- a given queue has data pushed or popped.
variable v_first_idx : t_buffer_natural_array := (others => 0);
variable v_last_idx : t_buffer_natural_array := (others => 0);
type t_string_pointer is access string;
variable v_scope : t_string_pointer := NULL;
------------------------------------------
-- init_queue
------------------------------------------
impure function init_queue(
queue_size_in_bits : natural;
scope : string := "data_queue"
) return natural is
variable vr_queue_idx : natural;
variable vr_queue_idx_found : boolean := false;
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not check_value(v_next_available_idx < C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER, TB_ERROR,
"init_queue called, but no more space in buffer!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Find first available queue
-- and tag as initialized
for i in t_buffer_boolean_array'range loop
if not v_queue_initialized(i) then
-- Save queue idx
vr_queue_idx := i;
vr_queue_idx_found := true;
-- Tag this queue as initialized
v_queue_initialized(vr_queue_idx) := true;
exit; -- exit loop
end if;
end loop;
-- Verify that an available queue idx was found, else trigger alert and return 0
if not check_value(vr_queue_idx_found, TB_ERROR,
"init_queue called, but all queues have already been initialized!", v_scope.all, ID_NEVER)
then
return 0;
end if;
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(vr_queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(vr_queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(vr_queue_idx) := v_next_available_idx;
v_max_idx(vr_queue_idx) := v_min_idx(vr_queue_idx) + v_queue_size_in_bits(vr_queue_idx) - 1;
v_first_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_last_idx(vr_queue_idx) := v_min_idx(vr_queue_idx);
v_next_available_idx := v_max_idx(vr_queue_idx) + 1;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(vr_queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(vr_queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(vr_queue_idx);
-- Return the index of the buffer
return vr_queue_idx;
end function;
------------------------------------------
-- init_queue
------------------------------------------
procedure init_queue(
queue_idx : natural;
queue_size_in_bits : natural;
scope : string := "data_queue"
) is
begin
if v_scope = NULL then
v_scope := new string'(scope);
end if;
if not v_queue_initialized(queue_idx) then
-- Set buffer size for this buffer to queue_size_in_bits
if queue_size_in_bits <= (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - (v_next_available_idx - 1) then -- less than or equal to the remaining total buffer space available
v_queue_size_in_bits(queue_idx) := queue_size_in_bits;
else
alert(TB_ERROR, "queue_size_in_bits larger than maximum allowed!", v_scope.all);
v_queue_size_in_bits(queue_idx) := (C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER - 1) - v_next_available_idx; -- Set to remaining available bits
end if;
-- Set starting and ending indices for this queue_idx
v_min_idx(queue_idx) := v_next_available_idx;
v_max_idx(queue_idx) := v_min_idx(queue_idx) + v_queue_size_in_bits(queue_idx) - 1;
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_next_available_idx := v_max_idx(queue_idx) + 1;
-- Tag this buffer as initialized
v_queue_initialized(queue_idx) := true;
log(ID_UVVM_DATA_QUEUE, "Queue " & to_string(queue_idx) & " initialized with buffer size " & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
-- Clear the buffer just to be sure
flush(queue_idx);
else
alert(TB_ERROR, "init_queue called, but the desired buffer index is already in use! No action taken.", v_scope.all);
return;
end if;
end procedure;
------------------------------------------
-- push_back
------------------------------------------
procedure push_back(
queue_idx : natural;
data : std_logic_vector
) is
alias a_data : std_logic_vector(data'length - 1 downto 0) is data;
begin
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"push_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
for i in a_data'right to a_data'left loop -- From right to left since LSB shall be first in the queue.
shared_data_buffer(v_last_idx(queue_idx)) := a_data(i);
if v_last_idx(queue_idx) /= v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_last_idx(queue_idx) + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) + 1;
end loop;
log(ID_UVVM_DATA_QUEUE, "Data " & to_string(data, HEX) & " pushed to back of queue " & to_string(queue_idx) & " (index " & to_string(v_last_idx(queue_idx)) & "). Fill level is " & to_string(v_count(queue_idx)) & "/" & to_string(v_queue_size_in_bits(queue_idx)) & ".", v_scope.all);
end if;
end procedure;
------------------------------------------
-- flush
------------------------------------------
procedure flush(
queue_idx : natural
) is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "flush called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
shared_data_buffer(v_max_idx(queue_idx) downto v_min_idx(queue_idx)) := (others => '0');
v_first_idx(queue_idx) := v_min_idx(queue_idx);
v_last_idx(queue_idx) := v_min_idx(queue_idx);
v_count(queue_idx) := 0;
end procedure;
------------------------------------------
-- peek_front
------------------------------------------
impure function peek_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_front() called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_front() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
v_current_idx := v_first_idx(queue_idx);
-- Generate return value
for i in 0 to v_return_entry'length - 1 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- peek_back
------------------------------------------
impure function peek_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits - 1 downto 0) := (others => '0');
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "peek_back called, but queue not initialized.", v_scope.all, ID_NEVER);
check_value(v_count(queue_idx) > 0, TB_WARNING, "peek_back() when queue " & to_string(queue_idx) & " is empty. Return value will be garbage.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "peek_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_last_idx(queue_idx) > 0 then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Generate return value
for i in v_return_entry'length - 1 downto 0 loop
v_return_entry(i) := shared_data_buffer(v_current_idx);
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
end loop;
return v_return_entry;
end function;
------------------------------------------
-- pop_back
------------------------------------------
impure function pop_back(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural;
begin
check_value(v_queue_initialized(queue_idx), TB_ERROR, "pop_back called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_back called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if v_queue_initialized(queue_idx) then
v_return_entry := peek_back(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
if v_last_idx(queue_idx) > v_min_idx(queue_idx) then
v_current_idx := v_last_idx(queue_idx) - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx > v_min_idx(queue_idx) then
v_current_idx := v_current_idx - 1;
else
v_current_idx := v_max_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
-- Set last idx
if v_current_idx < v_max_idx(queue_idx) then
v_last_idx(queue_idx) := v_current_idx + 1;
else
v_last_idx(queue_idx) := v_min_idx(queue_idx);
end if;
end if;
end if;
return v_return_entry;
end function;
------------------------------------------
-- pop_front
------------------------------------------
impure function pop_front(
queue_idx : natural;
entry_size_in_bits : natural
) return std_logic_vector is
variable v_return_entry : std_logic_vector(entry_size_in_bits-1 downto 0);
variable v_current_idx : natural := v_first_idx(queue_idx);
begin
check_value(entry_size_in_bits <= v_queue_size_in_bits(queue_idx), TB_WARNING, "pop_front called, but entry size is larger than buffer size!", v_scope.all, ID_NEVER);
if check_value(v_queue_initialized(queue_idx), TB_ERROR,
"pop_front called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER)
then
v_return_entry := peek_front(queue_idx, entry_size_in_bits);
if v_count(queue_idx) > 0 then
-- v_first_idx points to the idx PREVIOUS to the first element in the buffer.
-- Therefore must correct if at max_idx.
v_current_idx := v_first_idx(queue_idx);
-- Clear fields that belong to the return value
for i in 0 to entry_size_in_bits - 1 loop
shared_data_buffer(v_current_idx) := '0';
if v_current_idx < v_max_idx(queue_idx) then
v_current_idx := v_current_idx + 1;
else
v_current_idx := v_min_idx(queue_idx);
end if;
v_count(queue_idx) := v_count(queue_idx) - 1;
end loop;
v_first_idx(queue_idx) := v_current_idx;
end if;
return v_return_entry;
end if;
v_return_entry := (others => '0');
return v_return_entry;
end function;
------------------------------------------
-- get_count
------------------------------------------
impure function get_count(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_count called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_count(queue_idx);
end function;
------------------------------------------
-- get_queue_count_max
------------------------------------------
impure function get_queue_count_max(
queue_idx : natural
) return natural is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_count_max called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
return v_queue_size_in_bits(queue_idx);
end function;
------------------------------------------
-- get_queue_is_full
------------------------------------------
impure function get_queue_is_full(
queue_idx : natural
) return boolean is
begin
check_value(v_queue_initialized(queue_idx), TB_WARNING, "get_queue_is_full called, but queue " & to_string(queue_idx) & " not initialized.", v_scope.all, ID_NEVER);
if v_count(queue_idx) >= v_queue_size_in_bits(queue_idx) then
return true;
else
return false;
end if;
end function;
------------------------------------------
-- deallocate_buffer
------------------------------------------
procedure deallocate_buffer(
dummy : t_void
) is
begin
shared_data_buffer := (others => '0');
v_queue_initialized := (others => false);
v_queue_size_in_bits := (others => 0);
v_count := (others => 0);
v_min_idx := (others => 0);
v_max_idx := (others => 0);
v_first_idx := (others => 0);
v_last_idx := (others => 0);
v_next_available_idx := 0;
log(ID_UVVM_DATA_QUEUE, "Buffer has been deallocated, i.e., all queues removed.", v_scope.all);
end procedure;
end protected body;
end package body data_queue_pkg;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: dmem_splitter
-- Date:2015-02-28
-- Author: Gideon
-- Description: This module takes the Wishbone alike memory bus and splits it
-- into a 32 bit DRAM bus and an 8-bit IO bus
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
library mblite;
use mblite.core_Pkg.all;
entity dmem_splitter is
generic (
g_tag : std_logic_vector(7 downto 0) := X"AE";
g_support_io : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
dmem_i : out dmem_in_type;
dmem_o : in dmem_out_type;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
io_req : out t_io_req;
io_resp : in t_io_resp );
end entity;
architecture arch of dmem_splitter is
type t_state is (idle, mem_read, mem_write, io_access);
signal state : t_state;
signal mem_req_i : t_mem_req_32 := c_mem_req_32_init;
signal io_req_i : t_io_req;
type t_int4_array is array(natural range <>) of integer range 0 to 3;
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F => 1,2,4,8 byte, 3,C word, F dword
constant c_remain : t_int4_array(0 to 15) := ( 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 3 );
signal remain : integer range 0 to 3;
begin
io_req <= io_req_i;
mem_req <= mem_req_i;
process(state, mem_resp)
begin
dmem_i.ena_i <= '0';
case state is
when idle =>
dmem_i.ena_i <= '1';
when mem_read | io_access =>
dmem_i.ena_i <= '0';
when mem_write =>
-- if mem_resp.rack = '1' then
-- dmem_i.ena_i <= '1';
-- end if;
when others =>
dmem_i.ena_i <= '0';
end case;
end process;
process(clock)
impure function get_next_io_byte(a : unsigned(1 downto 0)) return std_logic_vector is
begin
case a is
when "00" =>
return dmem_o.dat_o(23 downto 16);
when "01" =>
return dmem_o.dat_o(15 downto 8);
when "10" =>
return dmem_o.dat_o(7 downto 0);
when "11" =>
return dmem_o.dat_o(31 downto 24);
when others =>
return "XXXXXXXX";
end case;
end function;
begin
if rising_edge(clock) then
io_req_i.read <= '0';
io_req_i.write <= '0';
case state is
when idle =>
dmem_i.dat_i <= (others => 'X');
if dmem_o.ena_o = '1' then
mem_req_i.address <= unsigned(dmem_o.adr_o(mem_req_i.address'range));
mem_req_i.address(1 downto 0) <= "00";
mem_req_i.byte_en <= dmem_o.sel_o;
mem_req_i.data <= dmem_o.dat_o;
mem_req_i.read_writen <= not dmem_o.we_o;
mem_req_i.tag <= g_tag;
io_req_i.address <= unsigned(dmem_o.adr_o(19 downto 0));
io_req_i.data <= get_next_io_byte("11");
if dmem_o.adr_o(26) = '0' or not g_support_io then
mem_req_i.request <= '1';
if dmem_o.we_o = '1' then
state <= mem_write;
else
state <= mem_read;
end if;
else -- I/O
remain <= c_remain(to_integer(unsigned(dmem_o.sel_o)));
if dmem_o.we_o = '1' then
io_req_i.write <= '1';
else
io_req_i.read <= '1';
end if;
state <= io_access;
end if;
end if;
when mem_read =>
if mem_resp.rack_tag = g_tag then
mem_req_i.request <= '0';
end if;
if mem_resp.dack_tag = g_tag then
dmem_i.dat_i <= mem_resp.data;
state <= idle;
end if;
when mem_write =>
if mem_resp.rack_tag = g_tag then
mem_req_i.request <= '0';
state <= idle;
end if;
when io_access =>
case io_req_i.address(1 downto 0) is
when "00" =>
dmem_i.dat_i(31 downto 24) <= io_resp.data;
when "01" =>
dmem_i.dat_i(23 downto 16) <= io_resp.data;
when "10" =>
dmem_i.dat_i(15 downto 8) <= io_resp.data;
when "11" =>
dmem_i.dat_i(7 downto 0) <= io_resp.data;
when others =>
null;
end case;
if io_resp.ack = '1' then
io_req_i.data <= get_next_io_byte(io_req_i.address(1 downto 0));
if remain = 0 then
state <= idle;
else
remain <= remain - 1;
io_req_i.address(1 downto 0) <= io_req_i.address(1 downto 0) + 1;
if mem_req_i.read_writen = '0' then
io_req_i.write <= '1';
else
io_req_i.read <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
end arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 64 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1,2,3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_normus64;
ARCHITECTURE rtl OF hcc_normus64 IS
type delfracfftype IS ARRAY(2 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delfracff : delfracfftype;
component hcc_cntuspipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntuscomb64
PORT (
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO 64 LOOP
fracff(k) <= '0';
delfracff(1)(k) <= '0';
delfracff(2)(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
delfracff(1)(64 DOWNTO 1) <= fracin;
delfracff(2)(64 DOWNTO 1) <= delfracff(1)(64 DOWNTO 1);
END IF;
END IF;
END PROCESS;
gpa: IF (pipes = 1) GENERATE
ccone: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftcomb64
PORT MAP (inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpb: IF (pipes = 2) GENERATE
cctwo: hcc_cntuscomb64
PORT MAP (frac=>fracin,
count=>count);
countout <= countff; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff,
outbus=>fracout);
END GENERATE;
gpc: IF (pipes = 3) GENERATE
cctwo: hcc_cntuspipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
frac=>fracin,
count=>count);
countout <= count; -- always after 1 clock for pipes 1,2,3
sctwo: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>delfracff(2)(64 DOWNTO 1),shift=>countff,
outbus=>fracout);
END GENERATE;
END rtl;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_t
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:06:43 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../intra.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-conf-c.vhd,v 1.2 2006/01/19 08:50:41 wig Exp $
-- $Date: 2006/01/19 08:50:41 $
-- $Log: ent_t-rtl-conf-c.vhd,v $
-- Revision 1.2 2006/01/19 08:50:41 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_t_rtl_conf / ent_t
--
configuration ent_t_rtl_conf of ent_t is
for rtl
-- Generated Configuration
-- __I_NO_CONFIG_VERILOG --for inst_a : ent_a
-- __I_NO_CONFIG_VERILOG -- use configuration work.ent_a_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
for inst_b : ent_b
use configuration work.ent_b_rtl_conf;
end for;
end for;
end ent_t_rtl_conf;
--
-- End of Generated Configuration ent_t_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out std_logic; -- sop.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
data : out std_logic_vector(24 downto 0); -- data.wire
data_en : in std_logic := '0'; -- data_en.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
eop : out std_logic; -- eop.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GN33BXJAZX is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN33BXJAZX;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNWMX2GCN2;
component alt_dspbuilder_case_statement_GNFTM45DFU is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNFTM45DFU;
component alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in3 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNLGLCKYZ5;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_delay_GNIYBMGPQQ is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNIYBMGPQQ;
component alt_dspbuilder_constant_GNLJWFEWBD is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLJWFEWBD;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_if_statement_GNTVBNRAAT is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNTVBNRAAT;
component alt_dspbuilder_delay_GNNBTO2F3L is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNNBTO2F3L;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNHQFFAUXQ;
component alt_dspbuilder_multiplexer_GN6ODCX3D4 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GN6ODCX3D4;
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
component alt_dspbuilder_cast_GN3ODVPHOL is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN3ODVPHOL;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKDE2NVCC is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKDE2NVCC;
component alt_dspbuilder_cast_GNCCZ56SYK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCCZ56SYK;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal delayenavcc_output_wire : std_logic; -- DelayenaVCC:output -> Delay:ena
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay5enavcc_output_wire : std_logic; -- Delay5enaVCC:output -> Delay5:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [Bus_Conversion1:input, If_Statement7:a, cast29:input, cast32:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Delay:input
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Delay1:input
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Delay2:input
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Delay3:input
signal constant7_output_wire : std_logic_vector(23 downto 0); -- Constant7:output -> Delay5:input
signal if_statement7_true_wire : std_logic; -- If_Statement7:true -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator9:data1]
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator10:data1, Logical_Bit_Operator3:data1, cast34:input]
signal case_statement2_r1_wire : std_logic; -- Case_Statement2:r1 -> Logical_Bit_Operator3:data0
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> [Logical_Bit_Operator4:data0, Logical_Bit_Operator9:data0, cast33:input]
signal case_statement2_r0_wire : std_logic; -- Case_Statement2:r0 -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Logical_Bit_Operator5:data0
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Logical_Bit_Operator5:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Logical_Bit_Operator6:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Logical_Bit_Operator6:data0
signal bus_conversion1_output_wire : std_logic_vector(1 downto 0); -- Bus_Conversion1:output -> Multiplexer:sel
signal delay_output_wire : std_logic_vector(23 downto 0); -- Delay:output -> Multiplexer:in0
signal delay1_output_wire : std_logic_vector(23 downto 0); -- Delay1:output -> Multiplexer:in1
signal delay2_output_wire : std_logic_vector(23 downto 0); -- Delay2:output -> Multiplexer:in2
signal delay3_output_wire : std_logic_vector(23 downto 0); -- Delay3:output -> Multiplexer:in3
signal bus_concatenation_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation:output -> Multiplexer1:sel
signal bus_concatenation1_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation1:output -> Multiplexer2:sel
signal multiplexer2_result_wire : std_logic_vector(24 downto 0); -- Multiplexer2:result -> Multiplexer1:in1
signal constant18_output_wire : std_logic_vector(23 downto 0); -- Constant18:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder2:result -> If_Statement7:c
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> sop_0:input
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> eop_0:input
signal multiplexer1_result_wire : std_logic_vector(24 downto 0); -- Multiplexer1:result -> data_0:input
signal cast29_output_wire : std_logic_vector(15 downto 0); -- cast29:output -> Case_Statement1:input
signal case_statement1_r0_wire : std_logic; -- Case_Statement1:r0 -> cast30:input
signal cast30_output_wire : std_logic_vector(0 downto 0); -- cast30:output -> Bus_Concatenation1:a
signal case_statement1_r1_wire : std_logic; -- Case_Statement1:r1 -> cast31:input
signal cast31_output_wire : std_logic_vector(0 downto 0); -- cast31:output -> Bus_Concatenation1:b
signal cast32_output_wire : std_logic_vector(15 downto 0); -- cast32:output -> Case_Statement2:input
signal cast33_output_wire : std_logic_vector(0 downto 0); -- cast33:output -> Bus_Concatenation:a
signal cast34_output_wire : std_logic_vector(0 downto 0); -- cast34:output -> Bus_Concatenation:b
signal constant16_output_wire : std_logic_vector(15 downto 0); -- Constant16:output -> cast35:input
signal cast35_output_wire : std_logic_vector(23 downto 0); -- cast35:output -> If_Statement7:b
signal constant5_output_wire : std_logic_vector(23 downto 0); -- Constant5:output -> cast36:input
signal cast36_output_wire : std_logic_vector(24 downto 0); -- cast36:output -> Multiplexer1:in0
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> cast37:input
signal cast37_output_wire : std_logic_vector(24 downto 0); -- cast37:output -> Multiplexer1:in2
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> cast38:input
signal cast38_output_wire : std_logic_vector(24 downto 0); -- cast38:output -> Multiplexer2:in0
signal delay5_output_wire : std_logic_vector(23 downto 0); -- Delay5:output -> cast39:input
signal cast39_output_wire : std_logic_vector(24 downto 0); -- cast39:output -> Multiplexer2:in1
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast40:input
signal cast40_output_wire : std_logic_vector(23 downto 0); -- cast40:output -> Pipelined_Adder2:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Case_Statement1:aclr, Case_Statement2:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay5:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Pipelined_Adder2:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation:clock, Case_Statement1:clock, Case_Statement2:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay5:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Pipelined_Adder2:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GN33BXJAZX
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast40_output_wire, -- dataa.wire
datab => constant18_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
case_statement1 : component alt_dspbuilder_case_statement_GNWMX2GCN2
generic map (
number_outputs => 2,
hasDefault => 1,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast29_output_wire, -- input.wire
r0 => case_statement1_r0_wire, -- r0.wire
r1 => case_statement1_r1_wire -- r1.wire
);
case_statement2 : component alt_dspbuilder_case_statement_GNFTM45DFU
generic map (
number_outputs => 2,
hasDefault => 0,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast32_output_wire, -- input.wire
r0 => case_statement2_r0_wire, -- r0.wire
r1 => case_statement2_r1_wire -- r1.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNLGLCKYZ5
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_conversion1_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => delay_output_wire, -- in0.wire
in1 => delay1_output_wire, -- in1.wire
in2 => delay2_output_wire, -- in2.wire
in3 => delay3_output_wire -- in3.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => multiplexer1_result_wire, -- input.wire
output => data -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant7_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant5_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast30_output_wire, -- a.wire
b => cast31_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => logical_bit_operator9_result_wire, -- data0.wire
data1 => logical_bit_operator10_result_wire -- data1.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => logical_bit_operator4_result_wire, -- data0.wire
data1 => logical_bit_operator3_result_wire -- data1.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => case_statement2_r0_wire -- data1.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast33_output_wire, -- a.wire
b => cast34_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => if_statement7_true_wire -- data1.wire
);
constant1 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNIYBMGPQQ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000001111",
width => 24
)
port map (
input => constant1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => delayenavcc_output_wire -- ena.wire
);
delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);
delayenavcc : component alt_dspbuilder_vcc_GN
port map (
output => delayenavcc_output_wire -- output.wire
);
constant16 : component alt_dspbuilder_constant_GNLJWFEWBD
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000011",
width => 16
)
port map (
output => constant16_output_wire -- output.wire
);
constant18 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant18_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => case_statement2_r1_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator6_result_wire, -- input.wire
output => eop -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
if_statement7 : component alt_dspbuilder_if_statement_GNTVBNRAAT
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement7_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast35_output_wire, -- b.wire
c => pipelined_adder2_result_wire -- c.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => constant7_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => delay5enavcc_output_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay5enavcc_output_wire -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak3_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator5_result_wire, -- input.wire
output => sop -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => if_statement7_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNHQFFAUXQ
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 25,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast36_output_wire, -- in0.wire
in1 => multiplexer2_result_wire, -- in1.wire
in2 => cast37_output_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak1_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GN6ODCX3D4
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 25,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation1_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast38_output_wire, -- in0.wire
in1 => cast39_output_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVJUPFOX3
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000000",
width => 24
)
port map (
input => ctrl_pak2_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
cast29 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast29_output_wire -- output.wire
);
cast30 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r0_wire, -- input.wire
output => cast30_output_wire -- output.wire
);
cast31 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r1_wire, -- input.wire
output => cast31_output_wire -- output.wire
);
cast32 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast32_output_wire -- output.wire
);
cast33 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => ctrl_en_0_output_wire, -- input.wire
output => cast33_output_wire -- output.wire
);
cast34 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_en_0_output_wire, -- input.wire
output => cast34_output_wire -- output.wire
);
cast35 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant16_output_wire, -- input.wire
output => cast35_output_wire -- output.wire
);
cast36 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => constant5_output_wire, -- input.wire
output => cast36_output_wire -- output.wire
);
cast37 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplexer_result_wire, -- input.wire
output => cast37_output_wire -- output.wire
);
cast38 : component alt_dspbuilder_cast_GNCCZ56SYK
generic map (
round => 0,
saturate => 0
)
port map (
input => colorbar_0_output_wire, -- input.wire
output => cast38_output_wire -- output.wire
);
cast39 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => cast39_output_wire -- output.wire
);
cast40 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast40_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
|
-- Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:05:29
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
port (
sop : out std_logic; -- sop.wire
pixel_num : in std_logic_vector(47 downto 0) := (others => '0'); -- pixel_num.wire
ctrl_en : in std_logic := '0'; -- ctrl_en.wire
counter : in std_logic_vector(23 downto 0) := (others => '0'); -- counter.wire
ctrl_pak1 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak1.wire
colorbar : in std_logic_vector(23 downto 0) := (others => '0'); -- colorbar.wire
data : out std_logic_vector(24 downto 0); -- data.wire
data_en : in std_logic := '0'; -- data_en.wire
ctrl_pak2 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak2.wire
eop : out std_logic; -- eop.wire
ctrl_pak3 : in std_logic_vector(23 downto 0) := (others => '0'); -- ctrl_pak3.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT;
architecture rtl of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GN33BXJAZX is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN33BXJAZX;
component alt_dspbuilder_pipelined_adder_GNTWZRTG4I is
generic (
width : natural := 0;
pipeline : integer := 0
);
port (
aclr : in std_logic := 'X'; -- clk
add_sub : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cout : out std_logic; -- wire
dataa : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
datab : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
ena : in std_logic := 'X'; -- wire
result : out std_logic_vector(width-1 downto 0); -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_pipelined_adder_GNTWZRTG4I;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_case_statement_GNWMX2GCN2 is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNWMX2GCN2;
component alt_dspbuilder_case_statement_GNFTM45DFU is
generic (
number_outputs : integer := 8;
hasDefault : natural := 0;
pipeline : natural := 0;
width : integer := 8
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
r0 : out std_logic; -- wire
r1 : out std_logic -- wire
);
end component alt_dspbuilder_case_statement_GNFTM45DFU;
component alt_dspbuilder_multiplexer_GNLGLCKYZ5 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(23 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
in3 : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNLGLCKYZ5;
component alt_dspbuilder_port_GNEHYJMBQS is
port (
input : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEHYJMBQS;
component alt_dspbuilder_constant_GNNKZSYI73 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNNKZSYI73;
component alt_dspbuilder_bus_concat_GN6E6AAQPZ is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GN6E6AAQPZ;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_constant_GNZEH3JAKA is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNZEH3JAKA;
component alt_dspbuilder_delay_GNIYBMGPQQ is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNIYBMGPQQ;
component alt_dspbuilder_constant_GNLJWFEWBD is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNLJWFEWBD;
component alt_dspbuilder_constant_GNQJ63TWA6 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNQJ63TWA6;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_if_statement_GNTVBNRAAT is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
c : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNTVBNRAAT;
component alt_dspbuilder_delay_GNNBTO2F3L is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNNBTO2F3L;
component alt_dspbuilder_port_GNUJT4YY5I is
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(47 downto 0) -- wire
);
end component alt_dspbuilder_port_GNUJT4YY5I;
component alt_dspbuilder_multiplexer_GNHQFFAUXQ is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in2 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GNHQFFAUXQ;
component alt_dspbuilder_multiplexer_GN6ODCX3D4 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 8;
pipeline : natural := 0;
number_inputs : natural := 4
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
sel : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
result : out std_logic_vector(24 downto 0); -- wire
ena : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X'; -- wire
in0 : in std_logic_vector(24 downto 0) := (others => 'X'); -- wire
in1 : in std_logic_vector(24 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_multiplexer_GN6ODCX3D4;
component alt_dspbuilder_delay_GNVJUPFOX3 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVJUPFOX3;
component alt_dspbuilder_cast_GN3ODVPHOL is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN3ODVPHOL;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNCPEUNC4M is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCPEUNC4M;
component alt_dspbuilder_cast_GNKDE2NVCC is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKDE2NVCC;
component alt_dspbuilder_cast_GNCCZ56SYK is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(24 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNCCZ56SYK;
component alt_dspbuilder_cast_GNKIWLRTQI is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(47 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNKIWLRTQI;
signal pipelined_adder2user_aclrgnd_output_wire : std_logic; -- Pipelined_Adder2user_aclrGND:output -> Pipelined_Adder2:user_aclr
signal pipelined_adder2enavcc_output_wire : std_logic; -- Pipelined_Adder2enaVCC:output -> Pipelined_Adder2:ena
signal multiplexeruser_aclrgnd_output_wire : std_logic; -- Multiplexeruser_aclrGND:output -> Multiplexer:user_aclr
signal multiplexerenavcc_output_wire : std_logic; -- MultiplexerenaVCC:output -> Multiplexer:ena
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal delayenavcc_output_wire : std_logic; -- DelayenaVCC:output -> Delay:ena
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay5enavcc_output_wire : std_logic; -- Delay5enaVCC:output -> Delay5:ena
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay3enavcc_output_wire : std_logic; -- Delay3enaVCC:output -> Delay3:ena
signal multiplexer1user_aclrgnd_output_wire : std_logic; -- Multiplexer1user_aclrGND:output -> Multiplexer1:user_aclr
signal multiplexer1enavcc_output_wire : std_logic; -- Multiplexer1enaVCC:output -> Multiplexer1:ena
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay1enavcc_output_wire : std_logic; -- Delay1enaVCC:output -> Delay1:ena
signal multiplexer2user_aclrgnd_output_wire : std_logic; -- Multiplexer2user_aclrGND:output -> Multiplexer2:user_aclr
signal multiplexer2enavcc_output_wire : std_logic; -- Multiplexer2enaVCC:output -> Multiplexer2:ena
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal delay2enavcc_output_wire : std_logic; -- Delay2enaVCC:output -> Delay2:ena
signal counter_0_output_wire : std_logic_vector(23 downto 0); -- counter_0:output -> [Bus_Conversion1:input, If_Statement7:a, cast29:input, cast32:input]
signal constant1_output_wire : std_logic_vector(23 downto 0); -- Constant1:output -> Delay:input
signal ctrl_pak1_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak1_0:output -> Delay1:input
signal ctrl_pak2_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak2_0:output -> Delay2:input
signal ctrl_pak3_0_output_wire : std_logic_vector(23 downto 0); -- ctrl_pak3_0:output -> Delay3:input
signal constant7_output_wire : std_logic_vector(23 downto 0); -- Constant7:output -> Delay5:input
signal if_statement7_true_wire : std_logic; -- If_Statement7:true -> [Logical_Bit_Operator10:data0, Logical_Bit_Operator9:data1]
signal data_en_0_output_wire : std_logic; -- data_en_0:output -> [Logical_Bit_Operator10:data1, Logical_Bit_Operator3:data1, cast34:input]
signal case_statement2_r1_wire : std_logic; -- Case_Statement2:r1 -> Logical_Bit_Operator3:data0
signal ctrl_en_0_output_wire : std_logic; -- ctrl_en_0:output -> [Logical_Bit_Operator4:data0, Logical_Bit_Operator9:data0, cast33:input]
signal case_statement2_r0_wire : std_logic; -- Case_Statement2:r0 -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Logical_Bit_Operator5:data0
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Logical_Bit_Operator5:data1
signal logical_bit_operator10_result_wire : std_logic; -- Logical_Bit_Operator10:result -> Logical_Bit_Operator6:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Logical_Bit_Operator6:data0
signal bus_conversion1_output_wire : std_logic_vector(1 downto 0); -- Bus_Conversion1:output -> Multiplexer:sel
signal delay_output_wire : std_logic_vector(23 downto 0); -- Delay:output -> Multiplexer:in0
signal delay1_output_wire : std_logic_vector(23 downto 0); -- Delay1:output -> Multiplexer:in1
signal delay2_output_wire : std_logic_vector(23 downto 0); -- Delay2:output -> Multiplexer:in2
signal delay3_output_wire : std_logic_vector(23 downto 0); -- Delay3:output -> Multiplexer:in3
signal bus_concatenation_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation:output -> Multiplexer1:sel
signal bus_concatenation1_output_wire : std_logic_vector(1 downto 0); -- Bus_Concatenation1:output -> Multiplexer2:sel
signal multiplexer2_result_wire : std_logic_vector(24 downto 0); -- Multiplexer2:result -> Multiplexer1:in1
signal constant18_output_wire : std_logic_vector(23 downto 0); -- Constant18:output -> Pipelined_Adder2:datab
signal pipelined_adder2_result_wire : std_logic_vector(23 downto 0); -- Pipelined_Adder2:result -> If_Statement7:c
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> sop_0:input
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> eop_0:input
signal multiplexer1_result_wire : std_logic_vector(24 downto 0); -- Multiplexer1:result -> data_0:input
signal cast29_output_wire : std_logic_vector(15 downto 0); -- cast29:output -> Case_Statement1:input
signal case_statement1_r0_wire : std_logic; -- Case_Statement1:r0 -> cast30:input
signal cast30_output_wire : std_logic_vector(0 downto 0); -- cast30:output -> Bus_Concatenation1:a
signal case_statement1_r1_wire : std_logic; -- Case_Statement1:r1 -> cast31:input
signal cast31_output_wire : std_logic_vector(0 downto 0); -- cast31:output -> Bus_Concatenation1:b
signal cast32_output_wire : std_logic_vector(15 downto 0); -- cast32:output -> Case_Statement2:input
signal cast33_output_wire : std_logic_vector(0 downto 0); -- cast33:output -> Bus_Concatenation:a
signal cast34_output_wire : std_logic_vector(0 downto 0); -- cast34:output -> Bus_Concatenation:b
signal constant16_output_wire : std_logic_vector(15 downto 0); -- Constant16:output -> cast35:input
signal cast35_output_wire : std_logic_vector(23 downto 0); -- cast35:output -> If_Statement7:b
signal constant5_output_wire : std_logic_vector(23 downto 0); -- Constant5:output -> cast36:input
signal cast36_output_wire : std_logic_vector(24 downto 0); -- cast36:output -> Multiplexer1:in0
signal multiplexer_result_wire : std_logic_vector(23 downto 0); -- Multiplexer:result -> cast37:input
signal cast37_output_wire : std_logic_vector(24 downto 0); -- cast37:output -> Multiplexer1:in2
signal colorbar_0_output_wire : std_logic_vector(23 downto 0); -- colorbar_0:output -> cast38:input
signal cast38_output_wire : std_logic_vector(24 downto 0); -- cast38:output -> Multiplexer2:in0
signal delay5_output_wire : std_logic_vector(23 downto 0); -- Delay5:output -> cast39:input
signal cast39_output_wire : std_logic_vector(24 downto 0); -- cast39:output -> Multiplexer2:in1
signal pixel_num_0_output_wire : std_logic_vector(47 downto 0); -- pixel_num_0:output -> cast40:input
signal cast40_output_wire : std_logic_vector(23 downto 0); -- cast40:output -> Pipelined_Adder2:dataa
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation:aclr, Case_Statement1:aclr, Case_Statement2:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay5:aclr, Delay:aclr, Multiplexer1:aclr, Multiplexer2:aclr, Multiplexer:aclr, Pipelined_Adder2:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation:clock, Case_Statement1:clock, Case_Statement2:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay5:clock, Delay:clock, Multiplexer1:clock, Multiplexer2:clock, Multiplexer:clock, Pipelined_Adder2:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GN33BXJAZX
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
pipelined_adder2 : component alt_dspbuilder_pipelined_adder_GNTWZRTG4I
generic map (
width => 24,
pipeline => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
dataa => cast40_output_wire, -- dataa.wire
datab => constant18_output_wire, -- datab.wire
result => pipelined_adder2_result_wire, -- result.wire
user_aclr => pipelined_adder2user_aclrgnd_output_wire, -- user_aclr.wire
ena => pipelined_adder2enavcc_output_wire -- ena.wire
);
pipelined_adder2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => pipelined_adder2user_aclrgnd_output_wire -- output.wire
);
pipelined_adder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => pipelined_adder2enavcc_output_wire -- output.wire
);
case_statement1 : component alt_dspbuilder_case_statement_GNWMX2GCN2
generic map (
number_outputs => 2,
hasDefault => 1,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast29_output_wire, -- input.wire
r0 => case_statement1_r0_wire, -- r0.wire
r1 => case_statement1_r1_wire -- r1.wire
);
case_statement2 : component alt_dspbuilder_case_statement_GNFTM45DFU
generic map (
number_outputs => 2,
hasDefault => 0,
pipeline => 0,
width => 16
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
input => cast32_output_wire, -- input.wire
r0 => case_statement2_r0_wire, -- r0.wire
r1 => case_statement2_r1_wire -- r1.wire
);
multiplexer : component alt_dspbuilder_multiplexer_GNLGLCKYZ5
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 24,
pipeline => 0,
number_inputs => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_conversion1_output_wire, -- sel.wire
result => multiplexer_result_wire, -- result.wire
ena => multiplexerenavcc_output_wire, -- ena.wire
user_aclr => multiplexeruser_aclrgnd_output_wire, -- user_aclr.wire
in0 => delay_output_wire, -- in0.wire
in1 => delay1_output_wire, -- in1.wire
in2 => delay2_output_wire, -- in2.wire
in3 => delay3_output_wire -- in3.wire
);
multiplexeruser_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexeruser_aclrgnd_output_wire -- output.wire
);
multiplexerenavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexerenavcc_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNEHYJMBQS
port map (
input => multiplexer1_result_wire, -- input.wire
output => data -- output.wire
);
constant7 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant7_output_wire -- output.wire
);
constant5 : component alt_dspbuilder_constant_GNNKZSYI73
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000000",
width => 24
)
port map (
output => constant5_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast30_output_wire, -- a.wire
b => cast31_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => logical_bit_operator9_result_wire, -- data0.wire
data1 => logical_bit_operator10_result_wire -- data1.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => logical_bit_operator4_result_wire, -- data0.wire
data1 => logical_bit_operator3_result_wire -- data1.wire
);
ctrl_pak2_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak2, -- input.wire
output => ctrl_pak2_0_output_wire -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => case_statement2_r0_wire -- data1.wire
);
ctrl_pak3_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak3, -- input.wire
output => ctrl_pak3_0_output_wire -- output.wire
);
bus_concatenation : component alt_dspbuilder_bus_concat_GN6E6AAQPZ
generic map (
widthB => 1,
widthA => 1
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => cast33_output_wire, -- a.wire
b => cast34_output_wire, -- b.wire
output => bus_concatenation_output_wire -- output.wire
);
ctrl_pak1_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => ctrl_pak1, -- input.wire
output => ctrl_pak1_0_output_wire -- output.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => ctrl_en_0_output_wire, -- data0.wire
data1 => if_statement7_true_wire -- data1.wire
);
constant1 : component alt_dspbuilder_constant_GNZEH3JAKA
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000001111",
width => 24
)
port map (
output => constant1_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNIYBMGPQQ
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000001111",
width => 24
)
port map (
input => constant1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => delayenavcc_output_wire -- ena.wire
);
delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);
delayenavcc : component alt_dspbuilder_vcc_GN
port map (
output => delayenavcc_output_wire -- output.wire
);
constant16 : component alt_dspbuilder_constant_GNLJWFEWBD
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "0000000000000011",
width => 16
)
port map (
output => constant16_output_wire -- output.wire
);
constant18 : component alt_dspbuilder_constant_GNQJ63TWA6
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "000000000000000000000100",
width => 24
)
port map (
output => constant18_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => case_statement2_r1_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
eop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator6_result_wire, -- input.wire
output => eop -- output.wire
);
colorbar_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => colorbar, -- input.wire
output => colorbar_0_output_wire -- output.wire
);
if_statement7 : component alt_dspbuilder_if_statement_GNTVBNRAAT
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a=b) or (a=c)",
number_inputs => 3,
width => 24
)
port map (
true => if_statement7_true_wire, -- true.wire
a => counter_0_output_wire, -- a.wire
b => cast35_output_wire, -- b.wire
c => pipelined_adder2_result_wire -- c.wire
);
counter_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => counter, -- input.wire
output => counter_0_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => constant7_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => delay5enavcc_output_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay5enavcc_output_wire -- output.wire
);
pixel_num_0 : component alt_dspbuilder_port_GNUJT4YY5I
port map (
input => pixel_num, -- input.wire
output => pixel_num_0_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak3_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => delay3enavcc_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
delay3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay3enavcc_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => logical_bit_operator5_result_wire, -- input.wire
output => sop -- output.wire
);
logical_bit_operator10 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator10_result_wire, -- result.wire
data0 => if_statement7_true_wire, -- data0.wire
data1 => data_en_0_output_wire -- data1.wire
);
ctrl_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => ctrl_en, -- input.wire
output => ctrl_en_0_output_wire -- output.wire
);
multiplexer1 : component alt_dspbuilder_multiplexer_GNHQFFAUXQ
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 0,
width => 25,
pipeline => 0,
number_inputs => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation_output_wire, -- sel.wire
result => multiplexer1_result_wire, -- result.wire
ena => multiplexer1enavcc_output_wire, -- ena.wire
user_aclr => multiplexer1user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast36_output_wire, -- in0.wire
in1 => multiplexer2_result_wire, -- in1.wire
in2 => cast37_output_wire -- in2.wire
);
multiplexer1user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer1user_aclrgnd_output_wire -- output.wire
);
multiplexer1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer1enavcc_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNNBTO2F3L
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000010",
width => 24
)
port map (
input => ctrl_pak1_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => delay1enavcc_output_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay1enavcc_output_wire -- output.wire
);
multiplexer2 : component alt_dspbuilder_multiplexer_GN6ODCX3D4
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
use_one_hot_select_bus => 1,
width => 25,
pipeline => 0,
number_inputs => 2
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
sel => bus_concatenation1_output_wire, -- sel.wire
result => multiplexer2_result_wire, -- result.wire
ena => multiplexer2enavcc_output_wire, -- ena.wire
user_aclr => multiplexer2user_aclrgnd_output_wire, -- user_aclr.wire
in0 => cast38_output_wire, -- in0.wire
in1 => cast39_output_wire -- in1.wire
);
multiplexer2user_aclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => multiplexer2user_aclrgnd_output_wire -- output.wire
);
multiplexer2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => multiplexer2enavcc_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNVJUPFOX3
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000000",
width => 24
)
port map (
input => ctrl_pak2_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => delay2enavcc_output_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
delay2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => delay2enavcc_output_wire -- output.wire
);
data_en_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data_en, -- input.wire
output => data_en_0_output_wire -- output.wire
);
cast29 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast29_output_wire -- output.wire
);
cast30 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r0_wire, -- input.wire
output => cast30_output_wire -- output.wire
);
cast31 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => case_statement1_r1_wire, -- input.wire
output => cast31_output_wire -- output.wire
);
cast32 : component alt_dspbuilder_cast_GN3ODVPHOL
generic map (
round => 0,
saturate => 0
)
port map (
input => counter_0_output_wire, -- input.wire
output => cast32_output_wire -- output.wire
);
cast33 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => ctrl_en_0_output_wire, -- input.wire
output => cast33_output_wire -- output.wire
);
cast34 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => data_en_0_output_wire, -- input.wire
output => cast34_output_wire -- output.wire
);
cast35 : component alt_dspbuilder_cast_GNCPEUNC4M
generic map (
round => 0,
saturate => 0
)
port map (
input => constant16_output_wire, -- input.wire
output => cast35_output_wire -- output.wire
);
cast36 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => constant5_output_wire, -- input.wire
output => cast36_output_wire -- output.wire
);
cast37 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => multiplexer_result_wire, -- input.wire
output => cast37_output_wire -- output.wire
);
cast38 : component alt_dspbuilder_cast_GNCCZ56SYK
generic map (
round => 0,
saturate => 0
)
port map (
input => colorbar_0_output_wire, -- input.wire
output => cast38_output_wire -- output.wire
);
cast39 : component alt_dspbuilder_cast_GNKDE2NVCC
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => cast39_output_wire -- output.wire
);
cast40 : component alt_dspbuilder_cast_GNKIWLRTQI
generic map (
round => 0,
saturate => 0
)
port map (
input => pixel_num_0_output_wire, -- input.wire
output => cast40_output_wire -- output.wire
);
end architecture rtl; -- of Test_Pattern_Generator_GN_Test_Pattern_Generator_MAIN_CTRL_SIGNAL_OUT
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni, ram_data_r_uart : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail,
reg_enable =>ram_enable,
reg_write_byte_enable =>ram_byte_we,
reg_address =>ram_address,
reg_data_write =>ram_data_w,
reg_data_read =>ram_data_r_uart);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni, ram_data_r_uart : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail,
reg_enable =>ram_enable,
reg_write_byte_enable =>ram_byte_we,
reg_address =>ram_address,
reg_data_write =>ram_data_w,
reg_data_read =>ram_data_r_uart);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni, ram_data_r_uart : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail,
reg_enable =>ram_enable,
reg_write_byte_enable =>ram_byte_we,
reg_address =>ram_address,
reg_data_write =>ram_data_w,
reg_data_read =>ram_data_r_uart);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX
);
end; --architecture logic
|
-- ======================================================================
-- AES encryption/decryption
-- Copyright (C) 2019 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
-- aes implementation
-- key length: 128 bit -> Nk = 4
-- data width: 128 bit -> Nb = 4
-- round number Nr = 10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package aes_pkg is
-- components
component aes_enc is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic;
clk_i : in std_logic;
key_i : in std_logic_vector(0 to 127);
data_i : in std_logic_vector(0 to 127);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127);
valid_o : out std_logic;
accept_i : in std_logic
);
end component aes_enc;
component aes_dec is
generic (
design_type : string := "ITER"
);
port (
reset_i : in std_logic;
clk_i : in std_logic;
key_i : in std_logic_vector(0 to 127);
data_i : in std_logic_vector(0 to 127);
valid_i : in std_logic;
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 127);
valid_o : out std_logic;
accept_i : in std_logic
);
end component aes_dec;
-- constants for AES128
constant c_nk : natural := 4; -- key size
constant c_nb : natural := 4; -- number of bytes
constant c_nr : natural := 10; -- number of rounds
subtype t_rounds is natural range 0 to c_nr + 1;
subtype t_key_rounds is natural range 0 to 9;
subtype t_enc_rounds is natural range t_rounds'low to t_rounds'high+1;
subtype t_dec_rounds is natural range t_rounds'low to t_rounds'high+1;
type t_datatable1d is array (0 to 3) of std_logic_vector(7 downto 0);
type t_datatable2d is array (0 to 3) of t_datatable1d;
type t_stable1d is array (0 to 15) of std_logic_vector(7 downto 0);
type t_stable2d is array (0 to 15) of t_stable1d;
type t_key is array (0 to 3) of std_logic_vector(31 downto 0);
type t_rcon is array (0 to 9) of std_logic_vector(7 downto 0);
constant c_sbox : t_stable2d := (
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F
(x"63", x"7c", x"77", x"7b", x"f2", x"6b", x"6f", x"c5", x"30", x"01", x"67", x"2b", x"fe", x"d7", x"ab", x"76"), -- 0
(x"ca", x"82", x"c9", x"7d", x"fa", x"59", x"47", x"f0", x"ad", x"d4", x"a2", x"af", x"9c", x"a4", x"72", x"c0"), -- 1
(x"b7", x"fd", x"93", x"26", x"36", x"3f", x"f7", x"cc", x"34", x"a5", x"e5", x"f1", x"71", x"d8", x"31", x"15"), -- 2
(x"04", x"c7", x"23", x"c3", x"18", x"96", x"05", x"9a", x"07", x"12", x"80", x"e2", x"eb", x"27", x"b2", x"75"), -- 3
(x"09", x"83", x"2c", x"1a", x"1b", x"6e", x"5a", x"a0", x"52", x"3b", x"d6", x"b3", x"29", x"e3", x"2f", x"84"), -- 4
(x"53", x"d1", x"00", x"ed", x"20", x"fc", x"b1", x"5b", x"6a", x"cb", x"be", x"39", x"4a", x"4c", x"58", x"cf"), -- 5
(x"d0", x"ef", x"aa", x"fb", x"43", x"4d", x"33", x"85", x"45", x"f9", x"02", x"7f", x"50", x"3c", x"9f", x"a8"), -- 6
(x"51", x"a3", x"40", x"8f", x"92", x"9d", x"38", x"f5", x"bc", x"b6", x"da", x"21", x"10", x"ff", x"f3", x"d2"), -- 7
(x"cd", x"0c", x"13", x"ec", x"5f", x"97", x"44", x"17", x"c4", x"a7", x"7e", x"3d", x"64", x"5d", x"19", x"73"), -- 8
(x"60", x"81", x"4f", x"dc", x"22", x"2a", x"90", x"88", x"46", x"ee", x"b8", x"14", x"de", x"5e", x"0b", x"db"), -- 9
(x"e0", x"32", x"3a", x"0a", x"49", x"06", x"24", x"5c", x"c2", x"d3", x"ac", x"62", x"91", x"95", x"e4", x"79"), -- A
(x"e7", x"c8", x"37", x"6d", x"8d", x"d5", x"4e", x"a9", x"6c", x"56", x"f4", x"ea", x"65", x"7a", x"ae", x"08"), -- B
(x"ba", x"78", x"25", x"2e", x"1c", x"a6", x"b4", x"c6", x"e8", x"dd", x"74", x"1f", x"4b", x"bd", x"8b", x"8a"), -- C
(x"70", x"3e", x"b5", x"66", x"48", x"03", x"f6", x"0e", x"61", x"35", x"57", x"b9", x"86", x"c1", x"1d", x"9e"), -- D
(x"e1", x"f8", x"98", x"11", x"69", x"d9", x"8e", x"94", x"9b", x"1e", x"87", x"e9", x"ce", x"55", x"28", x"df"), -- E
(x"8c", x"a1", x"89", x"0d", x"bf", x"e6", x"42", x"68", x"41", x"99", x"2d", x"0f", x"b0", x"54", x"bb", x"16")); -- F
constant c_sbox_invers : t_stable2d := (
-- 0 1 2 3 4 5 6 7 8 9 A B C D E F
(x"52", x"09", x"6a", x"d5", x"30", x"36", x"a5", x"38", x"bf", x"40", x"a3", x"9e", x"81", x"f3", x"d7", x"fb"), -- 0
(x"7c", x"e3", x"39", x"82", x"9b", x"2f", x"ff", x"87", x"34", x"8e", x"43", x"44", x"c4", x"de", x"e9", x"cb"), -- 1
(x"54", x"7b", x"94", x"32", x"a6", x"c2", x"23", x"3d", x"ee", x"4c", x"95", x"0b", x"42", x"fa", x"c3", x"4e"), -- 2
(x"08", x"2e", x"a1", x"66", x"28", x"d9", x"24", x"b2", x"76", x"5b", x"a2", x"49", x"6d", x"8b", x"d1", x"25"), -- 3
(x"72", x"f8", x"f6", x"64", x"86", x"68", x"98", x"16", x"d4", x"a4", x"5c", x"cc", x"5d", x"65", x"b6", x"92"), -- 4
(x"6c", x"70", x"48", x"50", x"fd", x"ed", x"b9", x"da", x"5e", x"15", x"46", x"57", x"a7", x"8d", x"9d", x"84"), -- 5
(x"90", x"d8", x"ab", x"00", x"8c", x"bc", x"d3", x"0a", x"f7", x"e4", x"58", x"05", x"b8", x"b3", x"45", x"06"), -- 6
(x"d0", x"2c", x"1e", x"8f", x"ca", x"3f", x"0f", x"02", x"c1", x"af", x"bd", x"03", x"01", x"13", x"8a", x"6b"), -- 7
(x"3a", x"91", x"11", x"41", x"4f", x"67", x"dc", x"ea", x"97", x"f2", x"cf", x"ce", x"f0", x"b4", x"e6", x"73"), -- 8
(x"96", x"ac", x"74", x"22", x"e7", x"ad", x"35", x"85", x"e2", x"f9", x"37", x"e8", x"1c", x"75", x"df", x"6e"), -- 9
(x"47", x"f1", x"1a", x"71", x"1d", x"29", x"c5", x"89", x"6f", x"b7", x"62", x"0e", x"aa", x"18", x"be", x"1b"), -- A
(x"fc", x"56", x"3e", x"4b", x"c6", x"d2", x"79", x"20", x"9a", x"db", x"c0", x"fe", x"78", x"cd", x"5a", x"f4"), -- B
(x"1f", x"dd", x"a8", x"33", x"88", x"07", x"c7", x"31", x"b1", x"12", x"10", x"59", x"27", x"80", x"ec", x"5f"), -- C
(x"60", x"51", x"7f", x"a9", x"19", x"b5", x"4a", x"0d", x"2d", x"e5", x"7a", x"9f", x"93", x"c9", x"9c", x"ef"), -- D
(x"a0", x"e0", x"3b", x"4d", x"ae", x"2a", x"f5", x"b0", x"c8", x"eb", x"bb", x"3c", x"83", x"53", x"99", x"61"), -- E
(x"17", x"2b", x"04", x"7e", x"ba", x"77", x"d6", x"26", x"e1", x"69", x"14", x"63", x"55", x"21", x"0c", x"7d"));-- F
constant c_rcon : t_rcon := (x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36");
function bytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector;
function invbytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector;
function subbytes (input : in t_datatable2d) return t_datatable2d;
function invsubbytes (input : in t_datatable2d) return t_datatable2d;
function shiftrow (input : t_datatable2d) return t_datatable2d;
function invshiftrow (input : t_datatable2d) return t_datatable2d;
function mixcolumns (input : t_datatable2d) return t_datatable2d;
function invmixcolumns (input : t_datatable2d) return t_datatable2d;
function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector;
function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d;
function subword (input : in std_logic_vector(31 downto 0)) return std_logic_vector;
function rotword (input : in std_logic_vector(31 downto 0)) return std_logic_vector;
function key_round (key : t_key; round : t_key_rounds) return t_key;
function set_state (input : in std_logic_vector(0 to 127)) return t_datatable2d;
function get_state (input : in t_datatable2d) return std_logic_vector;
function set_key (input : in std_logic_vector(0 to 127)) return t_key;
function to_string(input : t_datatable2d) return string;
end package aes_pkg;
package body aes_pkg is
function bytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return c_sbox(to_integer(unsigned(input(7 downto 4))))(to_integer(unsigned(input(3 downto 0))));
end function bytesub;
function invbytesub (input : std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return c_sbox_invers(to_integer(unsigned(input(7 downto 4))))(to_integer(unsigned(input(3 downto 0))));
end function invbytesub;
function subbytes (input : in t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
for row in 0 to 3 loop
v_data(row)(column) := c_sbox(to_integer(unsigned(input(row)(column)(7 downto 4))))(to_integer(unsigned(input(row)(column)(3 downto 0))));
end loop;
end loop;
return v_data;
end function subbytes;
function invsubbytes (input : in t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
for row in 0 to 3 loop
v_data(row)(column) := c_sbox_invers(to_integer(unsigned(input(row)(column)(7 downto 4))))(to_integer(unsigned(input(row)(column)(3 downto 0))));
end loop;
end loop;
return v_data;
end function invsubbytes;
function shiftrow (input : t_datatable2d) return t_datatable2d is
variable v_datamatrix : t_datatable2d;
begin
-- copy input in internal matrix
v_datamatrix := input;
-- 2nd row
v_datamatrix(1)(0) := input(1)(1);
v_datamatrix(1)(1) := input(1)(2);
v_datamatrix(1)(2) := input(1)(3);
v_datamatrix(1)(3) := input(1)(0);
-- 3rd row
v_datamatrix(2)(0) := input(2)(2);
v_datamatrix(2)(1) := input(2)(3);
v_datamatrix(2)(2) := input(2)(0);
v_datamatrix(2)(3) := input(2)(1);
-- 4rd row
v_datamatrix(3)(0) := input(3)(3);
v_datamatrix(3)(1) := input(3)(0);
v_datamatrix(3)(2) := input(3)(1);
v_datamatrix(3)(3) := input(3)(2);
-- return manipulated internal matrix
return v_datamatrix;
end function shiftrow;
function invshiftrow (input : t_datatable2d) return t_datatable2d is
variable v_datamatrix : t_datatable2d;
begin
-- copy input in internal matrix
v_datamatrix := input;
-- 2nd row
v_datamatrix(1)(0) := input(1)(3);
v_datamatrix(1)(1) := input(1)(0);
v_datamatrix(1)(2) := input(1)(1);
v_datamatrix(1)(3) := input(1)(2);
-- 3rd row
v_datamatrix(2)(0) := input(2)(2);
v_datamatrix(2)(1) := input(2)(3);
v_datamatrix(2)(2) := input(2)(0);
v_datamatrix(2)(3) := input(2)(1);
-- 4rd row
v_datamatrix(3)(0) := input(3)(1);
v_datamatrix(3)(1) := input(3)(2);
v_datamatrix(3)(2) := input(3)(3);
v_datamatrix(3)(3) := input(3)(0);
-- return manipulated internal matrix
return v_datamatrix;
end function invshiftrow;
-- trivial algorithmus to multiply two bytes in the GF(2^8) finite field defined
-- by the polynomial x^8 + x^4 + x^3 + x + 1
-- taken from http://www.codeplanet.eu/tutorials/cpp/51-advanced-encryption-standard.html
-- and ported to vhdl
function gmul (a : std_logic_vector(7 downto 0); b : std_logic_vector(7 downto 0)) return std_logic_vector is
variable v_a, v_b : std_logic_vector(7 downto 0);
variable v_data : std_logic_vector(7 downto 0) := (others => '0');
variable v_hi_bit_set : boolean;
begin
v_a := a;
v_b := b;
for index in 0 to 7 loop
if(v_b(0) = '1') then
v_data := v_data xor v_a;
end if;
v_hi_bit_set := v_a(7) = '1';
v_a := v_a(6 downto 0) & '0';
if (v_hi_bit_set) then
v_a := v_a xor x"1B";
end if;
v_b := '0' & v_b(7 downto 1);
end loop;
return v_data;
end function gmul;
-- matrix columns manipulation
function mixcolumns (input : t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
v_data(0)(column) := gmul(x"02", input(0)(column)) xor gmul(x"03", input(1)(column)) xor input(2)(column) xor input(3)(column);
v_data(1)(column) := input(0)(column) xor gmul(x"02", input(1)(column)) xor gmul(x"03",input(2)(column)) xor input(3)(column);
v_data(2)(column) := input(0)(column) xor input(1)(column) xor gmul(x"02",input(2)(column)) xor gmul(x"03",input(3)(column));
v_data(3)(column) := gmul(x"03", input(0)(column)) xor input(1)(column) xor input(2)(column) xor gmul(x"02",input(3)(column));
end loop;
return v_data;
end function mixcolumns;
-- matrix columns manipulation
function invmixcolumns (input : t_datatable2d) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
v_data(0)(column) := gmul(x"0E", input(0)(column)) xor gmul(x"0B", input(1)(column)) xor gmul(x"0D", input(2)(column)) xor gmul(x"09", input(3)(column));
v_data(1)(column) := gmul(x"09", input(0)(column)) xor gmul(x"0E", input(1)(column)) xor gmul(x"0B", input(2)(column)) xor gmul(x"0D", input(3)(column));
v_data(2)(column) := gmul(x"0D", input(0)(column)) xor gmul(x"09", input(1)(column)) xor gmul(x"0E", input(2)(column)) xor gmul(x"0B", input(3)(column));
v_data(3)(column) := gmul(x"0B", input(0)(column)) xor gmul(x"0D", input(1)(column)) xor gmul(x"09", input(2)(column)) xor gmul(x"0E", input(3)(column));
end loop;
return v_data;
end function invmixcolumns;
function addroundkey (input : in t_datatable2d; key : in t_key) return t_datatable2d is
variable v_data : t_datatable2d;
variable v_key : t_datatable1d;
begin
for column in 0 to 3 loop
v_key := (key(column)(31 downto 24), key(column)(23 downto 16), key(column)(15 downto 8), key(column)(7 downto 0));
for row in 0 to 3 loop
v_data(row)(column) := input(row)(column) xor v_key(row);
end loop;
end loop;
return v_data;
end function addroundkey;
function subword (input : in std_logic_vector(31 downto 0)) return std_logic_vector is
variable v_data : std_logic_vector(31 downto 0);
begin
v_data := bytesub(input(31 downto 24)) & bytesub(input(23 downto 16)) & bytesub(input(15 downto 8)) & bytesub(input(7 downto 0));
return v_data;
end function subword;
function rotword (input : in std_logic_vector(31 downto 0)) return std_logic_vector is
begin
return (input(23 downto 16), input(15 downto 8), input(7 downto 0), input(31 downto 24));
end function rotword;
function key_round (key : t_key; round : t_key_rounds) return t_key is
variable v_key : t_key;
begin
v_key(3) := subword(rotword(key(3))) xor (c_rcon(round) & x"000000");
v_key(0) := key(0) xor v_key(3);
v_key(1) := v_key(0) xor key(1);
v_key(2) := v_key(1) xor key(2);
v_key(3) := v_key(2) xor key(3);
return v_key;
end function key_round;
function set_state (input : in std_logic_vector(0 to 127)) return t_datatable2d is
variable v_data : t_datatable2d;
begin
for column in 0 to 3 loop
for row in 0 to 3 loop
v_data(row)(column) := input(row*8+column*32 to row*8+column*32+7);
end loop;
end loop;
return v_data;
end function set_state;
function get_state (input : in t_datatable2d) return std_logic_vector is
begin
return input(0)(0) & input(1)(0) & input(2)(0) & input(3)(0) &
input(0)(1) & input(1)(1) & input(2)(1) & input(3)(1) &
input(0)(2) & input(1)(2) & input(2)(2) & input(3)(2) &
input(0)(3) & input(1)(3) & input(2)(3) & input(3)(3);
end function get_state;
function set_key (input : in std_logic_vector(0 to 127)) return t_key is
begin
return (input(0 to 31), input(32 to 63), input(64 to 95), input(96 to 127));
end function set_key;
function to_string(input : t_datatable2d) return string is
begin
return '(' & to_hstring(input(0)(0)) & ',' & to_hstring(input(0)(1)) & ',' & to_hstring(input(0)(2)) & ',' & to_hstring(input(0)(3)) & ')' & LF &
'(' & to_hstring(input(1)(0)) & ',' & to_hstring(input(1)(1)) & ',' & to_hstring(input(1)(2)) & ',' & to_hstring(input(1)(3)) & ')' & LF &
'(' & to_hstring(input(2)(0)) & ',' & to_hstring(input(2)(1)) & ',' & to_hstring(input(2)(2)) & ',' & to_hstring(input(2)(3)) & ')' & LF &
'(' & to_hstring(input(3)(0)) & ',' & to_hstring(input(3)(1)) & ',' & to_hstring(input(3)(2)) & ',' & to_hstring(input(3)(3)) & ')';
end function to_string;
end package body aes_pkg;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2);
tck, tms, tdi : in std_logic;
tdo : out std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkx, clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal gclk : std_logic_vector(NCPU-1 downto 0);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal pci_dirq : std_logic_vector(3 downto 0);
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 40000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN + CFG_GRPCI2_MASTER;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET), CFG_PCIDLL, CFG_PCISYSCLK)
port map (lclk, pci_lclk, clkx, open, open, sdclkl, pciclk, cgi, cgo);
clkpwd : entity work.clkgate generic map (fabtech, NCPU, CFG_DSU)
port map (rstn, clkx, dsuo.pwd(NCPU-1 downto 0), clkm, gclk);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1, CFG_DFIXED,
CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), gclk(i));
nodsu : if CFG_DSU = 0 generate
dsuo.pwd(i) <= dbgo(i).pwd and not dbgo(i).ipend;
end generate;
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
dbgi <= (others => dbgi_none);
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 5, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(5) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp0 : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
grpci2xt : if (CFG_GRPCI2_TARGET) /= 0 and (CFG_GRPCI2_MASTER+CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, open, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xmt : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) > 1 and (CFG_GRPCI2_DMA) = 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
open, open, open, open, open);
end generate;
grpci2xd : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 and CFG_GRPCI2_DMA /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
hmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
hdmindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
hsindex => 4, haddr => 16#C00#, hmask => 16#E00#, ioaddr => 16#400#,
pindex => 4, paddr => 4, irq => 4, irqmode => 0,
master => CFG_GRPCI2_MASTER, target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA, tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID, deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS, revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP, ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO, extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0, bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2, bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4, bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH, fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN, deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK, hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2, hostrst => 1, bypass => CFG_GRPCI2_BYPASS,
debug => 0, tbapben => 0, tbpindex => 5, tbpaddr => 16#400#, tbpmask => 16#C00#
)
port map (
rstn, clkm, pciclk, pci_dirq, pcii, pcio, apbi, apbo(4), ahbsi, ahbso(4), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
open, open, open, open);
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_GRPCI2_MASTER = 0 generate ahbso(4) <= ahbs_none; end generate;
nop2 : if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
apbo(4) <= apb_none; apbo(5) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0'; -- For second port
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, ports => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC,rmapbufs => CFG_SPW_RMAPBUF,
dmachan => CFG_SPW_DMACHAN,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT, rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
-- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 13.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_INOUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal COUNT_DAT_INPUT : std_logic_vector(15 downto 0); -- Dateninput
signal WRITE_M : std_logic; --Schreibanzeiger, Ausgang Master, (1=schreiben)
signal n_WRITE : std_logic; --Schreibanzeiger, neuer Wert
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_M <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_M <= n_WRITE;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_M <= WRITE_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S, COUNT_DAT_INPUT)
begin
--setze fuer alle Zustaende
n_WRITE <= '0'; --kein Schreiben
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_WRITE <= '1'; --schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT_INPUT; --Daten einlesen
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- DATEN einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT_INPUT; -- Daten einlesen
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
n_SV <= ST_RAM_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT(0);
DISPL1_n_SV(1) <= COUNT_DAT(1);
DISPL1_n_SV(2) <= COUNT_DAT(2);
DISPL1_n_SV(3) <= COUNT_DAT(3);
DISPL2_n_SV(0) <= COUNT_DAT(4);
DISPL2_n_SV(1) <= COUNT_DAT(5);
DISPL2_n_SV(2) <= COUNT_DAT(6);
DISPL2_n_SV(3) <= COUNT_DAT(7);
end if;
end process;
-- Adressen Output
COUNT_ADR_OUT <= n_COUNT_ADR;
-- Daten lesen
COUNT_DAT_INPUT <= COUNT_DAT_INOUT;
-- Daten schreiben
-- Tri-State Buffer control
COUNT_DAT_INOUT <= n_COUNT_DAT when WRITE_M = '1' else (others=>'Z'); --geht nicht in einem Prozess weil Fehler
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.std_logic_1164_additions.all;
use work.AEAD_pkg.all;
library std;
use std.textio.all;
entity top is
generic (
G_W : integer := 32;
G_SW : integer := 32;
G_ASYNC_RSTN : boolean := False;
G_ENABLE_PAD : boolean := True;
G_CIPH_EXP : boolean := False;
G_REVERSE_CIPH : boolean := False;
G_MERGE_TAG : boolean := False;
G_ABLK_SIZE : integer := 64; -- change this when changing Ascon version
G_DBLK_SIZE : integer := 64;
G_KEY_SIZE : integer := 32;
G_TAG_SIZE : integer := 128;
G_PAD_STYLE : integer := 1;
G_PAD_AD : integer := 3;
G_PAD_D : integer := 4);
port (
clk : in std_logic;
rst : in std_logic;
pdi_data : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
sdi_data : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
do_data : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic);
end entity top;
architecture structural of top is
begin -- architecture structural
AEAD_1: entity work.AEAD
generic map (
G_W => G_W,
G_SW => G_SW,
G_ASYNC_RSTN => G_ASYNC_RSTN,
G_ENABLE_PAD => G_ENABLE_PAD,
G_CIPH_EXP => G_CIPH_EXP,
G_REVERSE_CIPH => G_REVERSE_CIPH,
G_MERGE_TAG => G_MERGE_TAG,
G_ABLK_SIZE => G_ABLK_SIZE,
G_DBLK_SIZE => G_DBLK_SIZE,
G_KEY_SIZE => G_KEY_SIZE,
G_TAG_SIZE => G_TAG_SIZE,
G_PAD_STYLE => G_PAD_STYLE,
G_PAD_AD => G_PAD_AD,
G_PAD_D => G_PAD_D)
port map (
clk => clk,
rst => rst,
pdi_data => pdi_data,
pdi_valid => pdi_valid,
pdi_ready => pdi_ready,
sdi_data => sdi_data,
sdi_valid => sdi_valid,
sdi_ready => sdi_ready,
do_data => do_data,
do_ready => do_ready,
do_valid => do_valid);
end architecture structural;
|
-------------------------------------------------------------------------------
-- $Id: parityenable.vhd,v 1.1.2.3 2010/10/04 06:07:06 stefana Exp $
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-- Revision: $Revision: 1.1.2.3 $
-- Date: $Date: 2010/10/04 06:07:06 $
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ParityEnable is
generic (
C_USE_LUT6 : boolean := true;
C_SIZE : integer := 4
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Enable : in std_logic;
Res : out std_logic
);
end entity ParityEnable;
library unisim;
use unisim.vcomponents.all;
architecture IMP of ParityEnable is
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_LUT6 : if (C_USE_LUT6) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 5 generate
signal inA5 : std_logic_vector(0 to 4);
begin
Assign_InA : process (InA) is
begin
inA5 <= (others => '0');
inA5(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : LUT6
generic map(
INIT => X"9669699600000000")
port map(
O => Res,
I0 => InA5(4),
I1 => inA5(3),
I2 => inA5(2),
I3 => inA5(1),
I4 => inA5(0),
I5 => Enable);
end generate Single_LUT6;
end generate Using_LUT6;
-- Fall-back implementation without LUT6
Not_Using_LUT6 : if not C_USE_LUT6 or C_SIZE > 8 generate
begin
Res <= Enable and ParityGen(InA);
end generate Not_Using_LUT6;
end architecture IMP;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture rtl of mac is
signal pipelined_x_real,
pipelined_x_imag,
pipelined_y_real,
pipelined_y_imag : std_ulogic_vector(15 downto 0);
signal real_part_product_1,
real_part_product_2,
imag_part_product_1,
imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal pipelined_real_part_product_1,
pipelined_real_part_product_2,
pipelined_imag_part_product_1,
pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal real_product,
imag_product : std_ulogic_vector(32 downto 0);
signal pipelined_real_product,
pipelined_imag_product : std_ulogic_vector(19 downto 0);
signal real_sum,
imag_sum : std_ulogic_vector(21 downto 0);
signal real_accumulator_ovf,
imag_accumulator_ovf : std_ulogic;
signal pipelined_real_sum,
pipelined_imag_sum : std_ulogic_vector(21 downto 0);
signal pipelined_real_accumulator_ovf,
pipelined_imag_accumulator_ovf : std_ulogic;
begin
x_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_real, q => pipelined_x_real );
x_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
y_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_real, q => pipelined_y_real );
y_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
real_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_real,
p => real_part_product_1 );
real_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_imag,
p => real_part_product_2 );
imag_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_imag,
p => imag_part_product_1 );
imag_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_real,
p => imag_part_product_2 );
real_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_1,
q => pipelined_real_part_product_1 );
real_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_2,
q => pipelined_real_part_product_2 );
imag_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_1,
q => pipelined_imag_part_product_1 );
imag_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_2,
q => pipelined_imag_part_product_2 );
real_product_subtracter : entity work.product_adder_subtracter(behavioral)
port map ( mode => '1',
a => pipelined_real_part_product_1,
b => pipelined_real_part_product_2,
s => real_product );
imag_product_adder : entity work.product_adder_subtracter(behavioral)
port map ( mode => '0',
a => pipelined_imag_part_product_1,
b => pipelined_imag_part_product_2,
s => imag_product );
real_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => real_product(32 downto 13),
q => pipelined_real_product );
imag_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => imag_product(32 downto 13),
q => pipelined_imag_product );
real_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
a(20) => pipelined_real_product(19),
a(21) => pipelined_real_product(19),
b => pipelined_real_sum,
s => real_sum,
ovf => real_accumulator_ovf );
imag_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
a(20) => pipelined_imag_product(19),
a(21) => pipelined_imag_product(19),
b => pipelined_imag_sum,
s => imag_sum,
ovf => imag_accumulator_ovf );
real_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => real_sum, q => pipelined_real_sum );
imag_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => imag_sum, q => pipelined_imag_sum );
real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => real_accumulator_ovf, clr => clr,
q => pipelined_real_accumulator_ovf );
imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => imag_accumulator_ovf, clr => clr,
q => pipelined_imag_accumulator_ovf );
s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
result_overflow_logic : entity work.overflow_logic(behavioral)
port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
real_sum => pipelined_real_sum(21 downto 17),
imag_sum => pipelined_imag_sum(21 downto 17),
ovf => ovf );
end architecture rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture rtl of mac is
signal pipelined_x_real,
pipelined_x_imag,
pipelined_y_real,
pipelined_y_imag : std_ulogic_vector(15 downto 0);
signal real_part_product_1,
real_part_product_2,
imag_part_product_1,
imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal pipelined_real_part_product_1,
pipelined_real_part_product_2,
pipelined_imag_part_product_1,
pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal real_product,
imag_product : std_ulogic_vector(32 downto 0);
signal pipelined_real_product,
pipelined_imag_product : std_ulogic_vector(19 downto 0);
signal real_sum,
imag_sum : std_ulogic_vector(21 downto 0);
signal real_accumulator_ovf,
imag_accumulator_ovf : std_ulogic;
signal pipelined_real_sum,
pipelined_imag_sum : std_ulogic_vector(21 downto 0);
signal pipelined_real_accumulator_ovf,
pipelined_imag_accumulator_ovf : std_ulogic;
begin
x_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_real, q => pipelined_x_real );
x_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
y_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_real, q => pipelined_y_real );
y_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
real_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_real,
p => real_part_product_1 );
real_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_imag,
p => real_part_product_2 );
imag_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_imag,
p => imag_part_product_1 );
imag_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_real,
p => imag_part_product_2 );
real_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_1,
q => pipelined_real_part_product_1 );
real_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_2,
q => pipelined_real_part_product_2 );
imag_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_1,
q => pipelined_imag_part_product_1 );
imag_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_2,
q => pipelined_imag_part_product_2 );
real_product_subtracter : entity work.product_adder_subtracter(behavioral)
port map ( mode => '1',
a => pipelined_real_part_product_1,
b => pipelined_real_part_product_2,
s => real_product );
imag_product_adder : entity work.product_adder_subtracter(behavioral)
port map ( mode => '0',
a => pipelined_imag_part_product_1,
b => pipelined_imag_part_product_2,
s => imag_product );
real_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => real_product(32 downto 13),
q => pipelined_real_product );
imag_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => imag_product(32 downto 13),
q => pipelined_imag_product );
real_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
a(20) => pipelined_real_product(19),
a(21) => pipelined_real_product(19),
b => pipelined_real_sum,
s => real_sum,
ovf => real_accumulator_ovf );
imag_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
a(20) => pipelined_imag_product(19),
a(21) => pipelined_imag_product(19),
b => pipelined_imag_sum,
s => imag_sum,
ovf => imag_accumulator_ovf );
real_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => real_sum, q => pipelined_real_sum );
imag_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => imag_sum, q => pipelined_imag_sum );
real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => real_accumulator_ovf, clr => clr,
q => pipelined_real_accumulator_ovf );
imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => imag_accumulator_ovf, clr => clr,
q => pipelined_imag_accumulator_ovf );
s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
result_overflow_logic : entity work.overflow_logic(behavioral)
port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
real_sum => pipelined_real_sum(21 downto 17),
imag_sum => pipelined_imag_sum(21 downto 17),
ovf => ovf );
end architecture rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture rtl of mac is
signal pipelined_x_real,
pipelined_x_imag,
pipelined_y_real,
pipelined_y_imag : std_ulogic_vector(15 downto 0);
signal real_part_product_1,
real_part_product_2,
imag_part_product_1,
imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal pipelined_real_part_product_1,
pipelined_real_part_product_2,
pipelined_imag_part_product_1,
pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
signal real_product,
imag_product : std_ulogic_vector(32 downto 0);
signal pipelined_real_product,
pipelined_imag_product : std_ulogic_vector(19 downto 0);
signal real_sum,
imag_sum : std_ulogic_vector(21 downto 0);
signal real_accumulator_ovf,
imag_accumulator_ovf : std_ulogic;
signal pipelined_real_sum,
pipelined_imag_sum : std_ulogic_vector(21 downto 0);
signal pipelined_real_accumulator_ovf,
pipelined_imag_accumulator_ovf : std_ulogic;
begin
x_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_real, q => pipelined_x_real );
x_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
y_real_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_real, q => pipelined_y_real );
y_imag_input_reg : entity work.reg(behavioral)
port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
real_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_real,
p => real_part_product_1 );
real_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_imag,
p => real_part_product_2 );
imag_mult_1 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_real, b => pipelined_y_imag,
p => imag_part_product_1 );
imag_mult_2 : entity work.multiplier(behavioral)
port map ( a => pipelined_x_imag, b => pipelined_y_real,
p => imag_part_product_2 );
real_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_1,
q => pipelined_real_part_product_1 );
real_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => real_part_product_2,
q => pipelined_real_part_product_2 );
imag_part_product_reg_1 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_1,
q => pipelined_imag_part_product_1 );
imag_part_product_reg_2 : entity work.reg(behavioral)
port map ( clk => clk, d => imag_part_product_2,
q => pipelined_imag_part_product_2 );
real_product_subtracter : entity work.product_adder_subtracter(behavioral)
port map ( mode => '1',
a => pipelined_real_part_product_1,
b => pipelined_real_part_product_2,
s => real_product );
imag_product_adder : entity work.product_adder_subtracter(behavioral)
port map ( mode => '0',
a => pipelined_imag_part_product_1,
b => pipelined_imag_part_product_2,
s => imag_product );
real_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => real_product(32 downto 13),
q => pipelined_real_product );
imag_product_reg : entity work.reg(behavioral)
port map ( clk => clk,
d => imag_product(32 downto 13),
q => pipelined_imag_product );
real_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
a(20) => pipelined_real_product(19),
a(21) => pipelined_real_product(19),
b => pipelined_real_sum,
s => real_sum,
ovf => real_accumulator_ovf );
imag_accumulator : entity work.accumulator_adder(behavioral)
port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
a(20) => pipelined_imag_product(19),
a(21) => pipelined_imag_product(19),
b => pipelined_imag_sum,
s => imag_sum,
ovf => imag_accumulator_ovf );
real_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => real_sum, q => pipelined_real_sum );
imag_accumulator_reg : entity work.accumulator_reg(behavioral)
port map ( clk => clk, clr => clr,
d => imag_sum, q => pipelined_imag_sum );
real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => real_accumulator_ovf, clr => clr,
q => pipelined_real_accumulator_ovf );
imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
port map ( clk => clk,
set => imag_accumulator_ovf, clr => clr,
q => pipelined_imag_accumulator_ovf );
s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
result_overflow_logic : entity work.overflow_logic(behavioral)
port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
real_sum => pipelined_real_sum(21 downto 17),
imag_sum => pipelined_imag_sum(21 downto 17),
ovf => ovf );
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_700a is
generic (
g_version : unsigned(7 downto 0) := X"02" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_700a;
architecture structural of boot_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_cartridge => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_700a is
generic (
g_version : unsigned(7 downto 0) := X"02" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_700a;
architecture structural of boot_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_cartridge => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_700a is
generic (
g_version : unsigned(7 downto 0) := X"02" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_700a;
architecture structural of boot_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_cartridge => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_700a is
generic (
g_version : unsigned(7 downto 0) := X"02" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_700a;
architecture structural of boot_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_cartridge => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_700a is
generic (
g_version : unsigned(7 downto 0) := X"02" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_700a;
architecture structural of boot_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_cartridge => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-------------------------------------------------------------------------
entity BLOCKRAM is
generic
(
B : NATURAL := 8; -- Address Bus width
W : NATURAL := 2 -- Data Bus width
);
port
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
wr_en : in STD_LOGIC;
w_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
r_addr : in STD_LOGIC_VECTOR(W-1 downto 0);
w_data : in STD_LOGIC_VECTOR(B-1 downto 0);
r_data : out STD_LOGIC_VECTOR(B-1 downto 0)
);
end BLOCKRAM;
-------------------------------------------------------------------------
architecture Behavioral of BLOCKRAM is
type REG_FILE_TYPE is array (2**W-1 downto 0) of STD_LOGIC_VECTOR (B-1 downto 0);
signal array_reg : REG_FILE_TYPE;
begin
-- Read-First Mode
process(clk)
begin
if (rising_edge(clk)) then
if (wr_en = '1') then
array_reg(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end process;
r_data <= array_reg(to_integer(unsigned(r_addr)));
-- Write-First Mode
--process(clk)
--begin
--if (rising_edge(clk)) then
--if (wr_en = '1') then
--array_reg(to_integer(unsigned(w_addr))) <= w_data;
--r_data <= w_data;
--else
--r_data <= array_reg(to_integer(unsigned(r_addr)));
--end if;
--end if;
--end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ethtx_output is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 16;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
reset : in std_logic;
txclk : in std_logic;
txd : out std_logic_vector(3 downto 0);
txen : out std_logic;
tx_queue_empty : in std_logic;
tx_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
tx_head_rdata : in std_logic_vector(7 downto 0);
tx_head_rd_block : out std_logic;
db_queue_empty : in std_logic;
db_head_raddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0);
db_head_rdata : in std_logic_vector(7 downto 0);
db_head_rd_block : out std_logic;
buff_raddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_rdata : in std_logic_vector(7 downto 0);
dma_start : out std_logic;
dma_start_addr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- dma_start_addr : out std_logic_vector(23 downto 0);
dma_length : out std_logic_vector(15 downto 0);
dma_step : out std_logic_vector(7 downto 0);
localtime : in std_logic_vector(31 downto 0)
);
end ethtx_output;
architecture arch_ethtx_output of ethtx_output is
component crcrom
port(
addr : in std_logic_vector(3 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component fifo_async
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async use entity WORK.fifo_async(fast_write);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
-- constant INFO_LENGTH : natural := 7;
constant INFO_LENGTH : natural := 8;
signal full : std_logic;
signal ce : std_logic;
signal txd_int : std_logic_vector(3 downto 0);
signal txen_int : std_logic;
signal txd_buf : std_logic_vector(3 downto 0);
signal txen_buf : std_logic;
signal d_int : std_logic_vector(4 downto 0);
signal d_ext : std_logic_vector(4 downto 0);
signal busy : std_logic;
signal nibble_cnt : std_logic_vector(11 downto 0);
signal head_length : std_logic_vector(7 downto 0);
signal data_length : std_logic_vector(10 downto 0);
signal source_select : std_logic;
signal head_rd_block : std_logic;
signal info_ena : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal data_ena : std_logic;
signal data_ena_d1 : std_logic;
signal data_ena_d2 : std_logic;
signal data_ena_d3 : std_logic;
signal data_ena_d4 : std_logic;
signal data_ena_d5 : std_logic;
signal head_ena : std_logic;
signal buff_ena : std_logic;
signal info_start : std_logic;
signal data_start : std_logic;
signal byte_data : std_logic_vector(7 downto 0);
signal nibble_data : std_logic_vector(3 downto 0);
signal nibble_data_buf : std_logic_vector(3 downto 0);
signal nibble_data_dly : std_logic_vector(3 downto 0);
signal head_rden : std_logic;
signal head_rdata : std_logic_vector(7 downto 0);
signal head_raddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal buff_rden : std_logic;
signal buff_raddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal crc_din : std_logic_vector(3 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(3 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal v2 : std_logic_vector(0 downto 0);
signal v3 : std_logic_vector(0 downto 0);
signal localtime_reg : std_logic_vector(31 downto 0);
signal crc_reg_dly : std_logic_vector(3 downto 0);
signal IFG_cnt : std_logic_vector(4 downto 0);
signal IFG_busy : std_logic;
signal m4_TxFIFO_DN : std_logic_vector( 3 downto 0 );
signal s_N_Empty : std_logic;
signal s_N_Empty_TxClk : std_logic;
signal s_N_Empty_TxClk_D1 : std_logic;
begin
-- p_IFG_count : process(clk, reset)
p_info_start : process(clk, reset)
begin
if reset = '1' then
info_start <= '0';
source_select <= '0';
elsif rising_edge(clk) then
if ce = '1' then
if busy = '0' then
if tx_queue_empty = '0' then
info_start <= '1';
source_select <= '0';
elsif db_queue_empty = '0' then
info_start <= '1';
source_select <= '1';
end if;
else
info_start <= '0';
end if;
end if;
end if;
end process;
-- busy <= info_start or info_ena or data_start or data_ena or data_ena_d3;
busy <= info_start or info_ena or data_start or data_ena or data_ena_d4 or IFG_busy;
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
info_ena <= '0';
info_cnt <= 0;
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
info_ena <= '1';
elsif info_cnt = INFO_LENGTH - 1 then
info_ena <= '0';
end if;
if info_ena = '0' then
info_cnt <= 0;
else
info_cnt <= info_cnt + 1;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
data_start <= '1' when info_cnt = INFO_LENGTH else '0';
p_nibble_cnt : process(clk, reset)
begin
if reset = '1' then
data_ena <= '0';
nibble_cnt <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
data_ena <= '1';
elsif nibble_cnt = (data_length & '0') - 1 then
data_ena <= '0';
end if;
if data_start = '1' then
nibble_cnt <= (others => '0');
else
nibble_cnt <= nibble_cnt + 1;
end if;
end if;
end if;
end process;
head_ena <= '1' when data_ena = '1' and nibble_cnt < head_length & '0' else '0';
buff_ena <= '1' when data_ena = '1' and nibble_cnt >= head_length & '0' else '0';
------------------------------------------------------------------------------
head_rden <= (info_ena or (head_ena and (not nibble_cnt(0)))) and ce;
p_head_raddr : process(clk, reset)
begin
if reset = '1' then
head_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_start = '1' then
head_raddr_buf <= (others => '0');
elsif head_rden = '1' then
head_raddr_buf <= head_raddr_buf + 1;
end if;
end if;
end if;
end process;
tx_head_raddr <= head_raddr_buf;
db_head_raddr <= head_raddr_buf;
head_rdata <= tx_head_rdata when source_select = '0' else db_head_rdata;
head_rd_block <= '1' when nibble_cnt = head_length & '0' else '0';
tx_head_rd_block <= head_rd_block and ce and (not source_select);
db_head_rd_block <= head_rd_block and ce and source_select;
p_get_info : process(clk, reset)
begin
if reset = '1' then
head_length <= (others => '0');
data_length <= (others => '0');
dma_start_addr <= (others => '0');
dma_step <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if info_ena = '1' then
case info_cnt is
when 0 =>
head_length(7 downto 0) <= head_rdata;
when 1 =>
data_length(7 downto 0) <= head_rdata;
when 2 =>
data_length(10 downto 8) <= head_rdata(2 downto 0);
when 3 =>
dma_start_addr(7 downto 0) <= head_rdata;
when 4 =>
dma_start_addr(15 downto 8) <= head_rdata;
when 5 =>
dma_start_addr(23 downto 16) <= head_rdata;
-- 4 bytes dma addr --
when 6 =>
dma_start_addr(31 downto 24) <= head_rdata;
when 7 =>
dma_step <= head_rdata;
--when 6 =>
--dma_step <= head_rdata;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
dma_start <= '1' when info_cnt = INFO_LENGTH and ce = '1' and data_length /= head_length else '0';
dma_length <= SXT(data_length, 16) - SXT(head_length, 16);
------------------------------------------------------------------------------
buff_rden <= buff_ena and (not nibble_cnt(0)) and ce;
p_buff_raddr : process(clk, reset)
begin
if reset = '1' then
buff_raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
buff_raddr_buf <= (others => '0');
elsif buff_rden = '1' then
buff_raddr_buf <= buff_raddr_buf + 1;
end if;
end if;
end if;
end process;
buff_raddr <= buff_raddr_buf;
------------------------------------------------------------------------------
byte_data <= head_rdata when head_ena = '1' else
buff_rdata when buff_ena = '1' else
(others => '0');
p_nibble_data_buf : process(clk, reset)
begin
if reset = '1' then
nibble_data_buf <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
nibble_data_buf <= byte_data(7 downto 4);
end if;
end if;
end process;
--local time --
p_localtime : process(reset, clk)
begin
if reset = '1' then
localtime_reg <= (others => '0');
elsif rising_edge(clk) then
if nibble_cnt = 15 then
localtime_reg <= localtime;
end if;
end if;
end process;
nibble_data <= localtime_reg(31 downto 28) when nibble_cnt = 29 and source_select = '0' else
localtime_reg(27 downto 24) when nibble_cnt = 28 and source_select = '0' else
localtime_reg(23 downto 20) when nibble_cnt = 31 and source_select = '0' else
localtime_reg(19 downto 16) when nibble_cnt = 30 and source_select = '0' else
localtime_reg(15 downto 12) when nibble_cnt = 33 and source_select = '0' else
localtime_reg(11 downto 8) when nibble_cnt = 32 and source_select = '0' else
localtime_reg(7 downto 4) when nibble_cnt = 35 and source_select = '0' else
localtime_reg(3 downto 0) when nibble_cnt = 34 and source_select = '0' else
byte_data(3 downto 0) when nibble_cnt(0) = '0' else nibble_data_buf;
-- nibble_data <= byte_data(3 downto 0) when nibble_cnt(0) = '0' else nibble_data_buf;
------------------------------------------------------------------------------
u_crc_rom : CRCRom
port map(
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 28);
crc_din <= (others => '0') when data_ena = '0' else
not (nibble_data(0) & nibble_data(1) & nibble_data(2) & nibble_data(3)) when nibble_cnt < 8 else
nibble_data(0) & nibble_data(1) & nibble_data(2) & nibble_data(3);
p_calc_crc : process(clk, reset)
begin
if reset = '1' then
crc_reg <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if data_start = '1' then
crc_reg <= (others => '0');
elsif data_ena_d1 = '1' then
crc_reg <= (crc_reg(27 downto 0) & crc_din) xor crcrom_dout;
else
crc_reg <= (crc_reg(27 downto 0) & crc_din);
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
u_nibble_data_dly : ShiftReg
generic map(
WIDTH => 4,
DEPTH => 16 -- 8
)
port map(
clk => clk,
ce => ce,
D => nibble_data,
Q => nibble_data_dly,
S => open
);
u_crc_reg_dly : ShiftReg
generic map(
WIDTH => 4,
DEPTH => 8 -- 8
)
port map(
clk => clk,
ce => ce,
D => crc_reg(31 downto 28),
Q => crc_reg_dly(3 downto 0),
S => open
);
u_data_ena_d1 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 -- 8
)
port map(
clk => clk,
ce => ce,
D => v0,
Q => v1,
S => open
);
u_data_ena_d2 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 --8
)
port map(
clk => clk,
ce => ce,
D => v1,
Q => v2,
S => open
);
u_data_ena_d3 : ShiftReg
generic map(
WIDTH => 1,
DEPTH => 8 --8
)
port map(
clk => clk,
ce => ce,
D => v2,
Q => v3,
S => open
);
v0(0) <= data_ena;
data_ena_d1 <= v1(0);
data_ena_d2 <= v2(0);
data_ena_d3 <= v3(0);
txd_int <= "0101" when data_ena = '1' and nibble_cnt < 15 else
"1101" when data_ena = '1' and nibble_cnt = 15 else
--
nibble_data_dly when data_ena_d2 = '1' else
not(crc_reg_dly(0) & crc_reg_dly(1) & crc_reg_dly(2) & crc_reg_dly(3));
txen_int <= data_ena or data_ena_d3;
------------------------------------------------------------------------------
-- u_dout_sync : fifo_async
-- generic map(
-- depth => 4,
-- awidth => 2,
-- dwidth => 5,
-- ram_type => "DIS_RAM"
-- )
-- port map(
-- reset => reset,
-- clr => '0',
-- clka => clk,
-- wea => ce,
-- dia => d_int,
-- clkb => txclk,
-- rdb => '1',
-- dob => d_ext,
-- empty => open,
-- full => full,
-- dn => open
-- );
u_dout_sync : fifo_async
generic map(
depth => 16,
awidth => 4,
dwidth => 5,
ram_type => "DIS_RAM"
)
port map(
reset => reset,
clr => '0',
clka => clk,
wea => ce,
dia => d_int,
clkb => txclk,
rdb => s_N_Empty_TxClk,
dob => d_ext,
empty => open,
full => full,
dn => m4_TxFIFO_DN
);
NEmpty : process( reset, clk )
begin
if ( reset = '1' ) then
s_N_Empty <= '0';
elsif ( rising_edge( clk ) ) then
if ( m4_TxFIFO_DN > "0111" ) then
s_N_Empty <= '1';
-- else
-- s_N_Empty <= '0';
end if;
end if;
end process;
NEmpty_TxClk : process( reset, txclk )
begin
if ( reset = '1' ) then
s_N_Empty_TxClk <= '0';
s_N_Empty_TxClk_D1 <= '0';
elsif ( rising_edge( txclk ) ) then
s_N_Empty_TxClk <= s_N_Empty;
s_N_Empty_TxClk_D1 <= s_N_Empty_TxClk;
end if;
end process;
d_int <= txen_int & txd_int;
txen_buf <= d_ext(4) and s_N_Empty_TxClk_D1;
txd_buf <= d_ext(3 downto 0) and ( s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 & s_N_Empty_TxClk_D1 );
ce <= not full;
p_mii_dout : process(reset, txclk)
begin
if ( reset = '1' ) then
txen <= '0';
txd <= ( others => '0' );
elsif rising_edge(txclk) then
txen <= txen_buf;
txd <= txd_buf;
end if;
end process;
--------------------------------------------------------------
--- IFG - Inter Frame Gap generation
----------------------------------------------------------------
p_ifg_count : process(clk, reset)
begin
if reset = '1' then
IFG_cnt <= "00000";
elsif rising_edge(clk) then
data_ena_d4 <= data_ena_d3;
data_ena_d5 <= data_ena_d4;
if IFG_busy = '1' then
IFG_cnt <= IFG_cnt + '1';
else
IFG_cnt <= "00000";
end if;
end if;
end process;
p_ifg_busy_flag : process(clk, reset)
begin
if reset = '1' then
IFG_busy <= '0';
elsif rising_edge(clk) then
if data_ena_d3 = '0' and data_ena_d4 = '1' then
IFG_busy <= '1';
elsif IFG_cnt = "11111" then
IFG_busy <= '0';
end if;
end if;
end process;
end arch_ethtx_output;
|
--------------------------------------------------------------------------------
--
-- Title : cl_text.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for main text
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_text is
generic(
constant yend : std_logic_vector(4 downto 0); --! Y end area
constant ystart : std_logic_vector(4 downto 0); --! Y start area
constant xend : std_logic_vector(6 downto 0); --! X end area
constant xstart : std_logic_vector(6 downto 0) --! X start area
);
port(
-- system signals:
clk : in std_logic; --! clock
reset : in std_logic; --! system reset
-- control signals:
addr_rnd : in std_logic_vector(4 downto 0); --! address round
display : in std_logic; --! display enable
cntgames : in std_logic; --! games counter enable
win : in std_logic; --! win value
lose : in std_logic; --! lose value
game : in std_logic; --! game value
flash : in std_logic_vector(2 downto 0); --! RGB blinking
-- vga XoY:
x_char : in std_logic_vector(9 downto 0); --! X line: 0:79
y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0) --! RGB Colour
);
end cl_text;
architecture cl_text of cl_text is
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
component cl_select_text is
port(
x_char : in std_logic_vector(6 downto 0);
y_char : in std_logic_vector(4 downto 0);
win : in std_logic;
lose : in std_logic;
game : in std_logic;
cntgames: in std_logic;
addr_rnd: in std_logic_vector(4 downto 0);
ch_data : out std_logic_vector(7 downto 0)
);
end component;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal color : std_logic_vector(2 downto 0):="111";
signal addr_rom : std_logic_vector(10 downto 0);
signal data_rom : std_logic_vector(7 downto 0);
signal data_box : std_logic_vector(7 downto 0);
begin
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_select_text: cl_select_text
port map (
x_char => x_in,
y_char => y_in,
win => win,
lose => lose,
game => game,
cntgames=> cntgames,
addr_rnd=> addr_rnd,
ch_data => data_box
);
addr_rom <= data_box(6 downto 0) & y_char(3 downto 0) when rising_edge(clk);
x_char_rom: ctrl_8x16_rom
port map (
clk => clk,
addr => addr_rom,
data => data_rom
);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
color <= flash when (x_in > "0011001") and (y_in = "10000") else "100" when (y_in < "00111") else "010";
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
if display = '0' then
data <= '0';
else
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_text; |
-- Binary Multiplier with n = 4: VHDL Description
-- See Figures 8-6 and 8-7 for block diagram and ASM Chart
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity binary_multiplier is
port(CLK, RESET, G, LOADB, LOADQ: in std_logic;
MULT_IN: in std_logic_vector(15 downto 0);
MULT_OUT: out std_logic_vector(31 downto 0));
end binary_multiplier;
architecture behavior_16 of binary_multiplier is
type state_type is (IDLE, MUL0, MUL1);
signal state, next_state : state_type;
signal A, B, Q: std_logic_vector(15 downto 0);
signal P: std_logic_vector(3 downto 0);
signal C, Z: std_logic;
begin
Z <= not( P(3) OR P(2) OR P(1) OR P(0) );
MULT_OUT <= A & Q;
state_register: process (CLK, RESET)
begin
if (RESET = '1') then
state <= IDLE;
elsif (CLK'event and CLK = '1') then
state <= next_state;
end if;
end process;
next_state_func: process (G, Z, state)
begin
case state is
when IDLE =>
if G = '1' then
next_state <= MUL0;
else
next_state <= IDLE;
end if;
when MUL0 =>
next_state <= MUL1;
when MUL1 =>
if Z = '1' then
next_state <= IDLE;
else
next_state <= MUL0;
end if;
end case;
end process;
datapath_func: process (CLK)
variable CA: std_logic_vector(16 downto 0);
begin
if (CLK'event and CLK = '1') then
if LOADB = '1' then
B <= MULT_IN;
end if;
if LOADQ = '1' then
Q <= MULT_IN;
end if;
case state is
when IDLE =>
if G = '1' then
C <= '0';
A <= "0000000000000000";
P <= "1111";
end if;
when MUL0 =>
if Q(0) = '1' then
CA := ('0' & A) + ('0' & B);
else
CA := C & A;
end if;
C <= CA(16);
A <= CA(15 downto 0);
when MUL1 =>
C <= '0';
A <= C & A(15 downto 1);
Q <= A(0) & Q(15 downto 1);
P <= P - "0001";
end case;
end if;
end process;
end behavior_16;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AxiStreamSampleEnt is
generic (
C_DATA_WIDTH : positive := 32;
C_USER_WIDTH : positive := 2
);
port (
RX0_ETH_TDATA : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
RX0_ETH_TKEEP : in std_logic_vector(C_DATA_WIDTH / 8 - 1 downto 0);
RX0_ETH_TUSER : in std_logic_vector(C_USER_WIDTH - 1 downto 0);
RX0_ETH_TLAST : in std_logic;
RX0_ETH_TVALID : in std_logic;
RX0_ETH_TREADY : out std_logic;
RX0_CTL_TDATA : in std_logic_vector(31 downto 0);
RX0_CTL_TLAST : in std_logic;
RX0_CTL_TVALID : in std_logic;
RX0_CTL_TREADY : out std_logic;
TX0_ETH_TDATA : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
TX0_ETH_TKEEP : out std_logic_vector(C_DATA_WIDTH / 8 - 1 downto 0);
TX0_ETH_TUSER : out std_logic_vector(C_USER_WIDTH - 1 downto 0);
TX0_ETH_TLAST : out std_logic;
TX0_ETH_TVALID : out std_logic;
TX0_ETH_TREADY : in std_logic;
TX0_CTL_TDATA : out std_logic_vector(31 downto 0);
TX0_CTL_TLAST : out std_logic;
TX0_CTL_TVALID : out std_logic;
TX0_CTL_TREADY : in std_logic
);
end entity; |
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