content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity xnor_gate is
port (
a_i : in std_logic; -- inputs
b_i : in std_logic;
c_o : out std_logic -- output
);
end entity xnor_gate;
architecture rtl of xnor_gate is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_6_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 06:48:17 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $... |
architecture rtl of fifo is
variable v_element : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-----------------------------------------------------------------------
-- The column entity implements all the components needed by a single
-- column of the AES state:
-- + two linear layer for the first tw... |
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.globals.all;
-----------------------------------------------------------------------
-- The column entity implements all the components needed by a single
-- column of the AES state:
-- + two linear layer for the first tw... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
--
-- UART for ZPUINO - Receiver unit
--
-- Copyright 2011 Alvaro Lopes <alvieboy@alvie.com>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Red... |
use work.bit_vector_pkg.all;
use work.tbu_bdd_pkg.all;
entity bit_vector_pkg_tb is
end entity bit_vector_pkg_tb;
architecture testbench of bit_vector_pkg_tb is begin
test_null_bit_vector: process is begin
describe("null_bit_vector");
should("generate a null vector with 1 element",
null_b... |
architecture RTL of ENTITY_NAME is
begin
process
begin
EXIT_LABEL : exit loop_label when a(23 downto 5) = 20;
exit loop_label when a(23 downto 5) = 20;
EXIT_LABEL : exit when a(23 downto 5) = 20;
exit when a(23 downto 5) = 20;
EXIT_LABEL : exit loop_label;
exit loop_label;
exit... |
------------------------------------------------------------------------------/
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------/
-- ____ ____
-- / /\/ /
-- /___/... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1') else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1') else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1')... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity faultify_top is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
aclk : in std_logic; -- interface clock
arst_n : in std_logic; -- interface reset
... |
library ieee;
use ieee.std_logic_1164.all;
-- somador completo (fulladder)
entity fulladder is
port (a, b, c: in std_logic;
soma, carry: out std_logic);
end fulladder;
architecture fulladder_beh of fulladder is
begin
soma <= (a xor b) xor c;
carry <= b when ((a xor b) = '0')
else c;
end fulladder_beh;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity StackPointer is
port (
DATA : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
LD : in STD_LOGIC;
INCR : in STD_LOGIC;
DECR : in STD_LOGIC;
CLK : in STD_LOGIC;
DOUT ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.i2s_controller;
library work;
use work.axi_streaming_dma_rx_fifo;
use work.axi_streaming_dma_tx_fifo;
use work.pl330_dma_fifo;
use work.axi_ctrlif;
entity ax... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:00:36 01/16/2014
-- Design Name:
-- Module Name: BoothPartProdGen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-- -------------------------------------------------------------
--
-- Generated Configuration for vgca_cpu
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
--... |
entity FIFO is
port (
I_PORT1 : in integer;
I_PORT2 : in std_logic;
I_PORTA : in t_user2;
I_PORT3 : in std_logic_vector(3 downto 0);
I_PORT4 : in signed(15 downto 0);
I_PORT5 : in unsigned(7 downto 0);
I_PORT6 : in std_ulogic;
I_PORT7 : in t_user1
);
end entity FIFO;
-- Violatio... |
-- file: multiplex.vhd
-------------------------------------
-- n bit multiplexer
-- Shauna Rae
-- October 18, 1999
library ieee;
use ieee.std_logic_1164.all;
--define the entity of multiplex
entity multiplex is
generic (data_width : positive := 16);
port(select_line: in std_logic;
in_a, in_b: in... |
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
a <= b;
end block;
BLOCK_LABEL : block is
begin
a <= b;
end block;
end architecture RTL;
|
----------------------------------------------------------------------------------
--! Company: Weizmann Institute of Science
--! Engineer: juna
--!
--! Create Date: 18/12/2014
--! Module Name: pulse_pdxx_pwxx
----------------------------------------------------------------------------------
--! Use s... |
----------------------------------------------------------------------------------
--! Company: Weizmann Institute of Science
--! Engineer: juna
--!
--! Create Date: 18/12/2014
--! Module Name: pulse_pdxx_pwxx
----------------------------------------------------------------------------------
--! Use s... |
----------------------------------------------------------------------------------
--! Company: Weizmann Institute of Science
--! Engineer: juna
--!
--! Create Date: 18/12/2014
--! Module Name: pulse_pdxx_pwxx
----------------------------------------------------------------------------------
--! Use s... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ... |
----------------------------------------------------------------------------------
-- Company: University of Paderborn
-- Engineer: Markus Happe
--
-- Create Date: 15:04:59 02/09/2011
-- Design Name:
-- Module Name: ring_oscillator - Behavioral
-- Project Name: Thermal Sensor Net
-- Target Devices: Virtex ... |
-----------------------------------
-- Module Name: CDiv - Divide --
-----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CDiv is
port(Cin : in std_logic;
TCvl : in integer;
Cout : out std_logic);
end CDiv;
-- Important val... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_harness
-- Date:2015-01-27
-- Author: Gideon
-- Description: Harness for USB Host Controller
---------------------------------------------------------------------------... |
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_harness
-- Date:2015-01-27
-- Author: Gideon
-- Description: Harness for USB Host Controller
---------------------------------------------------------------------------... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
ENTITY counterTb IS
Generic (
counter1Width : integer :=2;
counter2Width : integer :=5;
counter3Width : integer :=8;
counter4Width : integer :=16
);
END counterTb;
... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter10.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball_rom is
port(
addr: in std_logic_vector(3 downto 0);
data: out std_logic_vector(0 to 15)
);
end ball_rom;
architecture content of ball_rom is
type rom_type is array(0 to 15) of std_logic_vector(0 to 15);... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball_rom is
port(
addr: in std_logic_vector(3 downto 0);
data: out std_logic_vector(0 to 15)
);
end ball_rom;
architecture content of ball_rom is
type rom_type is array(0 to 15) of std_logic_vector(0 to 15);... |
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.caph_flow_pkg.caph_ports_t;
package caph_external_component is
component caph_toplevel is
generic (
IN_SIZE :posi... |
-- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_SHIFTREG
-- ============================================================
-- File Name: lpm_shiftreg1.vhd
-- Megafunction Name(s):
-- LPM_SHIFTREG
--
-- Simulation Library Files(s):
-- lpm
-- =========================... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port (
a_in : in std_ulogic_vector(9 downto 0);
b_out : out std_ulogic
);
end entity test;
architecture behaviour of test is
type array_type_t is array(0 to 1023) of std_ulogic;
constant ary : arr... |
library IEEE;
use IEEE.std_logic_1164.all;
entity fluxo_dados is
port ();
end fluxo_dados;
architecture estrutural of fluxo_dados is
component divisor is
port(
clock : in std_logic;
reset : in std_logic;
enable : in std_logic;
amostra : out std_logic;
conta4 :... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 12;
type lut_type is arra... |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 8;
constant AMPL_WIDTH : integer := 12;
type lut_type is arra... |
library verilog;
use verilog.vl_types.all;
entity \ABS\ is
port(
data : in vl_logic_vector(29 downto 0);
result : out vl_logic_vector(29 downto 0)
);
end \ABS\;
|
library verilog;
use verilog.vl_types.all;
entity \ABS\ is
port(
data : in vl_logic_vector(29 downto 0);
result : out vl_logic_vector(29 downto 0)
);
end \ABS\;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity BlkRAM is
port (
clk : in std_logic;
addr : in blkram_addr;
inst : out instruction_t := (others => '0');
w : in blkram_write_t);
end entity;
architecture behavioral of BlkRAM is
type... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confiden... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY ParametrizationExample IS
GENERIC(
PARAM_0 : INTEGER := 0;
PARAM_10 : INTEGER := 10;
PARAM_1_sll_512 : STD_LOGIC_VECTOR(512 DOWNTO 0) := "100000000000000000000000000000000000000000000... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
entity wbarb2_1 is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
... |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the... |
LIBRARY ieee;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
PACKAGE processor_functions IS
TYPE opcode IS (load, store, add, nott, andd, orr, xorr, inc, sub, branch);
FUNCTION Decode (word: STD_LOGIC_VECTOR) RETURN opcode;
CONSTANT n: integer := 16;
CONSTANT wordlen: integer := 16;
CONSTANT ... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:38:15 2017
-- Host : GILAMONSTER running 64-bit major rel... |
entity tb_ent is
end tb_ent;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_ent is
signal clk : std_logic;
signal dout : std_logic;
signal set : std_logic;
signal reset : std_logic;
begin
dut: entity work.ent
port map (
set => set,
reset => reset,
q => dout,
... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
entity register_bank is
port(
clk,rst : in std_logic;
data : in std_logic_vector(7 downto 0);
write_addr : in std_logic_vector(3 downto 0);
read_addr1 : in std_logic_vector(3... |
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity fft_2048ch_6a_core_ip is
port (
pol0_in0 : in std_logic_vector( 18-1 downto 0 );
pol0_in1 : in std_logic_vector( 18-1 downto 0 );
pol1_in0 : in std_logic_vector( 18-... |
-- $Id: serport.vhd 437 2011-12-09 19:38:07Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux4x1 is
port (w, x, y, z: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(3 downto 0)
);
end mux4x1;
architecture circuito of mux4x1 is
begin
m <= w when s = "00" else
x when s = "01" else
y when s = "10"... |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux4x1 is
port (w, x, y, z: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
m: out std_logic_vector(3 downto 0)
);
end mux4x1;
architecture circuito of mux4x1 is
begin
m <= w when s = "00" else
x when s = "01" else
y when s = "10"... |
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\Control_Unit.vhd
-- Created: 2014-03-05 16:19:14
--
-- Generated by MATLAB 7.12 and Simulink HDL Coder 2.1
--
-- -------------------------------------------------------------
-- ------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cic_up is
generic(
num_bits : natural := 16; -- How many bits in our incoming data?
num_stages : natural := 3; -- How many stages in the CIC? (N)
resamp : natural := 32; -- By what factor are w... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cic_up is
generic(
num_bits : natural := 16; -- How many bits in our incoming data?
num_stages : natural := 3; -- How many stages in the CIC? (N)
resamp : natural := 32; -- By what factor are w... |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpu_config.all;
entity wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := maxIObit;
ADDRESS_LOW: integer := maxIObit
);
port (
wb_clk_i: in std_logic;
wb_rst_i:... |
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