content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc783.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p12n04i00783a IS
port ( c1 : out bit_vector;
c2 : inout bit_vector;
c3 : buffer bit_vector;
c4 : linkage bit_vector);
END c01s01b01x02p12n04i00783ent_a;
ARCHITECTURE c01s01b01x02p12n04i00783arch_a OF c01s01b01x02p12n04i00783ent_a IS
BEGIN
END c01s01b01x02p12n04i00783arch_a;
ENTITY c01s01b01x02p12n04i00783ent IS
END c01s01b01x02p12n04i00783ent;
ARCHITECTURE c01s01b01x02p12n04i00783arch OF c01s01b01x02p12n04i00783ent IS
component c01s01b01x02p12n04i00783ent_b
port ( c1 : out bit_vector;
c2 : inout bit_vector;
c3 : buffer bit_vector;
c4 : linkage bit_vector);
end component;
for L : c01s01b01x02p12n04i00783ent_b use entity work.c01s01b01x02p12n04i00783ent_a(c01s01b01x02p12n04i00783arch_a);
BEGIN
L : ch01010102_p01204_03_ent_b
port map ( OPEN, -- Failure_here
OPEN, -- Failure_here
OPEN, -- Failure_here
OPEN); -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p12n04i00783 - The port which is of mode other than in and whose type is unconstrained may not be unconnected."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p12n04i00783arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc783.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p12n04i00783a IS
port ( c1 : out bit_vector;
c2 : inout bit_vector;
c3 : buffer bit_vector;
c4 : linkage bit_vector);
END c01s01b01x02p12n04i00783ent_a;
ARCHITECTURE c01s01b01x02p12n04i00783arch_a OF c01s01b01x02p12n04i00783ent_a IS
BEGIN
END c01s01b01x02p12n04i00783arch_a;
ENTITY c01s01b01x02p12n04i00783ent IS
END c01s01b01x02p12n04i00783ent;
ARCHITECTURE c01s01b01x02p12n04i00783arch OF c01s01b01x02p12n04i00783ent IS
component c01s01b01x02p12n04i00783ent_b
port ( c1 : out bit_vector;
c2 : inout bit_vector;
c3 : buffer bit_vector;
c4 : linkage bit_vector);
end component;
for L : c01s01b01x02p12n04i00783ent_b use entity work.c01s01b01x02p12n04i00783ent_a(c01s01b01x02p12n04i00783arch_a);
BEGIN
L : ch01010102_p01204_03_ent_b
port map ( OPEN, -- Failure_here
OPEN, -- Failure_here
OPEN, -- Failure_here
OPEN); -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p12n04i00783 - The port which is of mode other than in and whose type is unconstrained may not be unconnected."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p12n04i00783arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc783.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p12n04i00783a IS
port ( c1 : out bit_vector;
c2 : inout bit_vector;
c3 : buffer bit_vector;
c4 : linkage bit_vector);
END c01s01b01x02p12n04i00783ent_a;
ARCHITECTURE c01s01b01x02p12n04i00783arch_a OF c01s01b01x02p12n04i00783ent_a IS
BEGIN
END c01s01b01x02p12n04i00783arch_a;
ENTITY c01s01b01x02p12n04i00783ent IS
END c01s01b01x02p12n04i00783ent;
ARCHITECTURE c01s01b01x02p12n04i00783arch OF c01s01b01x02p12n04i00783ent IS
component c01s01b01x02p12n04i00783ent_b
port ( c1 : out bit_vector;
c2 : inout bit_vector;
c3 : buffer bit_vector;
c4 : linkage bit_vector);
end component;
for L : c01s01b01x02p12n04i00783ent_b use entity work.c01s01b01x02p12n04i00783ent_a(c01s01b01x02p12n04i00783arch_a);
BEGIN
L : ch01010102_p01204_03_ent_b
port map ( OPEN, -- Failure_here
OPEN, -- Failure_here
OPEN, -- Failure_here
OPEN); -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p12n04i00783 - The port which is of mode other than in and whose type is unconstrained may not be unconnected."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p12n04i00783arch;
|
-------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0);
signal rd_cnt : unsigned(5 downto 0);
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : ZZ_TOP.vhd
--
-- Project : JPEG_ENC
--
-- Module : ZZ_TOP
--
-- Content : ZigZag Top level
--
-- Description : Zig Zag scan
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity ZZ_TOP is
port
(
CLK : in std_logic;
RST : in std_logic;
-- CTRL
start_pb : in std_logic;
ready_pb : out std_logic;
zig_sm_settings : in T_SM_SETTINGS;
-- Quantizer
qua_buf_sel : in std_logic;
qua_rdaddr : in std_logic_vector(5 downto 0);
qua_data : out std_logic_vector(11 downto 0);
-- FDCT
fdct_buf_sel : out std_logic;
fdct_rd_addr : out std_logic_vector(5 downto 0);
fdct_data : in std_logic_vector(11 downto 0);
fdct_rden : out std_logic
);
end entity ZZ_TOP;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of ZZ_TOP is
signal dbuf_data : std_logic_vector(11 downto 0);
signal dbuf_q : std_logic_vector(11 downto 0);
signal dbuf_we : std_logic;
signal dbuf_waddr : std_logic_vector(6 downto 0);
signal dbuf_raddr : std_logic_vector(6 downto 0);
signal zigzag_di : std_logic_vector(11 downto 0);
signal zigzag_divalid : std_logic;
signal zigzag_dout : std_logic_vector(11 downto 0);
signal zigzag_dovalid : std_logic;
signal wr_cnt : unsigned(5 downto 0);
signal rd_cnt : unsigned(5 downto 0);
signal rd_en_d : std_logic_vector(5 downto 0);
signal rd_en : std_logic;
signal fdct_buf_sel_s : std_logic;
signal zz_rd_addr : std_logic_vector(5 downto 0);
signal fifo_empty : std_logic;
signal fifo_rden : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
fdct_rd_addr <= std_logic_vector(zz_rd_addr);
qua_data <= dbuf_q;
fdct_buf_sel <= fdct_buf_sel_s;
fdct_rden <= rd_en;
-------------------------------------------------------------------
-- ZigZag Core
-------------------------------------------------------------------
U_zigzag : entity work.zigzag
generic map
(
RAMADDR_W => 6,
RAMDATA_W => 12
)
port map
(
rst => RST,
clk => CLK,
di => zigzag_di,
divalid => zigzag_divalid,
rd_addr => rd_cnt,
fifo_rden => fifo_rden,
fifo_empty => fifo_empty,
dout => zigzag_dout,
dovalid => zigzag_dovalid,
zz_rd_addr => zz_rd_addr
);
zigzag_di <= fdct_data;
zigzag_divalid <= rd_en_d(1);
-------------------------------------------------------------------
-- DBUF
-------------------------------------------------------------------
U_RAMZ : entity work.RAMZ
generic map
(
RAMADDR_W => 7,
RAMDATA_W => 12
)
port map
(
d => dbuf_data,
waddr => dbuf_waddr,
raddr => dbuf_raddr,
we => dbuf_we,
clk => CLK,
q => dbuf_q
);
dbuf_data <= zigzag_dout;
dbuf_waddr <= (not qua_buf_sel) & std_logic_vector(wr_cnt);
dbuf_we <= zigzag_dovalid;
dbuf_raddr <= qua_buf_sel & qua_rdaddr;
-------------------------------------------------------------------
-- FIFO Ctrl
-------------------------------------------------------------------
p_fifo_ctrl : process(CLK, RST)
begin
if RST = '1' then
fifo_rden <= '0';
elsif CLK'event and CLK = '1' then
if fifo_empty = '0' then
fifo_rden <= '1';
else
fifo_rden <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Counter1
-------------------------------------------------------------------
p_counter1 : process(CLK, RST)
begin
if RST = '1' then
rd_en <= '0';
rd_en_d <= (others => '0');
rd_cnt <= (others => '0');
elsif CLK'event and CLK = '1' then
rd_en_d <= rd_en_d(rd_en_d'length-2 downto 0) & rd_en;
if start_pb = '1' then
rd_cnt <= (others => '0');
rd_en <= '1';
end if;
if rd_en = '1' then
if rd_cnt = 64-1 then
rd_cnt <= (others => '0');
rd_en <= '0';
else
rd_cnt <= rd_cnt + 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- wr_cnt
-------------------------------------------------------------------
p_wr_cnt : process(CLK, RST)
begin
if RST = '1' then
wr_cnt <= (others => '0');
ready_pb <= '0';
elsif CLK'event and CLK = '1' then
ready_pb <= '0';
if start_pb = '1' then
wr_cnt <= (others => '0');
end if;
if zigzag_dovalid = '1' then
if wr_cnt = 64-1 then
wr_cnt <= (others => '0');
else
wr_cnt <=wr_cnt + 1;
end if;
-- give ready ahead to save cycles!
if wr_cnt = 64-1-3 then
ready_pb <= '1';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- fdct_buf_sel
-------------------------------------------------------------------
p_buf_sel : process(CLK, RST)
begin
if RST = '1' then
fdct_buf_sel_s <= '0';
elsif CLK'event and CLK = '1' then
if start_pb = '1' then
fdct_buf_sel_s <= not fdct_buf_sel_s;
end if;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
package fifo_pkg is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
end package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity interruptgen is
port(
I_clk: in std_logic := '0';
I_interrupt: in std_logic := '0';
O_interrupt: out std_logic := '0'
);
end interruptgen;
architecture Behavioral of interruptgen is
constant CYCLELENGTH: integer := 3000000;
signal act: boolean := false;
begin
-- generate interrupt signals if active
process(I_clk)
variable clockcnt: integer range 0 to CYCLELENGTH;
begin
if rising_edge(I_clk) then
O_interrupt <= '0';
if(clockcnt < (CYCLELENGTH / 30) and act) then
O_interrupt <= '1';
end if;
clockcnt := clockcnt + 1;
if(clockcnt >= CYCLELENGTH) then
clockcnt := 0;
end if;
end if;
end process;
-- toggle activity
process(I_interrupt)
begin
if rising_edge(I_interrupt) then
act <= not act;
end if;
end process;
end Behavioral; |
-- $Id: s3boardlib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: s3boardlib
-- Description: S3BOARD components
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-07-09 391 1.3.5 move s3_rs232_iob_int_ext to bpgenlib
-- 2011-07-08 390 1.3.4 move s3_(dispdrv|humanio*) to bpgenlib
-- 2011-07-03 387 1.3.3 move s3_rs232_iob_(int|ext) to bpgenlib
-- 2010-12-30 351 1.3.2 use rblib; rename human s3_humanio_rri -> _rbus
-- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50
-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib)
-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.2.1 rename memctl_s3sram -> s3_sram_memctl; _usp->_fusp
-- 2010-05-01 286 1.2 added s3board_usp_aif (base+pm1_rs232)
-- 2010-04-17 278 1.1.6 rename, prefix dispdrv,sram_summy with s3_;
-- add s3_rs232_iob_(int|ext|int_ext)
-- 2010-04-11 276 1.1.5 add DEBOUNCE for s3_humanio
-- 2010-04-10 275 1.1.4 add s3_humanio
-- 2008-02-17 117 1.1.3 memctl_s3sram: use req,we interface
-- 2008-01-20 113 1.1.2 rename memdrv -> memctl_s3sram
-- 2007-12-16 101 1.1.1 use _N for active low
-- 2007-12-09 100 1.1 add sram memory signals; sram_dummy; memdrv
-- 2007-09-23 84 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package s3boardlib is
component s3board_aif is -- S3BOARD, abstract iface, base
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end component;
component s3board_fusp_aif is -- S3BOARD, abstract iface, base+fusp
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
I_BTN : in slv4; -- s3 buttons
O_LED : out slv8; -- s3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32; -- sram: data lines
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
component s3_sram_dummy is -- SRAM protection dummy
port (
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end component;
component s3_sram_memctl is -- SRAM controller
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv18; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end component;
end package s3boardlib;
|
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_left_shift_by_2 is
end test_left_shift_by_2;
architecture behavior of test_left_shift_by_2 is
signal data_in: std_logic_vector(0 to 27);
signal data_out: std_logic_vector(0 to 27);
begin
uut: entity left_shift_by_2 port map (data_in, data_out);
testprocess: process is
begin
data_in<="0111111111111111111111111110";
wait for 10 ns;
end process testprocess;
end architecture behavior;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : This is NOT an example of how to implement a UART core. This is just
-- a simple test vehicle that can be used to demonstrate the functionality
-- of the UVVM VVC Framework.
--
-- See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.uart_pif_pkg.all;
use work.uart_pkg.all;
entity uart_core is
generic (
GC_START_BIT : std_logic := '0';
GC_STOP_BIT : std_logic := '1';
GC_CLOCKS_PER_BIT : integer := 16);
port(
-- DSP interface and general control signals
clk : in std_logic;
arst : in std_logic;
-- PIF-core interface
p2c : in t_p2c;
c2p : out t_c2p;
-- Interrupt related signals
rx_a : in std_logic;
tx : out std_logic
);
end entity uart_core;
architecture rtl of uart_core is
type t_slv_array is array (3 downto 0) of std_logic_vector(7 downto 0);
-- tx signals
signal tx_data : t_slv_array:= (others => (others => '0'));
signal tx_buffer : std_logic_vector(7 downto 0) := (others => '0');
signal tx_data_valid : std_logic := '0';
signal tx_ready : std_logic := '0';
signal tx_active : std_logic := '0';
signal tx_clk_counter : unsigned(f_log2(GC_CLOCKS_PER_BIT)-1 downto 0) := (others => '0');
-- count through the bits (12 total)
signal tx_bit_counter : unsigned(3 downto 0) := (others => '0');
-- receive signals
signal rx_buffer : std_logic_vector(7 downto 0) := (others => '0');
signal rx_active : std_logic := '0';
signal rx_clk_counter : unsigned(f_log2(GC_CLOCKS_PER_BIT)-1 downto 0) := (others => '0');
-- count through the bits (12 total)
signal rx_bit_counter : unsigned(3 downto 0) := (others => '0');
signal rx_bit_samples : std_logic_vector(GC_CLOCKS_PER_BIT-1 downto 0) := (others => '0');
signal rx_data : t_slv_array := (others => (others => '0'));
signal rx_data_valid : std_logic := '0';
signal rx_data_full : std_logic := '0';
-- rx synced to clk
signal rx_s : std_logic_vector(1 downto 0) := (others => '1'); -- synchronized serial data input
signal rx_just_active : boolean; -- helper signal when we start receiving
signal parity_err : std_logic := '0'; -- parity error detected
signal stop_err : std_logic := '0'; -- stop error detected
signal transient_err : std_logic := '0'; -- data value is transient
signal c2p_i : t_c2p; -- Internal version of output
begin
c2p <= c2p_i;
c2p_i.aro_tx_ready <= tx_ready;
c2p_i.aro_rx_data_valid <= rx_data_valid;
-- synchronize rx input (async)
p_rx_s : process(clk, arst) is
begin
if arst = '1' then
rx_s <= (others => '1');
elsif rising_edge(clk) then
rx_s <= rx_s(0) & rx_a;
end if;
end process p_rx_s;
---------------------------------------------------------------------------
-- Transmit process; drives tx serial output.
--
-- Stores 4 pending bytes in the tx_data array, and the byte currently
-- being output in the tx_buffer register.
--
-- Tx_buffer is filled with data from tx_data(0) if there is valid data
-- available (tx_data_valid is active), and no other byte is currently
-- being output (tx_active is inactive).
--
-- Data received via SBI is inserted in tx_data at the index pointed to
-- by vr_tx_data_idx. vr_tx_data_idx is incremented when a new byte is
-- received via SBI, and decremented when a new byte is loaded into
-- tx_buffer.
---------------------------------------------------------------------------
uart_tx : process (clk, arst) is
variable vr_tx_data_idx : unsigned(2 downto 0) := (others => '0');
begin -- process uart_tx
if arst = '1' then -- asynchronous reset (active high)
tx_data <= (others => (others => '0'));
tx_buffer <= (others => '0');
tx_data_valid <= '0';
tx_ready <= '1';
tx_active <= '0';
tx_bit_counter <= (others => '0');
tx_clk_counter <= (others => '0');
tx <= '1';
vr_tx_data_idx := (others => '0');
elsif rising_edge(clk) then -- rising clock edge
-- There is valid data in tx_data.
-- Load the tx_buffer and activate TX operation.
-- Decrement vr_tx_data_idx.
if tx_data_valid = '1' and tx_active = '0' then
tx_active <= '1';
tx_buffer <= tx_data(0);
tx_data <= x"00" & tx_data(3 downto 1);
if vr_tx_data_idx > 0 then
-- Decrement idx
if vr_tx_data_idx < 3 then
vr_tx_data_idx := vr_tx_data_idx - 1;
else -- vr_tx_data_idx = 3
-- Special case for idx=3 (max).
-- When tx_data is full (tx_ready = '0'), we do not wish to
-- decrement the idx. The reason is that the idx points
-- to where the next incoming data byte shall be stored,
-- which is still idx 3.
-- Therefore, only decrement when tx_ready = '1'.
if tx_ready = '1' then
vr_tx_data_idx := vr_tx_data_idx - 1;
end if;
end if;
else
-- vr_tx_data_idx already at 0,
-- which means that the final byte in tx_data
-- was just loaded into tx_buffer, no more valid
-- data left in tx_data.
tx_data_valid <= '0';
tx_active <= '0';
end if;
-- Tx is now ready to receive another byte.
tx_ready <= '1';
end if;
-- loading the tx_data shift reg
if tx_ready = '1' then
if p2c.awo_tx_data_we = '1' then
tx_data(to_integer(vr_tx_data_idx)) <= p2c.awo_tx_data;
tx_data_valid <= '1';
-- Increment idx if tx_data not full.
if vr_tx_data_idx < 3 then
vr_tx_data_idx := vr_tx_data_idx + 1;
else -- tx_data full
tx_ready <= '0';
end if;
end if;
end if;
if tx_active = '0' then
-- default
tx_clk_counter <= (others => '0');
tx_bit_counter <= (others => '0');
tx <= '1'; -- idle as default
else
-- tx clock counter keeps running when active
if tx_clk_counter <= GC_CLOCKS_PER_BIT - 1 then
tx_clk_counter <= tx_clk_counter + 1;
else
tx_clk_counter <= (others => '0');
end if;
-- GC_CLOCKS_PER_BIT tx clocks per tx bit
if tx_clk_counter >= GC_CLOCKS_PER_BIT - 1 then
tx_bit_counter <= tx_bit_counter + 1;
end if;
case to_integer(tx_bit_counter) is
when 0 =>
tx <= GC_START_BIT;
when 1 to 8 =>
-- mux out the correct tx bit
tx <= tx_buffer(to_integer(tx_bit_counter)-1);
when 9 =>
tx <= odd_parity(tx_buffer);
when 10 =>
tx <= GC_STOP_BIT;
when others =>
tx <= '1';
tx_active <= '0';
end case;
end if;
end if;
end process uart_tx;
-- Data is set on the output when available on rx_data(0)
c2p_i.aro_rx_data <= rx_data(0);
---------------------------------------------------------------------------
-- Receive process
---------------------------------------------------------------------------
uart_rx : process (clk, arst) is
variable vr_rx_data_idx : unsigned(2 downto 0) := (others => '0');
begin -- process uart_tx
if arst = '1' then -- asynchronous reset (active high)
rx_active <= '0';
rx_just_active <= false;
rx_data <= (others => (others => '0'));
rx_data_valid <= '0';
rx_bit_samples <= (others => '1');
rx_buffer <= (others => '0');
rx_clk_counter <= (others => '0');
rx_bit_counter <= (others => '0');
stop_err <= '0';
parity_err <= '0';
transient_err <= '0';
vr_rx_data_idx := (others => '0');
rx_data_full <= '1';
elsif rising_edge(clk) then -- rising clock edge
-- Perform read.
-- When there is data available in rx_data,
-- output the data when read enable detected.
if p2c.aro_rx_data_re = '1' and rx_data_valid = '1' then
rx_data <= x"00" & rx_data(3 downto 1);
rx_data_full <= '0';
if vr_rx_data_idx > 0 then
vr_rx_data_idx := vr_rx_data_idx - 1;
if vr_rx_data_idx = 0 then -- rx_data empty
rx_data_valid <= '0';
end if;
end if;
end if;
-- always shift in new synchronized serial data
rx_bit_samples <= rx_bit_samples(GC_CLOCKS_PER_BIT-2 downto 0) & rx_s(1);
-- look for enough GC_START_BITs in rx_bit_samples vector
if rx_active = '0' and
(find_num_hits(rx_bit_samples, GC_START_BIT) >= GC_CLOCKS_PER_BIT-1) then
rx_active <= '1';
rx_just_active <= true;
end if;
if rx_active = '0' then
-- defaults
stop_err <= '0';
parity_err <= '0';
transient_err <= '0';
rx_clk_counter <= (others => '0');
rx_bit_counter <= (others => '0');
else
-- We could check when we first enter whether we find the full number
-- of start samples and adjust the time we start rx_clk_counter by a
-- clock cycle - to hit the eye of the rx data best possible.
if rx_just_active then
if find_num_hits(rx_bit_samples, GC_START_BIT) = GC_CLOCKS_PER_BIT then
-- reset rx_clk_counter
rx_clk_counter <= (others => '0');
end if;
rx_just_active <= false;
else
-- loop clk counter
if rx_clk_counter <= GC_CLOCKS_PER_BIT - 1 then
rx_clk_counter <= rx_clk_counter + 1;
else
rx_clk_counter <= (others => '0');
end if;
end if;
-- shift in data, check for consistency and forward
if rx_clk_counter >= GC_CLOCKS_PER_BIT - 1 then
rx_bit_counter <= rx_bit_counter + 1;
if transient_error(rx_bit_samples, GC_CLOCKS_PER_BIT - 2) then
transient_err <= '1';
end if;
-- are we done? not counting the start bit
if to_integer(rx_bit_counter) >= 9 then
rx_active <= '0';
end if;
case to_integer(rx_bit_counter) is
when 0 to 7 =>
-- mux in new bit
rx_buffer(to_integer(rx_bit_counter)) <= find_most_repeated_bit(rx_bit_samples);
when 8 =>
-- check parity
if (odd_parity(rx_buffer) /= find_most_repeated_bit(rx_bit_samples)) then
parity_err <= '1';
end if;
when 9 =>
-- check stop bit, and end byte receive
if find_most_repeated_bit(rx_bit_samples) /= GC_STOP_BIT then
stop_err <= '1';
end if;
rx_data(to_integer(vr_rx_data_idx)) <= rx_buffer;
rx_data_valid <= '1'; -- ready for higher level protocol
if vr_rx_data_idx < 3 then
vr_rx_data_idx := vr_rx_data_idx + 1;
else
rx_data_full <= '1';
end if;
when others =>
rx_active <= '0';
end case;
end if;
end if;
end if;
end process uart_rx;
p_busy_assert : process(clk) is
begin
if rising_edge(clk) then
assert not (p2c.awo_tx_data_we = '1' and tx_ready = '0')
report "Trying to transmit new UART data while transmitter is busy"
severity error;
end if;
end process;
assert stop_err /= '1'
report "Stop bit error detected!"
severity error;
assert parity_err /= '1'
report "Parity error detected!"
severity error;
assert transient_err /= '1'
report "Transient error detected!"
severity error;
end architecture rtl;
|
------------------------------------------------------------------------------
-- Title : Top FMC516 design
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-02-25
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top design for testing the integration/control of the FMC516
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-25 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_generic_pkg.all;
-- Ethernet MAC Modules and SDB structure
use work.ethmac_pkg.all;
-- Wishbone Fabric interface
use work.wr_fabric_pkg.all;
-- Etherbone slave core
use work.etherbone_pkg.all;
-- FMC516 definitions
use work.fmc_adc_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_fmc130m_4ch is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
rs232_txd_o : out std_logic;
rs232_rxd_i : in std_logic;
-----------------------------------------
-- PHY pins
-----------------------------------------
-- Clock and resets to PHY (GMII). Not used in MII mode (10/100)
mgtx_clk_o : out std_logic;
mrstn_o : out std_logic;
-- PHY TX
mtx_clk_pad_i : in std_logic;
mtxd_pad_o : out std_logic_vector(3 downto 0);
mtxen_pad_o : out std_logic;
mtxerr_pad_o : out std_logic;
-- PHY RX
mrx_clk_pad_i : in std_logic;
mrxd_pad_i : in std_logic_vector(3 downto 0);
mrxdv_pad_i : in std_logic;
mrxerr_pad_i : in std_logic;
mcoll_pad_i : in std_logic;
mcrs_pad_i : in std_logic;
-- MII
mdc_pad_o : out std_logic;
md_pad_b : inout std_logic;
-----------------------------
-- FMC130m_4ch ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------------------
-- General board status
-----------------------------------------
fmc_mmcm_lock_led_o : out std_logic;
fmc_pll_status_led_o : out std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
-- Directional leds
--led_south_o : out std_logic;
--led_east_o : out std_logic;
--led_north_o : out std_logic;
-- GPIO leds
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_fmc130m_4ch;
architecture rtl of dbe_bpm_fmc130m_4ch is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 9;
-- General Dual-port memory, Buffer Single-port memory, DMA control port, MAC,
--Etherbone, FMC516, Peripherals
-- Number of masters
--constant c_masters : natural := 9; -- LM32 master, Data + Instruction,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone, RS232-Syscon
constant c_masters : natural := 7; -- RS232-Syscon,
--DMA read+write master, Ethernet MAC, Ethernet MAC adapter read+write master, Etherbone
constant c_dpram_size : natural := 131072/4; -- in 32-bit words (128KB)
--constant c_dpram_ethbuf_size : natural := 32768/4; -- in 32-bit words (32KB)
constant c_dpram_ethbuf_size : natural := 65536/4; -- in 32-bit words (64KB)
-- GPIO num pinscalc
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- TICs counter period. 100MHz clock -> msec granularity
constant c_tics_cntr_period : natural := 100000;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- number of the ADC reference clock used for all downstream
-- FPGA logic
constant c_adc_ref_clk : natural := 1;
constant c_xwb_etherbone_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"68202b22",
version => x"00000001",
date => x"20120912",
name => "GSI_ETHERBONE_CFG ")));
constant c_xwb_ethmac_adapter_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", --32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"2ff9a28e",
version => x"00000001",
date => x"20130701",
name => "ETHMAC_ADAPTER ")));
-- FMC130m_4ch layout. Size (0x00000FFF) is larger than needed. Just to be sure
-- no address overlaps will occur
--constant c_fmc516_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- FMC130m_4ch
constant c_fmc130m_4ch_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000800");
-- General peripherals layout. UART, LEDs (GPIO), Buttons (GPIO) and Tics counter
constant c_periph_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00000FFF", x"00000400");
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 128KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(f_xwb_dpram(c_dpram_ethbuf_size),
x"20000000"), -- 64KB RAM
3 => f_sdb_embed_device(c_xwb_dma_sdb, x"30004000"), -- DMA control port
4 => f_sdb_embed_device(c_xwb_ethmac_sdb, x"30005000"), -- Ethernet MAC control port
5 => f_sdb_embed_device(c_xwb_ethmac_adapter_sdb, x"30006000"), -- Ethernet Adapter control port
6 => f_sdb_embed_device(c_xwb_etherbone_sdb, x"30007000"), -- Etherbone control port
7 => f_sdb_embed_bridge(c_fmc130m_4ch_bridge_sdb, x"30010000"), -- FMC130m_4ch control port
8 => f_sdb_embed_bridge(c_periph_bridge_sdb, x"30020000") -- General peripherals control port
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well
constant c_sdb_address : t_wishbone_address := x"30000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_sys_rst : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_sys_n : std_logic;
signal rs232_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelay_ctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- Ethernet MAC signals
signal ethmac_int : std_logic;
signal ethmac_md_in : std_logic;
signal ethmac_md_out : std_logic;
signal ethmac_md_oe : std_logic;
signal mtxd_pad_int : std_logic_vector(3 downto 0);
signal mtxen_pad_int : std_logic;
signal mtxerr_pad_int : std_logic;
signal mdc_pad_int : std_logic;
-- Ethrnet MAC adapter signals
signal irq_rx_done : std_logic;
signal irq_tx_done : std_logic;
-- Etherbone signals
signal wb_ebone_out : t_wishbone_master_out;
signal wb_ebone_in : t_wishbone_master_in;
signal eb_src_i : t_wrf_source_in;
signal eb_src_o : t_wrf_source_out;
signal eb_snk_i : t_wrf_sink_in;
signal eb_snk_o : t_wrf_sink_out;
-- DMA signals
signal dma_int : std_logic;
-- FMC130m_4ch Signals
signal wbs_fmc130m_4ch_in_array : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
signal wbs_fmc130m_4ch_out_array : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal fmc_mmcm_lock_int : std_logic;
signal fmc_pll_status_int : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
signal fmc_130m_4ch_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_130m_4ch_data : std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
signal fmc_130m_4ch_data_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc_debug : std_logic;
signal reset_adc_counter : unsigned(6 downto 0) := (others => '0');
signal fmc_130m_4ch_rst_n : std_logic_vector(c_num_adc_channels-1 downto 0);
-- fmc130m_4ch Debug
signal fmc130m_4ch_debug_valid_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc130m_4ch_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
signal sys_spi_din_int : std_logic;
signal sys_spi_miosio_oe_n_int : std_logic;
signal sys_spi_cs_adc0_n_int : std_logic;
signal sys_spi_cs_adc1_n_int : std_logic;
signal sys_spi_cs_adc2_n_int : std_logic;
signal sys_spi_cs_adc3_n_int : std_logic;
signal lmk_lock_int : std_logic;
signal lmk_sync_int : std_logic;
signal lmk_uwire_latch_en_int : std_logic;
signal lmk_uwire_data_int : std_logic;
signal lmk_uwire_clock_int : std_logic;
signal fmc_reset_adcs_n_int : std_logic;
signal fmc_reset_adcs_n_out : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal gpio_leds_int : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
signal CONTROL2 : std_logic_vector(35 downto 0);
signal CONTROL3 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 2 signals
signal TRIG_ILA2_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA2_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 3 signals
signal TRIG_ILA3_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA3_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
--component chipscope_icon_2_port
--port (
-- CONTROL0 : inout std_logic_vector(35 downto 0);
-- CONTROL1 : inout std_logic_vector(35 downto 0)
--);
--end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0);
CONTROL3 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
cmp_reset : gc_reset
generic map(
g_clocks => 1 -- CLK_SYS
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
--clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n and rs232_rstn;
clk_sys_rst <= not clk_sys_rstn;
mrstn_o <= clk_sys_rstn;
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
rst_button_sys_n <= not rst_button_sys;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
--cmp_lm32 : xwb_lm32
--generic map(
-- g_profile => "medium_icache_debug"
--) -- Including JTAG and I-cache (no divide)
--port map(
-- clk_sys_i => clk_sys,
-- rst_n_i => lm32_rstn,
-- irq_i => lm32_interrupt,
-- dwb_o => cbar_slave_i(0), -- Data bus
-- dwb_i => cbar_slave_o(0),
-- iwb_o => cbar_slave_i(1), -- Instruction bus
-- iwb_i => cbar_slave_o(1)
--);
-- Interrupt '0' is Ethmac.
-- Interrupt '1' is DMA completion.
-- Interrupt '2' is Button(0).
-- Interrupt '3' is Ethernet Adapter RX completion.
-- Interrupt '4' is Ethernet Adapter TX completion.
-- Interrupts 31 downto 5 are disabled
lm32_interrupt <= (0 => ethmac_int, 1 => dma_int, 2 => not buttons_i(0), 3 => irq_rx_done,
4 => irq_tx_done, others => '0');
cmp_xwb_rs232_syscon : xwb_rs232_syscon
generic map (
g_ma_interface_mode => PIPELINED,
g_ma_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rstn_i => '1', -- No need for resetting the controller
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rs232_rstn,
-- WISHBONE master
wb_master_i => cbar_slave_o(0),
wb_master_o => cbar_slave_i(0)
);
-- A DMA controller is master 2+3, slave 3, and interrupt 1
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
r_master_i => cbar_slave_o(1),
r_master_o => cbar_slave_i(1),
w_master_i => cbar_slave_o(2),
w_master_o => cbar_slave_i(2),
interrupt_o => dma_int
);
-- Slave 0+1 is the RAM. Load a input file containing the embedded software
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
--g_init_file => "../../../embedded-sw/dbe.ram",
--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
--g_must_have_init_file => true,
g_must_have_init_file => false,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
);
-- Slave 2 is the RAM Buffer for Ethernet MAC.
cmp_ethmac_buf_ram : xwb_dpram
generic map(
g_size => c_dpram_ethbuf_size,
g_init_file => "",
g_must_have_init_file => false,
g_slave1_interface_mode => CLASSIC,
--g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE
--g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(2),
slave1_o => cbar_master_i(2),
-- Second port connected to the crossbar
slave2_i => cc_dummy_slave_in, -- CYC always low
slave2_o => open
);
-- The Ethernet MAC is master 4, slave 4
cmp_xwb_ethmac : xwb_ethmac
generic map (
--g_ma_interface_mode => PIPELINED,
g_ma_interface_mode => CLASSIC, -- NOT used for now
--g_ma_address_granularity => WORD,
g_ma_address_granularity => BYTE, -- NOT used for now
g_sl_interface_mode => PIPELINED,
--g_sl_interface_mode => CLASSIC,
--g_sl_address_granularity => WORD
g_sl_address_granularity => BYTE
)
port map(
-- WISHBONE common
wb_clk_i => clk_sys,
wb_rst_i => clk_sys_rst,
-- WISHBONE slave
wb_slave_in => cbar_master_o(4),
wb_slave_out => cbar_master_i(4),
-- WISHBONE master
wb_master_in => cbar_slave_o(3),
wb_master_out => cbar_slave_i(3),
-- PHY TX
mtx_clk_pad_i => mtx_clk_pad_i,
--mtxd_pad_o => mtxd_pad_o,
mtxd_pad_o => mtxd_pad_int,
--mtxen_pad_o => mtxen_pad_o,
mtxen_pad_o => mtxen_pad_int,
--mtxerr_pad_o => mtxerr_pad_o,
mtxerr_pad_o => mtxerr_pad_int,
-- PHY RX
mrx_clk_pad_i => mrx_clk_pad_i,
mrxd_pad_i => mrxd_pad_i,
mrxdv_pad_i => mrxdv_pad_i,
mrxerr_pad_i => mrxerr_pad_i,
mcoll_pad_i => mcoll_pad_i,
mcrs_pad_i => mcrs_pad_i,
-- MII
--mdc_pad_o => mdc_pad_o,
mdc_pad_o => mdc_pad_int,
md_pad_i => ethmac_md_in,
md_pad_o => ethmac_md_out,
md_padoe_o => ethmac_md_oe,
-- Interrupt
int_o => ethmac_int
);
-- Tri-state buffer for MII config
md_pad_b <= ethmac_md_out when ethmac_md_oe = '1' else 'Z';
ethmac_md_in <= md_pad_b;
mtxd_pad_o <= mtxd_pad_int;
mtxen_pad_o <= mtxen_pad_int;
mtxerr_pad_o <= mtxerr_pad_int;
mdc_pad_o <= mdc_pad_int;
-- The Ethernet MAC Adapter is master 5+6, slave 5
cmp_xwb_ethmac_adapter : xwb_ethmac_adapter
port map(
clk_i => clk_sys,
rstn_i => clk_sys_rstn,
wb_slave_o => cbar_master_i(5),
wb_slave_i => cbar_master_o(5),
tx_ram_o => cbar_slave_i(4),
tx_ram_i => cbar_slave_o(4),
rx_ram_o => cbar_slave_i(5),
rx_ram_i => cbar_slave_o(5),
rx_eb_o => eb_snk_i,
rx_eb_i => eb_snk_o,
tx_eb_o => eb_src_i,
tx_eb_i => eb_src_o,
irq_tx_done_o => irq_tx_done,
irq_rx_done_o => irq_rx_done
);
-- The Etherbone is slave 6
cmp_eb_slave_core : eb_slave_core
generic map(
g_sdb_address => x"00000000" & c_sdb_address
)
port map
(
clk_i => clk_sys,
nRst_i => clk_sys_rstn,
-- EB streaming sink
snk_i => eb_snk_i,
snk_o => eb_snk_o,
-- EB streaming source
src_i => eb_src_i,
src_o => eb_src_o,
-- WB slave - Cfg IF
cfg_slave_o => cbar_master_i(6),
cfg_slave_i => cbar_master_o(6),
-- WB master - Bus IF
master_o => wb_ebone_out,
master_i => wb_ebone_in
);
cbar_slave_i(6) <= wb_ebone_out;
wb_ebone_in <= cbar_slave_o(6);
-- The FMC130M_4CH is slave 7
cmp_xwb_fmc130m_4ch : xwb_fmc130m_4ch
generic map(
g_fpga_device => "VIRTEX6",
g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
g_address_granularity => BYTE,
--g_adc_clk_period_values => default_adc_clk_period_values,
g_adc_clk_period_values => (8.88, 8.88, 8.88, 8.88),
--g_use_clk_chains => default_clk_use_chain,
-- using clock1 from fmc130m_4ch (CLK2_ M2C_P, CLK2_ M2C_M pair)
-- using clock0 from fmc130m_4ch.
-- BUFIO can drive half-bank only, not the full IO bank
g_use_clk_chains => "1111",
g_with_bufio_clk_chains => "0000",
g_with_bufr_clk_chains => "1111",
g_use_data_chains => "1111",
--g_map_clk_data_chains => (-1,-1,-1,-1),
-- Clock 1 is the adc reference clock
g_ref_clk => c_adc_ref_clk,
g_packet_size => 32,
g_sim => 0
)
port map(
sys_clk_i => clk_sys,
sys_rst_n_i => clk_sys_rstn,
sys_clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i => cbar_master_o(7),
wb_slv_o => cbar_master_i(7),
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_int,
fmc_led2_o => fmc_led2_int,
fmc_led3_o => fmc_led3_int,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => fmc_130m_4ch_clk,
adc_clk2x_o => fmc_130m_4ch_clk2x,
adc_rst_n_o => fmc_130m_4ch_rst_n,
adc_data_o => fmc_130m_4ch_data,
adc_data_valid_o => fmc_130m_4ch_data_valid,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_int,
fmc_pll_status_o => fmc_pll_status_int,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i => wbs_fmc130m_4ch_in_array,
wbs_source_o => wbs_fmc130m_4ch_out_array,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc130m_4ch_debug_valid_int,
fifo_debug_full_o => fmc130m_4ch_debug_full_int,
fifo_debug_empty_o => fmc130m_4ch_debug_empty_int
);
gen_wbs_dummy_signals : for i in 0 to c_num_adc_channels-1 generate
wbs_fmc130m_4ch_in_array(i) <= cc_dummy_src_com_in;
end generate;
fmc_mmcm_lock_led_o <= fmc_mmcm_lock_int;
fmc_pll_status_led_o <= fmc_pll_status_int;
fmc_led1_o <= fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
--led_south_o <= fmc_led1_int;
--led_east_o <= fmc_led2_int;
--led_north_o <= fmc_led3_int;
-- The board peripherals components is slave 8
cmp_xwb_dbe_periph : xwb_dbe_periph
generic map(
-- NOT used!
--g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
--g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period => c_tics_cntr_period,
g_num_leds => c_leds_num_pins,
g_num_buttons => c_buttons_num_pins
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- UART
uart_rxd_i => '0',
uart_txd_o => open,
-- LEDs
led_out_o => gpio_leds_int,
led_in_i => gpio_leds_int,
led_oen_o => open,
-- Buttons
button_out_o => open,
button_in_i => buttons_i,
button_oen_o => open,
-- Wishbone
slave_i => cbar_master_o(8),
slave_o => cbar_master_i(8)
);
leds_o <= gpio_leds_int;
---- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_4_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1,
CONTROL2 => CONTROL2,
CONTROL3 => CONTROL3
);
cmp_chipscope_ila_0_fmc130m_4ch_clk0 : chipscope_ila
port map (
CONTROL => CONTROL0,
--CLK => clk_sys,
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- fmc130m_4ch WBS master output data
--TRIG_ILA0_0 <= wbs_fmc130m_4ch_out_array(3).dat &
-- wbs_fmc130m_4ch_out_array(2).dat;
TRIG_ILA0_0 <= fmc_130m_4ch_data(31 downto 16) &
fmc_130m_4ch_data(47 downto 32);
-- fmc130m_4ch WBS master output data
--TRIG_ILA0_1 <= wbs_fmc130m_4ch_out_array(1).dat &
-- wbs_fmc130m_4ch_out_array(0).dat;
--TRIG_ILA0_1 <= fmc130m_4ch_adc_data(15 downto 0) &
-- fmc130m_4ch_adc_data(47 downto 32);
TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).clk_chain.idelay.pulse &
adc_dly_debug_int(1).data_chain.idelay.pulse &
adc_dly_debug_int(1).clk_chain.idelay.val &
adc_dly_debug_int(1).data_chain.idelay.val;
TRIG_ILA0_1(31 downto 12) <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA0_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc &
wbs_fmc130m_4ch_out_array(1).stb &
wbs_fmc130m_4ch_out_array(1).adr &
wbs_fmc130m_4ch_out_array(1).sel &
wbs_fmc130m_4ch_out_array(1).we &
wbs_fmc130m_4ch_out_array(2).cyc &
wbs_fmc130m_4ch_out_array(2).stb &
wbs_fmc130m_4ch_out_array(2).adr &
wbs_fmc130m_4ch_out_array(2).sel &
wbs_fmc130m_4ch_out_array(2).we;
TRIG_ILA0_2(18) <= '0';
TRIG_ILA0_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA0_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA0_2(24) <= fmc_pll_status_int;
TRIG_ILA0_2(25) <= fmc130m_4ch_debug_valid_int(1);
TRIG_ILA0_2(26) <= fmc130m_4ch_debug_full_int(1);
TRIG_ILA0_2(27) <= fmc130m_4ch_debug_empty_int(1);
TRIG_ILA0_2(31 downto 28) <= (others => '0');
-- fmc130m_4ch WBS master output control signals
--TRIG_ILA0_3(17 downto 0) <= wbs_fmc130m_4ch_out_array(1).cyc &
-- wbs_fmc130m_4ch_out_array(1).stb &
-- wbs_fmc130m_4ch_out_array(1).adr &
-- wbs_fmc130m_4ch_out_array(1).sel &
-- wbs_fmc130m_4ch_out_array(1).we &
-- wbs_fmc130m_4ch_out_array(0).cyc &
-- wbs_fmc130m_4ch_out_array(0).stb &
-- wbs_fmc130m_4ch_out_array(0).adr &
-- wbs_fmc130m_4ch_out_array(0).sel &
-- wbs_fmc130m_4ch_out_array(0).we;
--TRIG_ILA0_3(18) <= fmc_reset_adcs_n_out;
--TRIG_ILA0_3(22 downto 19) <= fmc130m_4ch_adc_valid;
--TRIG_ILA0_3(23) <= fmc130m_4ch_mmcm_lock_int;
--TRIG_ILA0_3(24) <= fmc130m_4ch_lmk_lock_int;
--TRIG_ILA0_3(25) <= fmc130m_4ch_debug_valid_int(1);
--TRIG_ILA0_3(26) <= fmc130m_4ch_debug_full_int(1);
--TRIG_ILA0_3(27) <= fmc130m_4ch_debug_empty_int(1);
--TRIG_ILA0_3(31 downto 28) <= (others => '0');
TRIG_ILA0_3 <= (others => '0');
-- Etherbone debuging signals
--cmp_chipscope_ila_1_etherbone : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--TRIG_ILA1_0 <= wb_ebone_out.dat;
--TRIG_ILA1_1 <= wb_ebone_in.dat;
--TRIG_ILA1_2 <= wb_ebone_out.adr;
--TRIG_ILA1_3(6 downto 0) <= wb_ebone_out.cyc &
-- wb_ebone_out.stb &
-- wb_ebone_out.sel &
-- wb_ebone_out.we;
--TRIG_ILA1_3(11 downto 7) <= wb_ebone_in.ack &
-- wb_ebone_in.err &
-- wb_ebone_in.rty &
-- wb_ebone_in.stall &
-- wb_ebone_in.int;
--TRIG_ILA1_3(31 downto 12) <= (others => '0');
--cmp_chipscope_ila_1_ethmac_rx : chipscope_ila
--port map (
-- CONTROL => CONTROL1,
-- CLK => mrx_clk_pad_i,
-- TRIG0 => TRIG_ILA1_0,
-- TRIG1 => TRIG_ILA1_1,
-- TRIG2 => TRIG_ILA1_2,
-- TRIG3 => TRIG_ILA1_3
--);
--
--TRIG_ILA1_0(7 downto 0) <= mrxd_pad_i &
-- mrxdv_pad_i &
-- mrxerr_pad_i &
-- mcoll_pad_i &
-- mcrs_pad_i;
--
--TRIG_ILA1_0(31 downto 8) <= (others => '0');
--TRIG_ILA1_1 <= (others => '0');
--TRIG_ILA1_2 <= (others => '0');
--TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_1_fmc130m_4ch_clk1 : chipscope_ila
port map (
CONTROL => CONTROL1,
--CLK => fmc_130m_4ch_clk(1),
CLK => fmc_130m_4ch_clk(c_adc_ref_clk),
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_0 <= fmc_130m_4ch_data(15 downto 0) &
fmc_130m_4ch_data(63 downto 48);
-- fmc130m_4ch WBS master output data
TRIG_ILA1_1 <= (others => '0');
-- fmc130m_4ch WBS master output control signals
TRIG_ILA1_2(17 downto 0) <= wbs_fmc130m_4ch_out_array(0).cyc &
wbs_fmc130m_4ch_out_array(0).stb &
wbs_fmc130m_4ch_out_array(0).adr &
wbs_fmc130m_4ch_out_array(0).sel &
wbs_fmc130m_4ch_out_array(0).we &
wbs_fmc130m_4ch_out_array(3).cyc &
wbs_fmc130m_4ch_out_array(3).stb &
wbs_fmc130m_4ch_out_array(3).adr &
wbs_fmc130m_4ch_out_array(3).sel &
wbs_fmc130m_4ch_out_array(3).we;
TRIG_ILA1_2(18) <= '0';
TRIG_ILA1_2(22 downto 19) <= fmc_130m_4ch_data_valid;
TRIG_ILA1_2(23) <= fmc_mmcm_lock_int;
TRIG_ILA1_2(24) <= fmc_pll_status_int;
TRIG_ILA1_2(25) <= fmc130m_4ch_debug_valid_int(0);
TRIG_ILA1_2(26) <= fmc130m_4ch_debug_full_int(0);
TRIG_ILA1_2(27) <= fmc130m_4ch_debug_empty_int(0);
TRIG_ILA1_2(31 downto 28) <= (others => '0');
TRIG_ILA1_3 <= (others => '0');
cmp_chipscope_ila_2_ethmac_tx : chipscope_ila
port map (
CONTROL => CONTROL2,
CLK => mtx_clk_pad_i,
TRIG0 => TRIG_ILA2_0,
TRIG1 => TRIG_ILA2_1,
TRIG2 => TRIG_ILA2_2,
TRIG3 => TRIG_ILA2_3
);
TRIG_ILA2_0(5 downto 0) <= mtxd_pad_int &
mtxen_pad_int &
mtxerr_pad_int;
TRIG_ILA2_0(31 downto 6) <= (others => '0');
TRIG_ILA2_1 <= (others => '0');
TRIG_ILA2_2 <= (others => '0');
TRIG_ILA2_3 <= (others => '0');
--cmp_chipscope_ila_3_ethmac_miim : chipscope_ila
--port map (
-- CONTROL => CONTROL3,
-- CLK => clk_sys,
-- TRIG0 => TRIG_ILA3_0,
-- TRIG1 => TRIG_ILA3_1,
-- TRIG2 => TRIG_ILA3_2,
-- TRIG3 => TRIG_ILA3_3
--);
--
--TRIG_ILA3_0(4 downto 0) <= mdc_pad_int &
-- ethmac_md_in &
-- ethmac_md_out &
-- ethmac_md_oe &
-- ethmac_int;
--
--TRIG_ILA3_0(31 downto 6) <= (others => '0');
--TRIG_ILA3_1 <= (others => '0');
--TRIG_ILA3_2 <= (others => '0');
--TRIG_ILA3_3 <= (others => '0');
-- The clocks to/from peripherals are derived from the bus clock.
-- Therefore we don't have to worry about synchronization here, just
-- keep in mind that the data/ss lines will appear longer than normal
cmp_chipscope_ila_3_fmc130m_4ch_periph : chipscope_ila
port map (
CONTROL => CONTROL3,
CLK => clk_sys,
TRIG0 => TRIG_ILA3_0,
TRIG1 => TRIG_ILA3_1,
TRIG2 => TRIG_ILA3_2,
TRIG3 => TRIG_ILA3_3
);
TRIG_ILA3_0(7 downto 0) <= (others => '0');
TRIG_ILA3_0(31 downto 8) <= (others => '0');
TRIG_ILA3_1(4 downto 0) <= (others => '0');
TRIG_ILA3_1(31 downto 5) <= (others => '0');
TRIG_ILA3_2 <= (others => '0');
TRIG_ILA3_3 <= (others => '0');
end rtl;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0;
USE cic_compiler_v4_0.cic_compiler_v4_0;
ENTITY cascaded_integrator_comb IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END cascaded_integrator_comb;
ARCHITECTURE cascaded_integrator_comb_arch OF cascaded_integrator_comb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cascaded_integrator_comb_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0
GENERIC MAP (
C_COMPONENT_NAME => "cascaded_integrator_comb",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 5,
C_DIFF_DELAY => 1,
C_RATE => 16,
C_INPUT_WIDTH => 2,
C_OUTPUT_WIDTH => 22,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 16,
C_MAX_RATE => 16,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_C1 => 22,
C_C2 => 22,
C_C3 => 22,
C_C4 => 22,
C_C5 => 22,
C_C6 => 0,
C_I1 => 22,
C_I2 => 22,
C_I3 => 22,
C_I4 => 22,
C_I5 => 22,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 8,
C_M_AXIS_DATA_TDATA_WIDTH => 24,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END cascaded_integrator_comb_arch;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
-- Company : None
--
--------------------------------------------------------------------------------
--
-- File : MDCT.VHD
-- Created : Sat Feb 25 16:12 2006
--
--------------------------------------------------------------------------------
--
-- Description : Discrete Cosine Transform - chip top level (w/ memories)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library WORK;
use WORK.MDCT_PKG.all;
entity MDCT is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(COE_W-1 downto 0);
-- debug
odv1 : out STD_LOGIC;
dcto1 : out std_logic_vector(OP_W-1 downto 0)
);
end MDCT;
architecture RTL of MDCT is
------------------------------
-- 1D DCT
------------------------------
component DCT1D
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end component;
------------------------------
-- 1D DCT (2nd stage)
------------------------------
component DCT2D
port(
clk : in STD_LOGIC;
rst : in std_logic;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao9 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao10 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
dataready : in STD_LOGIC;
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro9 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro10 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
rmemsel : out STD_LOGIC;
datareadyack : out STD_LOGIC
);
end component;
------------------------------
-- RAM
------------------------------
component RAM
port (
d : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
waddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
raddr : in STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
we : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
);
end component;
------------------------------
-- ROME
------------------------------
component ROME
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end component;
------------------------------
-- ROMO
------------------------------
component ROMO
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end component;
------------------------------
-- DBUFCTL
------------------------------
component DBUFCTL
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
wmemsel : in STD_LOGIC;
rmemsel : in STD_LOGIC;
datareadyack : in STD_LOGIC;
memswitchwr : out STD_LOGIC;
memswitchrd : out STD_LOGIC;
dataready : out STD_LOGIC
);
end component;
signal romedatao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romedatao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romodatao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal ramdatao_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal romeaddro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romeaddro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romoaddro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal ramraddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal rome2datao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao9_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2datao10_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao0_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao1_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao2_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao3_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao4_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao5_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao6_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao7_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao8_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao9_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal romo2datao10_s : STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
signal rome2addro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro9_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal rome2addro10_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro0_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro1_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro2_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro3_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro4_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro5_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro6_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro7_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro8_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro9_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal romo2addro10_s : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
signal odv2_s : STD_LOGIC;
signal dcto2_s : STD_LOGIC_VECTOR(OP_W-1 downto 0);
signal trigger2_s : STD_LOGIC;
signal trigger1_s : STD_LOGIC;
signal ramdatao1_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramdatao2_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe1_s : STD_LOGIC;
signal ramwe2_s : STD_LOGIC;
signal memswitchrd_s : STD_LOGIC;
signal memswitchwr_s : STD_LOGIC;
signal wmemsel_s : STD_LOGIC;
signal rmemsel_s : STD_LOGIC;
signal dataready_s : STD_LOGIC;
signal datareadyack_s : STD_LOGIC;
begin
------------------------------
-- 1D DCT port map
------------------------------
U_DCT1D : DCT1D
port map(
clk => clk,
rst => rst,
dcti => dcti,
idv => idv,
romedatao0 => romedatao0_s,
romedatao1 => romedatao1_s,
romedatao2 => romedatao2_s,
romedatao3 => romedatao3_s,
romedatao4 => romedatao4_s,
romedatao5 => romedatao5_s,
romedatao6 => romedatao6_s,
romedatao7 => romedatao7_s,
romedatao8 => romedatao8_s,
romodatao0 => romodatao0_s,
romodatao1 => romodatao1_s,
romodatao2 => romodatao2_s,
romodatao3 => romodatao3_s,
romodatao4 => romodatao4_s,
romodatao5 => romodatao5_s,
romodatao6 => romodatao6_s,
romodatao7 => romodatao7_s,
romodatao8 => romodatao8_s,
odv => odv1,
dcto => dcto1,
romeaddro0 => romeaddro0_s,
romeaddro1 => romeaddro1_s,
romeaddro2 => romeaddro2_s,
romeaddro3 => romeaddro3_s,
romeaddro4 => romeaddro4_s,
romeaddro5 => romeaddro5_s,
romeaddro6 => romeaddro6_s,
romeaddro7 => romeaddro7_s,
romeaddro8 => romeaddro8_s,
romoaddro0 => romoaddro0_s,
romoaddro1 => romoaddro1_s,
romoaddro2 => romoaddro2_s,
romoaddro3 => romoaddro3_s,
romoaddro4 => romoaddro4_s,
romoaddro5 => romoaddro5_s,
romoaddro6 => romoaddro6_s,
romoaddro7 => romoaddro7_s,
romoaddro8 => romoaddro8_s,
ramwaddro => ramwaddro_s,
ramdatai => ramdatai_s,
ramwe => ramwe_s,
wmemsel => wmemsel_s
);
------------------------------
-- 1D DCT port map
------------------------------
U_DCT2D : DCT2D
port map(
clk => clk,
rst => rst,
romedatao0 => rome2datao0_s,
romedatao1 => rome2datao1_s,
romedatao2 => rome2datao2_s,
romedatao3 => rome2datao3_s,
romedatao4 => rome2datao4_s,
romedatao5 => rome2datao5_s,
romedatao6 => rome2datao6_s,
romedatao7 => rome2datao7_s,
romedatao8 => rome2datao8_s,
romedatao9 => rome2datao9_s,
romedatao10 => rome2datao10_s,
romodatao0 => romo2datao0_s,
romodatao1 => romo2datao1_s,
romodatao2 => romo2datao2_s,
romodatao3 => romo2datao3_s,
romodatao4 => romo2datao4_s,
romodatao5 => romo2datao5_s,
romodatao6 => romo2datao6_s,
romodatao7 => romo2datao7_s,
romodatao8 => romo2datao8_s,
romodatao9 => romo2datao9_s,
romodatao10 => romo2datao10_s,
ramdatao => ramdatao_s,
dataready => dataready_s,
odv => odv,
dcto => dcto,
romeaddro0 => rome2addro0_s,
romeaddro1 => rome2addro1_s,
romeaddro2 => rome2addro2_s,
romeaddro3 => rome2addro3_s,
romeaddro4 => rome2addro4_s,
romeaddro5 => rome2addro5_s,
romeaddro6 => rome2addro6_s,
romeaddro7 => rome2addro7_s,
romeaddro8 => rome2addro8_s,
romeaddro9 => rome2addro9_s,
romeaddro10 => rome2addro10_s,
romoaddro0 => romo2addro0_s,
romoaddro1 => romo2addro1_s,
romoaddro2 => romo2addro2_s,
romoaddro3 => romo2addro3_s,
romoaddro4 => romo2addro4_s,
romoaddro5 => romo2addro5_s,
romoaddro6 => romo2addro6_s,
romoaddro7 => romo2addro7_s,
romoaddro8 => romo2addro8_s,
romoaddro9 => romo2addro9_s,
romoaddro10 => romo2addro10_s,
ramraddro => ramraddro_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s
);
------------------------------
-- RAM1 port map
------------------------------
U1_RAM : RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe1_s,
clk => clk,
q => ramdatao1_s
);
------------------------------
-- RAM2 port map
------------------------------
U2_RAM : RAM
port map (
d => ramdatai_s,
waddr => ramwaddro_s,
raddr => ramraddro_s,
we => ramwe2_s,
clk => clk,
q => ramdatao2_s
);
-- double buffer switch
ramwe1_s <= ramwe_s when memswitchwr_s = '0' else '0';
ramwe2_s <= ramwe_s when memswitchwr_s = '1' else '0';
ramdatao_s <= ramdatao1_s when memswitchrd_s = '0' else ramdatao2_s;
------------------------------
-- DBUFCTL
------------------------------
U_DBUFCTL : DBUFCTL
port map(
clk => clk,
rst => rst,
wmemsel => wmemsel_s,
rmemsel => rmemsel_s,
datareadyack => datareadyack_s,
memswitchwr => memswitchwr_s,
memswitchrd => memswitchrd_s,
dataready => dataready_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME0 : ROME
port map(
addr => romeaddro0_s,
clk => clk,
datao => romedatao0_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME1 : ROME
port map(
addr => romeaddro1_s,
clk => clk,
datao => romedatao1_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME2 : ROME
port map(
addr => romeaddro2_s,
clk => clk,
datao => romedatao2_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME3 : ROME
port map(
addr => romeaddro3_s,
clk => clk,
datao => romedatao3_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME4 : ROME
port map(
addr => romeaddro4_s,
clk => clk,
datao => romedatao4_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME5 : ROME
port map(
addr => romeaddro5_s,
clk => clk,
datao => romedatao5_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME6 : ROME
port map(
addr => romeaddro6_s,
clk => clk,
datao => romedatao6_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME7 : ROME
port map(
addr => romeaddro7_s,
clk => clk,
datao => romedatao7_s
);
------------------------------
-- ROME port map
------------------------------
U1_ROME8 : ROME
port map(
addr => romeaddro8_s,
clk => clk,
datao => romedatao8_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO0 : ROMO
port map(
addr => romoaddro0_s,
clk => clk,
datao => romodatao0_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO1 : ROMO
port map(
addr => romoaddro1_s,
clk => clk,
datao => romodatao1_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO2 : ROMO
port map(
addr => romoaddro2_s,
clk => clk,
datao => romodatao2_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO3 : ROMO
port map(
addr => romoaddro3_s,
clk => clk,
datao => romodatao3_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO4 : ROMO
port map(
addr => romoaddro4_s,
clk => clk,
datao => romodatao4_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO5 : ROMO
port map(
addr => romoaddro5_s,
clk => clk,
datao => romodatao5_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO6 : ROMO
port map(
addr => romoaddro6_s,
clk => clk,
datao => romodatao6_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO7 : ROMO
port map(
addr => romoaddro7_s,
clk => clk,
datao => romodatao7_s
);
------------------------------
-- ROMO port map
------------------------------
U1_ROMO8 : ROMO
port map(
addr => romoaddro8_s,
clk => clk,
datao => romodatao8_s
);
------------------------------
-- 2 stage ROMs
------------------------------
------------------------------
-- ROME port map
------------------------------
U2_ROME0 : ROME
port map(
addr => rome2addro0_s,
clk => clk,
datao => rome2datao0_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME1 : ROME
port map(
addr => rome2addro1_s,
clk => clk,
datao => rome2datao1_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME2 : ROME
port map(
addr => rome2addro2_s,
clk => clk,
datao => rome2datao2_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME3 : ROME
port map(
addr => rome2addro3_s,
clk => clk,
datao => rome2datao3_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME4 : ROME
port map(
addr => rome2addro4_s,
clk => clk,
datao => rome2datao4_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME5 : ROME
port map(
addr => rome2addro5_s,
clk => clk,
datao => rome2datao5_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME6 : ROME
port map(
addr => rome2addro6_s,
clk => clk,
datao => rome2datao6_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME7 : ROME
port map(
addr => rome2addro7_s,
clk => clk,
datao => rome2datao7_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME8 : ROME
port map(
addr => rome2addro8_s,
clk => clk,
datao => rome2datao8_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME9 : ROME
port map(
addr => rome2addro9_s,
clk => clk,
datao => rome2datao9_s
);
------------------------------
-- ROME port map
------------------------------
U2_ROME10 : ROME
port map(
addr => rome2addro10_s,
clk => clk,
datao => rome2datao10_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO0 : ROMO
port map(
addr => romo2addro0_s,
clk => clk,
datao => romo2datao0_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO1 : ROMO
port map(
addr => romo2addro1_s,
clk => clk,
datao => romo2datao1_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO2 : ROMO
port map(
addr => romo2addro2_s,
clk => clk,
datao => romo2datao2_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO3 : ROMO
port map(
addr => romo2addro3_s,
clk => clk,
datao => romo2datao3_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO4 : ROMO
port map(
addr => romo2addro4_s,
clk => clk,
datao => romo2datao4_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO5 : ROMO
port map(
addr => romo2addro5_s,
clk => clk,
datao => romo2datao5_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO6 : ROMO
port map(
addr => romo2addro6_s,
clk => clk,
datao => romo2datao6_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO7 : ROMO
port map(
addr => romo2addro7_s,
clk => clk,
datao => romo2datao7_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO8 : ROMO
port map(
addr => romo2addro8_s,
clk => clk,
datao => romo2datao8_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO9 : ROMO
port map(
addr => romo2addro9_s,
clk => clk,
datao => romo2datao9_s
);
------------------------------
-- ROMO port map
------------------------------
U2_ROMO10 : ROMO
port map(
addr => romo2addro10_s,
clk => clk,
datao => romo2datao10_s
);
end RTL;
|
--
-- indexing testcase "A" derived from gna bug16782
--
-- ghdl-0.31-mcode on win32 : indexing off the end of an unconstrained port results in an unhandled exception
--
entity comp2 is
port(a :in bit_vector);
end entity;
architecture arch of comp2 is
constant DATAPATH : natural := a'length;
signal tmp : bit;
begin
tmp <= a(DATAPATH+3);
end architecture;
entity index_range_test_A is end entity;
architecture arch of index_range_test_A is
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: entity work.comp2 port map(a);
end architecture; |
--
-- indexing testcase "A" derived from gna bug16782
--
-- ghdl-0.31-mcode on win32 : indexing off the end of an unconstrained port results in an unhandled exception
--
entity comp2 is
port(a :in bit_vector);
end entity;
architecture arch of comp2 is
constant DATAPATH : natural := a'length;
signal tmp : bit;
begin
tmp <= a(DATAPATH+3);
end architecture;
entity index_range_test_A is end entity;
architecture arch of index_range_test_A is
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: entity work.comp2 port map(a);
end architecture; |
--
-- indexing testcase "A" derived from gna bug16782
--
-- ghdl-0.31-mcode on win32 : indexing off the end of an unconstrained port results in an unhandled exception
--
entity comp2 is
port(a :in bit_vector);
end entity;
architecture arch of comp2 is
constant DATAPATH : natural := a'length;
signal tmp : bit;
begin
tmp <= a(DATAPATH+3);
end architecture;
entity index_range_test_A is end entity;
architecture arch of index_range_test_A is
constant DATAPATH :natural := 16;
signal a :bit_vector(DATAPATH-1 downto 0);
begin
i_comp: entity work.comp2 port map(a);
end architecture; |
-------------------------------------------------------------------------------
-- Title : I2C Bus Arbiter Hotone Decoder
-- Project : White Rabbit Project
-------------------------------------------------------------------------------
-- File : i2c_arbiter_hotone_dec.vhd
-- Author : Miguel Jimenez Lopez
-- Company : UGR
-- Created : 2015-08-06
-- Last update: 2015-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- This component allows to share a single I2C bus for many masters in a simple
-- way.
--
-------------------------------------------------------------------------------
-- TODO:
-------------------------------------------------------------------------------
--
-- Copyright (c) 2015 UGR
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity i2c_arbiter_hotone_dec is
generic (
g_num_inputs : natural range 2 to 32 := 2
);
port (
-- Clock & Reset
clk_i : in std_logic;
rst_n_i : in std_logic;
enable_i : in std_logic;
start_state_i : in std_logic_vector(g_num_inputs-1 downto 0);
input_enabled_o : out std_logic;
input_idx_enabled_o : out integer range 0 to g_num_inputs-1
);
end i2c_arbiter_hotone_dec;
architecture struct of i2c_arbiter_hotone_dec is
begin
main: process(clk_i)
variable idx : integer := -1;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
input_enabled_o <= '0';
input_idx_enabled_o <= 0;
else
if enable_i = '1' then
idx := -1;
for I in g_num_inputs-1 downto 0 loop
if start_state_i(I) = '1' then
idx := I;
end if;
end loop;
if idx = -1 then
input_enabled_o <= '0';
input_idx_enabled_o <= 0;
else
input_enabled_o <= '1';
input_idx_enabled_o <= idx;
end if;
end if;
end if;
end if;
end process main;
end struct;
|
------------------------------------------------------------------------------
-- Title : Simple Wishbone UART
-- Project : General Cores Collection (gencores) library
------------------------------------------------------------------------------
-- File : xwb_simple_uart.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2011-11-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple UART controller, providing two modes of operation
-- (both can be used simultenously):
-- - physical UART (encoding fixed to 8 data bits, no parity and one stop bit)
-- - virtual UART: TXed data is passed via a FIFO to the Wishbone host (and
-- vice versa).
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-- 2011-10-04 1.1 twlostow xwb module
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
entity xwb_simple_uart is
generic(
g_with_virtual_uart : boolean := true;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i: in std_logic;
uart_txd_o: out std_logic
);
end xwb_simple_uart;
architecture rtl of xwb_simple_uart is
component wb_simple_uart
generic (
g_with_virtual_uart : boolean;
g_with_physical_uart : boolean;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_vuart_fifo_size : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic);
end component;
begin -- rtl
U_Wrapped_UART: wb_simple_uart
generic map (
g_with_virtual_uart => g_with_virtual_uart,
g_with_physical_uart => g_with_physical_uart,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_vuart_fifo_size => g_vuart_fifo_size)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_adr_i => slave_i.adr(4 downto 0),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o);
slave_o.err <= '0';
slave_o.rty <= '0';
slave_o.int <='0';
end rtl;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:38 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_sim_netlist.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
signal \ARG__0_i_1_n_0\ : STD_LOGIC;
signal \ARG__0_n_100\ : STD_LOGIC;
signal \ARG__0_n_101\ : STD_LOGIC;
signal \ARG__0_n_102\ : STD_LOGIC;
signal \ARG__0_n_103\ : STD_LOGIC;
signal \ARG__0_n_104\ : STD_LOGIC;
signal \ARG__0_n_105\ : STD_LOGIC;
signal \ARG__0_n_92\ : STD_LOGIC;
signal \ARG__0_n_93\ : STD_LOGIC;
signal \ARG__0_n_94\ : STD_LOGIC;
signal \ARG__0_n_95\ : STD_LOGIC;
signal \ARG__0_n_96\ : STD_LOGIC;
signal \ARG__0_n_97\ : STD_LOGIC;
signal \ARG__0_n_98\ : STD_LOGIC;
signal \ARG__0_n_99\ : STD_LOGIC;
signal \ARG__10_i_1_n_0\ : STD_LOGIC;
signal \ARG__10_n_100\ : STD_LOGIC;
signal \ARG__10_n_101\ : STD_LOGIC;
signal \ARG__10_n_102\ : STD_LOGIC;
signal \ARG__10_n_103\ : STD_LOGIC;
signal \ARG__10_n_104\ : STD_LOGIC;
signal \ARG__10_n_105\ : STD_LOGIC;
signal \ARG__10_n_92\ : STD_LOGIC;
signal \ARG__10_n_93\ : STD_LOGIC;
signal \ARG__10_n_94\ : STD_LOGIC;
signal \ARG__10_n_95\ : STD_LOGIC;
signal \ARG__10_n_96\ : STD_LOGIC;
signal \ARG__10_n_97\ : STD_LOGIC;
signal \ARG__10_n_98\ : STD_LOGIC;
signal \ARG__10_n_99\ : STD_LOGIC;
signal \ARG__11_i_1_n_0\ : STD_LOGIC;
signal \ARG__11_n_100\ : STD_LOGIC;
signal \ARG__11_n_101\ : STD_LOGIC;
signal \ARG__11_n_102\ : STD_LOGIC;
signal \ARG__11_n_103\ : STD_LOGIC;
signal \ARG__11_n_104\ : STD_LOGIC;
signal \ARG__11_n_105\ : STD_LOGIC;
signal \ARG__11_n_76\ : STD_LOGIC;
signal \ARG__11_n_77\ : STD_LOGIC;
signal \ARG__11_n_78\ : STD_LOGIC;
signal \ARG__11_n_79\ : STD_LOGIC;
signal \ARG__11_n_80\ : STD_LOGIC;
signal \ARG__11_n_81\ : STD_LOGIC;
signal \ARG__11_n_82\ : STD_LOGIC;
signal \ARG__11_n_83\ : STD_LOGIC;
signal \ARG__11_n_84\ : STD_LOGIC;
signal \ARG__11_n_85\ : STD_LOGIC;
signal \ARG__11_n_86\ : STD_LOGIC;
signal \ARG__11_n_87\ : STD_LOGIC;
signal \ARG__11_n_88\ : STD_LOGIC;
signal \ARG__11_n_89\ : STD_LOGIC;
signal \ARG__11_n_90\ : STD_LOGIC;
signal \ARG__11_n_91\ : STD_LOGIC;
signal \ARG__11_n_92\ : STD_LOGIC;
signal \ARG__11_n_93\ : STD_LOGIC;
signal \ARG__11_n_94\ : STD_LOGIC;
signal \ARG__11_n_95\ : STD_LOGIC;
signal \ARG__11_n_96\ : STD_LOGIC;
signal \ARG__11_n_97\ : STD_LOGIC;
signal \ARG__11_n_98\ : STD_LOGIC;
signal \ARG__11_n_99\ : STD_LOGIC;
signal \ARG__12_i_1_n_0\ : STD_LOGIC;
signal \ARG__12_n_100\ : STD_LOGIC;
signal \ARG__12_n_101\ : STD_LOGIC;
signal \ARG__12_n_102\ : STD_LOGIC;
signal \ARG__12_n_103\ : STD_LOGIC;
signal \ARG__12_n_104\ : STD_LOGIC;
signal \ARG__12_n_105\ : STD_LOGIC;
signal \ARG__12_n_92\ : STD_LOGIC;
signal \ARG__12_n_93\ : STD_LOGIC;
signal \ARG__12_n_94\ : STD_LOGIC;
signal \ARG__12_n_95\ : STD_LOGIC;
signal \ARG__12_n_96\ : STD_LOGIC;
signal \ARG__12_n_97\ : STD_LOGIC;
signal \ARG__12_n_98\ : STD_LOGIC;
signal \ARG__12_n_99\ : STD_LOGIC;
signal \ARG__13_i_1_n_0\ : STD_LOGIC;
signal \ARG__13_n_100\ : STD_LOGIC;
signal \ARG__13_n_101\ : STD_LOGIC;
signal \ARG__13_n_102\ : STD_LOGIC;
signal \ARG__13_n_103\ : STD_LOGIC;
signal \ARG__13_n_104\ : STD_LOGIC;
signal \ARG__13_n_105\ : STD_LOGIC;
signal \ARG__13_n_76\ : STD_LOGIC;
signal \ARG__13_n_77\ : STD_LOGIC;
signal \ARG__13_n_78\ : STD_LOGIC;
signal \ARG__13_n_79\ : STD_LOGIC;
signal \ARG__13_n_80\ : STD_LOGIC;
signal \ARG__13_n_81\ : STD_LOGIC;
signal \ARG__13_n_82\ : STD_LOGIC;
signal \ARG__13_n_83\ : STD_LOGIC;
signal \ARG__13_n_84\ : STD_LOGIC;
signal \ARG__13_n_85\ : STD_LOGIC;
signal \ARG__13_n_86\ : STD_LOGIC;
signal \ARG__13_n_87\ : STD_LOGIC;
signal \ARG__13_n_88\ : STD_LOGIC;
signal \ARG__13_n_89\ : STD_LOGIC;
signal \ARG__13_n_90\ : STD_LOGIC;
signal \ARG__13_n_91\ : STD_LOGIC;
signal \ARG__13_n_92\ : STD_LOGIC;
signal \ARG__13_n_93\ : STD_LOGIC;
signal \ARG__13_n_94\ : STD_LOGIC;
signal \ARG__13_n_95\ : STD_LOGIC;
signal \ARG__13_n_96\ : STD_LOGIC;
signal \ARG__13_n_97\ : STD_LOGIC;
signal \ARG__13_n_98\ : STD_LOGIC;
signal \ARG__13_n_99\ : STD_LOGIC;
signal \ARG__14_i_1_n_0\ : STD_LOGIC;
signal \ARG__14_n_100\ : STD_LOGIC;
signal \ARG__14_n_101\ : STD_LOGIC;
signal \ARG__14_n_102\ : STD_LOGIC;
signal \ARG__14_n_103\ : STD_LOGIC;
signal \ARG__14_n_104\ : STD_LOGIC;
signal \ARG__14_n_105\ : STD_LOGIC;
signal \ARG__14_n_92\ : STD_LOGIC;
signal \ARG__14_n_93\ : STD_LOGIC;
signal \ARG__14_n_94\ : STD_LOGIC;
signal \ARG__14_n_95\ : STD_LOGIC;
signal \ARG__14_n_96\ : STD_LOGIC;
signal \ARG__14_n_97\ : STD_LOGIC;
signal \ARG__14_n_98\ : STD_LOGIC;
signal \ARG__14_n_99\ : STD_LOGIC;
signal \ARG__15_i_1_n_0\ : STD_LOGIC;
signal \ARG__15_n_100\ : STD_LOGIC;
signal \ARG__15_n_101\ : STD_LOGIC;
signal \ARG__15_n_102\ : STD_LOGIC;
signal \ARG__15_n_103\ : STD_LOGIC;
signal \ARG__15_n_104\ : STD_LOGIC;
signal \ARG__15_n_105\ : STD_LOGIC;
signal \ARG__15_n_76\ : STD_LOGIC;
signal \ARG__15_n_77\ : STD_LOGIC;
signal \ARG__15_n_78\ : STD_LOGIC;
signal \ARG__15_n_79\ : STD_LOGIC;
signal \ARG__15_n_80\ : STD_LOGIC;
signal \ARG__15_n_81\ : STD_LOGIC;
signal \ARG__15_n_82\ : STD_LOGIC;
signal \ARG__15_n_83\ : STD_LOGIC;
signal \ARG__15_n_84\ : STD_LOGIC;
signal \ARG__15_n_85\ : STD_LOGIC;
signal \ARG__15_n_86\ : STD_LOGIC;
signal \ARG__15_n_87\ : STD_LOGIC;
signal \ARG__15_n_88\ : STD_LOGIC;
signal \ARG__15_n_89\ : STD_LOGIC;
signal \ARG__15_n_90\ : STD_LOGIC;
signal \ARG__15_n_91\ : STD_LOGIC;
signal \ARG__15_n_92\ : STD_LOGIC;
signal \ARG__15_n_93\ : STD_LOGIC;
signal \ARG__15_n_94\ : STD_LOGIC;
signal \ARG__15_n_95\ : STD_LOGIC;
signal \ARG__15_n_96\ : STD_LOGIC;
signal \ARG__15_n_97\ : STD_LOGIC;
signal \ARG__15_n_98\ : STD_LOGIC;
signal \ARG__15_n_99\ : STD_LOGIC;
signal \ARG__16_i_1_n_0\ : STD_LOGIC;
signal \ARG__16_n_100\ : STD_LOGIC;
signal \ARG__16_n_101\ : STD_LOGIC;
signal \ARG__16_n_102\ : STD_LOGIC;
signal \ARG__16_n_103\ : STD_LOGIC;
signal \ARG__16_n_104\ : STD_LOGIC;
signal \ARG__16_n_105\ : STD_LOGIC;
signal \ARG__16_n_92\ : STD_LOGIC;
signal \ARG__16_n_93\ : STD_LOGIC;
signal \ARG__16_n_94\ : STD_LOGIC;
signal \ARG__16_n_95\ : STD_LOGIC;
signal \ARG__16_n_96\ : STD_LOGIC;
signal \ARG__16_n_97\ : STD_LOGIC;
signal \ARG__16_n_98\ : STD_LOGIC;
signal \ARG__16_n_99\ : STD_LOGIC;
signal \ARG__17_i_1_n_0\ : STD_LOGIC;
signal \ARG__17_n_100\ : STD_LOGIC;
signal \ARG__17_n_101\ : STD_LOGIC;
signal \ARG__17_n_102\ : STD_LOGIC;
signal \ARG__17_n_103\ : STD_LOGIC;
signal \ARG__17_n_104\ : STD_LOGIC;
signal \ARG__17_n_105\ : STD_LOGIC;
signal \ARG__17_n_76\ : STD_LOGIC;
signal \ARG__17_n_77\ : STD_LOGIC;
signal \ARG__17_n_78\ : STD_LOGIC;
signal \ARG__17_n_79\ : STD_LOGIC;
signal \ARG__17_n_80\ : STD_LOGIC;
signal \ARG__17_n_81\ : STD_LOGIC;
signal \ARG__17_n_82\ : STD_LOGIC;
signal \ARG__17_n_83\ : STD_LOGIC;
signal \ARG__17_n_84\ : STD_LOGIC;
signal \ARG__17_n_85\ : STD_LOGIC;
signal \ARG__17_n_86\ : STD_LOGIC;
signal \ARG__17_n_87\ : STD_LOGIC;
signal \ARG__17_n_88\ : STD_LOGIC;
signal \ARG__17_n_89\ : STD_LOGIC;
signal \ARG__17_n_90\ : STD_LOGIC;
signal \ARG__17_n_91\ : STD_LOGIC;
signal \ARG__17_n_92\ : STD_LOGIC;
signal \ARG__17_n_93\ : STD_LOGIC;
signal \ARG__17_n_94\ : STD_LOGIC;
signal \ARG__17_n_95\ : STD_LOGIC;
signal \ARG__17_n_96\ : STD_LOGIC;
signal \ARG__17_n_97\ : STD_LOGIC;
signal \ARG__17_n_98\ : STD_LOGIC;
signal \ARG__17_n_99\ : STD_LOGIC;
signal \ARG__18_i_1_n_0\ : STD_LOGIC;
signal \ARG__18_n_100\ : STD_LOGIC;
signal \ARG__18_n_101\ : STD_LOGIC;
signal \ARG__18_n_102\ : STD_LOGIC;
signal \ARG__18_n_103\ : STD_LOGIC;
signal \ARG__18_n_104\ : STD_LOGIC;
signal \ARG__18_n_105\ : STD_LOGIC;
signal \ARG__18_n_92\ : STD_LOGIC;
signal \ARG__18_n_93\ : STD_LOGIC;
signal \ARG__18_n_94\ : STD_LOGIC;
signal \ARG__18_n_95\ : STD_LOGIC;
signal \ARG__18_n_96\ : STD_LOGIC;
signal \ARG__18_n_97\ : STD_LOGIC;
signal \ARG__18_n_98\ : STD_LOGIC;
signal \ARG__18_n_99\ : STD_LOGIC;
signal \ARG__19_i_1_n_0\ : STD_LOGIC;
signal \ARG__19_n_100\ : STD_LOGIC;
signal \ARG__19_n_101\ : STD_LOGIC;
signal \ARG__19_n_102\ : STD_LOGIC;
signal \ARG__19_n_103\ : STD_LOGIC;
signal \ARG__19_n_104\ : STD_LOGIC;
signal \ARG__19_n_105\ : STD_LOGIC;
signal \ARG__19_n_76\ : STD_LOGIC;
signal \ARG__19_n_77\ : STD_LOGIC;
signal \ARG__19_n_78\ : STD_LOGIC;
signal \ARG__19_n_79\ : STD_LOGIC;
signal \ARG__19_n_80\ : STD_LOGIC;
signal \ARG__19_n_81\ : STD_LOGIC;
signal \ARG__19_n_82\ : STD_LOGIC;
signal \ARG__19_n_83\ : STD_LOGIC;
signal \ARG__19_n_84\ : STD_LOGIC;
signal \ARG__19_n_85\ : STD_LOGIC;
signal \ARG__19_n_86\ : STD_LOGIC;
signal \ARG__19_n_87\ : STD_LOGIC;
signal \ARG__19_n_88\ : STD_LOGIC;
signal \ARG__19_n_89\ : STD_LOGIC;
signal \ARG__19_n_90\ : STD_LOGIC;
signal \ARG__19_n_91\ : STD_LOGIC;
signal \ARG__19_n_92\ : STD_LOGIC;
signal \ARG__19_n_93\ : STD_LOGIC;
signal \ARG__19_n_94\ : STD_LOGIC;
signal \ARG__19_n_95\ : STD_LOGIC;
signal \ARG__19_n_96\ : STD_LOGIC;
signal \ARG__19_n_97\ : STD_LOGIC;
signal \ARG__19_n_98\ : STD_LOGIC;
signal \ARG__19_n_99\ : STD_LOGIC;
signal \ARG__1_i_1_n_0\ : STD_LOGIC;
signal \ARG__1_n_100\ : STD_LOGIC;
signal \ARG__1_n_101\ : STD_LOGIC;
signal \ARG__1_n_102\ : STD_LOGIC;
signal \ARG__1_n_103\ : STD_LOGIC;
signal \ARG__1_n_104\ : STD_LOGIC;
signal \ARG__1_n_105\ : STD_LOGIC;
signal \ARG__1_n_76\ : STD_LOGIC;
signal \ARG__1_n_77\ : STD_LOGIC;
signal \ARG__1_n_78\ : STD_LOGIC;
signal \ARG__1_n_79\ : STD_LOGIC;
signal \ARG__1_n_80\ : STD_LOGIC;
signal \ARG__1_n_81\ : STD_LOGIC;
signal \ARG__1_n_82\ : STD_LOGIC;
signal \ARG__1_n_83\ : STD_LOGIC;
signal \ARG__1_n_84\ : STD_LOGIC;
signal \ARG__1_n_85\ : STD_LOGIC;
signal \ARG__1_n_86\ : STD_LOGIC;
signal \ARG__1_n_87\ : STD_LOGIC;
signal \ARG__1_n_88\ : STD_LOGIC;
signal \ARG__1_n_89\ : STD_LOGIC;
signal \ARG__1_n_90\ : STD_LOGIC;
signal \ARG__1_n_91\ : STD_LOGIC;
signal \ARG__1_n_92\ : STD_LOGIC;
signal \ARG__1_n_93\ : STD_LOGIC;
signal \ARG__1_n_94\ : STD_LOGIC;
signal \ARG__1_n_95\ : STD_LOGIC;
signal \ARG__1_n_96\ : STD_LOGIC;
signal \ARG__1_n_97\ : STD_LOGIC;
signal \ARG__1_n_98\ : STD_LOGIC;
signal \ARG__1_n_99\ : STD_LOGIC;
signal \ARG__20_i_1_n_0\ : STD_LOGIC;
signal \ARG__20_n_100\ : STD_LOGIC;
signal \ARG__20_n_101\ : STD_LOGIC;
signal \ARG__20_n_102\ : STD_LOGIC;
signal \ARG__20_n_103\ : STD_LOGIC;
signal \ARG__20_n_104\ : STD_LOGIC;
signal \ARG__20_n_105\ : STD_LOGIC;
signal \ARG__20_n_92\ : STD_LOGIC;
signal \ARG__20_n_93\ : STD_LOGIC;
signal \ARG__20_n_94\ : STD_LOGIC;
signal \ARG__20_n_95\ : STD_LOGIC;
signal \ARG__20_n_96\ : STD_LOGIC;
signal \ARG__20_n_97\ : STD_LOGIC;
signal \ARG__20_n_98\ : STD_LOGIC;
signal \ARG__20_n_99\ : STD_LOGIC;
signal \ARG__21_i_1_n_0\ : STD_LOGIC;
signal \ARG__21_n_100\ : STD_LOGIC;
signal \ARG__21_n_101\ : STD_LOGIC;
signal \ARG__21_n_102\ : STD_LOGIC;
signal \ARG__21_n_103\ : STD_LOGIC;
signal \ARG__21_n_104\ : STD_LOGIC;
signal \ARG__21_n_105\ : STD_LOGIC;
signal \ARG__21_n_76\ : STD_LOGIC;
signal \ARG__21_n_77\ : STD_LOGIC;
signal \ARG__21_n_78\ : STD_LOGIC;
signal \ARG__21_n_79\ : STD_LOGIC;
signal \ARG__21_n_80\ : STD_LOGIC;
signal \ARG__21_n_81\ : STD_LOGIC;
signal \ARG__21_n_82\ : STD_LOGIC;
signal \ARG__21_n_83\ : STD_LOGIC;
signal \ARG__21_n_84\ : STD_LOGIC;
signal \ARG__21_n_85\ : STD_LOGIC;
signal \ARG__21_n_86\ : STD_LOGIC;
signal \ARG__21_n_87\ : STD_LOGIC;
signal \ARG__21_n_88\ : STD_LOGIC;
signal \ARG__21_n_89\ : STD_LOGIC;
signal \ARG__21_n_90\ : STD_LOGIC;
signal \ARG__21_n_91\ : STD_LOGIC;
signal \ARG__21_n_92\ : STD_LOGIC;
signal \ARG__21_n_93\ : STD_LOGIC;
signal \ARG__21_n_94\ : STD_LOGIC;
signal \ARG__21_n_95\ : STD_LOGIC;
signal \ARG__21_n_96\ : STD_LOGIC;
signal \ARG__21_n_97\ : STD_LOGIC;
signal \ARG__21_n_98\ : STD_LOGIC;
signal \ARG__21_n_99\ : STD_LOGIC;
signal \ARG__22_i_1_n_0\ : STD_LOGIC;
signal \ARG__22_n_100\ : STD_LOGIC;
signal \ARG__22_n_101\ : STD_LOGIC;
signal \ARG__22_n_102\ : STD_LOGIC;
signal \ARG__22_n_103\ : STD_LOGIC;
signal \ARG__22_n_104\ : STD_LOGIC;
signal \ARG__22_n_105\ : STD_LOGIC;
signal \ARG__22_n_92\ : STD_LOGIC;
signal \ARG__22_n_93\ : STD_LOGIC;
signal \ARG__22_n_94\ : STD_LOGIC;
signal \ARG__22_n_95\ : STD_LOGIC;
signal \ARG__22_n_96\ : STD_LOGIC;
signal \ARG__22_n_97\ : STD_LOGIC;
signal \ARG__22_n_98\ : STD_LOGIC;
signal \ARG__22_n_99\ : STD_LOGIC;
signal \ARG__23_i_1_n_0\ : STD_LOGIC;
signal \ARG__23_n_100\ : STD_LOGIC;
signal \ARG__23_n_101\ : STD_LOGIC;
signal \ARG__23_n_102\ : STD_LOGIC;
signal \ARG__23_n_103\ : STD_LOGIC;
signal \ARG__23_n_104\ : STD_LOGIC;
signal \ARG__23_n_105\ : STD_LOGIC;
signal \ARG__23_n_76\ : STD_LOGIC;
signal \ARG__23_n_77\ : STD_LOGIC;
signal \ARG__23_n_78\ : STD_LOGIC;
signal \ARG__23_n_79\ : STD_LOGIC;
signal \ARG__23_n_80\ : STD_LOGIC;
signal \ARG__23_n_81\ : STD_LOGIC;
signal \ARG__23_n_82\ : STD_LOGIC;
signal \ARG__23_n_83\ : STD_LOGIC;
signal \ARG__23_n_84\ : STD_LOGIC;
signal \ARG__23_n_85\ : STD_LOGIC;
signal \ARG__23_n_86\ : STD_LOGIC;
signal \ARG__23_n_87\ : STD_LOGIC;
signal \ARG__23_n_88\ : STD_LOGIC;
signal \ARG__23_n_89\ : STD_LOGIC;
signal \ARG__23_n_90\ : STD_LOGIC;
signal \ARG__23_n_91\ : STD_LOGIC;
signal \ARG__23_n_92\ : STD_LOGIC;
signal \ARG__23_n_93\ : STD_LOGIC;
signal \ARG__23_n_94\ : STD_LOGIC;
signal \ARG__23_n_95\ : STD_LOGIC;
signal \ARG__23_n_96\ : STD_LOGIC;
signal \ARG__23_n_97\ : STD_LOGIC;
signal \ARG__23_n_98\ : STD_LOGIC;
signal \ARG__23_n_99\ : STD_LOGIC;
signal \ARG__24_i_1_n_0\ : STD_LOGIC;
signal \ARG__24_n_100\ : STD_LOGIC;
signal \ARG__24_n_101\ : STD_LOGIC;
signal \ARG__24_n_102\ : STD_LOGIC;
signal \ARG__24_n_103\ : STD_LOGIC;
signal \ARG__24_n_104\ : STD_LOGIC;
signal \ARG__24_n_105\ : STD_LOGIC;
signal \ARG__24_n_92\ : STD_LOGIC;
signal \ARG__24_n_93\ : STD_LOGIC;
signal \ARG__24_n_94\ : STD_LOGIC;
signal \ARG__24_n_95\ : STD_LOGIC;
signal \ARG__24_n_96\ : STD_LOGIC;
signal \ARG__24_n_97\ : STD_LOGIC;
signal \ARG__24_n_98\ : STD_LOGIC;
signal \ARG__24_n_99\ : STD_LOGIC;
signal \ARG__25_i_1_n_0\ : STD_LOGIC;
signal \ARG__25_n_100\ : STD_LOGIC;
signal \ARG__25_n_101\ : STD_LOGIC;
signal \ARG__25_n_102\ : STD_LOGIC;
signal \ARG__25_n_103\ : STD_LOGIC;
signal \ARG__25_n_104\ : STD_LOGIC;
signal \ARG__25_n_105\ : STD_LOGIC;
signal \ARG__25_n_76\ : STD_LOGIC;
signal \ARG__25_n_77\ : STD_LOGIC;
signal \ARG__25_n_78\ : STD_LOGIC;
signal \ARG__25_n_79\ : STD_LOGIC;
signal \ARG__25_n_80\ : STD_LOGIC;
signal \ARG__25_n_81\ : STD_LOGIC;
signal \ARG__25_n_82\ : STD_LOGIC;
signal \ARG__25_n_83\ : STD_LOGIC;
signal \ARG__25_n_84\ : STD_LOGIC;
signal \ARG__25_n_85\ : STD_LOGIC;
signal \ARG__25_n_86\ : STD_LOGIC;
signal \ARG__25_n_87\ : STD_LOGIC;
signal \ARG__25_n_88\ : STD_LOGIC;
signal \ARG__25_n_89\ : STD_LOGIC;
signal \ARG__25_n_90\ : STD_LOGIC;
signal \ARG__25_n_91\ : STD_LOGIC;
signal \ARG__25_n_92\ : STD_LOGIC;
signal \ARG__25_n_93\ : STD_LOGIC;
signal \ARG__25_n_94\ : STD_LOGIC;
signal \ARG__25_n_95\ : STD_LOGIC;
signal \ARG__25_n_96\ : STD_LOGIC;
signal \ARG__25_n_97\ : STD_LOGIC;
signal \ARG__25_n_98\ : STD_LOGIC;
signal \ARG__25_n_99\ : STD_LOGIC;
signal \ARG__26_i_1_n_0\ : STD_LOGIC;
signal \ARG__26_n_100\ : STD_LOGIC;
signal \ARG__26_n_101\ : STD_LOGIC;
signal \ARG__26_n_102\ : STD_LOGIC;
signal \ARG__26_n_103\ : STD_LOGIC;
signal \ARG__26_n_104\ : STD_LOGIC;
signal \ARG__26_n_105\ : STD_LOGIC;
signal \ARG__26_n_92\ : STD_LOGIC;
signal \ARG__26_n_93\ : STD_LOGIC;
signal \ARG__26_n_94\ : STD_LOGIC;
signal \ARG__26_n_95\ : STD_LOGIC;
signal \ARG__26_n_96\ : STD_LOGIC;
signal \ARG__26_n_97\ : STD_LOGIC;
signal \ARG__26_n_98\ : STD_LOGIC;
signal \ARG__26_n_99\ : STD_LOGIC;
signal \ARG__27_i_1_n_0\ : STD_LOGIC;
signal \ARG__27_n_100\ : STD_LOGIC;
signal \ARG__27_n_101\ : STD_LOGIC;
signal \ARG__27_n_102\ : STD_LOGIC;
signal \ARG__27_n_103\ : STD_LOGIC;
signal \ARG__27_n_104\ : STD_LOGIC;
signal \ARG__27_n_105\ : STD_LOGIC;
signal \ARG__27_n_76\ : STD_LOGIC;
signal \ARG__27_n_77\ : STD_LOGIC;
signal \ARG__27_n_78\ : STD_LOGIC;
signal \ARG__27_n_79\ : STD_LOGIC;
signal \ARG__27_n_80\ : STD_LOGIC;
signal \ARG__27_n_81\ : STD_LOGIC;
signal \ARG__27_n_82\ : STD_LOGIC;
signal \ARG__27_n_83\ : STD_LOGIC;
signal \ARG__27_n_84\ : STD_LOGIC;
signal \ARG__27_n_85\ : STD_LOGIC;
signal \ARG__27_n_86\ : STD_LOGIC;
signal \ARG__27_n_87\ : STD_LOGIC;
signal \ARG__27_n_88\ : STD_LOGIC;
signal \ARG__27_n_89\ : STD_LOGIC;
signal \ARG__27_n_90\ : STD_LOGIC;
signal \ARG__27_n_91\ : STD_LOGIC;
signal \ARG__27_n_92\ : STD_LOGIC;
signal \ARG__27_n_93\ : STD_LOGIC;
signal \ARG__27_n_94\ : STD_LOGIC;
signal \ARG__27_n_95\ : STD_LOGIC;
signal \ARG__27_n_96\ : STD_LOGIC;
signal \ARG__27_n_97\ : STD_LOGIC;
signal \ARG__27_n_98\ : STD_LOGIC;
signal \ARG__27_n_99\ : STD_LOGIC;
signal \ARG__28_i_1_n_0\ : STD_LOGIC;
signal \ARG__28_n_100\ : STD_LOGIC;
signal \ARG__28_n_101\ : STD_LOGIC;
signal \ARG__28_n_102\ : STD_LOGIC;
signal \ARG__28_n_103\ : STD_LOGIC;
signal \ARG__28_n_104\ : STD_LOGIC;
signal \ARG__28_n_105\ : STD_LOGIC;
signal \ARG__28_n_92\ : STD_LOGIC;
signal \ARG__28_n_93\ : STD_LOGIC;
signal \ARG__28_n_94\ : STD_LOGIC;
signal \ARG__28_n_95\ : STD_LOGIC;
signal \ARG__28_n_96\ : STD_LOGIC;
signal \ARG__28_n_97\ : STD_LOGIC;
signal \ARG__28_n_98\ : STD_LOGIC;
signal \ARG__28_n_99\ : STD_LOGIC;
signal \ARG__29_i_1_n_0\ : STD_LOGIC;
signal \ARG__29_n_100\ : STD_LOGIC;
signal \ARG__29_n_101\ : STD_LOGIC;
signal \ARG__29_n_102\ : STD_LOGIC;
signal \ARG__29_n_103\ : STD_LOGIC;
signal \ARG__29_n_104\ : STD_LOGIC;
signal \ARG__29_n_105\ : STD_LOGIC;
signal \ARG__29_n_76\ : STD_LOGIC;
signal \ARG__29_n_77\ : STD_LOGIC;
signal \ARG__29_n_78\ : STD_LOGIC;
signal \ARG__29_n_79\ : STD_LOGIC;
signal \ARG__29_n_80\ : STD_LOGIC;
signal \ARG__29_n_81\ : STD_LOGIC;
signal \ARG__29_n_82\ : STD_LOGIC;
signal \ARG__29_n_83\ : STD_LOGIC;
signal \ARG__29_n_84\ : STD_LOGIC;
signal \ARG__29_n_85\ : STD_LOGIC;
signal \ARG__29_n_86\ : STD_LOGIC;
signal \ARG__29_n_87\ : STD_LOGIC;
signal \ARG__29_n_88\ : STD_LOGIC;
signal \ARG__29_n_89\ : STD_LOGIC;
signal \ARG__29_n_90\ : STD_LOGIC;
signal \ARG__29_n_91\ : STD_LOGIC;
signal \ARG__29_n_92\ : STD_LOGIC;
signal \ARG__29_n_93\ : STD_LOGIC;
signal \ARG__29_n_94\ : STD_LOGIC;
signal \ARG__29_n_95\ : STD_LOGIC;
signal \ARG__29_n_96\ : STD_LOGIC;
signal \ARG__29_n_97\ : STD_LOGIC;
signal \ARG__29_n_98\ : STD_LOGIC;
signal \ARG__29_n_99\ : STD_LOGIC;
signal \ARG__2_i_1_n_0\ : STD_LOGIC;
signal \ARG__2_n_100\ : STD_LOGIC;
signal \ARG__2_n_101\ : STD_LOGIC;
signal \ARG__2_n_102\ : STD_LOGIC;
signal \ARG__2_n_103\ : STD_LOGIC;
signal \ARG__2_n_104\ : STD_LOGIC;
signal \ARG__2_n_105\ : STD_LOGIC;
signal \ARG__2_n_92\ : STD_LOGIC;
signal \ARG__2_n_93\ : STD_LOGIC;
signal \ARG__2_n_94\ : STD_LOGIC;
signal \ARG__2_n_95\ : STD_LOGIC;
signal \ARG__2_n_96\ : STD_LOGIC;
signal \ARG__2_n_97\ : STD_LOGIC;
signal \ARG__2_n_98\ : STD_LOGIC;
signal \ARG__2_n_99\ : STD_LOGIC;
signal \ARG__30_i_1_n_0\ : STD_LOGIC;
signal \ARG__30_n_100\ : STD_LOGIC;
signal \ARG__30_n_101\ : STD_LOGIC;
signal \ARG__30_n_102\ : STD_LOGIC;
signal \ARG__30_n_103\ : STD_LOGIC;
signal \ARG__30_n_104\ : STD_LOGIC;
signal \ARG__30_n_105\ : STD_LOGIC;
signal \ARG__30_n_92\ : STD_LOGIC;
signal \ARG__30_n_93\ : STD_LOGIC;
signal \ARG__30_n_94\ : STD_LOGIC;
signal \ARG__30_n_95\ : STD_LOGIC;
signal \ARG__30_n_96\ : STD_LOGIC;
signal \ARG__30_n_97\ : STD_LOGIC;
signal \ARG__30_n_98\ : STD_LOGIC;
signal \ARG__30_n_99\ : STD_LOGIC;
signal \ARG__31\ : STD_LOGIC_VECTOR ( 32 downto 17 );
signal \ARG__3_i_1_n_0\ : STD_LOGIC;
signal \ARG__3_n_100\ : STD_LOGIC;
signal \ARG__3_n_101\ : STD_LOGIC;
signal \ARG__3_n_102\ : STD_LOGIC;
signal \ARG__3_n_103\ : STD_LOGIC;
signal \ARG__3_n_104\ : STD_LOGIC;
signal \ARG__3_n_105\ : STD_LOGIC;
signal \ARG__3_n_76\ : STD_LOGIC;
signal \ARG__3_n_77\ : STD_LOGIC;
signal \ARG__3_n_78\ : STD_LOGIC;
signal \ARG__3_n_79\ : STD_LOGIC;
signal \ARG__3_n_80\ : STD_LOGIC;
signal \ARG__3_n_81\ : STD_LOGIC;
signal \ARG__3_n_82\ : STD_LOGIC;
signal \ARG__3_n_83\ : STD_LOGIC;
signal \ARG__3_n_84\ : STD_LOGIC;
signal \ARG__3_n_85\ : STD_LOGIC;
signal \ARG__3_n_86\ : STD_LOGIC;
signal \ARG__3_n_87\ : STD_LOGIC;
signal \ARG__3_n_88\ : STD_LOGIC;
signal \ARG__3_n_89\ : STD_LOGIC;
signal \ARG__3_n_90\ : STD_LOGIC;
signal \ARG__3_n_91\ : STD_LOGIC;
signal \ARG__3_n_92\ : STD_LOGIC;
signal \ARG__3_n_93\ : STD_LOGIC;
signal \ARG__3_n_94\ : STD_LOGIC;
signal \ARG__3_n_95\ : STD_LOGIC;
signal \ARG__3_n_96\ : STD_LOGIC;
signal \ARG__3_n_97\ : STD_LOGIC;
signal \ARG__3_n_98\ : STD_LOGIC;
signal \ARG__3_n_99\ : STD_LOGIC;
signal \ARG__4_i_1_n_0\ : STD_LOGIC;
signal \ARG__4_n_100\ : STD_LOGIC;
signal \ARG__4_n_101\ : STD_LOGIC;
signal \ARG__4_n_102\ : STD_LOGIC;
signal \ARG__4_n_103\ : STD_LOGIC;
signal \ARG__4_n_104\ : STD_LOGIC;
signal \ARG__4_n_105\ : STD_LOGIC;
signal \ARG__4_n_92\ : STD_LOGIC;
signal \ARG__4_n_93\ : STD_LOGIC;
signal \ARG__4_n_94\ : STD_LOGIC;
signal \ARG__4_n_95\ : STD_LOGIC;
signal \ARG__4_n_96\ : STD_LOGIC;
signal \ARG__4_n_97\ : STD_LOGIC;
signal \ARG__4_n_98\ : STD_LOGIC;
signal \ARG__4_n_99\ : STD_LOGIC;
signal \ARG__5_i_1_n_0\ : STD_LOGIC;
signal \ARG__5_n_100\ : STD_LOGIC;
signal \ARG__5_n_101\ : STD_LOGIC;
signal \ARG__5_n_102\ : STD_LOGIC;
signal \ARG__5_n_103\ : STD_LOGIC;
signal \ARG__5_n_104\ : STD_LOGIC;
signal \ARG__5_n_105\ : STD_LOGIC;
signal \ARG__5_n_76\ : STD_LOGIC;
signal \ARG__5_n_77\ : STD_LOGIC;
signal \ARG__5_n_78\ : STD_LOGIC;
signal \ARG__5_n_79\ : STD_LOGIC;
signal \ARG__5_n_80\ : STD_LOGIC;
signal \ARG__5_n_81\ : STD_LOGIC;
signal \ARG__5_n_82\ : STD_LOGIC;
signal \ARG__5_n_83\ : STD_LOGIC;
signal \ARG__5_n_84\ : STD_LOGIC;
signal \ARG__5_n_85\ : STD_LOGIC;
signal \ARG__5_n_86\ : STD_LOGIC;
signal \ARG__5_n_87\ : STD_LOGIC;
signal \ARG__5_n_88\ : STD_LOGIC;
signal \ARG__5_n_89\ : STD_LOGIC;
signal \ARG__5_n_90\ : STD_LOGIC;
signal \ARG__5_n_91\ : STD_LOGIC;
signal \ARG__5_n_92\ : STD_LOGIC;
signal \ARG__5_n_93\ : STD_LOGIC;
signal \ARG__5_n_94\ : STD_LOGIC;
signal \ARG__5_n_95\ : STD_LOGIC;
signal \ARG__5_n_96\ : STD_LOGIC;
signal \ARG__5_n_97\ : STD_LOGIC;
signal \ARG__5_n_98\ : STD_LOGIC;
signal \ARG__5_n_99\ : STD_LOGIC;
signal \ARG__6_i_1_n_0\ : STD_LOGIC;
signal \ARG__6_n_100\ : STD_LOGIC;
signal \ARG__6_n_101\ : STD_LOGIC;
signal \ARG__6_n_102\ : STD_LOGIC;
signal \ARG__6_n_103\ : STD_LOGIC;
signal \ARG__6_n_104\ : STD_LOGIC;
signal \ARG__6_n_105\ : STD_LOGIC;
signal \ARG__6_n_92\ : STD_LOGIC;
signal \ARG__6_n_93\ : STD_LOGIC;
signal \ARG__6_n_94\ : STD_LOGIC;
signal \ARG__6_n_95\ : STD_LOGIC;
signal \ARG__6_n_96\ : STD_LOGIC;
signal \ARG__6_n_97\ : STD_LOGIC;
signal \ARG__6_n_98\ : STD_LOGIC;
signal \ARG__6_n_99\ : STD_LOGIC;
signal \ARG__7_i_1_n_0\ : STD_LOGIC;
signal \ARG__7_n_100\ : STD_LOGIC;
signal \ARG__7_n_101\ : STD_LOGIC;
signal \ARG__7_n_102\ : STD_LOGIC;
signal \ARG__7_n_103\ : STD_LOGIC;
signal \ARG__7_n_104\ : STD_LOGIC;
signal \ARG__7_n_105\ : STD_LOGIC;
signal \ARG__7_n_76\ : STD_LOGIC;
signal \ARG__7_n_77\ : STD_LOGIC;
signal \ARG__7_n_78\ : STD_LOGIC;
signal \ARG__7_n_79\ : STD_LOGIC;
signal \ARG__7_n_80\ : STD_LOGIC;
signal \ARG__7_n_81\ : STD_LOGIC;
signal \ARG__7_n_82\ : STD_LOGIC;
signal \ARG__7_n_83\ : STD_LOGIC;
signal \ARG__7_n_84\ : STD_LOGIC;
signal \ARG__7_n_85\ : STD_LOGIC;
signal \ARG__7_n_86\ : STD_LOGIC;
signal \ARG__7_n_87\ : STD_LOGIC;
signal \ARG__7_n_88\ : STD_LOGIC;
signal \ARG__7_n_89\ : STD_LOGIC;
signal \ARG__7_n_90\ : STD_LOGIC;
signal \ARG__7_n_91\ : STD_LOGIC;
signal \ARG__7_n_92\ : STD_LOGIC;
signal \ARG__7_n_93\ : STD_LOGIC;
signal \ARG__7_n_94\ : STD_LOGIC;
signal \ARG__7_n_95\ : STD_LOGIC;
signal \ARG__7_n_96\ : STD_LOGIC;
signal \ARG__7_n_97\ : STD_LOGIC;
signal \ARG__7_n_98\ : STD_LOGIC;
signal \ARG__7_n_99\ : STD_LOGIC;
signal \ARG__8_i_1_n_0\ : STD_LOGIC;
signal \ARG__8_n_100\ : STD_LOGIC;
signal \ARG__8_n_101\ : STD_LOGIC;
signal \ARG__8_n_102\ : STD_LOGIC;
signal \ARG__8_n_103\ : STD_LOGIC;
signal \ARG__8_n_104\ : STD_LOGIC;
signal \ARG__8_n_105\ : STD_LOGIC;
signal \ARG__8_n_92\ : STD_LOGIC;
signal \ARG__8_n_93\ : STD_LOGIC;
signal \ARG__8_n_94\ : STD_LOGIC;
signal \ARG__8_n_95\ : STD_LOGIC;
signal \ARG__8_n_96\ : STD_LOGIC;
signal \ARG__8_n_97\ : STD_LOGIC;
signal \ARG__8_n_98\ : STD_LOGIC;
signal \ARG__8_n_99\ : STD_LOGIC;
signal \ARG__9_i_1_n_0\ : STD_LOGIC;
signal \ARG__9_n_100\ : STD_LOGIC;
signal \ARG__9_n_101\ : STD_LOGIC;
signal \ARG__9_n_102\ : STD_LOGIC;
signal \ARG__9_n_103\ : STD_LOGIC;
signal \ARG__9_n_104\ : STD_LOGIC;
signal \ARG__9_n_105\ : STD_LOGIC;
signal \ARG__9_n_76\ : STD_LOGIC;
signal \ARG__9_n_77\ : STD_LOGIC;
signal \ARG__9_n_78\ : STD_LOGIC;
signal \ARG__9_n_79\ : STD_LOGIC;
signal \ARG__9_n_80\ : STD_LOGIC;
signal \ARG__9_n_81\ : STD_LOGIC;
signal \ARG__9_n_82\ : STD_LOGIC;
signal \ARG__9_n_83\ : STD_LOGIC;
signal \ARG__9_n_84\ : STD_LOGIC;
signal \ARG__9_n_85\ : STD_LOGIC;
signal \ARG__9_n_86\ : STD_LOGIC;
signal \ARG__9_n_87\ : STD_LOGIC;
signal \ARG__9_n_88\ : STD_LOGIC;
signal \ARG__9_n_89\ : STD_LOGIC;
signal \ARG__9_n_90\ : STD_LOGIC;
signal \ARG__9_n_91\ : STD_LOGIC;
signal \ARG__9_n_92\ : STD_LOGIC;
signal \ARG__9_n_93\ : STD_LOGIC;
signal \ARG__9_n_94\ : STD_LOGIC;
signal \ARG__9_n_95\ : STD_LOGIC;
signal \ARG__9_n_96\ : STD_LOGIC;
signal \ARG__9_n_97\ : STD_LOGIC;
signal \ARG__9_n_98\ : STD_LOGIC;
signal \ARG__9_n_99\ : STD_LOGIC;
signal \ARG_carry__0_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_1\ : STD_LOGIC;
signal \ARG_carry__0_n_2\ : STD_LOGIC;
signal \ARG_carry__0_n_3\ : STD_LOGIC;
signal \ARG_carry__1_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_1\ : STD_LOGIC;
signal \ARG_carry__1_n_2\ : STD_LOGIC;
signal \ARG_carry__1_n_3\ : STD_LOGIC;
signal \ARG_carry__2_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_1\ : STD_LOGIC;
signal \ARG_carry__2_n_2\ : STD_LOGIC;
signal \ARG_carry__2_n_3\ : STD_LOGIC;
signal \ARG_carry__3_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__3_n_3\ : STD_LOGIC;
signal ARG_carry_n_0 : STD_LOGIC;
signal ARG_carry_n_1 : STD_LOGIC;
signal ARG_carry_n_2 : STD_LOGIC;
signal ARG_carry_n_3 : STD_LOGIC;
signal ARG_i_1_n_0 : STD_LOGIC;
signal ARG_n_100 : STD_LOGIC;
signal ARG_n_101 : STD_LOGIC;
signal ARG_n_102 : STD_LOGIC;
signal ARG_n_103 : STD_LOGIC;
signal ARG_n_104 : STD_LOGIC;
signal ARG_n_105 : STD_LOGIC;
signal ARG_n_92 : STD_LOGIC;
signal ARG_n_93 : STD_LOGIC;
signal ARG_n_94 : STD_LOGIC;
signal ARG_n_95 : STD_LOGIC;
signal ARG_n_96 : STD_LOGIC;
signal ARG_n_97 : STD_LOGIC;
signal ARG_n_98 : STD_LOGIC;
signal ARG_n_99 : STD_LOGIC;
signal RESIZE15 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE16 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE18 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE22 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE24 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE26 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE28 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE30 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE32 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE34 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE36 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE38 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE40 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE42 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE44 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \add_temp_14__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_7\ : STD_LOGIC;
signal \data_pipeline_tmp_reg[0]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[10]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[11]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[12]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[13]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[14]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[1]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[2]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[3]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[4]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[5]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[6]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[7]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[8]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[9]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \in\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_1\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_10\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_10_n_100 : STD_LOGIC;
signal mul_temp_10_n_101 : STD_LOGIC;
signal mul_temp_10_n_102 : STD_LOGIC;
signal mul_temp_10_n_103 : STD_LOGIC;
signal mul_temp_10_n_104 : STD_LOGIC;
signal mul_temp_10_n_105 : STD_LOGIC;
signal mul_temp_10_n_74 : STD_LOGIC;
signal mul_temp_10_n_75 : STD_LOGIC;
signal mul_temp_10_n_76 : STD_LOGIC;
signal mul_temp_10_n_77 : STD_LOGIC;
signal mul_temp_10_n_78 : STD_LOGIC;
signal mul_temp_10_n_79 : STD_LOGIC;
signal mul_temp_10_n_80 : STD_LOGIC;
signal mul_temp_10_n_81 : STD_LOGIC;
signal mul_temp_10_n_82 : STD_LOGIC;
signal mul_temp_10_n_83 : STD_LOGIC;
signal mul_temp_10_n_84 : STD_LOGIC;
signal mul_temp_10_n_85 : STD_LOGIC;
signal mul_temp_10_n_86 : STD_LOGIC;
signal mul_temp_10_n_87 : STD_LOGIC;
signal mul_temp_10_n_88 : STD_LOGIC;
signal mul_temp_10_n_89 : STD_LOGIC;
signal mul_temp_10_n_90 : STD_LOGIC;
signal mul_temp_10_n_92 : STD_LOGIC;
signal mul_temp_10_n_93 : STD_LOGIC;
signal mul_temp_10_n_94 : STD_LOGIC;
signal mul_temp_10_n_95 : STD_LOGIC;
signal mul_temp_10_n_96 : STD_LOGIC;
signal mul_temp_10_n_97 : STD_LOGIC;
signal mul_temp_10_n_98 : STD_LOGIC;
signal mul_temp_10_n_99 : STD_LOGIC;
signal \^mul_temp_11\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_11_n_100 : STD_LOGIC;
signal mul_temp_11_n_101 : STD_LOGIC;
signal mul_temp_11_n_102 : STD_LOGIC;
signal mul_temp_11_n_103 : STD_LOGIC;
signal mul_temp_11_n_104 : STD_LOGIC;
signal mul_temp_11_n_105 : STD_LOGIC;
signal mul_temp_11_n_74 : STD_LOGIC;
signal mul_temp_11_n_75 : STD_LOGIC;
signal mul_temp_11_n_76 : STD_LOGIC;
signal mul_temp_11_n_77 : STD_LOGIC;
signal mul_temp_11_n_78 : STD_LOGIC;
signal mul_temp_11_n_79 : STD_LOGIC;
signal mul_temp_11_n_80 : STD_LOGIC;
signal mul_temp_11_n_81 : STD_LOGIC;
signal mul_temp_11_n_82 : STD_LOGIC;
signal mul_temp_11_n_83 : STD_LOGIC;
signal mul_temp_11_n_84 : STD_LOGIC;
signal mul_temp_11_n_85 : STD_LOGIC;
signal mul_temp_11_n_86 : STD_LOGIC;
signal mul_temp_11_n_87 : STD_LOGIC;
signal mul_temp_11_n_88 : STD_LOGIC;
signal mul_temp_11_n_89 : STD_LOGIC;
signal mul_temp_11_n_90 : STD_LOGIC;
signal mul_temp_11_n_92 : STD_LOGIC;
signal mul_temp_11_n_93 : STD_LOGIC;
signal mul_temp_11_n_94 : STD_LOGIC;
signal mul_temp_11_n_95 : STD_LOGIC;
signal mul_temp_11_n_96 : STD_LOGIC;
signal mul_temp_11_n_97 : STD_LOGIC;
signal mul_temp_11_n_98 : STD_LOGIC;
signal mul_temp_11_n_99 : STD_LOGIC;
signal \^mul_temp_12\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_12_n_100 : STD_LOGIC;
signal mul_temp_12_n_101 : STD_LOGIC;
signal mul_temp_12_n_102 : STD_LOGIC;
signal mul_temp_12_n_103 : STD_LOGIC;
signal mul_temp_12_n_104 : STD_LOGIC;
signal mul_temp_12_n_105 : STD_LOGIC;
signal mul_temp_12_n_74 : STD_LOGIC;
signal mul_temp_12_n_75 : STD_LOGIC;
signal mul_temp_12_n_76 : STD_LOGIC;
signal mul_temp_12_n_77 : STD_LOGIC;
signal mul_temp_12_n_78 : STD_LOGIC;
signal mul_temp_12_n_79 : STD_LOGIC;
signal mul_temp_12_n_80 : STD_LOGIC;
signal mul_temp_12_n_81 : STD_LOGIC;
signal mul_temp_12_n_82 : STD_LOGIC;
signal mul_temp_12_n_83 : STD_LOGIC;
signal mul_temp_12_n_84 : STD_LOGIC;
signal mul_temp_12_n_85 : STD_LOGIC;
signal mul_temp_12_n_86 : STD_LOGIC;
signal mul_temp_12_n_87 : STD_LOGIC;
signal mul_temp_12_n_88 : STD_LOGIC;
signal mul_temp_12_n_89 : STD_LOGIC;
signal mul_temp_12_n_90 : STD_LOGIC;
signal mul_temp_12_n_92 : STD_LOGIC;
signal mul_temp_12_n_93 : STD_LOGIC;
signal mul_temp_12_n_94 : STD_LOGIC;
signal mul_temp_12_n_95 : STD_LOGIC;
signal mul_temp_12_n_96 : STD_LOGIC;
signal mul_temp_12_n_97 : STD_LOGIC;
signal mul_temp_12_n_98 : STD_LOGIC;
signal mul_temp_12_n_99 : STD_LOGIC;
signal \^mul_temp_13\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_13_n_100 : STD_LOGIC;
signal mul_temp_13_n_101 : STD_LOGIC;
signal mul_temp_13_n_102 : STD_LOGIC;
signal mul_temp_13_n_103 : STD_LOGIC;
signal mul_temp_13_n_104 : STD_LOGIC;
signal mul_temp_13_n_105 : STD_LOGIC;
signal mul_temp_13_n_74 : STD_LOGIC;
signal mul_temp_13_n_75 : STD_LOGIC;
signal mul_temp_13_n_76 : STD_LOGIC;
signal mul_temp_13_n_77 : STD_LOGIC;
signal mul_temp_13_n_78 : STD_LOGIC;
signal mul_temp_13_n_79 : STD_LOGIC;
signal mul_temp_13_n_80 : STD_LOGIC;
signal mul_temp_13_n_81 : STD_LOGIC;
signal mul_temp_13_n_82 : STD_LOGIC;
signal mul_temp_13_n_83 : STD_LOGIC;
signal mul_temp_13_n_84 : STD_LOGIC;
signal mul_temp_13_n_85 : STD_LOGIC;
signal mul_temp_13_n_86 : STD_LOGIC;
signal mul_temp_13_n_87 : STD_LOGIC;
signal mul_temp_13_n_88 : STD_LOGIC;
signal mul_temp_13_n_89 : STD_LOGIC;
signal mul_temp_13_n_90 : STD_LOGIC;
signal mul_temp_13_n_92 : STD_LOGIC;
signal mul_temp_13_n_93 : STD_LOGIC;
signal mul_temp_13_n_94 : STD_LOGIC;
signal mul_temp_13_n_95 : STD_LOGIC;
signal mul_temp_13_n_96 : STD_LOGIC;
signal mul_temp_13_n_97 : STD_LOGIC;
signal mul_temp_13_n_98 : STD_LOGIC;
signal mul_temp_13_n_99 : STD_LOGIC;
signal \^mul_temp_14\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_14_n_100 : STD_LOGIC;
signal mul_temp_14_n_101 : STD_LOGIC;
signal mul_temp_14_n_102 : STD_LOGIC;
signal mul_temp_14_n_103 : STD_LOGIC;
signal mul_temp_14_n_104 : STD_LOGIC;
signal mul_temp_14_n_105 : STD_LOGIC;
signal mul_temp_14_n_74 : STD_LOGIC;
signal mul_temp_14_n_75 : STD_LOGIC;
signal mul_temp_14_n_76 : STD_LOGIC;
signal mul_temp_14_n_77 : STD_LOGIC;
signal mul_temp_14_n_78 : STD_LOGIC;
signal mul_temp_14_n_79 : STD_LOGIC;
signal mul_temp_14_n_80 : STD_LOGIC;
signal mul_temp_14_n_81 : STD_LOGIC;
signal mul_temp_14_n_82 : STD_LOGIC;
signal mul_temp_14_n_83 : STD_LOGIC;
signal mul_temp_14_n_84 : STD_LOGIC;
signal mul_temp_14_n_85 : STD_LOGIC;
signal mul_temp_14_n_86 : STD_LOGIC;
signal mul_temp_14_n_87 : STD_LOGIC;
signal mul_temp_14_n_88 : STD_LOGIC;
signal mul_temp_14_n_89 : STD_LOGIC;
signal mul_temp_14_n_90 : STD_LOGIC;
signal mul_temp_14_n_92 : STD_LOGIC;
signal mul_temp_14_n_93 : STD_LOGIC;
signal mul_temp_14_n_94 : STD_LOGIC;
signal mul_temp_14_n_95 : STD_LOGIC;
signal mul_temp_14_n_96 : STD_LOGIC;
signal mul_temp_14_n_97 : STD_LOGIC;
signal mul_temp_14_n_98 : STD_LOGIC;
signal mul_temp_14_n_99 : STD_LOGIC;
signal \^mul_temp_15\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_15_n_100 : STD_LOGIC;
signal mul_temp_15_n_101 : STD_LOGIC;
signal mul_temp_15_n_102 : STD_LOGIC;
signal mul_temp_15_n_103 : STD_LOGIC;
signal mul_temp_15_n_104 : STD_LOGIC;
signal mul_temp_15_n_105 : STD_LOGIC;
signal mul_temp_15_n_74 : STD_LOGIC;
signal mul_temp_15_n_75 : STD_LOGIC;
signal mul_temp_15_n_76 : STD_LOGIC;
signal mul_temp_15_n_77 : STD_LOGIC;
signal mul_temp_15_n_78 : STD_LOGIC;
signal mul_temp_15_n_79 : STD_LOGIC;
signal mul_temp_15_n_80 : STD_LOGIC;
signal mul_temp_15_n_81 : STD_LOGIC;
signal mul_temp_15_n_82 : STD_LOGIC;
signal mul_temp_15_n_83 : STD_LOGIC;
signal mul_temp_15_n_84 : STD_LOGIC;
signal mul_temp_15_n_85 : STD_LOGIC;
signal mul_temp_15_n_86 : STD_LOGIC;
signal mul_temp_15_n_87 : STD_LOGIC;
signal mul_temp_15_n_88 : STD_LOGIC;
signal mul_temp_15_n_89 : STD_LOGIC;
signal mul_temp_15_n_90 : STD_LOGIC;
signal mul_temp_15_n_92 : STD_LOGIC;
signal mul_temp_15_n_93 : STD_LOGIC;
signal mul_temp_15_n_94 : STD_LOGIC;
signal mul_temp_15_n_95 : STD_LOGIC;
signal mul_temp_15_n_96 : STD_LOGIC;
signal mul_temp_15_n_97 : STD_LOGIC;
signal mul_temp_15_n_98 : STD_LOGIC;
signal mul_temp_15_n_99 : STD_LOGIC;
signal \^mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp_17\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_17_n_100 : STD_LOGIC;
signal mul_temp_17_n_101 : STD_LOGIC;
signal mul_temp_17_n_102 : STD_LOGIC;
signal mul_temp_17_n_103 : STD_LOGIC;
signal mul_temp_17_n_104 : STD_LOGIC;
signal mul_temp_17_n_105 : STD_LOGIC;
signal mul_temp_17_n_74 : STD_LOGIC;
signal mul_temp_17_n_75 : STD_LOGIC;
signal mul_temp_17_n_76 : STD_LOGIC;
signal mul_temp_17_n_77 : STD_LOGIC;
signal mul_temp_17_n_78 : STD_LOGIC;
signal mul_temp_17_n_79 : STD_LOGIC;
signal mul_temp_17_n_80 : STD_LOGIC;
signal mul_temp_17_n_81 : STD_LOGIC;
signal mul_temp_17_n_82 : STD_LOGIC;
signal mul_temp_17_n_83 : STD_LOGIC;
signal mul_temp_17_n_84 : STD_LOGIC;
signal mul_temp_17_n_85 : STD_LOGIC;
signal mul_temp_17_n_86 : STD_LOGIC;
signal mul_temp_17_n_87 : STD_LOGIC;
signal mul_temp_17_n_88 : STD_LOGIC;
signal mul_temp_17_n_89 : STD_LOGIC;
signal mul_temp_17_n_90 : STD_LOGIC;
signal mul_temp_17_n_92 : STD_LOGIC;
signal mul_temp_17_n_93 : STD_LOGIC;
signal mul_temp_17_n_94 : STD_LOGIC;
signal mul_temp_17_n_95 : STD_LOGIC;
signal mul_temp_17_n_96 : STD_LOGIC;
signal mul_temp_17_n_97 : STD_LOGIC;
signal mul_temp_17_n_98 : STD_LOGIC;
signal mul_temp_17_n_99 : STD_LOGIC;
signal \^mul_temp_18\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_18_n_100 : STD_LOGIC;
signal mul_temp_18_n_101 : STD_LOGIC;
signal mul_temp_18_n_102 : STD_LOGIC;
signal mul_temp_18_n_103 : STD_LOGIC;
signal mul_temp_18_n_104 : STD_LOGIC;
signal mul_temp_18_n_105 : STD_LOGIC;
signal mul_temp_18_n_74 : STD_LOGIC;
signal mul_temp_18_n_75 : STD_LOGIC;
signal mul_temp_18_n_76 : STD_LOGIC;
signal mul_temp_18_n_77 : STD_LOGIC;
signal mul_temp_18_n_78 : STD_LOGIC;
signal mul_temp_18_n_79 : STD_LOGIC;
signal mul_temp_18_n_80 : STD_LOGIC;
signal mul_temp_18_n_81 : STD_LOGIC;
signal mul_temp_18_n_82 : STD_LOGIC;
signal mul_temp_18_n_83 : STD_LOGIC;
signal mul_temp_18_n_84 : STD_LOGIC;
signal mul_temp_18_n_85 : STD_LOGIC;
signal mul_temp_18_n_86 : STD_LOGIC;
signal mul_temp_18_n_87 : STD_LOGIC;
signal mul_temp_18_n_88 : STD_LOGIC;
signal mul_temp_18_n_89 : STD_LOGIC;
signal mul_temp_18_n_90 : STD_LOGIC;
signal mul_temp_18_n_92 : STD_LOGIC;
signal mul_temp_18_n_93 : STD_LOGIC;
signal mul_temp_18_n_94 : STD_LOGIC;
signal mul_temp_18_n_95 : STD_LOGIC;
signal mul_temp_18_n_96 : STD_LOGIC;
signal mul_temp_18_n_97 : STD_LOGIC;
signal mul_temp_18_n_98 : STD_LOGIC;
signal mul_temp_18_n_99 : STD_LOGIC;
signal \^mul_temp_19\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_19_n_100 : STD_LOGIC;
signal mul_temp_19_n_101 : STD_LOGIC;
signal mul_temp_19_n_102 : STD_LOGIC;
signal mul_temp_19_n_103 : STD_LOGIC;
signal mul_temp_19_n_104 : STD_LOGIC;
signal mul_temp_19_n_105 : STD_LOGIC;
signal mul_temp_19_n_74 : STD_LOGIC;
signal mul_temp_19_n_75 : STD_LOGIC;
signal mul_temp_19_n_76 : STD_LOGIC;
signal mul_temp_19_n_77 : STD_LOGIC;
signal mul_temp_19_n_78 : STD_LOGIC;
signal mul_temp_19_n_79 : STD_LOGIC;
signal mul_temp_19_n_80 : STD_LOGIC;
signal mul_temp_19_n_81 : STD_LOGIC;
signal mul_temp_19_n_82 : STD_LOGIC;
signal mul_temp_19_n_83 : STD_LOGIC;
signal mul_temp_19_n_84 : STD_LOGIC;
signal mul_temp_19_n_85 : STD_LOGIC;
signal mul_temp_19_n_86 : STD_LOGIC;
signal mul_temp_19_n_87 : STD_LOGIC;
signal mul_temp_19_n_88 : STD_LOGIC;
signal mul_temp_19_n_89 : STD_LOGIC;
signal mul_temp_19_n_90 : STD_LOGIC;
signal mul_temp_19_n_92 : STD_LOGIC;
signal mul_temp_19_n_93 : STD_LOGIC;
signal mul_temp_19_n_94 : STD_LOGIC;
signal mul_temp_19_n_95 : STD_LOGIC;
signal mul_temp_19_n_96 : STD_LOGIC;
signal mul_temp_19_n_97 : STD_LOGIC;
signal mul_temp_19_n_98 : STD_LOGIC;
signal mul_temp_19_n_99 : STD_LOGIC;
signal mul_temp_1_n_100 : STD_LOGIC;
signal mul_temp_1_n_101 : STD_LOGIC;
signal mul_temp_1_n_102 : STD_LOGIC;
signal mul_temp_1_n_103 : STD_LOGIC;
signal mul_temp_1_n_104 : STD_LOGIC;
signal mul_temp_1_n_105 : STD_LOGIC;
signal mul_temp_1_n_74 : STD_LOGIC;
signal mul_temp_1_n_75 : STD_LOGIC;
signal mul_temp_1_n_76 : STD_LOGIC;
signal mul_temp_1_n_77 : STD_LOGIC;
signal mul_temp_1_n_78 : STD_LOGIC;
signal mul_temp_1_n_79 : STD_LOGIC;
signal mul_temp_1_n_80 : STD_LOGIC;
signal mul_temp_1_n_81 : STD_LOGIC;
signal mul_temp_1_n_82 : STD_LOGIC;
signal mul_temp_1_n_83 : STD_LOGIC;
signal mul_temp_1_n_84 : STD_LOGIC;
signal mul_temp_1_n_85 : STD_LOGIC;
signal mul_temp_1_n_86 : STD_LOGIC;
signal mul_temp_1_n_87 : STD_LOGIC;
signal mul_temp_1_n_88 : STD_LOGIC;
signal mul_temp_1_n_89 : STD_LOGIC;
signal mul_temp_1_n_90 : STD_LOGIC;
signal mul_temp_1_n_92 : STD_LOGIC;
signal mul_temp_1_n_93 : STD_LOGIC;
signal mul_temp_1_n_94 : STD_LOGIC;
signal mul_temp_1_n_95 : STD_LOGIC;
signal mul_temp_1_n_96 : STD_LOGIC;
signal mul_temp_1_n_97 : STD_LOGIC;
signal mul_temp_1_n_98 : STD_LOGIC;
signal mul_temp_1_n_99 : STD_LOGIC;
signal \^mul_temp_2\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_20\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_20_n_100 : STD_LOGIC;
signal mul_temp_20_n_101 : STD_LOGIC;
signal mul_temp_20_n_102 : STD_LOGIC;
signal mul_temp_20_n_103 : STD_LOGIC;
signal mul_temp_20_n_104 : STD_LOGIC;
signal mul_temp_20_n_105 : STD_LOGIC;
signal mul_temp_20_n_74 : STD_LOGIC;
signal mul_temp_20_n_75 : STD_LOGIC;
signal mul_temp_20_n_76 : STD_LOGIC;
signal mul_temp_20_n_77 : STD_LOGIC;
signal mul_temp_20_n_78 : STD_LOGIC;
signal mul_temp_20_n_79 : STD_LOGIC;
signal mul_temp_20_n_80 : STD_LOGIC;
signal mul_temp_20_n_81 : STD_LOGIC;
signal mul_temp_20_n_82 : STD_LOGIC;
signal mul_temp_20_n_83 : STD_LOGIC;
signal mul_temp_20_n_84 : STD_LOGIC;
signal mul_temp_20_n_85 : STD_LOGIC;
signal mul_temp_20_n_86 : STD_LOGIC;
signal mul_temp_20_n_87 : STD_LOGIC;
signal mul_temp_20_n_88 : STD_LOGIC;
signal mul_temp_20_n_89 : STD_LOGIC;
signal mul_temp_20_n_90 : STD_LOGIC;
signal mul_temp_20_n_92 : STD_LOGIC;
signal mul_temp_20_n_93 : STD_LOGIC;
signal mul_temp_20_n_94 : STD_LOGIC;
signal mul_temp_20_n_95 : STD_LOGIC;
signal mul_temp_20_n_96 : STD_LOGIC;
signal mul_temp_20_n_97 : STD_LOGIC;
signal mul_temp_20_n_98 : STD_LOGIC;
signal mul_temp_20_n_99 : STD_LOGIC;
signal \^mul_temp_21\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_21_n_100 : STD_LOGIC;
signal mul_temp_21_n_101 : STD_LOGIC;
signal mul_temp_21_n_102 : STD_LOGIC;
signal mul_temp_21_n_103 : STD_LOGIC;
signal mul_temp_21_n_104 : STD_LOGIC;
signal mul_temp_21_n_105 : STD_LOGIC;
signal mul_temp_21_n_74 : STD_LOGIC;
signal mul_temp_21_n_75 : STD_LOGIC;
signal mul_temp_21_n_76 : STD_LOGIC;
signal mul_temp_21_n_77 : STD_LOGIC;
signal mul_temp_21_n_78 : STD_LOGIC;
signal mul_temp_21_n_79 : STD_LOGIC;
signal mul_temp_21_n_80 : STD_LOGIC;
signal mul_temp_21_n_81 : STD_LOGIC;
signal mul_temp_21_n_82 : STD_LOGIC;
signal mul_temp_21_n_83 : STD_LOGIC;
signal mul_temp_21_n_84 : STD_LOGIC;
signal mul_temp_21_n_85 : STD_LOGIC;
signal mul_temp_21_n_86 : STD_LOGIC;
signal mul_temp_21_n_87 : STD_LOGIC;
signal mul_temp_21_n_88 : STD_LOGIC;
signal mul_temp_21_n_89 : STD_LOGIC;
signal mul_temp_21_n_90 : STD_LOGIC;
signal mul_temp_21_n_92 : STD_LOGIC;
signal mul_temp_21_n_93 : STD_LOGIC;
signal mul_temp_21_n_94 : STD_LOGIC;
signal mul_temp_21_n_95 : STD_LOGIC;
signal mul_temp_21_n_96 : STD_LOGIC;
signal mul_temp_21_n_97 : STD_LOGIC;
signal mul_temp_21_n_98 : STD_LOGIC;
signal mul_temp_21_n_99 : STD_LOGIC;
signal \^mul_temp_22\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_22_n_100 : STD_LOGIC;
signal mul_temp_22_n_101 : STD_LOGIC;
signal mul_temp_22_n_102 : STD_LOGIC;
signal mul_temp_22_n_103 : STD_LOGIC;
signal mul_temp_22_n_104 : STD_LOGIC;
signal mul_temp_22_n_105 : STD_LOGIC;
signal mul_temp_22_n_74 : STD_LOGIC;
signal mul_temp_22_n_75 : STD_LOGIC;
signal mul_temp_22_n_76 : STD_LOGIC;
signal mul_temp_22_n_77 : STD_LOGIC;
signal mul_temp_22_n_78 : STD_LOGIC;
signal mul_temp_22_n_79 : STD_LOGIC;
signal mul_temp_22_n_80 : STD_LOGIC;
signal mul_temp_22_n_81 : STD_LOGIC;
signal mul_temp_22_n_82 : STD_LOGIC;
signal mul_temp_22_n_83 : STD_LOGIC;
signal mul_temp_22_n_84 : STD_LOGIC;
signal mul_temp_22_n_85 : STD_LOGIC;
signal mul_temp_22_n_86 : STD_LOGIC;
signal mul_temp_22_n_87 : STD_LOGIC;
signal mul_temp_22_n_88 : STD_LOGIC;
signal mul_temp_22_n_89 : STD_LOGIC;
signal mul_temp_22_n_90 : STD_LOGIC;
signal mul_temp_22_n_92 : STD_LOGIC;
signal mul_temp_22_n_93 : STD_LOGIC;
signal mul_temp_22_n_94 : STD_LOGIC;
signal mul_temp_22_n_95 : STD_LOGIC;
signal mul_temp_22_n_96 : STD_LOGIC;
signal mul_temp_22_n_97 : STD_LOGIC;
signal mul_temp_22_n_98 : STD_LOGIC;
signal mul_temp_22_n_99 : STD_LOGIC;
signal \^mul_temp_23\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_23_n_100 : STD_LOGIC;
signal mul_temp_23_n_101 : STD_LOGIC;
signal mul_temp_23_n_102 : STD_LOGIC;
signal mul_temp_23_n_103 : STD_LOGIC;
signal mul_temp_23_n_104 : STD_LOGIC;
signal mul_temp_23_n_105 : STD_LOGIC;
signal mul_temp_23_n_74 : STD_LOGIC;
signal mul_temp_23_n_75 : STD_LOGIC;
signal mul_temp_23_n_76 : STD_LOGIC;
signal mul_temp_23_n_77 : STD_LOGIC;
signal mul_temp_23_n_78 : STD_LOGIC;
signal mul_temp_23_n_79 : STD_LOGIC;
signal mul_temp_23_n_80 : STD_LOGIC;
signal mul_temp_23_n_81 : STD_LOGIC;
signal mul_temp_23_n_82 : STD_LOGIC;
signal mul_temp_23_n_83 : STD_LOGIC;
signal mul_temp_23_n_84 : STD_LOGIC;
signal mul_temp_23_n_85 : STD_LOGIC;
signal mul_temp_23_n_86 : STD_LOGIC;
signal mul_temp_23_n_87 : STD_LOGIC;
signal mul_temp_23_n_88 : STD_LOGIC;
signal mul_temp_23_n_89 : STD_LOGIC;
signal mul_temp_23_n_90 : STD_LOGIC;
signal mul_temp_23_n_92 : STD_LOGIC;
signal mul_temp_23_n_93 : STD_LOGIC;
signal mul_temp_23_n_94 : STD_LOGIC;
signal mul_temp_23_n_95 : STD_LOGIC;
signal mul_temp_23_n_96 : STD_LOGIC;
signal mul_temp_23_n_97 : STD_LOGIC;
signal mul_temp_23_n_98 : STD_LOGIC;
signal mul_temp_23_n_99 : STD_LOGIC;
signal \^mul_temp_24\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_24_n_100 : STD_LOGIC;
signal mul_temp_24_n_101 : STD_LOGIC;
signal mul_temp_24_n_102 : STD_LOGIC;
signal mul_temp_24_n_103 : STD_LOGIC;
signal mul_temp_24_n_104 : STD_LOGIC;
signal mul_temp_24_n_105 : STD_LOGIC;
signal mul_temp_24_n_74 : STD_LOGIC;
signal mul_temp_24_n_75 : STD_LOGIC;
signal mul_temp_24_n_76 : STD_LOGIC;
signal mul_temp_24_n_77 : STD_LOGIC;
signal mul_temp_24_n_78 : STD_LOGIC;
signal mul_temp_24_n_79 : STD_LOGIC;
signal mul_temp_24_n_80 : STD_LOGIC;
signal mul_temp_24_n_81 : STD_LOGIC;
signal mul_temp_24_n_82 : STD_LOGIC;
signal mul_temp_24_n_83 : STD_LOGIC;
signal mul_temp_24_n_84 : STD_LOGIC;
signal mul_temp_24_n_85 : STD_LOGIC;
signal mul_temp_24_n_86 : STD_LOGIC;
signal mul_temp_24_n_87 : STD_LOGIC;
signal mul_temp_24_n_88 : STD_LOGIC;
signal mul_temp_24_n_89 : STD_LOGIC;
signal mul_temp_24_n_90 : STD_LOGIC;
signal mul_temp_24_n_92 : STD_LOGIC;
signal mul_temp_24_n_93 : STD_LOGIC;
signal mul_temp_24_n_94 : STD_LOGIC;
signal mul_temp_24_n_95 : STD_LOGIC;
signal mul_temp_24_n_96 : STD_LOGIC;
signal mul_temp_24_n_97 : STD_LOGIC;
signal mul_temp_24_n_98 : STD_LOGIC;
signal mul_temp_24_n_99 : STD_LOGIC;
signal \^mul_temp_25\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_25_n_100 : STD_LOGIC;
signal mul_temp_25_n_101 : STD_LOGIC;
signal mul_temp_25_n_102 : STD_LOGIC;
signal mul_temp_25_n_103 : STD_LOGIC;
signal mul_temp_25_n_104 : STD_LOGIC;
signal mul_temp_25_n_105 : STD_LOGIC;
signal mul_temp_25_n_74 : STD_LOGIC;
signal mul_temp_25_n_75 : STD_LOGIC;
signal mul_temp_25_n_76 : STD_LOGIC;
signal mul_temp_25_n_77 : STD_LOGIC;
signal mul_temp_25_n_78 : STD_LOGIC;
signal mul_temp_25_n_79 : STD_LOGIC;
signal mul_temp_25_n_80 : STD_LOGIC;
signal mul_temp_25_n_81 : STD_LOGIC;
signal mul_temp_25_n_82 : STD_LOGIC;
signal mul_temp_25_n_83 : STD_LOGIC;
signal mul_temp_25_n_84 : STD_LOGIC;
signal mul_temp_25_n_85 : STD_LOGIC;
signal mul_temp_25_n_86 : STD_LOGIC;
signal mul_temp_25_n_87 : STD_LOGIC;
signal mul_temp_25_n_88 : STD_LOGIC;
signal mul_temp_25_n_89 : STD_LOGIC;
signal mul_temp_25_n_90 : STD_LOGIC;
signal mul_temp_25_n_92 : STD_LOGIC;
signal mul_temp_25_n_93 : STD_LOGIC;
signal mul_temp_25_n_94 : STD_LOGIC;
signal mul_temp_25_n_95 : STD_LOGIC;
signal mul_temp_25_n_96 : STD_LOGIC;
signal mul_temp_25_n_97 : STD_LOGIC;
signal mul_temp_25_n_98 : STD_LOGIC;
signal mul_temp_25_n_99 : STD_LOGIC;
signal \^mul_temp_26\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_26_n_100 : STD_LOGIC;
signal mul_temp_26_n_101 : STD_LOGIC;
signal mul_temp_26_n_102 : STD_LOGIC;
signal mul_temp_26_n_103 : STD_LOGIC;
signal mul_temp_26_n_104 : STD_LOGIC;
signal mul_temp_26_n_105 : STD_LOGIC;
signal mul_temp_26_n_74 : STD_LOGIC;
signal mul_temp_26_n_75 : STD_LOGIC;
signal mul_temp_26_n_76 : STD_LOGIC;
signal mul_temp_26_n_77 : STD_LOGIC;
signal mul_temp_26_n_78 : STD_LOGIC;
signal mul_temp_26_n_79 : STD_LOGIC;
signal mul_temp_26_n_80 : STD_LOGIC;
signal mul_temp_26_n_81 : STD_LOGIC;
signal mul_temp_26_n_82 : STD_LOGIC;
signal mul_temp_26_n_83 : STD_LOGIC;
signal mul_temp_26_n_84 : STD_LOGIC;
signal mul_temp_26_n_85 : STD_LOGIC;
signal mul_temp_26_n_86 : STD_LOGIC;
signal mul_temp_26_n_87 : STD_LOGIC;
signal mul_temp_26_n_88 : STD_LOGIC;
signal mul_temp_26_n_89 : STD_LOGIC;
signal mul_temp_26_n_90 : STD_LOGIC;
signal mul_temp_26_n_92 : STD_LOGIC;
signal mul_temp_26_n_93 : STD_LOGIC;
signal mul_temp_26_n_94 : STD_LOGIC;
signal mul_temp_26_n_95 : STD_LOGIC;
signal mul_temp_26_n_96 : STD_LOGIC;
signal mul_temp_26_n_97 : STD_LOGIC;
signal mul_temp_26_n_98 : STD_LOGIC;
signal mul_temp_26_n_99 : STD_LOGIC;
signal \^mul_temp_27\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_27_n_100 : STD_LOGIC;
signal mul_temp_27_n_101 : STD_LOGIC;
signal mul_temp_27_n_102 : STD_LOGIC;
signal mul_temp_27_n_103 : STD_LOGIC;
signal mul_temp_27_n_104 : STD_LOGIC;
signal mul_temp_27_n_105 : STD_LOGIC;
signal mul_temp_27_n_74 : STD_LOGIC;
signal mul_temp_27_n_75 : STD_LOGIC;
signal mul_temp_27_n_76 : STD_LOGIC;
signal mul_temp_27_n_77 : STD_LOGIC;
signal mul_temp_27_n_78 : STD_LOGIC;
signal mul_temp_27_n_79 : STD_LOGIC;
signal mul_temp_27_n_80 : STD_LOGIC;
signal mul_temp_27_n_81 : STD_LOGIC;
signal mul_temp_27_n_82 : STD_LOGIC;
signal mul_temp_27_n_83 : STD_LOGIC;
signal mul_temp_27_n_84 : STD_LOGIC;
signal mul_temp_27_n_85 : STD_LOGIC;
signal mul_temp_27_n_86 : STD_LOGIC;
signal mul_temp_27_n_87 : STD_LOGIC;
signal mul_temp_27_n_88 : STD_LOGIC;
signal mul_temp_27_n_89 : STD_LOGIC;
signal mul_temp_27_n_90 : STD_LOGIC;
signal mul_temp_27_n_92 : STD_LOGIC;
signal mul_temp_27_n_93 : STD_LOGIC;
signal mul_temp_27_n_94 : STD_LOGIC;
signal mul_temp_27_n_95 : STD_LOGIC;
signal mul_temp_27_n_96 : STD_LOGIC;
signal mul_temp_27_n_97 : STD_LOGIC;
signal mul_temp_27_n_98 : STD_LOGIC;
signal mul_temp_27_n_99 : STD_LOGIC;
signal \^mul_temp_28\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_28_n_100 : STD_LOGIC;
signal mul_temp_28_n_101 : STD_LOGIC;
signal mul_temp_28_n_102 : STD_LOGIC;
signal mul_temp_28_n_103 : STD_LOGIC;
signal mul_temp_28_n_104 : STD_LOGIC;
signal mul_temp_28_n_105 : STD_LOGIC;
signal mul_temp_28_n_74 : STD_LOGIC;
signal mul_temp_28_n_75 : STD_LOGIC;
signal mul_temp_28_n_76 : STD_LOGIC;
signal mul_temp_28_n_77 : STD_LOGIC;
signal mul_temp_28_n_78 : STD_LOGIC;
signal mul_temp_28_n_79 : STD_LOGIC;
signal mul_temp_28_n_80 : STD_LOGIC;
signal mul_temp_28_n_81 : STD_LOGIC;
signal mul_temp_28_n_82 : STD_LOGIC;
signal mul_temp_28_n_83 : STD_LOGIC;
signal mul_temp_28_n_84 : STD_LOGIC;
signal mul_temp_28_n_85 : STD_LOGIC;
signal mul_temp_28_n_86 : STD_LOGIC;
signal mul_temp_28_n_87 : STD_LOGIC;
signal mul_temp_28_n_88 : STD_LOGIC;
signal mul_temp_28_n_89 : STD_LOGIC;
signal mul_temp_28_n_90 : STD_LOGIC;
signal mul_temp_28_n_92 : STD_LOGIC;
signal mul_temp_28_n_93 : STD_LOGIC;
signal mul_temp_28_n_94 : STD_LOGIC;
signal mul_temp_28_n_95 : STD_LOGIC;
signal mul_temp_28_n_96 : STD_LOGIC;
signal mul_temp_28_n_97 : STD_LOGIC;
signal mul_temp_28_n_98 : STD_LOGIC;
signal mul_temp_28_n_99 : STD_LOGIC;
signal \^mul_temp_29\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_29_n_100 : STD_LOGIC;
signal mul_temp_29_n_101 : STD_LOGIC;
signal mul_temp_29_n_102 : STD_LOGIC;
signal mul_temp_29_n_103 : STD_LOGIC;
signal mul_temp_29_n_104 : STD_LOGIC;
signal mul_temp_29_n_105 : STD_LOGIC;
signal mul_temp_29_n_74 : STD_LOGIC;
signal mul_temp_29_n_75 : STD_LOGIC;
signal mul_temp_29_n_76 : STD_LOGIC;
signal mul_temp_29_n_77 : STD_LOGIC;
signal mul_temp_29_n_78 : STD_LOGIC;
signal mul_temp_29_n_79 : STD_LOGIC;
signal mul_temp_29_n_80 : STD_LOGIC;
signal mul_temp_29_n_81 : STD_LOGIC;
signal mul_temp_29_n_82 : STD_LOGIC;
signal mul_temp_29_n_83 : STD_LOGIC;
signal mul_temp_29_n_84 : STD_LOGIC;
signal mul_temp_29_n_85 : STD_LOGIC;
signal mul_temp_29_n_86 : STD_LOGIC;
signal mul_temp_29_n_87 : STD_LOGIC;
signal mul_temp_29_n_88 : STD_LOGIC;
signal mul_temp_29_n_89 : STD_LOGIC;
signal mul_temp_29_n_90 : STD_LOGIC;
signal mul_temp_29_n_92 : STD_LOGIC;
signal mul_temp_29_n_93 : STD_LOGIC;
signal mul_temp_29_n_94 : STD_LOGIC;
signal mul_temp_29_n_95 : STD_LOGIC;
signal mul_temp_29_n_96 : STD_LOGIC;
signal mul_temp_29_n_97 : STD_LOGIC;
signal mul_temp_29_n_98 : STD_LOGIC;
signal mul_temp_29_n_99 : STD_LOGIC;
signal mul_temp_2_n_100 : STD_LOGIC;
signal mul_temp_2_n_101 : STD_LOGIC;
signal mul_temp_2_n_102 : STD_LOGIC;
signal mul_temp_2_n_103 : STD_LOGIC;
signal mul_temp_2_n_104 : STD_LOGIC;
signal mul_temp_2_n_105 : STD_LOGIC;
signal mul_temp_2_n_74 : STD_LOGIC;
signal mul_temp_2_n_75 : STD_LOGIC;
signal mul_temp_2_n_76 : STD_LOGIC;
signal mul_temp_2_n_77 : STD_LOGIC;
signal mul_temp_2_n_78 : STD_LOGIC;
signal mul_temp_2_n_79 : STD_LOGIC;
signal mul_temp_2_n_80 : STD_LOGIC;
signal mul_temp_2_n_81 : STD_LOGIC;
signal mul_temp_2_n_82 : STD_LOGIC;
signal mul_temp_2_n_83 : STD_LOGIC;
signal mul_temp_2_n_84 : STD_LOGIC;
signal mul_temp_2_n_85 : STD_LOGIC;
signal mul_temp_2_n_86 : STD_LOGIC;
signal mul_temp_2_n_87 : STD_LOGIC;
signal mul_temp_2_n_88 : STD_LOGIC;
signal mul_temp_2_n_89 : STD_LOGIC;
signal mul_temp_2_n_90 : STD_LOGIC;
signal mul_temp_2_n_92 : STD_LOGIC;
signal mul_temp_2_n_93 : STD_LOGIC;
signal mul_temp_2_n_94 : STD_LOGIC;
signal mul_temp_2_n_95 : STD_LOGIC;
signal mul_temp_2_n_96 : STD_LOGIC;
signal mul_temp_2_n_97 : STD_LOGIC;
signal mul_temp_2_n_98 : STD_LOGIC;
signal mul_temp_2_n_99 : STD_LOGIC;
signal \^mul_temp_3\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_30\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_30_n_100 : STD_LOGIC;
signal mul_temp_30_n_101 : STD_LOGIC;
signal mul_temp_30_n_102 : STD_LOGIC;
signal mul_temp_30_n_103 : STD_LOGIC;
signal mul_temp_30_n_104 : STD_LOGIC;
signal mul_temp_30_n_105 : STD_LOGIC;
signal mul_temp_30_n_74 : STD_LOGIC;
signal mul_temp_30_n_75 : STD_LOGIC;
signal mul_temp_30_n_76 : STD_LOGIC;
signal mul_temp_30_n_77 : STD_LOGIC;
signal mul_temp_30_n_78 : STD_LOGIC;
signal mul_temp_30_n_79 : STD_LOGIC;
signal mul_temp_30_n_80 : STD_LOGIC;
signal mul_temp_30_n_81 : STD_LOGIC;
signal mul_temp_30_n_82 : STD_LOGIC;
signal mul_temp_30_n_83 : STD_LOGIC;
signal mul_temp_30_n_84 : STD_LOGIC;
signal mul_temp_30_n_85 : STD_LOGIC;
signal mul_temp_30_n_86 : STD_LOGIC;
signal mul_temp_30_n_87 : STD_LOGIC;
signal mul_temp_30_n_88 : STD_LOGIC;
signal mul_temp_30_n_89 : STD_LOGIC;
signal mul_temp_30_n_90 : STD_LOGIC;
signal mul_temp_30_n_92 : STD_LOGIC;
signal mul_temp_30_n_93 : STD_LOGIC;
signal mul_temp_30_n_94 : STD_LOGIC;
signal mul_temp_30_n_95 : STD_LOGIC;
signal mul_temp_30_n_96 : STD_LOGIC;
signal mul_temp_30_n_97 : STD_LOGIC;
signal mul_temp_30_n_98 : STD_LOGIC;
signal mul_temp_30_n_99 : STD_LOGIC;
signal \^mul_temp_31\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_31_n_100 : STD_LOGIC;
signal mul_temp_31_n_101 : STD_LOGIC;
signal mul_temp_31_n_102 : STD_LOGIC;
signal mul_temp_31_n_103 : STD_LOGIC;
signal mul_temp_31_n_104 : STD_LOGIC;
signal mul_temp_31_n_105 : STD_LOGIC;
signal mul_temp_31_n_74 : STD_LOGIC;
signal mul_temp_31_n_75 : STD_LOGIC;
signal mul_temp_31_n_76 : STD_LOGIC;
signal mul_temp_31_n_77 : STD_LOGIC;
signal mul_temp_31_n_78 : STD_LOGIC;
signal mul_temp_31_n_79 : STD_LOGIC;
signal mul_temp_31_n_80 : STD_LOGIC;
signal mul_temp_31_n_81 : STD_LOGIC;
signal mul_temp_31_n_82 : STD_LOGIC;
signal mul_temp_31_n_83 : STD_LOGIC;
signal mul_temp_31_n_84 : STD_LOGIC;
signal mul_temp_31_n_85 : STD_LOGIC;
signal mul_temp_31_n_86 : STD_LOGIC;
signal mul_temp_31_n_87 : STD_LOGIC;
signal mul_temp_31_n_88 : STD_LOGIC;
signal mul_temp_31_n_89 : STD_LOGIC;
signal mul_temp_31_n_90 : STD_LOGIC;
signal mul_temp_31_n_92 : STD_LOGIC;
signal mul_temp_31_n_93 : STD_LOGIC;
signal mul_temp_31_n_94 : STD_LOGIC;
signal mul_temp_31_n_95 : STD_LOGIC;
signal mul_temp_31_n_96 : STD_LOGIC;
signal mul_temp_31_n_97 : STD_LOGIC;
signal mul_temp_31_n_98 : STD_LOGIC;
signal mul_temp_31_n_99 : STD_LOGIC;
signal \^mul_temp_32\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_32_n_100 : STD_LOGIC;
signal mul_temp_32_n_101 : STD_LOGIC;
signal mul_temp_32_n_102 : STD_LOGIC;
signal mul_temp_32_n_103 : STD_LOGIC;
signal mul_temp_32_n_104 : STD_LOGIC;
signal mul_temp_32_n_105 : STD_LOGIC;
signal mul_temp_32_n_74 : STD_LOGIC;
signal mul_temp_32_n_75 : STD_LOGIC;
signal mul_temp_32_n_76 : STD_LOGIC;
signal mul_temp_32_n_77 : STD_LOGIC;
signal mul_temp_32_n_78 : STD_LOGIC;
signal mul_temp_32_n_79 : STD_LOGIC;
signal mul_temp_32_n_80 : STD_LOGIC;
signal mul_temp_32_n_81 : STD_LOGIC;
signal mul_temp_32_n_82 : STD_LOGIC;
signal mul_temp_32_n_83 : STD_LOGIC;
signal mul_temp_32_n_84 : STD_LOGIC;
signal mul_temp_32_n_85 : STD_LOGIC;
signal mul_temp_32_n_86 : STD_LOGIC;
signal mul_temp_32_n_87 : STD_LOGIC;
signal mul_temp_32_n_88 : STD_LOGIC;
signal mul_temp_32_n_89 : STD_LOGIC;
signal mul_temp_32_n_90 : STD_LOGIC;
signal mul_temp_32_n_92 : STD_LOGIC;
signal mul_temp_32_n_93 : STD_LOGIC;
signal mul_temp_32_n_94 : STD_LOGIC;
signal mul_temp_32_n_95 : STD_LOGIC;
signal mul_temp_32_n_96 : STD_LOGIC;
signal mul_temp_32_n_97 : STD_LOGIC;
signal mul_temp_32_n_98 : STD_LOGIC;
signal mul_temp_32_n_99 : STD_LOGIC;
signal mul_temp_3_n_100 : STD_LOGIC;
signal mul_temp_3_n_101 : STD_LOGIC;
signal mul_temp_3_n_102 : STD_LOGIC;
signal mul_temp_3_n_103 : STD_LOGIC;
signal mul_temp_3_n_104 : STD_LOGIC;
signal mul_temp_3_n_105 : STD_LOGIC;
signal mul_temp_3_n_74 : STD_LOGIC;
signal mul_temp_3_n_75 : STD_LOGIC;
signal mul_temp_3_n_76 : STD_LOGIC;
signal mul_temp_3_n_77 : STD_LOGIC;
signal mul_temp_3_n_78 : STD_LOGIC;
signal mul_temp_3_n_79 : STD_LOGIC;
signal mul_temp_3_n_80 : STD_LOGIC;
signal mul_temp_3_n_81 : STD_LOGIC;
signal mul_temp_3_n_82 : STD_LOGIC;
signal mul_temp_3_n_83 : STD_LOGIC;
signal mul_temp_3_n_84 : STD_LOGIC;
signal mul_temp_3_n_85 : STD_LOGIC;
signal mul_temp_3_n_86 : STD_LOGIC;
signal mul_temp_3_n_87 : STD_LOGIC;
signal mul_temp_3_n_88 : STD_LOGIC;
signal mul_temp_3_n_89 : STD_LOGIC;
signal mul_temp_3_n_90 : STD_LOGIC;
signal mul_temp_3_n_92 : STD_LOGIC;
signal mul_temp_3_n_93 : STD_LOGIC;
signal mul_temp_3_n_94 : STD_LOGIC;
signal mul_temp_3_n_95 : STD_LOGIC;
signal mul_temp_3_n_96 : STD_LOGIC;
signal mul_temp_3_n_97 : STD_LOGIC;
signal mul_temp_3_n_98 : STD_LOGIC;
signal mul_temp_3_n_99 : STD_LOGIC;
signal \^mul_temp_4\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_4_n_100 : STD_LOGIC;
signal mul_temp_4_n_101 : STD_LOGIC;
signal mul_temp_4_n_102 : STD_LOGIC;
signal mul_temp_4_n_103 : STD_LOGIC;
signal mul_temp_4_n_104 : STD_LOGIC;
signal mul_temp_4_n_105 : STD_LOGIC;
signal mul_temp_4_n_74 : STD_LOGIC;
signal mul_temp_4_n_75 : STD_LOGIC;
signal mul_temp_4_n_76 : STD_LOGIC;
signal mul_temp_4_n_77 : STD_LOGIC;
signal mul_temp_4_n_78 : STD_LOGIC;
signal mul_temp_4_n_79 : STD_LOGIC;
signal mul_temp_4_n_80 : STD_LOGIC;
signal mul_temp_4_n_81 : STD_LOGIC;
signal mul_temp_4_n_82 : STD_LOGIC;
signal mul_temp_4_n_83 : STD_LOGIC;
signal mul_temp_4_n_84 : STD_LOGIC;
signal mul_temp_4_n_85 : STD_LOGIC;
signal mul_temp_4_n_86 : STD_LOGIC;
signal mul_temp_4_n_87 : STD_LOGIC;
signal mul_temp_4_n_88 : STD_LOGIC;
signal mul_temp_4_n_89 : STD_LOGIC;
signal mul_temp_4_n_90 : STD_LOGIC;
signal mul_temp_4_n_92 : STD_LOGIC;
signal mul_temp_4_n_93 : STD_LOGIC;
signal mul_temp_4_n_94 : STD_LOGIC;
signal mul_temp_4_n_95 : STD_LOGIC;
signal mul_temp_4_n_96 : STD_LOGIC;
signal mul_temp_4_n_97 : STD_LOGIC;
signal mul_temp_4_n_98 : STD_LOGIC;
signal mul_temp_4_n_99 : STD_LOGIC;
signal \^mul_temp_5\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_5_n_100 : STD_LOGIC;
signal mul_temp_5_n_101 : STD_LOGIC;
signal mul_temp_5_n_102 : STD_LOGIC;
signal mul_temp_5_n_103 : STD_LOGIC;
signal mul_temp_5_n_104 : STD_LOGIC;
signal mul_temp_5_n_105 : STD_LOGIC;
signal mul_temp_5_n_74 : STD_LOGIC;
signal mul_temp_5_n_75 : STD_LOGIC;
signal mul_temp_5_n_76 : STD_LOGIC;
signal mul_temp_5_n_77 : STD_LOGIC;
signal mul_temp_5_n_78 : STD_LOGIC;
signal mul_temp_5_n_79 : STD_LOGIC;
signal mul_temp_5_n_80 : STD_LOGIC;
signal mul_temp_5_n_81 : STD_LOGIC;
signal mul_temp_5_n_82 : STD_LOGIC;
signal mul_temp_5_n_83 : STD_LOGIC;
signal mul_temp_5_n_84 : STD_LOGIC;
signal mul_temp_5_n_85 : STD_LOGIC;
signal mul_temp_5_n_86 : STD_LOGIC;
signal mul_temp_5_n_87 : STD_LOGIC;
signal mul_temp_5_n_88 : STD_LOGIC;
signal mul_temp_5_n_89 : STD_LOGIC;
signal mul_temp_5_n_90 : STD_LOGIC;
signal mul_temp_5_n_92 : STD_LOGIC;
signal mul_temp_5_n_93 : STD_LOGIC;
signal mul_temp_5_n_94 : STD_LOGIC;
signal mul_temp_5_n_95 : STD_LOGIC;
signal mul_temp_5_n_96 : STD_LOGIC;
signal mul_temp_5_n_97 : STD_LOGIC;
signal mul_temp_5_n_98 : STD_LOGIC;
signal mul_temp_5_n_99 : STD_LOGIC;
signal \^mul_temp_6\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_6_n_100 : STD_LOGIC;
signal mul_temp_6_n_101 : STD_LOGIC;
signal mul_temp_6_n_102 : STD_LOGIC;
signal mul_temp_6_n_103 : STD_LOGIC;
signal mul_temp_6_n_104 : STD_LOGIC;
signal mul_temp_6_n_105 : STD_LOGIC;
signal mul_temp_6_n_74 : STD_LOGIC;
signal mul_temp_6_n_75 : STD_LOGIC;
signal mul_temp_6_n_76 : STD_LOGIC;
signal mul_temp_6_n_77 : STD_LOGIC;
signal mul_temp_6_n_78 : STD_LOGIC;
signal mul_temp_6_n_79 : STD_LOGIC;
signal mul_temp_6_n_80 : STD_LOGIC;
signal mul_temp_6_n_81 : STD_LOGIC;
signal mul_temp_6_n_82 : STD_LOGIC;
signal mul_temp_6_n_83 : STD_LOGIC;
signal mul_temp_6_n_84 : STD_LOGIC;
signal mul_temp_6_n_85 : STD_LOGIC;
signal mul_temp_6_n_86 : STD_LOGIC;
signal mul_temp_6_n_87 : STD_LOGIC;
signal mul_temp_6_n_88 : STD_LOGIC;
signal mul_temp_6_n_89 : STD_LOGIC;
signal mul_temp_6_n_90 : STD_LOGIC;
signal mul_temp_6_n_92 : STD_LOGIC;
signal mul_temp_6_n_93 : STD_LOGIC;
signal mul_temp_6_n_94 : STD_LOGIC;
signal mul_temp_6_n_95 : STD_LOGIC;
signal mul_temp_6_n_96 : STD_LOGIC;
signal mul_temp_6_n_97 : STD_LOGIC;
signal mul_temp_6_n_98 : STD_LOGIC;
signal mul_temp_6_n_99 : STD_LOGIC;
signal \^mul_temp_7\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_7_n_100 : STD_LOGIC;
signal mul_temp_7_n_101 : STD_LOGIC;
signal mul_temp_7_n_102 : STD_LOGIC;
signal mul_temp_7_n_103 : STD_LOGIC;
signal mul_temp_7_n_104 : STD_LOGIC;
signal mul_temp_7_n_105 : STD_LOGIC;
signal mul_temp_7_n_74 : STD_LOGIC;
signal mul_temp_7_n_75 : STD_LOGIC;
signal mul_temp_7_n_76 : STD_LOGIC;
signal mul_temp_7_n_77 : STD_LOGIC;
signal mul_temp_7_n_78 : STD_LOGIC;
signal mul_temp_7_n_79 : STD_LOGIC;
signal mul_temp_7_n_80 : STD_LOGIC;
signal mul_temp_7_n_81 : STD_LOGIC;
signal mul_temp_7_n_82 : STD_LOGIC;
signal mul_temp_7_n_83 : STD_LOGIC;
signal mul_temp_7_n_84 : STD_LOGIC;
signal mul_temp_7_n_85 : STD_LOGIC;
signal mul_temp_7_n_86 : STD_LOGIC;
signal mul_temp_7_n_87 : STD_LOGIC;
signal mul_temp_7_n_88 : STD_LOGIC;
signal mul_temp_7_n_89 : STD_LOGIC;
signal mul_temp_7_n_90 : STD_LOGIC;
signal mul_temp_7_n_92 : STD_LOGIC;
signal mul_temp_7_n_93 : STD_LOGIC;
signal mul_temp_7_n_94 : STD_LOGIC;
signal mul_temp_7_n_95 : STD_LOGIC;
signal mul_temp_7_n_96 : STD_LOGIC;
signal mul_temp_7_n_97 : STD_LOGIC;
signal mul_temp_7_n_98 : STD_LOGIC;
signal mul_temp_7_n_99 : STD_LOGIC;
signal \^mul_temp_8\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_8_n_100 : STD_LOGIC;
signal mul_temp_8_n_101 : STD_LOGIC;
signal mul_temp_8_n_102 : STD_LOGIC;
signal mul_temp_8_n_103 : STD_LOGIC;
signal mul_temp_8_n_104 : STD_LOGIC;
signal mul_temp_8_n_105 : STD_LOGIC;
signal mul_temp_8_n_74 : STD_LOGIC;
signal mul_temp_8_n_75 : STD_LOGIC;
signal mul_temp_8_n_76 : STD_LOGIC;
signal mul_temp_8_n_77 : STD_LOGIC;
signal mul_temp_8_n_78 : STD_LOGIC;
signal mul_temp_8_n_79 : STD_LOGIC;
signal mul_temp_8_n_80 : STD_LOGIC;
signal mul_temp_8_n_81 : STD_LOGIC;
signal mul_temp_8_n_82 : STD_LOGIC;
signal mul_temp_8_n_83 : STD_LOGIC;
signal mul_temp_8_n_84 : STD_LOGIC;
signal mul_temp_8_n_85 : STD_LOGIC;
signal mul_temp_8_n_86 : STD_LOGIC;
signal mul_temp_8_n_87 : STD_LOGIC;
signal mul_temp_8_n_88 : STD_LOGIC;
signal mul_temp_8_n_89 : STD_LOGIC;
signal mul_temp_8_n_90 : STD_LOGIC;
signal mul_temp_8_n_92 : STD_LOGIC;
signal mul_temp_8_n_93 : STD_LOGIC;
signal mul_temp_8_n_94 : STD_LOGIC;
signal mul_temp_8_n_95 : STD_LOGIC;
signal mul_temp_8_n_96 : STD_LOGIC;
signal mul_temp_8_n_97 : STD_LOGIC;
signal mul_temp_8_n_98 : STD_LOGIC;
signal mul_temp_8_n_99 : STD_LOGIC;
signal \^mul_temp_9\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_9_n_100 : STD_LOGIC;
signal mul_temp_9_n_101 : STD_LOGIC;
signal mul_temp_9_n_102 : STD_LOGIC;
signal mul_temp_9_n_103 : STD_LOGIC;
signal mul_temp_9_n_104 : STD_LOGIC;
signal mul_temp_9_n_105 : STD_LOGIC;
signal mul_temp_9_n_74 : STD_LOGIC;
signal mul_temp_9_n_75 : STD_LOGIC;
signal mul_temp_9_n_76 : STD_LOGIC;
signal mul_temp_9_n_77 : STD_LOGIC;
signal mul_temp_9_n_78 : STD_LOGIC;
signal mul_temp_9_n_79 : STD_LOGIC;
signal mul_temp_9_n_80 : STD_LOGIC;
signal mul_temp_9_n_81 : STD_LOGIC;
signal mul_temp_9_n_82 : STD_LOGIC;
signal mul_temp_9_n_83 : STD_LOGIC;
signal mul_temp_9_n_84 : STD_LOGIC;
signal mul_temp_9_n_85 : STD_LOGIC;
signal mul_temp_9_n_86 : STD_LOGIC;
signal mul_temp_9_n_87 : STD_LOGIC;
signal mul_temp_9_n_88 : STD_LOGIC;
signal mul_temp_9_n_89 : STD_LOGIC;
signal mul_temp_9_n_90 : STD_LOGIC;
signal mul_temp_9_n_92 : STD_LOGIC;
signal mul_temp_9_n_93 : STD_LOGIC;
signal mul_temp_9_n_94 : STD_LOGIC;
signal mul_temp_9_n_95 : STD_LOGIC;
signal mul_temp_9_n_96 : STD_LOGIC;
signal mul_temp_9_n_97 : STD_LOGIC;
signal mul_temp_9_n_98 : STD_LOGIC;
signal mul_temp_9_n_99 : STD_LOGIC;
signal mul_temp_n_100 : STD_LOGIC;
signal mul_temp_n_101 : STD_LOGIC;
signal mul_temp_n_102 : STD_LOGIC;
signal mul_temp_n_103 : STD_LOGIC;
signal mul_temp_n_104 : STD_LOGIC;
signal mul_temp_n_105 : STD_LOGIC;
signal mul_temp_n_74 : STD_LOGIC;
signal mul_temp_n_75 : STD_LOGIC;
signal mul_temp_n_76 : STD_LOGIC;
signal mul_temp_n_77 : STD_LOGIC;
signal mul_temp_n_78 : STD_LOGIC;
signal mul_temp_n_79 : STD_LOGIC;
signal mul_temp_n_80 : STD_LOGIC;
signal mul_temp_n_81 : STD_LOGIC;
signal mul_temp_n_82 : STD_LOGIC;
signal mul_temp_n_83 : STD_LOGIC;
signal mul_temp_n_84 : STD_LOGIC;
signal mul_temp_n_85 : STD_LOGIC;
signal mul_temp_n_86 : STD_LOGIC;
signal mul_temp_n_87 : STD_LOGIC;
signal mul_temp_n_88 : STD_LOGIC;
signal mul_temp_n_89 : STD_LOGIC;
signal mul_temp_n_90 : STD_LOGIC;
signal mul_temp_n_92 : STD_LOGIC;
signal mul_temp_n_93 : STD_LOGIC;
signal mul_temp_n_94 : STD_LOGIC;
signal mul_temp_n_95 : STD_LOGIC;
signal mul_temp_n_96 : STD_LOGIC;
signal mul_temp_n_97 : STD_LOGIC;
signal mul_temp_n_98 : STD_LOGIC;
signal mul_temp_n_99 : STD_LOGIC;
signal \sub_temp_carry__0_n_0\ : STD_LOGIC;
signal \sub_temp_carry__0_n_1\ : STD_LOGIC;
signal \sub_temp_carry__0_n_2\ : STD_LOGIC;
signal \sub_temp_carry__0_n_3\ : STD_LOGIC;
signal \sub_temp_carry__1_n_0\ : STD_LOGIC;
signal \sub_temp_carry__1_n_1\ : STD_LOGIC;
signal \sub_temp_carry__1_n_2\ : STD_LOGIC;
signal \sub_temp_carry__1_n_3\ : STD_LOGIC;
signal \sub_temp_carry__2_n_1\ : STD_LOGIC;
signal \sub_temp_carry__2_n_2\ : STD_LOGIC;
signal \sub_temp_carry__2_n_3\ : STD_LOGIC;
signal sub_temp_carry_n_0 : STD_LOGIC;
signal sub_temp_carry_n_1 : STD_LOGIC;
signal sub_temp_carry_n_2 : STD_LOGIC;
signal sub_temp_carry_n_3 : STD_LOGIC;
signal \weight[0][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_5_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0]_15\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[10][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10]_9\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[11][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11]_10\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[12][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12]_11\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[13][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13]_12\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[14][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14]_13\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[15][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15]_14\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[1][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[2][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[3][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[4][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[5][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[6][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6]_5\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[7][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7]_6\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[8][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8]_7\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[9][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9]_8\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_ARG_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_ARG_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_ARG_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_ARG_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 30 );
signal NLW_ARG_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__1_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__1_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__10_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__10_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__10_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__10_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__11_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__11_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__11_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__11_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__12_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__12_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__12_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__12_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__13_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__13_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__13_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__13_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__14_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__14_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__14_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__14_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__15_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__15_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__15_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__15_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__16_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__16_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__16_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__16_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__17_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__17_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__17_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__17_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__18_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__18_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__18_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__18_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__19_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__19_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__19_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__19_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__2_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__20_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__20_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__20_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__20_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__21_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__21_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__21_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__21_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__22_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__22_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__22_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__22_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__23_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__23_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__23_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__23_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__24_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__24_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__24_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__24_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__25_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__25_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__25_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__25_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__26_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__26_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__26_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__26_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__27_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__27_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__27_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__27_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__28_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__28_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__28_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__28_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__29_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__29_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__29_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__29_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__3_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__3_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__3_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__3_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__30_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__30_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__30_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__30_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__4_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__4_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__4_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__4_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__5_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__5_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__5_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__5_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__6_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__6_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__6_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__6_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__7_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__7_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__7_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__7_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__8_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__8_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__8_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__8_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__9_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__9_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__9_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__9_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_ARG_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_ARG_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_mul_temp_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_1_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_1_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_10_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_10_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_10_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_10_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_11_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_11_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_11_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_11_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_12_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_12_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_12_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_12_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_13_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_13_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_13_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_13_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_14_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_14_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_14_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_14_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_15_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_15_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_15_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_15_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_17_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_17_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_17_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_17_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_18_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_18_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_18_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_18_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_19_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_19_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_19_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_19_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_2_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_2_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_20_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_20_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_20_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_20_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_21_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_21_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_21_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_21_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_22_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_22_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_22_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_22_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_23_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_23_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_23_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_23_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_24_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_24_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_24_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_24_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_25_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_25_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_25_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_25_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_26_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_26_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_26_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_26_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_27_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_27_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_27_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_27_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_28_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_28_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_28_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_28_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_29_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_29_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_29_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_29_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_3_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_3_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_30_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_30_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_30_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_30_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_31_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_31_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_31_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_31_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_32_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_32_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_32_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_32_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_4_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_4_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_4_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_4_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_5_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_5_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_5_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_5_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_6_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_6_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_6_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_6_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_7_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_7_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_7_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_7_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_8_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_8_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_8_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_8_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_9_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_9_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_9_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_9_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_sub_temp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of ARG : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__10\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__11\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__12\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__13\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__14\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__15\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__16\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__17\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__18\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__19\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__20\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__21\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__22\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__23\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__24\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__25\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__26\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__27\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__28\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__29\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__3\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__30\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__4\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__5\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__6\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__7\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__8\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__9\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute HLUTNM : string;
attribute HLUTNM of \add_temp_14__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry__0_i_5\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__1_i_1\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_2\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_3\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__1_i_4\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__1_i_5\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__1_i_6\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_7\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_8\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__2_i_1\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_2\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry__2_i_3\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__2_i_6\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_7\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__138_carry__0_i_1\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_2\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_3\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__0_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry__0_i_5\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__0_i_6\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_7\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_8\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__1_i_1\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_2\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_3\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__1_i_4\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__1_i_5\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__1_i_6\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_7\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_8\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__2_i_1\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_2\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry__2_i_3\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__2_i_6\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_7\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry_i_1\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_2\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_3\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__138_carry_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry_i_5\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_6\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_7\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__184_carry__0_i_1\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_2\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_3\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__0_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry__0_i_5\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__0_i_6\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_7\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_8\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__1_i_1\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_2\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_3\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__1_i_4\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__1_i_5\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__1_i_6\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_7\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_8\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__2_i_1\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_2\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry__2_i_3\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__2_i_6\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_7\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry_i_1\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_2\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_3\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__184_carry_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry_i_5\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_6\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_7\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__230_carry__0_i_1\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_2\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_3\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__0_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry__0_i_5\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__0_i_6\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_7\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_8\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__1_i_1\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_2\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_3\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__1_i_4\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__1_i_5\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__1_i_6\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_7\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_8\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__2_i_1\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_2\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry__2_i_3\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__2_i_6\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_7\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry_i_1\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_2\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_3\ : label is "lutpair70";
attribute HLUTNM of \add_temp_14__230_carry_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry_i_5\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_6\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_7\ : label is "lutpair70";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_11\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_8\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_9\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_10\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_9\ : label is "soft_lutpair6";
attribute HLUTNM of \add_temp_14__46_carry__0_i_1\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_2\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_3\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__0_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry__0_i_5\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__0_i_6\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_7\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_8\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__1_i_1\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_2\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_3\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__1_i_4\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__1_i_5\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__1_i_6\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_7\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_8\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__2_i_1\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_2\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry__2_i_3\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__2_i_6\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_7\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry_i_1\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_2\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_3\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__46_carry_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry_i_5\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_6\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_7\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__92_carry__0_i_1\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_2\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_3\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__0_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry__0_i_5\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__0_i_6\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_7\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_8\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__1_i_1\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_2\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_3\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__1_i_4\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__1_i_5\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__1_i_6\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_7\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_8\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__2_i_1\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_2\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry__2_i_3\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__2_i_6\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_7\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry_i_1\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_2\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_3\ : label is "lutpair28";
attribute HLUTNM of \add_temp_14__92_carry_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry_i_5\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_6\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_7\ : label is "lutpair28";
attribute METHODOLOGY_DRC_VIOS of mul_temp : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_10 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_11 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_12 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_13 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_14 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_15 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_17 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_18 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_19 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_2 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_20 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_21 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_22 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_23 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_24 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_25 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_26 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_27 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_28 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_29 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_30 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_31 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_32 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_4 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_5 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_6 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_7 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_8 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_9 : label is "{SYNTH-13 {cell *THIS*}}";
begin
mul_temp_16(15 downto 0) <= \^mul_temp_16\(15 downto 0);
ARG: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_ARG_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_ARG_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_18\(14),
C(12) => ARG_i_1_n_0,
C(11) => ARG_i_1_n_0,
C(10) => ARG_i_1_n_0,
C(9) => ARG_i_1_n_0,
C(8) => ARG_i_1_n_0,
C(7) => ARG_i_1_n_0,
C(6) => ARG_i_1_n_0,
C(5) => ARG_i_1_n_0,
C(4) => ARG_i_1_n_0,
C(3) => ARG_i_1_n_0,
C(2) => ARG_i_1_n_0,
C(1) => ARG_i_1_n_0,
C(0) => ARG_i_1_n_0,
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_ARG_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_ARG_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_ARG_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => NLW_ARG_OVERFLOW_UNCONNECTED,
P(47 downto 30) => NLW_ARG_P_UNCONNECTED(47 downto 30),
P(29 downto 14) => \in\(15 downto 0),
P(13) => ARG_n_92,
P(12) => ARG_n_93,
P(11) => ARG_n_94,
P(10) => ARG_n_95,
P(9) => ARG_n_96,
P(8) => ARG_n_97,
P(7) => ARG_n_98,
P(6) => ARG_n_99,
P(5) => ARG_n_100,
P(4) => ARG_n_101,
P(3) => ARG_n_102,
P(2) => ARG_n_103,
P(1) => ARG_n_104,
P(0) => ARG_n_105,
PATTERNBDETECT => NLW_ARG_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_ARG_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_ARG_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_ARG_UNDERFLOW_UNCONNECTED
);
\ARG__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_1\(14),
C(12) => \ARG__0_i_1_n_0\,
C(11) => \ARG__0_i_1_n_0\,
C(10) => \ARG__0_i_1_n_0\,
C(9) => \ARG__0_i_1_n_0\,
C(8) => \ARG__0_i_1_n_0\,
C(7) => \ARG__0_i_1_n_0\,
C(6) => \ARG__0_i_1_n_0\,
C(5) => \ARG__0_i_1_n_0\,
C(4) => \ARG__0_i_1_n_0\,
C(3) => \ARG__0_i_1_n_0\,
C(2) => \ARG__0_i_1_n_0\,
C(1) => \ARG__0_i_1_n_0\,
C(0) => \ARG__0_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__0_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__0_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE16(15 downto 0),
P(13) => \ARG__0_n_92\,
P(12) => \ARG__0_n_93\,
P(11) => \ARG__0_n_94\,
P(10) => \ARG__0_n_95\,
P(9) => \ARG__0_n_96\,
P(8) => \ARG__0_n_97\,
P(7) => \ARG__0_n_98\,
P(6) => \ARG__0_n_99\,
P(5) => \ARG__0_n_100\,
P(4) => \ARG__0_n_101\,
P(3) => \ARG__0_n_102\,
P(2) => \ARG__0_n_103\,
P(1) => \ARG__0_n_104\,
P(0) => \ARG__0_n_105\,
PATTERNBDETECT => \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__0_UNDERFLOW_UNCONNECTED\
);
\ARG__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_1\(14),
O => \ARG__0_i_1_n_0\
);
\ARG__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_19\(14),
C(12) => \ARG__1_i_1_n_0\,
C(11) => \ARG__1_i_1_n_0\,
C(10) => \ARG__1_i_1_n_0\,
C(9) => \ARG__1_i_1_n_0\,
C(8) => \ARG__1_i_1_n_0\,
C(7) => \ARG__1_i_1_n_0\,
C(6) => \ARG__1_i_1_n_0\,
C(5) => \ARG__1_i_1_n_0\,
C(4) => \ARG__1_i_1_n_0\,
C(3) => \ARG__1_i_1_n_0\,
C(2) => \ARG__1_i_1_n_0\,
C(1) => \ARG__1_i_1_n_0\,
C(0) => \ARG__1_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__1_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__1_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__1_n_76\,
P(28) => \ARG__1_n_77\,
P(27) => \ARG__1_n_78\,
P(26) => \ARG__1_n_79\,
P(25) => \ARG__1_n_80\,
P(24) => \ARG__1_n_81\,
P(23) => \ARG__1_n_82\,
P(22) => \ARG__1_n_83\,
P(21) => \ARG__1_n_84\,
P(20) => \ARG__1_n_85\,
P(19) => \ARG__1_n_86\,
P(18) => \ARG__1_n_87\,
P(17) => \ARG__1_n_88\,
P(16) => \ARG__1_n_89\,
P(15) => \ARG__1_n_90\,
P(14) => \ARG__1_n_91\,
P(13) => \ARG__1_n_92\,
P(12) => \ARG__1_n_93\,
P(11) => \ARG__1_n_94\,
P(10) => \ARG__1_n_95\,
P(9) => \ARG__1_n_96\,
P(8) => \ARG__1_n_97\,
P(7) => \ARG__1_n_98\,
P(6) => \ARG__1_n_99\,
P(5) => \ARG__1_n_100\,
P(4) => \ARG__1_n_101\,
P(3) => \ARG__1_n_102\,
P(2) => \ARG__1_n_103\,
P(1) => \ARG__1_n_104\,
P(0) => \ARG__1_n_105\,
PATTERNBDETECT => \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__1_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__1_UNDERFLOW_UNCONNECTED\
);
\ARG__10\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__10_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__10_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_6\(14),
C(12) => \ARG__10_i_1_n_0\,
C(11) => \ARG__10_i_1_n_0\,
C(10) => \ARG__10_i_1_n_0\,
C(9) => \ARG__10_i_1_n_0\,
C(8) => \ARG__10_i_1_n_0\,
C(7) => \ARG__10_i_1_n_0\,
C(6) => \ARG__10_i_1_n_0\,
C(5) => \ARG__10_i_1_n_0\,
C(4) => \ARG__10_i_1_n_0\,
C(3) => \ARG__10_i_1_n_0\,
C(2) => \ARG__10_i_1_n_0\,
C(1) => \ARG__10_i_1_n_0\,
C(0) => \ARG__10_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__10_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__10_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__10_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE26(15 downto 0),
P(13) => \ARG__10_n_92\,
P(12) => \ARG__10_n_93\,
P(11) => \ARG__10_n_94\,
P(10) => \ARG__10_n_95\,
P(9) => \ARG__10_n_96\,
P(8) => \ARG__10_n_97\,
P(7) => \ARG__10_n_98\,
P(6) => \ARG__10_n_99\,
P(5) => \ARG__10_n_100\,
P(4) => \ARG__10_n_101\,
P(3) => \ARG__10_n_102\,
P(2) => \ARG__10_n_103\,
P(1) => \ARG__10_n_104\,
P(0) => \ARG__10_n_105\,
PATTERNBDETECT => \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__10_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__10_UNDERFLOW_UNCONNECTED\
);
\ARG__10_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_6\(14),
O => \ARG__10_i_1_n_0\
);
\ARG__11\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__11_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__11_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_24\(14),
C(12) => \ARG__11_i_1_n_0\,
C(11) => \ARG__11_i_1_n_0\,
C(10) => \ARG__11_i_1_n_0\,
C(9) => \ARG__11_i_1_n_0\,
C(8) => \ARG__11_i_1_n_0\,
C(7) => \ARG__11_i_1_n_0\,
C(6) => \ARG__11_i_1_n_0\,
C(5) => \ARG__11_i_1_n_0\,
C(4) => \ARG__11_i_1_n_0\,
C(3) => \ARG__11_i_1_n_0\,
C(2) => \ARG__11_i_1_n_0\,
C(1) => \ARG__11_i_1_n_0\,
C(0) => \ARG__11_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__11_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__11_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__11_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__11_n_76\,
P(28) => \ARG__11_n_77\,
P(27) => \ARG__11_n_78\,
P(26) => \ARG__11_n_79\,
P(25) => \ARG__11_n_80\,
P(24) => \ARG__11_n_81\,
P(23) => \ARG__11_n_82\,
P(22) => \ARG__11_n_83\,
P(21) => \ARG__11_n_84\,
P(20) => \ARG__11_n_85\,
P(19) => \ARG__11_n_86\,
P(18) => \ARG__11_n_87\,
P(17) => \ARG__11_n_88\,
P(16) => \ARG__11_n_89\,
P(15) => \ARG__11_n_90\,
P(14) => \ARG__11_n_91\,
P(13) => \ARG__11_n_92\,
P(12) => \ARG__11_n_93\,
P(11) => \ARG__11_n_94\,
P(10) => \ARG__11_n_95\,
P(9) => \ARG__11_n_96\,
P(8) => \ARG__11_n_97\,
P(7) => \ARG__11_n_98\,
P(6) => \ARG__11_n_99\,
P(5) => \ARG__11_n_100\,
P(4) => \ARG__11_n_101\,
P(3) => \ARG__11_n_102\,
P(2) => \ARG__11_n_103\,
P(1) => \ARG__11_n_104\,
P(0) => \ARG__11_n_105\,
PATTERNBDETECT => \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__11_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__11_UNDERFLOW_UNCONNECTED\
);
\ARG__11_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_24\(14),
O => \ARG__11_i_1_n_0\
);
\ARG__12\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__12_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__12_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_7\(14),
C(12) => \ARG__12_i_1_n_0\,
C(11) => \ARG__12_i_1_n_0\,
C(10) => \ARG__12_i_1_n_0\,
C(9) => \ARG__12_i_1_n_0\,
C(8) => \ARG__12_i_1_n_0\,
C(7) => \ARG__12_i_1_n_0\,
C(6) => \ARG__12_i_1_n_0\,
C(5) => \ARG__12_i_1_n_0\,
C(4) => \ARG__12_i_1_n_0\,
C(3) => \ARG__12_i_1_n_0\,
C(2) => \ARG__12_i_1_n_0\,
C(1) => \ARG__12_i_1_n_0\,
C(0) => \ARG__12_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__12_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__12_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__12_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE28(15 downto 0),
P(13) => \ARG__12_n_92\,
P(12) => \ARG__12_n_93\,
P(11) => \ARG__12_n_94\,
P(10) => \ARG__12_n_95\,
P(9) => \ARG__12_n_96\,
P(8) => \ARG__12_n_97\,
P(7) => \ARG__12_n_98\,
P(6) => \ARG__12_n_99\,
P(5) => \ARG__12_n_100\,
P(4) => \ARG__12_n_101\,
P(3) => \ARG__12_n_102\,
P(2) => \ARG__12_n_103\,
P(1) => \ARG__12_n_104\,
P(0) => \ARG__12_n_105\,
PATTERNBDETECT => \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__12_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__12_UNDERFLOW_UNCONNECTED\
);
\ARG__12_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_7\(14),
O => \ARG__12_i_1_n_0\
);
\ARG__13\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__13_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__13_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_25\(14),
C(12) => \ARG__13_i_1_n_0\,
C(11) => \ARG__13_i_1_n_0\,
C(10) => \ARG__13_i_1_n_0\,
C(9) => \ARG__13_i_1_n_0\,
C(8) => \ARG__13_i_1_n_0\,
C(7) => \ARG__13_i_1_n_0\,
C(6) => \ARG__13_i_1_n_0\,
C(5) => \ARG__13_i_1_n_0\,
C(4) => \ARG__13_i_1_n_0\,
C(3) => \ARG__13_i_1_n_0\,
C(2) => \ARG__13_i_1_n_0\,
C(1) => \ARG__13_i_1_n_0\,
C(0) => \ARG__13_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__13_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__13_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__13_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__13_n_76\,
P(28) => \ARG__13_n_77\,
P(27) => \ARG__13_n_78\,
P(26) => \ARG__13_n_79\,
P(25) => \ARG__13_n_80\,
P(24) => \ARG__13_n_81\,
P(23) => \ARG__13_n_82\,
P(22) => \ARG__13_n_83\,
P(21) => \ARG__13_n_84\,
P(20) => \ARG__13_n_85\,
P(19) => \ARG__13_n_86\,
P(18) => \ARG__13_n_87\,
P(17) => \ARG__13_n_88\,
P(16) => \ARG__13_n_89\,
P(15) => \ARG__13_n_90\,
P(14) => \ARG__13_n_91\,
P(13) => \ARG__13_n_92\,
P(12) => \ARG__13_n_93\,
P(11) => \ARG__13_n_94\,
P(10) => \ARG__13_n_95\,
P(9) => \ARG__13_n_96\,
P(8) => \ARG__13_n_97\,
P(7) => \ARG__13_n_98\,
P(6) => \ARG__13_n_99\,
P(5) => \ARG__13_n_100\,
P(4) => \ARG__13_n_101\,
P(3) => \ARG__13_n_102\,
P(2) => \ARG__13_n_103\,
P(1) => \ARG__13_n_104\,
P(0) => \ARG__13_n_105\,
PATTERNBDETECT => \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__13_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__13_UNDERFLOW_UNCONNECTED\
);
\ARG__13_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_25\(14),
O => \ARG__13_i_1_n_0\
);
\ARG__14\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__14_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__14_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_8\(14),
C(12) => \ARG__14_i_1_n_0\,
C(11) => \ARG__14_i_1_n_0\,
C(10) => \ARG__14_i_1_n_0\,
C(9) => \ARG__14_i_1_n_0\,
C(8) => \ARG__14_i_1_n_0\,
C(7) => \ARG__14_i_1_n_0\,
C(6) => \ARG__14_i_1_n_0\,
C(5) => \ARG__14_i_1_n_0\,
C(4) => \ARG__14_i_1_n_0\,
C(3) => \ARG__14_i_1_n_0\,
C(2) => \ARG__14_i_1_n_0\,
C(1) => \ARG__14_i_1_n_0\,
C(0) => \ARG__14_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__14_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__14_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__14_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE30(15 downto 0),
P(13) => \ARG__14_n_92\,
P(12) => \ARG__14_n_93\,
P(11) => \ARG__14_n_94\,
P(10) => \ARG__14_n_95\,
P(9) => \ARG__14_n_96\,
P(8) => \ARG__14_n_97\,
P(7) => \ARG__14_n_98\,
P(6) => \ARG__14_n_99\,
P(5) => \ARG__14_n_100\,
P(4) => \ARG__14_n_101\,
P(3) => \ARG__14_n_102\,
P(2) => \ARG__14_n_103\,
P(1) => \ARG__14_n_104\,
P(0) => \ARG__14_n_105\,
PATTERNBDETECT => \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__14_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__14_UNDERFLOW_UNCONNECTED\
);
\ARG__14_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_8\(14),
O => \ARG__14_i_1_n_0\
);
\ARG__15\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__15_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__15_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_26\(14),
C(12) => \ARG__15_i_1_n_0\,
C(11) => \ARG__15_i_1_n_0\,
C(10) => \ARG__15_i_1_n_0\,
C(9) => \ARG__15_i_1_n_0\,
C(8) => \ARG__15_i_1_n_0\,
C(7) => \ARG__15_i_1_n_0\,
C(6) => \ARG__15_i_1_n_0\,
C(5) => \ARG__15_i_1_n_0\,
C(4) => \ARG__15_i_1_n_0\,
C(3) => \ARG__15_i_1_n_0\,
C(2) => \ARG__15_i_1_n_0\,
C(1) => \ARG__15_i_1_n_0\,
C(0) => \ARG__15_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__15_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__15_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__15_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__15_n_76\,
P(28) => \ARG__15_n_77\,
P(27) => \ARG__15_n_78\,
P(26) => \ARG__15_n_79\,
P(25) => \ARG__15_n_80\,
P(24) => \ARG__15_n_81\,
P(23) => \ARG__15_n_82\,
P(22) => \ARG__15_n_83\,
P(21) => \ARG__15_n_84\,
P(20) => \ARG__15_n_85\,
P(19) => \ARG__15_n_86\,
P(18) => \ARG__15_n_87\,
P(17) => \ARG__15_n_88\,
P(16) => \ARG__15_n_89\,
P(15) => \ARG__15_n_90\,
P(14) => \ARG__15_n_91\,
P(13) => \ARG__15_n_92\,
P(12) => \ARG__15_n_93\,
P(11) => \ARG__15_n_94\,
P(10) => \ARG__15_n_95\,
P(9) => \ARG__15_n_96\,
P(8) => \ARG__15_n_97\,
P(7) => \ARG__15_n_98\,
P(6) => \ARG__15_n_99\,
P(5) => \ARG__15_n_100\,
P(4) => \ARG__15_n_101\,
P(3) => \ARG__15_n_102\,
P(2) => \ARG__15_n_103\,
P(1) => \ARG__15_n_104\,
P(0) => \ARG__15_n_105\,
PATTERNBDETECT => \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__15_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__15_UNDERFLOW_UNCONNECTED\
);
\ARG__15_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_26\(14),
O => \ARG__15_i_1_n_0\
);
\ARG__16\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__16_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__16_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_9\(14),
C(12) => \ARG__16_i_1_n_0\,
C(11) => \ARG__16_i_1_n_0\,
C(10) => \ARG__16_i_1_n_0\,
C(9) => \ARG__16_i_1_n_0\,
C(8) => \ARG__16_i_1_n_0\,
C(7) => \ARG__16_i_1_n_0\,
C(6) => \ARG__16_i_1_n_0\,
C(5) => \ARG__16_i_1_n_0\,
C(4) => \ARG__16_i_1_n_0\,
C(3) => \ARG__16_i_1_n_0\,
C(2) => \ARG__16_i_1_n_0\,
C(1) => \ARG__16_i_1_n_0\,
C(0) => \ARG__16_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__16_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__16_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__16_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE32(15 downto 0),
P(13) => \ARG__16_n_92\,
P(12) => \ARG__16_n_93\,
P(11) => \ARG__16_n_94\,
P(10) => \ARG__16_n_95\,
P(9) => \ARG__16_n_96\,
P(8) => \ARG__16_n_97\,
P(7) => \ARG__16_n_98\,
P(6) => \ARG__16_n_99\,
P(5) => \ARG__16_n_100\,
P(4) => \ARG__16_n_101\,
P(3) => \ARG__16_n_102\,
P(2) => \ARG__16_n_103\,
P(1) => \ARG__16_n_104\,
P(0) => \ARG__16_n_105\,
PATTERNBDETECT => \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__16_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__16_UNDERFLOW_UNCONNECTED\
);
\ARG__16_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_9\(14),
O => \ARG__16_i_1_n_0\
);
\ARG__17\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__17_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__17_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_27\(14),
C(12) => \ARG__17_i_1_n_0\,
C(11) => \ARG__17_i_1_n_0\,
C(10) => \ARG__17_i_1_n_0\,
C(9) => \ARG__17_i_1_n_0\,
C(8) => \ARG__17_i_1_n_0\,
C(7) => \ARG__17_i_1_n_0\,
C(6) => \ARG__17_i_1_n_0\,
C(5) => \ARG__17_i_1_n_0\,
C(4) => \ARG__17_i_1_n_0\,
C(3) => \ARG__17_i_1_n_0\,
C(2) => \ARG__17_i_1_n_0\,
C(1) => \ARG__17_i_1_n_0\,
C(0) => \ARG__17_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__17_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__17_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__17_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__17_n_76\,
P(28) => \ARG__17_n_77\,
P(27) => \ARG__17_n_78\,
P(26) => \ARG__17_n_79\,
P(25) => \ARG__17_n_80\,
P(24) => \ARG__17_n_81\,
P(23) => \ARG__17_n_82\,
P(22) => \ARG__17_n_83\,
P(21) => \ARG__17_n_84\,
P(20) => \ARG__17_n_85\,
P(19) => \ARG__17_n_86\,
P(18) => \ARG__17_n_87\,
P(17) => \ARG__17_n_88\,
P(16) => \ARG__17_n_89\,
P(15) => \ARG__17_n_90\,
P(14) => \ARG__17_n_91\,
P(13) => \ARG__17_n_92\,
P(12) => \ARG__17_n_93\,
P(11) => \ARG__17_n_94\,
P(10) => \ARG__17_n_95\,
P(9) => \ARG__17_n_96\,
P(8) => \ARG__17_n_97\,
P(7) => \ARG__17_n_98\,
P(6) => \ARG__17_n_99\,
P(5) => \ARG__17_n_100\,
P(4) => \ARG__17_n_101\,
P(3) => \ARG__17_n_102\,
P(2) => \ARG__17_n_103\,
P(1) => \ARG__17_n_104\,
P(0) => \ARG__17_n_105\,
PATTERNBDETECT => \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__17_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__17_UNDERFLOW_UNCONNECTED\
);
\ARG__17_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_27\(14),
O => \ARG__17_i_1_n_0\
);
\ARG__18\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__18_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__18_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_10\(14),
C(12) => \ARG__18_i_1_n_0\,
C(11) => \ARG__18_i_1_n_0\,
C(10) => \ARG__18_i_1_n_0\,
C(9) => \ARG__18_i_1_n_0\,
C(8) => \ARG__18_i_1_n_0\,
C(7) => \ARG__18_i_1_n_0\,
C(6) => \ARG__18_i_1_n_0\,
C(5) => \ARG__18_i_1_n_0\,
C(4) => \ARG__18_i_1_n_0\,
C(3) => \ARG__18_i_1_n_0\,
C(2) => \ARG__18_i_1_n_0\,
C(1) => \ARG__18_i_1_n_0\,
C(0) => \ARG__18_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__18_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__18_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__18_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE34(15 downto 0),
P(13) => \ARG__18_n_92\,
P(12) => \ARG__18_n_93\,
P(11) => \ARG__18_n_94\,
P(10) => \ARG__18_n_95\,
P(9) => \ARG__18_n_96\,
P(8) => \ARG__18_n_97\,
P(7) => \ARG__18_n_98\,
P(6) => \ARG__18_n_99\,
P(5) => \ARG__18_n_100\,
P(4) => \ARG__18_n_101\,
P(3) => \ARG__18_n_102\,
P(2) => \ARG__18_n_103\,
P(1) => \ARG__18_n_104\,
P(0) => \ARG__18_n_105\,
PATTERNBDETECT => \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__18_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__18_UNDERFLOW_UNCONNECTED\
);
\ARG__18_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_10\(14),
O => \ARG__18_i_1_n_0\
);
\ARG__19\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__19_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__19_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_28\(14),
C(12) => \ARG__19_i_1_n_0\,
C(11) => \ARG__19_i_1_n_0\,
C(10) => \ARG__19_i_1_n_0\,
C(9) => \ARG__19_i_1_n_0\,
C(8) => \ARG__19_i_1_n_0\,
C(7) => \ARG__19_i_1_n_0\,
C(6) => \ARG__19_i_1_n_0\,
C(5) => \ARG__19_i_1_n_0\,
C(4) => \ARG__19_i_1_n_0\,
C(3) => \ARG__19_i_1_n_0\,
C(2) => \ARG__19_i_1_n_0\,
C(1) => \ARG__19_i_1_n_0\,
C(0) => \ARG__19_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__19_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__19_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__19_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__19_n_76\,
P(28) => \ARG__19_n_77\,
P(27) => \ARG__19_n_78\,
P(26) => \ARG__19_n_79\,
P(25) => \ARG__19_n_80\,
P(24) => \ARG__19_n_81\,
P(23) => \ARG__19_n_82\,
P(22) => \ARG__19_n_83\,
P(21) => \ARG__19_n_84\,
P(20) => \ARG__19_n_85\,
P(19) => \ARG__19_n_86\,
P(18) => \ARG__19_n_87\,
P(17) => \ARG__19_n_88\,
P(16) => \ARG__19_n_89\,
P(15) => \ARG__19_n_90\,
P(14) => \ARG__19_n_91\,
P(13) => \ARG__19_n_92\,
P(12) => \ARG__19_n_93\,
P(11) => \ARG__19_n_94\,
P(10) => \ARG__19_n_95\,
P(9) => \ARG__19_n_96\,
P(8) => \ARG__19_n_97\,
P(7) => \ARG__19_n_98\,
P(6) => \ARG__19_n_99\,
P(5) => \ARG__19_n_100\,
P(4) => \ARG__19_n_101\,
P(3) => \ARG__19_n_102\,
P(2) => \ARG__19_n_103\,
P(1) => \ARG__19_n_104\,
P(0) => \ARG__19_n_105\,
PATTERNBDETECT => \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__19_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__19_UNDERFLOW_UNCONNECTED\
);
\ARG__19_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_28\(14),
O => \ARG__19_i_1_n_0\
);
\ARG__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_19\(14),
O => \ARG__1_i_1_n_0\
);
\ARG__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_2\(14),
C(12) => \ARG__2_i_1_n_0\,
C(11) => \ARG__2_i_1_n_0\,
C(10) => \ARG__2_i_1_n_0\,
C(9) => \ARG__2_i_1_n_0\,
C(8) => \ARG__2_i_1_n_0\,
C(7) => \ARG__2_i_1_n_0\,
C(6) => \ARG__2_i_1_n_0\,
C(5) => \ARG__2_i_1_n_0\,
C(4) => \ARG__2_i_1_n_0\,
C(3) => \ARG__2_i_1_n_0\,
C(2) => \ARG__2_i_1_n_0\,
C(1) => \ARG__2_i_1_n_0\,
C(0) => \ARG__2_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__2_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__2_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE18(15 downto 0),
P(13) => \ARG__2_n_92\,
P(12) => \ARG__2_n_93\,
P(11) => \ARG__2_n_94\,
P(10) => \ARG__2_n_95\,
P(9) => \ARG__2_n_96\,
P(8) => \ARG__2_n_97\,
P(7) => \ARG__2_n_98\,
P(6) => \ARG__2_n_99\,
P(5) => \ARG__2_n_100\,
P(4) => \ARG__2_n_101\,
P(3) => \ARG__2_n_102\,
P(2) => \ARG__2_n_103\,
P(1) => \ARG__2_n_104\,
P(0) => \ARG__2_n_105\,
PATTERNBDETECT => \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__2_UNDERFLOW_UNCONNECTED\
);
\ARG__20\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__20_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__20_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_11\(14),
C(12) => \ARG__20_i_1_n_0\,
C(11) => \ARG__20_i_1_n_0\,
C(10) => \ARG__20_i_1_n_0\,
C(9) => \ARG__20_i_1_n_0\,
C(8) => \ARG__20_i_1_n_0\,
C(7) => \ARG__20_i_1_n_0\,
C(6) => \ARG__20_i_1_n_0\,
C(5) => \ARG__20_i_1_n_0\,
C(4) => \ARG__20_i_1_n_0\,
C(3) => \ARG__20_i_1_n_0\,
C(2) => \ARG__20_i_1_n_0\,
C(1) => \ARG__20_i_1_n_0\,
C(0) => \ARG__20_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__20_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__20_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__20_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE36(15 downto 0),
P(13) => \ARG__20_n_92\,
P(12) => \ARG__20_n_93\,
P(11) => \ARG__20_n_94\,
P(10) => \ARG__20_n_95\,
P(9) => \ARG__20_n_96\,
P(8) => \ARG__20_n_97\,
P(7) => \ARG__20_n_98\,
P(6) => \ARG__20_n_99\,
P(5) => \ARG__20_n_100\,
P(4) => \ARG__20_n_101\,
P(3) => \ARG__20_n_102\,
P(2) => \ARG__20_n_103\,
P(1) => \ARG__20_n_104\,
P(0) => \ARG__20_n_105\,
PATTERNBDETECT => \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__20_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__20_UNDERFLOW_UNCONNECTED\
);
\ARG__20_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_11\(14),
O => \ARG__20_i_1_n_0\
);
\ARG__21\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__21_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__21_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_29\(14),
C(12) => \ARG__21_i_1_n_0\,
C(11) => \ARG__21_i_1_n_0\,
C(10) => \ARG__21_i_1_n_0\,
C(9) => \ARG__21_i_1_n_0\,
C(8) => \ARG__21_i_1_n_0\,
C(7) => \ARG__21_i_1_n_0\,
C(6) => \ARG__21_i_1_n_0\,
C(5) => \ARG__21_i_1_n_0\,
C(4) => \ARG__21_i_1_n_0\,
C(3) => \ARG__21_i_1_n_0\,
C(2) => \ARG__21_i_1_n_0\,
C(1) => \ARG__21_i_1_n_0\,
C(0) => \ARG__21_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__21_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__21_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__21_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__21_n_76\,
P(28) => \ARG__21_n_77\,
P(27) => \ARG__21_n_78\,
P(26) => \ARG__21_n_79\,
P(25) => \ARG__21_n_80\,
P(24) => \ARG__21_n_81\,
P(23) => \ARG__21_n_82\,
P(22) => \ARG__21_n_83\,
P(21) => \ARG__21_n_84\,
P(20) => \ARG__21_n_85\,
P(19) => \ARG__21_n_86\,
P(18) => \ARG__21_n_87\,
P(17) => \ARG__21_n_88\,
P(16) => \ARG__21_n_89\,
P(15) => \ARG__21_n_90\,
P(14) => \ARG__21_n_91\,
P(13) => \ARG__21_n_92\,
P(12) => \ARG__21_n_93\,
P(11) => \ARG__21_n_94\,
P(10) => \ARG__21_n_95\,
P(9) => \ARG__21_n_96\,
P(8) => \ARG__21_n_97\,
P(7) => \ARG__21_n_98\,
P(6) => \ARG__21_n_99\,
P(5) => \ARG__21_n_100\,
P(4) => \ARG__21_n_101\,
P(3) => \ARG__21_n_102\,
P(2) => \ARG__21_n_103\,
P(1) => \ARG__21_n_104\,
P(0) => \ARG__21_n_105\,
PATTERNBDETECT => \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__21_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__21_UNDERFLOW_UNCONNECTED\
);
\ARG__21_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_29\(14),
O => \ARG__21_i_1_n_0\
);
\ARG__22\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__22_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__22_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_12\(14),
C(12) => \ARG__22_i_1_n_0\,
C(11) => \ARG__22_i_1_n_0\,
C(10) => \ARG__22_i_1_n_0\,
C(9) => \ARG__22_i_1_n_0\,
C(8) => \ARG__22_i_1_n_0\,
C(7) => \ARG__22_i_1_n_0\,
C(6) => \ARG__22_i_1_n_0\,
C(5) => \ARG__22_i_1_n_0\,
C(4) => \ARG__22_i_1_n_0\,
C(3) => \ARG__22_i_1_n_0\,
C(2) => \ARG__22_i_1_n_0\,
C(1) => \ARG__22_i_1_n_0\,
C(0) => \ARG__22_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__22_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__22_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__22_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE38(15 downto 0),
P(13) => \ARG__22_n_92\,
P(12) => \ARG__22_n_93\,
P(11) => \ARG__22_n_94\,
P(10) => \ARG__22_n_95\,
P(9) => \ARG__22_n_96\,
P(8) => \ARG__22_n_97\,
P(7) => \ARG__22_n_98\,
P(6) => \ARG__22_n_99\,
P(5) => \ARG__22_n_100\,
P(4) => \ARG__22_n_101\,
P(3) => \ARG__22_n_102\,
P(2) => \ARG__22_n_103\,
P(1) => \ARG__22_n_104\,
P(0) => \ARG__22_n_105\,
PATTERNBDETECT => \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__22_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__22_UNDERFLOW_UNCONNECTED\
);
\ARG__22_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_12\(14),
O => \ARG__22_i_1_n_0\
);
\ARG__23\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__23_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__23_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_30\(14),
C(12) => \ARG__23_i_1_n_0\,
C(11) => \ARG__23_i_1_n_0\,
C(10) => \ARG__23_i_1_n_0\,
C(9) => \ARG__23_i_1_n_0\,
C(8) => \ARG__23_i_1_n_0\,
C(7) => \ARG__23_i_1_n_0\,
C(6) => \ARG__23_i_1_n_0\,
C(5) => \ARG__23_i_1_n_0\,
C(4) => \ARG__23_i_1_n_0\,
C(3) => \ARG__23_i_1_n_0\,
C(2) => \ARG__23_i_1_n_0\,
C(1) => \ARG__23_i_1_n_0\,
C(0) => \ARG__23_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__23_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__23_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__23_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__23_n_76\,
P(28) => \ARG__23_n_77\,
P(27) => \ARG__23_n_78\,
P(26) => \ARG__23_n_79\,
P(25) => \ARG__23_n_80\,
P(24) => \ARG__23_n_81\,
P(23) => \ARG__23_n_82\,
P(22) => \ARG__23_n_83\,
P(21) => \ARG__23_n_84\,
P(20) => \ARG__23_n_85\,
P(19) => \ARG__23_n_86\,
P(18) => \ARG__23_n_87\,
P(17) => \ARG__23_n_88\,
P(16) => \ARG__23_n_89\,
P(15) => \ARG__23_n_90\,
P(14) => \ARG__23_n_91\,
P(13) => \ARG__23_n_92\,
P(12) => \ARG__23_n_93\,
P(11) => \ARG__23_n_94\,
P(10) => \ARG__23_n_95\,
P(9) => \ARG__23_n_96\,
P(8) => \ARG__23_n_97\,
P(7) => \ARG__23_n_98\,
P(6) => \ARG__23_n_99\,
P(5) => \ARG__23_n_100\,
P(4) => \ARG__23_n_101\,
P(3) => \ARG__23_n_102\,
P(2) => \ARG__23_n_103\,
P(1) => \ARG__23_n_104\,
P(0) => \ARG__23_n_105\,
PATTERNBDETECT => \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__23_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__23_UNDERFLOW_UNCONNECTED\
);
\ARG__23_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_30\(14),
O => \ARG__23_i_1_n_0\
);
\ARG__24\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__24_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__24_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_13\(14),
C(12) => \ARG__24_i_1_n_0\,
C(11) => \ARG__24_i_1_n_0\,
C(10) => \ARG__24_i_1_n_0\,
C(9) => \ARG__24_i_1_n_0\,
C(8) => \ARG__24_i_1_n_0\,
C(7) => \ARG__24_i_1_n_0\,
C(6) => \ARG__24_i_1_n_0\,
C(5) => \ARG__24_i_1_n_0\,
C(4) => \ARG__24_i_1_n_0\,
C(3) => \ARG__24_i_1_n_0\,
C(2) => \ARG__24_i_1_n_0\,
C(1) => \ARG__24_i_1_n_0\,
C(0) => \ARG__24_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__24_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__24_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__24_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE40(15 downto 0),
P(13) => \ARG__24_n_92\,
P(12) => \ARG__24_n_93\,
P(11) => \ARG__24_n_94\,
P(10) => \ARG__24_n_95\,
P(9) => \ARG__24_n_96\,
P(8) => \ARG__24_n_97\,
P(7) => \ARG__24_n_98\,
P(6) => \ARG__24_n_99\,
P(5) => \ARG__24_n_100\,
P(4) => \ARG__24_n_101\,
P(3) => \ARG__24_n_102\,
P(2) => \ARG__24_n_103\,
P(1) => \ARG__24_n_104\,
P(0) => \ARG__24_n_105\,
PATTERNBDETECT => \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__24_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__24_UNDERFLOW_UNCONNECTED\
);
\ARG__24_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_13\(14),
O => \ARG__24_i_1_n_0\
);
\ARG__25\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__25_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__25_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_31\(14),
C(12) => \ARG__25_i_1_n_0\,
C(11) => \ARG__25_i_1_n_0\,
C(10) => \ARG__25_i_1_n_0\,
C(9) => \ARG__25_i_1_n_0\,
C(8) => \ARG__25_i_1_n_0\,
C(7) => \ARG__25_i_1_n_0\,
C(6) => \ARG__25_i_1_n_0\,
C(5) => \ARG__25_i_1_n_0\,
C(4) => \ARG__25_i_1_n_0\,
C(3) => \ARG__25_i_1_n_0\,
C(2) => \ARG__25_i_1_n_0\,
C(1) => \ARG__25_i_1_n_0\,
C(0) => \ARG__25_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__25_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__25_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__25_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__25_n_76\,
P(28) => \ARG__25_n_77\,
P(27) => \ARG__25_n_78\,
P(26) => \ARG__25_n_79\,
P(25) => \ARG__25_n_80\,
P(24) => \ARG__25_n_81\,
P(23) => \ARG__25_n_82\,
P(22) => \ARG__25_n_83\,
P(21) => \ARG__25_n_84\,
P(20) => \ARG__25_n_85\,
P(19) => \ARG__25_n_86\,
P(18) => \ARG__25_n_87\,
P(17) => \ARG__25_n_88\,
P(16) => \ARG__25_n_89\,
P(15) => \ARG__25_n_90\,
P(14) => \ARG__25_n_91\,
P(13) => \ARG__25_n_92\,
P(12) => \ARG__25_n_93\,
P(11) => \ARG__25_n_94\,
P(10) => \ARG__25_n_95\,
P(9) => \ARG__25_n_96\,
P(8) => \ARG__25_n_97\,
P(7) => \ARG__25_n_98\,
P(6) => \ARG__25_n_99\,
P(5) => \ARG__25_n_100\,
P(4) => \ARG__25_n_101\,
P(3) => \ARG__25_n_102\,
P(2) => \ARG__25_n_103\,
P(1) => \ARG__25_n_104\,
P(0) => \ARG__25_n_105\,
PATTERNBDETECT => \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__25_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__25_UNDERFLOW_UNCONNECTED\
);
\ARG__25_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_31\(14),
O => \ARG__25_i_1_n_0\
);
\ARG__26\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__26_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__26_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_14\(14),
C(12) => \ARG__26_i_1_n_0\,
C(11) => \ARG__26_i_1_n_0\,
C(10) => \ARG__26_i_1_n_0\,
C(9) => \ARG__26_i_1_n_0\,
C(8) => \ARG__26_i_1_n_0\,
C(7) => \ARG__26_i_1_n_0\,
C(6) => \ARG__26_i_1_n_0\,
C(5) => \ARG__26_i_1_n_0\,
C(4) => \ARG__26_i_1_n_0\,
C(3) => \ARG__26_i_1_n_0\,
C(2) => \ARG__26_i_1_n_0\,
C(1) => \ARG__26_i_1_n_0\,
C(0) => \ARG__26_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__26_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__26_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__26_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE42(15 downto 0),
P(13) => \ARG__26_n_92\,
P(12) => \ARG__26_n_93\,
P(11) => \ARG__26_n_94\,
P(10) => \ARG__26_n_95\,
P(9) => \ARG__26_n_96\,
P(8) => \ARG__26_n_97\,
P(7) => \ARG__26_n_98\,
P(6) => \ARG__26_n_99\,
P(5) => \ARG__26_n_100\,
P(4) => \ARG__26_n_101\,
P(3) => \ARG__26_n_102\,
P(2) => \ARG__26_n_103\,
P(1) => \ARG__26_n_104\,
P(0) => \ARG__26_n_105\,
PATTERNBDETECT => \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__26_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__26_UNDERFLOW_UNCONNECTED\
);
\ARG__26_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_14\(14),
O => \ARG__26_i_1_n_0\
);
\ARG__27\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__27_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__27_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_32\(14),
C(12) => \ARG__27_i_1_n_0\,
C(11) => \ARG__27_i_1_n_0\,
C(10) => \ARG__27_i_1_n_0\,
C(9) => \ARG__27_i_1_n_0\,
C(8) => \ARG__27_i_1_n_0\,
C(7) => \ARG__27_i_1_n_0\,
C(6) => \ARG__27_i_1_n_0\,
C(5) => \ARG__27_i_1_n_0\,
C(4) => \ARG__27_i_1_n_0\,
C(3) => \ARG__27_i_1_n_0\,
C(2) => \ARG__27_i_1_n_0\,
C(1) => \ARG__27_i_1_n_0\,
C(0) => \ARG__27_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__27_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__27_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__27_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__27_n_76\,
P(28) => \ARG__27_n_77\,
P(27) => \ARG__27_n_78\,
P(26) => \ARG__27_n_79\,
P(25) => \ARG__27_n_80\,
P(24) => \ARG__27_n_81\,
P(23) => \ARG__27_n_82\,
P(22) => \ARG__27_n_83\,
P(21) => \ARG__27_n_84\,
P(20) => \ARG__27_n_85\,
P(19) => \ARG__27_n_86\,
P(18) => \ARG__27_n_87\,
P(17) => \ARG__27_n_88\,
P(16) => \ARG__27_n_89\,
P(15) => \ARG__27_n_90\,
P(14) => \ARG__27_n_91\,
P(13) => \ARG__27_n_92\,
P(12) => \ARG__27_n_93\,
P(11) => \ARG__27_n_94\,
P(10) => \ARG__27_n_95\,
P(9) => \ARG__27_n_96\,
P(8) => \ARG__27_n_97\,
P(7) => \ARG__27_n_98\,
P(6) => \ARG__27_n_99\,
P(5) => \ARG__27_n_100\,
P(4) => \ARG__27_n_101\,
P(3) => \ARG__27_n_102\,
P(2) => \ARG__27_n_103\,
P(1) => \ARG__27_n_104\,
P(0) => \ARG__27_n_105\,
PATTERNBDETECT => \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__27_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__27_UNDERFLOW_UNCONNECTED\
);
\ARG__27_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_32\(14),
O => \ARG__27_i_1_n_0\
);
\ARG__28\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__28_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__28_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_15\(14),
C(12) => \ARG__28_i_1_n_0\,
C(11) => \ARG__28_i_1_n_0\,
C(10) => \ARG__28_i_1_n_0\,
C(9) => \ARG__28_i_1_n_0\,
C(8) => \ARG__28_i_1_n_0\,
C(7) => \ARG__28_i_1_n_0\,
C(6) => \ARG__28_i_1_n_0\,
C(5) => \ARG__28_i_1_n_0\,
C(4) => \ARG__28_i_1_n_0\,
C(3) => \ARG__28_i_1_n_0\,
C(2) => \ARG__28_i_1_n_0\,
C(1) => \ARG__28_i_1_n_0\,
C(0) => \ARG__28_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__28_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__28_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__28_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE44(15 downto 0),
P(13) => \ARG__28_n_92\,
P(12) => \ARG__28_n_93\,
P(11) => \ARG__28_n_94\,
P(10) => \ARG__28_n_95\,
P(9) => \ARG__28_n_96\,
P(8) => \ARG__28_n_97\,
P(7) => \ARG__28_n_98\,
P(6) => \ARG__28_n_99\,
P(5) => \ARG__28_n_100\,
P(4) => \ARG__28_n_101\,
P(3) => \ARG__28_n_102\,
P(2) => \ARG__28_n_103\,
P(1) => \ARG__28_n_104\,
P(0) => \ARG__28_n_105\,
PATTERNBDETECT => \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__28_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__28_UNDERFLOW_UNCONNECTED\
);
\ARG__28_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_15\(14),
O => \ARG__28_i_1_n_0\
);
\ARG__29\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__29_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__29_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_17\(14),
C(12) => \ARG__29_i_1_n_0\,
C(11) => \ARG__29_i_1_n_0\,
C(10) => \ARG__29_i_1_n_0\,
C(9) => \ARG__29_i_1_n_0\,
C(8) => \ARG__29_i_1_n_0\,
C(7) => \ARG__29_i_1_n_0\,
C(6) => \ARG__29_i_1_n_0\,
C(5) => \ARG__29_i_1_n_0\,
C(4) => \ARG__29_i_1_n_0\,
C(3) => \ARG__29_i_1_n_0\,
C(2) => \ARG__29_i_1_n_0\,
C(1) => \ARG__29_i_1_n_0\,
C(0) => \ARG__29_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__29_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__29_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__29_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__29_n_76\,
P(28) => \ARG__29_n_77\,
P(27) => \ARG__29_n_78\,
P(26) => \ARG__29_n_79\,
P(25) => \ARG__29_n_80\,
P(24) => \ARG__29_n_81\,
P(23) => \ARG__29_n_82\,
P(22) => \ARG__29_n_83\,
P(21) => \ARG__29_n_84\,
P(20) => \ARG__29_n_85\,
P(19) => \ARG__29_n_86\,
P(18) => \ARG__29_n_87\,
P(17) => \ARG__29_n_88\,
P(16) => \ARG__29_n_89\,
P(15) => \ARG__29_n_90\,
P(14) => \ARG__29_n_91\,
P(13) => \ARG__29_n_92\,
P(12) => \ARG__29_n_93\,
P(11) => \ARG__29_n_94\,
P(10) => \ARG__29_n_95\,
P(9) => \ARG__29_n_96\,
P(8) => \ARG__29_n_97\,
P(7) => \ARG__29_n_98\,
P(6) => \ARG__29_n_99\,
P(5) => \ARG__29_n_100\,
P(4) => \ARG__29_n_101\,
P(3) => \ARG__29_n_102\,
P(2) => \ARG__29_n_103\,
P(1) => \ARG__29_n_104\,
P(0) => \ARG__29_n_105\,
PATTERNBDETECT => \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__29_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__29_UNDERFLOW_UNCONNECTED\
);
\ARG__29_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_17\(14),
O => \ARG__29_i_1_n_0\
);
\ARG__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_2\(14),
O => \ARG__2_i_1_n_0\
);
\ARG__3\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__3_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__3_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_20\(14),
C(12) => \ARG__3_i_1_n_0\,
C(11) => \ARG__3_i_1_n_0\,
C(10) => \ARG__3_i_1_n_0\,
C(9) => \ARG__3_i_1_n_0\,
C(8) => \ARG__3_i_1_n_0\,
C(7) => \ARG__3_i_1_n_0\,
C(6) => \ARG__3_i_1_n_0\,
C(5) => \ARG__3_i_1_n_0\,
C(4) => \ARG__3_i_1_n_0\,
C(3) => \ARG__3_i_1_n_0\,
C(2) => \ARG__3_i_1_n_0\,
C(1) => \ARG__3_i_1_n_0\,
C(0) => \ARG__3_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__3_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__3_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__3_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__3_n_76\,
P(28) => \ARG__3_n_77\,
P(27) => \ARG__3_n_78\,
P(26) => \ARG__3_n_79\,
P(25) => \ARG__3_n_80\,
P(24) => \ARG__3_n_81\,
P(23) => \ARG__3_n_82\,
P(22) => \ARG__3_n_83\,
P(21) => \ARG__3_n_84\,
P(20) => \ARG__3_n_85\,
P(19) => \ARG__3_n_86\,
P(18) => \ARG__3_n_87\,
P(17) => \ARG__3_n_88\,
P(16) => \ARG__3_n_89\,
P(15) => \ARG__3_n_90\,
P(14) => \ARG__3_n_91\,
P(13) => \ARG__3_n_92\,
P(12) => \ARG__3_n_93\,
P(11) => \ARG__3_n_94\,
P(10) => \ARG__3_n_95\,
P(9) => \ARG__3_n_96\,
P(8) => \ARG__3_n_97\,
P(7) => \ARG__3_n_98\,
P(6) => \ARG__3_n_99\,
P(5) => \ARG__3_n_100\,
P(4) => \ARG__3_n_101\,
P(3) => \ARG__3_n_102\,
P(2) => \ARG__3_n_103\,
P(1) => \ARG__3_n_104\,
P(0) => \ARG__3_n_105\,
PATTERNBDETECT => \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__3_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__3_UNDERFLOW_UNCONNECTED\
);
\ARG__30\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__30_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__30_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp\(14),
C(12) => \ARG__30_i_1_n_0\,
C(11) => \ARG__30_i_1_n_0\,
C(10) => \ARG__30_i_1_n_0\,
C(9) => \ARG__30_i_1_n_0\,
C(8) => \ARG__30_i_1_n_0\,
C(7) => \ARG__30_i_1_n_0\,
C(6) => \ARG__30_i_1_n_0\,
C(5) => \ARG__30_i_1_n_0\,
C(4) => \ARG__30_i_1_n_0\,
C(3) => \ARG__30_i_1_n_0\,
C(2) => \ARG__30_i_1_n_0\,
C(1) => \ARG__30_i_1_n_0\,
C(0) => \ARG__30_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__30_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__30_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__30_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE15(15 downto 0),
P(13) => \ARG__30_n_92\,
P(12) => \ARG__30_n_93\,
P(11) => \ARG__30_n_94\,
P(10) => \ARG__30_n_95\,
P(9) => \ARG__30_n_96\,
P(8) => \ARG__30_n_97\,
P(7) => \ARG__30_n_98\,
P(6) => \ARG__30_n_99\,
P(5) => \ARG__30_n_100\,
P(4) => \ARG__30_n_101\,
P(3) => \ARG__30_n_102\,
P(2) => \ARG__30_n_103\,
P(1) => \ARG__30_n_104\,
P(0) => \ARG__30_n_105\,
PATTERNBDETECT => \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__30_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__30_UNDERFLOW_UNCONNECTED\
);
\ARG__30_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp\(14),
O => \ARG__30_i_1_n_0\
);
\ARG__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_20\(14),
O => \ARG__3_i_1_n_0\
);
\ARG__4\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__4_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__4_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_3\(14),
C(12) => \ARG__4_i_1_n_0\,
C(11) => \ARG__4_i_1_n_0\,
C(10) => \ARG__4_i_1_n_0\,
C(9) => \ARG__4_i_1_n_0\,
C(8) => \ARG__4_i_1_n_0\,
C(7) => \ARG__4_i_1_n_0\,
C(6) => \ARG__4_i_1_n_0\,
C(5) => \ARG__4_i_1_n_0\,
C(4) => \ARG__4_i_1_n_0\,
C(3) => \ARG__4_i_1_n_0\,
C(2) => \ARG__4_i_1_n_0\,
C(1) => \ARG__4_i_1_n_0\,
C(0) => \ARG__4_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__4_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__4_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__4_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE20(15 downto 0),
P(13) => \ARG__4_n_92\,
P(12) => \ARG__4_n_93\,
P(11) => \ARG__4_n_94\,
P(10) => \ARG__4_n_95\,
P(9) => \ARG__4_n_96\,
P(8) => \ARG__4_n_97\,
P(7) => \ARG__4_n_98\,
P(6) => \ARG__4_n_99\,
P(5) => \ARG__4_n_100\,
P(4) => \ARG__4_n_101\,
P(3) => \ARG__4_n_102\,
P(2) => \ARG__4_n_103\,
P(1) => \ARG__4_n_104\,
P(0) => \ARG__4_n_105\,
PATTERNBDETECT => \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__4_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__4_UNDERFLOW_UNCONNECTED\
);
\ARG__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_3\(14),
O => \ARG__4_i_1_n_0\
);
\ARG__5\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__5_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__5_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_21\(14),
C(12) => \ARG__5_i_1_n_0\,
C(11) => \ARG__5_i_1_n_0\,
C(10) => \ARG__5_i_1_n_0\,
C(9) => \ARG__5_i_1_n_0\,
C(8) => \ARG__5_i_1_n_0\,
C(7) => \ARG__5_i_1_n_0\,
C(6) => \ARG__5_i_1_n_0\,
C(5) => \ARG__5_i_1_n_0\,
C(4) => \ARG__5_i_1_n_0\,
C(3) => \ARG__5_i_1_n_0\,
C(2) => \ARG__5_i_1_n_0\,
C(1) => \ARG__5_i_1_n_0\,
C(0) => \ARG__5_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__5_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__5_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__5_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__5_n_76\,
P(28) => \ARG__5_n_77\,
P(27) => \ARG__5_n_78\,
P(26) => \ARG__5_n_79\,
P(25) => \ARG__5_n_80\,
P(24) => \ARG__5_n_81\,
P(23) => \ARG__5_n_82\,
P(22) => \ARG__5_n_83\,
P(21) => \ARG__5_n_84\,
P(20) => \ARG__5_n_85\,
P(19) => \ARG__5_n_86\,
P(18) => \ARG__5_n_87\,
P(17) => \ARG__5_n_88\,
P(16) => \ARG__5_n_89\,
P(15) => \ARG__5_n_90\,
P(14) => \ARG__5_n_91\,
P(13) => \ARG__5_n_92\,
P(12) => \ARG__5_n_93\,
P(11) => \ARG__5_n_94\,
P(10) => \ARG__5_n_95\,
P(9) => \ARG__5_n_96\,
P(8) => \ARG__5_n_97\,
P(7) => \ARG__5_n_98\,
P(6) => \ARG__5_n_99\,
P(5) => \ARG__5_n_100\,
P(4) => \ARG__5_n_101\,
P(3) => \ARG__5_n_102\,
P(2) => \ARG__5_n_103\,
P(1) => \ARG__5_n_104\,
P(0) => \ARG__5_n_105\,
PATTERNBDETECT => \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__5_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__5_UNDERFLOW_UNCONNECTED\
);
\ARG__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_21\(14),
O => \ARG__5_i_1_n_0\
);
\ARG__6\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__6_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__6_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_4\(14),
C(12) => \ARG__6_i_1_n_0\,
C(11) => \ARG__6_i_1_n_0\,
C(10) => \ARG__6_i_1_n_0\,
C(9) => \ARG__6_i_1_n_0\,
C(8) => \ARG__6_i_1_n_0\,
C(7) => \ARG__6_i_1_n_0\,
C(6) => \ARG__6_i_1_n_0\,
C(5) => \ARG__6_i_1_n_0\,
C(4) => \ARG__6_i_1_n_0\,
C(3) => \ARG__6_i_1_n_0\,
C(2) => \ARG__6_i_1_n_0\,
C(1) => \ARG__6_i_1_n_0\,
C(0) => \ARG__6_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__6_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__6_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__6_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE22(15 downto 0),
P(13) => \ARG__6_n_92\,
P(12) => \ARG__6_n_93\,
P(11) => \ARG__6_n_94\,
P(10) => \ARG__6_n_95\,
P(9) => \ARG__6_n_96\,
P(8) => \ARG__6_n_97\,
P(7) => \ARG__6_n_98\,
P(6) => \ARG__6_n_99\,
P(5) => \ARG__6_n_100\,
P(4) => \ARG__6_n_101\,
P(3) => \ARG__6_n_102\,
P(2) => \ARG__6_n_103\,
P(1) => \ARG__6_n_104\,
P(0) => \ARG__6_n_105\,
PATTERNBDETECT => \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__6_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__6_UNDERFLOW_UNCONNECTED\
);
\ARG__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_4\(14),
O => \ARG__6_i_1_n_0\
);
\ARG__7\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__7_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__7_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_22\(14),
C(12) => \ARG__7_i_1_n_0\,
C(11) => \ARG__7_i_1_n_0\,
C(10) => \ARG__7_i_1_n_0\,
C(9) => \ARG__7_i_1_n_0\,
C(8) => \ARG__7_i_1_n_0\,
C(7) => \ARG__7_i_1_n_0\,
C(6) => \ARG__7_i_1_n_0\,
C(5) => \ARG__7_i_1_n_0\,
C(4) => \ARG__7_i_1_n_0\,
C(3) => \ARG__7_i_1_n_0\,
C(2) => \ARG__7_i_1_n_0\,
C(1) => \ARG__7_i_1_n_0\,
C(0) => \ARG__7_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__7_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__7_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__7_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__7_n_76\,
P(28) => \ARG__7_n_77\,
P(27) => \ARG__7_n_78\,
P(26) => \ARG__7_n_79\,
P(25) => \ARG__7_n_80\,
P(24) => \ARG__7_n_81\,
P(23) => \ARG__7_n_82\,
P(22) => \ARG__7_n_83\,
P(21) => \ARG__7_n_84\,
P(20) => \ARG__7_n_85\,
P(19) => \ARG__7_n_86\,
P(18) => \ARG__7_n_87\,
P(17) => \ARG__7_n_88\,
P(16) => \ARG__7_n_89\,
P(15) => \ARG__7_n_90\,
P(14) => \ARG__7_n_91\,
P(13) => \ARG__7_n_92\,
P(12) => \ARG__7_n_93\,
P(11) => \ARG__7_n_94\,
P(10) => \ARG__7_n_95\,
P(9) => \ARG__7_n_96\,
P(8) => \ARG__7_n_97\,
P(7) => \ARG__7_n_98\,
P(6) => \ARG__7_n_99\,
P(5) => \ARG__7_n_100\,
P(4) => \ARG__7_n_101\,
P(3) => \ARG__7_n_102\,
P(2) => \ARG__7_n_103\,
P(1) => \ARG__7_n_104\,
P(0) => \ARG__7_n_105\,
PATTERNBDETECT => \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__7_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__7_UNDERFLOW_UNCONNECTED\
);
\ARG__7_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_22\(14),
O => \ARG__7_i_1_n_0\
);
\ARG__8\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__8_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__8_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_5\(14),
C(12) => \ARG__8_i_1_n_0\,
C(11) => \ARG__8_i_1_n_0\,
C(10) => \ARG__8_i_1_n_0\,
C(9) => \ARG__8_i_1_n_0\,
C(8) => \ARG__8_i_1_n_0\,
C(7) => \ARG__8_i_1_n_0\,
C(6) => \ARG__8_i_1_n_0\,
C(5) => \ARG__8_i_1_n_0\,
C(4) => \ARG__8_i_1_n_0\,
C(3) => \ARG__8_i_1_n_0\,
C(2) => \ARG__8_i_1_n_0\,
C(1) => \ARG__8_i_1_n_0\,
C(0) => \ARG__8_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__8_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__8_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__8_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE24(15 downto 0),
P(13) => \ARG__8_n_92\,
P(12) => \ARG__8_n_93\,
P(11) => \ARG__8_n_94\,
P(10) => \ARG__8_n_95\,
P(9) => \ARG__8_n_96\,
P(8) => \ARG__8_n_97\,
P(7) => \ARG__8_n_98\,
P(6) => \ARG__8_n_99\,
P(5) => \ARG__8_n_100\,
P(4) => \ARG__8_n_101\,
P(3) => \ARG__8_n_102\,
P(2) => \ARG__8_n_103\,
P(1) => \ARG__8_n_104\,
P(0) => \ARG__8_n_105\,
PATTERNBDETECT => \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__8_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__8_UNDERFLOW_UNCONNECTED\
);
\ARG__8_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_5\(14),
O => \ARG__8_i_1_n_0\
);
\ARG__9\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__9_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__9_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_23\(14),
C(12) => \ARG__9_i_1_n_0\,
C(11) => \ARG__9_i_1_n_0\,
C(10) => \ARG__9_i_1_n_0\,
C(9) => \ARG__9_i_1_n_0\,
C(8) => \ARG__9_i_1_n_0\,
C(7) => \ARG__9_i_1_n_0\,
C(6) => \ARG__9_i_1_n_0\,
C(5) => \ARG__9_i_1_n_0\,
C(4) => \ARG__9_i_1_n_0\,
C(3) => \ARG__9_i_1_n_0\,
C(2) => \ARG__9_i_1_n_0\,
C(1) => \ARG__9_i_1_n_0\,
C(0) => \ARG__9_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__9_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__9_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__9_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__9_n_76\,
P(28) => \ARG__9_n_77\,
P(27) => \ARG__9_n_78\,
P(26) => \ARG__9_n_79\,
P(25) => \ARG__9_n_80\,
P(24) => \ARG__9_n_81\,
P(23) => \ARG__9_n_82\,
P(22) => \ARG__9_n_83\,
P(21) => \ARG__9_n_84\,
P(20) => \ARG__9_n_85\,
P(19) => \ARG__9_n_86\,
P(18) => \ARG__9_n_87\,
P(17) => \ARG__9_n_88\,
P(16) => \ARG__9_n_89\,
P(15) => \ARG__9_n_90\,
P(14) => \ARG__9_n_91\,
P(13) => \ARG__9_n_92\,
P(12) => \ARG__9_n_93\,
P(11) => \ARG__9_n_94\,
P(10) => \ARG__9_n_95\,
P(9) => \ARG__9_n_96\,
P(8) => \ARG__9_n_97\,
P(7) => \ARG__9_n_98\,
P(6) => \ARG__9_n_99\,
P(5) => \ARG__9_n_100\,
P(4) => \ARG__9_n_101\,
P(3) => \ARG__9_n_102\,
P(2) => \ARG__9_n_103\,
P(1) => \ARG__9_n_104\,
P(0) => \ARG__9_n_105\,
PATTERNBDETECT => \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__9_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__9_UNDERFLOW_UNCONNECTED\
);
\ARG__9_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_23\(14),
O => \ARG__9_i_1_n_0\
);
ARG_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => ARG_carry_n_0,
CO(2) => ARG_carry_n_1,
CO(1) => ARG_carry_n_2,
CO(0) => ARG_carry_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => \^mul_temp_16\(1 downto 0),
DI(0) => '1',
O(3 downto 0) => NLW_ARG_carry_O_UNCONNECTED(3 downto 0),
S(3) => \^mul_temp_16\(2),
S(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0)
);
\ARG_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => ARG_carry_n_0,
CO(3) => \ARG_carry__0_n_0\,
CO(2) => \ARG_carry__0_n_1\,
CO(1) => \ARG_carry__0_n_2\,
CO(0) => \ARG_carry__0_n_3\,
CYINIT => '0',
DI(3) => \^mul_temp_16\(5),
DI(2) => \^mul_temp_16\(3),
DI(1) => \^mul_temp_16\(4),
DI(0) => DI(0),
O(3 downto 0) => \ARG__31\(20 downto 17),
S(3) => \ARG_carry__0_i_2_n_0\,
S(2) => \ARG_carry__0_i_3_n_0\,
S(1) => \ARG_carry__0_i_4_n_0\,
S(0) => \^mul_temp_16\(3)
);
\ARG_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(5),
I1 => \^mul_temp_16\(6),
O => \ARG_carry__0_i_2_n_0\
);
\ARG_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(5),
O => \ARG_carry__0_i_3_n_0\
);
\ARG_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(4),
O => \ARG_carry__0_i_4_n_0\
);
\ARG_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__0_n_0\,
CO(3) => \ARG_carry__1_n_0\,
CO(2) => \ARG_carry__1_n_1\,
CO(1) => \ARG_carry__1_n_2\,
CO(0) => \ARG_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(9 downto 6),
O(3 downto 0) => \ARG__31\(24 downto 21),
S(3) => \ARG_carry__1_i_1_n_0\,
S(2) => \ARG_carry__1_i_2_n_0\,
S(1) => \ARG_carry__1_i_3_n_0\,
S(0) => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(9),
I1 => \^mul_temp_16\(10),
O => \ARG_carry__1_i_1_n_0\
);
\ARG_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(8),
I1 => \^mul_temp_16\(9),
O => \ARG_carry__1_i_2_n_0\
);
\ARG_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(7),
I1 => \^mul_temp_16\(8),
O => \ARG_carry__1_i_3_n_0\
);
\ARG_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(6),
I1 => \^mul_temp_16\(7),
O => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__1_n_0\,
CO(3) => \ARG_carry__2_n_0\,
CO(2) => \ARG_carry__2_n_1\,
CO(1) => \ARG_carry__2_n_2\,
CO(0) => \ARG_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(13 downto 10),
O(3 downto 0) => \ARG__31\(28 downto 25),
S(3) => \ARG_carry__2_i_1_n_0\,
S(2) => \ARG_carry__2_i_2_n_0\,
S(1) => \ARG_carry__2_i_3_n_0\,
S(0) => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(13),
I1 => \^mul_temp_16\(14),
O => \ARG_carry__2_i_1_n_0\
);
\ARG_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(12),
I1 => \^mul_temp_16\(13),
O => \ARG_carry__2_i_2_n_0\
);
\ARG_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(11),
I1 => \^mul_temp_16\(12),
O => \ARG_carry__2_i_3_n_0\
);
\ARG_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(10),
I1 => \^mul_temp_16\(11),
O => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__2_n_0\,
CO(3 downto 1) => \NLW_ARG_carry__3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \ARG_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^mul_temp_16\(14),
O(3 downto 2) => \NLW_ARG_carry__3_O_UNCONNECTED\(3 downto 2),
O(1) => \ARG__31\(32),
O(0) => \ARG__31\(29),
S(3 downto 1) => B"001",
S(0) => \ARG_carry__3_i_1_n_0\
);
\ARG_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(14),
I1 => \^mul_temp_16\(15),
O => \ARG_carry__3_i_1_n_0\
);
ARG_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_18\(14),
O => ARG_i_1_n_0
);
\add_temp_14__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__0_carry_n_0\,
CO(2) => \add_temp_14__0_carry_n_1\,
CO(1) => \add_temp_14__0_carry_n_2\,
CO(0) => \add_temp_14__0_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry_i_1_n_0\,
DI(2) => \add_temp_14__0_carry_i_2_n_0\,
DI(1) => \add_temp_14__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__0_carry_n_4\,
O(2) => \add_temp_14__0_carry_n_5\,
O(1) => \add_temp_14__0_carry_n_6\,
O(0) => \add_temp_14__0_carry_n_7\,
S(3) => \add_temp_14__0_carry_i_4_n_0\,
S(2) => \add_temp_14__0_carry_i_5_n_0\,
S(1) => \add_temp_14__0_carry_i_6_n_0\,
S(0) => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry_n_0\,
CO(3) => \add_temp_14__0_carry__0_n_0\,
CO(2) => \add_temp_14__0_carry__0_n_1\,
CO(1) => \add_temp_14__0_carry__0_n_2\,
CO(0) => \add_temp_14__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__0_i_4_n_0\,
O(3) => \add_temp_14__0_carry__0_n_4\,
O(2) => \add_temp_14__0_carry__0_n_5\,
O(1) => \add_temp_14__0_carry__0_n_6\,
O(0) => \add_temp_14__0_carry__0_n_7\,
S(3) => \add_temp_14__0_carry__0_i_5_n_0\,
S(2) => \add_temp_14__0_carry__0_i_6_n_0\,
S(1) => \add_temp_14__0_carry__0_i_7_n_0\,
S(0) => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
O => \add_temp_14__0_carry__0_i_1_n_0\
);
\add_temp_14__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
O => \add_temp_14__0_carry__0_i_2_n_0\
);
\add_temp_14__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
O => \add_temp_14__0_carry__0_i_3_n_0\
);
\add_temp_14__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
O => \add_temp_14__0_carry__0_i_4_n_0\
);
\add_temp_14__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
I3 => \add_temp_14__0_carry__0_i_1_n_0\,
O => \add_temp_14__0_carry__0_i_5_n_0\
);
\add_temp_14__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
I3 => \add_temp_14__0_carry__0_i_2_n_0\,
O => \add_temp_14__0_carry__0_i_6_n_0\
);
\add_temp_14__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
I3 => \add_temp_14__0_carry__0_i_3_n_0\,
O => \add_temp_14__0_carry__0_i_7_n_0\
);
\add_temp_14__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
I3 => \add_temp_14__0_carry__0_i_4_n_0\,
O => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__0_n_0\,
CO(3) => \add_temp_14__0_carry__1_n_0\,
CO(2) => \add_temp_14__0_carry__1_n_1\,
CO(1) => \add_temp_14__0_carry__1_n_2\,
CO(0) => \add_temp_14__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__1_i_4_n_0\,
O(3) => \add_temp_14__0_carry__1_n_4\,
O(2) => \add_temp_14__0_carry__1_n_5\,
O(1) => \add_temp_14__0_carry__1_n_6\,
O(0) => \add_temp_14__0_carry__1_n_7\,
S(3) => \add_temp_14__0_carry__1_i_5_n_0\,
S(2) => \add_temp_14__0_carry__1_i_6_n_0\,
S(1) => \add_temp_14__0_carry__1_i_7_n_0\,
S(0) => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
O => \add_temp_14__0_carry__1_i_1_n_0\
);
\add_temp_14__0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
O => \add_temp_14__0_carry__1_i_2_n_0\
);
\add_temp_14__0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
O => \add_temp_14__0_carry__1_i_3_n_0\
);
\add_temp_14__0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
O => \add_temp_14__0_carry__1_i_4_n_0\
);
\add_temp_14__0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
I3 => \add_temp_14__0_carry__1_i_1_n_0\,
O => \add_temp_14__0_carry__1_i_5_n_0\
);
\add_temp_14__0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
I3 => \add_temp_14__0_carry__1_i_2_n_0\,
O => \add_temp_14__0_carry__1_i_6_n_0\
);
\add_temp_14__0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
I3 => \add_temp_14__0_carry__1_i_3_n_0\,
O => \add_temp_14__0_carry__1_i_7_n_0\
);
\add_temp_14__0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
I3 => \add_temp_14__0_carry__1_i_4_n_0\,
O => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__0_carry__2_n_1\,
CO(1) => \add_temp_14__0_carry__2_n_2\,
CO(0) => \add_temp_14__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__0_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__0_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__0_carry__2_i_3_n_0\,
O(3) => \add_temp_14__0_carry__2_n_4\,
O(2) => \add_temp_14__0_carry__2_n_5\,
O(1) => \add_temp_14__0_carry__2_n_6\,
O(0) => \add_temp_14__0_carry__2_n_7\,
S(3) => \add_temp_14__0_carry__2_i_4_n_0\,
S(2) => \add_temp_14__0_carry__2_i_5_n_0\,
S(1) => \add_temp_14__0_carry__2_i_6_n_0\,
S(0) => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
O => \add_temp_14__0_carry__2_i_1_n_0\
);
\add_temp_14__0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
O => \add_temp_14__0_carry__2_i_2_n_0\
);
\add_temp_14__0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
O => \add_temp_14__0_carry__2_i_3_n_0\
);
\add_temp_14__0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE15(14),
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE44(15),
I4 => RESIZE42(15),
I5 => RESIZE15(15),
O => \add_temp_14__0_carry__2_i_4_n_0\
);
\add_temp_14__0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__2_i_1_n_0\,
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE15(14),
O => \add_temp_14__0_carry__2_i_5_n_0\
);
\add_temp_14__0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
I3 => \add_temp_14__0_carry__2_i_2_n_0\,
O => \add_temp_14__0_carry__2_i_6_n_0\
);
\add_temp_14__0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
I3 => \add_temp_14__0_carry__2_i_3_n_0\,
O => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
O => \add_temp_14__0_carry_i_1_n_0\
);
\add_temp_14__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
O => \add_temp_14__0_carry_i_2_n_0\
);
\add_temp_14__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_3_n_0\
);
\add_temp_14__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
I3 => \add_temp_14__0_carry_i_1_n_0\,
O => \add_temp_14__0_carry_i_4_n_0\
);
\add_temp_14__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
I3 => \add_temp_14__0_carry_i_2_n_0\,
O => \add_temp_14__0_carry_i_5_n_0\
);
\add_temp_14__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
I3 => \add_temp_14__0_carry_i_3_n_0\,
O => \add_temp_14__0_carry_i_6_n_0\
);
\add_temp_14__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__138_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__138_carry_n_0\,
CO(2) => \add_temp_14__138_carry_n_1\,
CO(1) => \add_temp_14__138_carry_n_2\,
CO(0) => \add_temp_14__138_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry_i_1_n_0\,
DI(2) => \add_temp_14__138_carry_i_2_n_0\,
DI(1) => \add_temp_14__138_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__138_carry_n_4\,
O(2) => \add_temp_14__138_carry_n_5\,
O(1) => \add_temp_14__138_carry_n_6\,
O(0) => \add_temp_14__138_carry_n_7\,
S(3) => \add_temp_14__138_carry_i_4_n_0\,
S(2) => \add_temp_14__138_carry_i_5_n_0\,
S(1) => \add_temp_14__138_carry_i_6_n_0\,
S(0) => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__138_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry_n_0\,
CO(3) => \add_temp_14__138_carry__0_n_0\,
CO(2) => \add_temp_14__138_carry__0_n_1\,
CO(1) => \add_temp_14__138_carry__0_n_2\,
CO(0) => \add_temp_14__138_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__0_i_4_n_0\,
O(3) => \add_temp_14__138_carry__0_n_4\,
O(2) => \add_temp_14__138_carry__0_n_5\,
O(1) => \add_temp_14__138_carry__0_n_6\,
O(0) => \add_temp_14__138_carry__0_n_7\,
S(3) => \add_temp_14__138_carry__0_i_5_n_0\,
S(2) => \add_temp_14__138_carry__0_i_6_n_0\,
S(1) => \add_temp_14__138_carry__0_i_7_n_0\,
S(0) => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
O => \add_temp_14__138_carry__0_i_1_n_0\
);
\add_temp_14__138_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
O => \add_temp_14__138_carry__0_i_2_n_0\
);
\add_temp_14__138_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
O => \add_temp_14__138_carry__0_i_3_n_0\
);
\add_temp_14__138_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
O => \add_temp_14__138_carry__0_i_4_n_0\
);
\add_temp_14__138_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
I3 => \add_temp_14__138_carry__0_i_1_n_0\,
O => \add_temp_14__138_carry__0_i_5_n_0\
);
\add_temp_14__138_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
I3 => \add_temp_14__138_carry__0_i_2_n_0\,
O => \add_temp_14__138_carry__0_i_6_n_0\
);
\add_temp_14__138_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
I3 => \add_temp_14__138_carry__0_i_3_n_0\,
O => \add_temp_14__138_carry__0_i_7_n_0\
);
\add_temp_14__138_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
I3 => \add_temp_14__138_carry__0_i_4_n_0\,
O => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__0_n_0\,
CO(3) => \add_temp_14__138_carry__1_n_0\,
CO(2) => \add_temp_14__138_carry__1_n_1\,
CO(1) => \add_temp_14__138_carry__1_n_2\,
CO(0) => \add_temp_14__138_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__1_i_4_n_0\,
O(3) => \add_temp_14__138_carry__1_n_4\,
O(2) => \add_temp_14__138_carry__1_n_5\,
O(1) => \add_temp_14__138_carry__1_n_6\,
O(0) => \add_temp_14__138_carry__1_n_7\,
S(3) => \add_temp_14__138_carry__1_i_5_n_0\,
S(2) => \add_temp_14__138_carry__1_i_6_n_0\,
S(1) => \add_temp_14__138_carry__1_i_7_n_0\,
S(0) => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
O => \add_temp_14__138_carry__1_i_1_n_0\
);
\add_temp_14__138_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
O => \add_temp_14__138_carry__1_i_2_n_0\
);
\add_temp_14__138_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
O => \add_temp_14__138_carry__1_i_3_n_0\
);
\add_temp_14__138_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
O => \add_temp_14__138_carry__1_i_4_n_0\
);
\add_temp_14__138_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
I3 => \add_temp_14__138_carry__1_i_1_n_0\,
O => \add_temp_14__138_carry__1_i_5_n_0\
);
\add_temp_14__138_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
I3 => \add_temp_14__138_carry__1_i_2_n_0\,
O => \add_temp_14__138_carry__1_i_6_n_0\
);
\add_temp_14__138_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
I3 => \add_temp_14__138_carry__1_i_3_n_0\,
O => \add_temp_14__138_carry__1_i_7_n_0\
);
\add_temp_14__138_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
I3 => \add_temp_14__138_carry__1_i_4_n_0\,
O => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__138_carry__2_n_1\,
CO(1) => \add_temp_14__138_carry__2_n_2\,
CO(0) => \add_temp_14__138_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__138_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__138_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__138_carry__2_i_3_n_0\,
O(3) => \add_temp_14__138_carry__2_n_4\,
O(2) => \add_temp_14__138_carry__2_n_5\,
O(1) => \add_temp_14__138_carry__2_n_6\,
O(0) => \add_temp_14__138_carry__2_n_7\,
S(3) => \add_temp_14__138_carry__2_i_4_n_0\,
S(2) => \add_temp_14__138_carry__2_i_5_n_0\,
S(1) => \add_temp_14__138_carry__2_i_6_n_0\,
S(0) => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
O => \add_temp_14__138_carry__2_i_1_n_0\
);
\add_temp_14__138_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
O => \add_temp_14__138_carry__2_i_2_n_0\
);
\add_temp_14__138_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
O => \add_temp_14__138_carry__2_i_3_n_0\
);
\add_temp_14__138_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE28(14),
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE26(15),
I4 => RESIZE24(15),
I5 => RESIZE28(15),
O => \add_temp_14__138_carry__2_i_4_n_0\
);
\add_temp_14__138_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__138_carry__2_i_1_n_0\,
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE28(14),
O => \add_temp_14__138_carry__2_i_5_n_0\
);
\add_temp_14__138_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
I3 => \add_temp_14__138_carry__2_i_2_n_0\,
O => \add_temp_14__138_carry__2_i_6_n_0\
);
\add_temp_14__138_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
I3 => \add_temp_14__138_carry__2_i_3_n_0\,
O => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
O => \add_temp_14__138_carry_i_1_n_0\
);
\add_temp_14__138_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
O => \add_temp_14__138_carry_i_2_n_0\
);
\add_temp_14__138_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_3_n_0\
);
\add_temp_14__138_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
I3 => \add_temp_14__138_carry_i_1_n_0\,
O => \add_temp_14__138_carry_i_4_n_0\
);
\add_temp_14__138_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
I3 => \add_temp_14__138_carry_i_2_n_0\,
O => \add_temp_14__138_carry_i_5_n_0\
);
\add_temp_14__138_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
I3 => \add_temp_14__138_carry_i_3_n_0\,
O => \add_temp_14__138_carry_i_6_n_0\
);
\add_temp_14__138_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__184_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__184_carry_n_0\,
CO(2) => \add_temp_14__184_carry_n_1\,
CO(1) => \add_temp_14__184_carry_n_2\,
CO(0) => \add_temp_14__184_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry_i_1_n_0\,
DI(2) => \add_temp_14__184_carry_i_2_n_0\,
DI(1) => \add_temp_14__184_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__184_carry_n_4\,
O(2) => \add_temp_14__184_carry_n_5\,
O(1) => \add_temp_14__184_carry_n_6\,
O(0) => \add_temp_14__184_carry_n_7\,
S(3) => \add_temp_14__184_carry_i_4_n_0\,
S(2) => \add_temp_14__184_carry_i_5_n_0\,
S(1) => \add_temp_14__184_carry_i_6_n_0\,
S(0) => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__184_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry_n_0\,
CO(3) => \add_temp_14__184_carry__0_n_0\,
CO(2) => \add_temp_14__184_carry__0_n_1\,
CO(1) => \add_temp_14__184_carry__0_n_2\,
CO(0) => \add_temp_14__184_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__0_i_4_n_0\,
O(3) => \add_temp_14__184_carry__0_n_4\,
O(2) => \add_temp_14__184_carry__0_n_5\,
O(1) => \add_temp_14__184_carry__0_n_6\,
O(0) => \add_temp_14__184_carry__0_n_7\,
S(3) => \add_temp_14__184_carry__0_i_5_n_0\,
S(2) => \add_temp_14__184_carry__0_i_6_n_0\,
S(1) => \add_temp_14__184_carry__0_i_7_n_0\,
S(0) => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
O => \add_temp_14__184_carry__0_i_1_n_0\
);
\add_temp_14__184_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
O => \add_temp_14__184_carry__0_i_2_n_0\
);
\add_temp_14__184_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
O => \add_temp_14__184_carry__0_i_3_n_0\
);
\add_temp_14__184_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
O => \add_temp_14__184_carry__0_i_4_n_0\
);
\add_temp_14__184_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
I3 => \add_temp_14__184_carry__0_i_1_n_0\,
O => \add_temp_14__184_carry__0_i_5_n_0\
);
\add_temp_14__184_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
I3 => \add_temp_14__184_carry__0_i_2_n_0\,
O => \add_temp_14__184_carry__0_i_6_n_0\
);
\add_temp_14__184_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
I3 => \add_temp_14__184_carry__0_i_3_n_0\,
O => \add_temp_14__184_carry__0_i_7_n_0\
);
\add_temp_14__184_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
I3 => \add_temp_14__184_carry__0_i_4_n_0\,
O => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__0_n_0\,
CO(3) => \add_temp_14__184_carry__1_n_0\,
CO(2) => \add_temp_14__184_carry__1_n_1\,
CO(1) => \add_temp_14__184_carry__1_n_2\,
CO(0) => \add_temp_14__184_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__1_i_4_n_0\,
O(3) => \add_temp_14__184_carry__1_n_4\,
O(2) => \add_temp_14__184_carry__1_n_5\,
O(1) => \add_temp_14__184_carry__1_n_6\,
O(0) => \add_temp_14__184_carry__1_n_7\,
S(3) => \add_temp_14__184_carry__1_i_5_n_0\,
S(2) => \add_temp_14__184_carry__1_i_6_n_0\,
S(1) => \add_temp_14__184_carry__1_i_7_n_0\,
S(0) => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
O => \add_temp_14__184_carry__1_i_1_n_0\
);
\add_temp_14__184_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
O => \add_temp_14__184_carry__1_i_2_n_0\
);
\add_temp_14__184_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
O => \add_temp_14__184_carry__1_i_3_n_0\
);
\add_temp_14__184_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
O => \add_temp_14__184_carry__1_i_4_n_0\
);
\add_temp_14__184_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
I3 => \add_temp_14__184_carry__1_i_1_n_0\,
O => \add_temp_14__184_carry__1_i_5_n_0\
);
\add_temp_14__184_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
I3 => \add_temp_14__184_carry__1_i_2_n_0\,
O => \add_temp_14__184_carry__1_i_6_n_0\
);
\add_temp_14__184_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
I3 => \add_temp_14__184_carry__1_i_3_n_0\,
O => \add_temp_14__184_carry__1_i_7_n_0\
);
\add_temp_14__184_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
I3 => \add_temp_14__184_carry__1_i_4_n_0\,
O => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__184_carry__2_n_1\,
CO(1) => \add_temp_14__184_carry__2_n_2\,
CO(0) => \add_temp_14__184_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__184_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__184_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__184_carry__2_i_3_n_0\,
O(3) => \add_temp_14__184_carry__2_n_4\,
O(2) => \add_temp_14__184_carry__2_n_5\,
O(1) => \add_temp_14__184_carry__2_n_6\,
O(0) => \add_temp_14__184_carry__2_n_7\,
S(3) => \add_temp_14__184_carry__2_i_4_n_0\,
S(2) => \add_temp_14__184_carry__2_i_5_n_0\,
S(1) => \add_temp_14__184_carry__2_i_6_n_0\,
S(0) => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
O => \add_temp_14__184_carry__2_i_1_n_0\
);
\add_temp_14__184_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
O => \add_temp_14__184_carry__2_i_2_n_0\
);
\add_temp_14__184_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
O => \add_temp_14__184_carry__2_i_3_n_0\
);
\add_temp_14__184_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE20(14),
I1 => RESIZE22(14),
I2 => RESIZE18(14),
I3 => RESIZE20(15),
I4 => RESIZE18(15),
I5 => RESIZE22(15),
O => \add_temp_14__184_carry__2_i_4_n_0\
);
\add_temp_14__184_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_i_1_n_0\,
I1 => RESIZE20(14),
I2 => RESIZE18(14),
I3 => RESIZE22(14),
O => \add_temp_14__184_carry__2_i_5_n_0\
);
\add_temp_14__184_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
I3 => \add_temp_14__184_carry__2_i_2_n_0\,
O => \add_temp_14__184_carry__2_i_6_n_0\
);
\add_temp_14__184_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
I3 => \add_temp_14__184_carry__2_i_3_n_0\,
O => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
O => \add_temp_14__184_carry_i_1_n_0\
);
\add_temp_14__184_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
O => \add_temp_14__184_carry_i_2_n_0\
);
\add_temp_14__184_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_3_n_0\
);
\add_temp_14__184_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
I3 => \add_temp_14__184_carry_i_1_n_0\,
O => \add_temp_14__184_carry_i_4_n_0\
);
\add_temp_14__184_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
I3 => \add_temp_14__184_carry_i_2_n_0\,
O => \add_temp_14__184_carry_i_5_n_0\
);
\add_temp_14__184_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
I3 => \add_temp_14__184_carry_i_3_n_0\,
O => \add_temp_14__184_carry_i_6_n_0\
);
\add_temp_14__184_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__230_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__230_carry_n_0\,
CO(2) => \add_temp_14__230_carry_n_1\,
CO(1) => \add_temp_14__230_carry_n_2\,
CO(0) => \add_temp_14__230_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry_i_1_n_0\,
DI(2) => \add_temp_14__230_carry_i_2_n_0\,
DI(1) => \add_temp_14__230_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__230_carry_n_4\,
O(2) => \add_temp_14__230_carry_n_5\,
O(1) => \add_temp_14__230_carry_n_6\,
O(0) => \add_temp_14__230_carry_n_7\,
S(3) => \add_temp_14__230_carry_i_4_n_0\,
S(2) => \add_temp_14__230_carry_i_5_n_0\,
S(1) => \add_temp_14__230_carry_i_6_n_0\,
S(0) => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__230_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry_n_0\,
CO(3) => \add_temp_14__230_carry__0_n_0\,
CO(2) => \add_temp_14__230_carry__0_n_1\,
CO(1) => \add_temp_14__230_carry__0_n_2\,
CO(0) => \add_temp_14__230_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__0_i_4_n_0\,
O(3) => \add_temp_14__230_carry__0_n_4\,
O(2) => \add_temp_14__230_carry__0_n_5\,
O(1) => \add_temp_14__230_carry__0_n_6\,
O(0) => \add_temp_14__230_carry__0_n_7\,
S(3) => \add_temp_14__230_carry__0_i_5_n_0\,
S(2) => \add_temp_14__230_carry__0_i_6_n_0\,
S(1) => \add_temp_14__230_carry__0_i_7_n_0\,
S(0) => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
O => \add_temp_14__230_carry__0_i_1_n_0\
);
\add_temp_14__230_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
O => \add_temp_14__230_carry__0_i_2_n_0\
);
\add_temp_14__230_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
O => \add_temp_14__230_carry__0_i_3_n_0\
);
\add_temp_14__230_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
O => \add_temp_14__230_carry__0_i_4_n_0\
);
\add_temp_14__230_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
I3 => \add_temp_14__230_carry__0_i_1_n_0\,
O => \add_temp_14__230_carry__0_i_5_n_0\
);
\add_temp_14__230_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
I3 => \add_temp_14__230_carry__0_i_2_n_0\,
O => \add_temp_14__230_carry__0_i_6_n_0\
);
\add_temp_14__230_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
I3 => \add_temp_14__230_carry__0_i_3_n_0\,
O => \add_temp_14__230_carry__0_i_7_n_0\
);
\add_temp_14__230_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
I3 => \add_temp_14__230_carry__0_i_4_n_0\,
O => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__0_n_0\,
CO(3) => \add_temp_14__230_carry__1_n_0\,
CO(2) => \add_temp_14__230_carry__1_n_1\,
CO(1) => \add_temp_14__230_carry__1_n_2\,
CO(0) => \add_temp_14__230_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__1_i_4_n_0\,
O(3) => \add_temp_14__230_carry__1_n_4\,
O(2) => \add_temp_14__230_carry__1_n_5\,
O(1) => \add_temp_14__230_carry__1_n_6\,
O(0) => \add_temp_14__230_carry__1_n_7\,
S(3) => \add_temp_14__230_carry__1_i_5_n_0\,
S(2) => \add_temp_14__230_carry__1_i_6_n_0\,
S(1) => \add_temp_14__230_carry__1_i_7_n_0\,
S(0) => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
O => \add_temp_14__230_carry__1_i_1_n_0\
);
\add_temp_14__230_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
O => \add_temp_14__230_carry__1_i_2_n_0\
);
\add_temp_14__230_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
O => \add_temp_14__230_carry__1_i_3_n_0\
);
\add_temp_14__230_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
O => \add_temp_14__230_carry__1_i_4_n_0\
);
\add_temp_14__230_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_i_1_n_0\,
O => \add_temp_14__230_carry__1_i_5_n_0\
);
\add_temp_14__230_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_i_2_n_0\,
O => \add_temp_14__230_carry__1_i_6_n_0\
);
\add_temp_14__230_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
I3 => \add_temp_14__230_carry__1_i_3_n_0\,
O => \add_temp_14__230_carry__1_i_7_n_0\
);
\add_temp_14__230_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
I3 => \add_temp_14__230_carry__1_i_4_n_0\,
O => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__230_carry__2_n_1\,
CO(1) => \add_temp_14__230_carry__2_n_2\,
CO(0) => \add_temp_14__230_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__230_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__230_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__230_carry__2_i_3_n_0\,
O(3) => \add_temp_14__230_carry__2_n_4\,
O(2) => \add_temp_14__230_carry__2_n_5\,
O(1) => \add_temp_14__230_carry__2_n_6\,
O(0) => \add_temp_14__230_carry__2_n_7\,
S(3) => \add_temp_14__230_carry__2_i_4_n_0\,
S(2) => \add_temp_14__230_carry__2_i_5_n_0\,
S(1) => \add_temp_14__230_carry__2_i_6_n_0\,
S(0) => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
O => \add_temp_14__230_carry__2_i_1_n_0\
);
\add_temp_14__230_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
O => \add_temp_14__230_carry__2_i_2_n_0\
);
\add_temp_14__230_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
O => \add_temp_14__230_carry__2_i_3_n_0\
);
\add_temp_14__230_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => \add_temp_14__46_carry__2_n_5\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => RESIZE16(14),
I3 => \add_temp_14__0_carry__2_n_4\,
I4 => \add_temp_14__46_carry__2_n_4\,
I5 => RESIZE16(15),
O => \add_temp_14__230_carry__2_i_4_n_0\
);
\add_temp_14__230_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__230_carry__2_i_1_n_0\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => \add_temp_14__46_carry__2_n_5\,
I3 => RESIZE16(14),
O => \add_temp_14__230_carry__2_i_5_n_0\
);
\add_temp_14__230_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
I3 => \add_temp_14__230_carry__2_i_2_n_0\,
O => \add_temp_14__230_carry__2_i_6_n_0\
);
\add_temp_14__230_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
I3 => \add_temp_14__230_carry__2_i_3_n_0\,
O => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
O => \add_temp_14__230_carry_i_1_n_0\
);
\add_temp_14__230_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
O => \add_temp_14__230_carry_i_2_n_0\
);
\add_temp_14__230_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_3_n_0\
);
\add_temp_14__230_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
I3 => \add_temp_14__230_carry_i_1_n_0\,
O => \add_temp_14__230_carry_i_4_n_0\
);
\add_temp_14__230_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
I3 => \add_temp_14__230_carry_i_2_n_0\,
O => \add_temp_14__230_carry_i_5_n_0\
);
\add_temp_14__230_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
I3 => \add_temp_14__230_carry_i_3_n_0\,
O => \add_temp_14__230_carry_i_6_n_0\
);
\add_temp_14__230_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__278_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__278_carry_n_0\,
CO(2) => \add_temp_14__278_carry_n_1\,
CO(1) => \add_temp_14__278_carry_n_2\,
CO(0) => \add_temp_14__278_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry_i_1_n_0\,
DI(2) => \add_temp_14__278_carry_i_2_n_0\,
DI(1) => \add_temp_14__278_carry_i_3_n_0\,
DI(0) => \add_temp_14__92_carry_n_7\,
O(3 downto 0) => filter_sum(3 downto 0),
S(3) => \add_temp_14__278_carry_i_4_n_0\,
S(2) => \add_temp_14__278_carry_i_5_n_0\,
S(1) => \add_temp_14__278_carry_i_6_n_0\,
S(0) => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry_n_0\,
CO(3) => \add_temp_14__278_carry__0_n_0\,
CO(2) => \add_temp_14__278_carry__0_n_1\,
CO(1) => \add_temp_14__278_carry__0_n_2\,
CO(0) => \add_temp_14__278_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__0_i_4_n_0\,
O(3 downto 0) => filter_sum(7 downto 4),
S(3) => \add_temp_14__278_carry__0_i_5_n_0\,
S(2) => \add_temp_14__278_carry__0_i_6_n_0\,
S(1) => \add_temp_14__278_carry__0_i_7_n_0\,
S(0) => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_5\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__278_carry__0_i_9_n_0\,
I4 => \add_temp_14__92_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_1_n_0\
);
\add_temp_14__278_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry__0_n_7\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__138_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_10_n_0\
);
\add_temp_14__278_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry_n_4\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__138_carry_n_4\,
O => \add_temp_14__278_carry__0_i_11_n_0\
);
\add_temp_14__278_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
O => \add_temp_14__278_carry__0_i_12_n_0\
);
\add_temp_14__278_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__230_carry__0_n_6\,
I2 => \add_temp_14__184_carry__0_n_6\,
I3 => \add_temp_14__278_carry__0_i_10_n_0\,
I4 => \add_temp_14__92_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_2_n_0\
);
\add_temp_14__278_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_7\,
I1 => \add_temp_14__230_carry__0_n_7\,
I2 => \add_temp_14__184_carry__0_n_7\,
I3 => \add_temp_14__278_carry__0_i_11_n_0\,
I4 => \add_temp_14__92_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_3_n_0\
);
\add_temp_14__278_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_4\,
I1 => \add_temp_14__230_carry_n_4\,
I2 => \add_temp_14__184_carry_n_4\,
I3 => \add_temp_14__278_carry_i_9_n_0\,
I4 => \add_temp_14__92_carry_n_4\,
O => \add_temp_14__278_carry__0_i_4_n_0\
);
\add_temp_14__278_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__0_i_1_n_0\,
I1 => \add_temp_14__278_carry__0_i_12_n_0\,
I2 => \add_temp_14__92_carry__0_n_4\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__184_carry__0_n_5\,
I5 => \add_temp_14__230_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_5_n_0\
);
\add_temp_14__278_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_2_n_0\,
I1 => \add_temp_14__184_carry__0_n_5\,
I2 => \add_temp_14__230_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__92_carry__0_n_5\,
I5 => \add_temp_14__278_carry__0_i_9_n_0\,
O => \add_temp_14__278_carry__0_i_6_n_0\
);
\add_temp_14__278_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_3_n_0\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
I3 => \add_temp_14__138_carry__0_n_6\,
I4 => \add_temp_14__92_carry__0_n_6\,
I5 => \add_temp_14__278_carry__0_i_10_n_0\,
O => \add_temp_14__278_carry__0_i_7_n_0\
);
\add_temp_14__278_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_4_n_0\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__230_carry__0_n_7\,
I3 => \add_temp_14__138_carry__0_n_7\,
I4 => \add_temp_14__92_carry__0_n_7\,
I5 => \add_temp_14__278_carry__0_i_11_n_0\,
O => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_9_n_0\
);
\add_temp_14__278_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__0_n_0\,
CO(3) => \add_temp_14__278_carry__1_n_0\,
CO(2) => \add_temp_14__278_carry__1_n_1\,
CO(1) => \add_temp_14__278_carry__1_n_2\,
CO(0) => \add_temp_14__278_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__1_i_4_n_0\,
O(3 downto 0) => filter_sum(11 downto 8),
S(3) => \add_temp_14__278_carry__1_i_5_n_0\,
S(2) => \add_temp_14__278_carry__1_i_6_n_0\,
S(1) => \add_temp_14__278_carry__1_i_7_n_0\,
S(0) => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_5\,
I1 => \add_temp_14__230_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__278_carry__1_i_9_n_0\,
I4 => \add_temp_14__92_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_1_n_0\
);
\add_temp_14__278_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_7\,
I1 => \add_temp_14__138_carry__1_n_7\,
I2 => \add_temp_14__230_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_10_n_0\
);
\add_temp_14__278_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_7\,
I1 => \add_temp_14__230_carry__1_n_7\,
I2 => \add_temp_14__184_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_11_n_0\
);
\add_temp_14__278_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_4\,
I1 => \add_temp_14__230_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
O => \add_temp_14__278_carry__1_i_12_n_0\
);
\add_temp_14__278_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__184_carry__1_n_6\,
I3 => \add_temp_14__278_carry__1_i_10_n_0\,
I4 => \add_temp_14__92_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_2_n_0\
);
\add_temp_14__278_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_7\,
I1 => \add_temp_14__138_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__278_carry__1_i_11_n_0\,
O => \add_temp_14__278_carry__1_i_3_n_0\
);
\add_temp_14__278_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__278_carry__0_i_12_n_0\,
O => \add_temp_14__278_carry__1_i_4_n_0\
);
\add_temp_14__278_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_1_n_0\,
I1 => \add_temp_14__278_carry__1_i_12_n_0\,
I2 => \add_temp_14__92_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__184_carry__1_n_5\,
I5 => \add_temp_14__138_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_5_n_0\
);
\add_temp_14__278_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_2_n_0\,
I1 => \add_temp_14__184_carry__1_n_5\,
I2 => \add_temp_14__230_carry__1_n_5\,
I3 => \add_temp_14__138_carry__1_n_5\,
I4 => \add_temp_14__92_carry__1_n_5\,
I5 => \add_temp_14__278_carry__1_i_9_n_0\,
O => \add_temp_14__278_carry__1_i_6_n_0\
);
\add_temp_14__278_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_3_n_0\,
I1 => \add_temp_14__184_carry__1_n_6\,
I2 => \add_temp_14__230_carry__1_n_6\,
I3 => \add_temp_14__138_carry__1_n_6\,
I4 => \add_temp_14__92_carry__1_n_6\,
I5 => \add_temp_14__278_carry__1_i_10_n_0\,
O => \add_temp_14__278_carry__1_i_7_n_0\
);
\add_temp_14__278_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_4_n_0\,
I1 => \add_temp_14__278_carry__1_i_11_n_0\,
I2 => \add_temp_14__92_carry__1_n_7\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__184_carry__0_n_4\,
I5 => \add_temp_14__138_carry__0_n_4\,
O => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__138_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_9_n_0\
);
\add_temp_14__278_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__278_carry__2_n_1\,
CO(1) => \add_temp_14__278_carry__2_n_2\,
CO(0) => \add_temp_14__278_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__278_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__278_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__278_carry__2_i_3_n_0\,
O(3 downto 0) => filter_sum(15 downto 12),
S(3) => \add_temp_14__278_carry__2_i_4_n_0\,
S(2) => \add_temp_14__278_carry__2_i_5_n_0\,
S(1) => \add_temp_14__278_carry__2_i_6_n_0\,
S(0) => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__184_carry__2_n_6\,
I3 => \add_temp_14__278_carry__2_i_8_n_0\,
I4 => \add_temp_14__92_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_1_n_0\
);
\add_temp_14__278_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__138_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_10_n_0\
);
\add_temp_14__278_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_n_4\,
I1 => \add_temp_14__230_carry__2_n_4\,
I2 => \add_temp_14__138_carry__2_n_4\,
I3 => \add_temp_14__92_carry__2_n_4\,
O => \add_temp_14__278_carry__2_i_11_n_0\
);
\add_temp_14__278_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__2_n_7\,
I1 => \add_temp_14__138_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__278_carry__2_i_9_n_0\,
O => \add_temp_14__278_carry__2_i_2_n_0\
);
\add_temp_14__278_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_4\,
I1 => \add_temp_14__138_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__278_carry__1_i_12_n_0\,
O => \add_temp_14__278_carry__2_i_3_n_0\
);
\add_temp_14__278_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E187871E871E1E78"
)
port map (
I0 => \add_temp_14__92_carry__2_n_5\,
I1 => \add_temp_14__278_carry__2_i_10_n_0\,
I2 => \add_temp_14__278_carry__2_i_11_n_0\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__184_carry__2_n_5\,
I5 => \add_temp_14__230_carry__2_n_5\,
O => \add_temp_14__278_carry__2_i_4_n_0\
);
\add_temp_14__278_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_1_n_0\,
I1 => \add_temp_14__184_carry__2_n_5\,
I2 => \add_temp_14__230_carry__2_n_5\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__92_carry__2_n_5\,
I5 => \add_temp_14__278_carry__2_i_10_n_0\,
O => \add_temp_14__278_carry__2_i_5_n_0\
);
\add_temp_14__278_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_2_n_0\,
I1 => \add_temp_14__184_carry__2_n_6\,
I2 => \add_temp_14__230_carry__2_n_6\,
I3 => \add_temp_14__138_carry__2_n_6\,
I4 => \add_temp_14__92_carry__2_n_6\,
I5 => \add_temp_14__278_carry__2_i_8_n_0\,
O => \add_temp_14__278_carry__2_i_6_n_0\
);
\add_temp_14__278_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__2_i_3_n_0\,
I1 => \add_temp_14__278_carry__2_i_9_n_0\,
I2 => \add_temp_14__92_carry__2_n_7\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__184_carry__1_n_4\,
I5 => \add_temp_14__138_carry__1_n_4\,
O => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_7\,
I1 => \add_temp_14__138_carry__2_n_7\,
I2 => \add_temp_14__230_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_8_n_0\
);
\add_temp_14__278_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__2_n_7\,
I1 => \add_temp_14__230_carry__2_n_7\,
I2 => \add_temp_14__184_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_9_n_0\
);
\add_temp_14__278_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
I3 => \add_temp_14__278_carry_i_8_n_0\,
I4 => \add_temp_14__92_carry_n_5\,
O => \add_temp_14__278_carry_i_1_n_0\
);
\add_temp_14__278_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_10_n_0\
);
\add_temp_14__278_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \add_temp_14__278_carry_i_8_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_5\,
I3 => \add_temp_14__230_carry_n_5\,
I4 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_2_n_0\
);
\add_temp_14__278_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_3_n_0\
);
\add_temp_14__278_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry_i_1_n_0\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__230_carry_n_4\,
I3 => \add_temp_14__138_carry_n_4\,
I4 => \add_temp_14__92_carry_n_4\,
I5 => \add_temp_14__278_carry_i_9_n_0\,
O => \add_temp_14__278_carry_i_4_n_0\
);
\add_temp_14__278_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999999699969666"
)
port map (
I0 => \add_temp_14__278_carry_i_10_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__230_carry_n_6\,
I4 => \add_temp_14__184_carry_n_6\,
I5 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_5_n_0\
);
\add_temp_14__278_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"566A"
)
port map (
I0 => \add_temp_14__278_carry_i_3_n_0\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__184_carry_n_7\,
I3 => \add_temp_14__138_carry_n_7\,
O => \add_temp_14__278_carry_i_6_n_0\
);
\add_temp_14__278_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_7\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__138_carry_n_7\,
I3 => \add_temp_14__92_carry_n_7\,
O => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__184_carry_n_6\,
O => \add_temp_14__278_carry_i_8_n_0\
);
\add_temp_14__278_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry_n_5\,
I1 => \add_temp_14__138_carry_n_5\,
I2 => \add_temp_14__230_carry_n_5\,
O => \add_temp_14__278_carry_i_9_n_0\
);
\add_temp_14__46_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__46_carry_n_0\,
CO(2) => \add_temp_14__46_carry_n_1\,
CO(1) => \add_temp_14__46_carry_n_2\,
CO(0) => \add_temp_14__46_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry_i_1_n_0\,
DI(2) => \add_temp_14__46_carry_i_2_n_0\,
DI(1) => \add_temp_14__46_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__46_carry_n_4\,
O(2) => \add_temp_14__46_carry_n_5\,
O(1) => \add_temp_14__46_carry_n_6\,
O(0) => \add_temp_14__46_carry_n_7\,
S(3) => \add_temp_14__46_carry_i_4_n_0\,
S(2) => \add_temp_14__46_carry_i_5_n_0\,
S(1) => \add_temp_14__46_carry_i_6_n_0\,
S(0) => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__46_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry_n_0\,
CO(3) => \add_temp_14__46_carry__0_n_0\,
CO(2) => \add_temp_14__46_carry__0_n_1\,
CO(1) => \add_temp_14__46_carry__0_n_2\,
CO(0) => \add_temp_14__46_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__0_i_4_n_0\,
O(3) => \add_temp_14__46_carry__0_n_4\,
O(2) => \add_temp_14__46_carry__0_n_5\,
O(1) => \add_temp_14__46_carry__0_n_6\,
O(0) => \add_temp_14__46_carry__0_n_7\,
S(3) => \add_temp_14__46_carry__0_i_5_n_0\,
S(2) => \add_temp_14__46_carry__0_i_6_n_0\,
S(1) => \add_temp_14__46_carry__0_i_7_n_0\,
S(0) => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
O => \add_temp_14__46_carry__0_i_1_n_0\
);
\add_temp_14__46_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
O => \add_temp_14__46_carry__0_i_2_n_0\
);
\add_temp_14__46_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
O => \add_temp_14__46_carry__0_i_3_n_0\
);
\add_temp_14__46_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
O => \add_temp_14__46_carry__0_i_4_n_0\
);
\add_temp_14__46_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
I3 => \add_temp_14__46_carry__0_i_1_n_0\,
O => \add_temp_14__46_carry__0_i_5_n_0\
);
\add_temp_14__46_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
I3 => \add_temp_14__46_carry__0_i_2_n_0\,
O => \add_temp_14__46_carry__0_i_6_n_0\
);
\add_temp_14__46_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
I3 => \add_temp_14__46_carry__0_i_3_n_0\,
O => \add_temp_14__46_carry__0_i_7_n_0\
);
\add_temp_14__46_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
I3 => \add_temp_14__46_carry__0_i_4_n_0\,
O => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__0_n_0\,
CO(3) => \add_temp_14__46_carry__1_n_0\,
CO(2) => \add_temp_14__46_carry__1_n_1\,
CO(1) => \add_temp_14__46_carry__1_n_2\,
CO(0) => \add_temp_14__46_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__1_i_4_n_0\,
O(3) => \add_temp_14__46_carry__1_n_4\,
O(2) => \add_temp_14__46_carry__1_n_5\,
O(1) => \add_temp_14__46_carry__1_n_6\,
O(0) => \add_temp_14__46_carry__1_n_7\,
S(3) => \add_temp_14__46_carry__1_i_5_n_0\,
S(2) => \add_temp_14__46_carry__1_i_6_n_0\,
S(1) => \add_temp_14__46_carry__1_i_7_n_0\,
S(0) => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
O => \add_temp_14__46_carry__1_i_1_n_0\
);
\add_temp_14__46_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
O => \add_temp_14__46_carry__1_i_2_n_0\
);
\add_temp_14__46_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
O => \add_temp_14__46_carry__1_i_3_n_0\
);
\add_temp_14__46_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
O => \add_temp_14__46_carry__1_i_4_n_0\
);
\add_temp_14__46_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
I3 => \add_temp_14__46_carry__1_i_1_n_0\,
O => \add_temp_14__46_carry__1_i_5_n_0\
);
\add_temp_14__46_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
I3 => \add_temp_14__46_carry__1_i_2_n_0\,
O => \add_temp_14__46_carry__1_i_6_n_0\
);
\add_temp_14__46_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
I3 => \add_temp_14__46_carry__1_i_3_n_0\,
O => \add_temp_14__46_carry__1_i_7_n_0\
);
\add_temp_14__46_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
I3 => \add_temp_14__46_carry__1_i_4_n_0\,
O => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__46_carry__2_n_1\,
CO(1) => \add_temp_14__46_carry__2_n_2\,
CO(0) => \add_temp_14__46_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__46_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__46_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__46_carry__2_i_3_n_0\,
O(3) => \add_temp_14__46_carry__2_n_4\,
O(2) => \add_temp_14__46_carry__2_n_5\,
O(1) => \add_temp_14__46_carry__2_n_6\,
O(0) => \add_temp_14__46_carry__2_n_7\,
S(3) => \add_temp_14__46_carry__2_i_4_n_0\,
S(2) => \add_temp_14__46_carry__2_i_5_n_0\,
S(1) => \add_temp_14__46_carry__2_i_6_n_0\,
S(0) => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
O => \add_temp_14__46_carry__2_i_1_n_0\
);
\add_temp_14__46_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
O => \add_temp_14__46_carry__2_i_2_n_0\
);
\add_temp_14__46_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
O => \add_temp_14__46_carry__2_i_3_n_0\
);
\add_temp_14__46_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE40(14),
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE38(15),
I4 => RESIZE36(15),
I5 => RESIZE40(15),
O => \add_temp_14__46_carry__2_i_4_n_0\
);
\add_temp_14__46_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry__2_i_1_n_0\,
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE40(14),
O => \add_temp_14__46_carry__2_i_5_n_0\
);
\add_temp_14__46_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
I3 => \add_temp_14__46_carry__2_i_2_n_0\,
O => \add_temp_14__46_carry__2_i_6_n_0\
);
\add_temp_14__46_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
I3 => \add_temp_14__46_carry__2_i_3_n_0\,
O => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
O => \add_temp_14__46_carry_i_1_n_0\
);
\add_temp_14__46_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
O => \add_temp_14__46_carry_i_2_n_0\
);
\add_temp_14__46_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_3_n_0\
);
\add_temp_14__46_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
I3 => \add_temp_14__46_carry_i_1_n_0\,
O => \add_temp_14__46_carry_i_4_n_0\
);
\add_temp_14__46_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
I3 => \add_temp_14__46_carry_i_2_n_0\,
O => \add_temp_14__46_carry_i_5_n_0\
);
\add_temp_14__46_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
I3 => \add_temp_14__46_carry_i_3_n_0\,
O => \add_temp_14__46_carry_i_6_n_0\
);
\add_temp_14__46_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__92_carry_n_0\,
CO(2) => \add_temp_14__92_carry_n_1\,
CO(1) => \add_temp_14__92_carry_n_2\,
CO(0) => \add_temp_14__92_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry_i_1_n_0\,
DI(2) => \add_temp_14__92_carry_i_2_n_0\,
DI(1) => \add_temp_14__92_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__92_carry_n_4\,
O(2) => \add_temp_14__92_carry_n_5\,
O(1) => \add_temp_14__92_carry_n_6\,
O(0) => \add_temp_14__92_carry_n_7\,
S(3) => \add_temp_14__92_carry_i_4_n_0\,
S(2) => \add_temp_14__92_carry_i_5_n_0\,
S(1) => \add_temp_14__92_carry_i_6_n_0\,
S(0) => \add_temp_14__92_carry_i_7_n_0\
);
\add_temp_14__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry_n_0\,
CO(3) => \add_temp_14__92_carry__0_n_0\,
CO(2) => \add_temp_14__92_carry__0_n_1\,
CO(1) => \add_temp_14__92_carry__0_n_2\,
CO(0) => \add_temp_14__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__0_i_4_n_0\,
O(3) => \add_temp_14__92_carry__0_n_4\,
O(2) => \add_temp_14__92_carry__0_n_5\,
O(1) => \add_temp_14__92_carry__0_n_6\,
O(0) => \add_temp_14__92_carry__0_n_7\,
S(3) => \add_temp_14__92_carry__0_i_5_n_0\,
S(2) => \add_temp_14__92_carry__0_i_6_n_0\,
S(1) => \add_temp_14__92_carry__0_i_7_n_0\,
S(0) => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
O => \add_temp_14__92_carry__0_i_1_n_0\
);
\add_temp_14__92_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
O => \add_temp_14__92_carry__0_i_2_n_0\
);
\add_temp_14__92_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
O => \add_temp_14__92_carry__0_i_3_n_0\
);
\add_temp_14__92_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
O => \add_temp_14__92_carry__0_i_4_n_0\
);
\add_temp_14__92_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
I3 => \add_temp_14__92_carry__0_i_1_n_0\,
O => \add_temp_14__92_carry__0_i_5_n_0\
);
\add_temp_14__92_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
I3 => \add_temp_14__92_carry__0_i_2_n_0\,
O => \add_temp_14__92_carry__0_i_6_n_0\
);
\add_temp_14__92_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
I3 => \add_temp_14__92_carry__0_i_3_n_0\,
O => \add_temp_14__92_carry__0_i_7_n_0\
);
\add_temp_14__92_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
I3 => \add_temp_14__92_carry__0_i_4_n_0\,
O => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__0_n_0\,
CO(3) => \add_temp_14__92_carry__1_n_0\,
CO(2) => \add_temp_14__92_carry__1_n_1\,
CO(1) => \add_temp_14__92_carry__1_n_2\,
CO(0) => \add_temp_14__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__1_i_4_n_0\,
O(3) => \add_temp_14__92_carry__1_n_4\,
O(2) => \add_temp_14__92_carry__1_n_5\,
O(1) => \add_temp_14__92_carry__1_n_6\,
O(0) => \add_temp_14__92_carry__1_n_7\,
S(3) => \add_temp_14__92_carry__1_i_5_n_0\,
S(2) => \add_temp_14__92_carry__1_i_6_n_0\,
S(1) => \add_temp_14__92_carry__1_i_7_n_0\,
S(0) => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
O => \add_temp_14__92_carry__1_i_1_n_0\
);
\add_temp_14__92_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
O => \add_temp_14__92_carry__1_i_2_n_0\
);
\add_temp_14__92_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
O => \add_temp_14__92_carry__1_i_3_n_0\
);
\add_temp_14__92_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
O => \add_temp_14__92_carry__1_i_4_n_0\
);
\add_temp_14__92_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
I3 => \add_temp_14__92_carry__1_i_1_n_0\,
O => \add_temp_14__92_carry__1_i_5_n_0\
);
\add_temp_14__92_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
I3 => \add_temp_14__92_carry__1_i_2_n_0\,
O => \add_temp_14__92_carry__1_i_6_n_0\
);
\add_temp_14__92_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
I3 => \add_temp_14__92_carry__1_i_3_n_0\,
O => \add_temp_14__92_carry__1_i_7_n_0\
);
\add_temp_14__92_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
I3 => \add_temp_14__92_carry__1_i_4_n_0\,
O => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__92_carry__2_n_1\,
CO(1) => \add_temp_14__92_carry__2_n_2\,
CO(0) => \add_temp_14__92_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__92_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__92_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__92_carry__2_i_3_n_0\,
O(3) => \add_temp_14__92_carry__2_n_4\,
O(2) => \add_temp_14__92_carry__2_n_5\,
O(1) => \add_temp_14__92_carry__2_n_6\,
O(0) => \add_temp_14__92_carry__2_n_7\,
S(3) => \add_temp_14__92_carry__2_i_4_n_0\,
S(2) => \add_temp_14__92_carry__2_i_5_n_0\,
S(1) => \add_temp_14__92_carry__2_i_6_n_0\,
S(0) => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
O => \add_temp_14__92_carry__2_i_1_n_0\
);
\add_temp_14__92_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
O => \add_temp_14__92_carry__2_i_2_n_0\
);
\add_temp_14__92_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
O => \add_temp_14__92_carry__2_i_3_n_0\
);
\add_temp_14__92_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE34(14),
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE32(15),
I4 => RESIZE30(15),
I5 => RESIZE34(15),
O => \add_temp_14__92_carry__2_i_4_n_0\
);
\add_temp_14__92_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__92_carry__2_i_1_n_0\,
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE34(14),
O => \add_temp_14__92_carry__2_i_5_n_0\
);
\add_temp_14__92_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
I3 => \add_temp_14__92_carry__2_i_2_n_0\,
O => \add_temp_14__92_carry__2_i_6_n_0\
);
\add_temp_14__92_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
I3 => \add_temp_14__92_carry__2_i_3_n_0\,
O => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
O => \add_temp_14__92_carry_i_1_n_0\
);
\add_temp_14__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
O => \add_temp_14__92_carry_i_2_n_0\
);
\add_temp_14__92_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_3_n_0\
);
\add_temp_14__92_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
I3 => \add_temp_14__92_carry_i_1_n_0\,
O => \add_temp_14__92_carry_i_4_n_0\
);
\add_temp_14__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
I3 => \add_temp_14__92_carry_i_2_n_0\,
O => \add_temp_14__92_carry_i_5_n_0\
);
\add_temp_14__92_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
I3 => \add_temp_14__92_carry_i_3_n_0\,
O => \add_temp_14__92_carry_i_6_n_0\
);
\add_temp_14__92_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_7_n_0\
);
\data_pipeline_tmp_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(0),
Q => \data_pipeline_tmp_reg[0]\(0)
);
\data_pipeline_tmp_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(10),
Q => \data_pipeline_tmp_reg[0]\(10)
);
\data_pipeline_tmp_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(11),
Q => \data_pipeline_tmp_reg[0]\(11)
);
\data_pipeline_tmp_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(12),
Q => \data_pipeline_tmp_reg[0]\(12)
);
\data_pipeline_tmp_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(13),
Q => \data_pipeline_tmp_reg[0]\(13)
);
\data_pipeline_tmp_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(14),
Q => \data_pipeline_tmp_reg[0]\(14)
);
\data_pipeline_tmp_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(15),
Q => \data_pipeline_tmp_reg[0]\(15)
);
\data_pipeline_tmp_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(1),
Q => \data_pipeline_tmp_reg[0]\(1)
);
\data_pipeline_tmp_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(2),
Q => \data_pipeline_tmp_reg[0]\(2)
);
\data_pipeline_tmp_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(3),
Q => \data_pipeline_tmp_reg[0]\(3)
);
\data_pipeline_tmp_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(4),
Q => \data_pipeline_tmp_reg[0]\(4)
);
\data_pipeline_tmp_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(5),
Q => \data_pipeline_tmp_reg[0]\(5)
);
\data_pipeline_tmp_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(6),
Q => \data_pipeline_tmp_reg[0]\(6)
);
\data_pipeline_tmp_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(7),
Q => \data_pipeline_tmp_reg[0]\(7)
);
\data_pipeline_tmp_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(8),
Q => \data_pipeline_tmp_reg[0]\(8)
);
\data_pipeline_tmp_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(9),
Q => \data_pipeline_tmp_reg[0]\(9)
);
\data_pipeline_tmp_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(0),
Q => \data_pipeline_tmp_reg[10]\(0)
);
\data_pipeline_tmp_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(10),
Q => \data_pipeline_tmp_reg[10]\(10)
);
\data_pipeline_tmp_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(11),
Q => \data_pipeline_tmp_reg[10]\(11)
);
\data_pipeline_tmp_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(12),
Q => \data_pipeline_tmp_reg[10]\(12)
);
\data_pipeline_tmp_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(13),
Q => \data_pipeline_tmp_reg[10]\(13)
);
\data_pipeline_tmp_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(14),
Q => \data_pipeline_tmp_reg[10]\(14)
);
\data_pipeline_tmp_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(15),
Q => \data_pipeline_tmp_reg[10]\(15)
);
\data_pipeline_tmp_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(1),
Q => \data_pipeline_tmp_reg[10]\(1)
);
\data_pipeline_tmp_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(2),
Q => \data_pipeline_tmp_reg[10]\(2)
);
\data_pipeline_tmp_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(3),
Q => \data_pipeline_tmp_reg[10]\(3)
);
\data_pipeline_tmp_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(4),
Q => \data_pipeline_tmp_reg[10]\(4)
);
\data_pipeline_tmp_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(5),
Q => \data_pipeline_tmp_reg[10]\(5)
);
\data_pipeline_tmp_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(6),
Q => \data_pipeline_tmp_reg[10]\(6)
);
\data_pipeline_tmp_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(7),
Q => \data_pipeline_tmp_reg[10]\(7)
);
\data_pipeline_tmp_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(8),
Q => \data_pipeline_tmp_reg[10]\(8)
);
\data_pipeline_tmp_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(9),
Q => \data_pipeline_tmp_reg[10]\(9)
);
\data_pipeline_tmp_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(0),
Q => \data_pipeline_tmp_reg[11]\(0)
);
\data_pipeline_tmp_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(10),
Q => \data_pipeline_tmp_reg[11]\(10)
);
\data_pipeline_tmp_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(11),
Q => \data_pipeline_tmp_reg[11]\(11)
);
\data_pipeline_tmp_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(12),
Q => \data_pipeline_tmp_reg[11]\(12)
);
\data_pipeline_tmp_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(13),
Q => \data_pipeline_tmp_reg[11]\(13)
);
\data_pipeline_tmp_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(14),
Q => \data_pipeline_tmp_reg[11]\(14)
);
\data_pipeline_tmp_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(15),
Q => \data_pipeline_tmp_reg[11]\(15)
);
\data_pipeline_tmp_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(1),
Q => \data_pipeline_tmp_reg[11]\(1)
);
\data_pipeline_tmp_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(2),
Q => \data_pipeline_tmp_reg[11]\(2)
);
\data_pipeline_tmp_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(3),
Q => \data_pipeline_tmp_reg[11]\(3)
);
\data_pipeline_tmp_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(4),
Q => \data_pipeline_tmp_reg[11]\(4)
);
\data_pipeline_tmp_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(5),
Q => \data_pipeline_tmp_reg[11]\(5)
);
\data_pipeline_tmp_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(6),
Q => \data_pipeline_tmp_reg[11]\(6)
);
\data_pipeline_tmp_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(7),
Q => \data_pipeline_tmp_reg[11]\(7)
);
\data_pipeline_tmp_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(8),
Q => \data_pipeline_tmp_reg[11]\(8)
);
\data_pipeline_tmp_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(9),
Q => \data_pipeline_tmp_reg[11]\(9)
);
\data_pipeline_tmp_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(0),
Q => \data_pipeline_tmp_reg[12]\(0)
);
\data_pipeline_tmp_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(10),
Q => \data_pipeline_tmp_reg[12]\(10)
);
\data_pipeline_tmp_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(11),
Q => \data_pipeline_tmp_reg[12]\(11)
);
\data_pipeline_tmp_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(12),
Q => \data_pipeline_tmp_reg[12]\(12)
);
\data_pipeline_tmp_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(13),
Q => \data_pipeline_tmp_reg[12]\(13)
);
\data_pipeline_tmp_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(14),
Q => \data_pipeline_tmp_reg[12]\(14)
);
\data_pipeline_tmp_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(15),
Q => \data_pipeline_tmp_reg[12]\(15)
);
\data_pipeline_tmp_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(1),
Q => \data_pipeline_tmp_reg[12]\(1)
);
\data_pipeline_tmp_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(2),
Q => \data_pipeline_tmp_reg[12]\(2)
);
\data_pipeline_tmp_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(3),
Q => \data_pipeline_tmp_reg[12]\(3)
);
\data_pipeline_tmp_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(4),
Q => \data_pipeline_tmp_reg[12]\(4)
);
\data_pipeline_tmp_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(5),
Q => \data_pipeline_tmp_reg[12]\(5)
);
\data_pipeline_tmp_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(6),
Q => \data_pipeline_tmp_reg[12]\(6)
);
\data_pipeline_tmp_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(7),
Q => \data_pipeline_tmp_reg[12]\(7)
);
\data_pipeline_tmp_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(8),
Q => \data_pipeline_tmp_reg[12]\(8)
);
\data_pipeline_tmp_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(9),
Q => \data_pipeline_tmp_reg[12]\(9)
);
\data_pipeline_tmp_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(0),
Q => \data_pipeline_tmp_reg[13]\(0)
);
\data_pipeline_tmp_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(10),
Q => \data_pipeline_tmp_reg[13]\(10)
);
\data_pipeline_tmp_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(11),
Q => \data_pipeline_tmp_reg[13]\(11)
);
\data_pipeline_tmp_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(12),
Q => \data_pipeline_tmp_reg[13]\(12)
);
\data_pipeline_tmp_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(13),
Q => \data_pipeline_tmp_reg[13]\(13)
);
\data_pipeline_tmp_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(14),
Q => \data_pipeline_tmp_reg[13]\(14)
);
\data_pipeline_tmp_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(15),
Q => \data_pipeline_tmp_reg[13]\(15)
);
\data_pipeline_tmp_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(1),
Q => \data_pipeline_tmp_reg[13]\(1)
);
\data_pipeline_tmp_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(2),
Q => \data_pipeline_tmp_reg[13]\(2)
);
\data_pipeline_tmp_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(3),
Q => \data_pipeline_tmp_reg[13]\(3)
);
\data_pipeline_tmp_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(4),
Q => \data_pipeline_tmp_reg[13]\(4)
);
\data_pipeline_tmp_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(5),
Q => \data_pipeline_tmp_reg[13]\(5)
);
\data_pipeline_tmp_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(6),
Q => \data_pipeline_tmp_reg[13]\(6)
);
\data_pipeline_tmp_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(7),
Q => \data_pipeline_tmp_reg[13]\(7)
);
\data_pipeline_tmp_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(8),
Q => \data_pipeline_tmp_reg[13]\(8)
);
\data_pipeline_tmp_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(9),
Q => \data_pipeline_tmp_reg[13]\(9)
);
\data_pipeline_tmp_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(0),
Q => \data_pipeline_tmp_reg[14]\(0)
);
\data_pipeline_tmp_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(10),
Q => \data_pipeline_tmp_reg[14]\(10)
);
\data_pipeline_tmp_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(11),
Q => \data_pipeline_tmp_reg[14]\(11)
);
\data_pipeline_tmp_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(12),
Q => \data_pipeline_tmp_reg[14]\(12)
);
\data_pipeline_tmp_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(13),
Q => \data_pipeline_tmp_reg[14]\(13)
);
\data_pipeline_tmp_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(14),
Q => \data_pipeline_tmp_reg[14]\(14)
);
\data_pipeline_tmp_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(15),
Q => \data_pipeline_tmp_reg[14]\(15)
);
\data_pipeline_tmp_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(1),
Q => \data_pipeline_tmp_reg[14]\(1)
);
\data_pipeline_tmp_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(2),
Q => \data_pipeline_tmp_reg[14]\(2)
);
\data_pipeline_tmp_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(3),
Q => \data_pipeline_tmp_reg[14]\(3)
);
\data_pipeline_tmp_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(4),
Q => \data_pipeline_tmp_reg[14]\(4)
);
\data_pipeline_tmp_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(5),
Q => \data_pipeline_tmp_reg[14]\(5)
);
\data_pipeline_tmp_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(6),
Q => \data_pipeline_tmp_reg[14]\(6)
);
\data_pipeline_tmp_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(7),
Q => \data_pipeline_tmp_reg[14]\(7)
);
\data_pipeline_tmp_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(8),
Q => \data_pipeline_tmp_reg[14]\(8)
);
\data_pipeline_tmp_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(9),
Q => \data_pipeline_tmp_reg[14]\(9)
);
\data_pipeline_tmp_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(0),
Q => \data_pipeline_tmp_reg[1]\(0)
);
\data_pipeline_tmp_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(10),
Q => \data_pipeline_tmp_reg[1]\(10)
);
\data_pipeline_tmp_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(11),
Q => \data_pipeline_tmp_reg[1]\(11)
);
\data_pipeline_tmp_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(12),
Q => \data_pipeline_tmp_reg[1]\(12)
);
\data_pipeline_tmp_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(13),
Q => \data_pipeline_tmp_reg[1]\(13)
);
\data_pipeline_tmp_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(14),
Q => \data_pipeline_tmp_reg[1]\(14)
);
\data_pipeline_tmp_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(15),
Q => \data_pipeline_tmp_reg[1]\(15)
);
\data_pipeline_tmp_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(1),
Q => \data_pipeline_tmp_reg[1]\(1)
);
\data_pipeline_tmp_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(2),
Q => \data_pipeline_tmp_reg[1]\(2)
);
\data_pipeline_tmp_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(3),
Q => \data_pipeline_tmp_reg[1]\(3)
);
\data_pipeline_tmp_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(4),
Q => \data_pipeline_tmp_reg[1]\(4)
);
\data_pipeline_tmp_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(5),
Q => \data_pipeline_tmp_reg[1]\(5)
);
\data_pipeline_tmp_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(6),
Q => \data_pipeline_tmp_reg[1]\(6)
);
\data_pipeline_tmp_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(7),
Q => \data_pipeline_tmp_reg[1]\(7)
);
\data_pipeline_tmp_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(8),
Q => \data_pipeline_tmp_reg[1]\(8)
);
\data_pipeline_tmp_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(9),
Q => \data_pipeline_tmp_reg[1]\(9)
);
\data_pipeline_tmp_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(0),
Q => \data_pipeline_tmp_reg[2]\(0)
);
\data_pipeline_tmp_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(10),
Q => \data_pipeline_tmp_reg[2]\(10)
);
\data_pipeline_tmp_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(11),
Q => \data_pipeline_tmp_reg[2]\(11)
);
\data_pipeline_tmp_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(12),
Q => \data_pipeline_tmp_reg[2]\(12)
);
\data_pipeline_tmp_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(13),
Q => \data_pipeline_tmp_reg[2]\(13)
);
\data_pipeline_tmp_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(14),
Q => \data_pipeline_tmp_reg[2]\(14)
);
\data_pipeline_tmp_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(15),
Q => \data_pipeline_tmp_reg[2]\(15)
);
\data_pipeline_tmp_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(1),
Q => \data_pipeline_tmp_reg[2]\(1)
);
\data_pipeline_tmp_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(2),
Q => \data_pipeline_tmp_reg[2]\(2)
);
\data_pipeline_tmp_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(3),
Q => \data_pipeline_tmp_reg[2]\(3)
);
\data_pipeline_tmp_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(4),
Q => \data_pipeline_tmp_reg[2]\(4)
);
\data_pipeline_tmp_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(5),
Q => \data_pipeline_tmp_reg[2]\(5)
);
\data_pipeline_tmp_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(6),
Q => \data_pipeline_tmp_reg[2]\(6)
);
\data_pipeline_tmp_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(7),
Q => \data_pipeline_tmp_reg[2]\(7)
);
\data_pipeline_tmp_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(8),
Q => \data_pipeline_tmp_reg[2]\(8)
);
\data_pipeline_tmp_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(9),
Q => \data_pipeline_tmp_reg[2]\(9)
);
\data_pipeline_tmp_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(0),
Q => \data_pipeline_tmp_reg[3]\(0)
);
\data_pipeline_tmp_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(10),
Q => \data_pipeline_tmp_reg[3]\(10)
);
\data_pipeline_tmp_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(11),
Q => \data_pipeline_tmp_reg[3]\(11)
);
\data_pipeline_tmp_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(12),
Q => \data_pipeline_tmp_reg[3]\(12)
);
\data_pipeline_tmp_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(13),
Q => \data_pipeline_tmp_reg[3]\(13)
);
\data_pipeline_tmp_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(14),
Q => \data_pipeline_tmp_reg[3]\(14)
);
\data_pipeline_tmp_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(15),
Q => \data_pipeline_tmp_reg[3]\(15)
);
\data_pipeline_tmp_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(1),
Q => \data_pipeline_tmp_reg[3]\(1)
);
\data_pipeline_tmp_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(2),
Q => \data_pipeline_tmp_reg[3]\(2)
);
\data_pipeline_tmp_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(3),
Q => \data_pipeline_tmp_reg[3]\(3)
);
\data_pipeline_tmp_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(4),
Q => \data_pipeline_tmp_reg[3]\(4)
);
\data_pipeline_tmp_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(5),
Q => \data_pipeline_tmp_reg[3]\(5)
);
\data_pipeline_tmp_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(6),
Q => \data_pipeline_tmp_reg[3]\(6)
);
\data_pipeline_tmp_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(7),
Q => \data_pipeline_tmp_reg[3]\(7)
);
\data_pipeline_tmp_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(8),
Q => \data_pipeline_tmp_reg[3]\(8)
);
\data_pipeline_tmp_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(9),
Q => \data_pipeline_tmp_reg[3]\(9)
);
\data_pipeline_tmp_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(0),
Q => \data_pipeline_tmp_reg[4]\(0)
);
\data_pipeline_tmp_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(10),
Q => \data_pipeline_tmp_reg[4]\(10)
);
\data_pipeline_tmp_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(11),
Q => \data_pipeline_tmp_reg[4]\(11)
);
\data_pipeline_tmp_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(12),
Q => \data_pipeline_tmp_reg[4]\(12)
);
\data_pipeline_tmp_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(13),
Q => \data_pipeline_tmp_reg[4]\(13)
);
\data_pipeline_tmp_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(14),
Q => \data_pipeline_tmp_reg[4]\(14)
);
\data_pipeline_tmp_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(15),
Q => \data_pipeline_tmp_reg[4]\(15)
);
\data_pipeline_tmp_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(1),
Q => \data_pipeline_tmp_reg[4]\(1)
);
\data_pipeline_tmp_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(2),
Q => \data_pipeline_tmp_reg[4]\(2)
);
\data_pipeline_tmp_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(3),
Q => \data_pipeline_tmp_reg[4]\(3)
);
\data_pipeline_tmp_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(4),
Q => \data_pipeline_tmp_reg[4]\(4)
);
\data_pipeline_tmp_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(5),
Q => \data_pipeline_tmp_reg[4]\(5)
);
\data_pipeline_tmp_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(6),
Q => \data_pipeline_tmp_reg[4]\(6)
);
\data_pipeline_tmp_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(7),
Q => \data_pipeline_tmp_reg[4]\(7)
);
\data_pipeline_tmp_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(8),
Q => \data_pipeline_tmp_reg[4]\(8)
);
\data_pipeline_tmp_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(9),
Q => \data_pipeline_tmp_reg[4]\(9)
);
\data_pipeline_tmp_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(0),
Q => \data_pipeline_tmp_reg[5]\(0)
);
\data_pipeline_tmp_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(10),
Q => \data_pipeline_tmp_reg[5]\(10)
);
\data_pipeline_tmp_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(11),
Q => \data_pipeline_tmp_reg[5]\(11)
);
\data_pipeline_tmp_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(12),
Q => \data_pipeline_tmp_reg[5]\(12)
);
\data_pipeline_tmp_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(13),
Q => \data_pipeline_tmp_reg[5]\(13)
);
\data_pipeline_tmp_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(14),
Q => \data_pipeline_tmp_reg[5]\(14)
);
\data_pipeline_tmp_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(15),
Q => \data_pipeline_tmp_reg[5]\(15)
);
\data_pipeline_tmp_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(1),
Q => \data_pipeline_tmp_reg[5]\(1)
);
\data_pipeline_tmp_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(2),
Q => \data_pipeline_tmp_reg[5]\(2)
);
\data_pipeline_tmp_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(3),
Q => \data_pipeline_tmp_reg[5]\(3)
);
\data_pipeline_tmp_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(4),
Q => \data_pipeline_tmp_reg[5]\(4)
);
\data_pipeline_tmp_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(5),
Q => \data_pipeline_tmp_reg[5]\(5)
);
\data_pipeline_tmp_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(6),
Q => \data_pipeline_tmp_reg[5]\(6)
);
\data_pipeline_tmp_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(7),
Q => \data_pipeline_tmp_reg[5]\(7)
);
\data_pipeline_tmp_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(8),
Q => \data_pipeline_tmp_reg[5]\(8)
);
\data_pipeline_tmp_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(9),
Q => \data_pipeline_tmp_reg[5]\(9)
);
\data_pipeline_tmp_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(0),
Q => \data_pipeline_tmp_reg[6]\(0)
);
\data_pipeline_tmp_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(10),
Q => \data_pipeline_tmp_reg[6]\(10)
);
\data_pipeline_tmp_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(11),
Q => \data_pipeline_tmp_reg[6]\(11)
);
\data_pipeline_tmp_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(12),
Q => \data_pipeline_tmp_reg[6]\(12)
);
\data_pipeline_tmp_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(13),
Q => \data_pipeline_tmp_reg[6]\(13)
);
\data_pipeline_tmp_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(14),
Q => \data_pipeline_tmp_reg[6]\(14)
);
\data_pipeline_tmp_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(15),
Q => \data_pipeline_tmp_reg[6]\(15)
);
\data_pipeline_tmp_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(1),
Q => \data_pipeline_tmp_reg[6]\(1)
);
\data_pipeline_tmp_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(2),
Q => \data_pipeline_tmp_reg[6]\(2)
);
\data_pipeline_tmp_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(3),
Q => \data_pipeline_tmp_reg[6]\(3)
);
\data_pipeline_tmp_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(4),
Q => \data_pipeline_tmp_reg[6]\(4)
);
\data_pipeline_tmp_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(5),
Q => \data_pipeline_tmp_reg[6]\(5)
);
\data_pipeline_tmp_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(6),
Q => \data_pipeline_tmp_reg[6]\(6)
);
\data_pipeline_tmp_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(7),
Q => \data_pipeline_tmp_reg[6]\(7)
);
\data_pipeline_tmp_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(8),
Q => \data_pipeline_tmp_reg[6]\(8)
);
\data_pipeline_tmp_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(9),
Q => \data_pipeline_tmp_reg[6]\(9)
);
\data_pipeline_tmp_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(0),
Q => \data_pipeline_tmp_reg[7]\(0)
);
\data_pipeline_tmp_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(10),
Q => \data_pipeline_tmp_reg[7]\(10)
);
\data_pipeline_tmp_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(11),
Q => \data_pipeline_tmp_reg[7]\(11)
);
\data_pipeline_tmp_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(12),
Q => \data_pipeline_tmp_reg[7]\(12)
);
\data_pipeline_tmp_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(13),
Q => \data_pipeline_tmp_reg[7]\(13)
);
\data_pipeline_tmp_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(14),
Q => \data_pipeline_tmp_reg[7]\(14)
);
\data_pipeline_tmp_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(15),
Q => \data_pipeline_tmp_reg[7]\(15)
);
\data_pipeline_tmp_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(1),
Q => \data_pipeline_tmp_reg[7]\(1)
);
\data_pipeline_tmp_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(2),
Q => \data_pipeline_tmp_reg[7]\(2)
);
\data_pipeline_tmp_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(3),
Q => \data_pipeline_tmp_reg[7]\(3)
);
\data_pipeline_tmp_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(4),
Q => \data_pipeline_tmp_reg[7]\(4)
);
\data_pipeline_tmp_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(5),
Q => \data_pipeline_tmp_reg[7]\(5)
);
\data_pipeline_tmp_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(6),
Q => \data_pipeline_tmp_reg[7]\(6)
);
\data_pipeline_tmp_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(7),
Q => \data_pipeline_tmp_reg[7]\(7)
);
\data_pipeline_tmp_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(8),
Q => \data_pipeline_tmp_reg[7]\(8)
);
\data_pipeline_tmp_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(9),
Q => \data_pipeline_tmp_reg[7]\(9)
);
\data_pipeline_tmp_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(0),
Q => \data_pipeline_tmp_reg[8]\(0)
);
\data_pipeline_tmp_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(10),
Q => \data_pipeline_tmp_reg[8]\(10)
);
\data_pipeline_tmp_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(11),
Q => \data_pipeline_tmp_reg[8]\(11)
);
\data_pipeline_tmp_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(12),
Q => \data_pipeline_tmp_reg[8]\(12)
);
\data_pipeline_tmp_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(13),
Q => \data_pipeline_tmp_reg[8]\(13)
);
\data_pipeline_tmp_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(14),
Q => \data_pipeline_tmp_reg[8]\(14)
);
\data_pipeline_tmp_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(15),
Q => \data_pipeline_tmp_reg[8]\(15)
);
\data_pipeline_tmp_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(1),
Q => \data_pipeline_tmp_reg[8]\(1)
);
\data_pipeline_tmp_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(2),
Q => \data_pipeline_tmp_reg[8]\(2)
);
\data_pipeline_tmp_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(3),
Q => \data_pipeline_tmp_reg[8]\(3)
);
\data_pipeline_tmp_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(4),
Q => \data_pipeline_tmp_reg[8]\(4)
);
\data_pipeline_tmp_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(5),
Q => \data_pipeline_tmp_reg[8]\(5)
);
\data_pipeline_tmp_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(6),
Q => \data_pipeline_tmp_reg[8]\(6)
);
\data_pipeline_tmp_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(7),
Q => \data_pipeline_tmp_reg[8]\(7)
);
\data_pipeline_tmp_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(8),
Q => \data_pipeline_tmp_reg[8]\(8)
);
\data_pipeline_tmp_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(9),
Q => \data_pipeline_tmp_reg[8]\(9)
);
\data_pipeline_tmp_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(0),
Q => \data_pipeline_tmp_reg[9]\(0)
);
\data_pipeline_tmp_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(10),
Q => \data_pipeline_tmp_reg[9]\(10)
);
\data_pipeline_tmp_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(11),
Q => \data_pipeline_tmp_reg[9]\(11)
);
\data_pipeline_tmp_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(12),
Q => \data_pipeline_tmp_reg[9]\(12)
);
\data_pipeline_tmp_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(13),
Q => \data_pipeline_tmp_reg[9]\(13)
);
\data_pipeline_tmp_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(14),
Q => \data_pipeline_tmp_reg[9]\(14)
);
\data_pipeline_tmp_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(15),
Q => \data_pipeline_tmp_reg[9]\(15)
);
\data_pipeline_tmp_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(1),
Q => \data_pipeline_tmp_reg[9]\(1)
);
\data_pipeline_tmp_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(2),
Q => \data_pipeline_tmp_reg[9]\(2)
);
\data_pipeline_tmp_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(3),
Q => \data_pipeline_tmp_reg[9]\(3)
);
\data_pipeline_tmp_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(4),
Q => \data_pipeline_tmp_reg[9]\(4)
);
\data_pipeline_tmp_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(5),
Q => \data_pipeline_tmp_reg[9]\(5)
);
\data_pipeline_tmp_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(6),
Q => \data_pipeline_tmp_reg[9]\(6)
);
\data_pipeline_tmp_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(7),
Q => \data_pipeline_tmp_reg[9]\(7)
);
\data_pipeline_tmp_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(8),
Q => \data_pipeline_tmp_reg[9]\(8)
);
\data_pipeline_tmp_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(9),
Q => \data_pipeline_tmp_reg[9]\(9)
);
mul_temp: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_n_74,
P(30) => mul_temp_n_75,
P(29) => mul_temp_n_76,
P(28) => mul_temp_n_77,
P(27) => mul_temp_n_78,
P(26) => mul_temp_n_79,
P(25) => mul_temp_n_80,
P(24) => mul_temp_n_81,
P(23) => mul_temp_n_82,
P(22) => mul_temp_n_83,
P(21) => mul_temp_n_84,
P(20) => mul_temp_n_85,
P(19) => mul_temp_n_86,
P(18) => mul_temp_n_87,
P(17) => mul_temp_n_88,
P(16) => mul_temp_n_89,
P(15) => mul_temp_n_90,
P(14) => \^mul_temp\(14),
P(13) => mul_temp_n_92,
P(12) => mul_temp_n_93,
P(11) => mul_temp_n_94,
P(10) => mul_temp_n_95,
P(9) => mul_temp_n_96,
P(8) => mul_temp_n_97,
P(7) => mul_temp_n_98,
P(6) => mul_temp_n_99,
P(5) => mul_temp_n_100,
P(4) => mul_temp_n_101,
P(3) => mul_temp_n_102,
P(2) => mul_temp_n_103,
P(1) => mul_temp_n_104,
P(0) => mul_temp_n_105,
PATTERNBDETECT => NLW_mul_temp_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_UNDERFLOW_UNCONNECTED
);
mul_temp_1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_1_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_1_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_1_n_74,
P(30) => mul_temp_1_n_75,
P(29) => mul_temp_1_n_76,
P(28) => mul_temp_1_n_77,
P(27) => mul_temp_1_n_78,
P(26) => mul_temp_1_n_79,
P(25) => mul_temp_1_n_80,
P(24) => mul_temp_1_n_81,
P(23) => mul_temp_1_n_82,
P(22) => mul_temp_1_n_83,
P(21) => mul_temp_1_n_84,
P(20) => mul_temp_1_n_85,
P(19) => mul_temp_1_n_86,
P(18) => mul_temp_1_n_87,
P(17) => mul_temp_1_n_88,
P(16) => mul_temp_1_n_89,
P(15) => mul_temp_1_n_90,
P(14) => \^mul_temp_1\(14),
P(13) => mul_temp_1_n_92,
P(12) => mul_temp_1_n_93,
P(11) => mul_temp_1_n_94,
P(10) => mul_temp_1_n_95,
P(9) => mul_temp_1_n_96,
P(8) => mul_temp_1_n_97,
P(7) => mul_temp_1_n_98,
P(6) => mul_temp_1_n_99,
P(5) => mul_temp_1_n_100,
P(4) => mul_temp_1_n_101,
P(3) => mul_temp_1_n_102,
P(2) => mul_temp_1_n_103,
P(1) => mul_temp_1_n_104,
P(0) => mul_temp_1_n_105,
PATTERNBDETECT => NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_1_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_1_UNDERFLOW_UNCONNECTED
);
mul_temp_10: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_10_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_10_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_10_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_10_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_10_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_10_n_74,
P(30) => mul_temp_10_n_75,
P(29) => mul_temp_10_n_76,
P(28) => mul_temp_10_n_77,
P(27) => mul_temp_10_n_78,
P(26) => mul_temp_10_n_79,
P(25) => mul_temp_10_n_80,
P(24) => mul_temp_10_n_81,
P(23) => mul_temp_10_n_82,
P(22) => mul_temp_10_n_83,
P(21) => mul_temp_10_n_84,
P(20) => mul_temp_10_n_85,
P(19) => mul_temp_10_n_86,
P(18) => mul_temp_10_n_87,
P(17) => mul_temp_10_n_88,
P(16) => mul_temp_10_n_89,
P(15) => mul_temp_10_n_90,
P(14) => \^mul_temp_10\(14),
P(13) => mul_temp_10_n_92,
P(12) => mul_temp_10_n_93,
P(11) => mul_temp_10_n_94,
P(10) => mul_temp_10_n_95,
P(9) => mul_temp_10_n_96,
P(8) => mul_temp_10_n_97,
P(7) => mul_temp_10_n_98,
P(6) => mul_temp_10_n_99,
P(5) => mul_temp_10_n_100,
P(4) => mul_temp_10_n_101,
P(3) => mul_temp_10_n_102,
P(2) => mul_temp_10_n_103,
P(1) => mul_temp_10_n_104,
P(0) => mul_temp_10_n_105,
PATTERNBDETECT => NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_10_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_10_UNDERFLOW_UNCONNECTED
);
mul_temp_11: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_11_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_11_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_11_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_11_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_11_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_11_n_74,
P(30) => mul_temp_11_n_75,
P(29) => mul_temp_11_n_76,
P(28) => mul_temp_11_n_77,
P(27) => mul_temp_11_n_78,
P(26) => mul_temp_11_n_79,
P(25) => mul_temp_11_n_80,
P(24) => mul_temp_11_n_81,
P(23) => mul_temp_11_n_82,
P(22) => mul_temp_11_n_83,
P(21) => mul_temp_11_n_84,
P(20) => mul_temp_11_n_85,
P(19) => mul_temp_11_n_86,
P(18) => mul_temp_11_n_87,
P(17) => mul_temp_11_n_88,
P(16) => mul_temp_11_n_89,
P(15) => mul_temp_11_n_90,
P(14) => \^mul_temp_11\(14),
P(13) => mul_temp_11_n_92,
P(12) => mul_temp_11_n_93,
P(11) => mul_temp_11_n_94,
P(10) => mul_temp_11_n_95,
P(9) => mul_temp_11_n_96,
P(8) => mul_temp_11_n_97,
P(7) => mul_temp_11_n_98,
P(6) => mul_temp_11_n_99,
P(5) => mul_temp_11_n_100,
P(4) => mul_temp_11_n_101,
P(3) => mul_temp_11_n_102,
P(2) => mul_temp_11_n_103,
P(1) => mul_temp_11_n_104,
P(0) => mul_temp_11_n_105,
PATTERNBDETECT => NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_11_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_11_UNDERFLOW_UNCONNECTED
);
mul_temp_12: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_12_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_12_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_12_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_12_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_12_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_12_n_74,
P(30) => mul_temp_12_n_75,
P(29) => mul_temp_12_n_76,
P(28) => mul_temp_12_n_77,
P(27) => mul_temp_12_n_78,
P(26) => mul_temp_12_n_79,
P(25) => mul_temp_12_n_80,
P(24) => mul_temp_12_n_81,
P(23) => mul_temp_12_n_82,
P(22) => mul_temp_12_n_83,
P(21) => mul_temp_12_n_84,
P(20) => mul_temp_12_n_85,
P(19) => mul_temp_12_n_86,
P(18) => mul_temp_12_n_87,
P(17) => mul_temp_12_n_88,
P(16) => mul_temp_12_n_89,
P(15) => mul_temp_12_n_90,
P(14) => \^mul_temp_12\(14),
P(13) => mul_temp_12_n_92,
P(12) => mul_temp_12_n_93,
P(11) => mul_temp_12_n_94,
P(10) => mul_temp_12_n_95,
P(9) => mul_temp_12_n_96,
P(8) => mul_temp_12_n_97,
P(7) => mul_temp_12_n_98,
P(6) => mul_temp_12_n_99,
P(5) => mul_temp_12_n_100,
P(4) => mul_temp_12_n_101,
P(3) => mul_temp_12_n_102,
P(2) => mul_temp_12_n_103,
P(1) => mul_temp_12_n_104,
P(0) => mul_temp_12_n_105,
PATTERNBDETECT => NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_12_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_12_UNDERFLOW_UNCONNECTED
);
mul_temp_13: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_13_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_13_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_13_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_13_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_13_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_13_n_74,
P(30) => mul_temp_13_n_75,
P(29) => mul_temp_13_n_76,
P(28) => mul_temp_13_n_77,
P(27) => mul_temp_13_n_78,
P(26) => mul_temp_13_n_79,
P(25) => mul_temp_13_n_80,
P(24) => mul_temp_13_n_81,
P(23) => mul_temp_13_n_82,
P(22) => mul_temp_13_n_83,
P(21) => mul_temp_13_n_84,
P(20) => mul_temp_13_n_85,
P(19) => mul_temp_13_n_86,
P(18) => mul_temp_13_n_87,
P(17) => mul_temp_13_n_88,
P(16) => mul_temp_13_n_89,
P(15) => mul_temp_13_n_90,
P(14) => \^mul_temp_13\(14),
P(13) => mul_temp_13_n_92,
P(12) => mul_temp_13_n_93,
P(11) => mul_temp_13_n_94,
P(10) => mul_temp_13_n_95,
P(9) => mul_temp_13_n_96,
P(8) => mul_temp_13_n_97,
P(7) => mul_temp_13_n_98,
P(6) => mul_temp_13_n_99,
P(5) => mul_temp_13_n_100,
P(4) => mul_temp_13_n_101,
P(3) => mul_temp_13_n_102,
P(2) => mul_temp_13_n_103,
P(1) => mul_temp_13_n_104,
P(0) => mul_temp_13_n_105,
PATTERNBDETECT => NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_13_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_13_UNDERFLOW_UNCONNECTED
);
mul_temp_14: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_14_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_14_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_14_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_14_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_14_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_14_n_74,
P(30) => mul_temp_14_n_75,
P(29) => mul_temp_14_n_76,
P(28) => mul_temp_14_n_77,
P(27) => mul_temp_14_n_78,
P(26) => mul_temp_14_n_79,
P(25) => mul_temp_14_n_80,
P(24) => mul_temp_14_n_81,
P(23) => mul_temp_14_n_82,
P(22) => mul_temp_14_n_83,
P(21) => mul_temp_14_n_84,
P(20) => mul_temp_14_n_85,
P(19) => mul_temp_14_n_86,
P(18) => mul_temp_14_n_87,
P(17) => mul_temp_14_n_88,
P(16) => mul_temp_14_n_89,
P(15) => mul_temp_14_n_90,
P(14) => \^mul_temp_14\(14),
P(13) => mul_temp_14_n_92,
P(12) => mul_temp_14_n_93,
P(11) => mul_temp_14_n_94,
P(10) => mul_temp_14_n_95,
P(9) => mul_temp_14_n_96,
P(8) => mul_temp_14_n_97,
P(7) => mul_temp_14_n_98,
P(6) => mul_temp_14_n_99,
P(5) => mul_temp_14_n_100,
P(4) => mul_temp_14_n_101,
P(3) => mul_temp_14_n_102,
P(2) => mul_temp_14_n_103,
P(1) => mul_temp_14_n_104,
P(0) => mul_temp_14_n_105,
PATTERNBDETECT => NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_14_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_14_UNDERFLOW_UNCONNECTED
);
mul_temp_15: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_15_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_15_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_15_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_15_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_15_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_15_n_74,
P(30) => mul_temp_15_n_75,
P(29) => mul_temp_15_n_76,
P(28) => mul_temp_15_n_77,
P(27) => mul_temp_15_n_78,
P(26) => mul_temp_15_n_79,
P(25) => mul_temp_15_n_80,
P(24) => mul_temp_15_n_81,
P(23) => mul_temp_15_n_82,
P(22) => mul_temp_15_n_83,
P(21) => mul_temp_15_n_84,
P(20) => mul_temp_15_n_85,
P(19) => mul_temp_15_n_86,
P(18) => mul_temp_15_n_87,
P(17) => mul_temp_15_n_88,
P(16) => mul_temp_15_n_89,
P(15) => mul_temp_15_n_90,
P(14) => \^mul_temp_15\(14),
P(13) => mul_temp_15_n_92,
P(12) => mul_temp_15_n_93,
P(11) => mul_temp_15_n_94,
P(10) => mul_temp_15_n_95,
P(9) => mul_temp_15_n_96,
P(8) => mul_temp_15_n_97,
P(7) => mul_temp_15_n_98,
P(6) => mul_temp_15_n_99,
P(5) => mul_temp_15_n_100,
P(4) => mul_temp_15_n_101,
P(3) => mul_temp_15_n_102,
P(2) => mul_temp_15_n_103,
P(1) => mul_temp_15_n_104,
P(0) => mul_temp_15_n_105,
PATTERNBDETECT => NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_15_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_15_UNDERFLOW_UNCONNECTED
);
mul_temp_17: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_17_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_17_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_17_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_17_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_17_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_17_n_74,
P(30) => mul_temp_17_n_75,
P(29) => mul_temp_17_n_76,
P(28) => mul_temp_17_n_77,
P(27) => mul_temp_17_n_78,
P(26) => mul_temp_17_n_79,
P(25) => mul_temp_17_n_80,
P(24) => mul_temp_17_n_81,
P(23) => mul_temp_17_n_82,
P(22) => mul_temp_17_n_83,
P(21) => mul_temp_17_n_84,
P(20) => mul_temp_17_n_85,
P(19) => mul_temp_17_n_86,
P(18) => mul_temp_17_n_87,
P(17) => mul_temp_17_n_88,
P(16) => mul_temp_17_n_89,
P(15) => mul_temp_17_n_90,
P(14) => \^mul_temp_17\(14),
P(13) => mul_temp_17_n_92,
P(12) => mul_temp_17_n_93,
P(11) => mul_temp_17_n_94,
P(10) => mul_temp_17_n_95,
P(9) => mul_temp_17_n_96,
P(8) => mul_temp_17_n_97,
P(7) => mul_temp_17_n_98,
P(6) => mul_temp_17_n_99,
P(5) => mul_temp_17_n_100,
P(4) => mul_temp_17_n_101,
P(3) => mul_temp_17_n_102,
P(2) => mul_temp_17_n_103,
P(1) => mul_temp_17_n_104,
P(0) => mul_temp_17_n_105,
PATTERNBDETECT => NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_17_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_17_UNDERFLOW_UNCONNECTED
);
mul_temp_18: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_18_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_18_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_18_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_18_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_18_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_18_n_74,
P(30) => mul_temp_18_n_75,
P(29) => mul_temp_18_n_76,
P(28) => mul_temp_18_n_77,
P(27) => mul_temp_18_n_78,
P(26) => mul_temp_18_n_79,
P(25) => mul_temp_18_n_80,
P(24) => mul_temp_18_n_81,
P(23) => mul_temp_18_n_82,
P(22) => mul_temp_18_n_83,
P(21) => mul_temp_18_n_84,
P(20) => mul_temp_18_n_85,
P(19) => mul_temp_18_n_86,
P(18) => mul_temp_18_n_87,
P(17) => mul_temp_18_n_88,
P(16) => mul_temp_18_n_89,
P(15) => mul_temp_18_n_90,
P(14) => \^mul_temp_18\(14),
P(13) => mul_temp_18_n_92,
P(12) => mul_temp_18_n_93,
P(11) => mul_temp_18_n_94,
P(10) => mul_temp_18_n_95,
P(9) => mul_temp_18_n_96,
P(8) => mul_temp_18_n_97,
P(7) => mul_temp_18_n_98,
P(6) => mul_temp_18_n_99,
P(5) => mul_temp_18_n_100,
P(4) => mul_temp_18_n_101,
P(3) => mul_temp_18_n_102,
P(2) => mul_temp_18_n_103,
P(1) => mul_temp_18_n_104,
P(0) => mul_temp_18_n_105,
PATTERNBDETECT => NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_18_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_18_UNDERFLOW_UNCONNECTED
);
mul_temp_19: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_19_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_19_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_19_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_19_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_19_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_19_n_74,
P(30) => mul_temp_19_n_75,
P(29) => mul_temp_19_n_76,
P(28) => mul_temp_19_n_77,
P(27) => mul_temp_19_n_78,
P(26) => mul_temp_19_n_79,
P(25) => mul_temp_19_n_80,
P(24) => mul_temp_19_n_81,
P(23) => mul_temp_19_n_82,
P(22) => mul_temp_19_n_83,
P(21) => mul_temp_19_n_84,
P(20) => mul_temp_19_n_85,
P(19) => mul_temp_19_n_86,
P(18) => mul_temp_19_n_87,
P(17) => mul_temp_19_n_88,
P(16) => mul_temp_19_n_89,
P(15) => mul_temp_19_n_90,
P(14) => \^mul_temp_19\(14),
P(13) => mul_temp_19_n_92,
P(12) => mul_temp_19_n_93,
P(11) => mul_temp_19_n_94,
P(10) => mul_temp_19_n_95,
P(9) => mul_temp_19_n_96,
P(8) => mul_temp_19_n_97,
P(7) => mul_temp_19_n_98,
P(6) => mul_temp_19_n_99,
P(5) => mul_temp_19_n_100,
P(4) => mul_temp_19_n_101,
P(3) => mul_temp_19_n_102,
P(2) => mul_temp_19_n_103,
P(1) => mul_temp_19_n_104,
P(0) => mul_temp_19_n_105,
PATTERNBDETECT => NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_19_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_19_UNDERFLOW_UNCONNECTED
);
mul_temp_2: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_2_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_2_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_2_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_2_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_2_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_2_n_74,
P(30) => mul_temp_2_n_75,
P(29) => mul_temp_2_n_76,
P(28) => mul_temp_2_n_77,
P(27) => mul_temp_2_n_78,
P(26) => mul_temp_2_n_79,
P(25) => mul_temp_2_n_80,
P(24) => mul_temp_2_n_81,
P(23) => mul_temp_2_n_82,
P(22) => mul_temp_2_n_83,
P(21) => mul_temp_2_n_84,
P(20) => mul_temp_2_n_85,
P(19) => mul_temp_2_n_86,
P(18) => mul_temp_2_n_87,
P(17) => mul_temp_2_n_88,
P(16) => mul_temp_2_n_89,
P(15) => mul_temp_2_n_90,
P(14) => \^mul_temp_2\(14),
P(13) => mul_temp_2_n_92,
P(12) => mul_temp_2_n_93,
P(11) => mul_temp_2_n_94,
P(10) => mul_temp_2_n_95,
P(9) => mul_temp_2_n_96,
P(8) => mul_temp_2_n_97,
P(7) => mul_temp_2_n_98,
P(6) => mul_temp_2_n_99,
P(5) => mul_temp_2_n_100,
P(4) => mul_temp_2_n_101,
P(3) => mul_temp_2_n_102,
P(2) => mul_temp_2_n_103,
P(1) => mul_temp_2_n_104,
P(0) => mul_temp_2_n_105,
PATTERNBDETECT => NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_2_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_2_UNDERFLOW_UNCONNECTED
);
mul_temp_20: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_20_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_20_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_20_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_20_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_20_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_20_n_74,
P(30) => mul_temp_20_n_75,
P(29) => mul_temp_20_n_76,
P(28) => mul_temp_20_n_77,
P(27) => mul_temp_20_n_78,
P(26) => mul_temp_20_n_79,
P(25) => mul_temp_20_n_80,
P(24) => mul_temp_20_n_81,
P(23) => mul_temp_20_n_82,
P(22) => mul_temp_20_n_83,
P(21) => mul_temp_20_n_84,
P(20) => mul_temp_20_n_85,
P(19) => mul_temp_20_n_86,
P(18) => mul_temp_20_n_87,
P(17) => mul_temp_20_n_88,
P(16) => mul_temp_20_n_89,
P(15) => mul_temp_20_n_90,
P(14) => \^mul_temp_20\(14),
P(13) => mul_temp_20_n_92,
P(12) => mul_temp_20_n_93,
P(11) => mul_temp_20_n_94,
P(10) => mul_temp_20_n_95,
P(9) => mul_temp_20_n_96,
P(8) => mul_temp_20_n_97,
P(7) => mul_temp_20_n_98,
P(6) => mul_temp_20_n_99,
P(5) => mul_temp_20_n_100,
P(4) => mul_temp_20_n_101,
P(3) => mul_temp_20_n_102,
P(2) => mul_temp_20_n_103,
P(1) => mul_temp_20_n_104,
P(0) => mul_temp_20_n_105,
PATTERNBDETECT => NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_20_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_20_UNDERFLOW_UNCONNECTED
);
mul_temp_21: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_21_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_21_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_21_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_21_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_21_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_21_n_74,
P(30) => mul_temp_21_n_75,
P(29) => mul_temp_21_n_76,
P(28) => mul_temp_21_n_77,
P(27) => mul_temp_21_n_78,
P(26) => mul_temp_21_n_79,
P(25) => mul_temp_21_n_80,
P(24) => mul_temp_21_n_81,
P(23) => mul_temp_21_n_82,
P(22) => mul_temp_21_n_83,
P(21) => mul_temp_21_n_84,
P(20) => mul_temp_21_n_85,
P(19) => mul_temp_21_n_86,
P(18) => mul_temp_21_n_87,
P(17) => mul_temp_21_n_88,
P(16) => mul_temp_21_n_89,
P(15) => mul_temp_21_n_90,
P(14) => \^mul_temp_21\(14),
P(13) => mul_temp_21_n_92,
P(12) => mul_temp_21_n_93,
P(11) => mul_temp_21_n_94,
P(10) => mul_temp_21_n_95,
P(9) => mul_temp_21_n_96,
P(8) => mul_temp_21_n_97,
P(7) => mul_temp_21_n_98,
P(6) => mul_temp_21_n_99,
P(5) => mul_temp_21_n_100,
P(4) => mul_temp_21_n_101,
P(3) => mul_temp_21_n_102,
P(2) => mul_temp_21_n_103,
P(1) => mul_temp_21_n_104,
P(0) => mul_temp_21_n_105,
PATTERNBDETECT => NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_21_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_21_UNDERFLOW_UNCONNECTED
);
mul_temp_22: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_22_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_22_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_22_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_22_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_22_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_22_n_74,
P(30) => mul_temp_22_n_75,
P(29) => mul_temp_22_n_76,
P(28) => mul_temp_22_n_77,
P(27) => mul_temp_22_n_78,
P(26) => mul_temp_22_n_79,
P(25) => mul_temp_22_n_80,
P(24) => mul_temp_22_n_81,
P(23) => mul_temp_22_n_82,
P(22) => mul_temp_22_n_83,
P(21) => mul_temp_22_n_84,
P(20) => mul_temp_22_n_85,
P(19) => mul_temp_22_n_86,
P(18) => mul_temp_22_n_87,
P(17) => mul_temp_22_n_88,
P(16) => mul_temp_22_n_89,
P(15) => mul_temp_22_n_90,
P(14) => \^mul_temp_22\(14),
P(13) => mul_temp_22_n_92,
P(12) => mul_temp_22_n_93,
P(11) => mul_temp_22_n_94,
P(10) => mul_temp_22_n_95,
P(9) => mul_temp_22_n_96,
P(8) => mul_temp_22_n_97,
P(7) => mul_temp_22_n_98,
P(6) => mul_temp_22_n_99,
P(5) => mul_temp_22_n_100,
P(4) => mul_temp_22_n_101,
P(3) => mul_temp_22_n_102,
P(2) => mul_temp_22_n_103,
P(1) => mul_temp_22_n_104,
P(0) => mul_temp_22_n_105,
PATTERNBDETECT => NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_22_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_22_UNDERFLOW_UNCONNECTED
);
mul_temp_23: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_23_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_23_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_23_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_23_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_23_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_23_n_74,
P(30) => mul_temp_23_n_75,
P(29) => mul_temp_23_n_76,
P(28) => mul_temp_23_n_77,
P(27) => mul_temp_23_n_78,
P(26) => mul_temp_23_n_79,
P(25) => mul_temp_23_n_80,
P(24) => mul_temp_23_n_81,
P(23) => mul_temp_23_n_82,
P(22) => mul_temp_23_n_83,
P(21) => mul_temp_23_n_84,
P(20) => mul_temp_23_n_85,
P(19) => mul_temp_23_n_86,
P(18) => mul_temp_23_n_87,
P(17) => mul_temp_23_n_88,
P(16) => mul_temp_23_n_89,
P(15) => mul_temp_23_n_90,
P(14) => \^mul_temp_23\(14),
P(13) => mul_temp_23_n_92,
P(12) => mul_temp_23_n_93,
P(11) => mul_temp_23_n_94,
P(10) => mul_temp_23_n_95,
P(9) => mul_temp_23_n_96,
P(8) => mul_temp_23_n_97,
P(7) => mul_temp_23_n_98,
P(6) => mul_temp_23_n_99,
P(5) => mul_temp_23_n_100,
P(4) => mul_temp_23_n_101,
P(3) => mul_temp_23_n_102,
P(2) => mul_temp_23_n_103,
P(1) => mul_temp_23_n_104,
P(0) => mul_temp_23_n_105,
PATTERNBDETECT => NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_23_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_23_UNDERFLOW_UNCONNECTED
);
mul_temp_24: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_24_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_24_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_24_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_24_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_24_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_24_n_74,
P(30) => mul_temp_24_n_75,
P(29) => mul_temp_24_n_76,
P(28) => mul_temp_24_n_77,
P(27) => mul_temp_24_n_78,
P(26) => mul_temp_24_n_79,
P(25) => mul_temp_24_n_80,
P(24) => mul_temp_24_n_81,
P(23) => mul_temp_24_n_82,
P(22) => mul_temp_24_n_83,
P(21) => mul_temp_24_n_84,
P(20) => mul_temp_24_n_85,
P(19) => mul_temp_24_n_86,
P(18) => mul_temp_24_n_87,
P(17) => mul_temp_24_n_88,
P(16) => mul_temp_24_n_89,
P(15) => mul_temp_24_n_90,
P(14) => \^mul_temp_24\(14),
P(13) => mul_temp_24_n_92,
P(12) => mul_temp_24_n_93,
P(11) => mul_temp_24_n_94,
P(10) => mul_temp_24_n_95,
P(9) => mul_temp_24_n_96,
P(8) => mul_temp_24_n_97,
P(7) => mul_temp_24_n_98,
P(6) => mul_temp_24_n_99,
P(5) => mul_temp_24_n_100,
P(4) => mul_temp_24_n_101,
P(3) => mul_temp_24_n_102,
P(2) => mul_temp_24_n_103,
P(1) => mul_temp_24_n_104,
P(0) => mul_temp_24_n_105,
PATTERNBDETECT => NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_24_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_24_UNDERFLOW_UNCONNECTED
);
mul_temp_25: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_25_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_25_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_25_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_25_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_25_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_25_n_74,
P(30) => mul_temp_25_n_75,
P(29) => mul_temp_25_n_76,
P(28) => mul_temp_25_n_77,
P(27) => mul_temp_25_n_78,
P(26) => mul_temp_25_n_79,
P(25) => mul_temp_25_n_80,
P(24) => mul_temp_25_n_81,
P(23) => mul_temp_25_n_82,
P(22) => mul_temp_25_n_83,
P(21) => mul_temp_25_n_84,
P(20) => mul_temp_25_n_85,
P(19) => mul_temp_25_n_86,
P(18) => mul_temp_25_n_87,
P(17) => mul_temp_25_n_88,
P(16) => mul_temp_25_n_89,
P(15) => mul_temp_25_n_90,
P(14) => \^mul_temp_25\(14),
P(13) => mul_temp_25_n_92,
P(12) => mul_temp_25_n_93,
P(11) => mul_temp_25_n_94,
P(10) => mul_temp_25_n_95,
P(9) => mul_temp_25_n_96,
P(8) => mul_temp_25_n_97,
P(7) => mul_temp_25_n_98,
P(6) => mul_temp_25_n_99,
P(5) => mul_temp_25_n_100,
P(4) => mul_temp_25_n_101,
P(3) => mul_temp_25_n_102,
P(2) => mul_temp_25_n_103,
P(1) => mul_temp_25_n_104,
P(0) => mul_temp_25_n_105,
PATTERNBDETECT => NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_25_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_25_UNDERFLOW_UNCONNECTED
);
mul_temp_26: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_26_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_26_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_26_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_26_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_26_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_26_n_74,
P(30) => mul_temp_26_n_75,
P(29) => mul_temp_26_n_76,
P(28) => mul_temp_26_n_77,
P(27) => mul_temp_26_n_78,
P(26) => mul_temp_26_n_79,
P(25) => mul_temp_26_n_80,
P(24) => mul_temp_26_n_81,
P(23) => mul_temp_26_n_82,
P(22) => mul_temp_26_n_83,
P(21) => mul_temp_26_n_84,
P(20) => mul_temp_26_n_85,
P(19) => mul_temp_26_n_86,
P(18) => mul_temp_26_n_87,
P(17) => mul_temp_26_n_88,
P(16) => mul_temp_26_n_89,
P(15) => mul_temp_26_n_90,
P(14) => \^mul_temp_26\(14),
P(13) => mul_temp_26_n_92,
P(12) => mul_temp_26_n_93,
P(11) => mul_temp_26_n_94,
P(10) => mul_temp_26_n_95,
P(9) => mul_temp_26_n_96,
P(8) => mul_temp_26_n_97,
P(7) => mul_temp_26_n_98,
P(6) => mul_temp_26_n_99,
P(5) => mul_temp_26_n_100,
P(4) => mul_temp_26_n_101,
P(3) => mul_temp_26_n_102,
P(2) => mul_temp_26_n_103,
P(1) => mul_temp_26_n_104,
P(0) => mul_temp_26_n_105,
PATTERNBDETECT => NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_26_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_26_UNDERFLOW_UNCONNECTED
);
mul_temp_27: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_27_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_27_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_27_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_27_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_27_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_27_n_74,
P(30) => mul_temp_27_n_75,
P(29) => mul_temp_27_n_76,
P(28) => mul_temp_27_n_77,
P(27) => mul_temp_27_n_78,
P(26) => mul_temp_27_n_79,
P(25) => mul_temp_27_n_80,
P(24) => mul_temp_27_n_81,
P(23) => mul_temp_27_n_82,
P(22) => mul_temp_27_n_83,
P(21) => mul_temp_27_n_84,
P(20) => mul_temp_27_n_85,
P(19) => mul_temp_27_n_86,
P(18) => mul_temp_27_n_87,
P(17) => mul_temp_27_n_88,
P(16) => mul_temp_27_n_89,
P(15) => mul_temp_27_n_90,
P(14) => \^mul_temp_27\(14),
P(13) => mul_temp_27_n_92,
P(12) => mul_temp_27_n_93,
P(11) => mul_temp_27_n_94,
P(10) => mul_temp_27_n_95,
P(9) => mul_temp_27_n_96,
P(8) => mul_temp_27_n_97,
P(7) => mul_temp_27_n_98,
P(6) => mul_temp_27_n_99,
P(5) => mul_temp_27_n_100,
P(4) => mul_temp_27_n_101,
P(3) => mul_temp_27_n_102,
P(2) => mul_temp_27_n_103,
P(1) => mul_temp_27_n_104,
P(0) => mul_temp_27_n_105,
PATTERNBDETECT => NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_27_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_27_UNDERFLOW_UNCONNECTED
);
mul_temp_28: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_28_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_28_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_28_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_28_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_28_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_28_n_74,
P(30) => mul_temp_28_n_75,
P(29) => mul_temp_28_n_76,
P(28) => mul_temp_28_n_77,
P(27) => mul_temp_28_n_78,
P(26) => mul_temp_28_n_79,
P(25) => mul_temp_28_n_80,
P(24) => mul_temp_28_n_81,
P(23) => mul_temp_28_n_82,
P(22) => mul_temp_28_n_83,
P(21) => mul_temp_28_n_84,
P(20) => mul_temp_28_n_85,
P(19) => mul_temp_28_n_86,
P(18) => mul_temp_28_n_87,
P(17) => mul_temp_28_n_88,
P(16) => mul_temp_28_n_89,
P(15) => mul_temp_28_n_90,
P(14) => \^mul_temp_28\(14),
P(13) => mul_temp_28_n_92,
P(12) => mul_temp_28_n_93,
P(11) => mul_temp_28_n_94,
P(10) => mul_temp_28_n_95,
P(9) => mul_temp_28_n_96,
P(8) => mul_temp_28_n_97,
P(7) => mul_temp_28_n_98,
P(6) => mul_temp_28_n_99,
P(5) => mul_temp_28_n_100,
P(4) => mul_temp_28_n_101,
P(3) => mul_temp_28_n_102,
P(2) => mul_temp_28_n_103,
P(1) => mul_temp_28_n_104,
P(0) => mul_temp_28_n_105,
PATTERNBDETECT => NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_28_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_28_UNDERFLOW_UNCONNECTED
);
mul_temp_29: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_29_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_29_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_29_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_29_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_29_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_29_n_74,
P(30) => mul_temp_29_n_75,
P(29) => mul_temp_29_n_76,
P(28) => mul_temp_29_n_77,
P(27) => mul_temp_29_n_78,
P(26) => mul_temp_29_n_79,
P(25) => mul_temp_29_n_80,
P(24) => mul_temp_29_n_81,
P(23) => mul_temp_29_n_82,
P(22) => mul_temp_29_n_83,
P(21) => mul_temp_29_n_84,
P(20) => mul_temp_29_n_85,
P(19) => mul_temp_29_n_86,
P(18) => mul_temp_29_n_87,
P(17) => mul_temp_29_n_88,
P(16) => mul_temp_29_n_89,
P(15) => mul_temp_29_n_90,
P(14) => \^mul_temp_29\(14),
P(13) => mul_temp_29_n_92,
P(12) => mul_temp_29_n_93,
P(11) => mul_temp_29_n_94,
P(10) => mul_temp_29_n_95,
P(9) => mul_temp_29_n_96,
P(8) => mul_temp_29_n_97,
P(7) => mul_temp_29_n_98,
P(6) => mul_temp_29_n_99,
P(5) => mul_temp_29_n_100,
P(4) => mul_temp_29_n_101,
P(3) => mul_temp_29_n_102,
P(2) => mul_temp_29_n_103,
P(1) => mul_temp_29_n_104,
P(0) => mul_temp_29_n_105,
PATTERNBDETECT => NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_29_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_29_UNDERFLOW_UNCONNECTED
);
mul_temp_3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_3_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_3_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_3_n_74,
P(30) => mul_temp_3_n_75,
P(29) => mul_temp_3_n_76,
P(28) => mul_temp_3_n_77,
P(27) => mul_temp_3_n_78,
P(26) => mul_temp_3_n_79,
P(25) => mul_temp_3_n_80,
P(24) => mul_temp_3_n_81,
P(23) => mul_temp_3_n_82,
P(22) => mul_temp_3_n_83,
P(21) => mul_temp_3_n_84,
P(20) => mul_temp_3_n_85,
P(19) => mul_temp_3_n_86,
P(18) => mul_temp_3_n_87,
P(17) => mul_temp_3_n_88,
P(16) => mul_temp_3_n_89,
P(15) => mul_temp_3_n_90,
P(14) => \^mul_temp_3\(14),
P(13) => mul_temp_3_n_92,
P(12) => mul_temp_3_n_93,
P(11) => mul_temp_3_n_94,
P(10) => mul_temp_3_n_95,
P(9) => mul_temp_3_n_96,
P(8) => mul_temp_3_n_97,
P(7) => mul_temp_3_n_98,
P(6) => mul_temp_3_n_99,
P(5) => mul_temp_3_n_100,
P(4) => mul_temp_3_n_101,
P(3) => mul_temp_3_n_102,
P(2) => mul_temp_3_n_103,
P(1) => mul_temp_3_n_104,
P(0) => mul_temp_3_n_105,
PATTERNBDETECT => NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_3_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_3_UNDERFLOW_UNCONNECTED
);
mul_temp_30: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_30_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_30_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_30_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_30_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_30_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_30_n_74,
P(30) => mul_temp_30_n_75,
P(29) => mul_temp_30_n_76,
P(28) => mul_temp_30_n_77,
P(27) => mul_temp_30_n_78,
P(26) => mul_temp_30_n_79,
P(25) => mul_temp_30_n_80,
P(24) => mul_temp_30_n_81,
P(23) => mul_temp_30_n_82,
P(22) => mul_temp_30_n_83,
P(21) => mul_temp_30_n_84,
P(20) => mul_temp_30_n_85,
P(19) => mul_temp_30_n_86,
P(18) => mul_temp_30_n_87,
P(17) => mul_temp_30_n_88,
P(16) => mul_temp_30_n_89,
P(15) => mul_temp_30_n_90,
P(14) => \^mul_temp_30\(14),
P(13) => mul_temp_30_n_92,
P(12) => mul_temp_30_n_93,
P(11) => mul_temp_30_n_94,
P(10) => mul_temp_30_n_95,
P(9) => mul_temp_30_n_96,
P(8) => mul_temp_30_n_97,
P(7) => mul_temp_30_n_98,
P(6) => mul_temp_30_n_99,
P(5) => mul_temp_30_n_100,
P(4) => mul_temp_30_n_101,
P(3) => mul_temp_30_n_102,
P(2) => mul_temp_30_n_103,
P(1) => mul_temp_30_n_104,
P(0) => mul_temp_30_n_105,
PATTERNBDETECT => NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_30_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_30_UNDERFLOW_UNCONNECTED
);
mul_temp_31: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_31_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_31_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_31_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_31_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_31_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_31_n_74,
P(30) => mul_temp_31_n_75,
P(29) => mul_temp_31_n_76,
P(28) => mul_temp_31_n_77,
P(27) => mul_temp_31_n_78,
P(26) => mul_temp_31_n_79,
P(25) => mul_temp_31_n_80,
P(24) => mul_temp_31_n_81,
P(23) => mul_temp_31_n_82,
P(22) => mul_temp_31_n_83,
P(21) => mul_temp_31_n_84,
P(20) => mul_temp_31_n_85,
P(19) => mul_temp_31_n_86,
P(18) => mul_temp_31_n_87,
P(17) => mul_temp_31_n_88,
P(16) => mul_temp_31_n_89,
P(15) => mul_temp_31_n_90,
P(14) => \^mul_temp_31\(14),
P(13) => mul_temp_31_n_92,
P(12) => mul_temp_31_n_93,
P(11) => mul_temp_31_n_94,
P(10) => mul_temp_31_n_95,
P(9) => mul_temp_31_n_96,
P(8) => mul_temp_31_n_97,
P(7) => mul_temp_31_n_98,
P(6) => mul_temp_31_n_99,
P(5) => mul_temp_31_n_100,
P(4) => mul_temp_31_n_101,
P(3) => mul_temp_31_n_102,
P(2) => mul_temp_31_n_103,
P(1) => mul_temp_31_n_104,
P(0) => mul_temp_31_n_105,
PATTERNBDETECT => NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_31_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_31_UNDERFLOW_UNCONNECTED
);
mul_temp_32: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_32_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_32_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_32_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_32_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_32_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_32_n_74,
P(30) => mul_temp_32_n_75,
P(29) => mul_temp_32_n_76,
P(28) => mul_temp_32_n_77,
P(27) => mul_temp_32_n_78,
P(26) => mul_temp_32_n_79,
P(25) => mul_temp_32_n_80,
P(24) => mul_temp_32_n_81,
P(23) => mul_temp_32_n_82,
P(22) => mul_temp_32_n_83,
P(21) => mul_temp_32_n_84,
P(20) => mul_temp_32_n_85,
P(19) => mul_temp_32_n_86,
P(18) => mul_temp_32_n_87,
P(17) => mul_temp_32_n_88,
P(16) => mul_temp_32_n_89,
P(15) => mul_temp_32_n_90,
P(14) => \^mul_temp_32\(14),
P(13) => mul_temp_32_n_92,
P(12) => mul_temp_32_n_93,
P(11) => mul_temp_32_n_94,
P(10) => mul_temp_32_n_95,
P(9) => mul_temp_32_n_96,
P(8) => mul_temp_32_n_97,
P(7) => mul_temp_32_n_98,
P(6) => mul_temp_32_n_99,
P(5) => mul_temp_32_n_100,
P(4) => mul_temp_32_n_101,
P(3) => mul_temp_32_n_102,
P(2) => mul_temp_32_n_103,
P(1) => mul_temp_32_n_104,
P(0) => mul_temp_32_n_105,
PATTERNBDETECT => NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_32_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_32_UNDERFLOW_UNCONNECTED
);
mul_temp_4: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_4_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_4_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_4_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_4_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_4_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_4_n_74,
P(30) => mul_temp_4_n_75,
P(29) => mul_temp_4_n_76,
P(28) => mul_temp_4_n_77,
P(27) => mul_temp_4_n_78,
P(26) => mul_temp_4_n_79,
P(25) => mul_temp_4_n_80,
P(24) => mul_temp_4_n_81,
P(23) => mul_temp_4_n_82,
P(22) => mul_temp_4_n_83,
P(21) => mul_temp_4_n_84,
P(20) => mul_temp_4_n_85,
P(19) => mul_temp_4_n_86,
P(18) => mul_temp_4_n_87,
P(17) => mul_temp_4_n_88,
P(16) => mul_temp_4_n_89,
P(15) => mul_temp_4_n_90,
P(14) => \^mul_temp_4\(14),
P(13) => mul_temp_4_n_92,
P(12) => mul_temp_4_n_93,
P(11) => mul_temp_4_n_94,
P(10) => mul_temp_4_n_95,
P(9) => mul_temp_4_n_96,
P(8) => mul_temp_4_n_97,
P(7) => mul_temp_4_n_98,
P(6) => mul_temp_4_n_99,
P(5) => mul_temp_4_n_100,
P(4) => mul_temp_4_n_101,
P(3) => mul_temp_4_n_102,
P(2) => mul_temp_4_n_103,
P(1) => mul_temp_4_n_104,
P(0) => mul_temp_4_n_105,
PATTERNBDETECT => NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_4_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_4_UNDERFLOW_UNCONNECTED
);
mul_temp_5: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_5_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_5_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_5_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_5_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_5_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_5_n_74,
P(30) => mul_temp_5_n_75,
P(29) => mul_temp_5_n_76,
P(28) => mul_temp_5_n_77,
P(27) => mul_temp_5_n_78,
P(26) => mul_temp_5_n_79,
P(25) => mul_temp_5_n_80,
P(24) => mul_temp_5_n_81,
P(23) => mul_temp_5_n_82,
P(22) => mul_temp_5_n_83,
P(21) => mul_temp_5_n_84,
P(20) => mul_temp_5_n_85,
P(19) => mul_temp_5_n_86,
P(18) => mul_temp_5_n_87,
P(17) => mul_temp_5_n_88,
P(16) => mul_temp_5_n_89,
P(15) => mul_temp_5_n_90,
P(14) => \^mul_temp_5\(14),
P(13) => mul_temp_5_n_92,
P(12) => mul_temp_5_n_93,
P(11) => mul_temp_5_n_94,
P(10) => mul_temp_5_n_95,
P(9) => mul_temp_5_n_96,
P(8) => mul_temp_5_n_97,
P(7) => mul_temp_5_n_98,
P(6) => mul_temp_5_n_99,
P(5) => mul_temp_5_n_100,
P(4) => mul_temp_5_n_101,
P(3) => mul_temp_5_n_102,
P(2) => mul_temp_5_n_103,
P(1) => mul_temp_5_n_104,
P(0) => mul_temp_5_n_105,
PATTERNBDETECT => NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_5_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_5_UNDERFLOW_UNCONNECTED
);
mul_temp_6: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_6_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_6_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_6_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_6_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_6_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_6_n_74,
P(30) => mul_temp_6_n_75,
P(29) => mul_temp_6_n_76,
P(28) => mul_temp_6_n_77,
P(27) => mul_temp_6_n_78,
P(26) => mul_temp_6_n_79,
P(25) => mul_temp_6_n_80,
P(24) => mul_temp_6_n_81,
P(23) => mul_temp_6_n_82,
P(22) => mul_temp_6_n_83,
P(21) => mul_temp_6_n_84,
P(20) => mul_temp_6_n_85,
P(19) => mul_temp_6_n_86,
P(18) => mul_temp_6_n_87,
P(17) => mul_temp_6_n_88,
P(16) => mul_temp_6_n_89,
P(15) => mul_temp_6_n_90,
P(14) => \^mul_temp_6\(14),
P(13) => mul_temp_6_n_92,
P(12) => mul_temp_6_n_93,
P(11) => mul_temp_6_n_94,
P(10) => mul_temp_6_n_95,
P(9) => mul_temp_6_n_96,
P(8) => mul_temp_6_n_97,
P(7) => mul_temp_6_n_98,
P(6) => mul_temp_6_n_99,
P(5) => mul_temp_6_n_100,
P(4) => mul_temp_6_n_101,
P(3) => mul_temp_6_n_102,
P(2) => mul_temp_6_n_103,
P(1) => mul_temp_6_n_104,
P(0) => mul_temp_6_n_105,
PATTERNBDETECT => NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_6_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_6_UNDERFLOW_UNCONNECTED
);
mul_temp_7: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_7_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_7_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_7_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_7_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_7_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_7_n_74,
P(30) => mul_temp_7_n_75,
P(29) => mul_temp_7_n_76,
P(28) => mul_temp_7_n_77,
P(27) => mul_temp_7_n_78,
P(26) => mul_temp_7_n_79,
P(25) => mul_temp_7_n_80,
P(24) => mul_temp_7_n_81,
P(23) => mul_temp_7_n_82,
P(22) => mul_temp_7_n_83,
P(21) => mul_temp_7_n_84,
P(20) => mul_temp_7_n_85,
P(19) => mul_temp_7_n_86,
P(18) => mul_temp_7_n_87,
P(17) => mul_temp_7_n_88,
P(16) => mul_temp_7_n_89,
P(15) => mul_temp_7_n_90,
P(14) => \^mul_temp_7\(14),
P(13) => mul_temp_7_n_92,
P(12) => mul_temp_7_n_93,
P(11) => mul_temp_7_n_94,
P(10) => mul_temp_7_n_95,
P(9) => mul_temp_7_n_96,
P(8) => mul_temp_7_n_97,
P(7) => mul_temp_7_n_98,
P(6) => mul_temp_7_n_99,
P(5) => mul_temp_7_n_100,
P(4) => mul_temp_7_n_101,
P(3) => mul_temp_7_n_102,
P(2) => mul_temp_7_n_103,
P(1) => mul_temp_7_n_104,
P(0) => mul_temp_7_n_105,
PATTERNBDETECT => NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_7_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_7_UNDERFLOW_UNCONNECTED
);
mul_temp_8: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_8_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_8_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_8_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_8_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_8_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_8_n_74,
P(30) => mul_temp_8_n_75,
P(29) => mul_temp_8_n_76,
P(28) => mul_temp_8_n_77,
P(27) => mul_temp_8_n_78,
P(26) => mul_temp_8_n_79,
P(25) => mul_temp_8_n_80,
P(24) => mul_temp_8_n_81,
P(23) => mul_temp_8_n_82,
P(22) => mul_temp_8_n_83,
P(21) => mul_temp_8_n_84,
P(20) => mul_temp_8_n_85,
P(19) => mul_temp_8_n_86,
P(18) => mul_temp_8_n_87,
P(17) => mul_temp_8_n_88,
P(16) => mul_temp_8_n_89,
P(15) => mul_temp_8_n_90,
P(14) => \^mul_temp_8\(14),
P(13) => mul_temp_8_n_92,
P(12) => mul_temp_8_n_93,
P(11) => mul_temp_8_n_94,
P(10) => mul_temp_8_n_95,
P(9) => mul_temp_8_n_96,
P(8) => mul_temp_8_n_97,
P(7) => mul_temp_8_n_98,
P(6) => mul_temp_8_n_99,
P(5) => mul_temp_8_n_100,
P(4) => mul_temp_8_n_101,
P(3) => mul_temp_8_n_102,
P(2) => mul_temp_8_n_103,
P(1) => mul_temp_8_n_104,
P(0) => mul_temp_8_n_105,
PATTERNBDETECT => NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_8_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_8_UNDERFLOW_UNCONNECTED
);
mul_temp_9: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_9_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_9_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_9_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_9_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_9_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_9_n_74,
P(30) => mul_temp_9_n_75,
P(29) => mul_temp_9_n_76,
P(28) => mul_temp_9_n_77,
P(27) => mul_temp_9_n_78,
P(26) => mul_temp_9_n_79,
P(25) => mul_temp_9_n_80,
P(24) => mul_temp_9_n_81,
P(23) => mul_temp_9_n_82,
P(22) => mul_temp_9_n_83,
P(21) => mul_temp_9_n_84,
P(20) => mul_temp_9_n_85,
P(19) => mul_temp_9_n_86,
P(18) => mul_temp_9_n_87,
P(17) => mul_temp_9_n_88,
P(16) => mul_temp_9_n_89,
P(15) => mul_temp_9_n_90,
P(14) => \^mul_temp_9\(14),
P(13) => mul_temp_9_n_92,
P(12) => mul_temp_9_n_93,
P(11) => mul_temp_9_n_94,
P(10) => mul_temp_9_n_95,
P(9) => mul_temp_9_n_96,
P(8) => mul_temp_9_n_97,
P(7) => mul_temp_9_n_98,
P(6) => mul_temp_9_n_99,
P(5) => mul_temp_9_n_100,
P(4) => mul_temp_9_n_101,
P(3) => mul_temp_9_n_102,
P(2) => mul_temp_9_n_103,
P(1) => mul_temp_9_n_104,
P(0) => mul_temp_9_n_105,
PATTERNBDETECT => NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_9_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_9_UNDERFLOW_UNCONNECTED
);
sub_temp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sub_temp_carry_n_0,
CO(2) => sub_temp_carry_n_1,
CO(1) => sub_temp_carry_n_2,
CO(0) => sub_temp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3 downto 0) => \^mul_temp_16\(3 downto 0),
S(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0)
);
\sub_temp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sub_temp_carry_n_0,
CO(3) => \sub_temp_carry__0_n_0\,
CO(2) => \sub_temp_carry__0_n_1\,
CO(1) => \sub_temp_carry__0_n_2\,
CO(0) => \sub_temp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3 downto 0) => \^mul_temp_16\(7 downto 4),
S(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0)
);
\sub_temp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__0_n_0\,
CO(3) => \sub_temp_carry__1_n_0\,
CO(2) => \sub_temp_carry__1_n_1\,
CO(1) => \sub_temp_carry__1_n_2\,
CO(0) => \sub_temp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(11 downto 8),
O(3 downto 0) => \^mul_temp_16\(11 downto 8),
S(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0)
);
\sub_temp_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__1_n_0\,
CO(3) => \NLW_sub_temp_carry__2_CO_UNCONNECTED\(3),
CO(2) => \sub_temp_carry__2_n_1\,
CO(1) => \sub_temp_carry__2_n_2\,
CO(0) => \sub_temp_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => Q(14 downto 12),
O(3 downto 0) => \^mul_temp_16\(15 downto 12),
S(3 downto 0) => S(3 downto 0)
);
\weight[0][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_88\,
I1 => \weight_reg[0]_15\(3),
O => \weight[0][0]_i_2_n_0\
);
\weight[0][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_89\,
I1 => \weight_reg[0]_15\(2),
O => \weight[0][0]_i_3_n_0\
);
\weight[0][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_90\,
I1 => \weight_reg[0]_15\(1),
O => \weight[0][0]_i_4_n_0\
);
\weight[0][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_91\,
I1 => \weight_reg[0]_15\(0),
O => \weight[0][0]_i_5_n_0\
);
\weight[0][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_76\,
I1 => \weight_reg[0]_15\(15),
O => \weight[0][12]_i_2_n_0\
);
\weight[0][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_77\,
I1 => \weight_reg[0]_15\(14),
O => \weight[0][12]_i_3_n_0\
);
\weight[0][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_78\,
I1 => \weight_reg[0]_15\(13),
O => \weight[0][12]_i_4_n_0\
);
\weight[0][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_79\,
I1 => \weight_reg[0]_15\(12),
O => \weight[0][12]_i_5_n_0\
);
\weight[0][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_84\,
I1 => \weight_reg[0]_15\(7),
O => \weight[0][4]_i_2_n_0\
);
\weight[0][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_85\,
I1 => \weight_reg[0]_15\(6),
O => \weight[0][4]_i_3_n_0\
);
\weight[0][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_86\,
I1 => \weight_reg[0]_15\(5),
O => \weight[0][4]_i_4_n_0\
);
\weight[0][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_87\,
I1 => \weight_reg[0]_15\(4),
O => \weight[0][4]_i_5_n_0\
);
\weight[0][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_80\,
I1 => \weight_reg[0]_15\(11),
O => \weight[0][8]_i_2_n_0\
);
\weight[0][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_81\,
I1 => \weight_reg[0]_15\(10),
O => \weight[0][8]_i_3_n_0\
);
\weight[0][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_82\,
I1 => \weight_reg[0]_15\(9),
O => \weight[0][8]_i_4_n_0\
);
\weight[0][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_83\,
I1 => \weight_reg[0]_15\(8),
O => \weight[0][8]_i_5_n_0\
);
\weight[10][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_88\,
I1 => \weight_reg[10]_9\(3),
O => \weight[10][0]_i_2_n_0\
);
\weight[10][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_89\,
I1 => \weight_reg[10]_9\(2),
O => \weight[10][0]_i_3_n_0\
);
\weight[10][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_90\,
I1 => \weight_reg[10]_9\(1),
O => \weight[10][0]_i_4_n_0\
);
\weight[10][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_91\,
I1 => \weight_reg[10]_9\(0),
O => \weight[10][0]_i_5_n_0\
);
\weight[10][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_76\,
I1 => \weight_reg[10]_9\(15),
O => \weight[10][12]_i_2_n_0\
);
\weight[10][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_77\,
I1 => \weight_reg[10]_9\(14),
O => \weight[10][12]_i_3_n_0\
);
\weight[10][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_78\,
I1 => \weight_reg[10]_9\(13),
O => \weight[10][12]_i_4_n_0\
);
\weight[10][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_79\,
I1 => \weight_reg[10]_9\(12),
O => \weight[10][12]_i_5_n_0\
);
\weight[10][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_84\,
I1 => \weight_reg[10]_9\(7),
O => \weight[10][4]_i_2_n_0\
);
\weight[10][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_85\,
I1 => \weight_reg[10]_9\(6),
O => \weight[10][4]_i_3_n_0\
);
\weight[10][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_86\,
I1 => \weight_reg[10]_9\(5),
O => \weight[10][4]_i_4_n_0\
);
\weight[10][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_87\,
I1 => \weight_reg[10]_9\(4),
O => \weight[10][4]_i_5_n_0\
);
\weight[10][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_80\,
I1 => \weight_reg[10]_9\(11),
O => \weight[10][8]_i_2_n_0\
);
\weight[10][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_81\,
I1 => \weight_reg[10]_9\(10),
O => \weight[10][8]_i_3_n_0\
);
\weight[10][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_82\,
I1 => \weight_reg[10]_9\(9),
O => \weight[10][8]_i_4_n_0\
);
\weight[10][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_83\,
I1 => \weight_reg[10]_9\(8),
O => \weight[10][8]_i_5_n_0\
);
\weight[11][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_88\,
I1 => \weight_reg[11]_10\(3),
O => \weight[11][0]_i_2_n_0\
);
\weight[11][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_89\,
I1 => \weight_reg[11]_10\(2),
O => \weight[11][0]_i_3_n_0\
);
\weight[11][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_90\,
I1 => \weight_reg[11]_10\(1),
O => \weight[11][0]_i_4_n_0\
);
\weight[11][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_91\,
I1 => \weight_reg[11]_10\(0),
O => \weight[11][0]_i_5_n_0\
);
\weight[11][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_76\,
I1 => \weight_reg[11]_10\(15),
O => \weight[11][12]_i_2_n_0\
);
\weight[11][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_77\,
I1 => \weight_reg[11]_10\(14),
O => \weight[11][12]_i_3_n_0\
);
\weight[11][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_78\,
I1 => \weight_reg[11]_10\(13),
O => \weight[11][12]_i_4_n_0\
);
\weight[11][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_79\,
I1 => \weight_reg[11]_10\(12),
O => \weight[11][12]_i_5_n_0\
);
\weight[11][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_84\,
I1 => \weight_reg[11]_10\(7),
O => \weight[11][4]_i_2_n_0\
);
\weight[11][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_85\,
I1 => \weight_reg[11]_10\(6),
O => \weight[11][4]_i_3_n_0\
);
\weight[11][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_86\,
I1 => \weight_reg[11]_10\(5),
O => \weight[11][4]_i_4_n_0\
);
\weight[11][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_87\,
I1 => \weight_reg[11]_10\(4),
O => \weight[11][4]_i_5_n_0\
);
\weight[11][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_80\,
I1 => \weight_reg[11]_10\(11),
O => \weight[11][8]_i_2_n_0\
);
\weight[11][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_81\,
I1 => \weight_reg[11]_10\(10),
O => \weight[11][8]_i_3_n_0\
);
\weight[11][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_82\,
I1 => \weight_reg[11]_10\(9),
O => \weight[11][8]_i_4_n_0\
);
\weight[11][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_83\,
I1 => \weight_reg[11]_10\(8),
O => \weight[11][8]_i_5_n_0\
);
\weight[12][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_88\,
I1 => \weight_reg[12]_11\(3),
O => \weight[12][0]_i_2_n_0\
);
\weight[12][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_89\,
I1 => \weight_reg[12]_11\(2),
O => \weight[12][0]_i_3_n_0\
);
\weight[12][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_90\,
I1 => \weight_reg[12]_11\(1),
O => \weight[12][0]_i_4_n_0\
);
\weight[12][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_91\,
I1 => \weight_reg[12]_11\(0),
O => \weight[12][0]_i_5_n_0\
);
\weight[12][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_76\,
I1 => \weight_reg[12]_11\(15),
O => \weight[12][12]_i_2_n_0\
);
\weight[12][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_77\,
I1 => \weight_reg[12]_11\(14),
O => \weight[12][12]_i_3_n_0\
);
\weight[12][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_78\,
I1 => \weight_reg[12]_11\(13),
O => \weight[12][12]_i_4_n_0\
);
\weight[12][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_79\,
I1 => \weight_reg[12]_11\(12),
O => \weight[12][12]_i_5_n_0\
);
\weight[12][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_84\,
I1 => \weight_reg[12]_11\(7),
O => \weight[12][4]_i_2_n_0\
);
\weight[12][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_85\,
I1 => \weight_reg[12]_11\(6),
O => \weight[12][4]_i_3_n_0\
);
\weight[12][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_86\,
I1 => \weight_reg[12]_11\(5),
O => \weight[12][4]_i_4_n_0\
);
\weight[12][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_87\,
I1 => \weight_reg[12]_11\(4),
O => \weight[12][4]_i_5_n_0\
);
\weight[12][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_80\,
I1 => \weight_reg[12]_11\(11),
O => \weight[12][8]_i_2_n_0\
);
\weight[12][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_81\,
I1 => \weight_reg[12]_11\(10),
O => \weight[12][8]_i_3_n_0\
);
\weight[12][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_82\,
I1 => \weight_reg[12]_11\(9),
O => \weight[12][8]_i_4_n_0\
);
\weight[12][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_83\,
I1 => \weight_reg[12]_11\(8),
O => \weight[12][8]_i_5_n_0\
);
\weight[13][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_88\,
I1 => \weight_reg[13]_12\(3),
O => \weight[13][0]_i_2_n_0\
);
\weight[13][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_89\,
I1 => \weight_reg[13]_12\(2),
O => \weight[13][0]_i_3_n_0\
);
\weight[13][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_90\,
I1 => \weight_reg[13]_12\(1),
O => \weight[13][0]_i_4_n_0\
);
\weight[13][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_91\,
I1 => \weight_reg[13]_12\(0),
O => \weight[13][0]_i_5_n_0\
);
\weight[13][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_76\,
I1 => \weight_reg[13]_12\(15),
O => \weight[13][12]_i_2_n_0\
);
\weight[13][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_77\,
I1 => \weight_reg[13]_12\(14),
O => \weight[13][12]_i_3_n_0\
);
\weight[13][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_78\,
I1 => \weight_reg[13]_12\(13),
O => \weight[13][12]_i_4_n_0\
);
\weight[13][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_79\,
I1 => \weight_reg[13]_12\(12),
O => \weight[13][12]_i_5_n_0\
);
\weight[13][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_84\,
I1 => \weight_reg[13]_12\(7),
O => \weight[13][4]_i_2_n_0\
);
\weight[13][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_85\,
I1 => \weight_reg[13]_12\(6),
O => \weight[13][4]_i_3_n_0\
);
\weight[13][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_86\,
I1 => \weight_reg[13]_12\(5),
O => \weight[13][4]_i_4_n_0\
);
\weight[13][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_87\,
I1 => \weight_reg[13]_12\(4),
O => \weight[13][4]_i_5_n_0\
);
\weight[13][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_80\,
I1 => \weight_reg[13]_12\(11),
O => \weight[13][8]_i_2_n_0\
);
\weight[13][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_81\,
I1 => \weight_reg[13]_12\(10),
O => \weight[13][8]_i_3_n_0\
);
\weight[13][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_82\,
I1 => \weight_reg[13]_12\(9),
O => \weight[13][8]_i_4_n_0\
);
\weight[13][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_83\,
I1 => \weight_reg[13]_12\(8),
O => \weight[13][8]_i_5_n_0\
);
\weight[14][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_88\,
I1 => \weight_reg[14]_13\(3),
O => \weight[14][0]_i_2_n_0\
);
\weight[14][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_89\,
I1 => \weight_reg[14]_13\(2),
O => \weight[14][0]_i_3_n_0\
);
\weight[14][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_90\,
I1 => \weight_reg[14]_13\(1),
O => \weight[14][0]_i_4_n_0\
);
\weight[14][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_91\,
I1 => \weight_reg[14]_13\(0),
O => \weight[14][0]_i_5_n_0\
);
\weight[14][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_76\,
I1 => \weight_reg[14]_13\(15),
O => \weight[14][12]_i_2_n_0\
);
\weight[14][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_77\,
I1 => \weight_reg[14]_13\(14),
O => \weight[14][12]_i_3_n_0\
);
\weight[14][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_78\,
I1 => \weight_reg[14]_13\(13),
O => \weight[14][12]_i_4_n_0\
);
\weight[14][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_79\,
I1 => \weight_reg[14]_13\(12),
O => \weight[14][12]_i_5_n_0\
);
\weight[14][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_84\,
I1 => \weight_reg[14]_13\(7),
O => \weight[14][4]_i_2_n_0\
);
\weight[14][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_85\,
I1 => \weight_reg[14]_13\(6),
O => \weight[14][4]_i_3_n_0\
);
\weight[14][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_86\,
I1 => \weight_reg[14]_13\(5),
O => \weight[14][4]_i_4_n_0\
);
\weight[14][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_87\,
I1 => \weight_reg[14]_13\(4),
O => \weight[14][4]_i_5_n_0\
);
\weight[14][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_80\,
I1 => \weight_reg[14]_13\(11),
O => \weight[14][8]_i_2_n_0\
);
\weight[14][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_81\,
I1 => \weight_reg[14]_13\(10),
O => \weight[14][8]_i_3_n_0\
);
\weight[14][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_82\,
I1 => \weight_reg[14]_13\(9),
O => \weight[14][8]_i_4_n_0\
);
\weight[14][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_83\,
I1 => \weight_reg[14]_13\(8),
O => \weight[14][8]_i_5_n_0\
);
\weight[15][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_88\,
I1 => \weight_reg[15]_14\(3),
O => \weight[15][0]_i_2_n_0\
);
\weight[15][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_89\,
I1 => \weight_reg[15]_14\(2),
O => \weight[15][0]_i_3_n_0\
);
\weight[15][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_90\,
I1 => \weight_reg[15]_14\(1),
O => \weight[15][0]_i_4_n_0\
);
\weight[15][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_91\,
I1 => \weight_reg[15]_14\(0),
O => \weight[15][0]_i_5_n_0\
);
\weight[15][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_76\,
I1 => \weight_reg[15]_14\(15),
O => \weight[15][12]_i_2_n_0\
);
\weight[15][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_77\,
I1 => \weight_reg[15]_14\(14),
O => \weight[15][12]_i_3_n_0\
);
\weight[15][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_78\,
I1 => \weight_reg[15]_14\(13),
O => \weight[15][12]_i_4_n_0\
);
\weight[15][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_79\,
I1 => \weight_reg[15]_14\(12),
O => \weight[15][12]_i_5_n_0\
);
\weight[15][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_84\,
I1 => \weight_reg[15]_14\(7),
O => \weight[15][4]_i_2_n_0\
);
\weight[15][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_85\,
I1 => \weight_reg[15]_14\(6),
O => \weight[15][4]_i_3_n_0\
);
\weight[15][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_86\,
I1 => \weight_reg[15]_14\(5),
O => \weight[15][4]_i_4_n_0\
);
\weight[15][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_87\,
I1 => \weight_reg[15]_14\(4),
O => \weight[15][4]_i_5_n_0\
);
\weight[15][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_80\,
I1 => \weight_reg[15]_14\(11),
O => \weight[15][8]_i_2_n_0\
);
\weight[15][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_81\,
I1 => \weight_reg[15]_14\(10),
O => \weight[15][8]_i_3_n_0\
);
\weight[15][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_82\,
I1 => \weight_reg[15]_14\(9),
O => \weight[15][8]_i_4_n_0\
);
\weight[15][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_83\,
I1 => \weight_reg[15]_14\(8),
O => \weight[15][8]_i_5_n_0\
);
\weight[1][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(3),
I1 => \weight_reg[1]_0\(3),
O => \weight[1][0]_i_2_n_0\
);
\weight[1][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(2),
I1 => \weight_reg[1]_0\(2),
O => \weight[1][0]_i_3_n_0\
);
\weight[1][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(1),
I1 => \weight_reg[1]_0\(1),
O => \weight[1][0]_i_4_n_0\
);
\weight[1][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(0),
I1 => \weight_reg[1]_0\(0),
O => \weight[1][0]_i_5_n_0\
);
\weight[1][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(15),
I1 => \weight_reg[1]_0\(15),
O => \weight[1][12]_i_2_n_0\
);
\weight[1][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(14),
I1 => \weight_reg[1]_0\(14),
O => \weight[1][12]_i_3_n_0\
);
\weight[1][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(13),
I1 => \weight_reg[1]_0\(13),
O => \weight[1][12]_i_4_n_0\
);
\weight[1][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(12),
I1 => \weight_reg[1]_0\(12),
O => \weight[1][12]_i_5_n_0\
);
\weight[1][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(7),
I1 => \weight_reg[1]_0\(7),
O => \weight[1][4]_i_2_n_0\
);
\weight[1][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(6),
I1 => \weight_reg[1]_0\(6),
O => \weight[1][4]_i_3_n_0\
);
\weight[1][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(5),
I1 => \weight_reg[1]_0\(5),
O => \weight[1][4]_i_4_n_0\
);
\weight[1][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(4),
I1 => \weight_reg[1]_0\(4),
O => \weight[1][4]_i_5_n_0\
);
\weight[1][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(11),
I1 => \weight_reg[1]_0\(11),
O => \weight[1][8]_i_2_n_0\
);
\weight[1][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(10),
I1 => \weight_reg[1]_0\(10),
O => \weight[1][8]_i_3_n_0\
);
\weight[1][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(9),
I1 => \weight_reg[1]_0\(9),
O => \weight[1][8]_i_4_n_0\
);
\weight[1][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(8),
I1 => \weight_reg[1]_0\(8),
O => \weight[1][8]_i_5_n_0\
);
\weight[2][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_88\,
I1 => \weight_reg[2]_1\(3),
O => \weight[2][0]_i_2_n_0\
);
\weight[2][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_89\,
I1 => \weight_reg[2]_1\(2),
O => \weight[2][0]_i_3_n_0\
);
\weight[2][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_90\,
I1 => \weight_reg[2]_1\(1),
O => \weight[2][0]_i_4_n_0\
);
\weight[2][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_91\,
I1 => \weight_reg[2]_1\(0),
O => \weight[2][0]_i_5_n_0\
);
\weight[2][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_76\,
I1 => \weight_reg[2]_1\(15),
O => \weight[2][12]_i_2_n_0\
);
\weight[2][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_77\,
I1 => \weight_reg[2]_1\(14),
O => \weight[2][12]_i_3_n_0\
);
\weight[2][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_78\,
I1 => \weight_reg[2]_1\(13),
O => \weight[2][12]_i_4_n_0\
);
\weight[2][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_79\,
I1 => \weight_reg[2]_1\(12),
O => \weight[2][12]_i_5_n_0\
);
\weight[2][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_84\,
I1 => \weight_reg[2]_1\(7),
O => \weight[2][4]_i_2_n_0\
);
\weight[2][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_85\,
I1 => \weight_reg[2]_1\(6),
O => \weight[2][4]_i_3_n_0\
);
\weight[2][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_86\,
I1 => \weight_reg[2]_1\(5),
O => \weight[2][4]_i_4_n_0\
);
\weight[2][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_87\,
I1 => \weight_reg[2]_1\(4),
O => \weight[2][4]_i_5_n_0\
);
\weight[2][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_80\,
I1 => \weight_reg[2]_1\(11),
O => \weight[2][8]_i_2_n_0\
);
\weight[2][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_81\,
I1 => \weight_reg[2]_1\(10),
O => \weight[2][8]_i_3_n_0\
);
\weight[2][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_82\,
I1 => \weight_reg[2]_1\(9),
O => \weight[2][8]_i_4_n_0\
);
\weight[2][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_83\,
I1 => \weight_reg[2]_1\(8),
O => \weight[2][8]_i_5_n_0\
);
\weight[3][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_88\,
I1 => \weight_reg[3]_2\(3),
O => \weight[3][0]_i_2_n_0\
);
\weight[3][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_89\,
I1 => \weight_reg[3]_2\(2),
O => \weight[3][0]_i_3_n_0\
);
\weight[3][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_90\,
I1 => \weight_reg[3]_2\(1),
O => \weight[3][0]_i_4_n_0\
);
\weight[3][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_91\,
I1 => \weight_reg[3]_2\(0),
O => \weight[3][0]_i_5_n_0\
);
\weight[3][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_76\,
I1 => \weight_reg[3]_2\(15),
O => \weight[3][12]_i_2_n_0\
);
\weight[3][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_77\,
I1 => \weight_reg[3]_2\(14),
O => \weight[3][12]_i_3_n_0\
);
\weight[3][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_78\,
I1 => \weight_reg[3]_2\(13),
O => \weight[3][12]_i_4_n_0\
);
\weight[3][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_79\,
I1 => \weight_reg[3]_2\(12),
O => \weight[3][12]_i_5_n_0\
);
\weight[3][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_84\,
I1 => \weight_reg[3]_2\(7),
O => \weight[3][4]_i_2_n_0\
);
\weight[3][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_85\,
I1 => \weight_reg[3]_2\(6),
O => \weight[3][4]_i_3_n_0\
);
\weight[3][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_86\,
I1 => \weight_reg[3]_2\(5),
O => \weight[3][4]_i_4_n_0\
);
\weight[3][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_87\,
I1 => \weight_reg[3]_2\(4),
O => \weight[3][4]_i_5_n_0\
);
\weight[3][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_80\,
I1 => \weight_reg[3]_2\(11),
O => \weight[3][8]_i_2_n_0\
);
\weight[3][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_81\,
I1 => \weight_reg[3]_2\(10),
O => \weight[3][8]_i_3_n_0\
);
\weight[3][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_82\,
I1 => \weight_reg[3]_2\(9),
O => \weight[3][8]_i_4_n_0\
);
\weight[3][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_83\,
I1 => \weight_reg[3]_2\(8),
O => \weight[3][8]_i_5_n_0\
);
\weight[4][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_88\,
I1 => \weight_reg[4]_3\(3),
O => \weight[4][0]_i_2_n_0\
);
\weight[4][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_89\,
I1 => \weight_reg[4]_3\(2),
O => \weight[4][0]_i_3_n_0\
);
\weight[4][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_90\,
I1 => \weight_reg[4]_3\(1),
O => \weight[4][0]_i_4_n_0\
);
\weight[4][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_91\,
I1 => \weight_reg[4]_3\(0),
O => \weight[4][0]_i_5_n_0\
);
\weight[4][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_76\,
I1 => \weight_reg[4]_3\(15),
O => \weight[4][12]_i_2_n_0\
);
\weight[4][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_77\,
I1 => \weight_reg[4]_3\(14),
O => \weight[4][12]_i_3_n_0\
);
\weight[4][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_78\,
I1 => \weight_reg[4]_3\(13),
O => \weight[4][12]_i_4_n_0\
);
\weight[4][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_79\,
I1 => \weight_reg[4]_3\(12),
O => \weight[4][12]_i_5_n_0\
);
\weight[4][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_84\,
I1 => \weight_reg[4]_3\(7),
O => \weight[4][4]_i_2_n_0\
);
\weight[4][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_85\,
I1 => \weight_reg[4]_3\(6),
O => \weight[4][4]_i_3_n_0\
);
\weight[4][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_86\,
I1 => \weight_reg[4]_3\(5),
O => \weight[4][4]_i_4_n_0\
);
\weight[4][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_87\,
I1 => \weight_reg[4]_3\(4),
O => \weight[4][4]_i_5_n_0\
);
\weight[4][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_80\,
I1 => \weight_reg[4]_3\(11),
O => \weight[4][8]_i_2_n_0\
);
\weight[4][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_81\,
I1 => \weight_reg[4]_3\(10),
O => \weight[4][8]_i_3_n_0\
);
\weight[4][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_82\,
I1 => \weight_reg[4]_3\(9),
O => \weight[4][8]_i_4_n_0\
);
\weight[4][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_83\,
I1 => \weight_reg[4]_3\(8),
O => \weight[4][8]_i_5_n_0\
);
\weight[5][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_88\,
I1 => \weight_reg[5]_4\(3),
O => \weight[5][0]_i_2_n_0\
);
\weight[5][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_89\,
I1 => \weight_reg[5]_4\(2),
O => \weight[5][0]_i_3_n_0\
);
\weight[5][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_90\,
I1 => \weight_reg[5]_4\(1),
O => \weight[5][0]_i_4_n_0\
);
\weight[5][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_91\,
I1 => \weight_reg[5]_4\(0),
O => \weight[5][0]_i_5_n_0\
);
\weight[5][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_76\,
I1 => \weight_reg[5]_4\(15),
O => \weight[5][12]_i_2_n_0\
);
\weight[5][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_77\,
I1 => \weight_reg[5]_4\(14),
O => \weight[5][12]_i_3_n_0\
);
\weight[5][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_78\,
I1 => \weight_reg[5]_4\(13),
O => \weight[5][12]_i_4_n_0\
);
\weight[5][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_79\,
I1 => \weight_reg[5]_4\(12),
O => \weight[5][12]_i_5_n_0\
);
\weight[5][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_84\,
I1 => \weight_reg[5]_4\(7),
O => \weight[5][4]_i_2_n_0\
);
\weight[5][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_85\,
I1 => \weight_reg[5]_4\(6),
O => \weight[5][4]_i_3_n_0\
);
\weight[5][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_86\,
I1 => \weight_reg[5]_4\(5),
O => \weight[5][4]_i_4_n_0\
);
\weight[5][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_87\,
I1 => \weight_reg[5]_4\(4),
O => \weight[5][4]_i_5_n_0\
);
\weight[5][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_80\,
I1 => \weight_reg[5]_4\(11),
O => \weight[5][8]_i_2_n_0\
);
\weight[5][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_81\,
I1 => \weight_reg[5]_4\(10),
O => \weight[5][8]_i_3_n_0\
);
\weight[5][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_82\,
I1 => \weight_reg[5]_4\(9),
O => \weight[5][8]_i_4_n_0\
);
\weight[5][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_83\,
I1 => \weight_reg[5]_4\(8),
O => \weight[5][8]_i_5_n_0\
);
\weight[6][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_88\,
I1 => \weight_reg[6]_5\(3),
O => \weight[6][0]_i_2_n_0\
);
\weight[6][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_89\,
I1 => \weight_reg[6]_5\(2),
O => \weight[6][0]_i_3_n_0\
);
\weight[6][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_90\,
I1 => \weight_reg[6]_5\(1),
O => \weight[6][0]_i_4_n_0\
);
\weight[6][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_91\,
I1 => \weight_reg[6]_5\(0),
O => \weight[6][0]_i_5_n_0\
);
\weight[6][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_76\,
I1 => \weight_reg[6]_5\(15),
O => \weight[6][12]_i_2_n_0\
);
\weight[6][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_77\,
I1 => \weight_reg[6]_5\(14),
O => \weight[6][12]_i_3_n_0\
);
\weight[6][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_78\,
I1 => \weight_reg[6]_5\(13),
O => \weight[6][12]_i_4_n_0\
);
\weight[6][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_79\,
I1 => \weight_reg[6]_5\(12),
O => \weight[6][12]_i_5_n_0\
);
\weight[6][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_84\,
I1 => \weight_reg[6]_5\(7),
O => \weight[6][4]_i_2_n_0\
);
\weight[6][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_85\,
I1 => \weight_reg[6]_5\(6),
O => \weight[6][4]_i_3_n_0\
);
\weight[6][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_86\,
I1 => \weight_reg[6]_5\(5),
O => \weight[6][4]_i_4_n_0\
);
\weight[6][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_87\,
I1 => \weight_reg[6]_5\(4),
O => \weight[6][4]_i_5_n_0\
);
\weight[6][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_80\,
I1 => \weight_reg[6]_5\(11),
O => \weight[6][8]_i_2_n_0\
);
\weight[6][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_81\,
I1 => \weight_reg[6]_5\(10),
O => \weight[6][8]_i_3_n_0\
);
\weight[6][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_82\,
I1 => \weight_reg[6]_5\(9),
O => \weight[6][8]_i_4_n_0\
);
\weight[6][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_83\,
I1 => \weight_reg[6]_5\(8),
O => \weight[6][8]_i_5_n_0\
);
\weight[7][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_88\,
I1 => \weight_reg[7]_6\(3),
O => \weight[7][0]_i_2_n_0\
);
\weight[7][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_89\,
I1 => \weight_reg[7]_6\(2),
O => \weight[7][0]_i_3_n_0\
);
\weight[7][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_90\,
I1 => \weight_reg[7]_6\(1),
O => \weight[7][0]_i_4_n_0\
);
\weight[7][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_91\,
I1 => \weight_reg[7]_6\(0),
O => \weight[7][0]_i_5_n_0\
);
\weight[7][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_76\,
I1 => \weight_reg[7]_6\(15),
O => \weight[7][12]_i_2_n_0\
);
\weight[7][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_77\,
I1 => \weight_reg[7]_6\(14),
O => \weight[7][12]_i_3_n_0\
);
\weight[7][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_78\,
I1 => \weight_reg[7]_6\(13),
O => \weight[7][12]_i_4_n_0\
);
\weight[7][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_79\,
I1 => \weight_reg[7]_6\(12),
O => \weight[7][12]_i_5_n_0\
);
\weight[7][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_84\,
I1 => \weight_reg[7]_6\(7),
O => \weight[7][4]_i_2_n_0\
);
\weight[7][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_85\,
I1 => \weight_reg[7]_6\(6),
O => \weight[7][4]_i_3_n_0\
);
\weight[7][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_86\,
I1 => \weight_reg[7]_6\(5),
O => \weight[7][4]_i_4_n_0\
);
\weight[7][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_87\,
I1 => \weight_reg[7]_6\(4),
O => \weight[7][4]_i_5_n_0\
);
\weight[7][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_80\,
I1 => \weight_reg[7]_6\(11),
O => \weight[7][8]_i_2_n_0\
);
\weight[7][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_81\,
I1 => \weight_reg[7]_6\(10),
O => \weight[7][8]_i_3_n_0\
);
\weight[7][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_82\,
I1 => \weight_reg[7]_6\(9),
O => \weight[7][8]_i_4_n_0\
);
\weight[7][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_83\,
I1 => \weight_reg[7]_6\(8),
O => \weight[7][8]_i_5_n_0\
);
\weight[8][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_88\,
I1 => \weight_reg[8]_7\(3),
O => \weight[8][0]_i_2_n_0\
);
\weight[8][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_89\,
I1 => \weight_reg[8]_7\(2),
O => \weight[8][0]_i_3_n_0\
);
\weight[8][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_90\,
I1 => \weight_reg[8]_7\(1),
O => \weight[8][0]_i_4_n_0\
);
\weight[8][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_91\,
I1 => \weight_reg[8]_7\(0),
O => \weight[8][0]_i_5_n_0\
);
\weight[8][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_76\,
I1 => \weight_reg[8]_7\(15),
O => \weight[8][12]_i_2_n_0\
);
\weight[8][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_77\,
I1 => \weight_reg[8]_7\(14),
O => \weight[8][12]_i_3_n_0\
);
\weight[8][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_78\,
I1 => \weight_reg[8]_7\(13),
O => \weight[8][12]_i_4_n_0\
);
\weight[8][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_79\,
I1 => \weight_reg[8]_7\(12),
O => \weight[8][12]_i_5_n_0\
);
\weight[8][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_84\,
I1 => \weight_reg[8]_7\(7),
O => \weight[8][4]_i_2_n_0\
);
\weight[8][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_85\,
I1 => \weight_reg[8]_7\(6),
O => \weight[8][4]_i_3_n_0\
);
\weight[8][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_86\,
I1 => \weight_reg[8]_7\(5),
O => \weight[8][4]_i_4_n_0\
);
\weight[8][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_87\,
I1 => \weight_reg[8]_7\(4),
O => \weight[8][4]_i_5_n_0\
);
\weight[8][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_80\,
I1 => \weight_reg[8]_7\(11),
O => \weight[8][8]_i_2_n_0\
);
\weight[8][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_81\,
I1 => \weight_reg[8]_7\(10),
O => \weight[8][8]_i_3_n_0\
);
\weight[8][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_82\,
I1 => \weight_reg[8]_7\(9),
O => \weight[8][8]_i_4_n_0\
);
\weight[8][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_83\,
I1 => \weight_reg[8]_7\(8),
O => \weight[8][8]_i_5_n_0\
);
\weight[9][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_88\,
I1 => \weight_reg[9]_8\(3),
O => \weight[9][0]_i_2_n_0\
);
\weight[9][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_89\,
I1 => \weight_reg[9]_8\(2),
O => \weight[9][0]_i_3_n_0\
);
\weight[9][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_90\,
I1 => \weight_reg[9]_8\(1),
O => \weight[9][0]_i_4_n_0\
);
\weight[9][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_91\,
I1 => \weight_reg[9]_8\(0),
O => \weight[9][0]_i_5_n_0\
);
\weight[9][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_76\,
I1 => \weight_reg[9]_8\(15),
O => \weight[9][12]_i_2_n_0\
);
\weight[9][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_77\,
I1 => \weight_reg[9]_8\(14),
O => \weight[9][12]_i_3_n_0\
);
\weight[9][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_78\,
I1 => \weight_reg[9]_8\(13),
O => \weight[9][12]_i_4_n_0\
);
\weight[9][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_79\,
I1 => \weight_reg[9]_8\(12),
O => \weight[9][12]_i_5_n_0\
);
\weight[9][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_84\,
I1 => \weight_reg[9]_8\(7),
O => \weight[9][4]_i_2_n_0\
);
\weight[9][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_85\,
I1 => \weight_reg[9]_8\(6),
O => \weight[9][4]_i_3_n_0\
);
\weight[9][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_86\,
I1 => \weight_reg[9]_8\(5),
O => \weight[9][4]_i_4_n_0\
);
\weight[9][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_87\,
I1 => \weight_reg[9]_8\(4),
O => \weight[9][4]_i_5_n_0\
);
\weight[9][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_80\,
I1 => \weight_reg[9]_8\(11),
O => \weight[9][8]_i_2_n_0\
);
\weight[9][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_81\,
I1 => \weight_reg[9]_8\(10),
O => \weight[9][8]_i_3_n_0\
);
\weight[9][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_82\,
I1 => \weight_reg[9]_8\(9),
O => \weight[9][8]_i_4_n_0\
);
\weight[9][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_83\,
I1 => \weight_reg[9]_8\(8),
O => \weight[9][8]_i_5_n_0\
);
\weight_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_7\,
Q => \weight_reg[0]_15\(0)
);
\weight_reg[0][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[0][0]_i_1_n_0\,
CO(2) => \weight_reg[0][0]_i_1_n_1\,
CO(1) => \weight_reg[0][0]_i_1_n_2\,
CO(0) => \weight_reg[0][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_88\,
DI(2) => \ARG__29_n_89\,
DI(1) => \ARG__29_n_90\,
DI(0) => \ARG__29_n_91\,
O(3) => \weight_reg[0][0]_i_1_n_4\,
O(2) => \weight_reg[0][0]_i_1_n_5\,
O(1) => \weight_reg[0][0]_i_1_n_6\,
O(0) => \weight_reg[0][0]_i_1_n_7\,
S(3) => \weight[0][0]_i_2_n_0\,
S(2) => \weight[0][0]_i_3_n_0\,
S(1) => \weight[0][0]_i_4_n_0\,
S(0) => \weight[0][0]_i_5_n_0\
);
\weight_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_5\,
Q => \weight_reg[0]_15\(10)
);
\weight_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_4\,
Q => \weight_reg[0]_15\(11)
);
\weight_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_7\,
Q => \weight_reg[0]_15\(12)
);
\weight_reg[0][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[0][12]_i_1_n_1\,
CO(1) => \weight_reg[0][12]_i_1_n_2\,
CO(0) => \weight_reg[0][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__29_n_77\,
DI(1) => \ARG__29_n_78\,
DI(0) => \ARG__29_n_79\,
O(3) => \weight_reg[0][12]_i_1_n_4\,
O(2) => \weight_reg[0][12]_i_1_n_5\,
O(1) => \weight_reg[0][12]_i_1_n_6\,
O(0) => \weight_reg[0][12]_i_1_n_7\,
S(3) => \weight[0][12]_i_2_n_0\,
S(2) => \weight[0][12]_i_3_n_0\,
S(1) => \weight[0][12]_i_4_n_0\,
S(0) => \weight[0][12]_i_5_n_0\
);
\weight_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_6\,
Q => \weight_reg[0]_15\(13)
);
\weight_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_5\,
Q => \weight_reg[0]_15\(14)
);
\weight_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_4\,
Q => \weight_reg[0]_15\(15)
);
\weight_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_6\,
Q => \weight_reg[0]_15\(1)
);
\weight_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_5\,
Q => \weight_reg[0]_15\(2)
);
\weight_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_4\,
Q => \weight_reg[0]_15\(3)
);
\weight_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_7\,
Q => \weight_reg[0]_15\(4)
);
\weight_reg[0][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][0]_i_1_n_0\,
CO(3) => \weight_reg[0][4]_i_1_n_0\,
CO(2) => \weight_reg[0][4]_i_1_n_1\,
CO(1) => \weight_reg[0][4]_i_1_n_2\,
CO(0) => \weight_reg[0][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_84\,
DI(2) => \ARG__29_n_85\,
DI(1) => \ARG__29_n_86\,
DI(0) => \ARG__29_n_87\,
O(3) => \weight_reg[0][4]_i_1_n_4\,
O(2) => \weight_reg[0][4]_i_1_n_5\,
O(1) => \weight_reg[0][4]_i_1_n_6\,
O(0) => \weight_reg[0][4]_i_1_n_7\,
S(3) => \weight[0][4]_i_2_n_0\,
S(2) => \weight[0][4]_i_3_n_0\,
S(1) => \weight[0][4]_i_4_n_0\,
S(0) => \weight[0][4]_i_5_n_0\
);
\weight_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_6\,
Q => \weight_reg[0]_15\(5)
);
\weight_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_5\,
Q => \weight_reg[0]_15\(6)
);
\weight_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_4\,
Q => \weight_reg[0]_15\(7)
);
\weight_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_7\,
Q => \weight_reg[0]_15\(8)
);
\weight_reg[0][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][4]_i_1_n_0\,
CO(3) => \weight_reg[0][8]_i_1_n_0\,
CO(2) => \weight_reg[0][8]_i_1_n_1\,
CO(1) => \weight_reg[0][8]_i_1_n_2\,
CO(0) => \weight_reg[0][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_80\,
DI(2) => \ARG__29_n_81\,
DI(1) => \ARG__29_n_82\,
DI(0) => \ARG__29_n_83\,
O(3) => \weight_reg[0][8]_i_1_n_4\,
O(2) => \weight_reg[0][8]_i_1_n_5\,
O(1) => \weight_reg[0][8]_i_1_n_6\,
O(0) => \weight_reg[0][8]_i_1_n_7\,
S(3) => \weight[0][8]_i_2_n_0\,
S(2) => \weight[0][8]_i_3_n_0\,
S(1) => \weight[0][8]_i_4_n_0\,
S(0) => \weight[0][8]_i_5_n_0\
);
\weight_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_6\,
Q => \weight_reg[0]_15\(9)
);
\weight_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_7\,
Q => \weight_reg[10]_9\(0)
);
\weight_reg[10][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[10][0]_i_1_n_0\,
CO(2) => \weight_reg[10][0]_i_1_n_1\,
CO(1) => \weight_reg[10][0]_i_1_n_2\,
CO(0) => \weight_reg[10][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_88\,
DI(2) => \ARG__17_n_89\,
DI(1) => \ARG__17_n_90\,
DI(0) => \ARG__17_n_91\,
O(3) => \weight_reg[10][0]_i_1_n_4\,
O(2) => \weight_reg[10][0]_i_1_n_5\,
O(1) => \weight_reg[10][0]_i_1_n_6\,
O(0) => \weight_reg[10][0]_i_1_n_7\,
S(3) => \weight[10][0]_i_2_n_0\,
S(2) => \weight[10][0]_i_3_n_0\,
S(1) => \weight[10][0]_i_4_n_0\,
S(0) => \weight[10][0]_i_5_n_0\
);
\weight_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_5\,
Q => \weight_reg[10]_9\(10)
);
\weight_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_4\,
Q => \weight_reg[10]_9\(11)
);
\weight_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_7\,
Q => \weight_reg[10]_9\(12)
);
\weight_reg[10][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[10][12]_i_1_n_1\,
CO(1) => \weight_reg[10][12]_i_1_n_2\,
CO(0) => \weight_reg[10][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__17_n_77\,
DI(1) => \ARG__17_n_78\,
DI(0) => \ARG__17_n_79\,
O(3) => \weight_reg[10][12]_i_1_n_4\,
O(2) => \weight_reg[10][12]_i_1_n_5\,
O(1) => \weight_reg[10][12]_i_1_n_6\,
O(0) => \weight_reg[10][12]_i_1_n_7\,
S(3) => \weight[10][12]_i_2_n_0\,
S(2) => \weight[10][12]_i_3_n_0\,
S(1) => \weight[10][12]_i_4_n_0\,
S(0) => \weight[10][12]_i_5_n_0\
);
\weight_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_6\,
Q => \weight_reg[10]_9\(13)
);
\weight_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_5\,
Q => \weight_reg[10]_9\(14)
);
\weight_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_4\,
Q => \weight_reg[10]_9\(15)
);
\weight_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_6\,
Q => \weight_reg[10]_9\(1)
);
\weight_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_5\,
Q => \weight_reg[10]_9\(2)
);
\weight_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_4\,
Q => \weight_reg[10]_9\(3)
);
\weight_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_7\,
Q => \weight_reg[10]_9\(4)
);
\weight_reg[10][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][0]_i_1_n_0\,
CO(3) => \weight_reg[10][4]_i_1_n_0\,
CO(2) => \weight_reg[10][4]_i_1_n_1\,
CO(1) => \weight_reg[10][4]_i_1_n_2\,
CO(0) => \weight_reg[10][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_84\,
DI(2) => \ARG__17_n_85\,
DI(1) => \ARG__17_n_86\,
DI(0) => \ARG__17_n_87\,
O(3) => \weight_reg[10][4]_i_1_n_4\,
O(2) => \weight_reg[10][4]_i_1_n_5\,
O(1) => \weight_reg[10][4]_i_1_n_6\,
O(0) => \weight_reg[10][4]_i_1_n_7\,
S(3) => \weight[10][4]_i_2_n_0\,
S(2) => \weight[10][4]_i_3_n_0\,
S(1) => \weight[10][4]_i_4_n_0\,
S(0) => \weight[10][4]_i_5_n_0\
);
\weight_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_6\,
Q => \weight_reg[10]_9\(5)
);
\weight_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_5\,
Q => \weight_reg[10]_9\(6)
);
\weight_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_4\,
Q => \weight_reg[10]_9\(7)
);
\weight_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_7\,
Q => \weight_reg[10]_9\(8)
);
\weight_reg[10][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][4]_i_1_n_0\,
CO(3) => \weight_reg[10][8]_i_1_n_0\,
CO(2) => \weight_reg[10][8]_i_1_n_1\,
CO(1) => \weight_reg[10][8]_i_1_n_2\,
CO(0) => \weight_reg[10][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_80\,
DI(2) => \ARG__17_n_81\,
DI(1) => \ARG__17_n_82\,
DI(0) => \ARG__17_n_83\,
O(3) => \weight_reg[10][8]_i_1_n_4\,
O(2) => \weight_reg[10][8]_i_1_n_5\,
O(1) => \weight_reg[10][8]_i_1_n_6\,
O(0) => \weight_reg[10][8]_i_1_n_7\,
S(3) => \weight[10][8]_i_2_n_0\,
S(2) => \weight[10][8]_i_3_n_0\,
S(1) => \weight[10][8]_i_4_n_0\,
S(0) => \weight[10][8]_i_5_n_0\
);
\weight_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_6\,
Q => \weight_reg[10]_9\(9)
);
\weight_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_7\,
Q => \weight_reg[11]_10\(0)
);
\weight_reg[11][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[11][0]_i_1_n_0\,
CO(2) => \weight_reg[11][0]_i_1_n_1\,
CO(1) => \weight_reg[11][0]_i_1_n_2\,
CO(0) => \weight_reg[11][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_88\,
DI(2) => \ARG__19_n_89\,
DI(1) => \ARG__19_n_90\,
DI(0) => \ARG__19_n_91\,
O(3) => \weight_reg[11][0]_i_1_n_4\,
O(2) => \weight_reg[11][0]_i_1_n_5\,
O(1) => \weight_reg[11][0]_i_1_n_6\,
O(0) => \weight_reg[11][0]_i_1_n_7\,
S(3) => \weight[11][0]_i_2_n_0\,
S(2) => \weight[11][0]_i_3_n_0\,
S(1) => \weight[11][0]_i_4_n_0\,
S(0) => \weight[11][0]_i_5_n_0\
);
\weight_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_5\,
Q => \weight_reg[11]_10\(10)
);
\weight_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_4\,
Q => \weight_reg[11]_10\(11)
);
\weight_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_7\,
Q => \weight_reg[11]_10\(12)
);
\weight_reg[11][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[11][12]_i_1_n_1\,
CO(1) => \weight_reg[11][12]_i_1_n_2\,
CO(0) => \weight_reg[11][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__19_n_77\,
DI(1) => \ARG__19_n_78\,
DI(0) => \ARG__19_n_79\,
O(3) => \weight_reg[11][12]_i_1_n_4\,
O(2) => \weight_reg[11][12]_i_1_n_5\,
O(1) => \weight_reg[11][12]_i_1_n_6\,
O(0) => \weight_reg[11][12]_i_1_n_7\,
S(3) => \weight[11][12]_i_2_n_0\,
S(2) => \weight[11][12]_i_3_n_0\,
S(1) => \weight[11][12]_i_4_n_0\,
S(0) => \weight[11][12]_i_5_n_0\
);
\weight_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_6\,
Q => \weight_reg[11]_10\(13)
);
\weight_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_5\,
Q => \weight_reg[11]_10\(14)
);
\weight_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_4\,
Q => \weight_reg[11]_10\(15)
);
\weight_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_6\,
Q => \weight_reg[11]_10\(1)
);
\weight_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_5\,
Q => \weight_reg[11]_10\(2)
);
\weight_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_4\,
Q => \weight_reg[11]_10\(3)
);
\weight_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_7\,
Q => \weight_reg[11]_10\(4)
);
\weight_reg[11][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][0]_i_1_n_0\,
CO(3) => \weight_reg[11][4]_i_1_n_0\,
CO(2) => \weight_reg[11][4]_i_1_n_1\,
CO(1) => \weight_reg[11][4]_i_1_n_2\,
CO(0) => \weight_reg[11][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_84\,
DI(2) => \ARG__19_n_85\,
DI(1) => \ARG__19_n_86\,
DI(0) => \ARG__19_n_87\,
O(3) => \weight_reg[11][4]_i_1_n_4\,
O(2) => \weight_reg[11][4]_i_1_n_5\,
O(1) => \weight_reg[11][4]_i_1_n_6\,
O(0) => \weight_reg[11][4]_i_1_n_7\,
S(3) => \weight[11][4]_i_2_n_0\,
S(2) => \weight[11][4]_i_3_n_0\,
S(1) => \weight[11][4]_i_4_n_0\,
S(0) => \weight[11][4]_i_5_n_0\
);
\weight_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_6\,
Q => \weight_reg[11]_10\(5)
);
\weight_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_5\,
Q => \weight_reg[11]_10\(6)
);
\weight_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_4\,
Q => \weight_reg[11]_10\(7)
);
\weight_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_7\,
Q => \weight_reg[11]_10\(8)
);
\weight_reg[11][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][4]_i_1_n_0\,
CO(3) => \weight_reg[11][8]_i_1_n_0\,
CO(2) => \weight_reg[11][8]_i_1_n_1\,
CO(1) => \weight_reg[11][8]_i_1_n_2\,
CO(0) => \weight_reg[11][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_80\,
DI(2) => \ARG__19_n_81\,
DI(1) => \ARG__19_n_82\,
DI(0) => \ARG__19_n_83\,
O(3) => \weight_reg[11][8]_i_1_n_4\,
O(2) => \weight_reg[11][8]_i_1_n_5\,
O(1) => \weight_reg[11][8]_i_1_n_6\,
O(0) => \weight_reg[11][8]_i_1_n_7\,
S(3) => \weight[11][8]_i_2_n_0\,
S(2) => \weight[11][8]_i_3_n_0\,
S(1) => \weight[11][8]_i_4_n_0\,
S(0) => \weight[11][8]_i_5_n_0\
);
\weight_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_6\,
Q => \weight_reg[11]_10\(9)
);
\weight_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_7\,
Q => \weight_reg[12]_11\(0)
);
\weight_reg[12][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[12][0]_i_1_n_0\,
CO(2) => \weight_reg[12][0]_i_1_n_1\,
CO(1) => \weight_reg[12][0]_i_1_n_2\,
CO(0) => \weight_reg[12][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_88\,
DI(2) => \ARG__21_n_89\,
DI(1) => \ARG__21_n_90\,
DI(0) => \ARG__21_n_91\,
O(3) => \weight_reg[12][0]_i_1_n_4\,
O(2) => \weight_reg[12][0]_i_1_n_5\,
O(1) => \weight_reg[12][0]_i_1_n_6\,
O(0) => \weight_reg[12][0]_i_1_n_7\,
S(3) => \weight[12][0]_i_2_n_0\,
S(2) => \weight[12][0]_i_3_n_0\,
S(1) => \weight[12][0]_i_4_n_0\,
S(0) => \weight[12][0]_i_5_n_0\
);
\weight_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_5\,
Q => \weight_reg[12]_11\(10)
);
\weight_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_4\,
Q => \weight_reg[12]_11\(11)
);
\weight_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_7\,
Q => \weight_reg[12]_11\(12)
);
\weight_reg[12][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[12][12]_i_1_n_1\,
CO(1) => \weight_reg[12][12]_i_1_n_2\,
CO(0) => \weight_reg[12][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__21_n_77\,
DI(1) => \ARG__21_n_78\,
DI(0) => \ARG__21_n_79\,
O(3) => \weight_reg[12][12]_i_1_n_4\,
O(2) => \weight_reg[12][12]_i_1_n_5\,
O(1) => \weight_reg[12][12]_i_1_n_6\,
O(0) => \weight_reg[12][12]_i_1_n_7\,
S(3) => \weight[12][12]_i_2_n_0\,
S(2) => \weight[12][12]_i_3_n_0\,
S(1) => \weight[12][12]_i_4_n_0\,
S(0) => \weight[12][12]_i_5_n_0\
);
\weight_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_6\,
Q => \weight_reg[12]_11\(13)
);
\weight_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_5\,
Q => \weight_reg[12]_11\(14)
);
\weight_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_4\,
Q => \weight_reg[12]_11\(15)
);
\weight_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_6\,
Q => \weight_reg[12]_11\(1)
);
\weight_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_5\,
Q => \weight_reg[12]_11\(2)
);
\weight_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_4\,
Q => \weight_reg[12]_11\(3)
);
\weight_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_7\,
Q => \weight_reg[12]_11\(4)
);
\weight_reg[12][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][0]_i_1_n_0\,
CO(3) => \weight_reg[12][4]_i_1_n_0\,
CO(2) => \weight_reg[12][4]_i_1_n_1\,
CO(1) => \weight_reg[12][4]_i_1_n_2\,
CO(0) => \weight_reg[12][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_84\,
DI(2) => \ARG__21_n_85\,
DI(1) => \ARG__21_n_86\,
DI(0) => \ARG__21_n_87\,
O(3) => \weight_reg[12][4]_i_1_n_4\,
O(2) => \weight_reg[12][4]_i_1_n_5\,
O(1) => \weight_reg[12][4]_i_1_n_6\,
O(0) => \weight_reg[12][4]_i_1_n_7\,
S(3) => \weight[12][4]_i_2_n_0\,
S(2) => \weight[12][4]_i_3_n_0\,
S(1) => \weight[12][4]_i_4_n_0\,
S(0) => \weight[12][4]_i_5_n_0\
);
\weight_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_6\,
Q => \weight_reg[12]_11\(5)
);
\weight_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_5\,
Q => \weight_reg[12]_11\(6)
);
\weight_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_4\,
Q => \weight_reg[12]_11\(7)
);
\weight_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_7\,
Q => \weight_reg[12]_11\(8)
);
\weight_reg[12][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][4]_i_1_n_0\,
CO(3) => \weight_reg[12][8]_i_1_n_0\,
CO(2) => \weight_reg[12][8]_i_1_n_1\,
CO(1) => \weight_reg[12][8]_i_1_n_2\,
CO(0) => \weight_reg[12][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_80\,
DI(2) => \ARG__21_n_81\,
DI(1) => \ARG__21_n_82\,
DI(0) => \ARG__21_n_83\,
O(3) => \weight_reg[12][8]_i_1_n_4\,
O(2) => \weight_reg[12][8]_i_1_n_5\,
O(1) => \weight_reg[12][8]_i_1_n_6\,
O(0) => \weight_reg[12][8]_i_1_n_7\,
S(3) => \weight[12][8]_i_2_n_0\,
S(2) => \weight[12][8]_i_3_n_0\,
S(1) => \weight[12][8]_i_4_n_0\,
S(0) => \weight[12][8]_i_5_n_0\
);
\weight_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_6\,
Q => \weight_reg[12]_11\(9)
);
\weight_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_7\,
Q => \weight_reg[13]_12\(0)
);
\weight_reg[13][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[13][0]_i_1_n_0\,
CO(2) => \weight_reg[13][0]_i_1_n_1\,
CO(1) => \weight_reg[13][0]_i_1_n_2\,
CO(0) => \weight_reg[13][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_88\,
DI(2) => \ARG__23_n_89\,
DI(1) => \ARG__23_n_90\,
DI(0) => \ARG__23_n_91\,
O(3) => \weight_reg[13][0]_i_1_n_4\,
O(2) => \weight_reg[13][0]_i_1_n_5\,
O(1) => \weight_reg[13][0]_i_1_n_6\,
O(0) => \weight_reg[13][0]_i_1_n_7\,
S(3) => \weight[13][0]_i_2_n_0\,
S(2) => \weight[13][0]_i_3_n_0\,
S(1) => \weight[13][0]_i_4_n_0\,
S(0) => \weight[13][0]_i_5_n_0\
);
\weight_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_5\,
Q => \weight_reg[13]_12\(10)
);
\weight_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_4\,
Q => \weight_reg[13]_12\(11)
);
\weight_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_7\,
Q => \weight_reg[13]_12\(12)
);
\weight_reg[13][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[13][12]_i_1_n_1\,
CO(1) => \weight_reg[13][12]_i_1_n_2\,
CO(0) => \weight_reg[13][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__23_n_77\,
DI(1) => \ARG__23_n_78\,
DI(0) => \ARG__23_n_79\,
O(3) => \weight_reg[13][12]_i_1_n_4\,
O(2) => \weight_reg[13][12]_i_1_n_5\,
O(1) => \weight_reg[13][12]_i_1_n_6\,
O(0) => \weight_reg[13][12]_i_1_n_7\,
S(3) => \weight[13][12]_i_2_n_0\,
S(2) => \weight[13][12]_i_3_n_0\,
S(1) => \weight[13][12]_i_4_n_0\,
S(0) => \weight[13][12]_i_5_n_0\
);
\weight_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_6\,
Q => \weight_reg[13]_12\(13)
);
\weight_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_5\,
Q => \weight_reg[13]_12\(14)
);
\weight_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_4\,
Q => \weight_reg[13]_12\(15)
);
\weight_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_6\,
Q => \weight_reg[13]_12\(1)
);
\weight_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_5\,
Q => \weight_reg[13]_12\(2)
);
\weight_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_4\,
Q => \weight_reg[13]_12\(3)
);
\weight_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_7\,
Q => \weight_reg[13]_12\(4)
);
\weight_reg[13][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][0]_i_1_n_0\,
CO(3) => \weight_reg[13][4]_i_1_n_0\,
CO(2) => \weight_reg[13][4]_i_1_n_1\,
CO(1) => \weight_reg[13][4]_i_1_n_2\,
CO(0) => \weight_reg[13][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_84\,
DI(2) => \ARG__23_n_85\,
DI(1) => \ARG__23_n_86\,
DI(0) => \ARG__23_n_87\,
O(3) => \weight_reg[13][4]_i_1_n_4\,
O(2) => \weight_reg[13][4]_i_1_n_5\,
O(1) => \weight_reg[13][4]_i_1_n_6\,
O(0) => \weight_reg[13][4]_i_1_n_7\,
S(3) => \weight[13][4]_i_2_n_0\,
S(2) => \weight[13][4]_i_3_n_0\,
S(1) => \weight[13][4]_i_4_n_0\,
S(0) => \weight[13][4]_i_5_n_0\
);
\weight_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_6\,
Q => \weight_reg[13]_12\(5)
);
\weight_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_5\,
Q => \weight_reg[13]_12\(6)
);
\weight_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_4\,
Q => \weight_reg[13]_12\(7)
);
\weight_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_7\,
Q => \weight_reg[13]_12\(8)
);
\weight_reg[13][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][4]_i_1_n_0\,
CO(3) => \weight_reg[13][8]_i_1_n_0\,
CO(2) => \weight_reg[13][8]_i_1_n_1\,
CO(1) => \weight_reg[13][8]_i_1_n_2\,
CO(0) => \weight_reg[13][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_80\,
DI(2) => \ARG__23_n_81\,
DI(1) => \ARG__23_n_82\,
DI(0) => \ARG__23_n_83\,
O(3) => \weight_reg[13][8]_i_1_n_4\,
O(2) => \weight_reg[13][8]_i_1_n_5\,
O(1) => \weight_reg[13][8]_i_1_n_6\,
O(0) => \weight_reg[13][8]_i_1_n_7\,
S(3) => \weight[13][8]_i_2_n_0\,
S(2) => \weight[13][8]_i_3_n_0\,
S(1) => \weight[13][8]_i_4_n_0\,
S(0) => \weight[13][8]_i_5_n_0\
);
\weight_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_6\,
Q => \weight_reg[13]_12\(9)
);
\weight_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_7\,
Q => \weight_reg[14]_13\(0)
);
\weight_reg[14][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[14][0]_i_1_n_0\,
CO(2) => \weight_reg[14][0]_i_1_n_1\,
CO(1) => \weight_reg[14][0]_i_1_n_2\,
CO(0) => \weight_reg[14][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_88\,
DI(2) => \ARG__25_n_89\,
DI(1) => \ARG__25_n_90\,
DI(0) => \ARG__25_n_91\,
O(3) => \weight_reg[14][0]_i_1_n_4\,
O(2) => \weight_reg[14][0]_i_1_n_5\,
O(1) => \weight_reg[14][0]_i_1_n_6\,
O(0) => \weight_reg[14][0]_i_1_n_7\,
S(3) => \weight[14][0]_i_2_n_0\,
S(2) => \weight[14][0]_i_3_n_0\,
S(1) => \weight[14][0]_i_4_n_0\,
S(0) => \weight[14][0]_i_5_n_0\
);
\weight_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_5\,
Q => \weight_reg[14]_13\(10)
);
\weight_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_4\,
Q => \weight_reg[14]_13\(11)
);
\weight_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_7\,
Q => \weight_reg[14]_13\(12)
);
\weight_reg[14][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[14][12]_i_1_n_1\,
CO(1) => \weight_reg[14][12]_i_1_n_2\,
CO(0) => \weight_reg[14][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__25_n_77\,
DI(1) => \ARG__25_n_78\,
DI(0) => \ARG__25_n_79\,
O(3) => \weight_reg[14][12]_i_1_n_4\,
O(2) => \weight_reg[14][12]_i_1_n_5\,
O(1) => \weight_reg[14][12]_i_1_n_6\,
O(0) => \weight_reg[14][12]_i_1_n_7\,
S(3) => \weight[14][12]_i_2_n_0\,
S(2) => \weight[14][12]_i_3_n_0\,
S(1) => \weight[14][12]_i_4_n_0\,
S(0) => \weight[14][12]_i_5_n_0\
);
\weight_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_6\,
Q => \weight_reg[14]_13\(13)
);
\weight_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_5\,
Q => \weight_reg[14]_13\(14)
);
\weight_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_4\,
Q => \weight_reg[14]_13\(15)
);
\weight_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_6\,
Q => \weight_reg[14]_13\(1)
);
\weight_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_5\,
Q => \weight_reg[14]_13\(2)
);
\weight_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_4\,
Q => \weight_reg[14]_13\(3)
);
\weight_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_7\,
Q => \weight_reg[14]_13\(4)
);
\weight_reg[14][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][0]_i_1_n_0\,
CO(3) => \weight_reg[14][4]_i_1_n_0\,
CO(2) => \weight_reg[14][4]_i_1_n_1\,
CO(1) => \weight_reg[14][4]_i_1_n_2\,
CO(0) => \weight_reg[14][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_84\,
DI(2) => \ARG__25_n_85\,
DI(1) => \ARG__25_n_86\,
DI(0) => \ARG__25_n_87\,
O(3) => \weight_reg[14][4]_i_1_n_4\,
O(2) => \weight_reg[14][4]_i_1_n_5\,
O(1) => \weight_reg[14][4]_i_1_n_6\,
O(0) => \weight_reg[14][4]_i_1_n_7\,
S(3) => \weight[14][4]_i_2_n_0\,
S(2) => \weight[14][4]_i_3_n_0\,
S(1) => \weight[14][4]_i_4_n_0\,
S(0) => \weight[14][4]_i_5_n_0\
);
\weight_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_6\,
Q => \weight_reg[14]_13\(5)
);
\weight_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_5\,
Q => \weight_reg[14]_13\(6)
);
\weight_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_4\,
Q => \weight_reg[14]_13\(7)
);
\weight_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_7\,
Q => \weight_reg[14]_13\(8)
);
\weight_reg[14][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][4]_i_1_n_0\,
CO(3) => \weight_reg[14][8]_i_1_n_0\,
CO(2) => \weight_reg[14][8]_i_1_n_1\,
CO(1) => \weight_reg[14][8]_i_1_n_2\,
CO(0) => \weight_reg[14][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_80\,
DI(2) => \ARG__25_n_81\,
DI(1) => \ARG__25_n_82\,
DI(0) => \ARG__25_n_83\,
O(3) => \weight_reg[14][8]_i_1_n_4\,
O(2) => \weight_reg[14][8]_i_1_n_5\,
O(1) => \weight_reg[14][8]_i_1_n_6\,
O(0) => \weight_reg[14][8]_i_1_n_7\,
S(3) => \weight[14][8]_i_2_n_0\,
S(2) => \weight[14][8]_i_3_n_0\,
S(1) => \weight[14][8]_i_4_n_0\,
S(0) => \weight[14][8]_i_5_n_0\
);
\weight_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_6\,
Q => \weight_reg[14]_13\(9)
);
\weight_reg[15][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_7\,
Q => \weight_reg[15]_14\(0)
);
\weight_reg[15][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[15][0]_i_1_n_0\,
CO(2) => \weight_reg[15][0]_i_1_n_1\,
CO(1) => \weight_reg[15][0]_i_1_n_2\,
CO(0) => \weight_reg[15][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_88\,
DI(2) => \ARG__27_n_89\,
DI(1) => \ARG__27_n_90\,
DI(0) => \ARG__27_n_91\,
O(3) => \weight_reg[15][0]_i_1_n_4\,
O(2) => \weight_reg[15][0]_i_1_n_5\,
O(1) => \weight_reg[15][0]_i_1_n_6\,
O(0) => \weight_reg[15][0]_i_1_n_7\,
S(3) => \weight[15][0]_i_2_n_0\,
S(2) => \weight[15][0]_i_3_n_0\,
S(1) => \weight[15][0]_i_4_n_0\,
S(0) => \weight[15][0]_i_5_n_0\
);
\weight_reg[15][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_5\,
Q => \weight_reg[15]_14\(10)
);
\weight_reg[15][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_4\,
Q => \weight_reg[15]_14\(11)
);
\weight_reg[15][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_7\,
Q => \weight_reg[15]_14\(12)
);
\weight_reg[15][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[15][12]_i_1_n_1\,
CO(1) => \weight_reg[15][12]_i_1_n_2\,
CO(0) => \weight_reg[15][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__27_n_77\,
DI(1) => \ARG__27_n_78\,
DI(0) => \ARG__27_n_79\,
O(3) => \weight_reg[15][12]_i_1_n_4\,
O(2) => \weight_reg[15][12]_i_1_n_5\,
O(1) => \weight_reg[15][12]_i_1_n_6\,
O(0) => \weight_reg[15][12]_i_1_n_7\,
S(3) => \weight[15][12]_i_2_n_0\,
S(2) => \weight[15][12]_i_3_n_0\,
S(1) => \weight[15][12]_i_4_n_0\,
S(0) => \weight[15][12]_i_5_n_0\
);
\weight_reg[15][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_6\,
Q => \weight_reg[15]_14\(13)
);
\weight_reg[15][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_5\,
Q => \weight_reg[15]_14\(14)
);
\weight_reg[15][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_4\,
Q => \weight_reg[15]_14\(15)
);
\weight_reg[15][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_6\,
Q => \weight_reg[15]_14\(1)
);
\weight_reg[15][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_5\,
Q => \weight_reg[15]_14\(2)
);
\weight_reg[15][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_4\,
Q => \weight_reg[15]_14\(3)
);
\weight_reg[15][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_7\,
Q => \weight_reg[15]_14\(4)
);
\weight_reg[15][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][0]_i_1_n_0\,
CO(3) => \weight_reg[15][4]_i_1_n_0\,
CO(2) => \weight_reg[15][4]_i_1_n_1\,
CO(1) => \weight_reg[15][4]_i_1_n_2\,
CO(0) => \weight_reg[15][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_84\,
DI(2) => \ARG__27_n_85\,
DI(1) => \ARG__27_n_86\,
DI(0) => \ARG__27_n_87\,
O(3) => \weight_reg[15][4]_i_1_n_4\,
O(2) => \weight_reg[15][4]_i_1_n_5\,
O(1) => \weight_reg[15][4]_i_1_n_6\,
O(0) => \weight_reg[15][4]_i_1_n_7\,
S(3) => \weight[15][4]_i_2_n_0\,
S(2) => \weight[15][4]_i_3_n_0\,
S(1) => \weight[15][4]_i_4_n_0\,
S(0) => \weight[15][4]_i_5_n_0\
);
\weight_reg[15][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_6\,
Q => \weight_reg[15]_14\(5)
);
\weight_reg[15][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_5\,
Q => \weight_reg[15]_14\(6)
);
\weight_reg[15][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_4\,
Q => \weight_reg[15]_14\(7)
);
\weight_reg[15][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_7\,
Q => \weight_reg[15]_14\(8)
);
\weight_reg[15][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][4]_i_1_n_0\,
CO(3) => \weight_reg[15][8]_i_1_n_0\,
CO(2) => \weight_reg[15][8]_i_1_n_1\,
CO(1) => \weight_reg[15][8]_i_1_n_2\,
CO(0) => \weight_reg[15][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_80\,
DI(2) => \ARG__27_n_81\,
DI(1) => \ARG__27_n_82\,
DI(0) => \ARG__27_n_83\,
O(3) => \weight_reg[15][8]_i_1_n_4\,
O(2) => \weight_reg[15][8]_i_1_n_5\,
O(1) => \weight_reg[15][8]_i_1_n_6\,
O(0) => \weight_reg[15][8]_i_1_n_7\,
S(3) => \weight[15][8]_i_2_n_0\,
S(2) => \weight[15][8]_i_3_n_0\,
S(1) => \weight[15][8]_i_4_n_0\,
S(0) => \weight[15][8]_i_5_n_0\
);
\weight_reg[15][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_6\,
Q => \weight_reg[15]_14\(9)
);
\weight_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_7\,
Q => \weight_reg[1]_0\(0)
);
\weight_reg[1][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[1][0]_i_1_n_0\,
CO(2) => \weight_reg[1][0]_i_1_n_1\,
CO(1) => \weight_reg[1][0]_i_1_n_2\,
CO(0) => \weight_reg[1][0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(3 downto 0),
O(3) => \weight_reg[1][0]_i_1_n_4\,
O(2) => \weight_reg[1][0]_i_1_n_5\,
O(1) => \weight_reg[1][0]_i_1_n_6\,
O(0) => \weight_reg[1][0]_i_1_n_7\,
S(3) => \weight[1][0]_i_2_n_0\,
S(2) => \weight[1][0]_i_3_n_0\,
S(1) => \weight[1][0]_i_4_n_0\,
S(0) => \weight[1][0]_i_5_n_0\
);
\weight_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_5\,
Q => \weight_reg[1]_0\(10)
);
\weight_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_4\,
Q => \weight_reg[1]_0\(11)
);
\weight_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_7\,
Q => \weight_reg[1]_0\(12)
);
\weight_reg[1][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[1][12]_i_1_n_1\,
CO(1) => \weight_reg[1][12]_i_1_n_2\,
CO(0) => \weight_reg[1][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \in\(14 downto 12),
O(3) => \weight_reg[1][12]_i_1_n_4\,
O(2) => \weight_reg[1][12]_i_1_n_5\,
O(1) => \weight_reg[1][12]_i_1_n_6\,
O(0) => \weight_reg[1][12]_i_1_n_7\,
S(3) => \weight[1][12]_i_2_n_0\,
S(2) => \weight[1][12]_i_3_n_0\,
S(1) => \weight[1][12]_i_4_n_0\,
S(0) => \weight[1][12]_i_5_n_0\
);
\weight_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_6\,
Q => \weight_reg[1]_0\(13)
);
\weight_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_5\,
Q => \weight_reg[1]_0\(14)
);
\weight_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_4\,
Q => \weight_reg[1]_0\(15)
);
\weight_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_6\,
Q => \weight_reg[1]_0\(1)
);
\weight_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_5\,
Q => \weight_reg[1]_0\(2)
);
\weight_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_4\,
Q => \weight_reg[1]_0\(3)
);
\weight_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_7\,
Q => \weight_reg[1]_0\(4)
);
\weight_reg[1][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][0]_i_1_n_0\,
CO(3) => \weight_reg[1][4]_i_1_n_0\,
CO(2) => \weight_reg[1][4]_i_1_n_1\,
CO(1) => \weight_reg[1][4]_i_1_n_2\,
CO(0) => \weight_reg[1][4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(7 downto 4),
O(3) => \weight_reg[1][4]_i_1_n_4\,
O(2) => \weight_reg[1][4]_i_1_n_5\,
O(1) => \weight_reg[1][4]_i_1_n_6\,
O(0) => \weight_reg[1][4]_i_1_n_7\,
S(3) => \weight[1][4]_i_2_n_0\,
S(2) => \weight[1][4]_i_3_n_0\,
S(1) => \weight[1][4]_i_4_n_0\,
S(0) => \weight[1][4]_i_5_n_0\
);
\weight_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_6\,
Q => \weight_reg[1]_0\(5)
);
\weight_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_5\,
Q => \weight_reg[1]_0\(6)
);
\weight_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_4\,
Q => \weight_reg[1]_0\(7)
);
\weight_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_7\,
Q => \weight_reg[1]_0\(8)
);
\weight_reg[1][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][4]_i_1_n_0\,
CO(3) => \weight_reg[1][8]_i_1_n_0\,
CO(2) => \weight_reg[1][8]_i_1_n_1\,
CO(1) => \weight_reg[1][8]_i_1_n_2\,
CO(0) => \weight_reg[1][8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(11 downto 8),
O(3) => \weight_reg[1][8]_i_1_n_4\,
O(2) => \weight_reg[1][8]_i_1_n_5\,
O(1) => \weight_reg[1][8]_i_1_n_6\,
O(0) => \weight_reg[1][8]_i_1_n_7\,
S(3) => \weight[1][8]_i_2_n_0\,
S(2) => \weight[1][8]_i_3_n_0\,
S(1) => \weight[1][8]_i_4_n_0\,
S(0) => \weight[1][8]_i_5_n_0\
);
\weight_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_6\,
Q => \weight_reg[1]_0\(9)
);
\weight_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_7\,
Q => \weight_reg[2]_1\(0)
);
\weight_reg[2][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[2][0]_i_1_n_0\,
CO(2) => \weight_reg[2][0]_i_1_n_1\,
CO(1) => \weight_reg[2][0]_i_1_n_2\,
CO(0) => \weight_reg[2][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_88\,
DI(2) => \ARG__1_n_89\,
DI(1) => \ARG__1_n_90\,
DI(0) => \ARG__1_n_91\,
O(3) => \weight_reg[2][0]_i_1_n_4\,
O(2) => \weight_reg[2][0]_i_1_n_5\,
O(1) => \weight_reg[2][0]_i_1_n_6\,
O(0) => \weight_reg[2][0]_i_1_n_7\,
S(3) => \weight[2][0]_i_2_n_0\,
S(2) => \weight[2][0]_i_3_n_0\,
S(1) => \weight[2][0]_i_4_n_0\,
S(0) => \weight[2][0]_i_5_n_0\
);
\weight_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_5\,
Q => \weight_reg[2]_1\(10)
);
\weight_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_4\,
Q => \weight_reg[2]_1\(11)
);
\weight_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_7\,
Q => \weight_reg[2]_1\(12)
);
\weight_reg[2][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[2][12]_i_1_n_1\,
CO(1) => \weight_reg[2][12]_i_1_n_2\,
CO(0) => \weight_reg[2][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__1_n_77\,
DI(1) => \ARG__1_n_78\,
DI(0) => \ARG__1_n_79\,
O(3) => \weight_reg[2][12]_i_1_n_4\,
O(2) => \weight_reg[2][12]_i_1_n_5\,
O(1) => \weight_reg[2][12]_i_1_n_6\,
O(0) => \weight_reg[2][12]_i_1_n_7\,
S(3) => \weight[2][12]_i_2_n_0\,
S(2) => \weight[2][12]_i_3_n_0\,
S(1) => \weight[2][12]_i_4_n_0\,
S(0) => \weight[2][12]_i_5_n_0\
);
\weight_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_6\,
Q => \weight_reg[2]_1\(13)
);
\weight_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_5\,
Q => \weight_reg[2]_1\(14)
);
\weight_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_4\,
Q => \weight_reg[2]_1\(15)
);
\weight_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_6\,
Q => \weight_reg[2]_1\(1)
);
\weight_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_5\,
Q => \weight_reg[2]_1\(2)
);
\weight_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_4\,
Q => \weight_reg[2]_1\(3)
);
\weight_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_7\,
Q => \weight_reg[2]_1\(4)
);
\weight_reg[2][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][0]_i_1_n_0\,
CO(3) => \weight_reg[2][4]_i_1_n_0\,
CO(2) => \weight_reg[2][4]_i_1_n_1\,
CO(1) => \weight_reg[2][4]_i_1_n_2\,
CO(0) => \weight_reg[2][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_84\,
DI(2) => \ARG__1_n_85\,
DI(1) => \ARG__1_n_86\,
DI(0) => \ARG__1_n_87\,
O(3) => \weight_reg[2][4]_i_1_n_4\,
O(2) => \weight_reg[2][4]_i_1_n_5\,
O(1) => \weight_reg[2][4]_i_1_n_6\,
O(0) => \weight_reg[2][4]_i_1_n_7\,
S(3) => \weight[2][4]_i_2_n_0\,
S(2) => \weight[2][4]_i_3_n_0\,
S(1) => \weight[2][4]_i_4_n_0\,
S(0) => \weight[2][4]_i_5_n_0\
);
\weight_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_6\,
Q => \weight_reg[2]_1\(5)
);
\weight_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_5\,
Q => \weight_reg[2]_1\(6)
);
\weight_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_4\,
Q => \weight_reg[2]_1\(7)
);
\weight_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_7\,
Q => \weight_reg[2]_1\(8)
);
\weight_reg[2][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][4]_i_1_n_0\,
CO(3) => \weight_reg[2][8]_i_1_n_0\,
CO(2) => \weight_reg[2][8]_i_1_n_1\,
CO(1) => \weight_reg[2][8]_i_1_n_2\,
CO(0) => \weight_reg[2][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_80\,
DI(2) => \ARG__1_n_81\,
DI(1) => \ARG__1_n_82\,
DI(0) => \ARG__1_n_83\,
O(3) => \weight_reg[2][8]_i_1_n_4\,
O(2) => \weight_reg[2][8]_i_1_n_5\,
O(1) => \weight_reg[2][8]_i_1_n_6\,
O(0) => \weight_reg[2][8]_i_1_n_7\,
S(3) => \weight[2][8]_i_2_n_0\,
S(2) => \weight[2][8]_i_3_n_0\,
S(1) => \weight[2][8]_i_4_n_0\,
S(0) => \weight[2][8]_i_5_n_0\
);
\weight_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_6\,
Q => \weight_reg[2]_1\(9)
);
\weight_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_7\,
Q => \weight_reg[3]_2\(0)
);
\weight_reg[3][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[3][0]_i_1_n_0\,
CO(2) => \weight_reg[3][0]_i_1_n_1\,
CO(1) => \weight_reg[3][0]_i_1_n_2\,
CO(0) => \weight_reg[3][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_88\,
DI(2) => \ARG__3_n_89\,
DI(1) => \ARG__3_n_90\,
DI(0) => \ARG__3_n_91\,
O(3) => \weight_reg[3][0]_i_1_n_4\,
O(2) => \weight_reg[3][0]_i_1_n_5\,
O(1) => \weight_reg[3][0]_i_1_n_6\,
O(0) => \weight_reg[3][0]_i_1_n_7\,
S(3) => \weight[3][0]_i_2_n_0\,
S(2) => \weight[3][0]_i_3_n_0\,
S(1) => \weight[3][0]_i_4_n_0\,
S(0) => \weight[3][0]_i_5_n_0\
);
\weight_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_5\,
Q => \weight_reg[3]_2\(10)
);
\weight_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_4\,
Q => \weight_reg[3]_2\(11)
);
\weight_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_7\,
Q => \weight_reg[3]_2\(12)
);
\weight_reg[3][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[3][12]_i_1_n_1\,
CO(1) => \weight_reg[3][12]_i_1_n_2\,
CO(0) => \weight_reg[3][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__3_n_77\,
DI(1) => \ARG__3_n_78\,
DI(0) => \ARG__3_n_79\,
O(3) => \weight_reg[3][12]_i_1_n_4\,
O(2) => \weight_reg[3][12]_i_1_n_5\,
O(1) => \weight_reg[3][12]_i_1_n_6\,
O(0) => \weight_reg[3][12]_i_1_n_7\,
S(3) => \weight[3][12]_i_2_n_0\,
S(2) => \weight[3][12]_i_3_n_0\,
S(1) => \weight[3][12]_i_4_n_0\,
S(0) => \weight[3][12]_i_5_n_0\
);
\weight_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_6\,
Q => \weight_reg[3]_2\(13)
);
\weight_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_5\,
Q => \weight_reg[3]_2\(14)
);
\weight_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_4\,
Q => \weight_reg[3]_2\(15)
);
\weight_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_6\,
Q => \weight_reg[3]_2\(1)
);
\weight_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_5\,
Q => \weight_reg[3]_2\(2)
);
\weight_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_4\,
Q => \weight_reg[3]_2\(3)
);
\weight_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_7\,
Q => \weight_reg[3]_2\(4)
);
\weight_reg[3][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][0]_i_1_n_0\,
CO(3) => \weight_reg[3][4]_i_1_n_0\,
CO(2) => \weight_reg[3][4]_i_1_n_1\,
CO(1) => \weight_reg[3][4]_i_1_n_2\,
CO(0) => \weight_reg[3][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_84\,
DI(2) => \ARG__3_n_85\,
DI(1) => \ARG__3_n_86\,
DI(0) => \ARG__3_n_87\,
O(3) => \weight_reg[3][4]_i_1_n_4\,
O(2) => \weight_reg[3][4]_i_1_n_5\,
O(1) => \weight_reg[3][4]_i_1_n_6\,
O(0) => \weight_reg[3][4]_i_1_n_7\,
S(3) => \weight[3][4]_i_2_n_0\,
S(2) => \weight[3][4]_i_3_n_0\,
S(1) => \weight[3][4]_i_4_n_0\,
S(0) => \weight[3][4]_i_5_n_0\
);
\weight_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_6\,
Q => \weight_reg[3]_2\(5)
);
\weight_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_5\,
Q => \weight_reg[3]_2\(6)
);
\weight_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_4\,
Q => \weight_reg[3]_2\(7)
);
\weight_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_7\,
Q => \weight_reg[3]_2\(8)
);
\weight_reg[3][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][4]_i_1_n_0\,
CO(3) => \weight_reg[3][8]_i_1_n_0\,
CO(2) => \weight_reg[3][8]_i_1_n_1\,
CO(1) => \weight_reg[3][8]_i_1_n_2\,
CO(0) => \weight_reg[3][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_80\,
DI(2) => \ARG__3_n_81\,
DI(1) => \ARG__3_n_82\,
DI(0) => \ARG__3_n_83\,
O(3) => \weight_reg[3][8]_i_1_n_4\,
O(2) => \weight_reg[3][8]_i_1_n_5\,
O(1) => \weight_reg[3][8]_i_1_n_6\,
O(0) => \weight_reg[3][8]_i_1_n_7\,
S(3) => \weight[3][8]_i_2_n_0\,
S(2) => \weight[3][8]_i_3_n_0\,
S(1) => \weight[3][8]_i_4_n_0\,
S(0) => \weight[3][8]_i_5_n_0\
);
\weight_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_6\,
Q => \weight_reg[3]_2\(9)
);
\weight_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_7\,
Q => \weight_reg[4]_3\(0)
);
\weight_reg[4][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[4][0]_i_1_n_0\,
CO(2) => \weight_reg[4][0]_i_1_n_1\,
CO(1) => \weight_reg[4][0]_i_1_n_2\,
CO(0) => \weight_reg[4][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_88\,
DI(2) => \ARG__5_n_89\,
DI(1) => \ARG__5_n_90\,
DI(0) => \ARG__5_n_91\,
O(3) => \weight_reg[4][0]_i_1_n_4\,
O(2) => \weight_reg[4][0]_i_1_n_5\,
O(1) => \weight_reg[4][0]_i_1_n_6\,
O(0) => \weight_reg[4][0]_i_1_n_7\,
S(3) => \weight[4][0]_i_2_n_0\,
S(2) => \weight[4][0]_i_3_n_0\,
S(1) => \weight[4][0]_i_4_n_0\,
S(0) => \weight[4][0]_i_5_n_0\
);
\weight_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_5\,
Q => \weight_reg[4]_3\(10)
);
\weight_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_4\,
Q => \weight_reg[4]_3\(11)
);
\weight_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_7\,
Q => \weight_reg[4]_3\(12)
);
\weight_reg[4][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[4][12]_i_1_n_1\,
CO(1) => \weight_reg[4][12]_i_1_n_2\,
CO(0) => \weight_reg[4][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__5_n_77\,
DI(1) => \ARG__5_n_78\,
DI(0) => \ARG__5_n_79\,
O(3) => \weight_reg[4][12]_i_1_n_4\,
O(2) => \weight_reg[4][12]_i_1_n_5\,
O(1) => \weight_reg[4][12]_i_1_n_6\,
O(0) => \weight_reg[4][12]_i_1_n_7\,
S(3) => \weight[4][12]_i_2_n_0\,
S(2) => \weight[4][12]_i_3_n_0\,
S(1) => \weight[4][12]_i_4_n_0\,
S(0) => \weight[4][12]_i_5_n_0\
);
\weight_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_6\,
Q => \weight_reg[4]_3\(13)
);
\weight_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_5\,
Q => \weight_reg[4]_3\(14)
);
\weight_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_4\,
Q => \weight_reg[4]_3\(15)
);
\weight_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_6\,
Q => \weight_reg[4]_3\(1)
);
\weight_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_5\,
Q => \weight_reg[4]_3\(2)
);
\weight_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_4\,
Q => \weight_reg[4]_3\(3)
);
\weight_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_7\,
Q => \weight_reg[4]_3\(4)
);
\weight_reg[4][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][0]_i_1_n_0\,
CO(3) => \weight_reg[4][4]_i_1_n_0\,
CO(2) => \weight_reg[4][4]_i_1_n_1\,
CO(1) => \weight_reg[4][4]_i_1_n_2\,
CO(0) => \weight_reg[4][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_84\,
DI(2) => \ARG__5_n_85\,
DI(1) => \ARG__5_n_86\,
DI(0) => \ARG__5_n_87\,
O(3) => \weight_reg[4][4]_i_1_n_4\,
O(2) => \weight_reg[4][4]_i_1_n_5\,
O(1) => \weight_reg[4][4]_i_1_n_6\,
O(0) => \weight_reg[4][4]_i_1_n_7\,
S(3) => \weight[4][4]_i_2_n_0\,
S(2) => \weight[4][4]_i_3_n_0\,
S(1) => \weight[4][4]_i_4_n_0\,
S(0) => \weight[4][4]_i_5_n_0\
);
\weight_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_6\,
Q => \weight_reg[4]_3\(5)
);
\weight_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_5\,
Q => \weight_reg[4]_3\(6)
);
\weight_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_4\,
Q => \weight_reg[4]_3\(7)
);
\weight_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_7\,
Q => \weight_reg[4]_3\(8)
);
\weight_reg[4][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][4]_i_1_n_0\,
CO(3) => \weight_reg[4][8]_i_1_n_0\,
CO(2) => \weight_reg[4][8]_i_1_n_1\,
CO(1) => \weight_reg[4][8]_i_1_n_2\,
CO(0) => \weight_reg[4][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_80\,
DI(2) => \ARG__5_n_81\,
DI(1) => \ARG__5_n_82\,
DI(0) => \ARG__5_n_83\,
O(3) => \weight_reg[4][8]_i_1_n_4\,
O(2) => \weight_reg[4][8]_i_1_n_5\,
O(1) => \weight_reg[4][8]_i_1_n_6\,
O(0) => \weight_reg[4][8]_i_1_n_7\,
S(3) => \weight[4][8]_i_2_n_0\,
S(2) => \weight[4][8]_i_3_n_0\,
S(1) => \weight[4][8]_i_4_n_0\,
S(0) => \weight[4][8]_i_5_n_0\
);
\weight_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_6\,
Q => \weight_reg[4]_3\(9)
);
\weight_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_7\,
Q => \weight_reg[5]_4\(0)
);
\weight_reg[5][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[5][0]_i_1_n_0\,
CO(2) => \weight_reg[5][0]_i_1_n_1\,
CO(1) => \weight_reg[5][0]_i_1_n_2\,
CO(0) => \weight_reg[5][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_88\,
DI(2) => \ARG__7_n_89\,
DI(1) => \ARG__7_n_90\,
DI(0) => \ARG__7_n_91\,
O(3) => \weight_reg[5][0]_i_1_n_4\,
O(2) => \weight_reg[5][0]_i_1_n_5\,
O(1) => \weight_reg[5][0]_i_1_n_6\,
O(0) => \weight_reg[5][0]_i_1_n_7\,
S(3) => \weight[5][0]_i_2_n_0\,
S(2) => \weight[5][0]_i_3_n_0\,
S(1) => \weight[5][0]_i_4_n_0\,
S(0) => \weight[5][0]_i_5_n_0\
);
\weight_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_5\,
Q => \weight_reg[5]_4\(10)
);
\weight_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_4\,
Q => \weight_reg[5]_4\(11)
);
\weight_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_7\,
Q => \weight_reg[5]_4\(12)
);
\weight_reg[5][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[5][12]_i_1_n_1\,
CO(1) => \weight_reg[5][12]_i_1_n_2\,
CO(0) => \weight_reg[5][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__7_n_77\,
DI(1) => \ARG__7_n_78\,
DI(0) => \ARG__7_n_79\,
O(3) => \weight_reg[5][12]_i_1_n_4\,
O(2) => \weight_reg[5][12]_i_1_n_5\,
O(1) => \weight_reg[5][12]_i_1_n_6\,
O(0) => \weight_reg[5][12]_i_1_n_7\,
S(3) => \weight[5][12]_i_2_n_0\,
S(2) => \weight[5][12]_i_3_n_0\,
S(1) => \weight[5][12]_i_4_n_0\,
S(0) => \weight[5][12]_i_5_n_0\
);
\weight_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_6\,
Q => \weight_reg[5]_4\(13)
);
\weight_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_5\,
Q => \weight_reg[5]_4\(14)
);
\weight_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_4\,
Q => \weight_reg[5]_4\(15)
);
\weight_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_6\,
Q => \weight_reg[5]_4\(1)
);
\weight_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_5\,
Q => \weight_reg[5]_4\(2)
);
\weight_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_4\,
Q => \weight_reg[5]_4\(3)
);
\weight_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_7\,
Q => \weight_reg[5]_4\(4)
);
\weight_reg[5][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][0]_i_1_n_0\,
CO(3) => \weight_reg[5][4]_i_1_n_0\,
CO(2) => \weight_reg[5][4]_i_1_n_1\,
CO(1) => \weight_reg[5][4]_i_1_n_2\,
CO(0) => \weight_reg[5][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_84\,
DI(2) => \ARG__7_n_85\,
DI(1) => \ARG__7_n_86\,
DI(0) => \ARG__7_n_87\,
O(3) => \weight_reg[5][4]_i_1_n_4\,
O(2) => \weight_reg[5][4]_i_1_n_5\,
O(1) => \weight_reg[5][4]_i_1_n_6\,
O(0) => \weight_reg[5][4]_i_1_n_7\,
S(3) => \weight[5][4]_i_2_n_0\,
S(2) => \weight[5][4]_i_3_n_0\,
S(1) => \weight[5][4]_i_4_n_0\,
S(0) => \weight[5][4]_i_5_n_0\
);
\weight_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_6\,
Q => \weight_reg[5]_4\(5)
);
\weight_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_5\,
Q => \weight_reg[5]_4\(6)
);
\weight_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_4\,
Q => \weight_reg[5]_4\(7)
);
\weight_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_7\,
Q => \weight_reg[5]_4\(8)
);
\weight_reg[5][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][4]_i_1_n_0\,
CO(3) => \weight_reg[5][8]_i_1_n_0\,
CO(2) => \weight_reg[5][8]_i_1_n_1\,
CO(1) => \weight_reg[5][8]_i_1_n_2\,
CO(0) => \weight_reg[5][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_80\,
DI(2) => \ARG__7_n_81\,
DI(1) => \ARG__7_n_82\,
DI(0) => \ARG__7_n_83\,
O(3) => \weight_reg[5][8]_i_1_n_4\,
O(2) => \weight_reg[5][8]_i_1_n_5\,
O(1) => \weight_reg[5][8]_i_1_n_6\,
O(0) => \weight_reg[5][8]_i_1_n_7\,
S(3) => \weight[5][8]_i_2_n_0\,
S(2) => \weight[5][8]_i_3_n_0\,
S(1) => \weight[5][8]_i_4_n_0\,
S(0) => \weight[5][8]_i_5_n_0\
);
\weight_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_6\,
Q => \weight_reg[5]_4\(9)
);
\weight_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_7\,
Q => \weight_reg[6]_5\(0)
);
\weight_reg[6][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[6][0]_i_1_n_0\,
CO(2) => \weight_reg[6][0]_i_1_n_1\,
CO(1) => \weight_reg[6][0]_i_1_n_2\,
CO(0) => \weight_reg[6][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_88\,
DI(2) => \ARG__9_n_89\,
DI(1) => \ARG__9_n_90\,
DI(0) => \ARG__9_n_91\,
O(3) => \weight_reg[6][0]_i_1_n_4\,
O(2) => \weight_reg[6][0]_i_1_n_5\,
O(1) => \weight_reg[6][0]_i_1_n_6\,
O(0) => \weight_reg[6][0]_i_1_n_7\,
S(3) => \weight[6][0]_i_2_n_0\,
S(2) => \weight[6][0]_i_3_n_0\,
S(1) => \weight[6][0]_i_4_n_0\,
S(0) => \weight[6][0]_i_5_n_0\
);
\weight_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_5\,
Q => \weight_reg[6]_5\(10)
);
\weight_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_4\,
Q => \weight_reg[6]_5\(11)
);
\weight_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_7\,
Q => \weight_reg[6]_5\(12)
);
\weight_reg[6][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[6][12]_i_1_n_1\,
CO(1) => \weight_reg[6][12]_i_1_n_2\,
CO(0) => \weight_reg[6][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__9_n_77\,
DI(1) => \ARG__9_n_78\,
DI(0) => \ARG__9_n_79\,
O(3) => \weight_reg[6][12]_i_1_n_4\,
O(2) => \weight_reg[6][12]_i_1_n_5\,
O(1) => \weight_reg[6][12]_i_1_n_6\,
O(0) => \weight_reg[6][12]_i_1_n_7\,
S(3) => \weight[6][12]_i_2_n_0\,
S(2) => \weight[6][12]_i_3_n_0\,
S(1) => \weight[6][12]_i_4_n_0\,
S(0) => \weight[6][12]_i_5_n_0\
);
\weight_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_6\,
Q => \weight_reg[6]_5\(13)
);
\weight_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_5\,
Q => \weight_reg[6]_5\(14)
);
\weight_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_4\,
Q => \weight_reg[6]_5\(15)
);
\weight_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_6\,
Q => \weight_reg[6]_5\(1)
);
\weight_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_5\,
Q => \weight_reg[6]_5\(2)
);
\weight_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_4\,
Q => \weight_reg[6]_5\(3)
);
\weight_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_7\,
Q => \weight_reg[6]_5\(4)
);
\weight_reg[6][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][0]_i_1_n_0\,
CO(3) => \weight_reg[6][4]_i_1_n_0\,
CO(2) => \weight_reg[6][4]_i_1_n_1\,
CO(1) => \weight_reg[6][4]_i_1_n_2\,
CO(0) => \weight_reg[6][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_84\,
DI(2) => \ARG__9_n_85\,
DI(1) => \ARG__9_n_86\,
DI(0) => \ARG__9_n_87\,
O(3) => \weight_reg[6][4]_i_1_n_4\,
O(2) => \weight_reg[6][4]_i_1_n_5\,
O(1) => \weight_reg[6][4]_i_1_n_6\,
O(0) => \weight_reg[6][4]_i_1_n_7\,
S(3) => \weight[6][4]_i_2_n_0\,
S(2) => \weight[6][4]_i_3_n_0\,
S(1) => \weight[6][4]_i_4_n_0\,
S(0) => \weight[6][4]_i_5_n_0\
);
\weight_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_6\,
Q => \weight_reg[6]_5\(5)
);
\weight_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_5\,
Q => \weight_reg[6]_5\(6)
);
\weight_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_4\,
Q => \weight_reg[6]_5\(7)
);
\weight_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_7\,
Q => \weight_reg[6]_5\(8)
);
\weight_reg[6][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][4]_i_1_n_0\,
CO(3) => \weight_reg[6][8]_i_1_n_0\,
CO(2) => \weight_reg[6][8]_i_1_n_1\,
CO(1) => \weight_reg[6][8]_i_1_n_2\,
CO(0) => \weight_reg[6][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_80\,
DI(2) => \ARG__9_n_81\,
DI(1) => \ARG__9_n_82\,
DI(0) => \ARG__9_n_83\,
O(3) => \weight_reg[6][8]_i_1_n_4\,
O(2) => \weight_reg[6][8]_i_1_n_5\,
O(1) => \weight_reg[6][8]_i_1_n_6\,
O(0) => \weight_reg[6][8]_i_1_n_7\,
S(3) => \weight[6][8]_i_2_n_0\,
S(2) => \weight[6][8]_i_3_n_0\,
S(1) => \weight[6][8]_i_4_n_0\,
S(0) => \weight[6][8]_i_5_n_0\
);
\weight_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_6\,
Q => \weight_reg[6]_5\(9)
);
\weight_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_7\,
Q => \weight_reg[7]_6\(0)
);
\weight_reg[7][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[7][0]_i_1_n_0\,
CO(2) => \weight_reg[7][0]_i_1_n_1\,
CO(1) => \weight_reg[7][0]_i_1_n_2\,
CO(0) => \weight_reg[7][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_88\,
DI(2) => \ARG__11_n_89\,
DI(1) => \ARG__11_n_90\,
DI(0) => \ARG__11_n_91\,
O(3) => \weight_reg[7][0]_i_1_n_4\,
O(2) => \weight_reg[7][0]_i_1_n_5\,
O(1) => \weight_reg[7][0]_i_1_n_6\,
O(0) => \weight_reg[7][0]_i_1_n_7\,
S(3) => \weight[7][0]_i_2_n_0\,
S(2) => \weight[7][0]_i_3_n_0\,
S(1) => \weight[7][0]_i_4_n_0\,
S(0) => \weight[7][0]_i_5_n_0\
);
\weight_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_5\,
Q => \weight_reg[7]_6\(10)
);
\weight_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_4\,
Q => \weight_reg[7]_6\(11)
);
\weight_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_7\,
Q => \weight_reg[7]_6\(12)
);
\weight_reg[7][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[7][12]_i_1_n_1\,
CO(1) => \weight_reg[7][12]_i_1_n_2\,
CO(0) => \weight_reg[7][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__11_n_77\,
DI(1) => \ARG__11_n_78\,
DI(0) => \ARG__11_n_79\,
O(3) => \weight_reg[7][12]_i_1_n_4\,
O(2) => \weight_reg[7][12]_i_1_n_5\,
O(1) => \weight_reg[7][12]_i_1_n_6\,
O(0) => \weight_reg[7][12]_i_1_n_7\,
S(3) => \weight[7][12]_i_2_n_0\,
S(2) => \weight[7][12]_i_3_n_0\,
S(1) => \weight[7][12]_i_4_n_0\,
S(0) => \weight[7][12]_i_5_n_0\
);
\weight_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_6\,
Q => \weight_reg[7]_6\(13)
);
\weight_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_5\,
Q => \weight_reg[7]_6\(14)
);
\weight_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_4\,
Q => \weight_reg[7]_6\(15)
);
\weight_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_6\,
Q => \weight_reg[7]_6\(1)
);
\weight_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_5\,
Q => \weight_reg[7]_6\(2)
);
\weight_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_4\,
Q => \weight_reg[7]_6\(3)
);
\weight_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_7\,
Q => \weight_reg[7]_6\(4)
);
\weight_reg[7][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][0]_i_1_n_0\,
CO(3) => \weight_reg[7][4]_i_1_n_0\,
CO(2) => \weight_reg[7][4]_i_1_n_1\,
CO(1) => \weight_reg[7][4]_i_1_n_2\,
CO(0) => \weight_reg[7][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_84\,
DI(2) => \ARG__11_n_85\,
DI(1) => \ARG__11_n_86\,
DI(0) => \ARG__11_n_87\,
O(3) => \weight_reg[7][4]_i_1_n_4\,
O(2) => \weight_reg[7][4]_i_1_n_5\,
O(1) => \weight_reg[7][4]_i_1_n_6\,
O(0) => \weight_reg[7][4]_i_1_n_7\,
S(3) => \weight[7][4]_i_2_n_0\,
S(2) => \weight[7][4]_i_3_n_0\,
S(1) => \weight[7][4]_i_4_n_0\,
S(0) => \weight[7][4]_i_5_n_0\
);
\weight_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_6\,
Q => \weight_reg[7]_6\(5)
);
\weight_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_5\,
Q => \weight_reg[7]_6\(6)
);
\weight_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_4\,
Q => \weight_reg[7]_6\(7)
);
\weight_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_7\,
Q => \weight_reg[7]_6\(8)
);
\weight_reg[7][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][4]_i_1_n_0\,
CO(3) => \weight_reg[7][8]_i_1_n_0\,
CO(2) => \weight_reg[7][8]_i_1_n_1\,
CO(1) => \weight_reg[7][8]_i_1_n_2\,
CO(0) => \weight_reg[7][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_80\,
DI(2) => \ARG__11_n_81\,
DI(1) => \ARG__11_n_82\,
DI(0) => \ARG__11_n_83\,
O(3) => \weight_reg[7][8]_i_1_n_4\,
O(2) => \weight_reg[7][8]_i_1_n_5\,
O(1) => \weight_reg[7][8]_i_1_n_6\,
O(0) => \weight_reg[7][8]_i_1_n_7\,
S(3) => \weight[7][8]_i_2_n_0\,
S(2) => \weight[7][8]_i_3_n_0\,
S(1) => \weight[7][8]_i_4_n_0\,
S(0) => \weight[7][8]_i_5_n_0\
);
\weight_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_6\,
Q => \weight_reg[7]_6\(9)
);
\weight_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_7\,
Q => \weight_reg[8]_7\(0)
);
\weight_reg[8][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[8][0]_i_1_n_0\,
CO(2) => \weight_reg[8][0]_i_1_n_1\,
CO(1) => \weight_reg[8][0]_i_1_n_2\,
CO(0) => \weight_reg[8][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_88\,
DI(2) => \ARG__13_n_89\,
DI(1) => \ARG__13_n_90\,
DI(0) => \ARG__13_n_91\,
O(3) => \weight_reg[8][0]_i_1_n_4\,
O(2) => \weight_reg[8][0]_i_1_n_5\,
O(1) => \weight_reg[8][0]_i_1_n_6\,
O(0) => \weight_reg[8][0]_i_1_n_7\,
S(3) => \weight[8][0]_i_2_n_0\,
S(2) => \weight[8][0]_i_3_n_0\,
S(1) => \weight[8][0]_i_4_n_0\,
S(0) => \weight[8][0]_i_5_n_0\
);
\weight_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_5\,
Q => \weight_reg[8]_7\(10)
);
\weight_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_4\,
Q => \weight_reg[8]_7\(11)
);
\weight_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_7\,
Q => \weight_reg[8]_7\(12)
);
\weight_reg[8][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[8][12]_i_1_n_1\,
CO(1) => \weight_reg[8][12]_i_1_n_2\,
CO(0) => \weight_reg[8][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__13_n_77\,
DI(1) => \ARG__13_n_78\,
DI(0) => \ARG__13_n_79\,
O(3) => \weight_reg[8][12]_i_1_n_4\,
O(2) => \weight_reg[8][12]_i_1_n_5\,
O(1) => \weight_reg[8][12]_i_1_n_6\,
O(0) => \weight_reg[8][12]_i_1_n_7\,
S(3) => \weight[8][12]_i_2_n_0\,
S(2) => \weight[8][12]_i_3_n_0\,
S(1) => \weight[8][12]_i_4_n_0\,
S(0) => \weight[8][12]_i_5_n_0\
);
\weight_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_6\,
Q => \weight_reg[8]_7\(13)
);
\weight_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_5\,
Q => \weight_reg[8]_7\(14)
);
\weight_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_4\,
Q => \weight_reg[8]_7\(15)
);
\weight_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_6\,
Q => \weight_reg[8]_7\(1)
);
\weight_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_5\,
Q => \weight_reg[8]_7\(2)
);
\weight_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_4\,
Q => \weight_reg[8]_7\(3)
);
\weight_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_7\,
Q => \weight_reg[8]_7\(4)
);
\weight_reg[8][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][0]_i_1_n_0\,
CO(3) => \weight_reg[8][4]_i_1_n_0\,
CO(2) => \weight_reg[8][4]_i_1_n_1\,
CO(1) => \weight_reg[8][4]_i_1_n_2\,
CO(0) => \weight_reg[8][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_84\,
DI(2) => \ARG__13_n_85\,
DI(1) => \ARG__13_n_86\,
DI(0) => \ARG__13_n_87\,
O(3) => \weight_reg[8][4]_i_1_n_4\,
O(2) => \weight_reg[8][4]_i_1_n_5\,
O(1) => \weight_reg[8][4]_i_1_n_6\,
O(0) => \weight_reg[8][4]_i_1_n_7\,
S(3) => \weight[8][4]_i_2_n_0\,
S(2) => \weight[8][4]_i_3_n_0\,
S(1) => \weight[8][4]_i_4_n_0\,
S(0) => \weight[8][4]_i_5_n_0\
);
\weight_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_6\,
Q => \weight_reg[8]_7\(5)
);
\weight_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_5\,
Q => \weight_reg[8]_7\(6)
);
\weight_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_4\,
Q => \weight_reg[8]_7\(7)
);
\weight_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_7\,
Q => \weight_reg[8]_7\(8)
);
\weight_reg[8][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][4]_i_1_n_0\,
CO(3) => \weight_reg[8][8]_i_1_n_0\,
CO(2) => \weight_reg[8][8]_i_1_n_1\,
CO(1) => \weight_reg[8][8]_i_1_n_2\,
CO(0) => \weight_reg[8][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_80\,
DI(2) => \ARG__13_n_81\,
DI(1) => \ARG__13_n_82\,
DI(0) => \ARG__13_n_83\,
O(3) => \weight_reg[8][8]_i_1_n_4\,
O(2) => \weight_reg[8][8]_i_1_n_5\,
O(1) => \weight_reg[8][8]_i_1_n_6\,
O(0) => \weight_reg[8][8]_i_1_n_7\,
S(3) => \weight[8][8]_i_2_n_0\,
S(2) => \weight[8][8]_i_3_n_0\,
S(1) => \weight[8][8]_i_4_n_0\,
S(0) => \weight[8][8]_i_5_n_0\
);
\weight_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_6\,
Q => \weight_reg[8]_7\(9)
);
\weight_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_7\,
Q => \weight_reg[9]_8\(0)
);
\weight_reg[9][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[9][0]_i_1_n_0\,
CO(2) => \weight_reg[9][0]_i_1_n_1\,
CO(1) => \weight_reg[9][0]_i_1_n_2\,
CO(0) => \weight_reg[9][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_88\,
DI(2) => \ARG__15_n_89\,
DI(1) => \ARG__15_n_90\,
DI(0) => \ARG__15_n_91\,
O(3) => \weight_reg[9][0]_i_1_n_4\,
O(2) => \weight_reg[9][0]_i_1_n_5\,
O(1) => \weight_reg[9][0]_i_1_n_6\,
O(0) => \weight_reg[9][0]_i_1_n_7\,
S(3) => \weight[9][0]_i_2_n_0\,
S(2) => \weight[9][0]_i_3_n_0\,
S(1) => \weight[9][0]_i_4_n_0\,
S(0) => \weight[9][0]_i_5_n_0\
);
\weight_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_5\,
Q => \weight_reg[9]_8\(10)
);
\weight_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_4\,
Q => \weight_reg[9]_8\(11)
);
\weight_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_7\,
Q => \weight_reg[9]_8\(12)
);
\weight_reg[9][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[9][12]_i_1_n_1\,
CO(1) => \weight_reg[9][12]_i_1_n_2\,
CO(0) => \weight_reg[9][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__15_n_77\,
DI(1) => \ARG__15_n_78\,
DI(0) => \ARG__15_n_79\,
O(3) => \weight_reg[9][12]_i_1_n_4\,
O(2) => \weight_reg[9][12]_i_1_n_5\,
O(1) => \weight_reg[9][12]_i_1_n_6\,
O(0) => \weight_reg[9][12]_i_1_n_7\,
S(3) => \weight[9][12]_i_2_n_0\,
S(2) => \weight[9][12]_i_3_n_0\,
S(1) => \weight[9][12]_i_4_n_0\,
S(0) => \weight[9][12]_i_5_n_0\
);
\weight_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_6\,
Q => \weight_reg[9]_8\(13)
);
\weight_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_5\,
Q => \weight_reg[9]_8\(14)
);
\weight_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_4\,
Q => \weight_reg[9]_8\(15)
);
\weight_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_6\,
Q => \weight_reg[9]_8\(1)
);
\weight_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_5\,
Q => \weight_reg[9]_8\(2)
);
\weight_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_4\,
Q => \weight_reg[9]_8\(3)
);
\weight_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_7\,
Q => \weight_reg[9]_8\(4)
);
\weight_reg[9][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][0]_i_1_n_0\,
CO(3) => \weight_reg[9][4]_i_1_n_0\,
CO(2) => \weight_reg[9][4]_i_1_n_1\,
CO(1) => \weight_reg[9][4]_i_1_n_2\,
CO(0) => \weight_reg[9][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_84\,
DI(2) => \ARG__15_n_85\,
DI(1) => \ARG__15_n_86\,
DI(0) => \ARG__15_n_87\,
O(3) => \weight_reg[9][4]_i_1_n_4\,
O(2) => \weight_reg[9][4]_i_1_n_5\,
O(1) => \weight_reg[9][4]_i_1_n_6\,
O(0) => \weight_reg[9][4]_i_1_n_7\,
S(3) => \weight[9][4]_i_2_n_0\,
S(2) => \weight[9][4]_i_3_n_0\,
S(1) => \weight[9][4]_i_4_n_0\,
S(0) => \weight[9][4]_i_5_n_0\
);
\weight_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_6\,
Q => \weight_reg[9]_8\(5)
);
\weight_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_5\,
Q => \weight_reg[9]_8\(6)
);
\weight_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_4\,
Q => \weight_reg[9]_8\(7)
);
\weight_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_7\,
Q => \weight_reg[9]_8\(8)
);
\weight_reg[9][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][4]_i_1_n_0\,
CO(3) => \weight_reg[9][8]_i_1_n_0\,
CO(2) => \weight_reg[9][8]_i_1_n_1\,
CO(1) => \weight_reg[9][8]_i_1_n_2\,
CO(0) => \weight_reg[9][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_80\,
DI(2) => \ARG__15_n_81\,
DI(1) => \ARG__15_n_82\,
DI(0) => \ARG__15_n_83\,
O(3) => \weight_reg[9][8]_i_1_n_4\,
O(2) => \weight_reg[9][8]_i_1_n_5\,
O(1) => \weight_reg[9][8]_i_1_n_6\,
O(0) => \weight_reg[9][8]_i_1_n_7\,
S(3) => \weight[9][8]_i_2_n_0\,
S(2) => \weight[9][8]_i_3_n_0\,
S(1) => \weight[9][8]_i_4_n_0\,
S(0) => \weight[9][8]_i_5_n_0\
);
\weight_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_6\,
Q => \weight_reg[9]_8\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
port (
read_reg_cop_out_ready : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\AXI4_Lite_RDATA_tmp_reg[31]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
strobe_sw_cop_in_strobe : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
cop_out_ready : in STD_LOGIC;
\wdata_reg[0]\ : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\wdata_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
wr_enb_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal in_strobe : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 15 to 15 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
write_reg_axi_enable <= \^write_reg_axi_enable\;
\ARG_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => DI(0)
);
ARG_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(1),
O => \ARG__29\(2)
);
ARG_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(0),
O => \ARG__29\(1)
);
ARG_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => \ARG__29\(0)
);
\cp_controller_cpstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F20"
)
port map (
I0 => in_strobe,
I1 => cp_controller_cpstate(1),
I2 => \^write_reg_axi_enable\,
I3 => cp_controller_cpstate(0),
O => \cp_controller_cpstate_reg[0]\
);
read_reg_cop_out_ready_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => cop_out_ready,
Q => read_reg_cop_out_ready
);
strobe_reg_cop_in_strobe_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => strobe_sw_cop_in_strobe,
Q => in_strobe
);
\sub_temp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => filter_sum(7),
O => \sync_reg_e_k_reg[7]_0\(3)
);
\sub_temp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => filter_sum(6),
O => \sync_reg_e_k_reg[7]_0\(2)
);
\sub_temp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => filter_sum(5),
O => \sync_reg_e_k_reg[7]_0\(1)
);
\sub_temp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => filter_sum(4),
O => \sync_reg_e_k_reg[7]_0\(0)
);
\sub_temp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => filter_sum(11),
O => \sync_reg_e_k_reg[11]_0\(3)
);
\sub_temp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => filter_sum(10),
O => \sync_reg_e_k_reg[11]_0\(2)
);
\sub_temp_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => filter_sum(9),
O => \sync_reg_e_k_reg[11]_0\(1)
);
\sub_temp_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => filter_sum(8),
O => \sync_reg_e_k_reg[11]_0\(0)
);
\sub_temp_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => write_reg_d_k(15),
I1 => filter_sum(15),
O => S(3)
);
\sub_temp_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => filter_sum(14),
O => S(2)
);
\sub_temp_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => filter_sum(13),
O => S(1)
);
\sub_temp_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => filter_sum(12),
O => S(0)
);
sub_temp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => filter_sum(3),
O => \sync_reg_e_k_reg[3]_0\(3)
);
sub_temp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => filter_sum(2),
O => \sync_reg_e_k_reg[3]_0\(2)
);
sub_temp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => filter_sum(1),
O => \sync_reg_e_k_reg[3]_0\(1)
);
sub_temp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => filter_sum(0),
O => \sync_reg_e_k_reg[3]_0\(0)
);
\sync_reg_e_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(0),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(0)
);
\sync_reg_e_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(10),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(10)
);
\sync_reg_e_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(11),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(11)
);
\sync_reg_e_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(12),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(12)
);
\sync_reg_e_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(13),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(13)
);
\sync_reg_e_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(14),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(14)
);
\sync_reg_e_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(15),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(15)
);
\sync_reg_e_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(1),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(1)
);
\sync_reg_e_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(2),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(2)
);
\sync_reg_e_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(3),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(3)
);
\sync_reg_e_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(4),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(4)
);
\sync_reg_e_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(5),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(5)
);
\sync_reg_e_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(6),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(6)
);
\sync_reg_e_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(7),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(7)
);
\sync_reg_e_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(8),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(8)
);
\sync_reg_e_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(9),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(9)
);
write_reg_axi_enable_reg: unisim.vcomponents.FDPE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
D => \wdata_reg[0]\,
PRE => AR(0),
Q => \^write_reg_axi_enable\
);
\write_reg_d_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \^q\(0)
);
\write_reg_d_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \^q\(10)
);
\write_reg_d_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \^q\(11)
);
\write_reg_d_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \^q\(12)
);
\write_reg_d_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \^q\(13)
);
\write_reg_d_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \^q\(14)
);
\write_reg_d_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => write_reg_d_k(15)
);
\write_reg_d_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \^q\(1)
);
\write_reg_d_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \^q\(2)
);
\write_reg_d_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \^q\(3)
);
\write_reg_d_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \^q\(4)
);
\write_reg_d_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \^q\(5)
);
\write_reg_d_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \^q\(6)
);
\write_reg_d_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \^q\(7)
);
\write_reg_d_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \^q\(8)
);
\write_reg_d_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \^q\(9)
);
\write_reg_x_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \ARG__28\(0)
);
\write_reg_x_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \ARG__28\(10)
);
\write_reg_x_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \ARG__28\(11)
);
\write_reg_x_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \ARG__28\(12)
);
\write_reg_x_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \ARG__28\(13)
);
\write_reg_x_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \ARG__28\(14)
);
\write_reg_x_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => \ARG__28\(15)
);
\write_reg_x_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \ARG__28\(1)
);
\write_reg_x_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \ARG__28\(2)
);
\write_reg_x_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \ARG__28\(3)
);
\write_reg_x_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \ARG__28\(4)
);
\write_reg_x_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \ARG__28\(5)
);
\write_reg_x_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \ARG__28\(6)
);
\write_reg_x_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \ARG__28\(7)
);
\write_reg_x_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \ARG__28\(8)
);
\write_reg_x_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \ARG__28\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
port (
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
write_reg_axi_enable_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
strobe_sw_cop_in_strobe : out STD_LOGIC;
\write_reg_d_k_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
write_reg_axi_enable : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
\sync_reg_e_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
read_reg_cop_out_ready : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
signal \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\ : STD_LOGIC;
signal \^axi4_lite_rvalid\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal aw_transfer : STD_LOGIC;
signal \axi_lite_rstate[0]_i_1_n_0\ : STD_LOGIC;
signal axi_lite_wstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axi_lite_wstate[0]_i_1_n_0\ : STD_LOGIC;
signal \axi_lite_wstate_next_inferred__1/i__n_0\ : STD_LOGIC;
signal data_read : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reset : STD_LOGIC;
signal sel0 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal soft_reset : STD_LOGIC;
signal soft_reset_i_2_n_0 : STD_LOGIC;
signal soft_reset_i_3_n_0 : STD_LOGIC;
signal soft_reset_i_4_n_0 : STD_LOGIC;
signal strobe_reg_cop_in_strobe_i_3_n_0 : STD_LOGIC;
signal strobe_sw : STD_LOGIC;
signal top_rd_enb : STD_LOGIC;
signal top_wr_enb : STD_LOGIC;
signal w_transfer : STD_LOGIC;
signal write_reg_axi_enable_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of AXI4_Lite_BVALID_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_7\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of AXI4_Lite_WREADY_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axi_lite_rstate[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axi_lite_wstate[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \axi_lite_wstate_next_inferred__1/i_\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of strobe_reg_cop_in_strobe_i_3 : label is "soft_lutpair1";
begin
AXI4_Lite_RVALID <= \^axi4_lite_rvalid\;
Q(15 downto 0) <= \^q\(15 downto 0);
AXI4_Lite_ARREADY_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi4_lite_rvalid\,
O => AXI4_Lite_ARREADY
);
AXI4_Lite_AWREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_AWREADY
);
AXI4_Lite_BVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(1),
I1 => axi_lite_wstate(0),
O => AXI4_Lite_BVALID
);
\AXI4_Lite_RDATA_tmp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008CCC00008000"
)
port map (
I0 => \sync_reg_e_k_reg[15]\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\,
O => data_read(0)
);
\AXI4_Lite_RDATA_tmp[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(6),
I1 => AXI4_Lite_ARADDR(6),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\
);
\AXI4_Lite_RDATA_tmp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B80000000000"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I5 => read_reg_cop_out_ready,
O => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\
);
\AXI4_Lite_RDATA_tmp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(10),
O => data_read(10)
);
\AXI4_Lite_RDATA_tmp[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(11),
O => data_read(11)
);
\AXI4_Lite_RDATA_tmp[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(12),
O => data_read(12)
);
\AXI4_Lite_RDATA_tmp[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(13),
O => data_read(13)
);
\AXI4_Lite_RDATA_tmp[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(14),
O => data_read(14)
);
\AXI4_Lite_RDATA_tmp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(1),
O => data_read(1)
);
\AXI4_Lite_RDATA_tmp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(2),
O => data_read(2)
);
\AXI4_Lite_RDATA_tmp[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => AXI4_Lite_ARVALID,
I1 => \^axi4_lite_rvalid\,
O => top_rd_enb
);
\AXI4_Lite_RDATA_tmp[31]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(5),
I1 => sel0(4),
I2 => AXI4_Lite_ARADDR(5),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(4),
O => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(3),
I1 => sel0(2),
I2 => AXI4_Lite_ARADDR(3),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(2),
O => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(9),
I1 => sel0(8),
I2 => AXI4_Lite_ARADDR(9),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(8),
O => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(15),
O => data_read(31)
);
\AXI4_Lite_RDATA_tmp[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => AXI4_Lite_ARESETN,
O => reset
);
\AXI4_Lite_RDATA_tmp[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFEFFFFAEFEA"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\,
I1 => AXI4_Lite_ARADDR(10),
I2 => AXI4_Lite_ARVALID,
I3 => sel0(10),
I4 => AXI4_Lite_ARADDR(11),
I5 => sel0(11),
O => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(1),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(1),
O => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
O => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
O => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"00011101"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\,
I2 => sel0(7),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(7),
O => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => AXI4_Lite_ARADDR(13),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(13),
I3 => AXI4_Lite_ARADDR(12),
I4 => sel0(12),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\,
O => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\
);
\AXI4_Lite_RDATA_tmp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(3),
O => data_read(3)
);
\AXI4_Lite_RDATA_tmp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(4),
O => data_read(4)
);
\AXI4_Lite_RDATA_tmp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(5),
O => data_read(5)
);
\AXI4_Lite_RDATA_tmp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(6),
O => data_read(6)
);
\AXI4_Lite_RDATA_tmp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(7),
O => data_read(7)
);
\AXI4_Lite_RDATA_tmp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(8),
O => data_read(8)
);
\AXI4_Lite_RDATA_tmp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(9),
O => data_read(9)
);
\AXI4_Lite_RDATA_tmp_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(0),
Q => AXI4_Lite_RDATA(0)
);
\AXI4_Lite_RDATA_tmp_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(10),
Q => AXI4_Lite_RDATA(10)
);
\AXI4_Lite_RDATA_tmp_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(11),
Q => AXI4_Lite_RDATA(11)
);
\AXI4_Lite_RDATA_tmp_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(12),
Q => AXI4_Lite_RDATA(12)
);
\AXI4_Lite_RDATA_tmp_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(13),
Q => AXI4_Lite_RDATA(13)
);
\AXI4_Lite_RDATA_tmp_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(14),
Q => AXI4_Lite_RDATA(14)
);
\AXI4_Lite_RDATA_tmp_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(1),
Q => AXI4_Lite_RDATA(1)
);
\AXI4_Lite_RDATA_tmp_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(2),
Q => AXI4_Lite_RDATA(2)
);
\AXI4_Lite_RDATA_tmp_reg[31]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(31),
Q => AXI4_Lite_RDATA(15)
);
\AXI4_Lite_RDATA_tmp_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(3),
Q => AXI4_Lite_RDATA(3)
);
\AXI4_Lite_RDATA_tmp_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(4),
Q => AXI4_Lite_RDATA(4)
);
\AXI4_Lite_RDATA_tmp_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(5),
Q => AXI4_Lite_RDATA(5)
);
\AXI4_Lite_RDATA_tmp_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(6),
Q => AXI4_Lite_RDATA(6)
);
\AXI4_Lite_RDATA_tmp_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(7),
Q => AXI4_Lite_RDATA(7)
);
\AXI4_Lite_RDATA_tmp_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(8),
Q => AXI4_Lite_RDATA(8)
);
\AXI4_Lite_RDATA_tmp_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(9),
Q => AXI4_Lite_RDATA(9)
);
AXI4_Lite_WREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_WREADY
);
\axi_lite_rstate[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => AXI4_Lite_RREADY,
I1 => \^axi4_lite_rvalid\,
I2 => AXI4_Lite_ARVALID,
O => \axi_lite_rstate[0]_i_1_n_0\
);
\axi_lite_rstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_rstate[0]_i_1_n_0\,
Q => \^axi4_lite_rvalid\
);
\axi_lite_wstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"002E"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(0),
I2 => AXI4_Lite_WVALID,
I3 => axi_lite_wstate(1),
O => \axi_lite_wstate[0]_i_1_n_0\
);
\axi_lite_wstate_next_inferred__1/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"0838"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(0),
I2 => axi_lite_wstate(1),
I3 => AXI4_Lite_BREADY,
O => \axi_lite_wstate_next_inferred__1/i__n_0\
);
\axi_lite_wstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate[0]_i_1_n_0\,
Q => axi_lite_wstate(0)
);
\axi_lite_wstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate_next_inferred__1/i__n_0\,
Q => axi_lite_wstate(1)
);
soft_reset_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => soft_reset_i_2_n_0,
I1 => sel0(1),
I2 => sel0(0),
I3 => sel0(7),
I4 => sel0(6),
I5 => soft_reset_i_3_n_0,
O => strobe_sw
);
soft_reset_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(13),
I1 => sel0(12),
I2 => sel0(11),
I3 => sel0(10),
O => soft_reset_i_2_n_0
);
soft_reset_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => sel0(2),
I1 => sel0(3),
I2 => sel0(8),
I3 => sel0(9),
I4 => soft_reset_i_4_n_0,
O => soft_reset_i_3_n_0
);
soft_reset_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => top_wr_enb,
I1 => \^q\(0),
I2 => sel0(5),
I3 => sel0(4),
O => soft_reset_i_4_n_0
);
soft_reset_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => strobe_sw,
Q => soft_reset
);
strobe_reg_cop_in_strobe_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \^q\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => strobe_reg_cop_in_strobe_i_3_n_0,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => strobe_sw_cop_in_strobe
);
strobe_reg_cop_in_strobe_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => AXI4_Lite_ARESETN,
I1 => soft_reset,
I2 => IPCORE_RESETN,
O => write_reg_axi_enable_reg
);
strobe_reg_cop_in_strobe_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(1),
I1 => AXI4_Lite_ARADDR(1),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => strobe_reg_cop_in_strobe_i_3_n_0
);
\waddr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => aw_transfer
);
\waddr_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(8),
Q => sel0(8)
);
\waddr_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(9),
Q => sel0(9)
);
\waddr_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(10),
Q => sel0(10)
);
\waddr_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(11),
Q => sel0(11)
);
\waddr_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(12),
Q => sel0(12)
);
\waddr_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(13),
Q => sel0(13)
);
\waddr_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(0),
Q => sel0(0)
);
\waddr_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(1),
Q => sel0(1)
);
\waddr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(2),
Q => sel0(2)
);
\waddr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(3),
Q => sel0(3)
);
\waddr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(4),
Q => sel0(4)
);
\waddr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(5),
Q => sel0(5)
);
\waddr_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(6),
Q => sel0(6)
);
\waddr_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(7),
Q => sel0(7)
);
\wdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => w_transfer
);
\wdata_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(0),
Q => \^q\(0)
);
\wdata_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(10),
Q => \^q\(10)
);
\wdata_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(11),
Q => \^q\(11)
);
\wdata_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(12),
Q => \^q\(12)
);
\wdata_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(13),
Q => \^q\(13)
);
\wdata_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(14),
Q => \^q\(14)
);
\wdata_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(15),
Q => \^q\(15)
);
\wdata_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(1),
Q => \^q\(1)
);
\wdata_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(2),
Q => \^q\(2)
);
\wdata_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(3),
Q => \^q\(3)
);
\wdata_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(4),
Q => \^q\(4)
);
\wdata_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(5),
Q => \^q\(5)
);
\wdata_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(6),
Q => \^q\(6)
);
\wdata_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(7),
Q => \^q\(7)
);
\wdata_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(8),
Q => \^q\(8)
);
\wdata_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(9),
Q => \^q\(9)
);
wr_enb_1_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => w_transfer,
Q => top_wr_enb
);
write_reg_axi_enable_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => write_reg_axi_enable_i_2_n_0,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I3 => top_wr_enb,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => write_reg_axi_enable,
O => write_reg_axi_enable_reg_0
);
write_reg_axi_enable_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
I3 => AXI4_Lite_ARADDR(0),
I4 => sel0(0),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
O => write_reg_axi_enable_i_2_n_0
);
\write_reg_d_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => \write_reg_d_k_reg[15]\(0)
);
\write_reg_x_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
port (
cp_controller_cpstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
cop_out_ready : out STD_LOGIC;
cop_dut_enable : out STD_LOGIC;
strobe_reg_cop_in_strobe_reg : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
write_reg_axi_enable : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
signal \^cp_controller_cpstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cp_controller_cpstate[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cp_controller_cpstate[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of read_reg_cop_out_ready_i_1 : label is "soft_lutpair5";
begin
cp_controller_cpstate(1 downto 0) <= \^cp_controller_cpstate\(1 downto 0);
\cp_controller_cpstate[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"38"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => write_reg_axi_enable,
I2 => \^cp_controller_cpstate\(1),
O => \cp_controller_cpstate[1]_i_1_n_0\
);
\cp_controller_cpstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => strobe_reg_cop_in_strobe_reg,
Q => \^cp_controller_cpstate\(0)
);
\cp_controller_cpstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => \cp_controller_cpstate[1]_i_1_n_0\,
Q => \^cp_controller_cpstate\(1)
);
\data_pipeline_tmp[14][15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_dut_enable
);
read_reg_cop_out_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_out_ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
port (
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
cop_out_ready : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
signal read_reg_cop_out_ready : STD_LOGIC;
signal reg_enb_d_k : STD_LOGIC;
signal reg_enb_x_k : STD_LOGIC;
signal strobe_sw_cop_in_strobe : STD_LOGIC;
signal sync_reg_e_k : STD_LOGIC_VECTOR ( 15 downto 0 );
signal top_data_write : STD_LOGIC_VECTOR ( 0 to 0 );
signal u_lms_pcore_axi_lite_module_inst_n_10 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_11 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_12 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_13 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_14 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_15 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_16 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_17 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_18 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_19 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_4 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_8 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_9 : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal \^write_reg_axi_enable_reg\ : STD_LOGIC;
begin
write_reg_axi_enable <= \^write_reg_axi_enable\;
write_reg_axi_enable_reg <= \^write_reg_axi_enable_reg\;
u_lms_pcore_addr_decoder_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder
port map (
AR(0) => \^write_reg_axi_enable_reg\,
\ARG__28\(15 downto 0) => \ARG__28\(15 downto 0),
\ARG__29\(2 downto 0) => \ARG__29\(2 downto 0),
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
\AXI4_Lite_RDATA_tmp_reg[31]\(15 downto 0) => sync_reg_e_k(15 downto 0),
DI(0) => DI(0),
E(0) => reg_enb_x_k,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => \cp_controller_cpstate_reg[0]\,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[11]_0\(3 downto 0) => \sync_reg_e_k_reg[11]\(3 downto 0),
\sync_reg_e_k_reg[3]_0\(3 downto 0) => \sync_reg_e_k_reg[3]\(3 downto 0),
\sync_reg_e_k_reg[7]_0\(3 downto 0) => \sync_reg_e_k_reg[7]\(3 downto 0),
\wdata_reg[0]\ => u_lms_pcore_axi_lite_module_inst_n_4,
\wdata_reg[15]\(15) => u_lms_pcore_axi_lite_module_inst_n_5,
\wdata_reg[15]\(14) => u_lms_pcore_axi_lite_module_inst_n_6,
\wdata_reg[15]\(13) => u_lms_pcore_axi_lite_module_inst_n_7,
\wdata_reg[15]\(12) => u_lms_pcore_axi_lite_module_inst_n_8,
\wdata_reg[15]\(11) => u_lms_pcore_axi_lite_module_inst_n_9,
\wdata_reg[15]\(10) => u_lms_pcore_axi_lite_module_inst_n_10,
\wdata_reg[15]\(9) => u_lms_pcore_axi_lite_module_inst_n_11,
\wdata_reg[15]\(8) => u_lms_pcore_axi_lite_module_inst_n_12,
\wdata_reg[15]\(7) => u_lms_pcore_axi_lite_module_inst_n_13,
\wdata_reg[15]\(6) => u_lms_pcore_axi_lite_module_inst_n_14,
\wdata_reg[15]\(5) => u_lms_pcore_axi_lite_module_inst_n_15,
\wdata_reg[15]\(4) => u_lms_pcore_axi_lite_module_inst_n_16,
\wdata_reg[15]\(3) => u_lms_pcore_axi_lite_module_inst_n_17,
\wdata_reg[15]\(2) => u_lms_pcore_axi_lite_module_inst_n_18,
\wdata_reg[15]\(1) => u_lms_pcore_axi_lite_module_inst_n_19,
\wdata_reg[15]\(0) => top_data_write(0),
wr_enb_1_reg(0) => reg_enb_d_k,
write_reg_axi_enable => \^write_reg_axi_enable\
);
u_lms_pcore_axi_lite_module_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
E(0) => reg_enb_x_k,
IPCORE_RESETN => IPCORE_RESETN,
Q(15) => u_lms_pcore_axi_lite_module_inst_n_5,
Q(14) => u_lms_pcore_axi_lite_module_inst_n_6,
Q(13) => u_lms_pcore_axi_lite_module_inst_n_7,
Q(12) => u_lms_pcore_axi_lite_module_inst_n_8,
Q(11) => u_lms_pcore_axi_lite_module_inst_n_9,
Q(10) => u_lms_pcore_axi_lite_module_inst_n_10,
Q(9) => u_lms_pcore_axi_lite_module_inst_n_11,
Q(8) => u_lms_pcore_axi_lite_module_inst_n_12,
Q(7) => u_lms_pcore_axi_lite_module_inst_n_13,
Q(6) => u_lms_pcore_axi_lite_module_inst_n_14,
Q(5) => u_lms_pcore_axi_lite_module_inst_n_15,
Q(4) => u_lms_pcore_axi_lite_module_inst_n_16,
Q(3) => u_lms_pcore_axi_lite_module_inst_n_17,
Q(2) => u_lms_pcore_axi_lite_module_inst_n_18,
Q(1) => u_lms_pcore_axi_lite_module_inst_n_19,
Q(0) => top_data_write(0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[15]\(15 downto 0) => sync_reg_e_k(15 downto 0),
write_reg_axi_enable => \^write_reg_axi_enable\,
write_reg_axi_enable_reg => \^write_reg_axi_enable_reg\,
write_reg_axi_enable_reg_0 => u_lms_pcore_axi_lite_module_inst_n_4,
\write_reg_d_k_reg[15]\(0) => reg_enb_d_k
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
begin
u_LMS: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS
port map (
AR(0) => AR(0),
DI(0) => DI(0),
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
\write_reg_d_k_reg[11]\(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0),
\write_reg_d_k_reg[3]\(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0),
\write_reg_d_k_reg[3]_0\(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0),
\write_reg_d_k_reg[7]\(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0),
\write_reg_x_k_reg[15]\(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
port (
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
IPCORE_CLK : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
signal cop_dut_enable : STD_LOGIC;
signal cop_out_ready : STD_LOGIC;
signal cp_controller_cpstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal filter_sum : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \u_LMS/mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal u_lms_pcore_axi_lite_inst_n_0 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_24 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_25 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_26 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_27 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_28 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_29 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_30 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_31 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_32 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_33 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_34 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_35 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_36 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_37 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_38 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_39 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_40 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_8 : STD_LOGIC;
signal write_reg_axi_enable : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 14 downto 0 );
signal write_reg_x_k : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
u_lms_pcore_axi_lite_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite
port map (
\ARG__28\(15 downto 0) => write_reg_x_k(15 downto 0),
\ARG__29\(2) => u_lms_pcore_axi_lite_inst_n_37,
\ARG__29\(1) => u_lms_pcore_axi_lite_inst_n_38,
\ARG__29\(0) => u_lms_pcore_axi_lite_inst_n_39,
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_RESETN => IPCORE_RESETN,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => u_lms_pcore_axi_lite_inst_n_40,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\sync_reg_e_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\sync_reg_e_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\sync_reg_e_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\sync_reg_e_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\sync_reg_e_k_reg[3]\(3) => u_lms_pcore_axi_lite_inst_n_32,
\sync_reg_e_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_33,
\sync_reg_e_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_34,
\sync_reg_e_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_35,
\sync_reg_e_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\sync_reg_e_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\sync_reg_e_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\sync_reg_e_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
write_reg_axi_enable => write_reg_axi_enable,
write_reg_axi_enable_reg => u_lms_pcore_axi_lite_inst_n_0
);
u_lms_pcore_cop_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
IPCORE_CLK => IPCORE_CLK,
cop_dut_enable => cop_dut_enable,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
strobe_reg_cop_in_strobe_reg => u_lms_pcore_axi_lite_inst_n_40,
write_reg_axi_enable => write_reg_axi_enable
);
u_lms_pcore_dut_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\write_reg_d_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\write_reg_d_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\write_reg_d_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\write_reg_d_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\write_reg_d_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_37,
\write_reg_d_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_38,
\write_reg_d_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_39,
\write_reg_d_k_reg[3]_0\(3) => u_lms_pcore_axi_lite_inst_n_32,
\write_reg_d_k_reg[3]_0\(2) => u_lms_pcore_axi_lite_inst_n_33,
\write_reg_d_k_reg[3]_0\(1) => u_lms_pcore_axi_lite_inst_n_34,
\write_reg_d_k_reg[3]_0\(0) => u_lms_pcore_axi_lite_inst_n_35,
\write_reg_d_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\write_reg_d_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\write_reg_d_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\write_reg_d_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
\write_reg_x_k_reg[15]\(15 downto 0) => write_reg_x_k(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_lms_pcore_0_0,lms_pcore,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "lms_pcore,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^axi4_lite_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
attribute x_interface_info : string;
attribute x_interface_info of AXI4_Lite_ACLK : signal is "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXI4_Lite_ACLK : signal is "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of AXI4_Lite_ARESETN : signal is "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST";
attribute x_interface_parameter of AXI4_Lite_ARESETN : signal is "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY";
attribute x_interface_info of AXI4_Lite_ARVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID";
attribute x_interface_info of AXI4_Lite_AWREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY";
attribute x_interface_info of AXI4_Lite_AWVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID";
attribute x_interface_info of AXI4_Lite_BREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY";
attribute x_interface_info of AXI4_Lite_BVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID";
attribute x_interface_info of AXI4_Lite_RREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY";
attribute x_interface_info of AXI4_Lite_RVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID";
attribute x_interface_info of AXI4_Lite_WREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY";
attribute x_interface_info of AXI4_Lite_WVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID";
attribute x_interface_info of IPCORE_CLK : signal is "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK";
attribute x_interface_parameter of IPCORE_CLK : signal is "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of IPCORE_RESETN : signal is "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST";
attribute x_interface_parameter of IPCORE_RESETN : signal is "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR";
attribute x_interface_info of AXI4_Lite_AWADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR";
attribute x_interface_parameter of AXI4_Lite_AWADDR : signal is "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of AXI4_Lite_BRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP";
attribute x_interface_info of AXI4_Lite_RDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA";
attribute x_interface_info of AXI4_Lite_RRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP";
attribute x_interface_info of AXI4_Lite_WDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA";
attribute x_interface_info of AXI4_Lite_WSTRB : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB";
begin
AXI4_Lite_BRESP(1) <= \<const0>\;
AXI4_Lite_BRESP(0) <= \<const0>\;
AXI4_Lite_RDATA(31) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(30) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(29) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(28) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(27) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(26) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(25) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(24) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(23) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(22) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(21) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(20) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(19) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(18) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(17) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(16) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(15) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(14 downto 0) <= \^axi4_lite_rdata\(14 downto 0);
AXI4_Lite_RRESP(1) <= \<const0>\;
AXI4_Lite_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(15 downto 2),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(15 downto 2),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15) => \^axi4_lite_rdata\(30),
AXI4_Lite_RDATA(14 downto 0) => \^axi4_lite_rdata\(14 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
IPCORE_CLK => IPCORE_CLK,
IPCORE_RESETN => IPCORE_RESETN
);
end STRUCTURE;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04 is
end entity inline_04;
----------------------------------------------------------------
architecture test of inline_04 is
begin
process_2_a : process is
-- code from book:
alias binary_string is bit_vector;
variable s1, s2 : binary_string(0 to 7);
-- . . .
-- end of code from book
begin
s1 := "10101010";
s2 := "11110000";
-- code from book:
s1 := s1 and not s2;
-- end of code from book
wait;
end process process_2_a;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04 is
end entity inline_04;
----------------------------------------------------------------
architecture test of inline_04 is
begin
process_2_a : process is
-- code from book:
alias binary_string is bit_vector;
variable s1, s2 : binary_string(0 to 7);
-- . . .
-- end of code from book
begin
s1 := "10101010";
s2 := "11110000";
-- code from book:
s1 := s1 and not s2;
-- end of code from book
wait;
end process process_2_a;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_04 is
end entity inline_04;
----------------------------------------------------------------
architecture test of inline_04 is
begin
process_2_a : process is
-- code from book:
alias binary_string is bit_vector;
variable s1, s2 : binary_string(0 to 7);
-- . . .
-- end of code from book
begin
s1 := "10101010";
s2 := "11110000";
-- code from book:
s1 := s1 and not s2;
-- end of code from book
wait;
end process process_2_a;
end architecture test;
|
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 16;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(512,AMPL_WIDTH),
conv_std_logic_vector(515,AMPL_WIDTH),
conv_std_logic_vector(518,AMPL_WIDTH),
conv_std_logic_vector(521,AMPL_WIDTH),
conv_std_logic_vector(525,AMPL_WIDTH),
conv_std_logic_vector(528,AMPL_WIDTH),
conv_std_logic_vector(531,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(537,AMPL_WIDTH),
conv_std_logic_vector(540,AMPL_WIDTH),
conv_std_logic_vector(543,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(553,AMPL_WIDTH),
conv_std_logic_vector(556,AMPL_WIDTH),
conv_std_logic_vector(559,AMPL_WIDTH),
conv_std_logic_vector(562,AMPL_WIDTH),
conv_std_logic_vector(565,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(591,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(597,AMPL_WIDTH),
conv_std_logic_vector(600,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(609,AMPL_WIDTH),
conv_std_logic_vector(613,AMPL_WIDTH),
conv_std_logic_vector(616,AMPL_WIDTH),
conv_std_logic_vector(619,AMPL_WIDTH),
conv_std_logic_vector(622,AMPL_WIDTH),
conv_std_logic_vector(625,AMPL_WIDTH),
conv_std_logic_vector(628,AMPL_WIDTH),
conv_std_logic_vector(631,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(657,AMPL_WIDTH),
conv_std_logic_vector(660,AMPL_WIDTH),
conv_std_logic_vector(663,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(669,AMPL_WIDTH),
conv_std_logic_vector(672,AMPL_WIDTH),
conv_std_logic_vector(675,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(682,AMPL_WIDTH),
conv_std_logic_vector(685,AMPL_WIDTH),
conv_std_logic_vector(688,AMPL_WIDTH),
conv_std_logic_vector(691,AMPL_WIDTH),
conv_std_logic_vector(694,AMPL_WIDTH),
conv_std_logic_vector(697,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(716,AMPL_WIDTH),
conv_std_logic_vector(719,AMPL_WIDTH),
conv_std_logic_vector(722,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(738,AMPL_WIDTH),
conv_std_logic_vector(741,AMPL_WIDTH),
conv_std_logic_vector(744,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(757,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(763,AMPL_WIDTH),
conv_std_logic_vector(766,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(773,AMPL_WIDTH),
conv_std_logic_vector(776,AMPL_WIDTH),
conv_std_logic_vector(779,AMPL_WIDTH),
conv_std_logic_vector(782,AMPL_WIDTH),
conv_std_logic_vector(785,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(792,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(798,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(810,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(820,AMPL_WIDTH),
conv_std_logic_vector(823,AMPL_WIDTH),
conv_std_logic_vector(826,AMPL_WIDTH),
conv_std_logic_vector(829,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(836,AMPL_WIDTH),
conv_std_logic_vector(839,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(848,AMPL_WIDTH),
conv_std_logic_vector(851,AMPL_WIDTH),
conv_std_logic_vector(854,AMPL_WIDTH),
conv_std_logic_vector(858,AMPL_WIDTH),
conv_std_logic_vector(861,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(873,AMPL_WIDTH),
conv_std_logic_vector(876,AMPL_WIDTH),
conv_std_logic_vector(880,AMPL_WIDTH),
conv_std_logic_vector(883,AMPL_WIDTH),
conv_std_logic_vector(886,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(892,AMPL_WIDTH),
conv_std_logic_vector(895,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(905,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(914,AMPL_WIDTH),
conv_std_logic_vector(917,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(923,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(930,AMPL_WIDTH),
conv_std_logic_vector(933,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(942,AMPL_WIDTH),
conv_std_logic_vector(945,AMPL_WIDTH),
conv_std_logic_vector(949,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(958,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(967,AMPL_WIDTH),
conv_std_logic_vector(971,AMPL_WIDTH),
conv_std_logic_vector(974,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(980,AMPL_WIDTH),
conv_std_logic_vector(983,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(989,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(996,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(1002,AMPL_WIDTH),
conv_std_logic_vector(1005,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1011,AMPL_WIDTH),
conv_std_logic_vector(1015,AMPL_WIDTH),
conv_std_logic_vector(1018,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1024,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1030,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1037,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1043,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1049,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1059,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1065,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1071,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1080,AMPL_WIDTH),
conv_std_logic_vector(1084,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1093,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1099,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1109,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1115,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1121,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1128,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1134,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1140,AMPL_WIDTH),
conv_std_logic_vector(1143,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1153,AMPL_WIDTH),
conv_std_logic_vector(1156,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1162,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1178,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1187,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1194,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1203,AMPL_WIDTH),
conv_std_logic_vector(1206,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1215,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1222,AMPL_WIDTH),
conv_std_logic_vector(1225,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1237,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1247,AMPL_WIDTH),
conv_std_logic_vector(1250,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1263,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1281,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1307,AMPL_WIDTH),
conv_std_logic_vector(1310,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1350,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1360,AMPL_WIDTH),
conv_std_logic_vector(1363,AMPL_WIDTH),
conv_std_logic_vector(1366,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1388,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1416,AMPL_WIDTH),
conv_std_logic_vector(1420,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1429,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1438,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1448,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1470,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1476,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1482,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1489,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1504,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2050,AMPL_WIDTH),
conv_std_logic_vector(2053,AMPL_WIDTH),
conv_std_logic_vector(2056,AMPL_WIDTH),
conv_std_logic_vector(2059,AMPL_WIDTH),
conv_std_logic_vector(2063,AMPL_WIDTH),
conv_std_logic_vector(2066,AMPL_WIDTH),
conv_std_logic_vector(2069,AMPL_WIDTH),
conv_std_logic_vector(2072,AMPL_WIDTH),
conv_std_logic_vector(2075,AMPL_WIDTH),
conv_std_logic_vector(2078,AMPL_WIDTH),
conv_std_logic_vector(2081,AMPL_WIDTH),
conv_std_logic_vector(2085,AMPL_WIDTH),
conv_std_logic_vector(2088,AMPL_WIDTH),
conv_std_logic_vector(2091,AMPL_WIDTH),
conv_std_logic_vector(2094,AMPL_WIDTH),
conv_std_logic_vector(2097,AMPL_WIDTH),
conv_std_logic_vector(2100,AMPL_WIDTH),
conv_std_logic_vector(2103,AMPL_WIDTH),
conv_std_logic_vector(2106,AMPL_WIDTH),
conv_std_logic_vector(2110,AMPL_WIDTH),
conv_std_logic_vector(2113,AMPL_WIDTH),
conv_std_logic_vector(2116,AMPL_WIDTH),
conv_std_logic_vector(2119,AMPL_WIDTH),
conv_std_logic_vector(2122,AMPL_WIDTH),
conv_std_logic_vector(2125,AMPL_WIDTH),
conv_std_logic_vector(2128,AMPL_WIDTH),
conv_std_logic_vector(2132,AMPL_WIDTH),
conv_std_logic_vector(2135,AMPL_WIDTH),
conv_std_logic_vector(2138,AMPL_WIDTH),
conv_std_logic_vector(2141,AMPL_WIDTH),
conv_std_logic_vector(2144,AMPL_WIDTH),
conv_std_logic_vector(2147,AMPL_WIDTH),
conv_std_logic_vector(2150,AMPL_WIDTH),
conv_std_logic_vector(2154,AMPL_WIDTH),
conv_std_logic_vector(2157,AMPL_WIDTH),
conv_std_logic_vector(2160,AMPL_WIDTH),
conv_std_logic_vector(2163,AMPL_WIDTH),
conv_std_logic_vector(2166,AMPL_WIDTH),
conv_std_logic_vector(2169,AMPL_WIDTH),
conv_std_logic_vector(2172,AMPL_WIDTH),
conv_std_logic_vector(2175,AMPL_WIDTH),
conv_std_logic_vector(2179,AMPL_WIDTH),
conv_std_logic_vector(2182,AMPL_WIDTH),
conv_std_logic_vector(2185,AMPL_WIDTH),
conv_std_logic_vector(2188,AMPL_WIDTH),
conv_std_logic_vector(2191,AMPL_WIDTH),
conv_std_logic_vector(2194,AMPL_WIDTH),
conv_std_logic_vector(2197,AMPL_WIDTH),
conv_std_logic_vector(2201,AMPL_WIDTH),
conv_std_logic_vector(2204,AMPL_WIDTH),
conv_std_logic_vector(2207,AMPL_WIDTH),
conv_std_logic_vector(2210,AMPL_WIDTH),
conv_std_logic_vector(2213,AMPL_WIDTH),
conv_std_logic_vector(2216,AMPL_WIDTH),
conv_std_logic_vector(2219,AMPL_WIDTH),
conv_std_logic_vector(2222,AMPL_WIDTH),
conv_std_logic_vector(2226,AMPL_WIDTH),
conv_std_logic_vector(2229,AMPL_WIDTH),
conv_std_logic_vector(2232,AMPL_WIDTH),
conv_std_logic_vector(2235,AMPL_WIDTH),
conv_std_logic_vector(2238,AMPL_WIDTH),
conv_std_logic_vector(2241,AMPL_WIDTH),
conv_std_logic_vector(2244,AMPL_WIDTH),
conv_std_logic_vector(2248,AMPL_WIDTH),
conv_std_logic_vector(2251,AMPL_WIDTH),
conv_std_logic_vector(2254,AMPL_WIDTH),
conv_std_logic_vector(2257,AMPL_WIDTH),
conv_std_logic_vector(2260,AMPL_WIDTH),
conv_std_logic_vector(2263,AMPL_WIDTH),
conv_std_logic_vector(2266,AMPL_WIDTH),
conv_std_logic_vector(2269,AMPL_WIDTH),
conv_std_logic_vector(2273,AMPL_WIDTH),
conv_std_logic_vector(2276,AMPL_WIDTH),
conv_std_logic_vector(2279,AMPL_WIDTH),
conv_std_logic_vector(2282,AMPL_WIDTH),
conv_std_logic_vector(2285,AMPL_WIDTH),
conv_std_logic_vector(2288,AMPL_WIDTH),
conv_std_logic_vector(2291,AMPL_WIDTH),
conv_std_logic_vector(2295,AMPL_WIDTH),
conv_std_logic_vector(2298,AMPL_WIDTH),
conv_std_logic_vector(2301,AMPL_WIDTH),
conv_std_logic_vector(2304,AMPL_WIDTH),
conv_std_logic_vector(2307,AMPL_WIDTH),
conv_std_logic_vector(2310,AMPL_WIDTH),
conv_std_logic_vector(2313,AMPL_WIDTH),
conv_std_logic_vector(2316,AMPL_WIDTH),
conv_std_logic_vector(2320,AMPL_WIDTH),
conv_std_logic_vector(2323,AMPL_WIDTH),
conv_std_logic_vector(2326,AMPL_WIDTH),
conv_std_logic_vector(2329,AMPL_WIDTH),
conv_std_logic_vector(2332,AMPL_WIDTH),
conv_std_logic_vector(2335,AMPL_WIDTH),
conv_std_logic_vector(2338,AMPL_WIDTH),
conv_std_logic_vector(2342,AMPL_WIDTH),
conv_std_logic_vector(2345,AMPL_WIDTH),
conv_std_logic_vector(2348,AMPL_WIDTH),
conv_std_logic_vector(2351,AMPL_WIDTH),
conv_std_logic_vector(2354,AMPL_WIDTH),
conv_std_logic_vector(2357,AMPL_WIDTH),
conv_std_logic_vector(2360,AMPL_WIDTH),
conv_std_logic_vector(2363,AMPL_WIDTH),
conv_std_logic_vector(2367,AMPL_WIDTH),
conv_std_logic_vector(2370,AMPL_WIDTH),
conv_std_logic_vector(2373,AMPL_WIDTH),
conv_std_logic_vector(2376,AMPL_WIDTH),
conv_std_logic_vector(2379,AMPL_WIDTH),
conv_std_logic_vector(2382,AMPL_WIDTH),
conv_std_logic_vector(2385,AMPL_WIDTH),
conv_std_logic_vector(2389,AMPL_WIDTH),
conv_std_logic_vector(2392,AMPL_WIDTH),
conv_std_logic_vector(2395,AMPL_WIDTH),
conv_std_logic_vector(2398,AMPL_WIDTH),
conv_std_logic_vector(2401,AMPL_WIDTH),
conv_std_logic_vector(2404,AMPL_WIDTH),
conv_std_logic_vector(2407,AMPL_WIDTH),
conv_std_logic_vector(2410,AMPL_WIDTH),
conv_std_logic_vector(2414,AMPL_WIDTH),
conv_std_logic_vector(2417,AMPL_WIDTH),
conv_std_logic_vector(2420,AMPL_WIDTH),
conv_std_logic_vector(2423,AMPL_WIDTH),
conv_std_logic_vector(2426,AMPL_WIDTH),
conv_std_logic_vector(2429,AMPL_WIDTH),
conv_std_logic_vector(2432,AMPL_WIDTH),
conv_std_logic_vector(2436,AMPL_WIDTH),
conv_std_logic_vector(2439,AMPL_WIDTH),
conv_std_logic_vector(2442,AMPL_WIDTH),
conv_std_logic_vector(2445,AMPL_WIDTH),
conv_std_logic_vector(2448,AMPL_WIDTH),
conv_std_logic_vector(2451,AMPL_WIDTH),
conv_std_logic_vector(2454,AMPL_WIDTH),
conv_std_logic_vector(2457,AMPL_WIDTH),
conv_std_logic_vector(2461,AMPL_WIDTH),
conv_std_logic_vector(2464,AMPL_WIDTH),
conv_std_logic_vector(2467,AMPL_WIDTH),
conv_std_logic_vector(2470,AMPL_WIDTH),
conv_std_logic_vector(2473,AMPL_WIDTH),
conv_std_logic_vector(2476,AMPL_WIDTH),
conv_std_logic_vector(2479,AMPL_WIDTH),
conv_std_logic_vector(2483,AMPL_WIDTH),
conv_std_logic_vector(2486,AMPL_WIDTH),
conv_std_logic_vector(2489,AMPL_WIDTH),
conv_std_logic_vector(2492,AMPL_WIDTH),
conv_std_logic_vector(2495,AMPL_WIDTH),
conv_std_logic_vector(2498,AMPL_WIDTH),
conv_std_logic_vector(2501,AMPL_WIDTH),
conv_std_logic_vector(2504,AMPL_WIDTH),
conv_std_logic_vector(2508,AMPL_WIDTH),
conv_std_logic_vector(2511,AMPL_WIDTH),
conv_std_logic_vector(2514,AMPL_WIDTH),
conv_std_logic_vector(2517,AMPL_WIDTH),
conv_std_logic_vector(2520,AMPL_WIDTH),
conv_std_logic_vector(2523,AMPL_WIDTH),
conv_std_logic_vector(2526,AMPL_WIDTH),
conv_std_logic_vector(2530,AMPL_WIDTH),
conv_std_logic_vector(2533,AMPL_WIDTH),
conv_std_logic_vector(2536,AMPL_WIDTH),
conv_std_logic_vector(2539,AMPL_WIDTH),
conv_std_logic_vector(2542,AMPL_WIDTH),
conv_std_logic_vector(2545,AMPL_WIDTH),
conv_std_logic_vector(2548,AMPL_WIDTH),
conv_std_logic_vector(2551,AMPL_WIDTH),
conv_std_logic_vector(2555,AMPL_WIDTH),
conv_std_logic_vector(2558,AMPL_WIDTH),
conv_std_logic_vector(2561,AMPL_WIDTH),
conv_std_logic_vector(2564,AMPL_WIDTH),
conv_std_logic_vector(2567,AMPL_WIDTH),
conv_std_logic_vector(2570,AMPL_WIDTH),
conv_std_logic_vector(2573,AMPL_WIDTH),
conv_std_logic_vector(2577,AMPL_WIDTH),
conv_std_logic_vector(2580,AMPL_WIDTH),
conv_std_logic_vector(2583,AMPL_WIDTH),
conv_std_logic_vector(2586,AMPL_WIDTH),
conv_std_logic_vector(2589,AMPL_WIDTH),
conv_std_logic_vector(2592,AMPL_WIDTH),
conv_std_logic_vector(2595,AMPL_WIDTH),
conv_std_logic_vector(2598,AMPL_WIDTH),
conv_std_logic_vector(2602,AMPL_WIDTH),
conv_std_logic_vector(2605,AMPL_WIDTH),
conv_std_logic_vector(2608,AMPL_WIDTH),
conv_std_logic_vector(2611,AMPL_WIDTH),
conv_std_logic_vector(2614,AMPL_WIDTH),
conv_std_logic_vector(2617,AMPL_WIDTH),
conv_std_logic_vector(2620,AMPL_WIDTH),
conv_std_logic_vector(2623,AMPL_WIDTH),
conv_std_logic_vector(2627,AMPL_WIDTH),
conv_std_logic_vector(2630,AMPL_WIDTH),
conv_std_logic_vector(2633,AMPL_WIDTH),
conv_std_logic_vector(2636,AMPL_WIDTH),
conv_std_logic_vector(2639,AMPL_WIDTH),
conv_std_logic_vector(2642,AMPL_WIDTH),
conv_std_logic_vector(2645,AMPL_WIDTH),
conv_std_logic_vector(2649,AMPL_WIDTH),
conv_std_logic_vector(2652,AMPL_WIDTH),
conv_std_logic_vector(2655,AMPL_WIDTH),
conv_std_logic_vector(2658,AMPL_WIDTH),
conv_std_logic_vector(2661,AMPL_WIDTH),
conv_std_logic_vector(2664,AMPL_WIDTH),
conv_std_logic_vector(2667,AMPL_WIDTH),
conv_std_logic_vector(2670,AMPL_WIDTH),
conv_std_logic_vector(2674,AMPL_WIDTH),
conv_std_logic_vector(2677,AMPL_WIDTH),
conv_std_logic_vector(2680,AMPL_WIDTH),
conv_std_logic_vector(2683,AMPL_WIDTH),
conv_std_logic_vector(2686,AMPL_WIDTH),
conv_std_logic_vector(2689,AMPL_WIDTH),
conv_std_logic_vector(2692,AMPL_WIDTH),
conv_std_logic_vector(2695,AMPL_WIDTH),
conv_std_logic_vector(2699,AMPL_WIDTH),
conv_std_logic_vector(2702,AMPL_WIDTH),
conv_std_logic_vector(2705,AMPL_WIDTH),
conv_std_logic_vector(2708,AMPL_WIDTH),
conv_std_logic_vector(2711,AMPL_WIDTH),
conv_std_logic_vector(2714,AMPL_WIDTH),
conv_std_logic_vector(2717,AMPL_WIDTH),
conv_std_logic_vector(2721,AMPL_WIDTH),
conv_std_logic_vector(2724,AMPL_WIDTH),
conv_std_logic_vector(2727,AMPL_WIDTH),
conv_std_logic_vector(2730,AMPL_WIDTH),
conv_std_logic_vector(2733,AMPL_WIDTH),
conv_std_logic_vector(2736,AMPL_WIDTH),
conv_std_logic_vector(2739,AMPL_WIDTH),
conv_std_logic_vector(2742,AMPL_WIDTH),
conv_std_logic_vector(2746,AMPL_WIDTH),
conv_std_logic_vector(2749,AMPL_WIDTH),
conv_std_logic_vector(2752,AMPL_WIDTH),
conv_std_logic_vector(2755,AMPL_WIDTH),
conv_std_logic_vector(2758,AMPL_WIDTH),
conv_std_logic_vector(2761,AMPL_WIDTH),
conv_std_logic_vector(2764,AMPL_WIDTH),
conv_std_logic_vector(2767,AMPL_WIDTH),
conv_std_logic_vector(2771,AMPL_WIDTH),
conv_std_logic_vector(2774,AMPL_WIDTH),
conv_std_logic_vector(2777,AMPL_WIDTH),
conv_std_logic_vector(2780,AMPL_WIDTH),
conv_std_logic_vector(2783,AMPL_WIDTH),
conv_std_logic_vector(2786,AMPL_WIDTH),
conv_std_logic_vector(2789,AMPL_WIDTH),
conv_std_logic_vector(2793,AMPL_WIDTH),
conv_std_logic_vector(2796,AMPL_WIDTH),
conv_std_logic_vector(2799,AMPL_WIDTH),
conv_std_logic_vector(2802,AMPL_WIDTH),
conv_std_logic_vector(2805,AMPL_WIDTH),
conv_std_logic_vector(2808,AMPL_WIDTH),
conv_std_logic_vector(2811,AMPL_WIDTH),
conv_std_logic_vector(2814,AMPL_WIDTH),
conv_std_logic_vector(2818,AMPL_WIDTH),
conv_std_logic_vector(2821,AMPL_WIDTH),
conv_std_logic_vector(2824,AMPL_WIDTH),
conv_std_logic_vector(2827,AMPL_WIDTH),
conv_std_logic_vector(2830,AMPL_WIDTH),
conv_std_logic_vector(2833,AMPL_WIDTH),
conv_std_logic_vector(2836,AMPL_WIDTH),
conv_std_logic_vector(2839,AMPL_WIDTH),
conv_std_logic_vector(2843,AMPL_WIDTH),
conv_std_logic_vector(2846,AMPL_WIDTH),
conv_std_logic_vector(2849,AMPL_WIDTH),
conv_std_logic_vector(2852,AMPL_WIDTH),
conv_std_logic_vector(2855,AMPL_WIDTH),
conv_std_logic_vector(2858,AMPL_WIDTH),
conv_std_logic_vector(2861,AMPL_WIDTH),
conv_std_logic_vector(2865,AMPL_WIDTH),
conv_std_logic_vector(2868,AMPL_WIDTH),
conv_std_logic_vector(2871,AMPL_WIDTH),
conv_std_logic_vector(2874,AMPL_WIDTH),
conv_std_logic_vector(2877,AMPL_WIDTH),
conv_std_logic_vector(2880,AMPL_WIDTH),
conv_std_logic_vector(2883,AMPL_WIDTH),
conv_std_logic_vector(2886,AMPL_WIDTH),
conv_std_logic_vector(2890,AMPL_WIDTH),
conv_std_logic_vector(2893,AMPL_WIDTH),
conv_std_logic_vector(2896,AMPL_WIDTH),
conv_std_logic_vector(2899,AMPL_WIDTH),
conv_std_logic_vector(2902,AMPL_WIDTH),
conv_std_logic_vector(2905,AMPL_WIDTH),
conv_std_logic_vector(2908,AMPL_WIDTH),
conv_std_logic_vector(2911,AMPL_WIDTH),
conv_std_logic_vector(2915,AMPL_WIDTH),
conv_std_logic_vector(2918,AMPL_WIDTH),
conv_std_logic_vector(2921,AMPL_WIDTH),
conv_std_logic_vector(2924,AMPL_WIDTH),
conv_std_logic_vector(2927,AMPL_WIDTH),
conv_std_logic_vector(2930,AMPL_WIDTH),
conv_std_logic_vector(2933,AMPL_WIDTH),
conv_std_logic_vector(2936,AMPL_WIDTH),
conv_std_logic_vector(2940,AMPL_WIDTH),
conv_std_logic_vector(2943,AMPL_WIDTH),
conv_std_logic_vector(2946,AMPL_WIDTH),
conv_std_logic_vector(2949,AMPL_WIDTH),
conv_std_logic_vector(2952,AMPL_WIDTH),
conv_std_logic_vector(2955,AMPL_WIDTH),
conv_std_logic_vector(2958,AMPL_WIDTH),
conv_std_logic_vector(2962,AMPL_WIDTH),
conv_std_logic_vector(2965,AMPL_WIDTH),
conv_std_logic_vector(2968,AMPL_WIDTH),
conv_std_logic_vector(2971,AMPL_WIDTH),
conv_std_logic_vector(2974,AMPL_WIDTH),
conv_std_logic_vector(2977,AMPL_WIDTH),
conv_std_logic_vector(2980,AMPL_WIDTH),
conv_std_logic_vector(2983,AMPL_WIDTH),
conv_std_logic_vector(2987,AMPL_WIDTH),
conv_std_logic_vector(2990,AMPL_WIDTH),
conv_std_logic_vector(2993,AMPL_WIDTH),
conv_std_logic_vector(2996,AMPL_WIDTH),
conv_std_logic_vector(2999,AMPL_WIDTH),
conv_std_logic_vector(3002,AMPL_WIDTH),
conv_std_logic_vector(3005,AMPL_WIDTH),
conv_std_logic_vector(3008,AMPL_WIDTH),
conv_std_logic_vector(3012,AMPL_WIDTH),
conv_std_logic_vector(3015,AMPL_WIDTH),
conv_std_logic_vector(3018,AMPL_WIDTH),
conv_std_logic_vector(3021,AMPL_WIDTH),
conv_std_logic_vector(3024,AMPL_WIDTH),
conv_std_logic_vector(3027,AMPL_WIDTH),
conv_std_logic_vector(3030,AMPL_WIDTH),
conv_std_logic_vector(3033,AMPL_WIDTH),
conv_std_logic_vector(3037,AMPL_WIDTH),
conv_std_logic_vector(3040,AMPL_WIDTH),
conv_std_logic_vector(3043,AMPL_WIDTH),
conv_std_logic_vector(3046,AMPL_WIDTH),
conv_std_logic_vector(3049,AMPL_WIDTH),
conv_std_logic_vector(3052,AMPL_WIDTH),
conv_std_logic_vector(3055,AMPL_WIDTH),
conv_std_logic_vector(3059,AMPL_WIDTH),
conv_std_logic_vector(3062,AMPL_WIDTH),
conv_std_logic_vector(3065,AMPL_WIDTH),
conv_std_logic_vector(3068,AMPL_WIDTH),
conv_std_logic_vector(3071,AMPL_WIDTH),
conv_std_logic_vector(3074,AMPL_WIDTH),
conv_std_logic_vector(3077,AMPL_WIDTH),
conv_std_logic_vector(3080,AMPL_WIDTH),
conv_std_logic_vector(3084,AMPL_WIDTH),
conv_std_logic_vector(3087,AMPL_WIDTH),
conv_std_logic_vector(3090,AMPL_WIDTH),
conv_std_logic_vector(3093,AMPL_WIDTH),
conv_std_logic_vector(3096,AMPL_WIDTH),
conv_std_logic_vector(3099,AMPL_WIDTH),
conv_std_logic_vector(3102,AMPL_WIDTH),
conv_std_logic_vector(3105,AMPL_WIDTH),
conv_std_logic_vector(3109,AMPL_WIDTH),
conv_std_logic_vector(3112,AMPL_WIDTH),
conv_std_logic_vector(3115,AMPL_WIDTH),
conv_std_logic_vector(3118,AMPL_WIDTH),
conv_std_logic_vector(3121,AMPL_WIDTH),
conv_std_logic_vector(3124,AMPL_WIDTH),
conv_std_logic_vector(3127,AMPL_WIDTH),
conv_std_logic_vector(3130,AMPL_WIDTH),
conv_std_logic_vector(3134,AMPL_WIDTH),
conv_std_logic_vector(3137,AMPL_WIDTH),
conv_std_logic_vector(3140,AMPL_WIDTH),
conv_std_logic_vector(3143,AMPL_WIDTH),
conv_std_logic_vector(3146,AMPL_WIDTH),
conv_std_logic_vector(3149,AMPL_WIDTH),
conv_std_logic_vector(3152,AMPL_WIDTH),
conv_std_logic_vector(3155,AMPL_WIDTH),
conv_std_logic_vector(3159,AMPL_WIDTH),
conv_std_logic_vector(3162,AMPL_WIDTH),
conv_std_logic_vector(3165,AMPL_WIDTH),
conv_std_logic_vector(3168,AMPL_WIDTH),
conv_std_logic_vector(3171,AMPL_WIDTH),
conv_std_logic_vector(3174,AMPL_WIDTH),
conv_std_logic_vector(3177,AMPL_WIDTH),
conv_std_logic_vector(3180,AMPL_WIDTH),
conv_std_logic_vector(3184,AMPL_WIDTH),
conv_std_logic_vector(3187,AMPL_WIDTH),
conv_std_logic_vector(3190,AMPL_WIDTH),
conv_std_logic_vector(3193,AMPL_WIDTH),
conv_std_logic_vector(3196,AMPL_WIDTH),
conv_std_logic_vector(3199,AMPL_WIDTH),
conv_std_logic_vector(3202,AMPL_WIDTH),
conv_std_logic_vector(3205,AMPL_WIDTH),
conv_std_logic_vector(3209,AMPL_WIDTH),
conv_std_logic_vector(3212,AMPL_WIDTH),
conv_std_logic_vector(3215,AMPL_WIDTH),
conv_std_logic_vector(3218,AMPL_WIDTH),
conv_std_logic_vector(3221,AMPL_WIDTH),
conv_std_logic_vector(3224,AMPL_WIDTH),
conv_std_logic_vector(3227,AMPL_WIDTH),
conv_std_logic_vector(3230,AMPL_WIDTH),
conv_std_logic_vector(3234,AMPL_WIDTH),
conv_std_logic_vector(3237,AMPL_WIDTH),
conv_std_logic_vector(3240,AMPL_WIDTH),
conv_std_logic_vector(3243,AMPL_WIDTH),
conv_std_logic_vector(3246,AMPL_WIDTH),
conv_std_logic_vector(3249,AMPL_WIDTH),
conv_std_logic_vector(3252,AMPL_WIDTH),
conv_std_logic_vector(3255,AMPL_WIDTH),
conv_std_logic_vector(3259,AMPL_WIDTH),
conv_std_logic_vector(3262,AMPL_WIDTH),
conv_std_logic_vector(3265,AMPL_WIDTH),
conv_std_logic_vector(3268,AMPL_WIDTH),
conv_std_logic_vector(3271,AMPL_WIDTH),
conv_std_logic_vector(3274,AMPL_WIDTH),
conv_std_logic_vector(3277,AMPL_WIDTH),
conv_std_logic_vector(3281,AMPL_WIDTH),
conv_std_logic_vector(3284,AMPL_WIDTH),
conv_std_logic_vector(3287,AMPL_WIDTH),
conv_std_logic_vector(3290,AMPL_WIDTH),
conv_std_logic_vector(3293,AMPL_WIDTH),
conv_std_logic_vector(3296,AMPL_WIDTH),
conv_std_logic_vector(3299,AMPL_WIDTH),
conv_std_logic_vector(3302,AMPL_WIDTH),
conv_std_logic_vector(3306,AMPL_WIDTH),
conv_std_logic_vector(3309,AMPL_WIDTH),
conv_std_logic_vector(3312,AMPL_WIDTH),
conv_std_logic_vector(3315,AMPL_WIDTH),
conv_std_logic_vector(3318,AMPL_WIDTH),
conv_std_logic_vector(3321,AMPL_WIDTH),
conv_std_logic_vector(3324,AMPL_WIDTH),
conv_std_logic_vector(3327,AMPL_WIDTH),
conv_std_logic_vector(3331,AMPL_WIDTH),
conv_std_logic_vector(3334,AMPL_WIDTH),
conv_std_logic_vector(3337,AMPL_WIDTH),
conv_std_logic_vector(3340,AMPL_WIDTH),
conv_std_logic_vector(3343,AMPL_WIDTH),
conv_std_logic_vector(3346,AMPL_WIDTH),
conv_std_logic_vector(3349,AMPL_WIDTH),
conv_std_logic_vector(3352,AMPL_WIDTH),
conv_std_logic_vector(3356,AMPL_WIDTH),
conv_std_logic_vector(3359,AMPL_WIDTH),
conv_std_logic_vector(3362,AMPL_WIDTH),
conv_std_logic_vector(3365,AMPL_WIDTH),
conv_std_logic_vector(3368,AMPL_WIDTH),
conv_std_logic_vector(3371,AMPL_WIDTH),
conv_std_logic_vector(3374,AMPL_WIDTH),
conv_std_logic_vector(3377,AMPL_WIDTH),
conv_std_logic_vector(3381,AMPL_WIDTH),
conv_std_logic_vector(3384,AMPL_WIDTH),
conv_std_logic_vector(3387,AMPL_WIDTH),
conv_std_logic_vector(3390,AMPL_WIDTH),
conv_std_logic_vector(3393,AMPL_WIDTH),
conv_std_logic_vector(3396,AMPL_WIDTH),
conv_std_logic_vector(3399,AMPL_WIDTH),
conv_std_logic_vector(3402,AMPL_WIDTH),
conv_std_logic_vector(3406,AMPL_WIDTH),
conv_std_logic_vector(3409,AMPL_WIDTH),
conv_std_logic_vector(3412,AMPL_WIDTH),
conv_std_logic_vector(3415,AMPL_WIDTH),
conv_std_logic_vector(3418,AMPL_WIDTH),
conv_std_logic_vector(3421,AMPL_WIDTH),
conv_std_logic_vector(3424,AMPL_WIDTH),
conv_std_logic_vector(3427,AMPL_WIDTH),
conv_std_logic_vector(3430,AMPL_WIDTH),
conv_std_logic_vector(3434,AMPL_WIDTH),
conv_std_logic_vector(3437,AMPL_WIDTH),
conv_std_logic_vector(3440,AMPL_WIDTH),
conv_std_logic_vector(3443,AMPL_WIDTH),
conv_std_logic_vector(3446,AMPL_WIDTH),
conv_std_logic_vector(3449,AMPL_WIDTH),
conv_std_logic_vector(3452,AMPL_WIDTH),
conv_std_logic_vector(3455,AMPL_WIDTH),
conv_std_logic_vector(3459,AMPL_WIDTH),
conv_std_logic_vector(3462,AMPL_WIDTH),
conv_std_logic_vector(3465,AMPL_WIDTH),
conv_std_logic_vector(3468,AMPL_WIDTH),
conv_std_logic_vector(3471,AMPL_WIDTH),
conv_std_logic_vector(3474,AMPL_WIDTH),
conv_std_logic_vector(3477,AMPL_WIDTH),
conv_std_logic_vector(3480,AMPL_WIDTH),
conv_std_logic_vector(3484,AMPL_WIDTH),
conv_std_logic_vector(3487,AMPL_WIDTH),
conv_std_logic_vector(3490,AMPL_WIDTH),
conv_std_logic_vector(3493,AMPL_WIDTH),
conv_std_logic_vector(3496,AMPL_WIDTH),
conv_std_logic_vector(3499,AMPL_WIDTH),
conv_std_logic_vector(3502,AMPL_WIDTH),
conv_std_logic_vector(3505,AMPL_WIDTH),
conv_std_logic_vector(3509,AMPL_WIDTH),
conv_std_logic_vector(3512,AMPL_WIDTH),
conv_std_logic_vector(3515,AMPL_WIDTH),
conv_std_logic_vector(3518,AMPL_WIDTH),
conv_std_logic_vector(3521,AMPL_WIDTH),
conv_std_logic_vector(3524,AMPL_WIDTH),
conv_std_logic_vector(3527,AMPL_WIDTH),
conv_std_logic_vector(3530,AMPL_WIDTH),
conv_std_logic_vector(3534,AMPL_WIDTH),
conv_std_logic_vector(3537,AMPL_WIDTH),
conv_std_logic_vector(3540,AMPL_WIDTH),
conv_std_logic_vector(3543,AMPL_WIDTH),
conv_std_logic_vector(3546,AMPL_WIDTH),
conv_std_logic_vector(3549,AMPL_WIDTH),
conv_std_logic_vector(3552,AMPL_WIDTH),
conv_std_logic_vector(3555,AMPL_WIDTH),
conv_std_logic_vector(3559,AMPL_WIDTH),
conv_std_logic_vector(3562,AMPL_WIDTH),
conv_std_logic_vector(3565,AMPL_WIDTH),
conv_std_logic_vector(3568,AMPL_WIDTH),
conv_std_logic_vector(3571,AMPL_WIDTH),
conv_std_logic_vector(3574,AMPL_WIDTH),
conv_std_logic_vector(3577,AMPL_WIDTH),
conv_std_logic_vector(3580,AMPL_WIDTH),
conv_std_logic_vector(3584,AMPL_WIDTH),
conv_std_logic_vector(3587,AMPL_WIDTH),
conv_std_logic_vector(3590,AMPL_WIDTH),
conv_std_logic_vector(3593,AMPL_WIDTH),
conv_std_logic_vector(3596,AMPL_WIDTH),
conv_std_logic_vector(3599,AMPL_WIDTH),
conv_std_logic_vector(3602,AMPL_WIDTH),
conv_std_logic_vector(3605,AMPL_WIDTH),
conv_std_logic_vector(3609,AMPL_WIDTH),
conv_std_logic_vector(3612,AMPL_WIDTH),
conv_std_logic_vector(3615,AMPL_WIDTH),
conv_std_logic_vector(3618,AMPL_WIDTH),
conv_std_logic_vector(3621,AMPL_WIDTH),
conv_std_logic_vector(3624,AMPL_WIDTH),
conv_std_logic_vector(3627,AMPL_WIDTH),
conv_std_logic_vector(3630,AMPL_WIDTH),
conv_std_logic_vector(3634,AMPL_WIDTH),
conv_std_logic_vector(3637,AMPL_WIDTH),
conv_std_logic_vector(3640,AMPL_WIDTH),
conv_std_logic_vector(3643,AMPL_WIDTH),
conv_std_logic_vector(3646,AMPL_WIDTH),
conv_std_logic_vector(3649,AMPL_WIDTH),
conv_std_logic_vector(3652,AMPL_WIDTH),
conv_std_logic_vector(3655,AMPL_WIDTH),
conv_std_logic_vector(3658,AMPL_WIDTH),
conv_std_logic_vector(3662,AMPL_WIDTH),
conv_std_logic_vector(3665,AMPL_WIDTH),
conv_std_logic_vector(3668,AMPL_WIDTH),
conv_std_logic_vector(3671,AMPL_WIDTH),
conv_std_logic_vector(3674,AMPL_WIDTH),
conv_std_logic_vector(3677,AMPL_WIDTH),
conv_std_logic_vector(3680,AMPL_WIDTH),
conv_std_logic_vector(3683,AMPL_WIDTH),
conv_std_logic_vector(3687,AMPL_WIDTH),
conv_std_logic_vector(3690,AMPL_WIDTH),
conv_std_logic_vector(3693,AMPL_WIDTH),
conv_std_logic_vector(3696,AMPL_WIDTH),
conv_std_logic_vector(3699,AMPL_WIDTH),
conv_std_logic_vector(3702,AMPL_WIDTH),
conv_std_logic_vector(3705,AMPL_WIDTH),
conv_std_logic_vector(3708,AMPL_WIDTH),
conv_std_logic_vector(3712,AMPL_WIDTH),
conv_std_logic_vector(3715,AMPL_WIDTH),
conv_std_logic_vector(3718,AMPL_WIDTH),
conv_std_logic_vector(3721,AMPL_WIDTH),
conv_std_logic_vector(3724,AMPL_WIDTH),
conv_std_logic_vector(3727,AMPL_WIDTH),
conv_std_logic_vector(3730,AMPL_WIDTH),
conv_std_logic_vector(3733,AMPL_WIDTH),
conv_std_logic_vector(3737,AMPL_WIDTH),
conv_std_logic_vector(3740,AMPL_WIDTH),
conv_std_logic_vector(3743,AMPL_WIDTH),
conv_std_logic_vector(3746,AMPL_WIDTH),
conv_std_logic_vector(3749,AMPL_WIDTH),
conv_std_logic_vector(3752,AMPL_WIDTH),
conv_std_logic_vector(3755,AMPL_WIDTH),
conv_std_logic_vector(3758,AMPL_WIDTH),
conv_std_logic_vector(3761,AMPL_WIDTH),
conv_std_logic_vector(3765,AMPL_WIDTH),
conv_std_logic_vector(3768,AMPL_WIDTH),
conv_std_logic_vector(3771,AMPL_WIDTH),
conv_std_logic_vector(3774,AMPL_WIDTH),
conv_std_logic_vector(3777,AMPL_WIDTH),
conv_std_logic_vector(3780,AMPL_WIDTH),
conv_std_logic_vector(3783,AMPL_WIDTH),
conv_std_logic_vector(3786,AMPL_WIDTH),
conv_std_logic_vector(3790,AMPL_WIDTH),
conv_std_logic_vector(3793,AMPL_WIDTH),
conv_std_logic_vector(3796,AMPL_WIDTH),
conv_std_logic_vector(3799,AMPL_WIDTH),
conv_std_logic_vector(3802,AMPL_WIDTH),
conv_std_logic_vector(3805,AMPL_WIDTH),
conv_std_logic_vector(3808,AMPL_WIDTH),
conv_std_logic_vector(3811,AMPL_WIDTH),
conv_std_logic_vector(3815,AMPL_WIDTH),
conv_std_logic_vector(3818,AMPL_WIDTH),
conv_std_logic_vector(3821,AMPL_WIDTH),
conv_std_logic_vector(3824,AMPL_WIDTH),
conv_std_logic_vector(3827,AMPL_WIDTH),
conv_std_logic_vector(3830,AMPL_WIDTH),
conv_std_logic_vector(3833,AMPL_WIDTH),
conv_std_logic_vector(3836,AMPL_WIDTH),
conv_std_logic_vector(3839,AMPL_WIDTH),
conv_std_logic_vector(3843,AMPL_WIDTH),
conv_std_logic_vector(3846,AMPL_WIDTH),
conv_std_logic_vector(3849,AMPL_WIDTH),
conv_std_logic_vector(3852,AMPL_WIDTH),
conv_std_logic_vector(3855,AMPL_WIDTH),
conv_std_logic_vector(3858,AMPL_WIDTH),
conv_std_logic_vector(3861,AMPL_WIDTH),
conv_std_logic_vector(3864,AMPL_WIDTH),
conv_std_logic_vector(3868,AMPL_WIDTH),
conv_std_logic_vector(3871,AMPL_WIDTH),
conv_std_logic_vector(3874,AMPL_WIDTH),
conv_std_logic_vector(3877,AMPL_WIDTH),
conv_std_logic_vector(3880,AMPL_WIDTH),
conv_std_logic_vector(3883,AMPL_WIDTH),
conv_std_logic_vector(3886,AMPL_WIDTH),
conv_std_logic_vector(3889,AMPL_WIDTH),
conv_std_logic_vector(3893,AMPL_WIDTH),
conv_std_logic_vector(3896,AMPL_WIDTH),
conv_std_logic_vector(3899,AMPL_WIDTH),
conv_std_logic_vector(3902,AMPL_WIDTH),
conv_std_logic_vector(3905,AMPL_WIDTH),
conv_std_logic_vector(3908,AMPL_WIDTH),
conv_std_logic_vector(3911,AMPL_WIDTH),
conv_std_logic_vector(3914,AMPL_WIDTH),
conv_std_logic_vector(3917,AMPL_WIDTH),
conv_std_logic_vector(3921,AMPL_WIDTH),
conv_std_logic_vector(3924,AMPL_WIDTH),
conv_std_logic_vector(3927,AMPL_WIDTH),
conv_std_logic_vector(3930,AMPL_WIDTH),
conv_std_logic_vector(3933,AMPL_WIDTH),
conv_std_logic_vector(3936,AMPL_WIDTH),
conv_std_logic_vector(3939,AMPL_WIDTH),
conv_std_logic_vector(3942,AMPL_WIDTH),
conv_std_logic_vector(3946,AMPL_WIDTH),
conv_std_logic_vector(3949,AMPL_WIDTH),
conv_std_logic_vector(3952,AMPL_WIDTH),
conv_std_logic_vector(3955,AMPL_WIDTH),
conv_std_logic_vector(3958,AMPL_WIDTH),
conv_std_logic_vector(3961,AMPL_WIDTH),
conv_std_logic_vector(3964,AMPL_WIDTH),
conv_std_logic_vector(3967,AMPL_WIDTH),
conv_std_logic_vector(3970,AMPL_WIDTH),
conv_std_logic_vector(3974,AMPL_WIDTH),
conv_std_logic_vector(3977,AMPL_WIDTH),
conv_std_logic_vector(3980,AMPL_WIDTH),
conv_std_logic_vector(3983,AMPL_WIDTH),
conv_std_logic_vector(3986,AMPL_WIDTH),
conv_std_logic_vector(3989,AMPL_WIDTH),
conv_std_logic_vector(3992,AMPL_WIDTH),
conv_std_logic_vector(3995,AMPL_WIDTH),
conv_std_logic_vector(3999,AMPL_WIDTH),
conv_std_logic_vector(4002,AMPL_WIDTH),
conv_std_logic_vector(4005,AMPL_WIDTH),
conv_std_logic_vector(4008,AMPL_WIDTH),
conv_std_logic_vector(4011,AMPL_WIDTH),
conv_std_logic_vector(4014,AMPL_WIDTH),
conv_std_logic_vector(4017,AMPL_WIDTH),
conv_std_logic_vector(4020,AMPL_WIDTH),
conv_std_logic_vector(4024,AMPL_WIDTH),
conv_std_logic_vector(4027,AMPL_WIDTH),
conv_std_logic_vector(4030,AMPL_WIDTH),
conv_std_logic_vector(4033,AMPL_WIDTH),
conv_std_logic_vector(4036,AMPL_WIDTH),
conv_std_logic_vector(4039,AMPL_WIDTH),
conv_std_logic_vector(4042,AMPL_WIDTH),
conv_std_logic_vector(4045,AMPL_WIDTH),
conv_std_logic_vector(4048,AMPL_WIDTH),
conv_std_logic_vector(4052,AMPL_WIDTH),
conv_std_logic_vector(4055,AMPL_WIDTH),
conv_std_logic_vector(4058,AMPL_WIDTH),
conv_std_logic_vector(4061,AMPL_WIDTH),
conv_std_logic_vector(4064,AMPL_WIDTH),
conv_std_logic_vector(4067,AMPL_WIDTH),
conv_std_logic_vector(4070,AMPL_WIDTH),
conv_std_logic_vector(4073,AMPL_WIDTH),
conv_std_logic_vector(4076,AMPL_WIDTH),
conv_std_logic_vector(4080,AMPL_WIDTH),
conv_std_logic_vector(4083,AMPL_WIDTH),
conv_std_logic_vector(4086,AMPL_WIDTH),
conv_std_logic_vector(4089,AMPL_WIDTH),
conv_std_logic_vector(4092,AMPL_WIDTH),
conv_std_logic_vector(4095,AMPL_WIDTH),
conv_std_logic_vector(4098,AMPL_WIDTH),
conv_std_logic_vector(4101,AMPL_WIDTH),
conv_std_logic_vector(4105,AMPL_WIDTH),
conv_std_logic_vector(4108,AMPL_WIDTH),
conv_std_logic_vector(4111,AMPL_WIDTH),
conv_std_logic_vector(4114,AMPL_WIDTH),
conv_std_logic_vector(4117,AMPL_WIDTH),
conv_std_logic_vector(4120,AMPL_WIDTH),
conv_std_logic_vector(4123,AMPL_WIDTH),
conv_std_logic_vector(4126,AMPL_WIDTH),
conv_std_logic_vector(4129,AMPL_WIDTH),
conv_std_logic_vector(4133,AMPL_WIDTH),
conv_std_logic_vector(4136,AMPL_WIDTH),
conv_std_logic_vector(4139,AMPL_WIDTH),
conv_std_logic_vector(4142,AMPL_WIDTH),
conv_std_logic_vector(4145,AMPL_WIDTH),
conv_std_logic_vector(4148,AMPL_WIDTH),
conv_std_logic_vector(4151,AMPL_WIDTH),
conv_std_logic_vector(4154,AMPL_WIDTH),
conv_std_logic_vector(4158,AMPL_WIDTH),
conv_std_logic_vector(4161,AMPL_WIDTH),
conv_std_logic_vector(4164,AMPL_WIDTH),
conv_std_logic_vector(4167,AMPL_WIDTH),
conv_std_logic_vector(4170,AMPL_WIDTH),
conv_std_logic_vector(4173,AMPL_WIDTH),
conv_std_logic_vector(4176,AMPL_WIDTH),
conv_std_logic_vector(4179,AMPL_WIDTH),
conv_std_logic_vector(4182,AMPL_WIDTH),
conv_std_logic_vector(4186,AMPL_WIDTH),
conv_std_logic_vector(4189,AMPL_WIDTH),
conv_std_logic_vector(4192,AMPL_WIDTH),
conv_std_logic_vector(4195,AMPL_WIDTH),
conv_std_logic_vector(4198,AMPL_WIDTH),
conv_std_logic_vector(4201,AMPL_WIDTH),
conv_std_logic_vector(4204,AMPL_WIDTH),
conv_std_logic_vector(4207,AMPL_WIDTH),
conv_std_logic_vector(4210,AMPL_WIDTH),
conv_std_logic_vector(4214,AMPL_WIDTH),
conv_std_logic_vector(4217,AMPL_WIDTH),
conv_std_logic_vector(4220,AMPL_WIDTH),
conv_std_logic_vector(4223,AMPL_WIDTH),
conv_std_logic_vector(4226,AMPL_WIDTH),
conv_std_logic_vector(4229,AMPL_WIDTH),
conv_std_logic_vector(4232,AMPL_WIDTH),
conv_std_logic_vector(4235,AMPL_WIDTH),
conv_std_logic_vector(4239,AMPL_WIDTH),
conv_std_logic_vector(4242,AMPL_WIDTH),
conv_std_logic_vector(4245,AMPL_WIDTH),
conv_std_logic_vector(4248,AMPL_WIDTH),
conv_std_logic_vector(4251,AMPL_WIDTH),
conv_std_logic_vector(4254,AMPL_WIDTH),
conv_std_logic_vector(4257,AMPL_WIDTH),
conv_std_logic_vector(4260,AMPL_WIDTH),
conv_std_logic_vector(4263,AMPL_WIDTH),
conv_std_logic_vector(4267,AMPL_WIDTH),
conv_std_logic_vector(4270,AMPL_WIDTH),
conv_std_logic_vector(4273,AMPL_WIDTH),
conv_std_logic_vector(4276,AMPL_WIDTH),
conv_std_logic_vector(4279,AMPL_WIDTH),
conv_std_logic_vector(4282,AMPL_WIDTH),
conv_std_logic_vector(4285,AMPL_WIDTH),
conv_std_logic_vector(4288,AMPL_WIDTH),
conv_std_logic_vector(4291,AMPL_WIDTH),
conv_std_logic_vector(4295,AMPL_WIDTH),
conv_std_logic_vector(4298,AMPL_WIDTH),
conv_std_logic_vector(4301,AMPL_WIDTH),
conv_std_logic_vector(4304,AMPL_WIDTH),
conv_std_logic_vector(4307,AMPL_WIDTH),
conv_std_logic_vector(4310,AMPL_WIDTH),
conv_std_logic_vector(4313,AMPL_WIDTH),
conv_std_logic_vector(4316,AMPL_WIDTH),
conv_std_logic_vector(4320,AMPL_WIDTH),
conv_std_logic_vector(4323,AMPL_WIDTH),
conv_std_logic_vector(4326,AMPL_WIDTH),
conv_std_logic_vector(4329,AMPL_WIDTH),
conv_std_logic_vector(4332,AMPL_WIDTH),
conv_std_logic_vector(4335,AMPL_WIDTH),
conv_std_logic_vector(4338,AMPL_WIDTH),
conv_std_logic_vector(4341,AMPL_WIDTH),
conv_std_logic_vector(4344,AMPL_WIDTH),
conv_std_logic_vector(4348,AMPL_WIDTH),
conv_std_logic_vector(4351,AMPL_WIDTH),
conv_std_logic_vector(4354,AMPL_WIDTH),
conv_std_logic_vector(4357,AMPL_WIDTH),
conv_std_logic_vector(4360,AMPL_WIDTH),
conv_std_logic_vector(4363,AMPL_WIDTH),
conv_std_logic_vector(4366,AMPL_WIDTH),
conv_std_logic_vector(4369,AMPL_WIDTH),
conv_std_logic_vector(4372,AMPL_WIDTH),
conv_std_logic_vector(4376,AMPL_WIDTH),
conv_std_logic_vector(4379,AMPL_WIDTH),
conv_std_logic_vector(4382,AMPL_WIDTH),
conv_std_logic_vector(4385,AMPL_WIDTH),
conv_std_logic_vector(4388,AMPL_WIDTH),
conv_std_logic_vector(4391,AMPL_WIDTH),
conv_std_logic_vector(4394,AMPL_WIDTH),
conv_std_logic_vector(4397,AMPL_WIDTH),
conv_std_logic_vector(4400,AMPL_WIDTH),
conv_std_logic_vector(4404,AMPL_WIDTH),
conv_std_logic_vector(4407,AMPL_WIDTH),
conv_std_logic_vector(4410,AMPL_WIDTH),
conv_std_logic_vector(4413,AMPL_WIDTH),
conv_std_logic_vector(4416,AMPL_WIDTH),
conv_std_logic_vector(4419,AMPL_WIDTH),
conv_std_logic_vector(4422,AMPL_WIDTH),
conv_std_logic_vector(4425,AMPL_WIDTH),
conv_std_logic_vector(4428,AMPL_WIDTH),
conv_std_logic_vector(4432,AMPL_WIDTH),
conv_std_logic_vector(4435,AMPL_WIDTH),
conv_std_logic_vector(4438,AMPL_WIDTH),
conv_std_logic_vector(4441,AMPL_WIDTH),
conv_std_logic_vector(4444,AMPL_WIDTH),
conv_std_logic_vector(4447,AMPL_WIDTH),
conv_std_logic_vector(4450,AMPL_WIDTH),
conv_std_logic_vector(4453,AMPL_WIDTH),
conv_std_logic_vector(4456,AMPL_WIDTH),
conv_std_logic_vector(4460,AMPL_WIDTH),
conv_std_logic_vector(4463,AMPL_WIDTH),
conv_std_logic_vector(4466,AMPL_WIDTH),
conv_std_logic_vector(4469,AMPL_WIDTH),
conv_std_logic_vector(4472,AMPL_WIDTH),
conv_std_logic_vector(4475,AMPL_WIDTH),
conv_std_logic_vector(4478,AMPL_WIDTH),
conv_std_logic_vector(4481,AMPL_WIDTH),
conv_std_logic_vector(4485,AMPL_WIDTH),
conv_std_logic_vector(4488,AMPL_WIDTH),
conv_std_logic_vector(4491,AMPL_WIDTH),
conv_std_logic_vector(4494,AMPL_WIDTH),
conv_std_logic_vector(4497,AMPL_WIDTH),
conv_std_logic_vector(4500,AMPL_WIDTH),
conv_std_logic_vector(4503,AMPL_WIDTH),
conv_std_logic_vector(4506,AMPL_WIDTH),
conv_std_logic_vector(4509,AMPL_WIDTH),
conv_std_logic_vector(4513,AMPL_WIDTH),
conv_std_logic_vector(4516,AMPL_WIDTH),
conv_std_logic_vector(4519,AMPL_WIDTH),
conv_std_logic_vector(4522,AMPL_WIDTH),
conv_std_logic_vector(4525,AMPL_WIDTH),
conv_std_logic_vector(4528,AMPL_WIDTH),
conv_std_logic_vector(4531,AMPL_WIDTH),
conv_std_logic_vector(4534,AMPL_WIDTH),
conv_std_logic_vector(4537,AMPL_WIDTH),
conv_std_logic_vector(4541,AMPL_WIDTH),
conv_std_logic_vector(4544,AMPL_WIDTH),
conv_std_logic_vector(4547,AMPL_WIDTH),
conv_std_logic_vector(4550,AMPL_WIDTH),
conv_std_logic_vector(4553,AMPL_WIDTH),
conv_std_logic_vector(4556,AMPL_WIDTH),
conv_std_logic_vector(4559,AMPL_WIDTH),
conv_std_logic_vector(4562,AMPL_WIDTH),
conv_std_logic_vector(4565,AMPL_WIDTH),
conv_std_logic_vector(4569,AMPL_WIDTH),
conv_std_logic_vector(4572,AMPL_WIDTH),
conv_std_logic_vector(4575,AMPL_WIDTH),
conv_std_logic_vector(4578,AMPL_WIDTH),
conv_std_logic_vector(4581,AMPL_WIDTH),
conv_std_logic_vector(4584,AMPL_WIDTH),
conv_std_logic_vector(4587,AMPL_WIDTH),
conv_std_logic_vector(4590,AMPL_WIDTH),
conv_std_logic_vector(4593,AMPL_WIDTH),
conv_std_logic_vector(4597,AMPL_WIDTH),
conv_std_logic_vector(4600,AMPL_WIDTH),
conv_std_logic_vector(4603,AMPL_WIDTH),
conv_std_logic_vector(4606,AMPL_WIDTH),
conv_std_logic_vector(4609,AMPL_WIDTH),
conv_std_logic_vector(4612,AMPL_WIDTH),
conv_std_logic_vector(4615,AMPL_WIDTH),
conv_std_logic_vector(4618,AMPL_WIDTH),
conv_std_logic_vector(4621,AMPL_WIDTH),
conv_std_logic_vector(4624,AMPL_WIDTH),
conv_std_logic_vector(4628,AMPL_WIDTH),
conv_std_logic_vector(4631,AMPL_WIDTH),
conv_std_logic_vector(4634,AMPL_WIDTH),
conv_std_logic_vector(4637,AMPL_WIDTH),
conv_std_logic_vector(4640,AMPL_WIDTH),
conv_std_logic_vector(4643,AMPL_WIDTH),
conv_std_logic_vector(4646,AMPL_WIDTH),
conv_std_logic_vector(4649,AMPL_WIDTH),
conv_std_logic_vector(4652,AMPL_WIDTH),
conv_std_logic_vector(4656,AMPL_WIDTH),
conv_std_logic_vector(4659,AMPL_WIDTH),
conv_std_logic_vector(4662,AMPL_WIDTH),
conv_std_logic_vector(4665,AMPL_WIDTH),
conv_std_logic_vector(4668,AMPL_WIDTH),
conv_std_logic_vector(4671,AMPL_WIDTH),
conv_std_logic_vector(4674,AMPL_WIDTH),
conv_std_logic_vector(4677,AMPL_WIDTH),
conv_std_logic_vector(4680,AMPL_WIDTH),
conv_std_logic_vector(4684,AMPL_WIDTH),
conv_std_logic_vector(4687,AMPL_WIDTH),
conv_std_logic_vector(4690,AMPL_WIDTH),
conv_std_logic_vector(4693,AMPL_WIDTH),
conv_std_logic_vector(4696,AMPL_WIDTH),
conv_std_logic_vector(4699,AMPL_WIDTH),
conv_std_logic_vector(4702,AMPL_WIDTH),
conv_std_logic_vector(4705,AMPL_WIDTH),
conv_std_logic_vector(4708,AMPL_WIDTH),
conv_std_logic_vector(4712,AMPL_WIDTH),
conv_std_logic_vector(4715,AMPL_WIDTH),
conv_std_logic_vector(4718,AMPL_WIDTH),
conv_std_logic_vector(4721,AMPL_WIDTH),
conv_std_logic_vector(4724,AMPL_WIDTH),
conv_std_logic_vector(4727,AMPL_WIDTH),
conv_std_logic_vector(4730,AMPL_WIDTH),
conv_std_logic_vector(4733,AMPL_WIDTH),
conv_std_logic_vector(4736,AMPL_WIDTH),
conv_std_logic_vector(4740,AMPL_WIDTH),
conv_std_logic_vector(4743,AMPL_WIDTH),
conv_std_logic_vector(4746,AMPL_WIDTH),
conv_std_logic_vector(4749,AMPL_WIDTH),
conv_std_logic_vector(4752,AMPL_WIDTH),
conv_std_logic_vector(4755,AMPL_WIDTH),
conv_std_logic_vector(4758,AMPL_WIDTH),
conv_std_logic_vector(4761,AMPL_WIDTH),
conv_std_logic_vector(4764,AMPL_WIDTH),
conv_std_logic_vector(4768,AMPL_WIDTH),
conv_std_logic_vector(4771,AMPL_WIDTH),
conv_std_logic_vector(4774,AMPL_WIDTH),
conv_std_logic_vector(4777,AMPL_WIDTH),
conv_std_logic_vector(4780,AMPL_WIDTH),
conv_std_logic_vector(4783,AMPL_WIDTH),
conv_std_logic_vector(4786,AMPL_WIDTH),
conv_std_logic_vector(4789,AMPL_WIDTH),
conv_std_logic_vector(4792,AMPL_WIDTH),
conv_std_logic_vector(4795,AMPL_WIDTH),
conv_std_logic_vector(4799,AMPL_WIDTH),
conv_std_logic_vector(4802,AMPL_WIDTH),
conv_std_logic_vector(4805,AMPL_WIDTH),
conv_std_logic_vector(4808,AMPL_WIDTH),
conv_std_logic_vector(4811,AMPL_WIDTH),
conv_std_logic_vector(4814,AMPL_WIDTH),
conv_std_logic_vector(4817,AMPL_WIDTH),
conv_std_logic_vector(4820,AMPL_WIDTH),
conv_std_logic_vector(4823,AMPL_WIDTH),
conv_std_logic_vector(4827,AMPL_WIDTH),
conv_std_logic_vector(4830,AMPL_WIDTH),
conv_std_logic_vector(4833,AMPL_WIDTH),
conv_std_logic_vector(4836,AMPL_WIDTH),
conv_std_logic_vector(4839,AMPL_WIDTH),
conv_std_logic_vector(4842,AMPL_WIDTH),
conv_std_logic_vector(4845,AMPL_WIDTH),
conv_std_logic_vector(4848,AMPL_WIDTH),
conv_std_logic_vector(4851,AMPL_WIDTH),
conv_std_logic_vector(4855,AMPL_WIDTH),
conv_std_logic_vector(4858,AMPL_WIDTH),
conv_std_logic_vector(4861,AMPL_WIDTH),
conv_std_logic_vector(4864,AMPL_WIDTH),
conv_std_logic_vector(4867,AMPL_WIDTH),
conv_std_logic_vector(4870,AMPL_WIDTH),
conv_std_logic_vector(4873,AMPL_WIDTH),
conv_std_logic_vector(4876,AMPL_WIDTH),
conv_std_logic_vector(4879,AMPL_WIDTH),
conv_std_logic_vector(4882,AMPL_WIDTH),
conv_std_logic_vector(4886,AMPL_WIDTH),
conv_std_logic_vector(4889,AMPL_WIDTH),
conv_std_logic_vector(4892,AMPL_WIDTH),
conv_std_logic_vector(4895,AMPL_WIDTH),
conv_std_logic_vector(4898,AMPL_WIDTH),
conv_std_logic_vector(4901,AMPL_WIDTH),
conv_std_logic_vector(4904,AMPL_WIDTH),
conv_std_logic_vector(4907,AMPL_WIDTH),
conv_std_logic_vector(4910,AMPL_WIDTH),
conv_std_logic_vector(4914,AMPL_WIDTH),
conv_std_logic_vector(4917,AMPL_WIDTH),
conv_std_logic_vector(4920,AMPL_WIDTH),
conv_std_logic_vector(4923,AMPL_WIDTH),
conv_std_logic_vector(4926,AMPL_WIDTH),
conv_std_logic_vector(4929,AMPL_WIDTH),
conv_std_logic_vector(4932,AMPL_WIDTH),
conv_std_logic_vector(4935,AMPL_WIDTH),
conv_std_logic_vector(4938,AMPL_WIDTH),
conv_std_logic_vector(4941,AMPL_WIDTH),
conv_std_logic_vector(4945,AMPL_WIDTH),
conv_std_logic_vector(4948,AMPL_WIDTH),
conv_std_logic_vector(4951,AMPL_WIDTH),
conv_std_logic_vector(4954,AMPL_WIDTH),
conv_std_logic_vector(4957,AMPL_WIDTH),
conv_std_logic_vector(4960,AMPL_WIDTH),
conv_std_logic_vector(4963,AMPL_WIDTH),
conv_std_logic_vector(4966,AMPL_WIDTH),
conv_std_logic_vector(4969,AMPL_WIDTH),
conv_std_logic_vector(4973,AMPL_WIDTH),
conv_std_logic_vector(4976,AMPL_WIDTH),
conv_std_logic_vector(4979,AMPL_WIDTH),
conv_std_logic_vector(4982,AMPL_WIDTH),
conv_std_logic_vector(4985,AMPL_WIDTH),
conv_std_logic_vector(4988,AMPL_WIDTH),
conv_std_logic_vector(4991,AMPL_WIDTH),
conv_std_logic_vector(4994,AMPL_WIDTH),
conv_std_logic_vector(4997,AMPL_WIDTH),
conv_std_logic_vector(5000,AMPL_WIDTH),
conv_std_logic_vector(5004,AMPL_WIDTH),
conv_std_logic_vector(5007,AMPL_WIDTH),
conv_std_logic_vector(5010,AMPL_WIDTH),
conv_std_logic_vector(5013,AMPL_WIDTH),
conv_std_logic_vector(5016,AMPL_WIDTH),
conv_std_logic_vector(5019,AMPL_WIDTH),
conv_std_logic_vector(5022,AMPL_WIDTH),
conv_std_logic_vector(5025,AMPL_WIDTH),
conv_std_logic_vector(5028,AMPL_WIDTH),
conv_std_logic_vector(5032,AMPL_WIDTH),
conv_std_logic_vector(5035,AMPL_WIDTH),
conv_std_logic_vector(5038,AMPL_WIDTH),
conv_std_logic_vector(5041,AMPL_WIDTH),
conv_std_logic_vector(5044,AMPL_WIDTH),
conv_std_logic_vector(5047,AMPL_WIDTH),
conv_std_logic_vector(5050,AMPL_WIDTH),
conv_std_logic_vector(5053,AMPL_WIDTH),
conv_std_logic_vector(5056,AMPL_WIDTH),
conv_std_logic_vector(5059,AMPL_WIDTH),
conv_std_logic_vector(5063,AMPL_WIDTH),
conv_std_logic_vector(5066,AMPL_WIDTH),
conv_std_logic_vector(5069,AMPL_WIDTH),
conv_std_logic_vector(5072,AMPL_WIDTH),
conv_std_logic_vector(5075,AMPL_WIDTH),
conv_std_logic_vector(5078,AMPL_WIDTH),
conv_std_logic_vector(5081,AMPL_WIDTH),
conv_std_logic_vector(5084,AMPL_WIDTH),
conv_std_logic_vector(5087,AMPL_WIDTH),
conv_std_logic_vector(5091,AMPL_WIDTH),
conv_std_logic_vector(5094,AMPL_WIDTH),
conv_std_logic_vector(5097,AMPL_WIDTH),
conv_std_logic_vector(5100,AMPL_WIDTH),
conv_std_logic_vector(5103,AMPL_WIDTH),
conv_std_logic_vector(5106,AMPL_WIDTH),
conv_std_logic_vector(5109,AMPL_WIDTH),
conv_std_logic_vector(5112,AMPL_WIDTH),
conv_std_logic_vector(5115,AMPL_WIDTH),
conv_std_logic_vector(5118,AMPL_WIDTH),
conv_std_logic_vector(5122,AMPL_WIDTH),
conv_std_logic_vector(5125,AMPL_WIDTH),
conv_std_logic_vector(5128,AMPL_WIDTH),
conv_std_logic_vector(5131,AMPL_WIDTH),
conv_std_logic_vector(5134,AMPL_WIDTH),
conv_std_logic_vector(5137,AMPL_WIDTH),
conv_std_logic_vector(5140,AMPL_WIDTH),
conv_std_logic_vector(5143,AMPL_WIDTH),
conv_std_logic_vector(5146,AMPL_WIDTH),
conv_std_logic_vector(5149,AMPL_WIDTH),
conv_std_logic_vector(5153,AMPL_WIDTH),
conv_std_logic_vector(5156,AMPL_WIDTH),
conv_std_logic_vector(5159,AMPL_WIDTH),
conv_std_logic_vector(5162,AMPL_WIDTH),
conv_std_logic_vector(5165,AMPL_WIDTH),
conv_std_logic_vector(5168,AMPL_WIDTH),
conv_std_logic_vector(5171,AMPL_WIDTH),
conv_std_logic_vector(5174,AMPL_WIDTH),
conv_std_logic_vector(5177,AMPL_WIDTH),
conv_std_logic_vector(5180,AMPL_WIDTH),
conv_std_logic_vector(5184,AMPL_WIDTH),
conv_std_logic_vector(5187,AMPL_WIDTH),
conv_std_logic_vector(5190,AMPL_WIDTH),
conv_std_logic_vector(5193,AMPL_WIDTH),
conv_std_logic_vector(5196,AMPL_WIDTH),
conv_std_logic_vector(5199,AMPL_WIDTH),
conv_std_logic_vector(5202,AMPL_WIDTH),
conv_std_logic_vector(5205,AMPL_WIDTH),
conv_std_logic_vector(5208,AMPL_WIDTH),
conv_std_logic_vector(5212,AMPL_WIDTH),
conv_std_logic_vector(5215,AMPL_WIDTH),
conv_std_logic_vector(5218,AMPL_WIDTH),
conv_std_logic_vector(5221,AMPL_WIDTH),
conv_std_logic_vector(5224,AMPL_WIDTH),
conv_std_logic_vector(5227,AMPL_WIDTH),
conv_std_logic_vector(5230,AMPL_WIDTH),
conv_std_logic_vector(5233,AMPL_WIDTH),
conv_std_logic_vector(5236,AMPL_WIDTH),
conv_std_logic_vector(5239,AMPL_WIDTH),
conv_std_logic_vector(5243,AMPL_WIDTH),
conv_std_logic_vector(5246,AMPL_WIDTH),
conv_std_logic_vector(5249,AMPL_WIDTH),
conv_std_logic_vector(5252,AMPL_WIDTH),
conv_std_logic_vector(5255,AMPL_WIDTH),
conv_std_logic_vector(5258,AMPL_WIDTH),
conv_std_logic_vector(5261,AMPL_WIDTH),
conv_std_logic_vector(5264,AMPL_WIDTH),
conv_std_logic_vector(5267,AMPL_WIDTH),
conv_std_logic_vector(5270,AMPL_WIDTH),
conv_std_logic_vector(5274,AMPL_WIDTH),
conv_std_logic_vector(5277,AMPL_WIDTH),
conv_std_logic_vector(5280,AMPL_WIDTH),
conv_std_logic_vector(5283,AMPL_WIDTH),
conv_std_logic_vector(5286,AMPL_WIDTH),
conv_std_logic_vector(5289,AMPL_WIDTH),
conv_std_logic_vector(5292,AMPL_WIDTH),
conv_std_logic_vector(5295,AMPL_WIDTH),
conv_std_logic_vector(5298,AMPL_WIDTH),
conv_std_logic_vector(5301,AMPL_WIDTH),
conv_std_logic_vector(5305,AMPL_WIDTH),
conv_std_logic_vector(5308,AMPL_WIDTH),
conv_std_logic_vector(5311,AMPL_WIDTH),
conv_std_logic_vector(5314,AMPL_WIDTH),
conv_std_logic_vector(5317,AMPL_WIDTH),
conv_std_logic_vector(5320,AMPL_WIDTH),
conv_std_logic_vector(5323,AMPL_WIDTH),
conv_std_logic_vector(5326,AMPL_WIDTH),
conv_std_logic_vector(5329,AMPL_WIDTH),
conv_std_logic_vector(5332,AMPL_WIDTH),
conv_std_logic_vector(5336,AMPL_WIDTH),
conv_std_logic_vector(5339,AMPL_WIDTH),
conv_std_logic_vector(5342,AMPL_WIDTH),
conv_std_logic_vector(5345,AMPL_WIDTH),
conv_std_logic_vector(5348,AMPL_WIDTH),
conv_std_logic_vector(5351,AMPL_WIDTH),
conv_std_logic_vector(5354,AMPL_WIDTH),
conv_std_logic_vector(5357,AMPL_WIDTH),
conv_std_logic_vector(5360,AMPL_WIDTH),
conv_std_logic_vector(5363,AMPL_WIDTH),
conv_std_logic_vector(5367,AMPL_WIDTH),
conv_std_logic_vector(5370,AMPL_WIDTH),
conv_std_logic_vector(5373,AMPL_WIDTH),
conv_std_logic_vector(5376,AMPL_WIDTH),
conv_std_logic_vector(5379,AMPL_WIDTH),
conv_std_logic_vector(5382,AMPL_WIDTH),
conv_std_logic_vector(5385,AMPL_WIDTH),
conv_std_logic_vector(5388,AMPL_WIDTH),
conv_std_logic_vector(5391,AMPL_WIDTH),
conv_std_logic_vector(5394,AMPL_WIDTH),
conv_std_logic_vector(5398,AMPL_WIDTH),
conv_std_logic_vector(5401,AMPL_WIDTH),
conv_std_logic_vector(5404,AMPL_WIDTH),
conv_std_logic_vector(5407,AMPL_WIDTH),
conv_std_logic_vector(5410,AMPL_WIDTH),
conv_std_logic_vector(5413,AMPL_WIDTH),
conv_std_logic_vector(5416,AMPL_WIDTH),
conv_std_logic_vector(5419,AMPL_WIDTH),
conv_std_logic_vector(5422,AMPL_WIDTH),
conv_std_logic_vector(5425,AMPL_WIDTH),
conv_std_logic_vector(5428,AMPL_WIDTH),
conv_std_logic_vector(5432,AMPL_WIDTH),
conv_std_logic_vector(5435,AMPL_WIDTH),
conv_std_logic_vector(5438,AMPL_WIDTH),
conv_std_logic_vector(5441,AMPL_WIDTH),
conv_std_logic_vector(5444,AMPL_WIDTH),
conv_std_logic_vector(5447,AMPL_WIDTH),
conv_std_logic_vector(5450,AMPL_WIDTH),
conv_std_logic_vector(5453,AMPL_WIDTH),
conv_std_logic_vector(5456,AMPL_WIDTH),
conv_std_logic_vector(5459,AMPL_WIDTH),
conv_std_logic_vector(5463,AMPL_WIDTH),
conv_std_logic_vector(5466,AMPL_WIDTH),
conv_std_logic_vector(5469,AMPL_WIDTH),
conv_std_logic_vector(5472,AMPL_WIDTH),
conv_std_logic_vector(5475,AMPL_WIDTH),
conv_std_logic_vector(5478,AMPL_WIDTH),
conv_std_logic_vector(5481,AMPL_WIDTH),
conv_std_logic_vector(5484,AMPL_WIDTH),
conv_std_logic_vector(5487,AMPL_WIDTH),
conv_std_logic_vector(5490,AMPL_WIDTH),
conv_std_logic_vector(5494,AMPL_WIDTH),
conv_std_logic_vector(5497,AMPL_WIDTH),
conv_std_logic_vector(5500,AMPL_WIDTH),
conv_std_logic_vector(5503,AMPL_WIDTH),
conv_std_logic_vector(5506,AMPL_WIDTH),
conv_std_logic_vector(5509,AMPL_WIDTH),
conv_std_logic_vector(5512,AMPL_WIDTH),
conv_std_logic_vector(5515,AMPL_WIDTH),
conv_std_logic_vector(5518,AMPL_WIDTH),
conv_std_logic_vector(5521,AMPL_WIDTH),
conv_std_logic_vector(5525,AMPL_WIDTH),
conv_std_logic_vector(5528,AMPL_WIDTH),
conv_std_logic_vector(5531,AMPL_WIDTH),
conv_std_logic_vector(5534,AMPL_WIDTH),
conv_std_logic_vector(5537,AMPL_WIDTH),
conv_std_logic_vector(5540,AMPL_WIDTH),
conv_std_logic_vector(5543,AMPL_WIDTH),
conv_std_logic_vector(5546,AMPL_WIDTH),
conv_std_logic_vector(5549,AMPL_WIDTH),
conv_std_logic_vector(5552,AMPL_WIDTH),
conv_std_logic_vector(5555,AMPL_WIDTH),
conv_std_logic_vector(5559,AMPL_WIDTH),
conv_std_logic_vector(5562,AMPL_WIDTH),
conv_std_logic_vector(5565,AMPL_WIDTH),
conv_std_logic_vector(5568,AMPL_WIDTH),
conv_std_logic_vector(5571,AMPL_WIDTH),
conv_std_logic_vector(5574,AMPL_WIDTH),
conv_std_logic_vector(5577,AMPL_WIDTH),
conv_std_logic_vector(5580,AMPL_WIDTH),
conv_std_logic_vector(5583,AMPL_WIDTH),
conv_std_logic_vector(5586,AMPL_WIDTH),
conv_std_logic_vector(5590,AMPL_WIDTH),
conv_std_logic_vector(5593,AMPL_WIDTH),
conv_std_logic_vector(5596,AMPL_WIDTH),
conv_std_logic_vector(5599,AMPL_WIDTH),
conv_std_logic_vector(5602,AMPL_WIDTH),
conv_std_logic_vector(5605,AMPL_WIDTH),
conv_std_logic_vector(5608,AMPL_WIDTH),
conv_std_logic_vector(5611,AMPL_WIDTH),
conv_std_logic_vector(5614,AMPL_WIDTH),
conv_std_logic_vector(5617,AMPL_WIDTH),
conv_std_logic_vector(5620,AMPL_WIDTH),
conv_std_logic_vector(5624,AMPL_WIDTH),
conv_std_logic_vector(5627,AMPL_WIDTH),
conv_std_logic_vector(5630,AMPL_WIDTH),
conv_std_logic_vector(5633,AMPL_WIDTH),
conv_std_logic_vector(5636,AMPL_WIDTH),
conv_std_logic_vector(5639,AMPL_WIDTH),
conv_std_logic_vector(5642,AMPL_WIDTH),
conv_std_logic_vector(5645,AMPL_WIDTH),
conv_std_logic_vector(5648,AMPL_WIDTH),
conv_std_logic_vector(5651,AMPL_WIDTH),
conv_std_logic_vector(5655,AMPL_WIDTH),
conv_std_logic_vector(5658,AMPL_WIDTH),
conv_std_logic_vector(5661,AMPL_WIDTH),
conv_std_logic_vector(5664,AMPL_WIDTH),
conv_std_logic_vector(5667,AMPL_WIDTH),
conv_std_logic_vector(5670,AMPL_WIDTH),
conv_std_logic_vector(5673,AMPL_WIDTH),
conv_std_logic_vector(5676,AMPL_WIDTH),
conv_std_logic_vector(5679,AMPL_WIDTH),
conv_std_logic_vector(5682,AMPL_WIDTH),
conv_std_logic_vector(5685,AMPL_WIDTH),
conv_std_logic_vector(5689,AMPL_WIDTH),
conv_std_logic_vector(5692,AMPL_WIDTH),
conv_std_logic_vector(5695,AMPL_WIDTH),
conv_std_logic_vector(5698,AMPL_WIDTH),
conv_std_logic_vector(5701,AMPL_WIDTH),
conv_std_logic_vector(5704,AMPL_WIDTH),
conv_std_logic_vector(5707,AMPL_WIDTH),
conv_std_logic_vector(5710,AMPL_WIDTH),
conv_std_logic_vector(5713,AMPL_WIDTH),
conv_std_logic_vector(5716,AMPL_WIDTH),
conv_std_logic_vector(5719,AMPL_WIDTH),
conv_std_logic_vector(5723,AMPL_WIDTH),
conv_std_logic_vector(5726,AMPL_WIDTH),
conv_std_logic_vector(5729,AMPL_WIDTH),
conv_std_logic_vector(5732,AMPL_WIDTH),
conv_std_logic_vector(5735,AMPL_WIDTH),
conv_std_logic_vector(5738,AMPL_WIDTH),
conv_std_logic_vector(5741,AMPL_WIDTH),
conv_std_logic_vector(5744,AMPL_WIDTH),
conv_std_logic_vector(5747,AMPL_WIDTH),
conv_std_logic_vector(5750,AMPL_WIDTH),
conv_std_logic_vector(5754,AMPL_WIDTH),
conv_std_logic_vector(5757,AMPL_WIDTH),
conv_std_logic_vector(5760,AMPL_WIDTH),
conv_std_logic_vector(5763,AMPL_WIDTH),
conv_std_logic_vector(5766,AMPL_WIDTH),
conv_std_logic_vector(5769,AMPL_WIDTH),
conv_std_logic_vector(5772,AMPL_WIDTH),
conv_std_logic_vector(5775,AMPL_WIDTH),
conv_std_logic_vector(5778,AMPL_WIDTH),
conv_std_logic_vector(5781,AMPL_WIDTH),
conv_std_logic_vector(5784,AMPL_WIDTH),
conv_std_logic_vector(5788,AMPL_WIDTH),
conv_std_logic_vector(5791,AMPL_WIDTH),
conv_std_logic_vector(5794,AMPL_WIDTH),
conv_std_logic_vector(5797,AMPL_WIDTH),
conv_std_logic_vector(5800,AMPL_WIDTH),
conv_std_logic_vector(5803,AMPL_WIDTH),
conv_std_logic_vector(5806,AMPL_WIDTH),
conv_std_logic_vector(5809,AMPL_WIDTH),
conv_std_logic_vector(5812,AMPL_WIDTH),
conv_std_logic_vector(5815,AMPL_WIDTH),
conv_std_logic_vector(5818,AMPL_WIDTH),
conv_std_logic_vector(5822,AMPL_WIDTH),
conv_std_logic_vector(5825,AMPL_WIDTH),
conv_std_logic_vector(5828,AMPL_WIDTH),
conv_std_logic_vector(5831,AMPL_WIDTH),
conv_std_logic_vector(5834,AMPL_WIDTH),
conv_std_logic_vector(5837,AMPL_WIDTH),
conv_std_logic_vector(5840,AMPL_WIDTH),
conv_std_logic_vector(5843,AMPL_WIDTH),
conv_std_logic_vector(5846,AMPL_WIDTH),
conv_std_logic_vector(5849,AMPL_WIDTH),
conv_std_logic_vector(5852,AMPL_WIDTH),
conv_std_logic_vector(5856,AMPL_WIDTH),
conv_std_logic_vector(5859,AMPL_WIDTH),
conv_std_logic_vector(5862,AMPL_WIDTH),
conv_std_logic_vector(5865,AMPL_WIDTH),
conv_std_logic_vector(5868,AMPL_WIDTH),
conv_std_logic_vector(5871,AMPL_WIDTH),
conv_std_logic_vector(5874,AMPL_WIDTH),
conv_std_logic_vector(5877,AMPL_WIDTH),
conv_std_logic_vector(5880,AMPL_WIDTH),
conv_std_logic_vector(5883,AMPL_WIDTH),
conv_std_logic_vector(5886,AMPL_WIDTH),
conv_std_logic_vector(5890,AMPL_WIDTH),
conv_std_logic_vector(5893,AMPL_WIDTH),
conv_std_logic_vector(5896,AMPL_WIDTH),
conv_std_logic_vector(5899,AMPL_WIDTH),
conv_std_logic_vector(5902,AMPL_WIDTH),
conv_std_logic_vector(5905,AMPL_WIDTH),
conv_std_logic_vector(5908,AMPL_WIDTH),
conv_std_logic_vector(5911,AMPL_WIDTH),
conv_std_logic_vector(5914,AMPL_WIDTH),
conv_std_logic_vector(5917,AMPL_WIDTH),
conv_std_logic_vector(5920,AMPL_WIDTH),
conv_std_logic_vector(5924,AMPL_WIDTH),
conv_std_logic_vector(5927,AMPL_WIDTH),
conv_std_logic_vector(5930,AMPL_WIDTH),
conv_std_logic_vector(5933,AMPL_WIDTH),
conv_std_logic_vector(5936,AMPL_WIDTH),
conv_std_logic_vector(5939,AMPL_WIDTH),
conv_std_logic_vector(5942,AMPL_WIDTH),
conv_std_logic_vector(5945,AMPL_WIDTH),
conv_std_logic_vector(5948,AMPL_WIDTH),
conv_std_logic_vector(5951,AMPL_WIDTH),
conv_std_logic_vector(5954,AMPL_WIDTH),
conv_std_logic_vector(5958,AMPL_WIDTH),
conv_std_logic_vector(5961,AMPL_WIDTH),
conv_std_logic_vector(5964,AMPL_WIDTH),
conv_std_logic_vector(5967,AMPL_WIDTH),
conv_std_logic_vector(5970,AMPL_WIDTH),
conv_std_logic_vector(5973,AMPL_WIDTH),
conv_std_logic_vector(5976,AMPL_WIDTH),
conv_std_logic_vector(5979,AMPL_WIDTH),
conv_std_logic_vector(5982,AMPL_WIDTH),
conv_std_logic_vector(5985,AMPL_WIDTH),
conv_std_logic_vector(5988,AMPL_WIDTH),
conv_std_logic_vector(5991,AMPL_WIDTH),
conv_std_logic_vector(5995,AMPL_WIDTH),
conv_std_logic_vector(5998,AMPL_WIDTH),
conv_std_logic_vector(6001,AMPL_WIDTH),
conv_std_logic_vector(6004,AMPL_WIDTH),
conv_std_logic_vector(6007,AMPL_WIDTH),
conv_std_logic_vector(6010,AMPL_WIDTH),
conv_std_logic_vector(6013,AMPL_WIDTH),
conv_std_logic_vector(6016,AMPL_WIDTH),
conv_std_logic_vector(6019,AMPL_WIDTH),
conv_std_logic_vector(6022,AMPL_WIDTH),
conv_std_logic_vector(6025,AMPL_WIDTH),
conv_std_logic_vector(6029,AMPL_WIDTH),
conv_std_logic_vector(6032,AMPL_WIDTH),
conv_std_logic_vector(6035,AMPL_WIDTH),
conv_std_logic_vector(6038,AMPL_WIDTH),
conv_std_logic_vector(6041,AMPL_WIDTH),
conv_std_logic_vector(6044,AMPL_WIDTH),
conv_std_logic_vector(6047,AMPL_WIDTH),
conv_std_logic_vector(6050,AMPL_WIDTH),
conv_std_logic_vector(6053,AMPL_WIDTH),
conv_std_logic_vector(6056,AMPL_WIDTH),
conv_std_logic_vector(6059,AMPL_WIDTH),
conv_std_logic_vector(6063,AMPL_WIDTH),
conv_std_logic_vector(6066,AMPL_WIDTH),
conv_std_logic_vector(6069,AMPL_WIDTH),
conv_std_logic_vector(6072,AMPL_WIDTH),
conv_std_logic_vector(6075,AMPL_WIDTH),
conv_std_logic_vector(6078,AMPL_WIDTH),
conv_std_logic_vector(6081,AMPL_WIDTH),
conv_std_logic_vector(6084,AMPL_WIDTH),
conv_std_logic_vector(6087,AMPL_WIDTH),
conv_std_logic_vector(6090,AMPL_WIDTH),
conv_std_logic_vector(6093,AMPL_WIDTH),
conv_std_logic_vector(6096,AMPL_WIDTH),
conv_std_logic_vector(6100,AMPL_WIDTH),
conv_std_logic_vector(6103,AMPL_WIDTH),
conv_std_logic_vector(6106,AMPL_WIDTH),
conv_std_logic_vector(6109,AMPL_WIDTH),
conv_std_logic_vector(6112,AMPL_WIDTH),
conv_std_logic_vector(6115,AMPL_WIDTH),
conv_std_logic_vector(6118,AMPL_WIDTH),
conv_std_logic_vector(6121,AMPL_WIDTH),
conv_std_logic_vector(6124,AMPL_WIDTH),
conv_std_logic_vector(6127,AMPL_WIDTH),
conv_std_logic_vector(6130,AMPL_WIDTH),
conv_std_logic_vector(6134,AMPL_WIDTH),
conv_std_logic_vector(6137,AMPL_WIDTH),
conv_std_logic_vector(6140,AMPL_WIDTH),
conv_std_logic_vector(6143,AMPL_WIDTH),
conv_std_logic_vector(6146,AMPL_WIDTH),
conv_std_logic_vector(6149,AMPL_WIDTH),
conv_std_logic_vector(6152,AMPL_WIDTH),
conv_std_logic_vector(6155,AMPL_WIDTH),
conv_std_logic_vector(6158,AMPL_WIDTH),
conv_std_logic_vector(6161,AMPL_WIDTH),
conv_std_logic_vector(6164,AMPL_WIDTH),
conv_std_logic_vector(6167,AMPL_WIDTH),
conv_std_logic_vector(6171,AMPL_WIDTH),
conv_std_logic_vector(6174,AMPL_WIDTH),
conv_std_logic_vector(6177,AMPL_WIDTH),
conv_std_logic_vector(6180,AMPL_WIDTH),
conv_std_logic_vector(6183,AMPL_WIDTH),
conv_std_logic_vector(6186,AMPL_WIDTH),
conv_std_logic_vector(6189,AMPL_WIDTH),
conv_std_logic_vector(6192,AMPL_WIDTH),
conv_std_logic_vector(6195,AMPL_WIDTH),
conv_std_logic_vector(6198,AMPL_WIDTH),
conv_std_logic_vector(6201,AMPL_WIDTH),
conv_std_logic_vector(6204,AMPL_WIDTH),
conv_std_logic_vector(6208,AMPL_WIDTH),
conv_std_logic_vector(6211,AMPL_WIDTH),
conv_std_logic_vector(6214,AMPL_WIDTH),
conv_std_logic_vector(6217,AMPL_WIDTH),
conv_std_logic_vector(6220,AMPL_WIDTH),
conv_std_logic_vector(6223,AMPL_WIDTH),
conv_std_logic_vector(6226,AMPL_WIDTH),
conv_std_logic_vector(6229,AMPL_WIDTH),
conv_std_logic_vector(6232,AMPL_WIDTH),
conv_std_logic_vector(6235,AMPL_WIDTH),
conv_std_logic_vector(6238,AMPL_WIDTH),
conv_std_logic_vector(6241,AMPL_WIDTH),
conv_std_logic_vector(6245,AMPL_WIDTH),
conv_std_logic_vector(6248,AMPL_WIDTH),
conv_std_logic_vector(6251,AMPL_WIDTH),
conv_std_logic_vector(6254,AMPL_WIDTH),
conv_std_logic_vector(6257,AMPL_WIDTH),
conv_std_logic_vector(6260,AMPL_WIDTH),
conv_std_logic_vector(6263,AMPL_WIDTH),
conv_std_logic_vector(6266,AMPL_WIDTH),
conv_std_logic_vector(6269,AMPL_WIDTH),
conv_std_logic_vector(6272,AMPL_WIDTH),
conv_std_logic_vector(6275,AMPL_WIDTH),
conv_std_logic_vector(6278,AMPL_WIDTH),
conv_std_logic_vector(6282,AMPL_WIDTH),
conv_std_logic_vector(6285,AMPL_WIDTH),
conv_std_logic_vector(6288,AMPL_WIDTH),
conv_std_logic_vector(6291,AMPL_WIDTH),
conv_std_logic_vector(6294,AMPL_WIDTH),
conv_std_logic_vector(6297,AMPL_WIDTH),
conv_std_logic_vector(6300,AMPL_WIDTH),
conv_std_logic_vector(6303,AMPL_WIDTH),
conv_std_logic_vector(6306,AMPL_WIDTH),
conv_std_logic_vector(6309,AMPL_WIDTH),
conv_std_logic_vector(6312,AMPL_WIDTH),
conv_std_logic_vector(6315,AMPL_WIDTH),
conv_std_logic_vector(6319,AMPL_WIDTH),
conv_std_logic_vector(6322,AMPL_WIDTH),
conv_std_logic_vector(6325,AMPL_WIDTH),
conv_std_logic_vector(6328,AMPL_WIDTH),
conv_std_logic_vector(6331,AMPL_WIDTH),
conv_std_logic_vector(6334,AMPL_WIDTH),
conv_std_logic_vector(6337,AMPL_WIDTH),
conv_std_logic_vector(6340,AMPL_WIDTH),
conv_std_logic_vector(6343,AMPL_WIDTH),
conv_std_logic_vector(6346,AMPL_WIDTH),
conv_std_logic_vector(6349,AMPL_WIDTH),
conv_std_logic_vector(6352,AMPL_WIDTH),
conv_std_logic_vector(6356,AMPL_WIDTH),
conv_std_logic_vector(6359,AMPL_WIDTH),
conv_std_logic_vector(6362,AMPL_WIDTH),
conv_std_logic_vector(6365,AMPL_WIDTH),
conv_std_logic_vector(6368,AMPL_WIDTH),
conv_std_logic_vector(6371,AMPL_WIDTH),
conv_std_logic_vector(6374,AMPL_WIDTH),
conv_std_logic_vector(6377,AMPL_WIDTH),
conv_std_logic_vector(6380,AMPL_WIDTH),
conv_std_logic_vector(6383,AMPL_WIDTH),
conv_std_logic_vector(6386,AMPL_WIDTH),
conv_std_logic_vector(6389,AMPL_WIDTH),
conv_std_logic_vector(6393,AMPL_WIDTH),
conv_std_logic_vector(6396,AMPL_WIDTH),
conv_std_logic_vector(6399,AMPL_WIDTH),
conv_std_logic_vector(6402,AMPL_WIDTH),
conv_std_logic_vector(6405,AMPL_WIDTH),
conv_std_logic_vector(6408,AMPL_WIDTH),
conv_std_logic_vector(6411,AMPL_WIDTH),
conv_std_logic_vector(6414,AMPL_WIDTH),
conv_std_logic_vector(6417,AMPL_WIDTH),
conv_std_logic_vector(6420,AMPL_WIDTH),
conv_std_logic_vector(6423,AMPL_WIDTH),
conv_std_logic_vector(6426,AMPL_WIDTH),
conv_std_logic_vector(6429,AMPL_WIDTH),
conv_std_logic_vector(6433,AMPL_WIDTH),
conv_std_logic_vector(6436,AMPL_WIDTH),
conv_std_logic_vector(6439,AMPL_WIDTH),
conv_std_logic_vector(6442,AMPL_WIDTH),
conv_std_logic_vector(6445,AMPL_WIDTH),
conv_std_logic_vector(6448,AMPL_WIDTH),
conv_std_logic_vector(6451,AMPL_WIDTH),
conv_std_logic_vector(6454,AMPL_WIDTH),
conv_std_logic_vector(6457,AMPL_WIDTH),
conv_std_logic_vector(6460,AMPL_WIDTH),
conv_std_logic_vector(6463,AMPL_WIDTH),
conv_std_logic_vector(6466,AMPL_WIDTH),
conv_std_logic_vector(6470,AMPL_WIDTH),
conv_std_logic_vector(6473,AMPL_WIDTH),
conv_std_logic_vector(6476,AMPL_WIDTH),
conv_std_logic_vector(6479,AMPL_WIDTH),
conv_std_logic_vector(6482,AMPL_WIDTH),
conv_std_logic_vector(6485,AMPL_WIDTH),
conv_std_logic_vector(6488,AMPL_WIDTH),
conv_std_logic_vector(6491,AMPL_WIDTH),
conv_std_logic_vector(6494,AMPL_WIDTH),
conv_std_logic_vector(6497,AMPL_WIDTH),
conv_std_logic_vector(6500,AMPL_WIDTH),
conv_std_logic_vector(6503,AMPL_WIDTH),
conv_std_logic_vector(6506,AMPL_WIDTH),
conv_std_logic_vector(6510,AMPL_WIDTH),
conv_std_logic_vector(6513,AMPL_WIDTH),
conv_std_logic_vector(6516,AMPL_WIDTH),
conv_std_logic_vector(6519,AMPL_WIDTH),
conv_std_logic_vector(6522,AMPL_WIDTH),
conv_std_logic_vector(6525,AMPL_WIDTH),
conv_std_logic_vector(6528,AMPL_WIDTH),
conv_std_logic_vector(6531,AMPL_WIDTH),
conv_std_logic_vector(6534,AMPL_WIDTH),
conv_std_logic_vector(6537,AMPL_WIDTH),
conv_std_logic_vector(6540,AMPL_WIDTH),
conv_std_logic_vector(6543,AMPL_WIDTH),
conv_std_logic_vector(6547,AMPL_WIDTH),
conv_std_logic_vector(6550,AMPL_WIDTH),
conv_std_logic_vector(6553,AMPL_WIDTH),
conv_std_logic_vector(6556,AMPL_WIDTH),
conv_std_logic_vector(6559,AMPL_WIDTH),
conv_std_logic_vector(6562,AMPL_WIDTH),
conv_std_logic_vector(6565,AMPL_WIDTH),
conv_std_logic_vector(6568,AMPL_WIDTH),
conv_std_logic_vector(6571,AMPL_WIDTH),
conv_std_logic_vector(6574,AMPL_WIDTH),
conv_std_logic_vector(6577,AMPL_WIDTH),
conv_std_logic_vector(6580,AMPL_WIDTH),
conv_std_logic_vector(6583,AMPL_WIDTH),
conv_std_logic_vector(6587,AMPL_WIDTH),
conv_std_logic_vector(6590,AMPL_WIDTH),
conv_std_logic_vector(6593,AMPL_WIDTH),
conv_std_logic_vector(6596,AMPL_WIDTH),
conv_std_logic_vector(6599,AMPL_WIDTH),
conv_std_logic_vector(6602,AMPL_WIDTH),
conv_std_logic_vector(6605,AMPL_WIDTH),
conv_std_logic_vector(6608,AMPL_WIDTH),
conv_std_logic_vector(6611,AMPL_WIDTH),
conv_std_logic_vector(6614,AMPL_WIDTH),
conv_std_logic_vector(6617,AMPL_WIDTH),
conv_std_logic_vector(6620,AMPL_WIDTH),
conv_std_logic_vector(6623,AMPL_WIDTH),
conv_std_logic_vector(6627,AMPL_WIDTH),
conv_std_logic_vector(6630,AMPL_WIDTH),
conv_std_logic_vector(6633,AMPL_WIDTH),
conv_std_logic_vector(6636,AMPL_WIDTH),
conv_std_logic_vector(6639,AMPL_WIDTH),
conv_std_logic_vector(6642,AMPL_WIDTH),
conv_std_logic_vector(6645,AMPL_WIDTH),
conv_std_logic_vector(6648,AMPL_WIDTH),
conv_std_logic_vector(6651,AMPL_WIDTH),
conv_std_logic_vector(6654,AMPL_WIDTH),
conv_std_logic_vector(6657,AMPL_WIDTH),
conv_std_logic_vector(6660,AMPL_WIDTH),
conv_std_logic_vector(6663,AMPL_WIDTH),
conv_std_logic_vector(6667,AMPL_WIDTH),
conv_std_logic_vector(6670,AMPL_WIDTH),
conv_std_logic_vector(6673,AMPL_WIDTH),
conv_std_logic_vector(6676,AMPL_WIDTH),
conv_std_logic_vector(6679,AMPL_WIDTH),
conv_std_logic_vector(6682,AMPL_WIDTH),
conv_std_logic_vector(6685,AMPL_WIDTH),
conv_std_logic_vector(6688,AMPL_WIDTH),
conv_std_logic_vector(6691,AMPL_WIDTH),
conv_std_logic_vector(6694,AMPL_WIDTH),
conv_std_logic_vector(6697,AMPL_WIDTH),
conv_std_logic_vector(6700,AMPL_WIDTH),
conv_std_logic_vector(6703,AMPL_WIDTH),
conv_std_logic_vector(6706,AMPL_WIDTH),
conv_std_logic_vector(6710,AMPL_WIDTH),
conv_std_logic_vector(6713,AMPL_WIDTH),
conv_std_logic_vector(6716,AMPL_WIDTH),
conv_std_logic_vector(6719,AMPL_WIDTH),
conv_std_logic_vector(6722,AMPL_WIDTH),
conv_std_logic_vector(6725,AMPL_WIDTH),
conv_std_logic_vector(6728,AMPL_WIDTH),
conv_std_logic_vector(6731,AMPL_WIDTH),
conv_std_logic_vector(6734,AMPL_WIDTH),
conv_std_logic_vector(6737,AMPL_WIDTH),
conv_std_logic_vector(6740,AMPL_WIDTH),
conv_std_logic_vector(6743,AMPL_WIDTH),
conv_std_logic_vector(6746,AMPL_WIDTH),
conv_std_logic_vector(6750,AMPL_WIDTH),
conv_std_logic_vector(6753,AMPL_WIDTH),
conv_std_logic_vector(6756,AMPL_WIDTH),
conv_std_logic_vector(6759,AMPL_WIDTH),
conv_std_logic_vector(6762,AMPL_WIDTH),
conv_std_logic_vector(6765,AMPL_WIDTH),
conv_std_logic_vector(6768,AMPL_WIDTH),
conv_std_logic_vector(6771,AMPL_WIDTH),
conv_std_logic_vector(6774,AMPL_WIDTH),
conv_std_logic_vector(6777,AMPL_WIDTH),
conv_std_logic_vector(6780,AMPL_WIDTH),
conv_std_logic_vector(6783,AMPL_WIDTH),
conv_std_logic_vector(6786,AMPL_WIDTH),
conv_std_logic_vector(6789,AMPL_WIDTH),
conv_std_logic_vector(6793,AMPL_WIDTH),
conv_std_logic_vector(6796,AMPL_WIDTH),
conv_std_logic_vector(6799,AMPL_WIDTH),
conv_std_logic_vector(6802,AMPL_WIDTH),
conv_std_logic_vector(6805,AMPL_WIDTH),
conv_std_logic_vector(6808,AMPL_WIDTH),
conv_std_logic_vector(6811,AMPL_WIDTH),
conv_std_logic_vector(6814,AMPL_WIDTH),
conv_std_logic_vector(6817,AMPL_WIDTH),
conv_std_logic_vector(6820,AMPL_WIDTH),
conv_std_logic_vector(6823,AMPL_WIDTH),
conv_std_logic_vector(6826,AMPL_WIDTH),
conv_std_logic_vector(6829,AMPL_WIDTH),
conv_std_logic_vector(6833,AMPL_WIDTH),
conv_std_logic_vector(6836,AMPL_WIDTH),
conv_std_logic_vector(6839,AMPL_WIDTH),
conv_std_logic_vector(6842,AMPL_WIDTH),
conv_std_logic_vector(6845,AMPL_WIDTH),
conv_std_logic_vector(6848,AMPL_WIDTH),
conv_std_logic_vector(6851,AMPL_WIDTH),
conv_std_logic_vector(6854,AMPL_WIDTH),
conv_std_logic_vector(6857,AMPL_WIDTH),
conv_std_logic_vector(6860,AMPL_WIDTH),
conv_std_logic_vector(6863,AMPL_WIDTH),
conv_std_logic_vector(6866,AMPL_WIDTH),
conv_std_logic_vector(6869,AMPL_WIDTH),
conv_std_logic_vector(6872,AMPL_WIDTH),
conv_std_logic_vector(6876,AMPL_WIDTH),
conv_std_logic_vector(6879,AMPL_WIDTH),
conv_std_logic_vector(6882,AMPL_WIDTH),
conv_std_logic_vector(6885,AMPL_WIDTH),
conv_std_logic_vector(6888,AMPL_WIDTH),
conv_std_logic_vector(6891,AMPL_WIDTH),
conv_std_logic_vector(6894,AMPL_WIDTH),
conv_std_logic_vector(6897,AMPL_WIDTH),
conv_std_logic_vector(6900,AMPL_WIDTH),
conv_std_logic_vector(6903,AMPL_WIDTH),
conv_std_logic_vector(6906,AMPL_WIDTH),
conv_std_logic_vector(6909,AMPL_WIDTH),
conv_std_logic_vector(6912,AMPL_WIDTH),
conv_std_logic_vector(6915,AMPL_WIDTH),
conv_std_logic_vector(6919,AMPL_WIDTH),
conv_std_logic_vector(6922,AMPL_WIDTH),
conv_std_logic_vector(6925,AMPL_WIDTH),
conv_std_logic_vector(6928,AMPL_WIDTH),
conv_std_logic_vector(6931,AMPL_WIDTH),
conv_std_logic_vector(6934,AMPL_WIDTH),
conv_std_logic_vector(6937,AMPL_WIDTH),
conv_std_logic_vector(6940,AMPL_WIDTH),
conv_std_logic_vector(6943,AMPL_WIDTH),
conv_std_logic_vector(6946,AMPL_WIDTH),
conv_std_logic_vector(6949,AMPL_WIDTH),
conv_std_logic_vector(6952,AMPL_WIDTH),
conv_std_logic_vector(6955,AMPL_WIDTH),
conv_std_logic_vector(6958,AMPL_WIDTH),
conv_std_logic_vector(6961,AMPL_WIDTH),
conv_std_logic_vector(6965,AMPL_WIDTH),
conv_std_logic_vector(6968,AMPL_WIDTH),
conv_std_logic_vector(6971,AMPL_WIDTH),
conv_std_logic_vector(6974,AMPL_WIDTH),
conv_std_logic_vector(6977,AMPL_WIDTH),
conv_std_logic_vector(6980,AMPL_WIDTH),
conv_std_logic_vector(6983,AMPL_WIDTH),
conv_std_logic_vector(6986,AMPL_WIDTH),
conv_std_logic_vector(6989,AMPL_WIDTH),
conv_std_logic_vector(6992,AMPL_WIDTH),
conv_std_logic_vector(6995,AMPL_WIDTH),
conv_std_logic_vector(6998,AMPL_WIDTH),
conv_std_logic_vector(7001,AMPL_WIDTH),
conv_std_logic_vector(7004,AMPL_WIDTH),
conv_std_logic_vector(7008,AMPL_WIDTH),
conv_std_logic_vector(7011,AMPL_WIDTH),
conv_std_logic_vector(7014,AMPL_WIDTH),
conv_std_logic_vector(7017,AMPL_WIDTH),
conv_std_logic_vector(7020,AMPL_WIDTH),
conv_std_logic_vector(7023,AMPL_WIDTH),
conv_std_logic_vector(7026,AMPL_WIDTH),
conv_std_logic_vector(7029,AMPL_WIDTH),
conv_std_logic_vector(7032,AMPL_WIDTH),
conv_std_logic_vector(7035,AMPL_WIDTH),
conv_std_logic_vector(7038,AMPL_WIDTH),
conv_std_logic_vector(7041,AMPL_WIDTH),
conv_std_logic_vector(7044,AMPL_WIDTH),
conv_std_logic_vector(7047,AMPL_WIDTH),
conv_std_logic_vector(7050,AMPL_WIDTH),
conv_std_logic_vector(7054,AMPL_WIDTH),
conv_std_logic_vector(7057,AMPL_WIDTH),
conv_std_logic_vector(7060,AMPL_WIDTH),
conv_std_logic_vector(7063,AMPL_WIDTH),
conv_std_logic_vector(7066,AMPL_WIDTH),
conv_std_logic_vector(7069,AMPL_WIDTH),
conv_std_logic_vector(7072,AMPL_WIDTH),
conv_std_logic_vector(7075,AMPL_WIDTH),
conv_std_logic_vector(7078,AMPL_WIDTH),
conv_std_logic_vector(7081,AMPL_WIDTH),
conv_std_logic_vector(7084,AMPL_WIDTH),
conv_std_logic_vector(7087,AMPL_WIDTH),
conv_std_logic_vector(7090,AMPL_WIDTH),
conv_std_logic_vector(7093,AMPL_WIDTH),
conv_std_logic_vector(7097,AMPL_WIDTH),
conv_std_logic_vector(7100,AMPL_WIDTH),
conv_std_logic_vector(7103,AMPL_WIDTH),
conv_std_logic_vector(7106,AMPL_WIDTH),
conv_std_logic_vector(7109,AMPL_WIDTH),
conv_std_logic_vector(7112,AMPL_WIDTH),
conv_std_logic_vector(7115,AMPL_WIDTH),
conv_std_logic_vector(7118,AMPL_WIDTH),
conv_std_logic_vector(7121,AMPL_WIDTH),
conv_std_logic_vector(7124,AMPL_WIDTH),
conv_std_logic_vector(7127,AMPL_WIDTH),
conv_std_logic_vector(7130,AMPL_WIDTH),
conv_std_logic_vector(7133,AMPL_WIDTH),
conv_std_logic_vector(7136,AMPL_WIDTH),
conv_std_logic_vector(7139,AMPL_WIDTH),
conv_std_logic_vector(7143,AMPL_WIDTH),
conv_std_logic_vector(7146,AMPL_WIDTH),
conv_std_logic_vector(7149,AMPL_WIDTH),
conv_std_logic_vector(7152,AMPL_WIDTH),
conv_std_logic_vector(7155,AMPL_WIDTH),
conv_std_logic_vector(7158,AMPL_WIDTH),
conv_std_logic_vector(7161,AMPL_WIDTH),
conv_std_logic_vector(7164,AMPL_WIDTH),
conv_std_logic_vector(7167,AMPL_WIDTH),
conv_std_logic_vector(7170,AMPL_WIDTH),
conv_std_logic_vector(7173,AMPL_WIDTH),
conv_std_logic_vector(7176,AMPL_WIDTH),
conv_std_logic_vector(7179,AMPL_WIDTH),
conv_std_logic_vector(7182,AMPL_WIDTH),
conv_std_logic_vector(7185,AMPL_WIDTH),
conv_std_logic_vector(7188,AMPL_WIDTH),
conv_std_logic_vector(7192,AMPL_WIDTH),
conv_std_logic_vector(7195,AMPL_WIDTH),
conv_std_logic_vector(7198,AMPL_WIDTH),
conv_std_logic_vector(7201,AMPL_WIDTH),
conv_std_logic_vector(7204,AMPL_WIDTH),
conv_std_logic_vector(7207,AMPL_WIDTH),
conv_std_logic_vector(7210,AMPL_WIDTH),
conv_std_logic_vector(7213,AMPL_WIDTH),
conv_std_logic_vector(7216,AMPL_WIDTH),
conv_std_logic_vector(7219,AMPL_WIDTH),
conv_std_logic_vector(7222,AMPL_WIDTH),
conv_std_logic_vector(7225,AMPL_WIDTH),
conv_std_logic_vector(7228,AMPL_WIDTH),
conv_std_logic_vector(7231,AMPL_WIDTH),
conv_std_logic_vector(7234,AMPL_WIDTH),
conv_std_logic_vector(7238,AMPL_WIDTH),
conv_std_logic_vector(7241,AMPL_WIDTH),
conv_std_logic_vector(7244,AMPL_WIDTH),
conv_std_logic_vector(7247,AMPL_WIDTH),
conv_std_logic_vector(7250,AMPL_WIDTH),
conv_std_logic_vector(7253,AMPL_WIDTH),
conv_std_logic_vector(7256,AMPL_WIDTH),
conv_std_logic_vector(7259,AMPL_WIDTH),
conv_std_logic_vector(7262,AMPL_WIDTH),
conv_std_logic_vector(7265,AMPL_WIDTH),
conv_std_logic_vector(7268,AMPL_WIDTH),
conv_std_logic_vector(7271,AMPL_WIDTH),
conv_std_logic_vector(7274,AMPL_WIDTH),
conv_std_logic_vector(7277,AMPL_WIDTH),
conv_std_logic_vector(7280,AMPL_WIDTH),
conv_std_logic_vector(7283,AMPL_WIDTH),
conv_std_logic_vector(7287,AMPL_WIDTH),
conv_std_logic_vector(7290,AMPL_WIDTH),
conv_std_logic_vector(7293,AMPL_WIDTH),
conv_std_logic_vector(7296,AMPL_WIDTH),
conv_std_logic_vector(7299,AMPL_WIDTH),
conv_std_logic_vector(7302,AMPL_WIDTH),
conv_std_logic_vector(7305,AMPL_WIDTH),
conv_std_logic_vector(7308,AMPL_WIDTH),
conv_std_logic_vector(7311,AMPL_WIDTH),
conv_std_logic_vector(7314,AMPL_WIDTH),
conv_std_logic_vector(7317,AMPL_WIDTH),
conv_std_logic_vector(7320,AMPL_WIDTH),
conv_std_logic_vector(7323,AMPL_WIDTH),
conv_std_logic_vector(7326,AMPL_WIDTH),
conv_std_logic_vector(7329,AMPL_WIDTH),
conv_std_logic_vector(7332,AMPL_WIDTH),
conv_std_logic_vector(7336,AMPL_WIDTH),
conv_std_logic_vector(7339,AMPL_WIDTH),
conv_std_logic_vector(7342,AMPL_WIDTH),
conv_std_logic_vector(7345,AMPL_WIDTH),
conv_std_logic_vector(7348,AMPL_WIDTH),
conv_std_logic_vector(7351,AMPL_WIDTH),
conv_std_logic_vector(7354,AMPL_WIDTH),
conv_std_logic_vector(7357,AMPL_WIDTH),
conv_std_logic_vector(7360,AMPL_WIDTH),
conv_std_logic_vector(7363,AMPL_WIDTH),
conv_std_logic_vector(7366,AMPL_WIDTH),
conv_std_logic_vector(7369,AMPL_WIDTH),
conv_std_logic_vector(7372,AMPL_WIDTH),
conv_std_logic_vector(7375,AMPL_WIDTH),
conv_std_logic_vector(7378,AMPL_WIDTH),
conv_std_logic_vector(7381,AMPL_WIDTH),
conv_std_logic_vector(7385,AMPL_WIDTH),
conv_std_logic_vector(7388,AMPL_WIDTH),
conv_std_logic_vector(7391,AMPL_WIDTH),
conv_std_logic_vector(7394,AMPL_WIDTH),
conv_std_logic_vector(7397,AMPL_WIDTH),
conv_std_logic_vector(7400,AMPL_WIDTH),
conv_std_logic_vector(7403,AMPL_WIDTH),
conv_std_logic_vector(7406,AMPL_WIDTH),
conv_std_logic_vector(7409,AMPL_WIDTH),
conv_std_logic_vector(7412,AMPL_WIDTH),
conv_std_logic_vector(7415,AMPL_WIDTH),
conv_std_logic_vector(7418,AMPL_WIDTH),
conv_std_logic_vector(7421,AMPL_WIDTH),
conv_std_logic_vector(7424,AMPL_WIDTH),
conv_std_logic_vector(7427,AMPL_WIDTH),
conv_std_logic_vector(7430,AMPL_WIDTH),
conv_std_logic_vector(7433,AMPL_WIDTH),
conv_std_logic_vector(7437,AMPL_WIDTH),
conv_std_logic_vector(7440,AMPL_WIDTH),
conv_std_logic_vector(7443,AMPL_WIDTH),
conv_std_logic_vector(7446,AMPL_WIDTH),
conv_std_logic_vector(7449,AMPL_WIDTH),
conv_std_logic_vector(7452,AMPL_WIDTH),
conv_std_logic_vector(7455,AMPL_WIDTH),
conv_std_logic_vector(7458,AMPL_WIDTH),
conv_std_logic_vector(7461,AMPL_WIDTH),
conv_std_logic_vector(7464,AMPL_WIDTH),
conv_std_logic_vector(7467,AMPL_WIDTH),
conv_std_logic_vector(7470,AMPL_WIDTH),
conv_std_logic_vector(7473,AMPL_WIDTH),
conv_std_logic_vector(7476,AMPL_WIDTH),
conv_std_logic_vector(7479,AMPL_WIDTH),
conv_std_logic_vector(7482,AMPL_WIDTH),
conv_std_logic_vector(7485,AMPL_WIDTH),
conv_std_logic_vector(7489,AMPL_WIDTH),
conv_std_logic_vector(7492,AMPL_WIDTH),
conv_std_logic_vector(7495,AMPL_WIDTH),
conv_std_logic_vector(7498,AMPL_WIDTH),
conv_std_logic_vector(7501,AMPL_WIDTH),
conv_std_logic_vector(7504,AMPL_WIDTH),
conv_std_logic_vector(7507,AMPL_WIDTH),
conv_std_logic_vector(7510,AMPL_WIDTH),
conv_std_logic_vector(7513,AMPL_WIDTH),
conv_std_logic_vector(7516,AMPL_WIDTH),
conv_std_logic_vector(7519,AMPL_WIDTH),
conv_std_logic_vector(7522,AMPL_WIDTH),
conv_std_logic_vector(7525,AMPL_WIDTH),
conv_std_logic_vector(7528,AMPL_WIDTH),
conv_std_logic_vector(7531,AMPL_WIDTH),
conv_std_logic_vector(7534,AMPL_WIDTH),
conv_std_logic_vector(7537,AMPL_WIDTH),
conv_std_logic_vector(7541,AMPL_WIDTH),
conv_std_logic_vector(7544,AMPL_WIDTH),
conv_std_logic_vector(7547,AMPL_WIDTH),
conv_std_logic_vector(7550,AMPL_WIDTH),
conv_std_logic_vector(7553,AMPL_WIDTH),
conv_std_logic_vector(7556,AMPL_WIDTH),
conv_std_logic_vector(7559,AMPL_WIDTH),
conv_std_logic_vector(7562,AMPL_WIDTH),
conv_std_logic_vector(7565,AMPL_WIDTH),
conv_std_logic_vector(7568,AMPL_WIDTH),
conv_std_logic_vector(7571,AMPL_WIDTH),
conv_std_logic_vector(7574,AMPL_WIDTH),
conv_std_logic_vector(7577,AMPL_WIDTH),
conv_std_logic_vector(7580,AMPL_WIDTH),
conv_std_logic_vector(7583,AMPL_WIDTH),
conv_std_logic_vector(7586,AMPL_WIDTH),
conv_std_logic_vector(7589,AMPL_WIDTH),
conv_std_logic_vector(7592,AMPL_WIDTH),
conv_std_logic_vector(7596,AMPL_WIDTH),
conv_std_logic_vector(7599,AMPL_WIDTH),
conv_std_logic_vector(7602,AMPL_WIDTH),
conv_std_logic_vector(7605,AMPL_WIDTH),
conv_std_logic_vector(7608,AMPL_WIDTH),
conv_std_logic_vector(7611,AMPL_WIDTH),
conv_std_logic_vector(7614,AMPL_WIDTH),
conv_std_logic_vector(7617,AMPL_WIDTH),
conv_std_logic_vector(7620,AMPL_WIDTH),
conv_std_logic_vector(7623,AMPL_WIDTH),
conv_std_logic_vector(7626,AMPL_WIDTH),
conv_std_logic_vector(7629,AMPL_WIDTH),
conv_std_logic_vector(7632,AMPL_WIDTH),
conv_std_logic_vector(7635,AMPL_WIDTH),
conv_std_logic_vector(7638,AMPL_WIDTH),
conv_std_logic_vector(7641,AMPL_WIDTH),
conv_std_logic_vector(7644,AMPL_WIDTH),
conv_std_logic_vector(7647,AMPL_WIDTH),
conv_std_logic_vector(7651,AMPL_WIDTH),
conv_std_logic_vector(7654,AMPL_WIDTH),
conv_std_logic_vector(7657,AMPL_WIDTH),
conv_std_logic_vector(7660,AMPL_WIDTH),
conv_std_logic_vector(7663,AMPL_WIDTH),
conv_std_logic_vector(7666,AMPL_WIDTH),
conv_std_logic_vector(7669,AMPL_WIDTH),
conv_std_logic_vector(7672,AMPL_WIDTH),
conv_std_logic_vector(7675,AMPL_WIDTH),
conv_std_logic_vector(7678,AMPL_WIDTH),
conv_std_logic_vector(7681,AMPL_WIDTH),
conv_std_logic_vector(7684,AMPL_WIDTH),
conv_std_logic_vector(7687,AMPL_WIDTH),
conv_std_logic_vector(7690,AMPL_WIDTH),
conv_std_logic_vector(7693,AMPL_WIDTH),
conv_std_logic_vector(7696,AMPL_WIDTH),
conv_std_logic_vector(7699,AMPL_WIDTH),
conv_std_logic_vector(7702,AMPL_WIDTH),
conv_std_logic_vector(7705,AMPL_WIDTH),
conv_std_logic_vector(7709,AMPL_WIDTH),
conv_std_logic_vector(7712,AMPL_WIDTH),
conv_std_logic_vector(7715,AMPL_WIDTH),
conv_std_logic_vector(7718,AMPL_WIDTH),
conv_std_logic_vector(7721,AMPL_WIDTH),
conv_std_logic_vector(7724,AMPL_WIDTH),
conv_std_logic_vector(7727,AMPL_WIDTH),
conv_std_logic_vector(7730,AMPL_WIDTH),
conv_std_logic_vector(7733,AMPL_WIDTH),
conv_std_logic_vector(7736,AMPL_WIDTH),
conv_std_logic_vector(7739,AMPL_WIDTH),
conv_std_logic_vector(7742,AMPL_WIDTH),
conv_std_logic_vector(7745,AMPL_WIDTH),
conv_std_logic_vector(7748,AMPL_WIDTH),
conv_std_logic_vector(7751,AMPL_WIDTH),
conv_std_logic_vector(7754,AMPL_WIDTH),
conv_std_logic_vector(7757,AMPL_WIDTH),
conv_std_logic_vector(7760,AMPL_WIDTH),
conv_std_logic_vector(7764,AMPL_WIDTH),
conv_std_logic_vector(7767,AMPL_WIDTH),
conv_std_logic_vector(7770,AMPL_WIDTH),
conv_std_logic_vector(7773,AMPL_WIDTH),
conv_std_logic_vector(7776,AMPL_WIDTH),
conv_std_logic_vector(7779,AMPL_WIDTH),
conv_std_logic_vector(7782,AMPL_WIDTH),
conv_std_logic_vector(7785,AMPL_WIDTH),
conv_std_logic_vector(7788,AMPL_WIDTH),
conv_std_logic_vector(7791,AMPL_WIDTH),
conv_std_logic_vector(7794,AMPL_WIDTH),
conv_std_logic_vector(7797,AMPL_WIDTH),
conv_std_logic_vector(7800,AMPL_WIDTH),
conv_std_logic_vector(7803,AMPL_WIDTH),
conv_std_logic_vector(7806,AMPL_WIDTH),
conv_std_logic_vector(7809,AMPL_WIDTH),
conv_std_logic_vector(7812,AMPL_WIDTH),
conv_std_logic_vector(7815,AMPL_WIDTH),
conv_std_logic_vector(7818,AMPL_WIDTH),
conv_std_logic_vector(7821,AMPL_WIDTH),
conv_std_logic_vector(7825,AMPL_WIDTH),
conv_std_logic_vector(7828,AMPL_WIDTH),
conv_std_logic_vector(7831,AMPL_WIDTH),
conv_std_logic_vector(7834,AMPL_WIDTH),
conv_std_logic_vector(7837,AMPL_WIDTH),
conv_std_logic_vector(7840,AMPL_WIDTH),
conv_std_logic_vector(7843,AMPL_WIDTH),
conv_std_logic_vector(7846,AMPL_WIDTH),
conv_std_logic_vector(7849,AMPL_WIDTH),
conv_std_logic_vector(7852,AMPL_WIDTH),
conv_std_logic_vector(7855,AMPL_WIDTH),
conv_std_logic_vector(7858,AMPL_WIDTH),
conv_std_logic_vector(7861,AMPL_WIDTH),
conv_std_logic_vector(7864,AMPL_WIDTH),
conv_std_logic_vector(7867,AMPL_WIDTH),
conv_std_logic_vector(7870,AMPL_WIDTH),
conv_std_logic_vector(7873,AMPL_WIDTH),
conv_std_logic_vector(7876,AMPL_WIDTH),
conv_std_logic_vector(7879,AMPL_WIDTH),
conv_std_logic_vector(7882,AMPL_WIDTH),
conv_std_logic_vector(7886,AMPL_WIDTH),
conv_std_logic_vector(7889,AMPL_WIDTH),
conv_std_logic_vector(7892,AMPL_WIDTH),
conv_std_logic_vector(7895,AMPL_WIDTH),
conv_std_logic_vector(7898,AMPL_WIDTH),
conv_std_logic_vector(7901,AMPL_WIDTH),
conv_std_logic_vector(7904,AMPL_WIDTH),
conv_std_logic_vector(7907,AMPL_WIDTH),
conv_std_logic_vector(7910,AMPL_WIDTH),
conv_std_logic_vector(7913,AMPL_WIDTH),
conv_std_logic_vector(7916,AMPL_WIDTH),
conv_std_logic_vector(7919,AMPL_WIDTH),
conv_std_logic_vector(7922,AMPL_WIDTH),
conv_std_logic_vector(7925,AMPL_WIDTH),
conv_std_logic_vector(7928,AMPL_WIDTH),
conv_std_logic_vector(7931,AMPL_WIDTH),
conv_std_logic_vector(7934,AMPL_WIDTH),
conv_std_logic_vector(7937,AMPL_WIDTH),
conv_std_logic_vector(7940,AMPL_WIDTH),
conv_std_logic_vector(7943,AMPL_WIDTH),
conv_std_logic_vector(7946,AMPL_WIDTH),
conv_std_logic_vector(7950,AMPL_WIDTH),
conv_std_logic_vector(7953,AMPL_WIDTH),
conv_std_logic_vector(7956,AMPL_WIDTH),
conv_std_logic_vector(7959,AMPL_WIDTH),
conv_std_logic_vector(7962,AMPL_WIDTH),
conv_std_logic_vector(7965,AMPL_WIDTH),
conv_std_logic_vector(7968,AMPL_WIDTH),
conv_std_logic_vector(7971,AMPL_WIDTH),
conv_std_logic_vector(7974,AMPL_WIDTH),
conv_std_logic_vector(7977,AMPL_WIDTH),
conv_std_logic_vector(7980,AMPL_WIDTH),
conv_std_logic_vector(7983,AMPL_WIDTH),
conv_std_logic_vector(7986,AMPL_WIDTH),
conv_std_logic_vector(7989,AMPL_WIDTH),
conv_std_logic_vector(7992,AMPL_WIDTH),
conv_std_logic_vector(7995,AMPL_WIDTH),
conv_std_logic_vector(7998,AMPL_WIDTH),
conv_std_logic_vector(8001,AMPL_WIDTH),
conv_std_logic_vector(8004,AMPL_WIDTH),
conv_std_logic_vector(8007,AMPL_WIDTH),
conv_std_logic_vector(8010,AMPL_WIDTH),
conv_std_logic_vector(8014,AMPL_WIDTH),
conv_std_logic_vector(8017,AMPL_WIDTH),
conv_std_logic_vector(8020,AMPL_WIDTH),
conv_std_logic_vector(8023,AMPL_WIDTH),
conv_std_logic_vector(8026,AMPL_WIDTH),
conv_std_logic_vector(8029,AMPL_WIDTH),
conv_std_logic_vector(8032,AMPL_WIDTH),
conv_std_logic_vector(8035,AMPL_WIDTH),
conv_std_logic_vector(8038,AMPL_WIDTH),
conv_std_logic_vector(8041,AMPL_WIDTH),
conv_std_logic_vector(8044,AMPL_WIDTH),
conv_std_logic_vector(8047,AMPL_WIDTH),
conv_std_logic_vector(8050,AMPL_WIDTH),
conv_std_logic_vector(8053,AMPL_WIDTH),
conv_std_logic_vector(8056,AMPL_WIDTH),
conv_std_logic_vector(8059,AMPL_WIDTH),
conv_std_logic_vector(8062,AMPL_WIDTH),
conv_std_logic_vector(8065,AMPL_WIDTH),
conv_std_logic_vector(8068,AMPL_WIDTH),
conv_std_logic_vector(8071,AMPL_WIDTH),
conv_std_logic_vector(8074,AMPL_WIDTH),
conv_std_logic_vector(8077,AMPL_WIDTH),
conv_std_logic_vector(8081,AMPL_WIDTH),
conv_std_logic_vector(8084,AMPL_WIDTH),
conv_std_logic_vector(8087,AMPL_WIDTH),
conv_std_logic_vector(8090,AMPL_WIDTH),
conv_std_logic_vector(8093,AMPL_WIDTH),
conv_std_logic_vector(8096,AMPL_WIDTH),
conv_std_logic_vector(8099,AMPL_WIDTH),
conv_std_logic_vector(8102,AMPL_WIDTH),
conv_std_logic_vector(8105,AMPL_WIDTH),
conv_std_logic_vector(8108,AMPL_WIDTH),
conv_std_logic_vector(8111,AMPL_WIDTH),
conv_std_logic_vector(8114,AMPL_WIDTH),
conv_std_logic_vector(8117,AMPL_WIDTH),
conv_std_logic_vector(8120,AMPL_WIDTH),
conv_std_logic_vector(8123,AMPL_WIDTH),
conv_std_logic_vector(8126,AMPL_WIDTH),
conv_std_logic_vector(8129,AMPL_WIDTH),
conv_std_logic_vector(8132,AMPL_WIDTH),
conv_std_logic_vector(8135,AMPL_WIDTH),
conv_std_logic_vector(8138,AMPL_WIDTH),
conv_std_logic_vector(8141,AMPL_WIDTH),
conv_std_logic_vector(8144,AMPL_WIDTH),
conv_std_logic_vector(8147,AMPL_WIDTH),
conv_std_logic_vector(8151,AMPL_WIDTH),
conv_std_logic_vector(8154,AMPL_WIDTH),
conv_std_logic_vector(8157,AMPL_WIDTH),
conv_std_logic_vector(8160,AMPL_WIDTH),
conv_std_logic_vector(8163,AMPL_WIDTH),
conv_std_logic_vector(8166,AMPL_WIDTH),
conv_std_logic_vector(8169,AMPL_WIDTH),
conv_std_logic_vector(8172,AMPL_WIDTH),
conv_std_logic_vector(8175,AMPL_WIDTH),
conv_std_logic_vector(8178,AMPL_WIDTH),
conv_std_logic_vector(8181,AMPL_WIDTH),
conv_std_logic_vector(8184,AMPL_WIDTH),
conv_std_logic_vector(8187,AMPL_WIDTH),
conv_std_logic_vector(8190,AMPL_WIDTH),
conv_std_logic_vector(8193,AMPL_WIDTH),
conv_std_logic_vector(8196,AMPL_WIDTH),
conv_std_logic_vector(8199,AMPL_WIDTH),
conv_std_logic_vector(8202,AMPL_WIDTH),
conv_std_logic_vector(8205,AMPL_WIDTH),
conv_std_logic_vector(8208,AMPL_WIDTH),
conv_std_logic_vector(8211,AMPL_WIDTH),
conv_std_logic_vector(8214,AMPL_WIDTH),
conv_std_logic_vector(8217,AMPL_WIDTH),
conv_std_logic_vector(8220,AMPL_WIDTH),
conv_std_logic_vector(8224,AMPL_WIDTH),
conv_std_logic_vector(8227,AMPL_WIDTH),
conv_std_logic_vector(8230,AMPL_WIDTH),
conv_std_logic_vector(8233,AMPL_WIDTH),
conv_std_logic_vector(8236,AMPL_WIDTH),
conv_std_logic_vector(8239,AMPL_WIDTH),
conv_std_logic_vector(8242,AMPL_WIDTH),
conv_std_logic_vector(8245,AMPL_WIDTH),
conv_std_logic_vector(8248,AMPL_WIDTH),
conv_std_logic_vector(8251,AMPL_WIDTH),
conv_std_logic_vector(8254,AMPL_WIDTH),
conv_std_logic_vector(8257,AMPL_WIDTH),
conv_std_logic_vector(8260,AMPL_WIDTH),
conv_std_logic_vector(8263,AMPL_WIDTH),
conv_std_logic_vector(8266,AMPL_WIDTH),
conv_std_logic_vector(8269,AMPL_WIDTH),
conv_std_logic_vector(8272,AMPL_WIDTH),
conv_std_logic_vector(8275,AMPL_WIDTH),
conv_std_logic_vector(8278,AMPL_WIDTH),
conv_std_logic_vector(8281,AMPL_WIDTH),
conv_std_logic_vector(8284,AMPL_WIDTH),
conv_std_logic_vector(8287,AMPL_WIDTH),
conv_std_logic_vector(8290,AMPL_WIDTH),
conv_std_logic_vector(8293,AMPL_WIDTH),
conv_std_logic_vector(8296,AMPL_WIDTH),
conv_std_logic_vector(8300,AMPL_WIDTH),
conv_std_logic_vector(8303,AMPL_WIDTH),
conv_std_logic_vector(8306,AMPL_WIDTH),
conv_std_logic_vector(8309,AMPL_WIDTH),
conv_std_logic_vector(8312,AMPL_WIDTH),
conv_std_logic_vector(8315,AMPL_WIDTH),
conv_std_logic_vector(8318,AMPL_WIDTH),
conv_std_logic_vector(8321,AMPL_WIDTH),
conv_std_logic_vector(8324,AMPL_WIDTH),
conv_std_logic_vector(8327,AMPL_WIDTH),
conv_std_logic_vector(8330,AMPL_WIDTH),
conv_std_logic_vector(8333,AMPL_WIDTH),
conv_std_logic_vector(8336,AMPL_WIDTH),
conv_std_logic_vector(8339,AMPL_WIDTH),
conv_std_logic_vector(8342,AMPL_WIDTH),
conv_std_logic_vector(8345,AMPL_WIDTH),
conv_std_logic_vector(8348,AMPL_WIDTH),
conv_std_logic_vector(8351,AMPL_WIDTH),
conv_std_logic_vector(8354,AMPL_WIDTH),
conv_std_logic_vector(8357,AMPL_WIDTH),
conv_std_logic_vector(8360,AMPL_WIDTH),
conv_std_logic_vector(8363,AMPL_WIDTH),
conv_std_logic_vector(8366,AMPL_WIDTH),
conv_std_logic_vector(8369,AMPL_WIDTH),
conv_std_logic_vector(8372,AMPL_WIDTH),
conv_std_logic_vector(8375,AMPL_WIDTH),
conv_std_logic_vector(8379,AMPL_WIDTH),
conv_std_logic_vector(8382,AMPL_WIDTH),
conv_std_logic_vector(8385,AMPL_WIDTH),
conv_std_logic_vector(8388,AMPL_WIDTH),
conv_std_logic_vector(8391,AMPL_WIDTH),
conv_std_logic_vector(8394,AMPL_WIDTH),
conv_std_logic_vector(8397,AMPL_WIDTH),
conv_std_logic_vector(8400,AMPL_WIDTH),
conv_std_logic_vector(8403,AMPL_WIDTH),
conv_std_logic_vector(8406,AMPL_WIDTH),
conv_std_logic_vector(8409,AMPL_WIDTH),
conv_std_logic_vector(8412,AMPL_WIDTH),
conv_std_logic_vector(8415,AMPL_WIDTH),
conv_std_logic_vector(8418,AMPL_WIDTH),
conv_std_logic_vector(8421,AMPL_WIDTH),
conv_std_logic_vector(8424,AMPL_WIDTH),
conv_std_logic_vector(8427,AMPL_WIDTH),
conv_std_logic_vector(8430,AMPL_WIDTH),
conv_std_logic_vector(8433,AMPL_WIDTH),
conv_std_logic_vector(8436,AMPL_WIDTH),
conv_std_logic_vector(8439,AMPL_WIDTH),
conv_std_logic_vector(8442,AMPL_WIDTH),
conv_std_logic_vector(8445,AMPL_WIDTH),
conv_std_logic_vector(8448,AMPL_WIDTH),
conv_std_logic_vector(8451,AMPL_WIDTH),
conv_std_logic_vector(8454,AMPL_WIDTH),
conv_std_logic_vector(8457,AMPL_WIDTH),
conv_std_logic_vector(8460,AMPL_WIDTH),
conv_std_logic_vector(8464,AMPL_WIDTH),
conv_std_logic_vector(8467,AMPL_WIDTH),
conv_std_logic_vector(8470,AMPL_WIDTH),
conv_std_logic_vector(8473,AMPL_WIDTH),
conv_std_logic_vector(8476,AMPL_WIDTH),
conv_std_logic_vector(8479,AMPL_WIDTH),
conv_std_logic_vector(8482,AMPL_WIDTH),
conv_std_logic_vector(8485,AMPL_WIDTH),
conv_std_logic_vector(8488,AMPL_WIDTH),
conv_std_logic_vector(8491,AMPL_WIDTH),
conv_std_logic_vector(8494,AMPL_WIDTH),
conv_std_logic_vector(8497,AMPL_WIDTH),
conv_std_logic_vector(8500,AMPL_WIDTH),
conv_std_logic_vector(8503,AMPL_WIDTH),
conv_std_logic_vector(8506,AMPL_WIDTH),
conv_std_logic_vector(8509,AMPL_WIDTH),
conv_std_logic_vector(8512,AMPL_WIDTH),
conv_std_logic_vector(8515,AMPL_WIDTH),
conv_std_logic_vector(8518,AMPL_WIDTH),
conv_std_logic_vector(8521,AMPL_WIDTH),
conv_std_logic_vector(8524,AMPL_WIDTH),
conv_std_logic_vector(8527,AMPL_WIDTH),
conv_std_logic_vector(8530,AMPL_WIDTH),
conv_std_logic_vector(8533,AMPL_WIDTH),
conv_std_logic_vector(8536,AMPL_WIDTH),
conv_std_logic_vector(8539,AMPL_WIDTH),
conv_std_logic_vector(8542,AMPL_WIDTH),
conv_std_logic_vector(8545,AMPL_WIDTH),
conv_std_logic_vector(8548,AMPL_WIDTH),
conv_std_logic_vector(8552,AMPL_WIDTH),
conv_std_logic_vector(8555,AMPL_WIDTH),
conv_std_logic_vector(8558,AMPL_WIDTH),
conv_std_logic_vector(8561,AMPL_WIDTH),
conv_std_logic_vector(8564,AMPL_WIDTH),
conv_std_logic_vector(8567,AMPL_WIDTH),
conv_std_logic_vector(8570,AMPL_WIDTH),
conv_std_logic_vector(8573,AMPL_WIDTH),
conv_std_logic_vector(8576,AMPL_WIDTH),
conv_std_logic_vector(8579,AMPL_WIDTH),
conv_std_logic_vector(8582,AMPL_WIDTH),
conv_std_logic_vector(8585,AMPL_WIDTH),
conv_std_logic_vector(8588,AMPL_WIDTH),
conv_std_logic_vector(8591,AMPL_WIDTH),
conv_std_logic_vector(8594,AMPL_WIDTH),
conv_std_logic_vector(8597,AMPL_WIDTH),
conv_std_logic_vector(8600,AMPL_WIDTH),
conv_std_logic_vector(8603,AMPL_WIDTH),
conv_std_logic_vector(8606,AMPL_WIDTH),
conv_std_logic_vector(8609,AMPL_WIDTH),
conv_std_logic_vector(8612,AMPL_WIDTH),
conv_std_logic_vector(8615,AMPL_WIDTH),
conv_std_logic_vector(8618,AMPL_WIDTH),
conv_std_logic_vector(8621,AMPL_WIDTH),
conv_std_logic_vector(8624,AMPL_WIDTH),
conv_std_logic_vector(8627,AMPL_WIDTH),
conv_std_logic_vector(8630,AMPL_WIDTH),
conv_std_logic_vector(8633,AMPL_WIDTH),
conv_std_logic_vector(8636,AMPL_WIDTH),
conv_std_logic_vector(8639,AMPL_WIDTH),
conv_std_logic_vector(8642,AMPL_WIDTH),
conv_std_logic_vector(8645,AMPL_WIDTH),
conv_std_logic_vector(8649,AMPL_WIDTH),
conv_std_logic_vector(8652,AMPL_WIDTH),
conv_std_logic_vector(8655,AMPL_WIDTH),
conv_std_logic_vector(8658,AMPL_WIDTH),
conv_std_logic_vector(8661,AMPL_WIDTH),
conv_std_logic_vector(8664,AMPL_WIDTH),
conv_std_logic_vector(8667,AMPL_WIDTH),
conv_std_logic_vector(8670,AMPL_WIDTH),
conv_std_logic_vector(8673,AMPL_WIDTH),
conv_std_logic_vector(8676,AMPL_WIDTH),
conv_std_logic_vector(8679,AMPL_WIDTH),
conv_std_logic_vector(8682,AMPL_WIDTH),
conv_std_logic_vector(8685,AMPL_WIDTH),
conv_std_logic_vector(8688,AMPL_WIDTH),
conv_std_logic_vector(8691,AMPL_WIDTH),
conv_std_logic_vector(8694,AMPL_WIDTH),
conv_std_logic_vector(8697,AMPL_WIDTH),
conv_std_logic_vector(8700,AMPL_WIDTH),
conv_std_logic_vector(8703,AMPL_WIDTH),
conv_std_logic_vector(8706,AMPL_WIDTH),
conv_std_logic_vector(8709,AMPL_WIDTH),
conv_std_logic_vector(8712,AMPL_WIDTH),
conv_std_logic_vector(8715,AMPL_WIDTH),
conv_std_logic_vector(8718,AMPL_WIDTH),
conv_std_logic_vector(8721,AMPL_WIDTH),
conv_std_logic_vector(8724,AMPL_WIDTH),
conv_std_logic_vector(8727,AMPL_WIDTH),
conv_std_logic_vector(8730,AMPL_WIDTH),
conv_std_logic_vector(8733,AMPL_WIDTH),
conv_std_logic_vector(8736,AMPL_WIDTH),
conv_std_logic_vector(8739,AMPL_WIDTH),
conv_std_logic_vector(8742,AMPL_WIDTH),
conv_std_logic_vector(8745,AMPL_WIDTH),
conv_std_logic_vector(8748,AMPL_WIDTH),
conv_std_logic_vector(8751,AMPL_WIDTH),
conv_std_logic_vector(8755,AMPL_WIDTH),
conv_std_logic_vector(8758,AMPL_WIDTH),
conv_std_logic_vector(8761,AMPL_WIDTH),
conv_std_logic_vector(8764,AMPL_WIDTH),
conv_std_logic_vector(8767,AMPL_WIDTH),
conv_std_logic_vector(8770,AMPL_WIDTH),
conv_std_logic_vector(8773,AMPL_WIDTH),
conv_std_logic_vector(8776,AMPL_WIDTH),
conv_std_logic_vector(8779,AMPL_WIDTH),
conv_std_logic_vector(8782,AMPL_WIDTH),
conv_std_logic_vector(8785,AMPL_WIDTH),
conv_std_logic_vector(8788,AMPL_WIDTH),
conv_std_logic_vector(8791,AMPL_WIDTH),
conv_std_logic_vector(8794,AMPL_WIDTH),
conv_std_logic_vector(8797,AMPL_WIDTH),
conv_std_logic_vector(8800,AMPL_WIDTH),
conv_std_logic_vector(8803,AMPL_WIDTH),
conv_std_logic_vector(8806,AMPL_WIDTH),
conv_std_logic_vector(8809,AMPL_WIDTH),
conv_std_logic_vector(8812,AMPL_WIDTH),
conv_std_logic_vector(8815,AMPL_WIDTH),
conv_std_logic_vector(8818,AMPL_WIDTH),
conv_std_logic_vector(8821,AMPL_WIDTH),
conv_std_logic_vector(8824,AMPL_WIDTH),
conv_std_logic_vector(8827,AMPL_WIDTH),
conv_std_logic_vector(8830,AMPL_WIDTH),
conv_std_logic_vector(8833,AMPL_WIDTH),
conv_std_logic_vector(8836,AMPL_WIDTH),
conv_std_logic_vector(8839,AMPL_WIDTH),
conv_std_logic_vector(8842,AMPL_WIDTH),
conv_std_logic_vector(8845,AMPL_WIDTH),
conv_std_logic_vector(8848,AMPL_WIDTH),
conv_std_logic_vector(8851,AMPL_WIDTH),
conv_std_logic_vector(8854,AMPL_WIDTH),
conv_std_logic_vector(8857,AMPL_WIDTH),
conv_std_logic_vector(8860,AMPL_WIDTH),
conv_std_logic_vector(8863,AMPL_WIDTH),
conv_std_logic_vector(8866,AMPL_WIDTH),
conv_std_logic_vector(8869,AMPL_WIDTH),
conv_std_logic_vector(8873,AMPL_WIDTH),
conv_std_logic_vector(8876,AMPL_WIDTH),
conv_std_logic_vector(8879,AMPL_WIDTH),
conv_std_logic_vector(8882,AMPL_WIDTH),
conv_std_logic_vector(8885,AMPL_WIDTH),
conv_std_logic_vector(8888,AMPL_WIDTH),
conv_std_logic_vector(8891,AMPL_WIDTH),
conv_std_logic_vector(8894,AMPL_WIDTH),
conv_std_logic_vector(8897,AMPL_WIDTH),
conv_std_logic_vector(8900,AMPL_WIDTH),
conv_std_logic_vector(8903,AMPL_WIDTH),
conv_std_logic_vector(8906,AMPL_WIDTH),
conv_std_logic_vector(8909,AMPL_WIDTH),
conv_std_logic_vector(8912,AMPL_WIDTH),
conv_std_logic_vector(8915,AMPL_WIDTH),
conv_std_logic_vector(8918,AMPL_WIDTH),
conv_std_logic_vector(8921,AMPL_WIDTH),
conv_std_logic_vector(8924,AMPL_WIDTH),
conv_std_logic_vector(8927,AMPL_WIDTH),
conv_std_logic_vector(8930,AMPL_WIDTH),
conv_std_logic_vector(8933,AMPL_WIDTH),
conv_std_logic_vector(8936,AMPL_WIDTH),
conv_std_logic_vector(8939,AMPL_WIDTH),
conv_std_logic_vector(8942,AMPL_WIDTH),
conv_std_logic_vector(8945,AMPL_WIDTH),
conv_std_logic_vector(8948,AMPL_WIDTH),
conv_std_logic_vector(8951,AMPL_WIDTH),
conv_std_logic_vector(8954,AMPL_WIDTH),
conv_std_logic_vector(8957,AMPL_WIDTH),
conv_std_logic_vector(8960,AMPL_WIDTH),
conv_std_logic_vector(8963,AMPL_WIDTH),
conv_std_logic_vector(8966,AMPL_WIDTH),
conv_std_logic_vector(8969,AMPL_WIDTH),
conv_std_logic_vector(8972,AMPL_WIDTH),
conv_std_logic_vector(8975,AMPL_WIDTH),
conv_std_logic_vector(8978,AMPL_WIDTH),
conv_std_logic_vector(8981,AMPL_WIDTH),
conv_std_logic_vector(8984,AMPL_WIDTH),
conv_std_logic_vector(8987,AMPL_WIDTH),
conv_std_logic_vector(8990,AMPL_WIDTH),
conv_std_logic_vector(8993,AMPL_WIDTH),
conv_std_logic_vector(8996,AMPL_WIDTH),
conv_std_logic_vector(8999,AMPL_WIDTH),
conv_std_logic_vector(9002,AMPL_WIDTH),
conv_std_logic_vector(9006,AMPL_WIDTH),
conv_std_logic_vector(9009,AMPL_WIDTH),
conv_std_logic_vector(9012,AMPL_WIDTH),
conv_std_logic_vector(9015,AMPL_WIDTH),
conv_std_logic_vector(9018,AMPL_WIDTH),
conv_std_logic_vector(9021,AMPL_WIDTH),
conv_std_logic_vector(9024,AMPL_WIDTH),
conv_std_logic_vector(9027,AMPL_WIDTH),
conv_std_logic_vector(9030,AMPL_WIDTH),
conv_std_logic_vector(9033,AMPL_WIDTH),
conv_std_logic_vector(9036,AMPL_WIDTH),
conv_std_logic_vector(9039,AMPL_WIDTH),
conv_std_logic_vector(9042,AMPL_WIDTH),
conv_std_logic_vector(9045,AMPL_WIDTH),
conv_std_logic_vector(9048,AMPL_WIDTH),
conv_std_logic_vector(9051,AMPL_WIDTH),
conv_std_logic_vector(9054,AMPL_WIDTH),
conv_std_logic_vector(9057,AMPL_WIDTH),
conv_std_logic_vector(9060,AMPL_WIDTH),
conv_std_logic_vector(9063,AMPL_WIDTH),
conv_std_logic_vector(9066,AMPL_WIDTH),
conv_std_logic_vector(9069,AMPL_WIDTH),
conv_std_logic_vector(9072,AMPL_WIDTH),
conv_std_logic_vector(9075,AMPL_WIDTH),
conv_std_logic_vector(9078,AMPL_WIDTH),
conv_std_logic_vector(9081,AMPL_WIDTH),
conv_std_logic_vector(9084,AMPL_WIDTH),
conv_std_logic_vector(9087,AMPL_WIDTH),
conv_std_logic_vector(9090,AMPL_WIDTH),
conv_std_logic_vector(9093,AMPL_WIDTH),
conv_std_logic_vector(9096,AMPL_WIDTH),
conv_std_logic_vector(9099,AMPL_WIDTH),
conv_std_logic_vector(9102,AMPL_WIDTH),
conv_std_logic_vector(9105,AMPL_WIDTH),
conv_std_logic_vector(9108,AMPL_WIDTH),
conv_std_logic_vector(9111,AMPL_WIDTH),
conv_std_logic_vector(9114,AMPL_WIDTH),
conv_std_logic_vector(9117,AMPL_WIDTH),
conv_std_logic_vector(9120,AMPL_WIDTH),
conv_std_logic_vector(9123,AMPL_WIDTH),
conv_std_logic_vector(9126,AMPL_WIDTH),
conv_std_logic_vector(9129,AMPL_WIDTH),
conv_std_logic_vector(9132,AMPL_WIDTH),
conv_std_logic_vector(9135,AMPL_WIDTH),
conv_std_logic_vector(9138,AMPL_WIDTH),
conv_std_logic_vector(9141,AMPL_WIDTH),
conv_std_logic_vector(9144,AMPL_WIDTH),
conv_std_logic_vector(9147,AMPL_WIDTH),
conv_std_logic_vector(9150,AMPL_WIDTH),
conv_std_logic_vector(9153,AMPL_WIDTH),
conv_std_logic_vector(9156,AMPL_WIDTH),
conv_std_logic_vector(9159,AMPL_WIDTH),
conv_std_logic_vector(9162,AMPL_WIDTH),
conv_std_logic_vector(9165,AMPL_WIDTH),
conv_std_logic_vector(9168,AMPL_WIDTH),
conv_std_logic_vector(9172,AMPL_WIDTH),
conv_std_logic_vector(9175,AMPL_WIDTH),
conv_std_logic_vector(9178,AMPL_WIDTH),
conv_std_logic_vector(9181,AMPL_WIDTH),
conv_std_logic_vector(9184,AMPL_WIDTH),
conv_std_logic_vector(9187,AMPL_WIDTH),
conv_std_logic_vector(9190,AMPL_WIDTH),
conv_std_logic_vector(9193,AMPL_WIDTH),
conv_std_logic_vector(9196,AMPL_WIDTH),
conv_std_logic_vector(9199,AMPL_WIDTH),
conv_std_logic_vector(9202,AMPL_WIDTH),
conv_std_logic_vector(9205,AMPL_WIDTH),
conv_std_logic_vector(9208,AMPL_WIDTH),
conv_std_logic_vector(9211,AMPL_WIDTH),
conv_std_logic_vector(9214,AMPL_WIDTH),
conv_std_logic_vector(9217,AMPL_WIDTH),
conv_std_logic_vector(9220,AMPL_WIDTH),
conv_std_logic_vector(9223,AMPL_WIDTH),
conv_std_logic_vector(9226,AMPL_WIDTH),
conv_std_logic_vector(9229,AMPL_WIDTH),
conv_std_logic_vector(9232,AMPL_WIDTH),
conv_std_logic_vector(9235,AMPL_WIDTH),
conv_std_logic_vector(9238,AMPL_WIDTH),
conv_std_logic_vector(9241,AMPL_WIDTH),
conv_std_logic_vector(9244,AMPL_WIDTH),
conv_std_logic_vector(9247,AMPL_WIDTH),
conv_std_logic_vector(9250,AMPL_WIDTH),
conv_std_logic_vector(9253,AMPL_WIDTH),
conv_std_logic_vector(9256,AMPL_WIDTH),
conv_std_logic_vector(9259,AMPL_WIDTH),
conv_std_logic_vector(9262,AMPL_WIDTH),
conv_std_logic_vector(9265,AMPL_WIDTH),
conv_std_logic_vector(9268,AMPL_WIDTH),
conv_std_logic_vector(9271,AMPL_WIDTH),
conv_std_logic_vector(9274,AMPL_WIDTH),
conv_std_logic_vector(9277,AMPL_WIDTH),
conv_std_logic_vector(9280,AMPL_WIDTH),
conv_std_logic_vector(9283,AMPL_WIDTH),
conv_std_logic_vector(9286,AMPL_WIDTH),
conv_std_logic_vector(9289,AMPL_WIDTH),
conv_std_logic_vector(9292,AMPL_WIDTH),
conv_std_logic_vector(9295,AMPL_WIDTH),
conv_std_logic_vector(9298,AMPL_WIDTH),
conv_std_logic_vector(9301,AMPL_WIDTH),
conv_std_logic_vector(9304,AMPL_WIDTH),
conv_std_logic_vector(9307,AMPL_WIDTH),
conv_std_logic_vector(9310,AMPL_WIDTH),
conv_std_logic_vector(9313,AMPL_WIDTH),
conv_std_logic_vector(9316,AMPL_WIDTH),
conv_std_logic_vector(9319,AMPL_WIDTH),
conv_std_logic_vector(9322,AMPL_WIDTH),
conv_std_logic_vector(9325,AMPL_WIDTH),
conv_std_logic_vector(9328,AMPL_WIDTH),
conv_std_logic_vector(9331,AMPL_WIDTH),
conv_std_logic_vector(9334,AMPL_WIDTH),
conv_std_logic_vector(9337,AMPL_WIDTH),
conv_std_logic_vector(9340,AMPL_WIDTH),
conv_std_logic_vector(9343,AMPL_WIDTH),
conv_std_logic_vector(9346,AMPL_WIDTH),
conv_std_logic_vector(9349,AMPL_WIDTH),
conv_std_logic_vector(9352,AMPL_WIDTH),
conv_std_logic_vector(9355,AMPL_WIDTH),
conv_std_logic_vector(9358,AMPL_WIDTH),
conv_std_logic_vector(9361,AMPL_WIDTH),
conv_std_logic_vector(9364,AMPL_WIDTH),
conv_std_logic_vector(9367,AMPL_WIDTH),
conv_std_logic_vector(9370,AMPL_WIDTH),
conv_std_logic_vector(9373,AMPL_WIDTH),
conv_std_logic_vector(9376,AMPL_WIDTH),
conv_std_logic_vector(9379,AMPL_WIDTH),
conv_std_logic_vector(9382,AMPL_WIDTH),
conv_std_logic_vector(9385,AMPL_WIDTH),
conv_std_logic_vector(9388,AMPL_WIDTH),
conv_std_logic_vector(9391,AMPL_WIDTH),
conv_std_logic_vector(9394,AMPL_WIDTH),
conv_std_logic_vector(9397,AMPL_WIDTH),
conv_std_logic_vector(9400,AMPL_WIDTH),
conv_std_logic_vector(9403,AMPL_WIDTH),
conv_std_logic_vector(9406,AMPL_WIDTH),
conv_std_logic_vector(9409,AMPL_WIDTH),
conv_std_logic_vector(9413,AMPL_WIDTH),
conv_std_logic_vector(9416,AMPL_WIDTH),
conv_std_logic_vector(9419,AMPL_WIDTH),
conv_std_logic_vector(9422,AMPL_WIDTH),
conv_std_logic_vector(9425,AMPL_WIDTH),
conv_std_logic_vector(9428,AMPL_WIDTH),
conv_std_logic_vector(9431,AMPL_WIDTH),
conv_std_logic_vector(9434,AMPL_WIDTH),
conv_std_logic_vector(9437,AMPL_WIDTH),
conv_std_logic_vector(9440,AMPL_WIDTH),
conv_std_logic_vector(9443,AMPL_WIDTH),
conv_std_logic_vector(9446,AMPL_WIDTH),
conv_std_logic_vector(9449,AMPL_WIDTH),
conv_std_logic_vector(9452,AMPL_WIDTH),
conv_std_logic_vector(9455,AMPL_WIDTH),
conv_std_logic_vector(9458,AMPL_WIDTH),
conv_std_logic_vector(9461,AMPL_WIDTH),
conv_std_logic_vector(9464,AMPL_WIDTH),
conv_std_logic_vector(9467,AMPL_WIDTH),
conv_std_logic_vector(9470,AMPL_WIDTH),
conv_std_logic_vector(9473,AMPL_WIDTH),
conv_std_logic_vector(9476,AMPL_WIDTH),
conv_std_logic_vector(9479,AMPL_WIDTH),
conv_std_logic_vector(9482,AMPL_WIDTH),
conv_std_logic_vector(9485,AMPL_WIDTH),
conv_std_logic_vector(9488,AMPL_WIDTH),
conv_std_logic_vector(9491,AMPL_WIDTH),
conv_std_logic_vector(9494,AMPL_WIDTH),
conv_std_logic_vector(9497,AMPL_WIDTH),
conv_std_logic_vector(9500,AMPL_WIDTH),
conv_std_logic_vector(9503,AMPL_WIDTH),
conv_std_logic_vector(9506,AMPL_WIDTH),
conv_std_logic_vector(9509,AMPL_WIDTH),
conv_std_logic_vector(9512,AMPL_WIDTH),
conv_std_logic_vector(9515,AMPL_WIDTH),
conv_std_logic_vector(9518,AMPL_WIDTH),
conv_std_logic_vector(9521,AMPL_WIDTH),
conv_std_logic_vector(9524,AMPL_WIDTH),
conv_std_logic_vector(9527,AMPL_WIDTH),
conv_std_logic_vector(9530,AMPL_WIDTH),
conv_std_logic_vector(9533,AMPL_WIDTH),
conv_std_logic_vector(9536,AMPL_WIDTH),
conv_std_logic_vector(9539,AMPL_WIDTH),
conv_std_logic_vector(9542,AMPL_WIDTH),
conv_std_logic_vector(9545,AMPL_WIDTH),
conv_std_logic_vector(9548,AMPL_WIDTH),
conv_std_logic_vector(9551,AMPL_WIDTH),
conv_std_logic_vector(9554,AMPL_WIDTH),
conv_std_logic_vector(9557,AMPL_WIDTH),
conv_std_logic_vector(9560,AMPL_WIDTH),
conv_std_logic_vector(9563,AMPL_WIDTH),
conv_std_logic_vector(9566,AMPL_WIDTH),
conv_std_logic_vector(9569,AMPL_WIDTH),
conv_std_logic_vector(9572,AMPL_WIDTH),
conv_std_logic_vector(9575,AMPL_WIDTH),
conv_std_logic_vector(9578,AMPL_WIDTH),
conv_std_logic_vector(9581,AMPL_WIDTH),
conv_std_logic_vector(9584,AMPL_WIDTH),
conv_std_logic_vector(9587,AMPL_WIDTH),
conv_std_logic_vector(9590,AMPL_WIDTH),
conv_std_logic_vector(9593,AMPL_WIDTH),
conv_std_logic_vector(9596,AMPL_WIDTH),
conv_std_logic_vector(9599,AMPL_WIDTH),
conv_std_logic_vector(9602,AMPL_WIDTH),
conv_std_logic_vector(9605,AMPL_WIDTH),
conv_std_logic_vector(9608,AMPL_WIDTH),
conv_std_logic_vector(9611,AMPL_WIDTH),
conv_std_logic_vector(9614,AMPL_WIDTH),
conv_std_logic_vector(9617,AMPL_WIDTH),
conv_std_logic_vector(9620,AMPL_WIDTH),
conv_std_logic_vector(9623,AMPL_WIDTH),
conv_std_logic_vector(9626,AMPL_WIDTH),
conv_std_logic_vector(9629,AMPL_WIDTH),
conv_std_logic_vector(9632,AMPL_WIDTH),
conv_std_logic_vector(9635,AMPL_WIDTH),
conv_std_logic_vector(9638,AMPL_WIDTH),
conv_std_logic_vector(9641,AMPL_WIDTH),
conv_std_logic_vector(9644,AMPL_WIDTH),
conv_std_logic_vector(9647,AMPL_WIDTH),
conv_std_logic_vector(9650,AMPL_WIDTH),
conv_std_logic_vector(9653,AMPL_WIDTH),
conv_std_logic_vector(9656,AMPL_WIDTH),
conv_std_logic_vector(9659,AMPL_WIDTH),
conv_std_logic_vector(9662,AMPL_WIDTH),
conv_std_logic_vector(9665,AMPL_WIDTH),
conv_std_logic_vector(9668,AMPL_WIDTH),
conv_std_logic_vector(9671,AMPL_WIDTH),
conv_std_logic_vector(9674,AMPL_WIDTH),
conv_std_logic_vector(9677,AMPL_WIDTH),
conv_std_logic_vector(9680,AMPL_WIDTH),
conv_std_logic_vector(9683,AMPL_WIDTH),
conv_std_logic_vector(9686,AMPL_WIDTH),
conv_std_logic_vector(9689,AMPL_WIDTH),
conv_std_logic_vector(9692,AMPL_WIDTH),
conv_std_logic_vector(9695,AMPL_WIDTH),
conv_std_logic_vector(9698,AMPL_WIDTH),
conv_std_logic_vector(9701,AMPL_WIDTH),
conv_std_logic_vector(9704,AMPL_WIDTH),
conv_std_logic_vector(9707,AMPL_WIDTH),
conv_std_logic_vector(9710,AMPL_WIDTH),
conv_std_logic_vector(9713,AMPL_WIDTH),
conv_std_logic_vector(9716,AMPL_WIDTH),
conv_std_logic_vector(9719,AMPL_WIDTH),
conv_std_logic_vector(9722,AMPL_WIDTH),
conv_std_logic_vector(9725,AMPL_WIDTH),
conv_std_logic_vector(9728,AMPL_WIDTH),
conv_std_logic_vector(9731,AMPL_WIDTH),
conv_std_logic_vector(9734,AMPL_WIDTH),
conv_std_logic_vector(9737,AMPL_WIDTH),
conv_std_logic_vector(9740,AMPL_WIDTH),
conv_std_logic_vector(9743,AMPL_WIDTH),
conv_std_logic_vector(9746,AMPL_WIDTH),
conv_std_logic_vector(9749,AMPL_WIDTH),
conv_std_logic_vector(9752,AMPL_WIDTH),
conv_std_logic_vector(9755,AMPL_WIDTH),
conv_std_logic_vector(9758,AMPL_WIDTH),
conv_std_logic_vector(9761,AMPL_WIDTH),
conv_std_logic_vector(9764,AMPL_WIDTH),
conv_std_logic_vector(9767,AMPL_WIDTH),
conv_std_logic_vector(9770,AMPL_WIDTH),
conv_std_logic_vector(9773,AMPL_WIDTH),
conv_std_logic_vector(9776,AMPL_WIDTH),
conv_std_logic_vector(9779,AMPL_WIDTH),
conv_std_logic_vector(9782,AMPL_WIDTH),
conv_std_logic_vector(9785,AMPL_WIDTH),
conv_std_logic_vector(9788,AMPL_WIDTH),
conv_std_logic_vector(9791,AMPL_WIDTH),
conv_std_logic_vector(9794,AMPL_WIDTH),
conv_std_logic_vector(9797,AMPL_WIDTH),
conv_std_logic_vector(9800,AMPL_WIDTH),
conv_std_logic_vector(9803,AMPL_WIDTH),
conv_std_logic_vector(9806,AMPL_WIDTH),
conv_std_logic_vector(9809,AMPL_WIDTH),
conv_std_logic_vector(9812,AMPL_WIDTH),
conv_std_logic_vector(9815,AMPL_WIDTH),
conv_std_logic_vector(9818,AMPL_WIDTH),
conv_std_logic_vector(9821,AMPL_WIDTH),
conv_std_logic_vector(9824,AMPL_WIDTH),
conv_std_logic_vector(9827,AMPL_WIDTH),
conv_std_logic_vector(9830,AMPL_WIDTH),
conv_std_logic_vector(9833,AMPL_WIDTH),
conv_std_logic_vector(9836,AMPL_WIDTH),
conv_std_logic_vector(9839,AMPL_WIDTH),
conv_std_logic_vector(9842,AMPL_WIDTH),
conv_std_logic_vector(9845,AMPL_WIDTH),
conv_std_logic_vector(9848,AMPL_WIDTH),
conv_std_logic_vector(9851,AMPL_WIDTH),
conv_std_logic_vector(9854,AMPL_WIDTH),
conv_std_logic_vector(9857,AMPL_WIDTH),
conv_std_logic_vector(9860,AMPL_WIDTH),
conv_std_logic_vector(9863,AMPL_WIDTH),
conv_std_logic_vector(9866,AMPL_WIDTH),
conv_std_logic_vector(9869,AMPL_WIDTH),
conv_std_logic_vector(9872,AMPL_WIDTH),
conv_std_logic_vector(9875,AMPL_WIDTH),
conv_std_logic_vector(9878,AMPL_WIDTH),
conv_std_logic_vector(9881,AMPL_WIDTH),
conv_std_logic_vector(9884,AMPL_WIDTH),
conv_std_logic_vector(9887,AMPL_WIDTH),
conv_std_logic_vector(9890,AMPL_WIDTH),
conv_std_logic_vector(9893,AMPL_WIDTH),
conv_std_logic_vector(9896,AMPL_WIDTH),
conv_std_logic_vector(9899,AMPL_WIDTH),
conv_std_logic_vector(9902,AMPL_WIDTH),
conv_std_logic_vector(9905,AMPL_WIDTH),
conv_std_logic_vector(9908,AMPL_WIDTH),
conv_std_logic_vector(9911,AMPL_WIDTH),
conv_std_logic_vector(9914,AMPL_WIDTH),
conv_std_logic_vector(9917,AMPL_WIDTH),
conv_std_logic_vector(9920,AMPL_WIDTH),
conv_std_logic_vector(9923,AMPL_WIDTH),
conv_std_logic_vector(9926,AMPL_WIDTH),
conv_std_logic_vector(9929,AMPL_WIDTH),
conv_std_logic_vector(9932,AMPL_WIDTH),
conv_std_logic_vector(9935,AMPL_WIDTH),
conv_std_logic_vector(9938,AMPL_WIDTH),
conv_std_logic_vector(9941,AMPL_WIDTH),
conv_std_logic_vector(9944,AMPL_WIDTH),
conv_std_logic_vector(9947,AMPL_WIDTH),
conv_std_logic_vector(9950,AMPL_WIDTH),
conv_std_logic_vector(9953,AMPL_WIDTH),
conv_std_logic_vector(9956,AMPL_WIDTH),
conv_std_logic_vector(9959,AMPL_WIDTH),
conv_std_logic_vector(9962,AMPL_WIDTH),
conv_std_logic_vector(9965,AMPL_WIDTH),
conv_std_logic_vector(9968,AMPL_WIDTH),
conv_std_logic_vector(9971,AMPL_WIDTH),
conv_std_logic_vector(9974,AMPL_WIDTH),
conv_std_logic_vector(9977,AMPL_WIDTH),
conv_std_logic_vector(9980,AMPL_WIDTH),
conv_std_logic_vector(9983,AMPL_WIDTH),
conv_std_logic_vector(9986,AMPL_WIDTH),
conv_std_logic_vector(9989,AMPL_WIDTH),
conv_std_logic_vector(9992,AMPL_WIDTH),
conv_std_logic_vector(9995,AMPL_WIDTH),
conv_std_logic_vector(9998,AMPL_WIDTH),
conv_std_logic_vector(10001,AMPL_WIDTH),
conv_std_logic_vector(10004,AMPL_WIDTH),
conv_std_logic_vector(10007,AMPL_WIDTH),
conv_std_logic_vector(10010,AMPL_WIDTH),
conv_std_logic_vector(10013,AMPL_WIDTH),
conv_std_logic_vector(10016,AMPL_WIDTH),
conv_std_logic_vector(10019,AMPL_WIDTH),
conv_std_logic_vector(10022,AMPL_WIDTH),
conv_std_logic_vector(10025,AMPL_WIDTH),
conv_std_logic_vector(10028,AMPL_WIDTH),
conv_std_logic_vector(10031,AMPL_WIDTH),
conv_std_logic_vector(10033,AMPL_WIDTH),
conv_std_logic_vector(10036,AMPL_WIDTH),
conv_std_logic_vector(10039,AMPL_WIDTH),
conv_std_logic_vector(10042,AMPL_WIDTH),
conv_std_logic_vector(10045,AMPL_WIDTH),
conv_std_logic_vector(10048,AMPL_WIDTH),
conv_std_logic_vector(10051,AMPL_WIDTH),
conv_std_logic_vector(10054,AMPL_WIDTH),
conv_std_logic_vector(10057,AMPL_WIDTH),
conv_std_logic_vector(10060,AMPL_WIDTH),
conv_std_logic_vector(10063,AMPL_WIDTH),
conv_std_logic_vector(10066,AMPL_WIDTH),
conv_std_logic_vector(10069,AMPL_WIDTH),
conv_std_logic_vector(10072,AMPL_WIDTH),
conv_std_logic_vector(10075,AMPL_WIDTH),
conv_std_logic_vector(10078,AMPL_WIDTH),
conv_std_logic_vector(10081,AMPL_WIDTH),
conv_std_logic_vector(10084,AMPL_WIDTH),
conv_std_logic_vector(10087,AMPL_WIDTH),
conv_std_logic_vector(10090,AMPL_WIDTH),
conv_std_logic_vector(10093,AMPL_WIDTH),
conv_std_logic_vector(10096,AMPL_WIDTH),
conv_std_logic_vector(10099,AMPL_WIDTH),
conv_std_logic_vector(10102,AMPL_WIDTH),
conv_std_logic_vector(10105,AMPL_WIDTH),
conv_std_logic_vector(10108,AMPL_WIDTH),
conv_std_logic_vector(10111,AMPL_WIDTH),
conv_std_logic_vector(10114,AMPL_WIDTH),
conv_std_logic_vector(10117,AMPL_WIDTH),
conv_std_logic_vector(10120,AMPL_WIDTH),
conv_std_logic_vector(10123,AMPL_WIDTH),
conv_std_logic_vector(10126,AMPL_WIDTH),
conv_std_logic_vector(10129,AMPL_WIDTH),
conv_std_logic_vector(10132,AMPL_WIDTH),
conv_std_logic_vector(10135,AMPL_WIDTH),
conv_std_logic_vector(10138,AMPL_WIDTH),
conv_std_logic_vector(10141,AMPL_WIDTH),
conv_std_logic_vector(10144,AMPL_WIDTH),
conv_std_logic_vector(10147,AMPL_WIDTH),
conv_std_logic_vector(10150,AMPL_WIDTH),
conv_std_logic_vector(10153,AMPL_WIDTH),
conv_std_logic_vector(10156,AMPL_WIDTH),
conv_std_logic_vector(10159,AMPL_WIDTH),
conv_std_logic_vector(10162,AMPL_WIDTH),
conv_std_logic_vector(10165,AMPL_WIDTH),
conv_std_logic_vector(10168,AMPL_WIDTH),
conv_std_logic_vector(10171,AMPL_WIDTH),
conv_std_logic_vector(10174,AMPL_WIDTH),
conv_std_logic_vector(10177,AMPL_WIDTH),
conv_std_logic_vector(10180,AMPL_WIDTH),
conv_std_logic_vector(10183,AMPL_WIDTH),
conv_std_logic_vector(10186,AMPL_WIDTH),
conv_std_logic_vector(10189,AMPL_WIDTH),
conv_std_logic_vector(10192,AMPL_WIDTH),
conv_std_logic_vector(10195,AMPL_WIDTH),
conv_std_logic_vector(10198,AMPL_WIDTH),
conv_std_logic_vector(10201,AMPL_WIDTH),
conv_std_logic_vector(10204,AMPL_WIDTH),
conv_std_logic_vector(10207,AMPL_WIDTH),
conv_std_logic_vector(10210,AMPL_WIDTH),
conv_std_logic_vector(10213,AMPL_WIDTH),
conv_std_logic_vector(10216,AMPL_WIDTH),
conv_std_logic_vector(10219,AMPL_WIDTH),
conv_std_logic_vector(10222,AMPL_WIDTH),
conv_std_logic_vector(10225,AMPL_WIDTH),
conv_std_logic_vector(10228,AMPL_WIDTH),
conv_std_logic_vector(10231,AMPL_WIDTH),
conv_std_logic_vector(10234,AMPL_WIDTH),
conv_std_logic_vector(10237,AMPL_WIDTH),
conv_std_logic_vector(10240,AMPL_WIDTH),
conv_std_logic_vector(10243,AMPL_WIDTH),
conv_std_logic_vector(10246,AMPL_WIDTH),
conv_std_logic_vector(10249,AMPL_WIDTH),
conv_std_logic_vector(10252,AMPL_WIDTH),
conv_std_logic_vector(10255,AMPL_WIDTH),
conv_std_logic_vector(10258,AMPL_WIDTH),
conv_std_logic_vector(10261,AMPL_WIDTH),
conv_std_logic_vector(10263,AMPL_WIDTH),
conv_std_logic_vector(10266,AMPL_WIDTH),
conv_std_logic_vector(10269,AMPL_WIDTH),
conv_std_logic_vector(10272,AMPL_WIDTH),
conv_std_logic_vector(10275,AMPL_WIDTH),
conv_std_logic_vector(10278,AMPL_WIDTH),
conv_std_logic_vector(10281,AMPL_WIDTH),
conv_std_logic_vector(10284,AMPL_WIDTH),
conv_std_logic_vector(10287,AMPL_WIDTH),
conv_std_logic_vector(10290,AMPL_WIDTH),
conv_std_logic_vector(10293,AMPL_WIDTH),
conv_std_logic_vector(10296,AMPL_WIDTH),
conv_std_logic_vector(10299,AMPL_WIDTH),
conv_std_logic_vector(10302,AMPL_WIDTH),
conv_std_logic_vector(10305,AMPL_WIDTH),
conv_std_logic_vector(10308,AMPL_WIDTH),
conv_std_logic_vector(10311,AMPL_WIDTH),
conv_std_logic_vector(10314,AMPL_WIDTH),
conv_std_logic_vector(10317,AMPL_WIDTH),
conv_std_logic_vector(10320,AMPL_WIDTH),
conv_std_logic_vector(10323,AMPL_WIDTH),
conv_std_logic_vector(10326,AMPL_WIDTH),
conv_std_logic_vector(10329,AMPL_WIDTH),
conv_std_logic_vector(10332,AMPL_WIDTH),
conv_std_logic_vector(10335,AMPL_WIDTH),
conv_std_logic_vector(10338,AMPL_WIDTH),
conv_std_logic_vector(10341,AMPL_WIDTH),
conv_std_logic_vector(10344,AMPL_WIDTH),
conv_std_logic_vector(10347,AMPL_WIDTH),
conv_std_logic_vector(10350,AMPL_WIDTH),
conv_std_logic_vector(10353,AMPL_WIDTH),
conv_std_logic_vector(10356,AMPL_WIDTH),
conv_std_logic_vector(10359,AMPL_WIDTH),
conv_std_logic_vector(10362,AMPL_WIDTH),
conv_std_logic_vector(10365,AMPL_WIDTH),
conv_std_logic_vector(10368,AMPL_WIDTH),
conv_std_logic_vector(10371,AMPL_WIDTH),
conv_std_logic_vector(10374,AMPL_WIDTH),
conv_std_logic_vector(10377,AMPL_WIDTH),
conv_std_logic_vector(10380,AMPL_WIDTH),
conv_std_logic_vector(10383,AMPL_WIDTH),
conv_std_logic_vector(10386,AMPL_WIDTH),
conv_std_logic_vector(10389,AMPL_WIDTH),
conv_std_logic_vector(10392,AMPL_WIDTH),
conv_std_logic_vector(10395,AMPL_WIDTH),
conv_std_logic_vector(10398,AMPL_WIDTH),
conv_std_logic_vector(10401,AMPL_WIDTH),
conv_std_logic_vector(10404,AMPL_WIDTH),
conv_std_logic_vector(10407,AMPL_WIDTH),
conv_std_logic_vector(10410,AMPL_WIDTH),
conv_std_logic_vector(10413,AMPL_WIDTH),
conv_std_logic_vector(10416,AMPL_WIDTH),
conv_std_logic_vector(10419,AMPL_WIDTH),
conv_std_logic_vector(10421,AMPL_WIDTH),
conv_std_logic_vector(10424,AMPL_WIDTH),
conv_std_logic_vector(10427,AMPL_WIDTH),
conv_std_logic_vector(10430,AMPL_WIDTH),
conv_std_logic_vector(10433,AMPL_WIDTH),
conv_std_logic_vector(10436,AMPL_WIDTH),
conv_std_logic_vector(10439,AMPL_WIDTH),
conv_std_logic_vector(10442,AMPL_WIDTH),
conv_std_logic_vector(10445,AMPL_WIDTH),
conv_std_logic_vector(10448,AMPL_WIDTH),
conv_std_logic_vector(10451,AMPL_WIDTH),
conv_std_logic_vector(10454,AMPL_WIDTH),
conv_std_logic_vector(10457,AMPL_WIDTH),
conv_std_logic_vector(10460,AMPL_WIDTH),
conv_std_logic_vector(10463,AMPL_WIDTH),
conv_std_logic_vector(10466,AMPL_WIDTH),
conv_std_logic_vector(10469,AMPL_WIDTH),
conv_std_logic_vector(10472,AMPL_WIDTH),
conv_std_logic_vector(10475,AMPL_WIDTH),
conv_std_logic_vector(10478,AMPL_WIDTH),
conv_std_logic_vector(10481,AMPL_WIDTH),
conv_std_logic_vector(10484,AMPL_WIDTH),
conv_std_logic_vector(10487,AMPL_WIDTH),
conv_std_logic_vector(10490,AMPL_WIDTH),
conv_std_logic_vector(10493,AMPL_WIDTH),
conv_std_logic_vector(10496,AMPL_WIDTH),
conv_std_logic_vector(10499,AMPL_WIDTH),
conv_std_logic_vector(10502,AMPL_WIDTH),
conv_std_logic_vector(10505,AMPL_WIDTH),
conv_std_logic_vector(10508,AMPL_WIDTH),
conv_std_logic_vector(10511,AMPL_WIDTH),
conv_std_logic_vector(10514,AMPL_WIDTH),
conv_std_logic_vector(10517,AMPL_WIDTH),
conv_std_logic_vector(10520,AMPL_WIDTH),
conv_std_logic_vector(10523,AMPL_WIDTH),
conv_std_logic_vector(10526,AMPL_WIDTH),
conv_std_logic_vector(10529,AMPL_WIDTH),
conv_std_logic_vector(10532,AMPL_WIDTH),
conv_std_logic_vector(10535,AMPL_WIDTH),
conv_std_logic_vector(10538,AMPL_WIDTH),
conv_std_logic_vector(10541,AMPL_WIDTH),
conv_std_logic_vector(10544,AMPL_WIDTH),
conv_std_logic_vector(10546,AMPL_WIDTH),
conv_std_logic_vector(10549,AMPL_WIDTH),
conv_std_logic_vector(10552,AMPL_WIDTH),
conv_std_logic_vector(10555,AMPL_WIDTH),
conv_std_logic_vector(10558,AMPL_WIDTH),
conv_std_logic_vector(10561,AMPL_WIDTH),
conv_std_logic_vector(10564,AMPL_WIDTH),
conv_std_logic_vector(10567,AMPL_WIDTH),
conv_std_logic_vector(10570,AMPL_WIDTH),
conv_std_logic_vector(10573,AMPL_WIDTH),
conv_std_logic_vector(10576,AMPL_WIDTH),
conv_std_logic_vector(10579,AMPL_WIDTH),
conv_std_logic_vector(10582,AMPL_WIDTH),
conv_std_logic_vector(10585,AMPL_WIDTH),
conv_std_logic_vector(10588,AMPL_WIDTH),
conv_std_logic_vector(10591,AMPL_WIDTH),
conv_std_logic_vector(10594,AMPL_WIDTH),
conv_std_logic_vector(10597,AMPL_WIDTH),
conv_std_logic_vector(10600,AMPL_WIDTH),
conv_std_logic_vector(10603,AMPL_WIDTH),
conv_std_logic_vector(10606,AMPL_WIDTH),
conv_std_logic_vector(10609,AMPL_WIDTH),
conv_std_logic_vector(10612,AMPL_WIDTH),
conv_std_logic_vector(10615,AMPL_WIDTH),
conv_std_logic_vector(10618,AMPL_WIDTH),
conv_std_logic_vector(10621,AMPL_WIDTH),
conv_std_logic_vector(10624,AMPL_WIDTH),
conv_std_logic_vector(10627,AMPL_WIDTH),
conv_std_logic_vector(10630,AMPL_WIDTH),
conv_std_logic_vector(10633,AMPL_WIDTH),
conv_std_logic_vector(10636,AMPL_WIDTH),
conv_std_logic_vector(10639,AMPL_WIDTH),
conv_std_logic_vector(10642,AMPL_WIDTH),
conv_std_logic_vector(10645,AMPL_WIDTH),
conv_std_logic_vector(10648,AMPL_WIDTH),
conv_std_logic_vector(10651,AMPL_WIDTH),
conv_std_logic_vector(10654,AMPL_WIDTH),
conv_std_logic_vector(10656,AMPL_WIDTH),
conv_std_logic_vector(10659,AMPL_WIDTH),
conv_std_logic_vector(10662,AMPL_WIDTH),
conv_std_logic_vector(10665,AMPL_WIDTH),
conv_std_logic_vector(10668,AMPL_WIDTH),
conv_std_logic_vector(10671,AMPL_WIDTH),
conv_std_logic_vector(10674,AMPL_WIDTH),
conv_std_logic_vector(10677,AMPL_WIDTH),
conv_std_logic_vector(10680,AMPL_WIDTH),
conv_std_logic_vector(10683,AMPL_WIDTH),
conv_std_logic_vector(10686,AMPL_WIDTH),
conv_std_logic_vector(10689,AMPL_WIDTH),
conv_std_logic_vector(10692,AMPL_WIDTH),
conv_std_logic_vector(10695,AMPL_WIDTH),
conv_std_logic_vector(10698,AMPL_WIDTH),
conv_std_logic_vector(10701,AMPL_WIDTH),
conv_std_logic_vector(10704,AMPL_WIDTH),
conv_std_logic_vector(10707,AMPL_WIDTH),
conv_std_logic_vector(10710,AMPL_WIDTH),
conv_std_logic_vector(10713,AMPL_WIDTH),
conv_std_logic_vector(10716,AMPL_WIDTH),
conv_std_logic_vector(10719,AMPL_WIDTH),
conv_std_logic_vector(10722,AMPL_WIDTH),
conv_std_logic_vector(10725,AMPL_WIDTH),
conv_std_logic_vector(10728,AMPL_WIDTH),
conv_std_logic_vector(10731,AMPL_WIDTH),
conv_std_logic_vector(10734,AMPL_WIDTH),
conv_std_logic_vector(10737,AMPL_WIDTH),
conv_std_logic_vector(10740,AMPL_WIDTH),
conv_std_logic_vector(10743,AMPL_WIDTH),
conv_std_logic_vector(10746,AMPL_WIDTH),
conv_std_logic_vector(10749,AMPL_WIDTH),
conv_std_logic_vector(10751,AMPL_WIDTH),
conv_std_logic_vector(10754,AMPL_WIDTH),
conv_std_logic_vector(10757,AMPL_WIDTH),
conv_std_logic_vector(10760,AMPL_WIDTH),
conv_std_logic_vector(10763,AMPL_WIDTH),
conv_std_logic_vector(10766,AMPL_WIDTH),
conv_std_logic_vector(10769,AMPL_WIDTH),
conv_std_logic_vector(10772,AMPL_WIDTH),
conv_std_logic_vector(10775,AMPL_WIDTH),
conv_std_logic_vector(10778,AMPL_WIDTH),
conv_std_logic_vector(10781,AMPL_WIDTH),
conv_std_logic_vector(10784,AMPL_WIDTH),
conv_std_logic_vector(10787,AMPL_WIDTH),
conv_std_logic_vector(10790,AMPL_WIDTH),
conv_std_logic_vector(10793,AMPL_WIDTH),
conv_std_logic_vector(10796,AMPL_WIDTH),
conv_std_logic_vector(10799,AMPL_WIDTH),
conv_std_logic_vector(10802,AMPL_WIDTH),
conv_std_logic_vector(10805,AMPL_WIDTH),
conv_std_logic_vector(10808,AMPL_WIDTH),
conv_std_logic_vector(10811,AMPL_WIDTH),
conv_std_logic_vector(10814,AMPL_WIDTH),
conv_std_logic_vector(10817,AMPL_WIDTH),
conv_std_logic_vector(10820,AMPL_WIDTH),
conv_std_logic_vector(10823,AMPL_WIDTH),
conv_std_logic_vector(10826,AMPL_WIDTH),
conv_std_logic_vector(10829,AMPL_WIDTH),
conv_std_logic_vector(10832,AMPL_WIDTH),
conv_std_logic_vector(10835,AMPL_WIDTH),
conv_std_logic_vector(10838,AMPL_WIDTH),
conv_std_logic_vector(10840,AMPL_WIDTH),
conv_std_logic_vector(10843,AMPL_WIDTH),
conv_std_logic_vector(10846,AMPL_WIDTH),
conv_std_logic_vector(10849,AMPL_WIDTH),
conv_std_logic_vector(10852,AMPL_WIDTH),
conv_std_logic_vector(10855,AMPL_WIDTH),
conv_std_logic_vector(10858,AMPL_WIDTH),
conv_std_logic_vector(10861,AMPL_WIDTH),
conv_std_logic_vector(10864,AMPL_WIDTH),
conv_std_logic_vector(10867,AMPL_WIDTH),
conv_std_logic_vector(10870,AMPL_WIDTH),
conv_std_logic_vector(10873,AMPL_WIDTH),
conv_std_logic_vector(10876,AMPL_WIDTH),
conv_std_logic_vector(10879,AMPL_WIDTH),
conv_std_logic_vector(10882,AMPL_WIDTH),
conv_std_logic_vector(10885,AMPL_WIDTH),
conv_std_logic_vector(10888,AMPL_WIDTH),
conv_std_logic_vector(10891,AMPL_WIDTH),
conv_std_logic_vector(10894,AMPL_WIDTH),
conv_std_logic_vector(10897,AMPL_WIDTH),
conv_std_logic_vector(10900,AMPL_WIDTH),
conv_std_logic_vector(10903,AMPL_WIDTH),
conv_std_logic_vector(10906,AMPL_WIDTH),
conv_std_logic_vector(10909,AMPL_WIDTH),
conv_std_logic_vector(10912,AMPL_WIDTH),
conv_std_logic_vector(10915,AMPL_WIDTH),
conv_std_logic_vector(10918,AMPL_WIDTH),
conv_std_logic_vector(10920,AMPL_WIDTH),
conv_std_logic_vector(10923,AMPL_WIDTH),
conv_std_logic_vector(10926,AMPL_WIDTH),
conv_std_logic_vector(10929,AMPL_WIDTH),
conv_std_logic_vector(10932,AMPL_WIDTH),
conv_std_logic_vector(10935,AMPL_WIDTH),
conv_std_logic_vector(10938,AMPL_WIDTH),
conv_std_logic_vector(10941,AMPL_WIDTH),
conv_std_logic_vector(10944,AMPL_WIDTH),
conv_std_logic_vector(10947,AMPL_WIDTH),
conv_std_logic_vector(10950,AMPL_WIDTH),
conv_std_logic_vector(10953,AMPL_WIDTH),
conv_std_logic_vector(10956,AMPL_WIDTH),
conv_std_logic_vector(10959,AMPL_WIDTH),
conv_std_logic_vector(10962,AMPL_WIDTH),
conv_std_logic_vector(10965,AMPL_WIDTH),
conv_std_logic_vector(10968,AMPL_WIDTH),
conv_std_logic_vector(10971,AMPL_WIDTH),
conv_std_logic_vector(10974,AMPL_WIDTH),
conv_std_logic_vector(10977,AMPL_WIDTH),
conv_std_logic_vector(10980,AMPL_WIDTH),
conv_std_logic_vector(10983,AMPL_WIDTH),
conv_std_logic_vector(10986,AMPL_WIDTH),
conv_std_logic_vector(10989,AMPL_WIDTH),
conv_std_logic_vector(10992,AMPL_WIDTH),
conv_std_logic_vector(10994,AMPL_WIDTH),
conv_std_logic_vector(10997,AMPL_WIDTH),
conv_std_logic_vector(11000,AMPL_WIDTH),
conv_std_logic_vector(11003,AMPL_WIDTH),
conv_std_logic_vector(11006,AMPL_WIDTH),
conv_std_logic_vector(11009,AMPL_WIDTH),
conv_std_logic_vector(11012,AMPL_WIDTH),
conv_std_logic_vector(11015,AMPL_WIDTH),
conv_std_logic_vector(11018,AMPL_WIDTH),
conv_std_logic_vector(11021,AMPL_WIDTH),
conv_std_logic_vector(11024,AMPL_WIDTH),
conv_std_logic_vector(11027,AMPL_WIDTH),
conv_std_logic_vector(11030,AMPL_WIDTH),
conv_std_logic_vector(11033,AMPL_WIDTH),
conv_std_logic_vector(11036,AMPL_WIDTH),
conv_std_logic_vector(11039,AMPL_WIDTH),
conv_std_logic_vector(11042,AMPL_WIDTH),
conv_std_logic_vector(11045,AMPL_WIDTH),
conv_std_logic_vector(11048,AMPL_WIDTH),
conv_std_logic_vector(11051,AMPL_WIDTH),
conv_std_logic_vector(11054,AMPL_WIDTH),
conv_std_logic_vector(11057,AMPL_WIDTH),
conv_std_logic_vector(11060,AMPL_WIDTH),
conv_std_logic_vector(11063,AMPL_WIDTH),
conv_std_logic_vector(11065,AMPL_WIDTH),
conv_std_logic_vector(11068,AMPL_WIDTH),
conv_std_logic_vector(11071,AMPL_WIDTH),
conv_std_logic_vector(11074,AMPL_WIDTH),
conv_std_logic_vector(11077,AMPL_WIDTH),
conv_std_logic_vector(11080,AMPL_WIDTH),
conv_std_logic_vector(11083,AMPL_WIDTH),
conv_std_logic_vector(11086,AMPL_WIDTH),
conv_std_logic_vector(11089,AMPL_WIDTH),
conv_std_logic_vector(11092,AMPL_WIDTH),
conv_std_logic_vector(11095,AMPL_WIDTH),
conv_std_logic_vector(11098,AMPL_WIDTH),
conv_std_logic_vector(11101,AMPL_WIDTH),
conv_std_logic_vector(11104,AMPL_WIDTH),
conv_std_logic_vector(11107,AMPL_WIDTH),
conv_std_logic_vector(11110,AMPL_WIDTH),
conv_std_logic_vector(11113,AMPL_WIDTH),
conv_std_logic_vector(11116,AMPL_WIDTH),
conv_std_logic_vector(11119,AMPL_WIDTH),
conv_std_logic_vector(11122,AMPL_WIDTH),
conv_std_logic_vector(11125,AMPL_WIDTH),
conv_std_logic_vector(11128,AMPL_WIDTH),
conv_std_logic_vector(11131,AMPL_WIDTH),
conv_std_logic_vector(11133,AMPL_WIDTH),
conv_std_logic_vector(11136,AMPL_WIDTH),
conv_std_logic_vector(11139,AMPL_WIDTH),
conv_std_logic_vector(11142,AMPL_WIDTH),
conv_std_logic_vector(11145,AMPL_WIDTH),
conv_std_logic_vector(11148,AMPL_WIDTH),
conv_std_logic_vector(11151,AMPL_WIDTH),
conv_std_logic_vector(11154,AMPL_WIDTH),
conv_std_logic_vector(11157,AMPL_WIDTH),
conv_std_logic_vector(11160,AMPL_WIDTH),
conv_std_logic_vector(11163,AMPL_WIDTH),
conv_std_logic_vector(11166,AMPL_WIDTH),
conv_std_logic_vector(11169,AMPL_WIDTH),
conv_std_logic_vector(11172,AMPL_WIDTH),
conv_std_logic_vector(11175,AMPL_WIDTH),
conv_std_logic_vector(11178,AMPL_WIDTH),
conv_std_logic_vector(11181,AMPL_WIDTH),
conv_std_logic_vector(11184,AMPL_WIDTH),
conv_std_logic_vector(11187,AMPL_WIDTH),
conv_std_logic_vector(11190,AMPL_WIDTH),
conv_std_logic_vector(11193,AMPL_WIDTH),
conv_std_logic_vector(11195,AMPL_WIDTH),
conv_std_logic_vector(11198,AMPL_WIDTH),
conv_std_logic_vector(11201,AMPL_WIDTH),
conv_std_logic_vector(11204,AMPL_WIDTH),
conv_std_logic_vector(11207,AMPL_WIDTH),
conv_std_logic_vector(11210,AMPL_WIDTH),
conv_std_logic_vector(11213,AMPL_WIDTH),
conv_std_logic_vector(11216,AMPL_WIDTH),
conv_std_logic_vector(11219,AMPL_WIDTH),
conv_std_logic_vector(11222,AMPL_WIDTH),
conv_std_logic_vector(11225,AMPL_WIDTH),
conv_std_logic_vector(11228,AMPL_WIDTH),
conv_std_logic_vector(11231,AMPL_WIDTH),
conv_std_logic_vector(11234,AMPL_WIDTH),
conv_std_logic_vector(11237,AMPL_WIDTH),
conv_std_logic_vector(11240,AMPL_WIDTH),
conv_std_logic_vector(11243,AMPL_WIDTH),
conv_std_logic_vector(11246,AMPL_WIDTH),
conv_std_logic_vector(11249,AMPL_WIDTH),
conv_std_logic_vector(11252,AMPL_WIDTH),
conv_std_logic_vector(11255,AMPL_WIDTH),
conv_std_logic_vector(11257,AMPL_WIDTH),
conv_std_logic_vector(11260,AMPL_WIDTH),
conv_std_logic_vector(11263,AMPL_WIDTH),
conv_std_logic_vector(11266,AMPL_WIDTH),
conv_std_logic_vector(11269,AMPL_WIDTH),
conv_std_logic_vector(11272,AMPL_WIDTH),
conv_std_logic_vector(11275,AMPL_WIDTH),
conv_std_logic_vector(11278,AMPL_WIDTH),
conv_std_logic_vector(11281,AMPL_WIDTH),
conv_std_logic_vector(11284,AMPL_WIDTH),
conv_std_logic_vector(11287,AMPL_WIDTH),
conv_std_logic_vector(11290,AMPL_WIDTH),
conv_std_logic_vector(11293,AMPL_WIDTH),
conv_std_logic_vector(11296,AMPL_WIDTH),
conv_std_logic_vector(11299,AMPL_WIDTH),
conv_std_logic_vector(11302,AMPL_WIDTH),
conv_std_logic_vector(11305,AMPL_WIDTH),
conv_std_logic_vector(11308,AMPL_WIDTH),
conv_std_logic_vector(11311,AMPL_WIDTH),
conv_std_logic_vector(11314,AMPL_WIDTH),
conv_std_logic_vector(11316,AMPL_WIDTH),
conv_std_logic_vector(11319,AMPL_WIDTH),
conv_std_logic_vector(11322,AMPL_WIDTH),
conv_std_logic_vector(11325,AMPL_WIDTH),
conv_std_logic_vector(11328,AMPL_WIDTH),
conv_std_logic_vector(11331,AMPL_WIDTH),
conv_std_logic_vector(11334,AMPL_WIDTH),
conv_std_logic_vector(11337,AMPL_WIDTH),
conv_std_logic_vector(11340,AMPL_WIDTH),
conv_std_logic_vector(11343,AMPL_WIDTH),
conv_std_logic_vector(11346,AMPL_WIDTH),
conv_std_logic_vector(11349,AMPL_WIDTH),
conv_std_logic_vector(11352,AMPL_WIDTH),
conv_std_logic_vector(11355,AMPL_WIDTH),
conv_std_logic_vector(11358,AMPL_WIDTH),
conv_std_logic_vector(11361,AMPL_WIDTH),
conv_std_logic_vector(11364,AMPL_WIDTH),
conv_std_logic_vector(11367,AMPL_WIDTH),
conv_std_logic_vector(11370,AMPL_WIDTH),
conv_std_logic_vector(11372,AMPL_WIDTH),
conv_std_logic_vector(11375,AMPL_WIDTH),
conv_std_logic_vector(11378,AMPL_WIDTH),
conv_std_logic_vector(11381,AMPL_WIDTH),
conv_std_logic_vector(11384,AMPL_WIDTH),
conv_std_logic_vector(11387,AMPL_WIDTH),
conv_std_logic_vector(11390,AMPL_WIDTH),
conv_std_logic_vector(11393,AMPL_WIDTH),
conv_std_logic_vector(11396,AMPL_WIDTH),
conv_std_logic_vector(11399,AMPL_WIDTH),
conv_std_logic_vector(11402,AMPL_WIDTH),
conv_std_logic_vector(11405,AMPL_WIDTH),
conv_std_logic_vector(11408,AMPL_WIDTH),
conv_std_logic_vector(11411,AMPL_WIDTH),
conv_std_logic_vector(11414,AMPL_WIDTH),
conv_std_logic_vector(11417,AMPL_WIDTH),
conv_std_logic_vector(11420,AMPL_WIDTH),
conv_std_logic_vector(11423,AMPL_WIDTH),
conv_std_logic_vector(11425,AMPL_WIDTH),
conv_std_logic_vector(11428,AMPL_WIDTH),
conv_std_logic_vector(11431,AMPL_WIDTH),
conv_std_logic_vector(11434,AMPL_WIDTH),
conv_std_logic_vector(11437,AMPL_WIDTH),
conv_std_logic_vector(11440,AMPL_WIDTH),
conv_std_logic_vector(11443,AMPL_WIDTH),
conv_std_logic_vector(11446,AMPL_WIDTH),
conv_std_logic_vector(11449,AMPL_WIDTH),
conv_std_logic_vector(11452,AMPL_WIDTH),
conv_std_logic_vector(11455,AMPL_WIDTH),
conv_std_logic_vector(11458,AMPL_WIDTH),
conv_std_logic_vector(11461,AMPL_WIDTH),
conv_std_logic_vector(11464,AMPL_WIDTH),
conv_std_logic_vector(11467,AMPL_WIDTH),
conv_std_logic_vector(11470,AMPL_WIDTH),
conv_std_logic_vector(11473,AMPL_WIDTH),
conv_std_logic_vector(11476,AMPL_WIDTH),
conv_std_logic_vector(11478,AMPL_WIDTH),
conv_std_logic_vector(11481,AMPL_WIDTH),
conv_std_logic_vector(11484,AMPL_WIDTH),
conv_std_logic_vector(11487,AMPL_WIDTH),
conv_std_logic_vector(11490,AMPL_WIDTH),
conv_std_logic_vector(11493,AMPL_WIDTH),
conv_std_logic_vector(11496,AMPL_WIDTH),
conv_std_logic_vector(11499,AMPL_WIDTH),
conv_std_logic_vector(11502,AMPL_WIDTH),
conv_std_logic_vector(11505,AMPL_WIDTH),
conv_std_logic_vector(11508,AMPL_WIDTH),
conv_std_logic_vector(11511,AMPL_WIDTH),
conv_std_logic_vector(11514,AMPL_WIDTH),
conv_std_logic_vector(11517,AMPL_WIDTH),
conv_std_logic_vector(11520,AMPL_WIDTH),
conv_std_logic_vector(11523,AMPL_WIDTH),
conv_std_logic_vector(11526,AMPL_WIDTH),
conv_std_logic_vector(11528,AMPL_WIDTH),
conv_std_logic_vector(11531,AMPL_WIDTH),
conv_std_logic_vector(11534,AMPL_WIDTH),
conv_std_logic_vector(11537,AMPL_WIDTH),
conv_std_logic_vector(11540,AMPL_WIDTH),
conv_std_logic_vector(11543,AMPL_WIDTH),
conv_std_logic_vector(11546,AMPL_WIDTH),
conv_std_logic_vector(11549,AMPL_WIDTH),
conv_std_logic_vector(11552,AMPL_WIDTH),
conv_std_logic_vector(11555,AMPL_WIDTH),
conv_std_logic_vector(11558,AMPL_WIDTH),
conv_std_logic_vector(11561,AMPL_WIDTH),
conv_std_logic_vector(11564,AMPL_WIDTH),
conv_std_logic_vector(11567,AMPL_WIDTH),
conv_std_logic_vector(11570,AMPL_WIDTH),
conv_std_logic_vector(11573,AMPL_WIDTH),
conv_std_logic_vector(11575,AMPL_WIDTH),
conv_std_logic_vector(11578,AMPL_WIDTH),
conv_std_logic_vector(11581,AMPL_WIDTH),
conv_std_logic_vector(11584,AMPL_WIDTH),
conv_std_logic_vector(11587,AMPL_WIDTH),
conv_std_logic_vector(11590,AMPL_WIDTH),
conv_std_logic_vector(11593,AMPL_WIDTH),
conv_std_logic_vector(11596,AMPL_WIDTH),
conv_std_logic_vector(11599,AMPL_WIDTH),
conv_std_logic_vector(11602,AMPL_WIDTH),
conv_std_logic_vector(11605,AMPL_WIDTH),
conv_std_logic_vector(11608,AMPL_WIDTH),
conv_std_logic_vector(11611,AMPL_WIDTH),
conv_std_logic_vector(11614,AMPL_WIDTH),
conv_std_logic_vector(11617,AMPL_WIDTH),
conv_std_logic_vector(11620,AMPL_WIDTH),
conv_std_logic_vector(11623,AMPL_WIDTH),
conv_std_logic_vector(11625,AMPL_WIDTH),
conv_std_logic_vector(11628,AMPL_WIDTH),
conv_std_logic_vector(11631,AMPL_WIDTH),
conv_std_logic_vector(11634,AMPL_WIDTH),
conv_std_logic_vector(11637,AMPL_WIDTH),
conv_std_logic_vector(11640,AMPL_WIDTH),
conv_std_logic_vector(11643,AMPL_WIDTH),
conv_std_logic_vector(11646,AMPL_WIDTH),
conv_std_logic_vector(11649,AMPL_WIDTH),
conv_std_logic_vector(11652,AMPL_WIDTH),
conv_std_logic_vector(11655,AMPL_WIDTH),
conv_std_logic_vector(11658,AMPL_WIDTH),
conv_std_logic_vector(11661,AMPL_WIDTH),
conv_std_logic_vector(11664,AMPL_WIDTH),
conv_std_logic_vector(11667,AMPL_WIDTH),
conv_std_logic_vector(11669,AMPL_WIDTH),
conv_std_logic_vector(11672,AMPL_WIDTH),
conv_std_logic_vector(11675,AMPL_WIDTH),
conv_std_logic_vector(11678,AMPL_WIDTH),
conv_std_logic_vector(11681,AMPL_WIDTH),
conv_std_logic_vector(11684,AMPL_WIDTH),
conv_std_logic_vector(11687,AMPL_WIDTH),
conv_std_logic_vector(11690,AMPL_WIDTH),
conv_std_logic_vector(11693,AMPL_WIDTH),
conv_std_logic_vector(11696,AMPL_WIDTH),
conv_std_logic_vector(11699,AMPL_WIDTH),
conv_std_logic_vector(11702,AMPL_WIDTH),
conv_std_logic_vector(11705,AMPL_WIDTH),
conv_std_logic_vector(11708,AMPL_WIDTH),
conv_std_logic_vector(11711,AMPL_WIDTH),
conv_std_logic_vector(11714,AMPL_WIDTH),
conv_std_logic_vector(11716,AMPL_WIDTH),
conv_std_logic_vector(11719,AMPL_WIDTH),
conv_std_logic_vector(11722,AMPL_WIDTH),
conv_std_logic_vector(11725,AMPL_WIDTH),
conv_std_logic_vector(11728,AMPL_WIDTH),
conv_std_logic_vector(11731,AMPL_WIDTH),
conv_std_logic_vector(11734,AMPL_WIDTH),
conv_std_logic_vector(11737,AMPL_WIDTH),
conv_std_logic_vector(11740,AMPL_WIDTH),
conv_std_logic_vector(11743,AMPL_WIDTH),
conv_std_logic_vector(11746,AMPL_WIDTH),
conv_std_logic_vector(11749,AMPL_WIDTH),
conv_std_logic_vector(11752,AMPL_WIDTH),
conv_std_logic_vector(11755,AMPL_WIDTH),
conv_std_logic_vector(11758,AMPL_WIDTH),
conv_std_logic_vector(11760,AMPL_WIDTH),
conv_std_logic_vector(11763,AMPL_WIDTH),
conv_std_logic_vector(11766,AMPL_WIDTH),
conv_std_logic_vector(11769,AMPL_WIDTH),
conv_std_logic_vector(11772,AMPL_WIDTH),
conv_std_logic_vector(11775,AMPL_WIDTH),
conv_std_logic_vector(11778,AMPL_WIDTH),
conv_std_logic_vector(11781,AMPL_WIDTH),
conv_std_logic_vector(11784,AMPL_WIDTH),
conv_std_logic_vector(11787,AMPL_WIDTH),
conv_std_logic_vector(11790,AMPL_WIDTH),
conv_std_logic_vector(11793,AMPL_WIDTH),
conv_std_logic_vector(11796,AMPL_WIDTH),
conv_std_logic_vector(11799,AMPL_WIDTH),
conv_std_logic_vector(11801,AMPL_WIDTH),
conv_std_logic_vector(11804,AMPL_WIDTH),
conv_std_logic_vector(11807,AMPL_WIDTH),
conv_std_logic_vector(11810,AMPL_WIDTH),
conv_std_logic_vector(11813,AMPL_WIDTH),
conv_std_logic_vector(11816,AMPL_WIDTH),
conv_std_logic_vector(11819,AMPL_WIDTH),
conv_std_logic_vector(11822,AMPL_WIDTH),
conv_std_logic_vector(11825,AMPL_WIDTH),
conv_std_logic_vector(11828,AMPL_WIDTH),
conv_std_logic_vector(11831,AMPL_WIDTH),
conv_std_logic_vector(11834,AMPL_WIDTH),
conv_std_logic_vector(11837,AMPL_WIDTH),
conv_std_logic_vector(11840,AMPL_WIDTH),
conv_std_logic_vector(11842,AMPL_WIDTH),
conv_std_logic_vector(11845,AMPL_WIDTH),
conv_std_logic_vector(11848,AMPL_WIDTH),
conv_std_logic_vector(11851,AMPL_WIDTH),
conv_std_logic_vector(11854,AMPL_WIDTH),
conv_std_logic_vector(11857,AMPL_WIDTH),
conv_std_logic_vector(11860,AMPL_WIDTH),
conv_std_logic_vector(11863,AMPL_WIDTH),
conv_std_logic_vector(11866,AMPL_WIDTH),
conv_std_logic_vector(11869,AMPL_WIDTH),
conv_std_logic_vector(11872,AMPL_WIDTH),
conv_std_logic_vector(11875,AMPL_WIDTH),
conv_std_logic_vector(11878,AMPL_WIDTH),
conv_std_logic_vector(11881,AMPL_WIDTH),
conv_std_logic_vector(11883,AMPL_WIDTH),
conv_std_logic_vector(11886,AMPL_WIDTH),
conv_std_logic_vector(11889,AMPL_WIDTH),
conv_std_logic_vector(11892,AMPL_WIDTH),
conv_std_logic_vector(11895,AMPL_WIDTH),
conv_std_logic_vector(11898,AMPL_WIDTH),
conv_std_logic_vector(11901,AMPL_WIDTH),
conv_std_logic_vector(11904,AMPL_WIDTH),
conv_std_logic_vector(11907,AMPL_WIDTH),
conv_std_logic_vector(11910,AMPL_WIDTH),
conv_std_logic_vector(11913,AMPL_WIDTH),
conv_std_logic_vector(11916,AMPL_WIDTH),
conv_std_logic_vector(11919,AMPL_WIDTH),
conv_std_logic_vector(11922,AMPL_WIDTH),
conv_std_logic_vector(11924,AMPL_WIDTH),
conv_std_logic_vector(11927,AMPL_WIDTH),
conv_std_logic_vector(11930,AMPL_WIDTH),
conv_std_logic_vector(11933,AMPL_WIDTH),
conv_std_logic_vector(11936,AMPL_WIDTH),
conv_std_logic_vector(11939,AMPL_WIDTH),
conv_std_logic_vector(11942,AMPL_WIDTH),
conv_std_logic_vector(11945,AMPL_WIDTH),
conv_std_logic_vector(11948,AMPL_WIDTH),
conv_std_logic_vector(11951,AMPL_WIDTH),
conv_std_logic_vector(11954,AMPL_WIDTH),
conv_std_logic_vector(11957,AMPL_WIDTH),
conv_std_logic_vector(11960,AMPL_WIDTH),
conv_std_logic_vector(11962,AMPL_WIDTH),
conv_std_logic_vector(11965,AMPL_WIDTH),
conv_std_logic_vector(11968,AMPL_WIDTH),
conv_std_logic_vector(11971,AMPL_WIDTH),
conv_std_logic_vector(11974,AMPL_WIDTH),
conv_std_logic_vector(11977,AMPL_WIDTH),
conv_std_logic_vector(11980,AMPL_WIDTH),
conv_std_logic_vector(11983,AMPL_WIDTH),
conv_std_logic_vector(11986,AMPL_WIDTH),
conv_std_logic_vector(11989,AMPL_WIDTH),
conv_std_logic_vector(11992,AMPL_WIDTH),
conv_std_logic_vector(11995,AMPL_WIDTH),
conv_std_logic_vector(11998,AMPL_WIDTH),
conv_std_logic_vector(12001,AMPL_WIDTH),
conv_std_logic_vector(12003,AMPL_WIDTH),
conv_std_logic_vector(12006,AMPL_WIDTH),
conv_std_logic_vector(12009,AMPL_WIDTH),
conv_std_logic_vector(12012,AMPL_WIDTH),
conv_std_logic_vector(12015,AMPL_WIDTH),
conv_std_logic_vector(12018,AMPL_WIDTH),
conv_std_logic_vector(12021,AMPL_WIDTH),
conv_std_logic_vector(12024,AMPL_WIDTH),
conv_std_logic_vector(12027,AMPL_WIDTH),
conv_std_logic_vector(12030,AMPL_WIDTH),
conv_std_logic_vector(12033,AMPL_WIDTH),
conv_std_logic_vector(12036,AMPL_WIDTH),
conv_std_logic_vector(12038,AMPL_WIDTH),
conv_std_logic_vector(12041,AMPL_WIDTH),
conv_std_logic_vector(12044,AMPL_WIDTH),
conv_std_logic_vector(12047,AMPL_WIDTH),
conv_std_logic_vector(12050,AMPL_WIDTH),
conv_std_logic_vector(12053,AMPL_WIDTH),
conv_std_logic_vector(12056,AMPL_WIDTH),
conv_std_logic_vector(12059,AMPL_WIDTH),
conv_std_logic_vector(12062,AMPL_WIDTH),
conv_std_logic_vector(12065,AMPL_WIDTH),
conv_std_logic_vector(12068,AMPL_WIDTH),
conv_std_logic_vector(12071,AMPL_WIDTH),
conv_std_logic_vector(12074,AMPL_WIDTH),
conv_std_logic_vector(12076,AMPL_WIDTH),
conv_std_logic_vector(12079,AMPL_WIDTH),
conv_std_logic_vector(12082,AMPL_WIDTH),
conv_std_logic_vector(12085,AMPL_WIDTH),
conv_std_logic_vector(12088,AMPL_WIDTH),
conv_std_logic_vector(12091,AMPL_WIDTH),
conv_std_logic_vector(12094,AMPL_WIDTH),
conv_std_logic_vector(12097,AMPL_WIDTH),
conv_std_logic_vector(12100,AMPL_WIDTH),
conv_std_logic_vector(12103,AMPL_WIDTH),
conv_std_logic_vector(12106,AMPL_WIDTH),
conv_std_logic_vector(12109,AMPL_WIDTH),
conv_std_logic_vector(12112,AMPL_WIDTH),
conv_std_logic_vector(12114,AMPL_WIDTH),
conv_std_logic_vector(12117,AMPL_WIDTH),
conv_std_logic_vector(12120,AMPL_WIDTH),
conv_std_logic_vector(12123,AMPL_WIDTH),
conv_std_logic_vector(12126,AMPL_WIDTH),
conv_std_logic_vector(12129,AMPL_WIDTH),
conv_std_logic_vector(12132,AMPL_WIDTH),
conv_std_logic_vector(12135,AMPL_WIDTH),
conv_std_logic_vector(12138,AMPL_WIDTH),
conv_std_logic_vector(12141,AMPL_WIDTH),
conv_std_logic_vector(12144,AMPL_WIDTH),
conv_std_logic_vector(12147,AMPL_WIDTH),
conv_std_logic_vector(12149,AMPL_WIDTH),
conv_std_logic_vector(12152,AMPL_WIDTH),
conv_std_logic_vector(12155,AMPL_WIDTH),
conv_std_logic_vector(12158,AMPL_WIDTH),
conv_std_logic_vector(12161,AMPL_WIDTH),
conv_std_logic_vector(12164,AMPL_WIDTH),
conv_std_logic_vector(12167,AMPL_WIDTH),
conv_std_logic_vector(12170,AMPL_WIDTH),
conv_std_logic_vector(12173,AMPL_WIDTH),
conv_std_logic_vector(12176,AMPL_WIDTH),
conv_std_logic_vector(12179,AMPL_WIDTH),
conv_std_logic_vector(12182,AMPL_WIDTH),
conv_std_logic_vector(12184,AMPL_WIDTH),
conv_std_logic_vector(12187,AMPL_WIDTH),
conv_std_logic_vector(12190,AMPL_WIDTH),
conv_std_logic_vector(12193,AMPL_WIDTH),
conv_std_logic_vector(12196,AMPL_WIDTH),
conv_std_logic_vector(12199,AMPL_WIDTH),
conv_std_logic_vector(12202,AMPL_WIDTH),
conv_std_logic_vector(12205,AMPL_WIDTH),
conv_std_logic_vector(12208,AMPL_WIDTH),
conv_std_logic_vector(12211,AMPL_WIDTH),
conv_std_logic_vector(12214,AMPL_WIDTH),
conv_std_logic_vector(12217,AMPL_WIDTH),
conv_std_logic_vector(12219,AMPL_WIDTH),
conv_std_logic_vector(12222,AMPL_WIDTH),
conv_std_logic_vector(12225,AMPL_WIDTH),
conv_std_logic_vector(12228,AMPL_WIDTH),
conv_std_logic_vector(12231,AMPL_WIDTH),
conv_std_logic_vector(12234,AMPL_WIDTH),
conv_std_logic_vector(12237,AMPL_WIDTH),
conv_std_logic_vector(12240,AMPL_WIDTH),
conv_std_logic_vector(12243,AMPL_WIDTH),
conv_std_logic_vector(12246,AMPL_WIDTH),
conv_std_logic_vector(12249,AMPL_WIDTH),
conv_std_logic_vector(12251,AMPL_WIDTH),
conv_std_logic_vector(12254,AMPL_WIDTH),
conv_std_logic_vector(12257,AMPL_WIDTH),
conv_std_logic_vector(12260,AMPL_WIDTH),
conv_std_logic_vector(12263,AMPL_WIDTH),
conv_std_logic_vector(12266,AMPL_WIDTH),
conv_std_logic_vector(12269,AMPL_WIDTH),
conv_std_logic_vector(12272,AMPL_WIDTH),
conv_std_logic_vector(12275,AMPL_WIDTH),
conv_std_logic_vector(12278,AMPL_WIDTH),
conv_std_logic_vector(12281,AMPL_WIDTH),
conv_std_logic_vector(12284,AMPL_WIDTH),
conv_std_logic_vector(12286,AMPL_WIDTH),
conv_std_logic_vector(12289,AMPL_WIDTH),
conv_std_logic_vector(12292,AMPL_WIDTH),
conv_std_logic_vector(12295,AMPL_WIDTH),
conv_std_logic_vector(12298,AMPL_WIDTH),
conv_std_logic_vector(12301,AMPL_WIDTH),
conv_std_logic_vector(12304,AMPL_WIDTH),
conv_std_logic_vector(12307,AMPL_WIDTH),
conv_std_logic_vector(12310,AMPL_WIDTH),
conv_std_logic_vector(12313,AMPL_WIDTH),
conv_std_logic_vector(12316,AMPL_WIDTH),
conv_std_logic_vector(12318,AMPL_WIDTH),
conv_std_logic_vector(12321,AMPL_WIDTH),
conv_std_logic_vector(12324,AMPL_WIDTH),
conv_std_logic_vector(12327,AMPL_WIDTH),
conv_std_logic_vector(12330,AMPL_WIDTH),
conv_std_logic_vector(12333,AMPL_WIDTH),
conv_std_logic_vector(12336,AMPL_WIDTH),
conv_std_logic_vector(12339,AMPL_WIDTH),
conv_std_logic_vector(12342,AMPL_WIDTH),
conv_std_logic_vector(12345,AMPL_WIDTH),
conv_std_logic_vector(12348,AMPL_WIDTH),
conv_std_logic_vector(12350,AMPL_WIDTH),
conv_std_logic_vector(12353,AMPL_WIDTH),
conv_std_logic_vector(12356,AMPL_WIDTH),
conv_std_logic_vector(12359,AMPL_WIDTH),
conv_std_logic_vector(12362,AMPL_WIDTH),
conv_std_logic_vector(12365,AMPL_WIDTH),
conv_std_logic_vector(12368,AMPL_WIDTH),
conv_std_logic_vector(12371,AMPL_WIDTH),
conv_std_logic_vector(12374,AMPL_WIDTH),
conv_std_logic_vector(12377,AMPL_WIDTH),
conv_std_logic_vector(12380,AMPL_WIDTH),
conv_std_logic_vector(12382,AMPL_WIDTH),
conv_std_logic_vector(12385,AMPL_WIDTH),
conv_std_logic_vector(12388,AMPL_WIDTH),
conv_std_logic_vector(12391,AMPL_WIDTH),
conv_std_logic_vector(12394,AMPL_WIDTH),
conv_std_logic_vector(12397,AMPL_WIDTH),
conv_std_logic_vector(12400,AMPL_WIDTH),
conv_std_logic_vector(12403,AMPL_WIDTH),
conv_std_logic_vector(12406,AMPL_WIDTH),
conv_std_logic_vector(12409,AMPL_WIDTH),
conv_std_logic_vector(12412,AMPL_WIDTH),
conv_std_logic_vector(12414,AMPL_WIDTH),
conv_std_logic_vector(12417,AMPL_WIDTH),
conv_std_logic_vector(12420,AMPL_WIDTH),
conv_std_logic_vector(12423,AMPL_WIDTH),
conv_std_logic_vector(12426,AMPL_WIDTH),
conv_std_logic_vector(12429,AMPL_WIDTH),
conv_std_logic_vector(12432,AMPL_WIDTH),
conv_std_logic_vector(12435,AMPL_WIDTH),
conv_std_logic_vector(12438,AMPL_WIDTH),
conv_std_logic_vector(12441,AMPL_WIDTH),
conv_std_logic_vector(12444,AMPL_WIDTH),
conv_std_logic_vector(12446,AMPL_WIDTH),
conv_std_logic_vector(12449,AMPL_WIDTH),
conv_std_logic_vector(12452,AMPL_WIDTH),
conv_std_logic_vector(12455,AMPL_WIDTH),
conv_std_logic_vector(12458,AMPL_WIDTH),
conv_std_logic_vector(12461,AMPL_WIDTH),
conv_std_logic_vector(12464,AMPL_WIDTH),
conv_std_logic_vector(12467,AMPL_WIDTH),
conv_std_logic_vector(12470,AMPL_WIDTH),
conv_std_logic_vector(12473,AMPL_WIDTH),
conv_std_logic_vector(12476,AMPL_WIDTH),
conv_std_logic_vector(12478,AMPL_WIDTH),
conv_std_logic_vector(12481,AMPL_WIDTH),
conv_std_logic_vector(12484,AMPL_WIDTH),
conv_std_logic_vector(12487,AMPL_WIDTH),
conv_std_logic_vector(12490,AMPL_WIDTH),
conv_std_logic_vector(12493,AMPL_WIDTH),
conv_std_logic_vector(12496,AMPL_WIDTH),
conv_std_logic_vector(12499,AMPL_WIDTH),
conv_std_logic_vector(12502,AMPL_WIDTH),
conv_std_logic_vector(12505,AMPL_WIDTH),
conv_std_logic_vector(12507,AMPL_WIDTH),
conv_std_logic_vector(12510,AMPL_WIDTH),
conv_std_logic_vector(12513,AMPL_WIDTH),
conv_std_logic_vector(12516,AMPL_WIDTH),
conv_std_logic_vector(12519,AMPL_WIDTH),
conv_std_logic_vector(12522,AMPL_WIDTH),
conv_std_logic_vector(12525,AMPL_WIDTH),
conv_std_logic_vector(12528,AMPL_WIDTH),
conv_std_logic_vector(12531,AMPL_WIDTH),
conv_std_logic_vector(12534,AMPL_WIDTH),
conv_std_logic_vector(12536,AMPL_WIDTH),
conv_std_logic_vector(12539,AMPL_WIDTH),
conv_std_logic_vector(12542,AMPL_WIDTH),
conv_std_logic_vector(12545,AMPL_WIDTH),
conv_std_logic_vector(12548,AMPL_WIDTH),
conv_std_logic_vector(12551,AMPL_WIDTH),
conv_std_logic_vector(12554,AMPL_WIDTH),
conv_std_logic_vector(12557,AMPL_WIDTH),
conv_std_logic_vector(12560,AMPL_WIDTH),
conv_std_logic_vector(12563,AMPL_WIDTH),
conv_std_logic_vector(12566,AMPL_WIDTH),
conv_std_logic_vector(12568,AMPL_WIDTH),
conv_std_logic_vector(12571,AMPL_WIDTH),
conv_std_logic_vector(12574,AMPL_WIDTH),
conv_std_logic_vector(12577,AMPL_WIDTH),
conv_std_logic_vector(12580,AMPL_WIDTH),
conv_std_logic_vector(12583,AMPL_WIDTH),
conv_std_logic_vector(12586,AMPL_WIDTH),
conv_std_logic_vector(12589,AMPL_WIDTH),
conv_std_logic_vector(12592,AMPL_WIDTH),
conv_std_logic_vector(12595,AMPL_WIDTH),
conv_std_logic_vector(12597,AMPL_WIDTH),
conv_std_logic_vector(12600,AMPL_WIDTH),
conv_std_logic_vector(12603,AMPL_WIDTH),
conv_std_logic_vector(12606,AMPL_WIDTH),
conv_std_logic_vector(12609,AMPL_WIDTH),
conv_std_logic_vector(12612,AMPL_WIDTH),
conv_std_logic_vector(12615,AMPL_WIDTH),
conv_std_logic_vector(12618,AMPL_WIDTH),
conv_std_logic_vector(12621,AMPL_WIDTH),
conv_std_logic_vector(12624,AMPL_WIDTH),
conv_std_logic_vector(12626,AMPL_WIDTH),
conv_std_logic_vector(12629,AMPL_WIDTH),
conv_std_logic_vector(12632,AMPL_WIDTH),
conv_std_logic_vector(12635,AMPL_WIDTH),
conv_std_logic_vector(12638,AMPL_WIDTH),
conv_std_logic_vector(12641,AMPL_WIDTH),
conv_std_logic_vector(12644,AMPL_WIDTH),
conv_std_logic_vector(12647,AMPL_WIDTH),
conv_std_logic_vector(12650,AMPL_WIDTH),
conv_std_logic_vector(12652,AMPL_WIDTH),
conv_std_logic_vector(12655,AMPL_WIDTH),
conv_std_logic_vector(12658,AMPL_WIDTH),
conv_std_logic_vector(12661,AMPL_WIDTH),
conv_std_logic_vector(12664,AMPL_WIDTH),
conv_std_logic_vector(12667,AMPL_WIDTH),
conv_std_logic_vector(12670,AMPL_WIDTH),
conv_std_logic_vector(12673,AMPL_WIDTH),
conv_std_logic_vector(12676,AMPL_WIDTH),
conv_std_logic_vector(12679,AMPL_WIDTH),
conv_std_logic_vector(12681,AMPL_WIDTH),
conv_std_logic_vector(12684,AMPL_WIDTH),
conv_std_logic_vector(12687,AMPL_WIDTH),
conv_std_logic_vector(12690,AMPL_WIDTH),
conv_std_logic_vector(12693,AMPL_WIDTH),
conv_std_logic_vector(12696,AMPL_WIDTH),
conv_std_logic_vector(12699,AMPL_WIDTH),
conv_std_logic_vector(12702,AMPL_WIDTH),
conv_std_logic_vector(12705,AMPL_WIDTH),
conv_std_logic_vector(12708,AMPL_WIDTH),
conv_std_logic_vector(12710,AMPL_WIDTH),
conv_std_logic_vector(12713,AMPL_WIDTH),
conv_std_logic_vector(12716,AMPL_WIDTH),
conv_std_logic_vector(12719,AMPL_WIDTH),
conv_std_logic_vector(12722,AMPL_WIDTH),
conv_std_logic_vector(12725,AMPL_WIDTH),
conv_std_logic_vector(12728,AMPL_WIDTH),
conv_std_logic_vector(12731,AMPL_WIDTH),
conv_std_logic_vector(12734,AMPL_WIDTH),
conv_std_logic_vector(12736,AMPL_WIDTH),
conv_std_logic_vector(12739,AMPL_WIDTH),
conv_std_logic_vector(12742,AMPL_WIDTH),
conv_std_logic_vector(12745,AMPL_WIDTH),
conv_std_logic_vector(12748,AMPL_WIDTH),
conv_std_logic_vector(12751,AMPL_WIDTH),
conv_std_logic_vector(12754,AMPL_WIDTH),
conv_std_logic_vector(12757,AMPL_WIDTH),
conv_std_logic_vector(12760,AMPL_WIDTH),
conv_std_logic_vector(12763,AMPL_WIDTH),
conv_std_logic_vector(12765,AMPL_WIDTH),
conv_std_logic_vector(12768,AMPL_WIDTH),
conv_std_logic_vector(12771,AMPL_WIDTH),
conv_std_logic_vector(12774,AMPL_WIDTH),
conv_std_logic_vector(12777,AMPL_WIDTH),
conv_std_logic_vector(12780,AMPL_WIDTH),
conv_std_logic_vector(12783,AMPL_WIDTH),
conv_std_logic_vector(12786,AMPL_WIDTH),
conv_std_logic_vector(12789,AMPL_WIDTH),
conv_std_logic_vector(12791,AMPL_WIDTH),
conv_std_logic_vector(12794,AMPL_WIDTH),
conv_std_logic_vector(12797,AMPL_WIDTH),
conv_std_logic_vector(12800,AMPL_WIDTH),
conv_std_logic_vector(12803,AMPL_WIDTH),
conv_std_logic_vector(12806,AMPL_WIDTH),
conv_std_logic_vector(12809,AMPL_WIDTH),
conv_std_logic_vector(12812,AMPL_WIDTH),
conv_std_logic_vector(12815,AMPL_WIDTH),
conv_std_logic_vector(12817,AMPL_WIDTH),
conv_std_logic_vector(12820,AMPL_WIDTH),
conv_std_logic_vector(12823,AMPL_WIDTH),
conv_std_logic_vector(12826,AMPL_WIDTH),
conv_std_logic_vector(12829,AMPL_WIDTH),
conv_std_logic_vector(12832,AMPL_WIDTH),
conv_std_logic_vector(12835,AMPL_WIDTH),
conv_std_logic_vector(12838,AMPL_WIDTH),
conv_std_logic_vector(12841,AMPL_WIDTH),
conv_std_logic_vector(12843,AMPL_WIDTH),
conv_std_logic_vector(12846,AMPL_WIDTH),
conv_std_logic_vector(12849,AMPL_WIDTH),
conv_std_logic_vector(12852,AMPL_WIDTH),
conv_std_logic_vector(12855,AMPL_WIDTH),
conv_std_logic_vector(12858,AMPL_WIDTH),
conv_std_logic_vector(12861,AMPL_WIDTH),
conv_std_logic_vector(12864,AMPL_WIDTH),
conv_std_logic_vector(12867,AMPL_WIDTH),
conv_std_logic_vector(12870,AMPL_WIDTH),
conv_std_logic_vector(12872,AMPL_WIDTH),
conv_std_logic_vector(12875,AMPL_WIDTH),
conv_std_logic_vector(12878,AMPL_WIDTH),
conv_std_logic_vector(12881,AMPL_WIDTH),
conv_std_logic_vector(12884,AMPL_WIDTH),
conv_std_logic_vector(12887,AMPL_WIDTH),
conv_std_logic_vector(12890,AMPL_WIDTH),
conv_std_logic_vector(12893,AMPL_WIDTH),
conv_std_logic_vector(12895,AMPL_WIDTH),
conv_std_logic_vector(12898,AMPL_WIDTH),
conv_std_logic_vector(12901,AMPL_WIDTH),
conv_std_logic_vector(12904,AMPL_WIDTH),
conv_std_logic_vector(12907,AMPL_WIDTH),
conv_std_logic_vector(12910,AMPL_WIDTH),
conv_std_logic_vector(12913,AMPL_WIDTH),
conv_std_logic_vector(12916,AMPL_WIDTH),
conv_std_logic_vector(12919,AMPL_WIDTH),
conv_std_logic_vector(12921,AMPL_WIDTH),
conv_std_logic_vector(12924,AMPL_WIDTH),
conv_std_logic_vector(12927,AMPL_WIDTH),
conv_std_logic_vector(12930,AMPL_WIDTH),
conv_std_logic_vector(12933,AMPL_WIDTH),
conv_std_logic_vector(12936,AMPL_WIDTH),
conv_std_logic_vector(12939,AMPL_WIDTH),
conv_std_logic_vector(12942,AMPL_WIDTH),
conv_std_logic_vector(12945,AMPL_WIDTH),
conv_std_logic_vector(12947,AMPL_WIDTH),
conv_std_logic_vector(12950,AMPL_WIDTH),
conv_std_logic_vector(12953,AMPL_WIDTH),
conv_std_logic_vector(12956,AMPL_WIDTH),
conv_std_logic_vector(12959,AMPL_WIDTH),
conv_std_logic_vector(12962,AMPL_WIDTH),
conv_std_logic_vector(12965,AMPL_WIDTH),
conv_std_logic_vector(12968,AMPL_WIDTH),
conv_std_logic_vector(12971,AMPL_WIDTH),
conv_std_logic_vector(12973,AMPL_WIDTH),
conv_std_logic_vector(12976,AMPL_WIDTH),
conv_std_logic_vector(12979,AMPL_WIDTH),
conv_std_logic_vector(12982,AMPL_WIDTH),
conv_std_logic_vector(12985,AMPL_WIDTH),
conv_std_logic_vector(12988,AMPL_WIDTH),
conv_std_logic_vector(12991,AMPL_WIDTH),
conv_std_logic_vector(12994,AMPL_WIDTH),
conv_std_logic_vector(12997,AMPL_WIDTH),
conv_std_logic_vector(12999,AMPL_WIDTH),
conv_std_logic_vector(13002,AMPL_WIDTH),
conv_std_logic_vector(13005,AMPL_WIDTH),
conv_std_logic_vector(13008,AMPL_WIDTH),
conv_std_logic_vector(13011,AMPL_WIDTH),
conv_std_logic_vector(13014,AMPL_WIDTH),
conv_std_logic_vector(13017,AMPL_WIDTH),
conv_std_logic_vector(13020,AMPL_WIDTH),
conv_std_logic_vector(13022,AMPL_WIDTH),
conv_std_logic_vector(13025,AMPL_WIDTH),
conv_std_logic_vector(13028,AMPL_WIDTH),
conv_std_logic_vector(13031,AMPL_WIDTH),
conv_std_logic_vector(13034,AMPL_WIDTH),
conv_std_logic_vector(13037,AMPL_WIDTH),
conv_std_logic_vector(13040,AMPL_WIDTH),
conv_std_logic_vector(13043,AMPL_WIDTH),
conv_std_logic_vector(13046,AMPL_WIDTH),
conv_std_logic_vector(13048,AMPL_WIDTH),
conv_std_logic_vector(13051,AMPL_WIDTH),
conv_std_logic_vector(13054,AMPL_WIDTH),
conv_std_logic_vector(13057,AMPL_WIDTH),
conv_std_logic_vector(13060,AMPL_WIDTH),
conv_std_logic_vector(13063,AMPL_WIDTH),
conv_std_logic_vector(13066,AMPL_WIDTH),
conv_std_logic_vector(13069,AMPL_WIDTH),
conv_std_logic_vector(13071,AMPL_WIDTH),
conv_std_logic_vector(13074,AMPL_WIDTH),
conv_std_logic_vector(13077,AMPL_WIDTH),
conv_std_logic_vector(13080,AMPL_WIDTH),
conv_std_logic_vector(13083,AMPL_WIDTH),
conv_std_logic_vector(13086,AMPL_WIDTH),
conv_std_logic_vector(13089,AMPL_WIDTH),
conv_std_logic_vector(13092,AMPL_WIDTH),
conv_std_logic_vector(13094,AMPL_WIDTH),
conv_std_logic_vector(13097,AMPL_WIDTH),
conv_std_logic_vector(13100,AMPL_WIDTH),
conv_std_logic_vector(13103,AMPL_WIDTH),
conv_std_logic_vector(13106,AMPL_WIDTH),
conv_std_logic_vector(13109,AMPL_WIDTH),
conv_std_logic_vector(13112,AMPL_WIDTH),
conv_std_logic_vector(13115,AMPL_WIDTH),
conv_std_logic_vector(13118,AMPL_WIDTH),
conv_std_logic_vector(13120,AMPL_WIDTH),
conv_std_logic_vector(13123,AMPL_WIDTH),
conv_std_logic_vector(13126,AMPL_WIDTH),
conv_std_logic_vector(13129,AMPL_WIDTH),
conv_std_logic_vector(13132,AMPL_WIDTH),
conv_std_logic_vector(13135,AMPL_WIDTH),
conv_std_logic_vector(13138,AMPL_WIDTH),
conv_std_logic_vector(13141,AMPL_WIDTH),
conv_std_logic_vector(13143,AMPL_WIDTH),
conv_std_logic_vector(13146,AMPL_WIDTH),
conv_std_logic_vector(13149,AMPL_WIDTH),
conv_std_logic_vector(13152,AMPL_WIDTH),
conv_std_logic_vector(13155,AMPL_WIDTH),
conv_std_logic_vector(13158,AMPL_WIDTH),
conv_std_logic_vector(13161,AMPL_WIDTH),
conv_std_logic_vector(13164,AMPL_WIDTH),
conv_std_logic_vector(13166,AMPL_WIDTH),
conv_std_logic_vector(13169,AMPL_WIDTH),
conv_std_logic_vector(13172,AMPL_WIDTH),
conv_std_logic_vector(13175,AMPL_WIDTH),
conv_std_logic_vector(13178,AMPL_WIDTH),
conv_std_logic_vector(13181,AMPL_WIDTH),
conv_std_logic_vector(13184,AMPL_WIDTH),
conv_std_logic_vector(13187,AMPL_WIDTH),
conv_std_logic_vector(13189,AMPL_WIDTH),
conv_std_logic_vector(13192,AMPL_WIDTH),
conv_std_logic_vector(13195,AMPL_WIDTH),
conv_std_logic_vector(13198,AMPL_WIDTH),
conv_std_logic_vector(13201,AMPL_WIDTH),
conv_std_logic_vector(13204,AMPL_WIDTH),
conv_std_logic_vector(13207,AMPL_WIDTH),
conv_std_logic_vector(13210,AMPL_WIDTH),
conv_std_logic_vector(13212,AMPL_WIDTH),
conv_std_logic_vector(13215,AMPL_WIDTH),
conv_std_logic_vector(13218,AMPL_WIDTH),
conv_std_logic_vector(13221,AMPL_WIDTH),
conv_std_logic_vector(13224,AMPL_WIDTH),
conv_std_logic_vector(13227,AMPL_WIDTH),
conv_std_logic_vector(13230,AMPL_WIDTH),
conv_std_logic_vector(13233,AMPL_WIDTH),
conv_std_logic_vector(13235,AMPL_WIDTH),
conv_std_logic_vector(13238,AMPL_WIDTH),
conv_std_logic_vector(13241,AMPL_WIDTH),
conv_std_logic_vector(13244,AMPL_WIDTH),
conv_std_logic_vector(13247,AMPL_WIDTH),
conv_std_logic_vector(13250,AMPL_WIDTH),
conv_std_logic_vector(13253,AMPL_WIDTH),
conv_std_logic_vector(13256,AMPL_WIDTH),
conv_std_logic_vector(13258,AMPL_WIDTH),
conv_std_logic_vector(13261,AMPL_WIDTH),
conv_std_logic_vector(13264,AMPL_WIDTH),
conv_std_logic_vector(13267,AMPL_WIDTH),
conv_std_logic_vector(13270,AMPL_WIDTH),
conv_std_logic_vector(13273,AMPL_WIDTH),
conv_std_logic_vector(13276,AMPL_WIDTH),
conv_std_logic_vector(13279,AMPL_WIDTH),
conv_std_logic_vector(13281,AMPL_WIDTH),
conv_std_logic_vector(13284,AMPL_WIDTH),
conv_std_logic_vector(13287,AMPL_WIDTH),
conv_std_logic_vector(13290,AMPL_WIDTH),
conv_std_logic_vector(13293,AMPL_WIDTH),
conv_std_logic_vector(13296,AMPL_WIDTH),
conv_std_logic_vector(13299,AMPL_WIDTH),
conv_std_logic_vector(13302,AMPL_WIDTH),
conv_std_logic_vector(13304,AMPL_WIDTH),
conv_std_logic_vector(13307,AMPL_WIDTH),
conv_std_logic_vector(13310,AMPL_WIDTH),
conv_std_logic_vector(13313,AMPL_WIDTH),
conv_std_logic_vector(13316,AMPL_WIDTH),
conv_std_logic_vector(13319,AMPL_WIDTH),
conv_std_logic_vector(13322,AMPL_WIDTH),
conv_std_logic_vector(13324,AMPL_WIDTH),
conv_std_logic_vector(13327,AMPL_WIDTH),
conv_std_logic_vector(13330,AMPL_WIDTH),
conv_std_logic_vector(13333,AMPL_WIDTH),
conv_std_logic_vector(13336,AMPL_WIDTH),
conv_std_logic_vector(13339,AMPL_WIDTH),
conv_std_logic_vector(13342,AMPL_WIDTH),
conv_std_logic_vector(13345,AMPL_WIDTH),
conv_std_logic_vector(13347,AMPL_WIDTH),
conv_std_logic_vector(13350,AMPL_WIDTH),
conv_std_logic_vector(13353,AMPL_WIDTH),
conv_std_logic_vector(13356,AMPL_WIDTH),
conv_std_logic_vector(13359,AMPL_WIDTH),
conv_std_logic_vector(13362,AMPL_WIDTH),
conv_std_logic_vector(13365,AMPL_WIDTH),
conv_std_logic_vector(13368,AMPL_WIDTH),
conv_std_logic_vector(13370,AMPL_WIDTH),
conv_std_logic_vector(13373,AMPL_WIDTH),
conv_std_logic_vector(13376,AMPL_WIDTH),
conv_std_logic_vector(13379,AMPL_WIDTH),
conv_std_logic_vector(13382,AMPL_WIDTH),
conv_std_logic_vector(13385,AMPL_WIDTH),
conv_std_logic_vector(13388,AMPL_WIDTH),
conv_std_logic_vector(13390,AMPL_WIDTH),
conv_std_logic_vector(13393,AMPL_WIDTH),
conv_std_logic_vector(13396,AMPL_WIDTH),
conv_std_logic_vector(13399,AMPL_WIDTH),
conv_std_logic_vector(13402,AMPL_WIDTH),
conv_std_logic_vector(13405,AMPL_WIDTH),
conv_std_logic_vector(13408,AMPL_WIDTH),
conv_std_logic_vector(13411,AMPL_WIDTH),
conv_std_logic_vector(13413,AMPL_WIDTH),
conv_std_logic_vector(13416,AMPL_WIDTH),
conv_std_logic_vector(13419,AMPL_WIDTH),
conv_std_logic_vector(13422,AMPL_WIDTH),
conv_std_logic_vector(13425,AMPL_WIDTH),
conv_std_logic_vector(13428,AMPL_WIDTH),
conv_std_logic_vector(13431,AMPL_WIDTH),
conv_std_logic_vector(13433,AMPL_WIDTH),
conv_std_logic_vector(13436,AMPL_WIDTH),
conv_std_logic_vector(13439,AMPL_WIDTH),
conv_std_logic_vector(13442,AMPL_WIDTH),
conv_std_logic_vector(13445,AMPL_WIDTH),
conv_std_logic_vector(13448,AMPL_WIDTH),
conv_std_logic_vector(13451,AMPL_WIDTH),
conv_std_logic_vector(13454,AMPL_WIDTH),
conv_std_logic_vector(13456,AMPL_WIDTH),
conv_std_logic_vector(13459,AMPL_WIDTH),
conv_std_logic_vector(13462,AMPL_WIDTH),
conv_std_logic_vector(13465,AMPL_WIDTH),
conv_std_logic_vector(13468,AMPL_WIDTH),
conv_std_logic_vector(13471,AMPL_WIDTH),
conv_std_logic_vector(13474,AMPL_WIDTH),
conv_std_logic_vector(13476,AMPL_WIDTH),
conv_std_logic_vector(13479,AMPL_WIDTH),
conv_std_logic_vector(13482,AMPL_WIDTH),
conv_std_logic_vector(13485,AMPL_WIDTH),
conv_std_logic_vector(13488,AMPL_WIDTH),
conv_std_logic_vector(13491,AMPL_WIDTH),
conv_std_logic_vector(13494,AMPL_WIDTH),
conv_std_logic_vector(13496,AMPL_WIDTH),
conv_std_logic_vector(13499,AMPL_WIDTH),
conv_std_logic_vector(13502,AMPL_WIDTH),
conv_std_logic_vector(13505,AMPL_WIDTH),
conv_std_logic_vector(13508,AMPL_WIDTH),
conv_std_logic_vector(13511,AMPL_WIDTH),
conv_std_logic_vector(13514,AMPL_WIDTH),
conv_std_logic_vector(13516,AMPL_WIDTH),
conv_std_logic_vector(13519,AMPL_WIDTH),
conv_std_logic_vector(13522,AMPL_WIDTH),
conv_std_logic_vector(13525,AMPL_WIDTH),
conv_std_logic_vector(13528,AMPL_WIDTH),
conv_std_logic_vector(13531,AMPL_WIDTH),
conv_std_logic_vector(13534,AMPL_WIDTH),
conv_std_logic_vector(13537,AMPL_WIDTH),
conv_std_logic_vector(13539,AMPL_WIDTH),
conv_std_logic_vector(13542,AMPL_WIDTH),
conv_std_logic_vector(13545,AMPL_WIDTH),
conv_std_logic_vector(13548,AMPL_WIDTH),
conv_std_logic_vector(13551,AMPL_WIDTH),
conv_std_logic_vector(13554,AMPL_WIDTH),
conv_std_logic_vector(13557,AMPL_WIDTH),
conv_std_logic_vector(13559,AMPL_WIDTH),
conv_std_logic_vector(13562,AMPL_WIDTH),
conv_std_logic_vector(13565,AMPL_WIDTH),
conv_std_logic_vector(13568,AMPL_WIDTH),
conv_std_logic_vector(13571,AMPL_WIDTH),
conv_std_logic_vector(13574,AMPL_WIDTH),
conv_std_logic_vector(13577,AMPL_WIDTH),
conv_std_logic_vector(13579,AMPL_WIDTH),
conv_std_logic_vector(13582,AMPL_WIDTH),
conv_std_logic_vector(13585,AMPL_WIDTH),
conv_std_logic_vector(13588,AMPL_WIDTH),
conv_std_logic_vector(13591,AMPL_WIDTH),
conv_std_logic_vector(13594,AMPL_WIDTH),
conv_std_logic_vector(13597,AMPL_WIDTH),
conv_std_logic_vector(13599,AMPL_WIDTH),
conv_std_logic_vector(13602,AMPL_WIDTH),
conv_std_logic_vector(13605,AMPL_WIDTH),
conv_std_logic_vector(13608,AMPL_WIDTH),
conv_std_logic_vector(13611,AMPL_WIDTH),
conv_std_logic_vector(13614,AMPL_WIDTH),
conv_std_logic_vector(13617,AMPL_WIDTH),
conv_std_logic_vector(13619,AMPL_WIDTH),
conv_std_logic_vector(13622,AMPL_WIDTH),
conv_std_logic_vector(13625,AMPL_WIDTH),
conv_std_logic_vector(13628,AMPL_WIDTH),
conv_std_logic_vector(13631,AMPL_WIDTH),
conv_std_logic_vector(13634,AMPL_WIDTH),
conv_std_logic_vector(13637,AMPL_WIDTH),
conv_std_logic_vector(13639,AMPL_WIDTH),
conv_std_logic_vector(13642,AMPL_WIDTH),
conv_std_logic_vector(13645,AMPL_WIDTH),
conv_std_logic_vector(13648,AMPL_WIDTH),
conv_std_logic_vector(13651,AMPL_WIDTH),
conv_std_logic_vector(13654,AMPL_WIDTH),
conv_std_logic_vector(13657,AMPL_WIDTH),
conv_std_logic_vector(13659,AMPL_WIDTH),
conv_std_logic_vector(13662,AMPL_WIDTH),
conv_std_logic_vector(13665,AMPL_WIDTH),
conv_std_logic_vector(13668,AMPL_WIDTH),
conv_std_logic_vector(13671,AMPL_WIDTH),
conv_std_logic_vector(13674,AMPL_WIDTH),
conv_std_logic_vector(13677,AMPL_WIDTH),
conv_std_logic_vector(13679,AMPL_WIDTH),
conv_std_logic_vector(13682,AMPL_WIDTH),
conv_std_logic_vector(13685,AMPL_WIDTH),
conv_std_logic_vector(13688,AMPL_WIDTH),
conv_std_logic_vector(13691,AMPL_WIDTH),
conv_std_logic_vector(13694,AMPL_WIDTH),
conv_std_logic_vector(13697,AMPL_WIDTH),
conv_std_logic_vector(13699,AMPL_WIDTH),
conv_std_logic_vector(13702,AMPL_WIDTH),
conv_std_logic_vector(13705,AMPL_WIDTH),
conv_std_logic_vector(13708,AMPL_WIDTH),
conv_std_logic_vector(13711,AMPL_WIDTH),
conv_std_logic_vector(13714,AMPL_WIDTH),
conv_std_logic_vector(13717,AMPL_WIDTH),
conv_std_logic_vector(13719,AMPL_WIDTH),
conv_std_logic_vector(13722,AMPL_WIDTH),
conv_std_logic_vector(13725,AMPL_WIDTH),
conv_std_logic_vector(13728,AMPL_WIDTH),
conv_std_logic_vector(13731,AMPL_WIDTH),
conv_std_logic_vector(13734,AMPL_WIDTH),
conv_std_logic_vector(13736,AMPL_WIDTH),
conv_std_logic_vector(13739,AMPL_WIDTH),
conv_std_logic_vector(13742,AMPL_WIDTH),
conv_std_logic_vector(13745,AMPL_WIDTH),
conv_std_logic_vector(13748,AMPL_WIDTH),
conv_std_logic_vector(13751,AMPL_WIDTH),
conv_std_logic_vector(13754,AMPL_WIDTH),
conv_std_logic_vector(13756,AMPL_WIDTH),
conv_std_logic_vector(13759,AMPL_WIDTH),
conv_std_logic_vector(13762,AMPL_WIDTH),
conv_std_logic_vector(13765,AMPL_WIDTH),
conv_std_logic_vector(13768,AMPL_WIDTH),
conv_std_logic_vector(13771,AMPL_WIDTH),
conv_std_logic_vector(13774,AMPL_WIDTH),
conv_std_logic_vector(13776,AMPL_WIDTH),
conv_std_logic_vector(13779,AMPL_WIDTH),
conv_std_logic_vector(13782,AMPL_WIDTH),
conv_std_logic_vector(13785,AMPL_WIDTH),
conv_std_logic_vector(13788,AMPL_WIDTH),
conv_std_logic_vector(13791,AMPL_WIDTH),
conv_std_logic_vector(13793,AMPL_WIDTH),
conv_std_logic_vector(13796,AMPL_WIDTH),
conv_std_logic_vector(13799,AMPL_WIDTH),
conv_std_logic_vector(13802,AMPL_WIDTH),
conv_std_logic_vector(13805,AMPL_WIDTH),
conv_std_logic_vector(13808,AMPL_WIDTH),
conv_std_logic_vector(13811,AMPL_WIDTH),
conv_std_logic_vector(13813,AMPL_WIDTH),
conv_std_logic_vector(13816,AMPL_WIDTH),
conv_std_logic_vector(13819,AMPL_WIDTH),
conv_std_logic_vector(13822,AMPL_WIDTH),
conv_std_logic_vector(13825,AMPL_WIDTH),
conv_std_logic_vector(13828,AMPL_WIDTH),
conv_std_logic_vector(13831,AMPL_WIDTH),
conv_std_logic_vector(13833,AMPL_WIDTH),
conv_std_logic_vector(13836,AMPL_WIDTH),
conv_std_logic_vector(13839,AMPL_WIDTH),
conv_std_logic_vector(13842,AMPL_WIDTH),
conv_std_logic_vector(13845,AMPL_WIDTH),
conv_std_logic_vector(13848,AMPL_WIDTH),
conv_std_logic_vector(13850,AMPL_WIDTH),
conv_std_logic_vector(13853,AMPL_WIDTH),
conv_std_logic_vector(13856,AMPL_WIDTH),
conv_std_logic_vector(13859,AMPL_WIDTH),
conv_std_logic_vector(13862,AMPL_WIDTH),
conv_std_logic_vector(13865,AMPL_WIDTH),
conv_std_logic_vector(13868,AMPL_WIDTH),
conv_std_logic_vector(13870,AMPL_WIDTH),
conv_std_logic_vector(13873,AMPL_WIDTH),
conv_std_logic_vector(13876,AMPL_WIDTH),
conv_std_logic_vector(13879,AMPL_WIDTH),
conv_std_logic_vector(13882,AMPL_WIDTH),
conv_std_logic_vector(13885,AMPL_WIDTH),
conv_std_logic_vector(13887,AMPL_WIDTH),
conv_std_logic_vector(13890,AMPL_WIDTH),
conv_std_logic_vector(13893,AMPL_WIDTH),
conv_std_logic_vector(13896,AMPL_WIDTH),
conv_std_logic_vector(13899,AMPL_WIDTH),
conv_std_logic_vector(13902,AMPL_WIDTH),
conv_std_logic_vector(13905,AMPL_WIDTH),
conv_std_logic_vector(13907,AMPL_WIDTH),
conv_std_logic_vector(13910,AMPL_WIDTH),
conv_std_logic_vector(13913,AMPL_WIDTH),
conv_std_logic_vector(13916,AMPL_WIDTH),
conv_std_logic_vector(13919,AMPL_WIDTH),
conv_std_logic_vector(13922,AMPL_WIDTH),
conv_std_logic_vector(13924,AMPL_WIDTH),
conv_std_logic_vector(13927,AMPL_WIDTH),
conv_std_logic_vector(13930,AMPL_WIDTH),
conv_std_logic_vector(13933,AMPL_WIDTH),
conv_std_logic_vector(13936,AMPL_WIDTH),
conv_std_logic_vector(13939,AMPL_WIDTH),
conv_std_logic_vector(13942,AMPL_WIDTH),
conv_std_logic_vector(13944,AMPL_WIDTH),
conv_std_logic_vector(13947,AMPL_WIDTH),
conv_std_logic_vector(13950,AMPL_WIDTH),
conv_std_logic_vector(13953,AMPL_WIDTH),
conv_std_logic_vector(13956,AMPL_WIDTH),
conv_std_logic_vector(13959,AMPL_WIDTH),
conv_std_logic_vector(13961,AMPL_WIDTH),
conv_std_logic_vector(13964,AMPL_WIDTH),
conv_std_logic_vector(13967,AMPL_WIDTH),
conv_std_logic_vector(13970,AMPL_WIDTH),
conv_std_logic_vector(13973,AMPL_WIDTH),
conv_std_logic_vector(13976,AMPL_WIDTH),
conv_std_logic_vector(13978,AMPL_WIDTH),
conv_std_logic_vector(13981,AMPL_WIDTH),
conv_std_logic_vector(13984,AMPL_WIDTH),
conv_std_logic_vector(13987,AMPL_WIDTH),
conv_std_logic_vector(13990,AMPL_WIDTH),
conv_std_logic_vector(13993,AMPL_WIDTH),
conv_std_logic_vector(13995,AMPL_WIDTH),
conv_std_logic_vector(13998,AMPL_WIDTH),
conv_std_logic_vector(14001,AMPL_WIDTH),
conv_std_logic_vector(14004,AMPL_WIDTH),
conv_std_logic_vector(14007,AMPL_WIDTH),
conv_std_logic_vector(14010,AMPL_WIDTH),
conv_std_logic_vector(14013,AMPL_WIDTH),
conv_std_logic_vector(14015,AMPL_WIDTH),
conv_std_logic_vector(14018,AMPL_WIDTH),
conv_std_logic_vector(14021,AMPL_WIDTH),
conv_std_logic_vector(14024,AMPL_WIDTH),
conv_std_logic_vector(14027,AMPL_WIDTH),
conv_std_logic_vector(14030,AMPL_WIDTH),
conv_std_logic_vector(14032,AMPL_WIDTH),
conv_std_logic_vector(14035,AMPL_WIDTH),
conv_std_logic_vector(14038,AMPL_WIDTH),
conv_std_logic_vector(14041,AMPL_WIDTH),
conv_std_logic_vector(14044,AMPL_WIDTH),
conv_std_logic_vector(14047,AMPL_WIDTH),
conv_std_logic_vector(14049,AMPL_WIDTH),
conv_std_logic_vector(14052,AMPL_WIDTH),
conv_std_logic_vector(14055,AMPL_WIDTH),
conv_std_logic_vector(14058,AMPL_WIDTH),
conv_std_logic_vector(14061,AMPL_WIDTH),
conv_std_logic_vector(14064,AMPL_WIDTH),
conv_std_logic_vector(14066,AMPL_WIDTH),
conv_std_logic_vector(14069,AMPL_WIDTH),
conv_std_logic_vector(14072,AMPL_WIDTH),
conv_std_logic_vector(14075,AMPL_WIDTH),
conv_std_logic_vector(14078,AMPL_WIDTH),
conv_std_logic_vector(14081,AMPL_WIDTH),
conv_std_logic_vector(14083,AMPL_WIDTH),
conv_std_logic_vector(14086,AMPL_WIDTH),
conv_std_logic_vector(14089,AMPL_WIDTH),
conv_std_logic_vector(14092,AMPL_WIDTH),
conv_std_logic_vector(14095,AMPL_WIDTH),
conv_std_logic_vector(14098,AMPL_WIDTH),
conv_std_logic_vector(14101,AMPL_WIDTH),
conv_std_logic_vector(14103,AMPL_WIDTH),
conv_std_logic_vector(14106,AMPL_WIDTH),
conv_std_logic_vector(14109,AMPL_WIDTH),
conv_std_logic_vector(14112,AMPL_WIDTH),
conv_std_logic_vector(14115,AMPL_WIDTH),
conv_std_logic_vector(14118,AMPL_WIDTH),
conv_std_logic_vector(14120,AMPL_WIDTH),
conv_std_logic_vector(14123,AMPL_WIDTH),
conv_std_logic_vector(14126,AMPL_WIDTH),
conv_std_logic_vector(14129,AMPL_WIDTH),
conv_std_logic_vector(14132,AMPL_WIDTH),
conv_std_logic_vector(14135,AMPL_WIDTH),
conv_std_logic_vector(14137,AMPL_WIDTH),
conv_std_logic_vector(14140,AMPL_WIDTH),
conv_std_logic_vector(14143,AMPL_WIDTH),
conv_std_logic_vector(14146,AMPL_WIDTH),
conv_std_logic_vector(14149,AMPL_WIDTH),
conv_std_logic_vector(14152,AMPL_WIDTH),
conv_std_logic_vector(14154,AMPL_WIDTH),
conv_std_logic_vector(14157,AMPL_WIDTH),
conv_std_logic_vector(14160,AMPL_WIDTH),
conv_std_logic_vector(14163,AMPL_WIDTH),
conv_std_logic_vector(14166,AMPL_WIDTH),
conv_std_logic_vector(14169,AMPL_WIDTH),
conv_std_logic_vector(14171,AMPL_WIDTH),
conv_std_logic_vector(14174,AMPL_WIDTH),
conv_std_logic_vector(14177,AMPL_WIDTH),
conv_std_logic_vector(14180,AMPL_WIDTH),
conv_std_logic_vector(14183,AMPL_WIDTH),
conv_std_logic_vector(14186,AMPL_WIDTH),
conv_std_logic_vector(14188,AMPL_WIDTH),
conv_std_logic_vector(14191,AMPL_WIDTH),
conv_std_logic_vector(14194,AMPL_WIDTH),
conv_std_logic_vector(14197,AMPL_WIDTH),
conv_std_logic_vector(14200,AMPL_WIDTH),
conv_std_logic_vector(14203,AMPL_WIDTH),
conv_std_logic_vector(14205,AMPL_WIDTH),
conv_std_logic_vector(14208,AMPL_WIDTH),
conv_std_logic_vector(14211,AMPL_WIDTH),
conv_std_logic_vector(14214,AMPL_WIDTH),
conv_std_logic_vector(14217,AMPL_WIDTH),
conv_std_logic_vector(14219,AMPL_WIDTH),
conv_std_logic_vector(14222,AMPL_WIDTH),
conv_std_logic_vector(14225,AMPL_WIDTH),
conv_std_logic_vector(14228,AMPL_WIDTH),
conv_std_logic_vector(14231,AMPL_WIDTH),
conv_std_logic_vector(14234,AMPL_WIDTH),
conv_std_logic_vector(14236,AMPL_WIDTH),
conv_std_logic_vector(14239,AMPL_WIDTH),
conv_std_logic_vector(14242,AMPL_WIDTH),
conv_std_logic_vector(14245,AMPL_WIDTH),
conv_std_logic_vector(14248,AMPL_WIDTH),
conv_std_logic_vector(14251,AMPL_WIDTH),
conv_std_logic_vector(14253,AMPL_WIDTH),
conv_std_logic_vector(14256,AMPL_WIDTH),
conv_std_logic_vector(14259,AMPL_WIDTH),
conv_std_logic_vector(14262,AMPL_WIDTH),
conv_std_logic_vector(14265,AMPL_WIDTH),
conv_std_logic_vector(14268,AMPL_WIDTH),
conv_std_logic_vector(14270,AMPL_WIDTH),
conv_std_logic_vector(14273,AMPL_WIDTH),
conv_std_logic_vector(14276,AMPL_WIDTH),
conv_std_logic_vector(14279,AMPL_WIDTH),
conv_std_logic_vector(14282,AMPL_WIDTH),
conv_std_logic_vector(14285,AMPL_WIDTH),
conv_std_logic_vector(14287,AMPL_WIDTH),
conv_std_logic_vector(14290,AMPL_WIDTH),
conv_std_logic_vector(14293,AMPL_WIDTH),
conv_std_logic_vector(14296,AMPL_WIDTH),
conv_std_logic_vector(14299,AMPL_WIDTH),
conv_std_logic_vector(14302,AMPL_WIDTH),
conv_std_logic_vector(14304,AMPL_WIDTH),
conv_std_logic_vector(14307,AMPL_WIDTH),
conv_std_logic_vector(14310,AMPL_WIDTH),
conv_std_logic_vector(14313,AMPL_WIDTH),
conv_std_logic_vector(14316,AMPL_WIDTH),
conv_std_logic_vector(14318,AMPL_WIDTH),
conv_std_logic_vector(14321,AMPL_WIDTH),
conv_std_logic_vector(14324,AMPL_WIDTH),
conv_std_logic_vector(14327,AMPL_WIDTH),
conv_std_logic_vector(14330,AMPL_WIDTH),
conv_std_logic_vector(14333,AMPL_WIDTH),
conv_std_logic_vector(14335,AMPL_WIDTH),
conv_std_logic_vector(14338,AMPL_WIDTH),
conv_std_logic_vector(14341,AMPL_WIDTH),
conv_std_logic_vector(14344,AMPL_WIDTH),
conv_std_logic_vector(14347,AMPL_WIDTH),
conv_std_logic_vector(14350,AMPL_WIDTH),
conv_std_logic_vector(14352,AMPL_WIDTH),
conv_std_logic_vector(14355,AMPL_WIDTH),
conv_std_logic_vector(14358,AMPL_WIDTH),
conv_std_logic_vector(14361,AMPL_WIDTH),
conv_std_logic_vector(14364,AMPL_WIDTH),
conv_std_logic_vector(14366,AMPL_WIDTH),
conv_std_logic_vector(14369,AMPL_WIDTH),
conv_std_logic_vector(14372,AMPL_WIDTH),
conv_std_logic_vector(14375,AMPL_WIDTH),
conv_std_logic_vector(14378,AMPL_WIDTH),
conv_std_logic_vector(14381,AMPL_WIDTH),
conv_std_logic_vector(14383,AMPL_WIDTH),
conv_std_logic_vector(14386,AMPL_WIDTH),
conv_std_logic_vector(14389,AMPL_WIDTH),
conv_std_logic_vector(14392,AMPL_WIDTH),
conv_std_logic_vector(14395,AMPL_WIDTH),
conv_std_logic_vector(14398,AMPL_WIDTH),
conv_std_logic_vector(14400,AMPL_WIDTH),
conv_std_logic_vector(14403,AMPL_WIDTH),
conv_std_logic_vector(14406,AMPL_WIDTH),
conv_std_logic_vector(14409,AMPL_WIDTH),
conv_std_logic_vector(14412,AMPL_WIDTH),
conv_std_logic_vector(14414,AMPL_WIDTH),
conv_std_logic_vector(14417,AMPL_WIDTH),
conv_std_logic_vector(14420,AMPL_WIDTH),
conv_std_logic_vector(14423,AMPL_WIDTH),
conv_std_logic_vector(14426,AMPL_WIDTH),
conv_std_logic_vector(14429,AMPL_WIDTH),
conv_std_logic_vector(14431,AMPL_WIDTH),
conv_std_logic_vector(14434,AMPL_WIDTH),
conv_std_logic_vector(14437,AMPL_WIDTH),
conv_std_logic_vector(14440,AMPL_WIDTH),
conv_std_logic_vector(14443,AMPL_WIDTH),
conv_std_logic_vector(14445,AMPL_WIDTH),
conv_std_logic_vector(14448,AMPL_WIDTH),
conv_std_logic_vector(14451,AMPL_WIDTH),
conv_std_logic_vector(14454,AMPL_WIDTH),
conv_std_logic_vector(14457,AMPL_WIDTH),
conv_std_logic_vector(14460,AMPL_WIDTH),
conv_std_logic_vector(14462,AMPL_WIDTH),
conv_std_logic_vector(14465,AMPL_WIDTH),
conv_std_logic_vector(14468,AMPL_WIDTH),
conv_std_logic_vector(14471,AMPL_WIDTH),
conv_std_logic_vector(14474,AMPL_WIDTH),
conv_std_logic_vector(14477,AMPL_WIDTH),
conv_std_logic_vector(14479,AMPL_WIDTH),
conv_std_logic_vector(14482,AMPL_WIDTH),
conv_std_logic_vector(14485,AMPL_WIDTH),
conv_std_logic_vector(14488,AMPL_WIDTH),
conv_std_logic_vector(14491,AMPL_WIDTH),
conv_std_logic_vector(14493,AMPL_WIDTH),
conv_std_logic_vector(14496,AMPL_WIDTH),
conv_std_logic_vector(14499,AMPL_WIDTH),
conv_std_logic_vector(14502,AMPL_WIDTH),
conv_std_logic_vector(14505,AMPL_WIDTH),
conv_std_logic_vector(14507,AMPL_WIDTH),
conv_std_logic_vector(14510,AMPL_WIDTH),
conv_std_logic_vector(14513,AMPL_WIDTH),
conv_std_logic_vector(14516,AMPL_WIDTH),
conv_std_logic_vector(14519,AMPL_WIDTH),
conv_std_logic_vector(14522,AMPL_WIDTH),
conv_std_logic_vector(14524,AMPL_WIDTH),
conv_std_logic_vector(14527,AMPL_WIDTH),
conv_std_logic_vector(14530,AMPL_WIDTH),
conv_std_logic_vector(14533,AMPL_WIDTH),
conv_std_logic_vector(14536,AMPL_WIDTH),
conv_std_logic_vector(14538,AMPL_WIDTH),
conv_std_logic_vector(14541,AMPL_WIDTH),
conv_std_logic_vector(14544,AMPL_WIDTH),
conv_std_logic_vector(14547,AMPL_WIDTH),
conv_std_logic_vector(14550,AMPL_WIDTH),
conv_std_logic_vector(14553,AMPL_WIDTH),
conv_std_logic_vector(14555,AMPL_WIDTH),
conv_std_logic_vector(14558,AMPL_WIDTH),
conv_std_logic_vector(14561,AMPL_WIDTH),
conv_std_logic_vector(14564,AMPL_WIDTH),
conv_std_logic_vector(14567,AMPL_WIDTH),
conv_std_logic_vector(14569,AMPL_WIDTH),
conv_std_logic_vector(14572,AMPL_WIDTH),
conv_std_logic_vector(14575,AMPL_WIDTH),
conv_std_logic_vector(14578,AMPL_WIDTH),
conv_std_logic_vector(14581,AMPL_WIDTH),
conv_std_logic_vector(14584,AMPL_WIDTH),
conv_std_logic_vector(14586,AMPL_WIDTH),
conv_std_logic_vector(14589,AMPL_WIDTH),
conv_std_logic_vector(14592,AMPL_WIDTH),
conv_std_logic_vector(14595,AMPL_WIDTH),
conv_std_logic_vector(14598,AMPL_WIDTH),
conv_std_logic_vector(14600,AMPL_WIDTH),
conv_std_logic_vector(14603,AMPL_WIDTH),
conv_std_logic_vector(14606,AMPL_WIDTH),
conv_std_logic_vector(14609,AMPL_WIDTH),
conv_std_logic_vector(14612,AMPL_WIDTH),
conv_std_logic_vector(14614,AMPL_WIDTH),
conv_std_logic_vector(14617,AMPL_WIDTH),
conv_std_logic_vector(14620,AMPL_WIDTH),
conv_std_logic_vector(14623,AMPL_WIDTH),
conv_std_logic_vector(14626,AMPL_WIDTH),
conv_std_logic_vector(14628,AMPL_WIDTH),
conv_std_logic_vector(14631,AMPL_WIDTH),
conv_std_logic_vector(14634,AMPL_WIDTH),
conv_std_logic_vector(14637,AMPL_WIDTH),
conv_std_logic_vector(14640,AMPL_WIDTH),
conv_std_logic_vector(14643,AMPL_WIDTH),
conv_std_logic_vector(14645,AMPL_WIDTH),
conv_std_logic_vector(14648,AMPL_WIDTH),
conv_std_logic_vector(14651,AMPL_WIDTH),
conv_std_logic_vector(14654,AMPL_WIDTH),
conv_std_logic_vector(14657,AMPL_WIDTH),
conv_std_logic_vector(14659,AMPL_WIDTH),
conv_std_logic_vector(14662,AMPL_WIDTH),
conv_std_logic_vector(14665,AMPL_WIDTH),
conv_std_logic_vector(14668,AMPL_WIDTH),
conv_std_logic_vector(14671,AMPL_WIDTH),
conv_std_logic_vector(14673,AMPL_WIDTH),
conv_std_logic_vector(14676,AMPL_WIDTH),
conv_std_logic_vector(14679,AMPL_WIDTH),
conv_std_logic_vector(14682,AMPL_WIDTH),
conv_std_logic_vector(14685,AMPL_WIDTH),
conv_std_logic_vector(14688,AMPL_WIDTH),
conv_std_logic_vector(14690,AMPL_WIDTH),
conv_std_logic_vector(14693,AMPL_WIDTH),
conv_std_logic_vector(14696,AMPL_WIDTH),
conv_std_logic_vector(14699,AMPL_WIDTH),
conv_std_logic_vector(14702,AMPL_WIDTH),
conv_std_logic_vector(14704,AMPL_WIDTH),
conv_std_logic_vector(14707,AMPL_WIDTH),
conv_std_logic_vector(14710,AMPL_WIDTH),
conv_std_logic_vector(14713,AMPL_WIDTH),
conv_std_logic_vector(14716,AMPL_WIDTH),
conv_std_logic_vector(14718,AMPL_WIDTH),
conv_std_logic_vector(14721,AMPL_WIDTH),
conv_std_logic_vector(14724,AMPL_WIDTH),
conv_std_logic_vector(14727,AMPL_WIDTH),
conv_std_logic_vector(14730,AMPL_WIDTH),
conv_std_logic_vector(14732,AMPL_WIDTH),
conv_std_logic_vector(14735,AMPL_WIDTH),
conv_std_logic_vector(14738,AMPL_WIDTH),
conv_std_logic_vector(14741,AMPL_WIDTH),
conv_std_logic_vector(14744,AMPL_WIDTH),
conv_std_logic_vector(14746,AMPL_WIDTH),
conv_std_logic_vector(14749,AMPL_WIDTH),
conv_std_logic_vector(14752,AMPL_WIDTH),
conv_std_logic_vector(14755,AMPL_WIDTH),
conv_std_logic_vector(14758,AMPL_WIDTH),
conv_std_logic_vector(14760,AMPL_WIDTH),
conv_std_logic_vector(14763,AMPL_WIDTH),
conv_std_logic_vector(14766,AMPL_WIDTH),
conv_std_logic_vector(14769,AMPL_WIDTH),
conv_std_logic_vector(14772,AMPL_WIDTH),
conv_std_logic_vector(14774,AMPL_WIDTH),
conv_std_logic_vector(14777,AMPL_WIDTH),
conv_std_logic_vector(14780,AMPL_WIDTH),
conv_std_logic_vector(14783,AMPL_WIDTH),
conv_std_logic_vector(14786,AMPL_WIDTH),
conv_std_logic_vector(14789,AMPL_WIDTH),
conv_std_logic_vector(14791,AMPL_WIDTH),
conv_std_logic_vector(14794,AMPL_WIDTH),
conv_std_logic_vector(14797,AMPL_WIDTH),
conv_std_logic_vector(14800,AMPL_WIDTH),
conv_std_logic_vector(14803,AMPL_WIDTH),
conv_std_logic_vector(14805,AMPL_WIDTH),
conv_std_logic_vector(14808,AMPL_WIDTH),
conv_std_logic_vector(14811,AMPL_WIDTH),
conv_std_logic_vector(14814,AMPL_WIDTH),
conv_std_logic_vector(14817,AMPL_WIDTH),
conv_std_logic_vector(14819,AMPL_WIDTH),
conv_std_logic_vector(14822,AMPL_WIDTH),
conv_std_logic_vector(14825,AMPL_WIDTH),
conv_std_logic_vector(14828,AMPL_WIDTH),
conv_std_logic_vector(14831,AMPL_WIDTH),
conv_std_logic_vector(14833,AMPL_WIDTH),
conv_std_logic_vector(14836,AMPL_WIDTH),
conv_std_logic_vector(14839,AMPL_WIDTH),
conv_std_logic_vector(14842,AMPL_WIDTH),
conv_std_logic_vector(14845,AMPL_WIDTH),
conv_std_logic_vector(14847,AMPL_WIDTH),
conv_std_logic_vector(14850,AMPL_WIDTH),
conv_std_logic_vector(14853,AMPL_WIDTH),
conv_std_logic_vector(14856,AMPL_WIDTH),
conv_std_logic_vector(14859,AMPL_WIDTH),
conv_std_logic_vector(14861,AMPL_WIDTH),
conv_std_logic_vector(14864,AMPL_WIDTH),
conv_std_logic_vector(14867,AMPL_WIDTH),
conv_std_logic_vector(14870,AMPL_WIDTH),
conv_std_logic_vector(14873,AMPL_WIDTH),
conv_std_logic_vector(14875,AMPL_WIDTH),
conv_std_logic_vector(14878,AMPL_WIDTH),
conv_std_logic_vector(14881,AMPL_WIDTH),
conv_std_logic_vector(14884,AMPL_WIDTH),
conv_std_logic_vector(14887,AMPL_WIDTH),
conv_std_logic_vector(14889,AMPL_WIDTH),
conv_std_logic_vector(14892,AMPL_WIDTH),
conv_std_logic_vector(14895,AMPL_WIDTH),
conv_std_logic_vector(14898,AMPL_WIDTH),
conv_std_logic_vector(14901,AMPL_WIDTH),
conv_std_logic_vector(14903,AMPL_WIDTH),
conv_std_logic_vector(14906,AMPL_WIDTH),
conv_std_logic_vector(14909,AMPL_WIDTH),
conv_std_logic_vector(14912,AMPL_WIDTH),
conv_std_logic_vector(14915,AMPL_WIDTH),
conv_std_logic_vector(14917,AMPL_WIDTH),
conv_std_logic_vector(14920,AMPL_WIDTH),
conv_std_logic_vector(14923,AMPL_WIDTH),
conv_std_logic_vector(14926,AMPL_WIDTH),
conv_std_logic_vector(14929,AMPL_WIDTH),
conv_std_logic_vector(14931,AMPL_WIDTH),
conv_std_logic_vector(14934,AMPL_WIDTH),
conv_std_logic_vector(14937,AMPL_WIDTH),
conv_std_logic_vector(14940,AMPL_WIDTH),
conv_std_logic_vector(14942,AMPL_WIDTH),
conv_std_logic_vector(14945,AMPL_WIDTH),
conv_std_logic_vector(14948,AMPL_WIDTH),
conv_std_logic_vector(14951,AMPL_WIDTH),
conv_std_logic_vector(14954,AMPL_WIDTH),
conv_std_logic_vector(14956,AMPL_WIDTH),
conv_std_logic_vector(14959,AMPL_WIDTH),
conv_std_logic_vector(14962,AMPL_WIDTH),
conv_std_logic_vector(14965,AMPL_WIDTH),
conv_std_logic_vector(14968,AMPL_WIDTH),
conv_std_logic_vector(14970,AMPL_WIDTH),
conv_std_logic_vector(14973,AMPL_WIDTH),
conv_std_logic_vector(14976,AMPL_WIDTH),
conv_std_logic_vector(14979,AMPL_WIDTH),
conv_std_logic_vector(14982,AMPL_WIDTH),
conv_std_logic_vector(14984,AMPL_WIDTH),
conv_std_logic_vector(14987,AMPL_WIDTH),
conv_std_logic_vector(14990,AMPL_WIDTH),
conv_std_logic_vector(14993,AMPL_WIDTH),
conv_std_logic_vector(14996,AMPL_WIDTH),
conv_std_logic_vector(14998,AMPL_WIDTH),
conv_std_logic_vector(15001,AMPL_WIDTH),
conv_std_logic_vector(15004,AMPL_WIDTH),
conv_std_logic_vector(15007,AMPL_WIDTH),
conv_std_logic_vector(15010,AMPL_WIDTH),
conv_std_logic_vector(15012,AMPL_WIDTH),
conv_std_logic_vector(15015,AMPL_WIDTH),
conv_std_logic_vector(15018,AMPL_WIDTH),
conv_std_logic_vector(15021,AMPL_WIDTH),
conv_std_logic_vector(15024,AMPL_WIDTH),
conv_std_logic_vector(15026,AMPL_WIDTH),
conv_std_logic_vector(15029,AMPL_WIDTH),
conv_std_logic_vector(15032,AMPL_WIDTH),
conv_std_logic_vector(15035,AMPL_WIDTH),
conv_std_logic_vector(15037,AMPL_WIDTH),
conv_std_logic_vector(15040,AMPL_WIDTH),
conv_std_logic_vector(15043,AMPL_WIDTH),
conv_std_logic_vector(15046,AMPL_WIDTH),
conv_std_logic_vector(15049,AMPL_WIDTH),
conv_std_logic_vector(15051,AMPL_WIDTH),
conv_std_logic_vector(15054,AMPL_WIDTH),
conv_std_logic_vector(15057,AMPL_WIDTH),
conv_std_logic_vector(15060,AMPL_WIDTH),
conv_std_logic_vector(15063,AMPL_WIDTH),
conv_std_logic_vector(15065,AMPL_WIDTH),
conv_std_logic_vector(15068,AMPL_WIDTH),
conv_std_logic_vector(15071,AMPL_WIDTH),
conv_std_logic_vector(15074,AMPL_WIDTH),
conv_std_logic_vector(15077,AMPL_WIDTH),
conv_std_logic_vector(15079,AMPL_WIDTH),
conv_std_logic_vector(15082,AMPL_WIDTH),
conv_std_logic_vector(15085,AMPL_WIDTH),
conv_std_logic_vector(15088,AMPL_WIDTH),
conv_std_logic_vector(15090,AMPL_WIDTH),
conv_std_logic_vector(15093,AMPL_WIDTH),
conv_std_logic_vector(15096,AMPL_WIDTH),
conv_std_logic_vector(15099,AMPL_WIDTH),
conv_std_logic_vector(15102,AMPL_WIDTH),
conv_std_logic_vector(15104,AMPL_WIDTH),
conv_std_logic_vector(15107,AMPL_WIDTH),
conv_std_logic_vector(15110,AMPL_WIDTH),
conv_std_logic_vector(15113,AMPL_WIDTH),
conv_std_logic_vector(15116,AMPL_WIDTH),
conv_std_logic_vector(15118,AMPL_WIDTH),
conv_std_logic_vector(15121,AMPL_WIDTH),
conv_std_logic_vector(15124,AMPL_WIDTH),
conv_std_logic_vector(15127,AMPL_WIDTH),
conv_std_logic_vector(15129,AMPL_WIDTH),
conv_std_logic_vector(15132,AMPL_WIDTH),
conv_std_logic_vector(15135,AMPL_WIDTH),
conv_std_logic_vector(15138,AMPL_WIDTH),
conv_std_logic_vector(15141,AMPL_WIDTH),
conv_std_logic_vector(15143,AMPL_WIDTH),
conv_std_logic_vector(15146,AMPL_WIDTH),
conv_std_logic_vector(15149,AMPL_WIDTH),
conv_std_logic_vector(15152,AMPL_WIDTH),
conv_std_logic_vector(15155,AMPL_WIDTH),
conv_std_logic_vector(15157,AMPL_WIDTH),
conv_std_logic_vector(15160,AMPL_WIDTH),
conv_std_logic_vector(15163,AMPL_WIDTH),
conv_std_logic_vector(15166,AMPL_WIDTH),
conv_std_logic_vector(15168,AMPL_WIDTH),
conv_std_logic_vector(15171,AMPL_WIDTH),
conv_std_logic_vector(15174,AMPL_WIDTH),
conv_std_logic_vector(15177,AMPL_WIDTH),
conv_std_logic_vector(15180,AMPL_WIDTH),
conv_std_logic_vector(15182,AMPL_WIDTH),
conv_std_logic_vector(15185,AMPL_WIDTH),
conv_std_logic_vector(15188,AMPL_WIDTH),
conv_std_logic_vector(15191,AMPL_WIDTH),
conv_std_logic_vector(15194,AMPL_WIDTH),
conv_std_logic_vector(15196,AMPL_WIDTH),
conv_std_logic_vector(15199,AMPL_WIDTH),
conv_std_logic_vector(15202,AMPL_WIDTH),
conv_std_logic_vector(15205,AMPL_WIDTH),
conv_std_logic_vector(15207,AMPL_WIDTH),
conv_std_logic_vector(15210,AMPL_WIDTH),
conv_std_logic_vector(15213,AMPL_WIDTH),
conv_std_logic_vector(15216,AMPL_WIDTH),
conv_std_logic_vector(15219,AMPL_WIDTH),
conv_std_logic_vector(15221,AMPL_WIDTH),
conv_std_logic_vector(15224,AMPL_WIDTH),
conv_std_logic_vector(15227,AMPL_WIDTH),
conv_std_logic_vector(15230,AMPL_WIDTH),
conv_std_logic_vector(15233,AMPL_WIDTH),
conv_std_logic_vector(15235,AMPL_WIDTH),
conv_std_logic_vector(15238,AMPL_WIDTH),
conv_std_logic_vector(15241,AMPL_WIDTH),
conv_std_logic_vector(15244,AMPL_WIDTH),
conv_std_logic_vector(15246,AMPL_WIDTH),
conv_std_logic_vector(15249,AMPL_WIDTH),
conv_std_logic_vector(15252,AMPL_WIDTH),
conv_std_logic_vector(15255,AMPL_WIDTH),
conv_std_logic_vector(15258,AMPL_WIDTH),
conv_std_logic_vector(15260,AMPL_WIDTH),
conv_std_logic_vector(15263,AMPL_WIDTH),
conv_std_logic_vector(15266,AMPL_WIDTH),
conv_std_logic_vector(15269,AMPL_WIDTH),
conv_std_logic_vector(15271,AMPL_WIDTH),
conv_std_logic_vector(15274,AMPL_WIDTH),
conv_std_logic_vector(15277,AMPL_WIDTH),
conv_std_logic_vector(15280,AMPL_WIDTH),
conv_std_logic_vector(15283,AMPL_WIDTH),
conv_std_logic_vector(15285,AMPL_WIDTH),
conv_std_logic_vector(15288,AMPL_WIDTH),
conv_std_logic_vector(15291,AMPL_WIDTH),
conv_std_logic_vector(15294,AMPL_WIDTH),
conv_std_logic_vector(15296,AMPL_WIDTH),
conv_std_logic_vector(15299,AMPL_WIDTH),
conv_std_logic_vector(15302,AMPL_WIDTH),
conv_std_logic_vector(15305,AMPL_WIDTH),
conv_std_logic_vector(15308,AMPL_WIDTH),
conv_std_logic_vector(15310,AMPL_WIDTH),
conv_std_logic_vector(15313,AMPL_WIDTH),
conv_std_logic_vector(15316,AMPL_WIDTH),
conv_std_logic_vector(15319,AMPL_WIDTH),
conv_std_logic_vector(15321,AMPL_WIDTH),
conv_std_logic_vector(15324,AMPL_WIDTH),
conv_std_logic_vector(15327,AMPL_WIDTH),
conv_std_logic_vector(15330,AMPL_WIDTH),
conv_std_logic_vector(15333,AMPL_WIDTH),
conv_std_logic_vector(15335,AMPL_WIDTH),
conv_std_logic_vector(15338,AMPL_WIDTH),
conv_std_logic_vector(15341,AMPL_WIDTH),
conv_std_logic_vector(15344,AMPL_WIDTH),
conv_std_logic_vector(15346,AMPL_WIDTH),
conv_std_logic_vector(15349,AMPL_WIDTH),
conv_std_logic_vector(15352,AMPL_WIDTH),
conv_std_logic_vector(15355,AMPL_WIDTH),
conv_std_logic_vector(15358,AMPL_WIDTH),
conv_std_logic_vector(15360,AMPL_WIDTH),
conv_std_logic_vector(15363,AMPL_WIDTH),
conv_std_logic_vector(15366,AMPL_WIDTH),
conv_std_logic_vector(15369,AMPL_WIDTH),
conv_std_logic_vector(15371,AMPL_WIDTH),
conv_std_logic_vector(15374,AMPL_WIDTH),
conv_std_logic_vector(15377,AMPL_WIDTH),
conv_std_logic_vector(15380,AMPL_WIDTH),
conv_std_logic_vector(15382,AMPL_WIDTH),
conv_std_logic_vector(15385,AMPL_WIDTH),
conv_std_logic_vector(15388,AMPL_WIDTH),
conv_std_logic_vector(15391,AMPL_WIDTH),
conv_std_logic_vector(15394,AMPL_WIDTH),
conv_std_logic_vector(15396,AMPL_WIDTH),
conv_std_logic_vector(15399,AMPL_WIDTH),
conv_std_logic_vector(15402,AMPL_WIDTH),
conv_std_logic_vector(15405,AMPL_WIDTH),
conv_std_logic_vector(15407,AMPL_WIDTH),
conv_std_logic_vector(15410,AMPL_WIDTH),
conv_std_logic_vector(15413,AMPL_WIDTH),
conv_std_logic_vector(15416,AMPL_WIDTH),
conv_std_logic_vector(15419,AMPL_WIDTH),
conv_std_logic_vector(15421,AMPL_WIDTH),
conv_std_logic_vector(15424,AMPL_WIDTH),
conv_std_logic_vector(15427,AMPL_WIDTH),
conv_std_logic_vector(15430,AMPL_WIDTH),
conv_std_logic_vector(15432,AMPL_WIDTH),
conv_std_logic_vector(15435,AMPL_WIDTH),
conv_std_logic_vector(15438,AMPL_WIDTH),
conv_std_logic_vector(15441,AMPL_WIDTH),
conv_std_logic_vector(15443,AMPL_WIDTH),
conv_std_logic_vector(15446,AMPL_WIDTH),
conv_std_logic_vector(15449,AMPL_WIDTH),
conv_std_logic_vector(15452,AMPL_WIDTH),
conv_std_logic_vector(15455,AMPL_WIDTH),
conv_std_logic_vector(15457,AMPL_WIDTH),
conv_std_logic_vector(15460,AMPL_WIDTH),
conv_std_logic_vector(15463,AMPL_WIDTH),
conv_std_logic_vector(15466,AMPL_WIDTH),
conv_std_logic_vector(15468,AMPL_WIDTH),
conv_std_logic_vector(15471,AMPL_WIDTH),
conv_std_logic_vector(15474,AMPL_WIDTH),
conv_std_logic_vector(15477,AMPL_WIDTH),
conv_std_logic_vector(15479,AMPL_WIDTH),
conv_std_logic_vector(15482,AMPL_WIDTH),
conv_std_logic_vector(15485,AMPL_WIDTH),
conv_std_logic_vector(15488,AMPL_WIDTH),
conv_std_logic_vector(15491,AMPL_WIDTH),
conv_std_logic_vector(15493,AMPL_WIDTH),
conv_std_logic_vector(15496,AMPL_WIDTH),
conv_std_logic_vector(15499,AMPL_WIDTH),
conv_std_logic_vector(15502,AMPL_WIDTH),
conv_std_logic_vector(15504,AMPL_WIDTH),
conv_std_logic_vector(15507,AMPL_WIDTH),
conv_std_logic_vector(15510,AMPL_WIDTH),
conv_std_logic_vector(15513,AMPL_WIDTH),
conv_std_logic_vector(15515,AMPL_WIDTH),
conv_std_logic_vector(15518,AMPL_WIDTH),
conv_std_logic_vector(15521,AMPL_WIDTH),
conv_std_logic_vector(15524,AMPL_WIDTH),
conv_std_logic_vector(15527,AMPL_WIDTH),
conv_std_logic_vector(15529,AMPL_WIDTH),
conv_std_logic_vector(15532,AMPL_WIDTH),
conv_std_logic_vector(15535,AMPL_WIDTH),
conv_std_logic_vector(15538,AMPL_WIDTH),
conv_std_logic_vector(15540,AMPL_WIDTH),
conv_std_logic_vector(15543,AMPL_WIDTH),
conv_std_logic_vector(15546,AMPL_WIDTH),
conv_std_logic_vector(15549,AMPL_WIDTH),
conv_std_logic_vector(15551,AMPL_WIDTH),
conv_std_logic_vector(15554,AMPL_WIDTH),
conv_std_logic_vector(15557,AMPL_WIDTH),
conv_std_logic_vector(15560,AMPL_WIDTH),
conv_std_logic_vector(15562,AMPL_WIDTH),
conv_std_logic_vector(15565,AMPL_WIDTH),
conv_std_logic_vector(15568,AMPL_WIDTH),
conv_std_logic_vector(15571,AMPL_WIDTH),
conv_std_logic_vector(15574,AMPL_WIDTH),
conv_std_logic_vector(15576,AMPL_WIDTH),
conv_std_logic_vector(15579,AMPL_WIDTH),
conv_std_logic_vector(15582,AMPL_WIDTH),
conv_std_logic_vector(15585,AMPL_WIDTH),
conv_std_logic_vector(15587,AMPL_WIDTH),
conv_std_logic_vector(15590,AMPL_WIDTH),
conv_std_logic_vector(15593,AMPL_WIDTH),
conv_std_logic_vector(15596,AMPL_WIDTH),
conv_std_logic_vector(15598,AMPL_WIDTH),
conv_std_logic_vector(15601,AMPL_WIDTH),
conv_std_logic_vector(15604,AMPL_WIDTH),
conv_std_logic_vector(15607,AMPL_WIDTH),
conv_std_logic_vector(15609,AMPL_WIDTH),
conv_std_logic_vector(15612,AMPL_WIDTH),
conv_std_logic_vector(15615,AMPL_WIDTH),
conv_std_logic_vector(15618,AMPL_WIDTH),
conv_std_logic_vector(15621,AMPL_WIDTH),
conv_std_logic_vector(15623,AMPL_WIDTH),
conv_std_logic_vector(15626,AMPL_WIDTH),
conv_std_logic_vector(15629,AMPL_WIDTH),
conv_std_logic_vector(15632,AMPL_WIDTH),
conv_std_logic_vector(15634,AMPL_WIDTH),
conv_std_logic_vector(15637,AMPL_WIDTH),
conv_std_logic_vector(15640,AMPL_WIDTH),
conv_std_logic_vector(15643,AMPL_WIDTH),
conv_std_logic_vector(15645,AMPL_WIDTH),
conv_std_logic_vector(15648,AMPL_WIDTH),
conv_std_logic_vector(15651,AMPL_WIDTH),
conv_std_logic_vector(15654,AMPL_WIDTH),
conv_std_logic_vector(15656,AMPL_WIDTH),
conv_std_logic_vector(15659,AMPL_WIDTH),
conv_std_logic_vector(15662,AMPL_WIDTH),
conv_std_logic_vector(15665,AMPL_WIDTH),
conv_std_logic_vector(15667,AMPL_WIDTH),
conv_std_logic_vector(15670,AMPL_WIDTH),
conv_std_logic_vector(15673,AMPL_WIDTH),
conv_std_logic_vector(15676,AMPL_WIDTH),
conv_std_logic_vector(15678,AMPL_WIDTH),
conv_std_logic_vector(15681,AMPL_WIDTH),
conv_std_logic_vector(15684,AMPL_WIDTH),
conv_std_logic_vector(15687,AMPL_WIDTH),
conv_std_logic_vector(15690,AMPL_WIDTH),
conv_std_logic_vector(15692,AMPL_WIDTH),
conv_std_logic_vector(15695,AMPL_WIDTH),
conv_std_logic_vector(15698,AMPL_WIDTH),
conv_std_logic_vector(15701,AMPL_WIDTH),
conv_std_logic_vector(15703,AMPL_WIDTH),
conv_std_logic_vector(15706,AMPL_WIDTH),
conv_std_logic_vector(15709,AMPL_WIDTH),
conv_std_logic_vector(15712,AMPL_WIDTH),
conv_std_logic_vector(15714,AMPL_WIDTH),
conv_std_logic_vector(15717,AMPL_WIDTH),
conv_std_logic_vector(15720,AMPL_WIDTH),
conv_std_logic_vector(15723,AMPL_WIDTH),
conv_std_logic_vector(15725,AMPL_WIDTH),
conv_std_logic_vector(15728,AMPL_WIDTH),
conv_std_logic_vector(15731,AMPL_WIDTH),
conv_std_logic_vector(15734,AMPL_WIDTH),
conv_std_logic_vector(15736,AMPL_WIDTH),
conv_std_logic_vector(15739,AMPL_WIDTH),
conv_std_logic_vector(15742,AMPL_WIDTH),
conv_std_logic_vector(15745,AMPL_WIDTH),
conv_std_logic_vector(15747,AMPL_WIDTH),
conv_std_logic_vector(15750,AMPL_WIDTH),
conv_std_logic_vector(15753,AMPL_WIDTH),
conv_std_logic_vector(15756,AMPL_WIDTH),
conv_std_logic_vector(15758,AMPL_WIDTH),
conv_std_logic_vector(15761,AMPL_WIDTH),
conv_std_logic_vector(15764,AMPL_WIDTH),
conv_std_logic_vector(15767,AMPL_WIDTH),
conv_std_logic_vector(15769,AMPL_WIDTH),
conv_std_logic_vector(15772,AMPL_WIDTH),
conv_std_logic_vector(15775,AMPL_WIDTH),
conv_std_logic_vector(15778,AMPL_WIDTH),
conv_std_logic_vector(15780,AMPL_WIDTH),
conv_std_logic_vector(15783,AMPL_WIDTH),
conv_std_logic_vector(15786,AMPL_WIDTH),
conv_std_logic_vector(15789,AMPL_WIDTH),
conv_std_logic_vector(15791,AMPL_WIDTH),
conv_std_logic_vector(15794,AMPL_WIDTH),
conv_std_logic_vector(15797,AMPL_WIDTH),
conv_std_logic_vector(15800,AMPL_WIDTH),
conv_std_logic_vector(15802,AMPL_WIDTH),
conv_std_logic_vector(15805,AMPL_WIDTH),
conv_std_logic_vector(15808,AMPL_WIDTH),
conv_std_logic_vector(15811,AMPL_WIDTH),
conv_std_logic_vector(15813,AMPL_WIDTH),
conv_std_logic_vector(15816,AMPL_WIDTH),
conv_std_logic_vector(15819,AMPL_WIDTH),
conv_std_logic_vector(15822,AMPL_WIDTH),
conv_std_logic_vector(15824,AMPL_WIDTH),
conv_std_logic_vector(15827,AMPL_WIDTH),
conv_std_logic_vector(15830,AMPL_WIDTH),
conv_std_logic_vector(15833,AMPL_WIDTH),
conv_std_logic_vector(15835,AMPL_WIDTH),
conv_std_logic_vector(15838,AMPL_WIDTH),
conv_std_logic_vector(15841,AMPL_WIDTH),
conv_std_logic_vector(15844,AMPL_WIDTH),
conv_std_logic_vector(15846,AMPL_WIDTH),
conv_std_logic_vector(15849,AMPL_WIDTH),
conv_std_logic_vector(15852,AMPL_WIDTH),
conv_std_logic_vector(15855,AMPL_WIDTH),
conv_std_logic_vector(15857,AMPL_WIDTH),
conv_std_logic_vector(15860,AMPL_WIDTH),
conv_std_logic_vector(15863,AMPL_WIDTH),
conv_std_logic_vector(15866,AMPL_WIDTH),
conv_std_logic_vector(15868,AMPL_WIDTH),
conv_std_logic_vector(15871,AMPL_WIDTH),
conv_std_logic_vector(15874,AMPL_WIDTH),
conv_std_logic_vector(15877,AMPL_WIDTH),
conv_std_logic_vector(15879,AMPL_WIDTH),
conv_std_logic_vector(15882,AMPL_WIDTH),
conv_std_logic_vector(15885,AMPL_WIDTH),
conv_std_logic_vector(15888,AMPL_WIDTH),
conv_std_logic_vector(15890,AMPL_WIDTH),
conv_std_logic_vector(15893,AMPL_WIDTH),
conv_std_logic_vector(15896,AMPL_WIDTH),
conv_std_logic_vector(15899,AMPL_WIDTH),
conv_std_logic_vector(15901,AMPL_WIDTH),
conv_std_logic_vector(15904,AMPL_WIDTH),
conv_std_logic_vector(15907,AMPL_WIDTH),
conv_std_logic_vector(15910,AMPL_WIDTH),
conv_std_logic_vector(15912,AMPL_WIDTH),
conv_std_logic_vector(15915,AMPL_WIDTH),
conv_std_logic_vector(15918,AMPL_WIDTH),
conv_std_logic_vector(15921,AMPL_WIDTH),
conv_std_logic_vector(15923,AMPL_WIDTH),
conv_std_logic_vector(15926,AMPL_WIDTH),
conv_std_logic_vector(15929,AMPL_WIDTH),
conv_std_logic_vector(15932,AMPL_WIDTH),
conv_std_logic_vector(15934,AMPL_WIDTH),
conv_std_logic_vector(15937,AMPL_WIDTH),
conv_std_logic_vector(15940,AMPL_WIDTH),
conv_std_logic_vector(15943,AMPL_WIDTH),
conv_std_logic_vector(15945,AMPL_WIDTH),
conv_std_logic_vector(15948,AMPL_WIDTH),
conv_std_logic_vector(15951,AMPL_WIDTH),
conv_std_logic_vector(15954,AMPL_WIDTH),
conv_std_logic_vector(15956,AMPL_WIDTH),
conv_std_logic_vector(15959,AMPL_WIDTH),
conv_std_logic_vector(15962,AMPL_WIDTH),
conv_std_logic_vector(15965,AMPL_WIDTH),
conv_std_logic_vector(15967,AMPL_WIDTH),
conv_std_logic_vector(15970,AMPL_WIDTH),
conv_std_logic_vector(15973,AMPL_WIDTH),
conv_std_logic_vector(15976,AMPL_WIDTH),
conv_std_logic_vector(15978,AMPL_WIDTH),
conv_std_logic_vector(15981,AMPL_WIDTH),
conv_std_logic_vector(15984,AMPL_WIDTH),
conv_std_logic_vector(15987,AMPL_WIDTH),
conv_std_logic_vector(15989,AMPL_WIDTH),
conv_std_logic_vector(15992,AMPL_WIDTH),
conv_std_logic_vector(15995,AMPL_WIDTH),
conv_std_logic_vector(15997,AMPL_WIDTH),
conv_std_logic_vector(16000,AMPL_WIDTH),
conv_std_logic_vector(16003,AMPL_WIDTH),
conv_std_logic_vector(16006,AMPL_WIDTH),
conv_std_logic_vector(16008,AMPL_WIDTH),
conv_std_logic_vector(16011,AMPL_WIDTH),
conv_std_logic_vector(16014,AMPL_WIDTH),
conv_std_logic_vector(16017,AMPL_WIDTH),
conv_std_logic_vector(16019,AMPL_WIDTH),
conv_std_logic_vector(16022,AMPL_WIDTH),
conv_std_logic_vector(16025,AMPL_WIDTH),
conv_std_logic_vector(16028,AMPL_WIDTH),
conv_std_logic_vector(16030,AMPL_WIDTH),
conv_std_logic_vector(16033,AMPL_WIDTH),
conv_std_logic_vector(16036,AMPL_WIDTH),
conv_std_logic_vector(16039,AMPL_WIDTH),
conv_std_logic_vector(16041,AMPL_WIDTH),
conv_std_logic_vector(16044,AMPL_WIDTH),
conv_std_logic_vector(16047,AMPL_WIDTH),
conv_std_logic_vector(16050,AMPL_WIDTH),
conv_std_logic_vector(16052,AMPL_WIDTH),
conv_std_logic_vector(16055,AMPL_WIDTH),
conv_std_logic_vector(16058,AMPL_WIDTH),
conv_std_logic_vector(16061,AMPL_WIDTH),
conv_std_logic_vector(16063,AMPL_WIDTH),
conv_std_logic_vector(16066,AMPL_WIDTH),
conv_std_logic_vector(16069,AMPL_WIDTH),
conv_std_logic_vector(16071,AMPL_WIDTH),
conv_std_logic_vector(16074,AMPL_WIDTH),
conv_std_logic_vector(16077,AMPL_WIDTH),
conv_std_logic_vector(16080,AMPL_WIDTH),
conv_std_logic_vector(16082,AMPL_WIDTH),
conv_std_logic_vector(16085,AMPL_WIDTH),
conv_std_logic_vector(16088,AMPL_WIDTH),
conv_std_logic_vector(16091,AMPL_WIDTH),
conv_std_logic_vector(16093,AMPL_WIDTH),
conv_std_logic_vector(16096,AMPL_WIDTH),
conv_std_logic_vector(16099,AMPL_WIDTH),
conv_std_logic_vector(16102,AMPL_WIDTH),
conv_std_logic_vector(16104,AMPL_WIDTH),
conv_std_logic_vector(16107,AMPL_WIDTH),
conv_std_logic_vector(16110,AMPL_WIDTH),
conv_std_logic_vector(16113,AMPL_WIDTH),
conv_std_logic_vector(16115,AMPL_WIDTH),
conv_std_logic_vector(16118,AMPL_WIDTH),
conv_std_logic_vector(16121,AMPL_WIDTH),
conv_std_logic_vector(16123,AMPL_WIDTH),
conv_std_logic_vector(16126,AMPL_WIDTH),
conv_std_logic_vector(16129,AMPL_WIDTH),
conv_std_logic_vector(16132,AMPL_WIDTH),
conv_std_logic_vector(16134,AMPL_WIDTH),
conv_std_logic_vector(16137,AMPL_WIDTH),
conv_std_logic_vector(16140,AMPL_WIDTH),
conv_std_logic_vector(16143,AMPL_WIDTH),
conv_std_logic_vector(16145,AMPL_WIDTH),
conv_std_logic_vector(16148,AMPL_WIDTH),
conv_std_logic_vector(16151,AMPL_WIDTH),
conv_std_logic_vector(16154,AMPL_WIDTH),
conv_std_logic_vector(16156,AMPL_WIDTH),
conv_std_logic_vector(16159,AMPL_WIDTH),
conv_std_logic_vector(16162,AMPL_WIDTH),
conv_std_logic_vector(16164,AMPL_WIDTH),
conv_std_logic_vector(16167,AMPL_WIDTH),
conv_std_logic_vector(16170,AMPL_WIDTH),
conv_std_logic_vector(16173,AMPL_WIDTH),
conv_std_logic_vector(16175,AMPL_WIDTH),
conv_std_logic_vector(16178,AMPL_WIDTH),
conv_std_logic_vector(16181,AMPL_WIDTH),
conv_std_logic_vector(16184,AMPL_WIDTH),
conv_std_logic_vector(16186,AMPL_WIDTH),
conv_std_logic_vector(16189,AMPL_WIDTH),
conv_std_logic_vector(16192,AMPL_WIDTH),
conv_std_logic_vector(16195,AMPL_WIDTH),
conv_std_logic_vector(16197,AMPL_WIDTH),
conv_std_logic_vector(16200,AMPL_WIDTH),
conv_std_logic_vector(16203,AMPL_WIDTH),
conv_std_logic_vector(16205,AMPL_WIDTH),
conv_std_logic_vector(16208,AMPL_WIDTH),
conv_std_logic_vector(16211,AMPL_WIDTH),
conv_std_logic_vector(16214,AMPL_WIDTH),
conv_std_logic_vector(16216,AMPL_WIDTH),
conv_std_logic_vector(16219,AMPL_WIDTH),
conv_std_logic_vector(16222,AMPL_WIDTH),
conv_std_logic_vector(16225,AMPL_WIDTH),
conv_std_logic_vector(16227,AMPL_WIDTH),
conv_std_logic_vector(16230,AMPL_WIDTH),
conv_std_logic_vector(16233,AMPL_WIDTH),
conv_std_logic_vector(16235,AMPL_WIDTH),
conv_std_logic_vector(16238,AMPL_WIDTH),
conv_std_logic_vector(16241,AMPL_WIDTH),
conv_std_logic_vector(16244,AMPL_WIDTH),
conv_std_logic_vector(16246,AMPL_WIDTH),
conv_std_logic_vector(16249,AMPL_WIDTH),
conv_std_logic_vector(16252,AMPL_WIDTH),
conv_std_logic_vector(16255,AMPL_WIDTH),
conv_std_logic_vector(16257,AMPL_WIDTH),
conv_std_logic_vector(16260,AMPL_WIDTH),
conv_std_logic_vector(16263,AMPL_WIDTH),
conv_std_logic_vector(16265,AMPL_WIDTH),
conv_std_logic_vector(16268,AMPL_WIDTH),
conv_std_logic_vector(16271,AMPL_WIDTH),
conv_std_logic_vector(16274,AMPL_WIDTH),
conv_std_logic_vector(16276,AMPL_WIDTH),
conv_std_logic_vector(16279,AMPL_WIDTH),
conv_std_logic_vector(16282,AMPL_WIDTH),
conv_std_logic_vector(16285,AMPL_WIDTH),
conv_std_logic_vector(16287,AMPL_WIDTH),
conv_std_logic_vector(16290,AMPL_WIDTH),
conv_std_logic_vector(16293,AMPL_WIDTH),
conv_std_logic_vector(16295,AMPL_WIDTH),
conv_std_logic_vector(16298,AMPL_WIDTH),
conv_std_logic_vector(16301,AMPL_WIDTH),
conv_std_logic_vector(16304,AMPL_WIDTH),
conv_std_logic_vector(16306,AMPL_WIDTH),
conv_std_logic_vector(16309,AMPL_WIDTH),
conv_std_logic_vector(16312,AMPL_WIDTH),
conv_std_logic_vector(16315,AMPL_WIDTH),
conv_std_logic_vector(16317,AMPL_WIDTH),
conv_std_logic_vector(16320,AMPL_WIDTH),
conv_std_logic_vector(16323,AMPL_WIDTH),
conv_std_logic_vector(16325,AMPL_WIDTH),
conv_std_logic_vector(16328,AMPL_WIDTH),
conv_std_logic_vector(16331,AMPL_WIDTH),
conv_std_logic_vector(16334,AMPL_WIDTH),
conv_std_logic_vector(16336,AMPL_WIDTH),
conv_std_logic_vector(16339,AMPL_WIDTH),
conv_std_logic_vector(16342,AMPL_WIDTH),
conv_std_logic_vector(16344,AMPL_WIDTH),
conv_std_logic_vector(16347,AMPL_WIDTH),
conv_std_logic_vector(16350,AMPL_WIDTH),
conv_std_logic_vector(16353,AMPL_WIDTH),
conv_std_logic_vector(16355,AMPL_WIDTH),
conv_std_logic_vector(16358,AMPL_WIDTH),
conv_std_logic_vector(16361,AMPL_WIDTH),
conv_std_logic_vector(16364,AMPL_WIDTH),
conv_std_logic_vector(16366,AMPL_WIDTH),
conv_std_logic_vector(16369,AMPL_WIDTH),
conv_std_logic_vector(16372,AMPL_WIDTH),
conv_std_logic_vector(16374,AMPL_WIDTH),
conv_std_logic_vector(16377,AMPL_WIDTH),
conv_std_logic_vector(16380,AMPL_WIDTH),
conv_std_logic_vector(16383,AMPL_WIDTH),
conv_std_logic_vector(16385,AMPL_WIDTH),
conv_std_logic_vector(16388,AMPL_WIDTH),
conv_std_logic_vector(16391,AMPL_WIDTH),
conv_std_logic_vector(16393,AMPL_WIDTH),
conv_std_logic_vector(16396,AMPL_WIDTH),
conv_std_logic_vector(16399,AMPL_WIDTH),
conv_std_logic_vector(16402,AMPL_WIDTH),
conv_std_logic_vector(16404,AMPL_WIDTH),
conv_std_logic_vector(16407,AMPL_WIDTH),
conv_std_logic_vector(16410,AMPL_WIDTH),
conv_std_logic_vector(16413,AMPL_WIDTH),
conv_std_logic_vector(16415,AMPL_WIDTH),
conv_std_logic_vector(16418,AMPL_WIDTH),
conv_std_logic_vector(16421,AMPL_WIDTH),
conv_std_logic_vector(16423,AMPL_WIDTH),
conv_std_logic_vector(16426,AMPL_WIDTH),
conv_std_logic_vector(16429,AMPL_WIDTH),
conv_std_logic_vector(16432,AMPL_WIDTH),
conv_std_logic_vector(16434,AMPL_WIDTH),
conv_std_logic_vector(16437,AMPL_WIDTH),
conv_std_logic_vector(16440,AMPL_WIDTH),
conv_std_logic_vector(16442,AMPL_WIDTH),
conv_std_logic_vector(16445,AMPL_WIDTH),
conv_std_logic_vector(16448,AMPL_WIDTH),
conv_std_logic_vector(16451,AMPL_WIDTH),
conv_std_logic_vector(16453,AMPL_WIDTH),
conv_std_logic_vector(16456,AMPL_WIDTH),
conv_std_logic_vector(16459,AMPL_WIDTH),
conv_std_logic_vector(16461,AMPL_WIDTH),
conv_std_logic_vector(16464,AMPL_WIDTH),
conv_std_logic_vector(16467,AMPL_WIDTH),
conv_std_logic_vector(16470,AMPL_WIDTH),
conv_std_logic_vector(16472,AMPL_WIDTH),
conv_std_logic_vector(16475,AMPL_WIDTH),
conv_std_logic_vector(16478,AMPL_WIDTH),
conv_std_logic_vector(16480,AMPL_WIDTH),
conv_std_logic_vector(16483,AMPL_WIDTH),
conv_std_logic_vector(16486,AMPL_WIDTH),
conv_std_logic_vector(16489,AMPL_WIDTH),
conv_std_logic_vector(16491,AMPL_WIDTH),
conv_std_logic_vector(16494,AMPL_WIDTH),
conv_std_logic_vector(16497,AMPL_WIDTH),
conv_std_logic_vector(16499,AMPL_WIDTH),
conv_std_logic_vector(16502,AMPL_WIDTH),
conv_std_logic_vector(16505,AMPL_WIDTH),
conv_std_logic_vector(16508,AMPL_WIDTH),
conv_std_logic_vector(16510,AMPL_WIDTH),
conv_std_logic_vector(16513,AMPL_WIDTH),
conv_std_logic_vector(16516,AMPL_WIDTH),
conv_std_logic_vector(16518,AMPL_WIDTH),
conv_std_logic_vector(16521,AMPL_WIDTH),
conv_std_logic_vector(16524,AMPL_WIDTH),
conv_std_logic_vector(16527,AMPL_WIDTH),
conv_std_logic_vector(16529,AMPL_WIDTH),
conv_std_logic_vector(16532,AMPL_WIDTH),
conv_std_logic_vector(16535,AMPL_WIDTH),
conv_std_logic_vector(16537,AMPL_WIDTH),
conv_std_logic_vector(16540,AMPL_WIDTH),
conv_std_logic_vector(16543,AMPL_WIDTH),
conv_std_logic_vector(16546,AMPL_WIDTH),
conv_std_logic_vector(16548,AMPL_WIDTH),
conv_std_logic_vector(16551,AMPL_WIDTH),
conv_std_logic_vector(16554,AMPL_WIDTH),
conv_std_logic_vector(16556,AMPL_WIDTH),
conv_std_logic_vector(16559,AMPL_WIDTH),
conv_std_logic_vector(16562,AMPL_WIDTH),
conv_std_logic_vector(16565,AMPL_WIDTH),
conv_std_logic_vector(16567,AMPL_WIDTH),
conv_std_logic_vector(16570,AMPL_WIDTH),
conv_std_logic_vector(16573,AMPL_WIDTH),
conv_std_logic_vector(16575,AMPL_WIDTH),
conv_std_logic_vector(16578,AMPL_WIDTH),
conv_std_logic_vector(16581,AMPL_WIDTH),
conv_std_logic_vector(16584,AMPL_WIDTH),
conv_std_logic_vector(16586,AMPL_WIDTH),
conv_std_logic_vector(16589,AMPL_WIDTH),
conv_std_logic_vector(16592,AMPL_WIDTH),
conv_std_logic_vector(16594,AMPL_WIDTH),
conv_std_logic_vector(16597,AMPL_WIDTH),
conv_std_logic_vector(16600,AMPL_WIDTH),
conv_std_logic_vector(16602,AMPL_WIDTH),
conv_std_logic_vector(16605,AMPL_WIDTH),
conv_std_logic_vector(16608,AMPL_WIDTH),
conv_std_logic_vector(16611,AMPL_WIDTH),
conv_std_logic_vector(16613,AMPL_WIDTH),
conv_std_logic_vector(16616,AMPL_WIDTH),
conv_std_logic_vector(16619,AMPL_WIDTH),
conv_std_logic_vector(16621,AMPL_WIDTH),
conv_std_logic_vector(16624,AMPL_WIDTH),
conv_std_logic_vector(16627,AMPL_WIDTH),
conv_std_logic_vector(16630,AMPL_WIDTH),
conv_std_logic_vector(16632,AMPL_WIDTH),
conv_std_logic_vector(16635,AMPL_WIDTH),
conv_std_logic_vector(16638,AMPL_WIDTH),
conv_std_logic_vector(16640,AMPL_WIDTH),
conv_std_logic_vector(16643,AMPL_WIDTH),
conv_std_logic_vector(16646,AMPL_WIDTH),
conv_std_logic_vector(16648,AMPL_WIDTH),
conv_std_logic_vector(16651,AMPL_WIDTH),
conv_std_logic_vector(16654,AMPL_WIDTH),
conv_std_logic_vector(16657,AMPL_WIDTH),
conv_std_logic_vector(16659,AMPL_WIDTH),
conv_std_logic_vector(16662,AMPL_WIDTH),
conv_std_logic_vector(16665,AMPL_WIDTH),
conv_std_logic_vector(16667,AMPL_WIDTH),
conv_std_logic_vector(16670,AMPL_WIDTH),
conv_std_logic_vector(16673,AMPL_WIDTH),
conv_std_logic_vector(16676,AMPL_WIDTH),
conv_std_logic_vector(16678,AMPL_WIDTH),
conv_std_logic_vector(16681,AMPL_WIDTH),
conv_std_logic_vector(16684,AMPL_WIDTH),
conv_std_logic_vector(16686,AMPL_WIDTH),
conv_std_logic_vector(16689,AMPL_WIDTH),
conv_std_logic_vector(16692,AMPL_WIDTH),
conv_std_logic_vector(16694,AMPL_WIDTH),
conv_std_logic_vector(16697,AMPL_WIDTH),
conv_std_logic_vector(16700,AMPL_WIDTH),
conv_std_logic_vector(16703,AMPL_WIDTH),
conv_std_logic_vector(16705,AMPL_WIDTH),
conv_std_logic_vector(16708,AMPL_WIDTH),
conv_std_logic_vector(16711,AMPL_WIDTH),
conv_std_logic_vector(16713,AMPL_WIDTH),
conv_std_logic_vector(16716,AMPL_WIDTH),
conv_std_logic_vector(16719,AMPL_WIDTH),
conv_std_logic_vector(16721,AMPL_WIDTH),
conv_std_logic_vector(16724,AMPL_WIDTH),
conv_std_logic_vector(16727,AMPL_WIDTH),
conv_std_logic_vector(16730,AMPL_WIDTH),
conv_std_logic_vector(16732,AMPL_WIDTH),
conv_std_logic_vector(16735,AMPL_WIDTH),
conv_std_logic_vector(16738,AMPL_WIDTH),
conv_std_logic_vector(16740,AMPL_WIDTH),
conv_std_logic_vector(16743,AMPL_WIDTH),
conv_std_logic_vector(16746,AMPL_WIDTH),
conv_std_logic_vector(16749,AMPL_WIDTH),
conv_std_logic_vector(16751,AMPL_WIDTH),
conv_std_logic_vector(16754,AMPL_WIDTH),
conv_std_logic_vector(16757,AMPL_WIDTH),
conv_std_logic_vector(16759,AMPL_WIDTH),
conv_std_logic_vector(16762,AMPL_WIDTH),
conv_std_logic_vector(16765,AMPL_WIDTH),
conv_std_logic_vector(16767,AMPL_WIDTH),
conv_std_logic_vector(16770,AMPL_WIDTH),
conv_std_logic_vector(16773,AMPL_WIDTH),
conv_std_logic_vector(16775,AMPL_WIDTH),
conv_std_logic_vector(16778,AMPL_WIDTH),
conv_std_logic_vector(16781,AMPL_WIDTH),
conv_std_logic_vector(16784,AMPL_WIDTH),
conv_std_logic_vector(16786,AMPL_WIDTH),
conv_std_logic_vector(16789,AMPL_WIDTH),
conv_std_logic_vector(16792,AMPL_WIDTH),
conv_std_logic_vector(16794,AMPL_WIDTH),
conv_std_logic_vector(16797,AMPL_WIDTH),
conv_std_logic_vector(16800,AMPL_WIDTH),
conv_std_logic_vector(16802,AMPL_WIDTH),
conv_std_logic_vector(16805,AMPL_WIDTH),
conv_std_logic_vector(16808,AMPL_WIDTH),
conv_std_logic_vector(16811,AMPL_WIDTH),
conv_std_logic_vector(16813,AMPL_WIDTH),
conv_std_logic_vector(16816,AMPL_WIDTH),
conv_std_logic_vector(16819,AMPL_WIDTH),
conv_std_logic_vector(16821,AMPL_WIDTH),
conv_std_logic_vector(16824,AMPL_WIDTH),
conv_std_logic_vector(16827,AMPL_WIDTH),
conv_std_logic_vector(16829,AMPL_WIDTH),
conv_std_logic_vector(16832,AMPL_WIDTH),
conv_std_logic_vector(16835,AMPL_WIDTH),
conv_std_logic_vector(16838,AMPL_WIDTH),
conv_std_logic_vector(16840,AMPL_WIDTH),
conv_std_logic_vector(16843,AMPL_WIDTH),
conv_std_logic_vector(16846,AMPL_WIDTH),
conv_std_logic_vector(16848,AMPL_WIDTH),
conv_std_logic_vector(16851,AMPL_WIDTH),
conv_std_logic_vector(16854,AMPL_WIDTH),
conv_std_logic_vector(16856,AMPL_WIDTH),
conv_std_logic_vector(16859,AMPL_WIDTH),
conv_std_logic_vector(16862,AMPL_WIDTH),
conv_std_logic_vector(16864,AMPL_WIDTH),
conv_std_logic_vector(16867,AMPL_WIDTH),
conv_std_logic_vector(16870,AMPL_WIDTH),
conv_std_logic_vector(16873,AMPL_WIDTH),
conv_std_logic_vector(16875,AMPL_WIDTH),
conv_std_logic_vector(16878,AMPL_WIDTH),
conv_std_logic_vector(16881,AMPL_WIDTH),
conv_std_logic_vector(16883,AMPL_WIDTH),
conv_std_logic_vector(16886,AMPL_WIDTH),
conv_std_logic_vector(16889,AMPL_WIDTH),
conv_std_logic_vector(16891,AMPL_WIDTH),
conv_std_logic_vector(16894,AMPL_WIDTH),
conv_std_logic_vector(16897,AMPL_WIDTH),
conv_std_logic_vector(16899,AMPL_WIDTH),
conv_std_logic_vector(16902,AMPL_WIDTH),
conv_std_logic_vector(16905,AMPL_WIDTH),
conv_std_logic_vector(16908,AMPL_WIDTH),
conv_std_logic_vector(16910,AMPL_WIDTH),
conv_std_logic_vector(16913,AMPL_WIDTH),
conv_std_logic_vector(16916,AMPL_WIDTH),
conv_std_logic_vector(16918,AMPL_WIDTH),
conv_std_logic_vector(16921,AMPL_WIDTH),
conv_std_logic_vector(16924,AMPL_WIDTH),
conv_std_logic_vector(16926,AMPL_WIDTH),
conv_std_logic_vector(16929,AMPL_WIDTH),
conv_std_logic_vector(16932,AMPL_WIDTH),
conv_std_logic_vector(16934,AMPL_WIDTH),
conv_std_logic_vector(16937,AMPL_WIDTH),
conv_std_logic_vector(16940,AMPL_WIDTH),
conv_std_logic_vector(16943,AMPL_WIDTH),
conv_std_logic_vector(16945,AMPL_WIDTH),
conv_std_logic_vector(16948,AMPL_WIDTH),
conv_std_logic_vector(16951,AMPL_WIDTH),
conv_std_logic_vector(16953,AMPL_WIDTH),
conv_std_logic_vector(16956,AMPL_WIDTH),
conv_std_logic_vector(16959,AMPL_WIDTH),
conv_std_logic_vector(16961,AMPL_WIDTH),
conv_std_logic_vector(16964,AMPL_WIDTH),
conv_std_logic_vector(16967,AMPL_WIDTH),
conv_std_logic_vector(16969,AMPL_WIDTH),
conv_std_logic_vector(16972,AMPL_WIDTH),
conv_std_logic_vector(16975,AMPL_WIDTH),
conv_std_logic_vector(16977,AMPL_WIDTH),
conv_std_logic_vector(16980,AMPL_WIDTH),
conv_std_logic_vector(16983,AMPL_WIDTH),
conv_std_logic_vector(16986,AMPL_WIDTH),
conv_std_logic_vector(16988,AMPL_WIDTH),
conv_std_logic_vector(16991,AMPL_WIDTH),
conv_std_logic_vector(16994,AMPL_WIDTH),
conv_std_logic_vector(16996,AMPL_WIDTH),
conv_std_logic_vector(16999,AMPL_WIDTH),
conv_std_logic_vector(17002,AMPL_WIDTH),
conv_std_logic_vector(17004,AMPL_WIDTH),
conv_std_logic_vector(17007,AMPL_WIDTH),
conv_std_logic_vector(17010,AMPL_WIDTH),
conv_std_logic_vector(17012,AMPL_WIDTH),
conv_std_logic_vector(17015,AMPL_WIDTH),
conv_std_logic_vector(17018,AMPL_WIDTH),
conv_std_logic_vector(17020,AMPL_WIDTH),
conv_std_logic_vector(17023,AMPL_WIDTH),
conv_std_logic_vector(17026,AMPL_WIDTH),
conv_std_logic_vector(17028,AMPL_WIDTH),
conv_std_logic_vector(17031,AMPL_WIDTH),
conv_std_logic_vector(17034,AMPL_WIDTH),
conv_std_logic_vector(17037,AMPL_WIDTH),
conv_std_logic_vector(17039,AMPL_WIDTH),
conv_std_logic_vector(17042,AMPL_WIDTH),
conv_std_logic_vector(17045,AMPL_WIDTH),
conv_std_logic_vector(17047,AMPL_WIDTH),
conv_std_logic_vector(17050,AMPL_WIDTH),
conv_std_logic_vector(17053,AMPL_WIDTH),
conv_std_logic_vector(17055,AMPL_WIDTH),
conv_std_logic_vector(17058,AMPL_WIDTH),
conv_std_logic_vector(17061,AMPL_WIDTH),
conv_std_logic_vector(17063,AMPL_WIDTH),
conv_std_logic_vector(17066,AMPL_WIDTH),
conv_std_logic_vector(17069,AMPL_WIDTH),
conv_std_logic_vector(17071,AMPL_WIDTH),
conv_std_logic_vector(17074,AMPL_WIDTH),
conv_std_logic_vector(17077,AMPL_WIDTH),
conv_std_logic_vector(17079,AMPL_WIDTH),
conv_std_logic_vector(17082,AMPL_WIDTH),
conv_std_logic_vector(17085,AMPL_WIDTH),
conv_std_logic_vector(17087,AMPL_WIDTH),
conv_std_logic_vector(17090,AMPL_WIDTH),
conv_std_logic_vector(17093,AMPL_WIDTH),
conv_std_logic_vector(17096,AMPL_WIDTH),
conv_std_logic_vector(17098,AMPL_WIDTH),
conv_std_logic_vector(17101,AMPL_WIDTH),
conv_std_logic_vector(17104,AMPL_WIDTH),
conv_std_logic_vector(17106,AMPL_WIDTH),
conv_std_logic_vector(17109,AMPL_WIDTH),
conv_std_logic_vector(17112,AMPL_WIDTH),
conv_std_logic_vector(17114,AMPL_WIDTH),
conv_std_logic_vector(17117,AMPL_WIDTH),
conv_std_logic_vector(17120,AMPL_WIDTH),
conv_std_logic_vector(17122,AMPL_WIDTH),
conv_std_logic_vector(17125,AMPL_WIDTH),
conv_std_logic_vector(17128,AMPL_WIDTH),
conv_std_logic_vector(17130,AMPL_WIDTH),
conv_std_logic_vector(17133,AMPL_WIDTH),
conv_std_logic_vector(17136,AMPL_WIDTH),
conv_std_logic_vector(17138,AMPL_WIDTH),
conv_std_logic_vector(17141,AMPL_WIDTH),
conv_std_logic_vector(17144,AMPL_WIDTH),
conv_std_logic_vector(17146,AMPL_WIDTH),
conv_std_logic_vector(17149,AMPL_WIDTH),
conv_std_logic_vector(17152,AMPL_WIDTH),
conv_std_logic_vector(17154,AMPL_WIDTH),
conv_std_logic_vector(17157,AMPL_WIDTH),
conv_std_logic_vector(17160,AMPL_WIDTH),
conv_std_logic_vector(17162,AMPL_WIDTH),
conv_std_logic_vector(17165,AMPL_WIDTH),
conv_std_logic_vector(17168,AMPL_WIDTH),
conv_std_logic_vector(17171,AMPL_WIDTH),
conv_std_logic_vector(17173,AMPL_WIDTH),
conv_std_logic_vector(17176,AMPL_WIDTH),
conv_std_logic_vector(17179,AMPL_WIDTH),
conv_std_logic_vector(17181,AMPL_WIDTH),
conv_std_logic_vector(17184,AMPL_WIDTH),
conv_std_logic_vector(17187,AMPL_WIDTH),
conv_std_logic_vector(17189,AMPL_WIDTH),
conv_std_logic_vector(17192,AMPL_WIDTH),
conv_std_logic_vector(17195,AMPL_WIDTH),
conv_std_logic_vector(17197,AMPL_WIDTH),
conv_std_logic_vector(17200,AMPL_WIDTH),
conv_std_logic_vector(17203,AMPL_WIDTH),
conv_std_logic_vector(17205,AMPL_WIDTH),
conv_std_logic_vector(17208,AMPL_WIDTH),
conv_std_logic_vector(17211,AMPL_WIDTH),
conv_std_logic_vector(17213,AMPL_WIDTH),
conv_std_logic_vector(17216,AMPL_WIDTH),
conv_std_logic_vector(17219,AMPL_WIDTH),
conv_std_logic_vector(17221,AMPL_WIDTH),
conv_std_logic_vector(17224,AMPL_WIDTH),
conv_std_logic_vector(17227,AMPL_WIDTH),
conv_std_logic_vector(17229,AMPL_WIDTH),
conv_std_logic_vector(17232,AMPL_WIDTH),
conv_std_logic_vector(17235,AMPL_WIDTH),
conv_std_logic_vector(17237,AMPL_WIDTH),
conv_std_logic_vector(17240,AMPL_WIDTH),
conv_std_logic_vector(17243,AMPL_WIDTH),
conv_std_logic_vector(17245,AMPL_WIDTH),
conv_std_logic_vector(17248,AMPL_WIDTH),
conv_std_logic_vector(17251,AMPL_WIDTH),
conv_std_logic_vector(17253,AMPL_WIDTH),
conv_std_logic_vector(17256,AMPL_WIDTH),
conv_std_logic_vector(17259,AMPL_WIDTH),
conv_std_logic_vector(17261,AMPL_WIDTH),
conv_std_logic_vector(17264,AMPL_WIDTH),
conv_std_logic_vector(17267,AMPL_WIDTH),
conv_std_logic_vector(17269,AMPL_WIDTH),
conv_std_logic_vector(17272,AMPL_WIDTH),
conv_std_logic_vector(17275,AMPL_WIDTH),
conv_std_logic_vector(17277,AMPL_WIDTH),
conv_std_logic_vector(17280,AMPL_WIDTH),
conv_std_logic_vector(17283,AMPL_WIDTH),
conv_std_logic_vector(17285,AMPL_WIDTH),
conv_std_logic_vector(17288,AMPL_WIDTH),
conv_std_logic_vector(17291,AMPL_WIDTH),
conv_std_logic_vector(17293,AMPL_WIDTH),
conv_std_logic_vector(17296,AMPL_WIDTH),
conv_std_logic_vector(17299,AMPL_WIDTH),
conv_std_logic_vector(17301,AMPL_WIDTH),
conv_std_logic_vector(17304,AMPL_WIDTH),
conv_std_logic_vector(17307,AMPL_WIDTH),
conv_std_logic_vector(17309,AMPL_WIDTH),
conv_std_logic_vector(17312,AMPL_WIDTH),
conv_std_logic_vector(17315,AMPL_WIDTH),
conv_std_logic_vector(17317,AMPL_WIDTH),
conv_std_logic_vector(17320,AMPL_WIDTH),
conv_std_logic_vector(17323,AMPL_WIDTH),
conv_std_logic_vector(17325,AMPL_WIDTH),
conv_std_logic_vector(17328,AMPL_WIDTH),
conv_std_logic_vector(17331,AMPL_WIDTH),
conv_std_logic_vector(17333,AMPL_WIDTH),
conv_std_logic_vector(17336,AMPL_WIDTH),
conv_std_logic_vector(17339,AMPL_WIDTH),
conv_std_logic_vector(17341,AMPL_WIDTH),
conv_std_logic_vector(17344,AMPL_WIDTH),
conv_std_logic_vector(17347,AMPL_WIDTH),
conv_std_logic_vector(17349,AMPL_WIDTH),
conv_std_logic_vector(17352,AMPL_WIDTH),
conv_std_logic_vector(17355,AMPL_WIDTH),
conv_std_logic_vector(17357,AMPL_WIDTH),
conv_std_logic_vector(17360,AMPL_WIDTH),
conv_std_logic_vector(17363,AMPL_WIDTH),
conv_std_logic_vector(17365,AMPL_WIDTH),
conv_std_logic_vector(17368,AMPL_WIDTH),
conv_std_logic_vector(17371,AMPL_WIDTH),
conv_std_logic_vector(17373,AMPL_WIDTH),
conv_std_logic_vector(17376,AMPL_WIDTH),
conv_std_logic_vector(17379,AMPL_WIDTH),
conv_std_logic_vector(17381,AMPL_WIDTH),
conv_std_logic_vector(17384,AMPL_WIDTH),
conv_std_logic_vector(17387,AMPL_WIDTH),
conv_std_logic_vector(17389,AMPL_WIDTH),
conv_std_logic_vector(17392,AMPL_WIDTH),
conv_std_logic_vector(17395,AMPL_WIDTH),
conv_std_logic_vector(17397,AMPL_WIDTH),
conv_std_logic_vector(17400,AMPL_WIDTH),
conv_std_logic_vector(17403,AMPL_WIDTH),
conv_std_logic_vector(17405,AMPL_WIDTH),
conv_std_logic_vector(17408,AMPL_WIDTH),
conv_std_logic_vector(17411,AMPL_WIDTH),
conv_std_logic_vector(17413,AMPL_WIDTH),
conv_std_logic_vector(17416,AMPL_WIDTH),
conv_std_logic_vector(17419,AMPL_WIDTH),
conv_std_logic_vector(17421,AMPL_WIDTH),
conv_std_logic_vector(17424,AMPL_WIDTH),
conv_std_logic_vector(17427,AMPL_WIDTH),
conv_std_logic_vector(17429,AMPL_WIDTH),
conv_std_logic_vector(17432,AMPL_WIDTH),
conv_std_logic_vector(17435,AMPL_WIDTH),
conv_std_logic_vector(17437,AMPL_WIDTH),
conv_std_logic_vector(17440,AMPL_WIDTH),
conv_std_logic_vector(17443,AMPL_WIDTH),
conv_std_logic_vector(17445,AMPL_WIDTH),
conv_std_logic_vector(17448,AMPL_WIDTH),
conv_std_logic_vector(17451,AMPL_WIDTH),
conv_std_logic_vector(17453,AMPL_WIDTH),
conv_std_logic_vector(17456,AMPL_WIDTH),
conv_std_logic_vector(17459,AMPL_WIDTH),
conv_std_logic_vector(17461,AMPL_WIDTH),
conv_std_logic_vector(17464,AMPL_WIDTH),
conv_std_logic_vector(17467,AMPL_WIDTH),
conv_std_logic_vector(17469,AMPL_WIDTH),
conv_std_logic_vector(17472,AMPL_WIDTH),
conv_std_logic_vector(17474,AMPL_WIDTH),
conv_std_logic_vector(17477,AMPL_WIDTH),
conv_std_logic_vector(17480,AMPL_WIDTH),
conv_std_logic_vector(17482,AMPL_WIDTH),
conv_std_logic_vector(17485,AMPL_WIDTH),
conv_std_logic_vector(17488,AMPL_WIDTH),
conv_std_logic_vector(17490,AMPL_WIDTH),
conv_std_logic_vector(17493,AMPL_WIDTH),
conv_std_logic_vector(17496,AMPL_WIDTH),
conv_std_logic_vector(17498,AMPL_WIDTH),
conv_std_logic_vector(17501,AMPL_WIDTH),
conv_std_logic_vector(17504,AMPL_WIDTH),
conv_std_logic_vector(17506,AMPL_WIDTH),
conv_std_logic_vector(17509,AMPL_WIDTH),
conv_std_logic_vector(17512,AMPL_WIDTH),
conv_std_logic_vector(17514,AMPL_WIDTH),
conv_std_logic_vector(17517,AMPL_WIDTH),
conv_std_logic_vector(17520,AMPL_WIDTH),
conv_std_logic_vector(17522,AMPL_WIDTH),
conv_std_logic_vector(17525,AMPL_WIDTH),
conv_std_logic_vector(17528,AMPL_WIDTH),
conv_std_logic_vector(17530,AMPL_WIDTH),
conv_std_logic_vector(17533,AMPL_WIDTH),
conv_std_logic_vector(17536,AMPL_WIDTH),
conv_std_logic_vector(17538,AMPL_WIDTH),
conv_std_logic_vector(17541,AMPL_WIDTH),
conv_std_logic_vector(17544,AMPL_WIDTH),
conv_std_logic_vector(17546,AMPL_WIDTH),
conv_std_logic_vector(17549,AMPL_WIDTH),
conv_std_logic_vector(17551,AMPL_WIDTH),
conv_std_logic_vector(17554,AMPL_WIDTH),
conv_std_logic_vector(17557,AMPL_WIDTH),
conv_std_logic_vector(17559,AMPL_WIDTH),
conv_std_logic_vector(17562,AMPL_WIDTH),
conv_std_logic_vector(17565,AMPL_WIDTH),
conv_std_logic_vector(17567,AMPL_WIDTH),
conv_std_logic_vector(17570,AMPL_WIDTH),
conv_std_logic_vector(17573,AMPL_WIDTH),
conv_std_logic_vector(17575,AMPL_WIDTH),
conv_std_logic_vector(17578,AMPL_WIDTH),
conv_std_logic_vector(17581,AMPL_WIDTH),
conv_std_logic_vector(17583,AMPL_WIDTH),
conv_std_logic_vector(17586,AMPL_WIDTH),
conv_std_logic_vector(17589,AMPL_WIDTH),
conv_std_logic_vector(17591,AMPL_WIDTH),
conv_std_logic_vector(17594,AMPL_WIDTH),
conv_std_logic_vector(17597,AMPL_WIDTH),
conv_std_logic_vector(17599,AMPL_WIDTH),
conv_std_logic_vector(17602,AMPL_WIDTH),
conv_std_logic_vector(17605,AMPL_WIDTH),
conv_std_logic_vector(17607,AMPL_WIDTH),
conv_std_logic_vector(17610,AMPL_WIDTH),
conv_std_logic_vector(17612,AMPL_WIDTH),
conv_std_logic_vector(17615,AMPL_WIDTH),
conv_std_logic_vector(17618,AMPL_WIDTH),
conv_std_logic_vector(17620,AMPL_WIDTH),
conv_std_logic_vector(17623,AMPL_WIDTH),
conv_std_logic_vector(17626,AMPL_WIDTH),
conv_std_logic_vector(17628,AMPL_WIDTH),
conv_std_logic_vector(17631,AMPL_WIDTH),
conv_std_logic_vector(17634,AMPL_WIDTH),
conv_std_logic_vector(17636,AMPL_WIDTH),
conv_std_logic_vector(17639,AMPL_WIDTH),
conv_std_logic_vector(17642,AMPL_WIDTH),
conv_std_logic_vector(17644,AMPL_WIDTH),
conv_std_logic_vector(17647,AMPL_WIDTH),
conv_std_logic_vector(17650,AMPL_WIDTH),
conv_std_logic_vector(17652,AMPL_WIDTH),
conv_std_logic_vector(17655,AMPL_WIDTH),
conv_std_logic_vector(17657,AMPL_WIDTH),
conv_std_logic_vector(17660,AMPL_WIDTH),
conv_std_logic_vector(17663,AMPL_WIDTH),
conv_std_logic_vector(17665,AMPL_WIDTH),
conv_std_logic_vector(17668,AMPL_WIDTH),
conv_std_logic_vector(17671,AMPL_WIDTH),
conv_std_logic_vector(17673,AMPL_WIDTH),
conv_std_logic_vector(17676,AMPL_WIDTH),
conv_std_logic_vector(17679,AMPL_WIDTH),
conv_std_logic_vector(17681,AMPL_WIDTH),
conv_std_logic_vector(17684,AMPL_WIDTH),
conv_std_logic_vector(17687,AMPL_WIDTH),
conv_std_logic_vector(17689,AMPL_WIDTH),
conv_std_logic_vector(17692,AMPL_WIDTH),
conv_std_logic_vector(17695,AMPL_WIDTH),
conv_std_logic_vector(17697,AMPL_WIDTH),
conv_std_logic_vector(17700,AMPL_WIDTH),
conv_std_logic_vector(17702,AMPL_WIDTH),
conv_std_logic_vector(17705,AMPL_WIDTH),
conv_std_logic_vector(17708,AMPL_WIDTH),
conv_std_logic_vector(17710,AMPL_WIDTH),
conv_std_logic_vector(17713,AMPL_WIDTH),
conv_std_logic_vector(17716,AMPL_WIDTH),
conv_std_logic_vector(17718,AMPL_WIDTH),
conv_std_logic_vector(17721,AMPL_WIDTH),
conv_std_logic_vector(17724,AMPL_WIDTH),
conv_std_logic_vector(17726,AMPL_WIDTH),
conv_std_logic_vector(17729,AMPL_WIDTH),
conv_std_logic_vector(17732,AMPL_WIDTH),
conv_std_logic_vector(17734,AMPL_WIDTH),
conv_std_logic_vector(17737,AMPL_WIDTH),
conv_std_logic_vector(17739,AMPL_WIDTH),
conv_std_logic_vector(17742,AMPL_WIDTH),
conv_std_logic_vector(17745,AMPL_WIDTH),
conv_std_logic_vector(17747,AMPL_WIDTH),
conv_std_logic_vector(17750,AMPL_WIDTH),
conv_std_logic_vector(17753,AMPL_WIDTH),
conv_std_logic_vector(17755,AMPL_WIDTH),
conv_std_logic_vector(17758,AMPL_WIDTH),
conv_std_logic_vector(17761,AMPL_WIDTH),
conv_std_logic_vector(17763,AMPL_WIDTH),
conv_std_logic_vector(17766,AMPL_WIDTH),
conv_std_logic_vector(17768,AMPL_WIDTH),
conv_std_logic_vector(17771,AMPL_WIDTH),
conv_std_logic_vector(17774,AMPL_WIDTH),
conv_std_logic_vector(17776,AMPL_WIDTH),
conv_std_logic_vector(17779,AMPL_WIDTH),
conv_std_logic_vector(17782,AMPL_WIDTH),
conv_std_logic_vector(17784,AMPL_WIDTH),
conv_std_logic_vector(17787,AMPL_WIDTH),
conv_std_logic_vector(17790,AMPL_WIDTH),
conv_std_logic_vector(17792,AMPL_WIDTH),
conv_std_logic_vector(17795,AMPL_WIDTH),
conv_std_logic_vector(17798,AMPL_WIDTH),
conv_std_logic_vector(17800,AMPL_WIDTH),
conv_std_logic_vector(17803,AMPL_WIDTH),
conv_std_logic_vector(17805,AMPL_WIDTH),
conv_std_logic_vector(17808,AMPL_WIDTH),
conv_std_logic_vector(17811,AMPL_WIDTH),
conv_std_logic_vector(17813,AMPL_WIDTH),
conv_std_logic_vector(17816,AMPL_WIDTH),
conv_std_logic_vector(17819,AMPL_WIDTH),
conv_std_logic_vector(17821,AMPL_WIDTH),
conv_std_logic_vector(17824,AMPL_WIDTH),
conv_std_logic_vector(17827,AMPL_WIDTH),
conv_std_logic_vector(17829,AMPL_WIDTH),
conv_std_logic_vector(17832,AMPL_WIDTH),
conv_std_logic_vector(17834,AMPL_WIDTH),
conv_std_logic_vector(17837,AMPL_WIDTH),
conv_std_logic_vector(17840,AMPL_WIDTH),
conv_std_logic_vector(17842,AMPL_WIDTH),
conv_std_logic_vector(17845,AMPL_WIDTH),
conv_std_logic_vector(17848,AMPL_WIDTH),
conv_std_logic_vector(17850,AMPL_WIDTH),
conv_std_logic_vector(17853,AMPL_WIDTH),
conv_std_logic_vector(17855,AMPL_WIDTH),
conv_std_logic_vector(17858,AMPL_WIDTH),
conv_std_logic_vector(17861,AMPL_WIDTH),
conv_std_logic_vector(17863,AMPL_WIDTH),
conv_std_logic_vector(17866,AMPL_WIDTH),
conv_std_logic_vector(17869,AMPL_WIDTH),
conv_std_logic_vector(17871,AMPL_WIDTH),
conv_std_logic_vector(17874,AMPL_WIDTH),
conv_std_logic_vector(17877,AMPL_WIDTH),
conv_std_logic_vector(17879,AMPL_WIDTH),
conv_std_logic_vector(17882,AMPL_WIDTH),
conv_std_logic_vector(17884,AMPL_WIDTH),
conv_std_logic_vector(17887,AMPL_WIDTH),
conv_std_logic_vector(17890,AMPL_WIDTH),
conv_std_logic_vector(17892,AMPL_WIDTH),
conv_std_logic_vector(17895,AMPL_WIDTH),
conv_std_logic_vector(17898,AMPL_WIDTH),
conv_std_logic_vector(17900,AMPL_WIDTH),
conv_std_logic_vector(17903,AMPL_WIDTH),
conv_std_logic_vector(17906,AMPL_WIDTH),
conv_std_logic_vector(17908,AMPL_WIDTH),
conv_std_logic_vector(17911,AMPL_WIDTH),
conv_std_logic_vector(17913,AMPL_WIDTH),
conv_std_logic_vector(17916,AMPL_WIDTH),
conv_std_logic_vector(17919,AMPL_WIDTH),
conv_std_logic_vector(17921,AMPL_WIDTH),
conv_std_logic_vector(17924,AMPL_WIDTH),
conv_std_logic_vector(17927,AMPL_WIDTH),
conv_std_logic_vector(17929,AMPL_WIDTH),
conv_std_logic_vector(17932,AMPL_WIDTH),
conv_std_logic_vector(17934,AMPL_WIDTH),
conv_std_logic_vector(17937,AMPL_WIDTH),
conv_std_logic_vector(17940,AMPL_WIDTH),
conv_std_logic_vector(17942,AMPL_WIDTH),
conv_std_logic_vector(17945,AMPL_WIDTH),
conv_std_logic_vector(17948,AMPL_WIDTH),
conv_std_logic_vector(17950,AMPL_WIDTH),
conv_std_logic_vector(17953,AMPL_WIDTH),
conv_std_logic_vector(17955,AMPL_WIDTH),
conv_std_logic_vector(17958,AMPL_WIDTH),
conv_std_logic_vector(17961,AMPL_WIDTH),
conv_std_logic_vector(17963,AMPL_WIDTH),
conv_std_logic_vector(17966,AMPL_WIDTH),
conv_std_logic_vector(17969,AMPL_WIDTH),
conv_std_logic_vector(17971,AMPL_WIDTH),
conv_std_logic_vector(17974,AMPL_WIDTH),
conv_std_logic_vector(17976,AMPL_WIDTH),
conv_std_logic_vector(17979,AMPL_WIDTH),
conv_std_logic_vector(17982,AMPL_WIDTH),
conv_std_logic_vector(17984,AMPL_WIDTH),
conv_std_logic_vector(17987,AMPL_WIDTH),
conv_std_logic_vector(17990,AMPL_WIDTH),
conv_std_logic_vector(17992,AMPL_WIDTH),
conv_std_logic_vector(17995,AMPL_WIDTH),
conv_std_logic_vector(17997,AMPL_WIDTH),
conv_std_logic_vector(18000,AMPL_WIDTH),
conv_std_logic_vector(18003,AMPL_WIDTH),
conv_std_logic_vector(18005,AMPL_WIDTH),
conv_std_logic_vector(18008,AMPL_WIDTH),
conv_std_logic_vector(18011,AMPL_WIDTH),
conv_std_logic_vector(18013,AMPL_WIDTH),
conv_std_logic_vector(18016,AMPL_WIDTH),
conv_std_logic_vector(18018,AMPL_WIDTH),
conv_std_logic_vector(18021,AMPL_WIDTH),
conv_std_logic_vector(18024,AMPL_WIDTH),
conv_std_logic_vector(18026,AMPL_WIDTH),
conv_std_logic_vector(18029,AMPL_WIDTH),
conv_std_logic_vector(18032,AMPL_WIDTH),
conv_std_logic_vector(18034,AMPL_WIDTH),
conv_std_logic_vector(18037,AMPL_WIDTH),
conv_std_logic_vector(18039,AMPL_WIDTH),
conv_std_logic_vector(18042,AMPL_WIDTH),
conv_std_logic_vector(18045,AMPL_WIDTH),
conv_std_logic_vector(18047,AMPL_WIDTH),
conv_std_logic_vector(18050,AMPL_WIDTH),
conv_std_logic_vector(18053,AMPL_WIDTH),
conv_std_logic_vector(18055,AMPL_WIDTH),
conv_std_logic_vector(18058,AMPL_WIDTH),
conv_std_logic_vector(18060,AMPL_WIDTH),
conv_std_logic_vector(18063,AMPL_WIDTH),
conv_std_logic_vector(18066,AMPL_WIDTH),
conv_std_logic_vector(18068,AMPL_WIDTH),
conv_std_logic_vector(18071,AMPL_WIDTH),
conv_std_logic_vector(18074,AMPL_WIDTH),
conv_std_logic_vector(18076,AMPL_WIDTH),
conv_std_logic_vector(18079,AMPL_WIDTH),
conv_std_logic_vector(18081,AMPL_WIDTH),
conv_std_logic_vector(18084,AMPL_WIDTH),
conv_std_logic_vector(18087,AMPL_WIDTH),
conv_std_logic_vector(18089,AMPL_WIDTH),
conv_std_logic_vector(18092,AMPL_WIDTH),
conv_std_logic_vector(18095,AMPL_WIDTH),
conv_std_logic_vector(18097,AMPL_WIDTH),
conv_std_logic_vector(18100,AMPL_WIDTH),
conv_std_logic_vector(18102,AMPL_WIDTH),
conv_std_logic_vector(18105,AMPL_WIDTH),
conv_std_logic_vector(18108,AMPL_WIDTH),
conv_std_logic_vector(18110,AMPL_WIDTH),
conv_std_logic_vector(18113,AMPL_WIDTH),
conv_std_logic_vector(18115,AMPL_WIDTH),
conv_std_logic_vector(18118,AMPL_WIDTH),
conv_std_logic_vector(18121,AMPL_WIDTH),
conv_std_logic_vector(18123,AMPL_WIDTH),
conv_std_logic_vector(18126,AMPL_WIDTH),
conv_std_logic_vector(18129,AMPL_WIDTH),
conv_std_logic_vector(18131,AMPL_WIDTH),
conv_std_logic_vector(18134,AMPL_WIDTH),
conv_std_logic_vector(18136,AMPL_WIDTH),
conv_std_logic_vector(18139,AMPL_WIDTH),
conv_std_logic_vector(18142,AMPL_WIDTH),
conv_std_logic_vector(18144,AMPL_WIDTH),
conv_std_logic_vector(18147,AMPL_WIDTH),
conv_std_logic_vector(18149,AMPL_WIDTH),
conv_std_logic_vector(18152,AMPL_WIDTH),
conv_std_logic_vector(18155,AMPL_WIDTH),
conv_std_logic_vector(18157,AMPL_WIDTH),
conv_std_logic_vector(18160,AMPL_WIDTH),
conv_std_logic_vector(18163,AMPL_WIDTH),
conv_std_logic_vector(18165,AMPL_WIDTH),
conv_std_logic_vector(18168,AMPL_WIDTH),
conv_std_logic_vector(18170,AMPL_WIDTH),
conv_std_logic_vector(18173,AMPL_WIDTH),
conv_std_logic_vector(18176,AMPL_WIDTH),
conv_std_logic_vector(18178,AMPL_WIDTH),
conv_std_logic_vector(18181,AMPL_WIDTH),
conv_std_logic_vector(18183,AMPL_WIDTH),
conv_std_logic_vector(18186,AMPL_WIDTH),
conv_std_logic_vector(18189,AMPL_WIDTH),
conv_std_logic_vector(18191,AMPL_WIDTH),
conv_std_logic_vector(18194,AMPL_WIDTH),
conv_std_logic_vector(18197,AMPL_WIDTH),
conv_std_logic_vector(18199,AMPL_WIDTH),
conv_std_logic_vector(18202,AMPL_WIDTH),
conv_std_logic_vector(18204,AMPL_WIDTH),
conv_std_logic_vector(18207,AMPL_WIDTH),
conv_std_logic_vector(18210,AMPL_WIDTH),
conv_std_logic_vector(18212,AMPL_WIDTH),
conv_std_logic_vector(18215,AMPL_WIDTH),
conv_std_logic_vector(18217,AMPL_WIDTH),
conv_std_logic_vector(18220,AMPL_WIDTH),
conv_std_logic_vector(18223,AMPL_WIDTH),
conv_std_logic_vector(18225,AMPL_WIDTH),
conv_std_logic_vector(18228,AMPL_WIDTH),
conv_std_logic_vector(18230,AMPL_WIDTH),
conv_std_logic_vector(18233,AMPL_WIDTH),
conv_std_logic_vector(18236,AMPL_WIDTH),
conv_std_logic_vector(18238,AMPL_WIDTH),
conv_std_logic_vector(18241,AMPL_WIDTH),
conv_std_logic_vector(18244,AMPL_WIDTH),
conv_std_logic_vector(18246,AMPL_WIDTH),
conv_std_logic_vector(18249,AMPL_WIDTH),
conv_std_logic_vector(18251,AMPL_WIDTH),
conv_std_logic_vector(18254,AMPL_WIDTH),
conv_std_logic_vector(18257,AMPL_WIDTH),
conv_std_logic_vector(18259,AMPL_WIDTH),
conv_std_logic_vector(18262,AMPL_WIDTH),
conv_std_logic_vector(18264,AMPL_WIDTH),
conv_std_logic_vector(18267,AMPL_WIDTH),
conv_std_logic_vector(18270,AMPL_WIDTH),
conv_std_logic_vector(18272,AMPL_WIDTH),
conv_std_logic_vector(18275,AMPL_WIDTH),
conv_std_logic_vector(18277,AMPL_WIDTH),
conv_std_logic_vector(18280,AMPL_WIDTH),
conv_std_logic_vector(18283,AMPL_WIDTH),
conv_std_logic_vector(18285,AMPL_WIDTH),
conv_std_logic_vector(18288,AMPL_WIDTH),
conv_std_logic_vector(18290,AMPL_WIDTH),
conv_std_logic_vector(18293,AMPL_WIDTH),
conv_std_logic_vector(18296,AMPL_WIDTH),
conv_std_logic_vector(18298,AMPL_WIDTH),
conv_std_logic_vector(18301,AMPL_WIDTH),
conv_std_logic_vector(18304,AMPL_WIDTH),
conv_std_logic_vector(18306,AMPL_WIDTH),
conv_std_logic_vector(18309,AMPL_WIDTH),
conv_std_logic_vector(18311,AMPL_WIDTH),
conv_std_logic_vector(18314,AMPL_WIDTH),
conv_std_logic_vector(18317,AMPL_WIDTH),
conv_std_logic_vector(18319,AMPL_WIDTH),
conv_std_logic_vector(18322,AMPL_WIDTH),
conv_std_logic_vector(18324,AMPL_WIDTH),
conv_std_logic_vector(18327,AMPL_WIDTH),
conv_std_logic_vector(18330,AMPL_WIDTH),
conv_std_logic_vector(18332,AMPL_WIDTH),
conv_std_logic_vector(18335,AMPL_WIDTH),
conv_std_logic_vector(18337,AMPL_WIDTH),
conv_std_logic_vector(18340,AMPL_WIDTH),
conv_std_logic_vector(18343,AMPL_WIDTH),
conv_std_logic_vector(18345,AMPL_WIDTH),
conv_std_logic_vector(18348,AMPL_WIDTH),
conv_std_logic_vector(18350,AMPL_WIDTH),
conv_std_logic_vector(18353,AMPL_WIDTH),
conv_std_logic_vector(18356,AMPL_WIDTH),
conv_std_logic_vector(18358,AMPL_WIDTH),
conv_std_logic_vector(18361,AMPL_WIDTH),
conv_std_logic_vector(18363,AMPL_WIDTH),
conv_std_logic_vector(18366,AMPL_WIDTH),
conv_std_logic_vector(18369,AMPL_WIDTH),
conv_std_logic_vector(18371,AMPL_WIDTH),
conv_std_logic_vector(18374,AMPL_WIDTH),
conv_std_logic_vector(18376,AMPL_WIDTH),
conv_std_logic_vector(18379,AMPL_WIDTH),
conv_std_logic_vector(18382,AMPL_WIDTH),
conv_std_logic_vector(18384,AMPL_WIDTH),
conv_std_logic_vector(18387,AMPL_WIDTH),
conv_std_logic_vector(18389,AMPL_WIDTH),
conv_std_logic_vector(18392,AMPL_WIDTH),
conv_std_logic_vector(18395,AMPL_WIDTH),
conv_std_logic_vector(18397,AMPL_WIDTH),
conv_std_logic_vector(18400,AMPL_WIDTH),
conv_std_logic_vector(18402,AMPL_WIDTH),
conv_std_logic_vector(18405,AMPL_WIDTH),
conv_std_logic_vector(18408,AMPL_WIDTH),
conv_std_logic_vector(18410,AMPL_WIDTH),
conv_std_logic_vector(18413,AMPL_WIDTH),
conv_std_logic_vector(18415,AMPL_WIDTH),
conv_std_logic_vector(18418,AMPL_WIDTH),
conv_std_logic_vector(18421,AMPL_WIDTH),
conv_std_logic_vector(18423,AMPL_WIDTH),
conv_std_logic_vector(18426,AMPL_WIDTH),
conv_std_logic_vector(18428,AMPL_WIDTH),
conv_std_logic_vector(18431,AMPL_WIDTH),
conv_std_logic_vector(18434,AMPL_WIDTH),
conv_std_logic_vector(18436,AMPL_WIDTH),
conv_std_logic_vector(18439,AMPL_WIDTH),
conv_std_logic_vector(18441,AMPL_WIDTH),
conv_std_logic_vector(18444,AMPL_WIDTH),
conv_std_logic_vector(18447,AMPL_WIDTH),
conv_std_logic_vector(18449,AMPL_WIDTH),
conv_std_logic_vector(18452,AMPL_WIDTH),
conv_std_logic_vector(18454,AMPL_WIDTH),
conv_std_logic_vector(18457,AMPL_WIDTH),
conv_std_logic_vector(18460,AMPL_WIDTH),
conv_std_logic_vector(18462,AMPL_WIDTH),
conv_std_logic_vector(18465,AMPL_WIDTH),
conv_std_logic_vector(18467,AMPL_WIDTH),
conv_std_logic_vector(18470,AMPL_WIDTH),
conv_std_logic_vector(18473,AMPL_WIDTH),
conv_std_logic_vector(18475,AMPL_WIDTH),
conv_std_logic_vector(18478,AMPL_WIDTH),
conv_std_logic_vector(18480,AMPL_WIDTH),
conv_std_logic_vector(18483,AMPL_WIDTH),
conv_std_logic_vector(18485,AMPL_WIDTH),
conv_std_logic_vector(18488,AMPL_WIDTH),
conv_std_logic_vector(18491,AMPL_WIDTH),
conv_std_logic_vector(18493,AMPL_WIDTH),
conv_std_logic_vector(18496,AMPL_WIDTH),
conv_std_logic_vector(18498,AMPL_WIDTH),
conv_std_logic_vector(18501,AMPL_WIDTH),
conv_std_logic_vector(18504,AMPL_WIDTH),
conv_std_logic_vector(18506,AMPL_WIDTH),
conv_std_logic_vector(18509,AMPL_WIDTH),
conv_std_logic_vector(18511,AMPL_WIDTH),
conv_std_logic_vector(18514,AMPL_WIDTH),
conv_std_logic_vector(18517,AMPL_WIDTH),
conv_std_logic_vector(18519,AMPL_WIDTH),
conv_std_logic_vector(18522,AMPL_WIDTH),
conv_std_logic_vector(18524,AMPL_WIDTH),
conv_std_logic_vector(18527,AMPL_WIDTH),
conv_std_logic_vector(18530,AMPL_WIDTH),
conv_std_logic_vector(18532,AMPL_WIDTH),
conv_std_logic_vector(18535,AMPL_WIDTH),
conv_std_logic_vector(18537,AMPL_WIDTH),
conv_std_logic_vector(18540,AMPL_WIDTH),
conv_std_logic_vector(18543,AMPL_WIDTH),
conv_std_logic_vector(18545,AMPL_WIDTH),
conv_std_logic_vector(18548,AMPL_WIDTH),
conv_std_logic_vector(18550,AMPL_WIDTH),
conv_std_logic_vector(18553,AMPL_WIDTH),
conv_std_logic_vector(18555,AMPL_WIDTH),
conv_std_logic_vector(18558,AMPL_WIDTH),
conv_std_logic_vector(18561,AMPL_WIDTH),
conv_std_logic_vector(18563,AMPL_WIDTH),
conv_std_logic_vector(18566,AMPL_WIDTH),
conv_std_logic_vector(18568,AMPL_WIDTH),
conv_std_logic_vector(18571,AMPL_WIDTH),
conv_std_logic_vector(18574,AMPL_WIDTH),
conv_std_logic_vector(18576,AMPL_WIDTH),
conv_std_logic_vector(18579,AMPL_WIDTH),
conv_std_logic_vector(18581,AMPL_WIDTH),
conv_std_logic_vector(18584,AMPL_WIDTH),
conv_std_logic_vector(18587,AMPL_WIDTH),
conv_std_logic_vector(18589,AMPL_WIDTH),
conv_std_logic_vector(18592,AMPL_WIDTH),
conv_std_logic_vector(18594,AMPL_WIDTH),
conv_std_logic_vector(18597,AMPL_WIDTH),
conv_std_logic_vector(18599,AMPL_WIDTH),
conv_std_logic_vector(18602,AMPL_WIDTH),
conv_std_logic_vector(18605,AMPL_WIDTH),
conv_std_logic_vector(18607,AMPL_WIDTH),
conv_std_logic_vector(18610,AMPL_WIDTH),
conv_std_logic_vector(18612,AMPL_WIDTH),
conv_std_logic_vector(18615,AMPL_WIDTH),
conv_std_logic_vector(18618,AMPL_WIDTH),
conv_std_logic_vector(18620,AMPL_WIDTH),
conv_std_logic_vector(18623,AMPL_WIDTH),
conv_std_logic_vector(18625,AMPL_WIDTH),
conv_std_logic_vector(18628,AMPL_WIDTH),
conv_std_logic_vector(18630,AMPL_WIDTH),
conv_std_logic_vector(18633,AMPL_WIDTH),
conv_std_logic_vector(18636,AMPL_WIDTH),
conv_std_logic_vector(18638,AMPL_WIDTH),
conv_std_logic_vector(18641,AMPL_WIDTH),
conv_std_logic_vector(18643,AMPL_WIDTH),
conv_std_logic_vector(18646,AMPL_WIDTH),
conv_std_logic_vector(18649,AMPL_WIDTH),
conv_std_logic_vector(18651,AMPL_WIDTH),
conv_std_logic_vector(18654,AMPL_WIDTH),
conv_std_logic_vector(18656,AMPL_WIDTH),
conv_std_logic_vector(18659,AMPL_WIDTH),
conv_std_logic_vector(18661,AMPL_WIDTH),
conv_std_logic_vector(18664,AMPL_WIDTH),
conv_std_logic_vector(18667,AMPL_WIDTH),
conv_std_logic_vector(18669,AMPL_WIDTH),
conv_std_logic_vector(18672,AMPL_WIDTH),
conv_std_logic_vector(18674,AMPL_WIDTH),
conv_std_logic_vector(18677,AMPL_WIDTH),
conv_std_logic_vector(18680,AMPL_WIDTH),
conv_std_logic_vector(18682,AMPL_WIDTH),
conv_std_logic_vector(18685,AMPL_WIDTH),
conv_std_logic_vector(18687,AMPL_WIDTH),
conv_std_logic_vector(18690,AMPL_WIDTH),
conv_std_logic_vector(18692,AMPL_WIDTH),
conv_std_logic_vector(18695,AMPL_WIDTH),
conv_std_logic_vector(18698,AMPL_WIDTH),
conv_std_logic_vector(18700,AMPL_WIDTH),
conv_std_logic_vector(18703,AMPL_WIDTH),
conv_std_logic_vector(18705,AMPL_WIDTH),
conv_std_logic_vector(18708,AMPL_WIDTH),
conv_std_logic_vector(18711,AMPL_WIDTH),
conv_std_logic_vector(18713,AMPL_WIDTH),
conv_std_logic_vector(18716,AMPL_WIDTH),
conv_std_logic_vector(18718,AMPL_WIDTH),
conv_std_logic_vector(18721,AMPL_WIDTH),
conv_std_logic_vector(18723,AMPL_WIDTH),
conv_std_logic_vector(18726,AMPL_WIDTH),
conv_std_logic_vector(18729,AMPL_WIDTH),
conv_std_logic_vector(18731,AMPL_WIDTH),
conv_std_logic_vector(18734,AMPL_WIDTH),
conv_std_logic_vector(18736,AMPL_WIDTH),
conv_std_logic_vector(18739,AMPL_WIDTH),
conv_std_logic_vector(18741,AMPL_WIDTH),
conv_std_logic_vector(18744,AMPL_WIDTH),
conv_std_logic_vector(18747,AMPL_WIDTH),
conv_std_logic_vector(18749,AMPL_WIDTH),
conv_std_logic_vector(18752,AMPL_WIDTH),
conv_std_logic_vector(18754,AMPL_WIDTH),
conv_std_logic_vector(18757,AMPL_WIDTH),
conv_std_logic_vector(18759,AMPL_WIDTH),
conv_std_logic_vector(18762,AMPL_WIDTH),
conv_std_logic_vector(18765,AMPL_WIDTH),
conv_std_logic_vector(18767,AMPL_WIDTH),
conv_std_logic_vector(18770,AMPL_WIDTH),
conv_std_logic_vector(18772,AMPL_WIDTH),
conv_std_logic_vector(18775,AMPL_WIDTH),
conv_std_logic_vector(18778,AMPL_WIDTH),
conv_std_logic_vector(18780,AMPL_WIDTH),
conv_std_logic_vector(18783,AMPL_WIDTH),
conv_std_logic_vector(18785,AMPL_WIDTH),
conv_std_logic_vector(18788,AMPL_WIDTH),
conv_std_logic_vector(18790,AMPL_WIDTH),
conv_std_logic_vector(18793,AMPL_WIDTH),
conv_std_logic_vector(18796,AMPL_WIDTH),
conv_std_logic_vector(18798,AMPL_WIDTH),
conv_std_logic_vector(18801,AMPL_WIDTH),
conv_std_logic_vector(18803,AMPL_WIDTH),
conv_std_logic_vector(18806,AMPL_WIDTH),
conv_std_logic_vector(18808,AMPL_WIDTH),
conv_std_logic_vector(18811,AMPL_WIDTH),
conv_std_logic_vector(18814,AMPL_WIDTH),
conv_std_logic_vector(18816,AMPL_WIDTH),
conv_std_logic_vector(18819,AMPL_WIDTH),
conv_std_logic_vector(18821,AMPL_WIDTH),
conv_std_logic_vector(18824,AMPL_WIDTH),
conv_std_logic_vector(18826,AMPL_WIDTH),
conv_std_logic_vector(18829,AMPL_WIDTH),
conv_std_logic_vector(18832,AMPL_WIDTH),
conv_std_logic_vector(18834,AMPL_WIDTH),
conv_std_logic_vector(18837,AMPL_WIDTH),
conv_std_logic_vector(18839,AMPL_WIDTH),
conv_std_logic_vector(18842,AMPL_WIDTH),
conv_std_logic_vector(18844,AMPL_WIDTH),
conv_std_logic_vector(18847,AMPL_WIDTH),
conv_std_logic_vector(18850,AMPL_WIDTH),
conv_std_logic_vector(18852,AMPL_WIDTH),
conv_std_logic_vector(18855,AMPL_WIDTH),
conv_std_logic_vector(18857,AMPL_WIDTH),
conv_std_logic_vector(18860,AMPL_WIDTH),
conv_std_logic_vector(18862,AMPL_WIDTH),
conv_std_logic_vector(18865,AMPL_WIDTH),
conv_std_logic_vector(18868,AMPL_WIDTH),
conv_std_logic_vector(18870,AMPL_WIDTH),
conv_std_logic_vector(18873,AMPL_WIDTH),
conv_std_logic_vector(18875,AMPL_WIDTH),
conv_std_logic_vector(18878,AMPL_WIDTH),
conv_std_logic_vector(18880,AMPL_WIDTH),
conv_std_logic_vector(18883,AMPL_WIDTH),
conv_std_logic_vector(18885,AMPL_WIDTH),
conv_std_logic_vector(18888,AMPL_WIDTH),
conv_std_logic_vector(18891,AMPL_WIDTH),
conv_std_logic_vector(18893,AMPL_WIDTH),
conv_std_logic_vector(18896,AMPL_WIDTH),
conv_std_logic_vector(18898,AMPL_WIDTH),
conv_std_logic_vector(18901,AMPL_WIDTH),
conv_std_logic_vector(18903,AMPL_WIDTH),
conv_std_logic_vector(18906,AMPL_WIDTH),
conv_std_logic_vector(18909,AMPL_WIDTH),
conv_std_logic_vector(18911,AMPL_WIDTH),
conv_std_logic_vector(18914,AMPL_WIDTH),
conv_std_logic_vector(18916,AMPL_WIDTH),
conv_std_logic_vector(18919,AMPL_WIDTH),
conv_std_logic_vector(18921,AMPL_WIDTH),
conv_std_logic_vector(18924,AMPL_WIDTH),
conv_std_logic_vector(18927,AMPL_WIDTH),
conv_std_logic_vector(18929,AMPL_WIDTH),
conv_std_logic_vector(18932,AMPL_WIDTH),
conv_std_logic_vector(18934,AMPL_WIDTH),
conv_std_logic_vector(18937,AMPL_WIDTH),
conv_std_logic_vector(18939,AMPL_WIDTH),
conv_std_logic_vector(18942,AMPL_WIDTH),
conv_std_logic_vector(18944,AMPL_WIDTH),
conv_std_logic_vector(18947,AMPL_WIDTH),
conv_std_logic_vector(18950,AMPL_WIDTH),
conv_std_logic_vector(18952,AMPL_WIDTH),
conv_std_logic_vector(18955,AMPL_WIDTH),
conv_std_logic_vector(18957,AMPL_WIDTH),
conv_std_logic_vector(18960,AMPL_WIDTH),
conv_std_logic_vector(18962,AMPL_WIDTH),
conv_std_logic_vector(18965,AMPL_WIDTH),
conv_std_logic_vector(18968,AMPL_WIDTH),
conv_std_logic_vector(18970,AMPL_WIDTH),
conv_std_logic_vector(18973,AMPL_WIDTH),
conv_std_logic_vector(18975,AMPL_WIDTH),
conv_std_logic_vector(18978,AMPL_WIDTH),
conv_std_logic_vector(18980,AMPL_WIDTH),
conv_std_logic_vector(18983,AMPL_WIDTH),
conv_std_logic_vector(18985,AMPL_WIDTH),
conv_std_logic_vector(18988,AMPL_WIDTH),
conv_std_logic_vector(18991,AMPL_WIDTH),
conv_std_logic_vector(18993,AMPL_WIDTH),
conv_std_logic_vector(18996,AMPL_WIDTH),
conv_std_logic_vector(18998,AMPL_WIDTH),
conv_std_logic_vector(19001,AMPL_WIDTH),
conv_std_logic_vector(19003,AMPL_WIDTH),
conv_std_logic_vector(19006,AMPL_WIDTH),
conv_std_logic_vector(19009,AMPL_WIDTH),
conv_std_logic_vector(19011,AMPL_WIDTH),
conv_std_logic_vector(19014,AMPL_WIDTH),
conv_std_logic_vector(19016,AMPL_WIDTH),
conv_std_logic_vector(19019,AMPL_WIDTH),
conv_std_logic_vector(19021,AMPL_WIDTH),
conv_std_logic_vector(19024,AMPL_WIDTH),
conv_std_logic_vector(19026,AMPL_WIDTH),
conv_std_logic_vector(19029,AMPL_WIDTH),
conv_std_logic_vector(19032,AMPL_WIDTH),
conv_std_logic_vector(19034,AMPL_WIDTH),
conv_std_logic_vector(19037,AMPL_WIDTH),
conv_std_logic_vector(19039,AMPL_WIDTH),
conv_std_logic_vector(19042,AMPL_WIDTH),
conv_std_logic_vector(19044,AMPL_WIDTH),
conv_std_logic_vector(19047,AMPL_WIDTH),
conv_std_logic_vector(19049,AMPL_WIDTH),
conv_std_logic_vector(19052,AMPL_WIDTH),
conv_std_logic_vector(19055,AMPL_WIDTH),
conv_std_logic_vector(19057,AMPL_WIDTH),
conv_std_logic_vector(19060,AMPL_WIDTH),
conv_std_logic_vector(19062,AMPL_WIDTH),
conv_std_logic_vector(19065,AMPL_WIDTH),
conv_std_logic_vector(19067,AMPL_WIDTH),
conv_std_logic_vector(19070,AMPL_WIDTH),
conv_std_logic_vector(19072,AMPL_WIDTH),
conv_std_logic_vector(19075,AMPL_WIDTH),
conv_std_logic_vector(19078,AMPL_WIDTH),
conv_std_logic_vector(19080,AMPL_WIDTH),
conv_std_logic_vector(19083,AMPL_WIDTH),
conv_std_logic_vector(19085,AMPL_WIDTH),
conv_std_logic_vector(19088,AMPL_WIDTH),
conv_std_logic_vector(19090,AMPL_WIDTH),
conv_std_logic_vector(19093,AMPL_WIDTH),
conv_std_logic_vector(19095,AMPL_WIDTH),
conv_std_logic_vector(19098,AMPL_WIDTH),
conv_std_logic_vector(19101,AMPL_WIDTH),
conv_std_logic_vector(19103,AMPL_WIDTH),
conv_std_logic_vector(19106,AMPL_WIDTH),
conv_std_logic_vector(19108,AMPL_WIDTH),
conv_std_logic_vector(19111,AMPL_WIDTH),
conv_std_logic_vector(19113,AMPL_WIDTH),
conv_std_logic_vector(19116,AMPL_WIDTH),
conv_std_logic_vector(19118,AMPL_WIDTH),
conv_std_logic_vector(19121,AMPL_WIDTH),
conv_std_logic_vector(19123,AMPL_WIDTH),
conv_std_logic_vector(19126,AMPL_WIDTH),
conv_std_logic_vector(19129,AMPL_WIDTH),
conv_std_logic_vector(19131,AMPL_WIDTH),
conv_std_logic_vector(19134,AMPL_WIDTH),
conv_std_logic_vector(19136,AMPL_WIDTH),
conv_std_logic_vector(19139,AMPL_WIDTH),
conv_std_logic_vector(19141,AMPL_WIDTH),
conv_std_logic_vector(19144,AMPL_WIDTH),
conv_std_logic_vector(19146,AMPL_WIDTH),
conv_std_logic_vector(19149,AMPL_WIDTH),
conv_std_logic_vector(19152,AMPL_WIDTH),
conv_std_logic_vector(19154,AMPL_WIDTH),
conv_std_logic_vector(19157,AMPL_WIDTH),
conv_std_logic_vector(19159,AMPL_WIDTH),
conv_std_logic_vector(19162,AMPL_WIDTH),
conv_std_logic_vector(19164,AMPL_WIDTH),
conv_std_logic_vector(19167,AMPL_WIDTH),
conv_std_logic_vector(19169,AMPL_WIDTH),
conv_std_logic_vector(19172,AMPL_WIDTH),
conv_std_logic_vector(19174,AMPL_WIDTH),
conv_std_logic_vector(19177,AMPL_WIDTH),
conv_std_logic_vector(19180,AMPL_WIDTH),
conv_std_logic_vector(19182,AMPL_WIDTH),
conv_std_logic_vector(19185,AMPL_WIDTH),
conv_std_logic_vector(19187,AMPL_WIDTH),
conv_std_logic_vector(19190,AMPL_WIDTH),
conv_std_logic_vector(19192,AMPL_WIDTH),
conv_std_logic_vector(19195,AMPL_WIDTH),
conv_std_logic_vector(19197,AMPL_WIDTH),
conv_std_logic_vector(19200,AMPL_WIDTH),
conv_std_logic_vector(19202,AMPL_WIDTH),
conv_std_logic_vector(19205,AMPL_WIDTH),
conv_std_logic_vector(19208,AMPL_WIDTH),
conv_std_logic_vector(19210,AMPL_WIDTH),
conv_std_logic_vector(19213,AMPL_WIDTH),
conv_std_logic_vector(19215,AMPL_WIDTH),
conv_std_logic_vector(19218,AMPL_WIDTH),
conv_std_logic_vector(19220,AMPL_WIDTH),
conv_std_logic_vector(19223,AMPL_WIDTH),
conv_std_logic_vector(19225,AMPL_WIDTH),
conv_std_logic_vector(19228,AMPL_WIDTH),
conv_std_logic_vector(19230,AMPL_WIDTH),
conv_std_logic_vector(19233,AMPL_WIDTH),
conv_std_logic_vector(19236,AMPL_WIDTH),
conv_std_logic_vector(19238,AMPL_WIDTH),
conv_std_logic_vector(19241,AMPL_WIDTH),
conv_std_logic_vector(19243,AMPL_WIDTH),
conv_std_logic_vector(19246,AMPL_WIDTH),
conv_std_logic_vector(19248,AMPL_WIDTH),
conv_std_logic_vector(19251,AMPL_WIDTH),
conv_std_logic_vector(19253,AMPL_WIDTH),
conv_std_logic_vector(19256,AMPL_WIDTH),
conv_std_logic_vector(19258,AMPL_WIDTH),
conv_std_logic_vector(19261,AMPL_WIDTH),
conv_std_logic_vector(19264,AMPL_WIDTH),
conv_std_logic_vector(19266,AMPL_WIDTH),
conv_std_logic_vector(19269,AMPL_WIDTH),
conv_std_logic_vector(19271,AMPL_WIDTH),
conv_std_logic_vector(19274,AMPL_WIDTH),
conv_std_logic_vector(19276,AMPL_WIDTH),
conv_std_logic_vector(19279,AMPL_WIDTH),
conv_std_logic_vector(19281,AMPL_WIDTH),
conv_std_logic_vector(19284,AMPL_WIDTH),
conv_std_logic_vector(19286,AMPL_WIDTH),
conv_std_logic_vector(19289,AMPL_WIDTH),
conv_std_logic_vector(19291,AMPL_WIDTH),
conv_std_logic_vector(19294,AMPL_WIDTH),
conv_std_logic_vector(19297,AMPL_WIDTH),
conv_std_logic_vector(19299,AMPL_WIDTH),
conv_std_logic_vector(19302,AMPL_WIDTH),
conv_std_logic_vector(19304,AMPL_WIDTH),
conv_std_logic_vector(19307,AMPL_WIDTH),
conv_std_logic_vector(19309,AMPL_WIDTH),
conv_std_logic_vector(19312,AMPL_WIDTH),
conv_std_logic_vector(19314,AMPL_WIDTH),
conv_std_logic_vector(19317,AMPL_WIDTH),
conv_std_logic_vector(19319,AMPL_WIDTH),
conv_std_logic_vector(19322,AMPL_WIDTH),
conv_std_logic_vector(19324,AMPL_WIDTH),
conv_std_logic_vector(19327,AMPL_WIDTH),
conv_std_logic_vector(19330,AMPL_WIDTH),
conv_std_logic_vector(19332,AMPL_WIDTH),
conv_std_logic_vector(19335,AMPL_WIDTH),
conv_std_logic_vector(19337,AMPL_WIDTH),
conv_std_logic_vector(19340,AMPL_WIDTH),
conv_std_logic_vector(19342,AMPL_WIDTH),
conv_std_logic_vector(19345,AMPL_WIDTH),
conv_std_logic_vector(19347,AMPL_WIDTH),
conv_std_logic_vector(19350,AMPL_WIDTH),
conv_std_logic_vector(19352,AMPL_WIDTH),
conv_std_logic_vector(19355,AMPL_WIDTH),
conv_std_logic_vector(19357,AMPL_WIDTH),
conv_std_logic_vector(19360,AMPL_WIDTH),
conv_std_logic_vector(19362,AMPL_WIDTH),
conv_std_logic_vector(19365,AMPL_WIDTH),
conv_std_logic_vector(19368,AMPL_WIDTH),
conv_std_logic_vector(19370,AMPL_WIDTH),
conv_std_logic_vector(19373,AMPL_WIDTH),
conv_std_logic_vector(19375,AMPL_WIDTH),
conv_std_logic_vector(19378,AMPL_WIDTH),
conv_std_logic_vector(19380,AMPL_WIDTH),
conv_std_logic_vector(19383,AMPL_WIDTH),
conv_std_logic_vector(19385,AMPL_WIDTH),
conv_std_logic_vector(19388,AMPL_WIDTH),
conv_std_logic_vector(19390,AMPL_WIDTH),
conv_std_logic_vector(19393,AMPL_WIDTH),
conv_std_logic_vector(19395,AMPL_WIDTH),
conv_std_logic_vector(19398,AMPL_WIDTH),
conv_std_logic_vector(19400,AMPL_WIDTH),
conv_std_logic_vector(19403,AMPL_WIDTH),
conv_std_logic_vector(19406,AMPL_WIDTH),
conv_std_logic_vector(19408,AMPL_WIDTH),
conv_std_logic_vector(19411,AMPL_WIDTH),
conv_std_logic_vector(19413,AMPL_WIDTH),
conv_std_logic_vector(19416,AMPL_WIDTH),
conv_std_logic_vector(19418,AMPL_WIDTH),
conv_std_logic_vector(19421,AMPL_WIDTH),
conv_std_logic_vector(19423,AMPL_WIDTH),
conv_std_logic_vector(19426,AMPL_WIDTH),
conv_std_logic_vector(19428,AMPL_WIDTH),
conv_std_logic_vector(19431,AMPL_WIDTH),
conv_std_logic_vector(19433,AMPL_WIDTH),
conv_std_logic_vector(19436,AMPL_WIDTH),
conv_std_logic_vector(19438,AMPL_WIDTH),
conv_std_logic_vector(19441,AMPL_WIDTH),
conv_std_logic_vector(19444,AMPL_WIDTH),
conv_std_logic_vector(19446,AMPL_WIDTH),
conv_std_logic_vector(19449,AMPL_WIDTH),
conv_std_logic_vector(19451,AMPL_WIDTH),
conv_std_logic_vector(19454,AMPL_WIDTH),
conv_std_logic_vector(19456,AMPL_WIDTH),
conv_std_logic_vector(19459,AMPL_WIDTH),
conv_std_logic_vector(19461,AMPL_WIDTH),
conv_std_logic_vector(19464,AMPL_WIDTH),
conv_std_logic_vector(19466,AMPL_WIDTH),
conv_std_logic_vector(19469,AMPL_WIDTH),
conv_std_logic_vector(19471,AMPL_WIDTH),
conv_std_logic_vector(19474,AMPL_WIDTH),
conv_std_logic_vector(19476,AMPL_WIDTH),
conv_std_logic_vector(19479,AMPL_WIDTH),
conv_std_logic_vector(19481,AMPL_WIDTH),
conv_std_logic_vector(19484,AMPL_WIDTH),
conv_std_logic_vector(19486,AMPL_WIDTH),
conv_std_logic_vector(19489,AMPL_WIDTH),
conv_std_logic_vector(19492,AMPL_WIDTH),
conv_std_logic_vector(19494,AMPL_WIDTH),
conv_std_logic_vector(19497,AMPL_WIDTH),
conv_std_logic_vector(19499,AMPL_WIDTH),
conv_std_logic_vector(19502,AMPL_WIDTH),
conv_std_logic_vector(19504,AMPL_WIDTH),
conv_std_logic_vector(19507,AMPL_WIDTH),
conv_std_logic_vector(19509,AMPL_WIDTH),
conv_std_logic_vector(19512,AMPL_WIDTH),
conv_std_logic_vector(19514,AMPL_WIDTH),
conv_std_logic_vector(19517,AMPL_WIDTH),
conv_std_logic_vector(19519,AMPL_WIDTH),
conv_std_logic_vector(19522,AMPL_WIDTH),
conv_std_logic_vector(19524,AMPL_WIDTH),
conv_std_logic_vector(19527,AMPL_WIDTH),
conv_std_logic_vector(19529,AMPL_WIDTH),
conv_std_logic_vector(19532,AMPL_WIDTH),
conv_std_logic_vector(19534,AMPL_WIDTH),
conv_std_logic_vector(19537,AMPL_WIDTH),
conv_std_logic_vector(19539,AMPL_WIDTH),
conv_std_logic_vector(19542,AMPL_WIDTH),
conv_std_logic_vector(19545,AMPL_WIDTH),
conv_std_logic_vector(19547,AMPL_WIDTH),
conv_std_logic_vector(19550,AMPL_WIDTH),
conv_std_logic_vector(19552,AMPL_WIDTH),
conv_std_logic_vector(19555,AMPL_WIDTH),
conv_std_logic_vector(19557,AMPL_WIDTH),
conv_std_logic_vector(19560,AMPL_WIDTH),
conv_std_logic_vector(19562,AMPL_WIDTH),
conv_std_logic_vector(19565,AMPL_WIDTH),
conv_std_logic_vector(19567,AMPL_WIDTH),
conv_std_logic_vector(19570,AMPL_WIDTH),
conv_std_logic_vector(19572,AMPL_WIDTH),
conv_std_logic_vector(19575,AMPL_WIDTH),
conv_std_logic_vector(19577,AMPL_WIDTH),
conv_std_logic_vector(19580,AMPL_WIDTH),
conv_std_logic_vector(19582,AMPL_WIDTH),
conv_std_logic_vector(19585,AMPL_WIDTH),
conv_std_logic_vector(19587,AMPL_WIDTH),
conv_std_logic_vector(19590,AMPL_WIDTH),
conv_std_logic_vector(19592,AMPL_WIDTH),
conv_std_logic_vector(19595,AMPL_WIDTH),
conv_std_logic_vector(19597,AMPL_WIDTH),
conv_std_logic_vector(19600,AMPL_WIDTH),
conv_std_logic_vector(19602,AMPL_WIDTH),
conv_std_logic_vector(19605,AMPL_WIDTH),
conv_std_logic_vector(19607,AMPL_WIDTH),
conv_std_logic_vector(19610,AMPL_WIDTH),
conv_std_logic_vector(19613,AMPL_WIDTH),
conv_std_logic_vector(19615,AMPL_WIDTH),
conv_std_logic_vector(19618,AMPL_WIDTH),
conv_std_logic_vector(19620,AMPL_WIDTH),
conv_std_logic_vector(19623,AMPL_WIDTH),
conv_std_logic_vector(19625,AMPL_WIDTH),
conv_std_logic_vector(19628,AMPL_WIDTH),
conv_std_logic_vector(19630,AMPL_WIDTH),
conv_std_logic_vector(19633,AMPL_WIDTH),
conv_std_logic_vector(19635,AMPL_WIDTH),
conv_std_logic_vector(19638,AMPL_WIDTH),
conv_std_logic_vector(19640,AMPL_WIDTH),
conv_std_logic_vector(19643,AMPL_WIDTH),
conv_std_logic_vector(19645,AMPL_WIDTH),
conv_std_logic_vector(19648,AMPL_WIDTH),
conv_std_logic_vector(19650,AMPL_WIDTH),
conv_std_logic_vector(19653,AMPL_WIDTH),
conv_std_logic_vector(19655,AMPL_WIDTH),
conv_std_logic_vector(19658,AMPL_WIDTH),
conv_std_logic_vector(19660,AMPL_WIDTH),
conv_std_logic_vector(19663,AMPL_WIDTH),
conv_std_logic_vector(19665,AMPL_WIDTH),
conv_std_logic_vector(19668,AMPL_WIDTH),
conv_std_logic_vector(19670,AMPL_WIDTH),
conv_std_logic_vector(19673,AMPL_WIDTH),
conv_std_logic_vector(19675,AMPL_WIDTH),
conv_std_logic_vector(19678,AMPL_WIDTH),
conv_std_logic_vector(19680,AMPL_WIDTH),
conv_std_logic_vector(19683,AMPL_WIDTH),
conv_std_logic_vector(19685,AMPL_WIDTH),
conv_std_logic_vector(19688,AMPL_WIDTH),
conv_std_logic_vector(19690,AMPL_WIDTH),
conv_std_logic_vector(19693,AMPL_WIDTH),
conv_std_logic_vector(19695,AMPL_WIDTH),
conv_std_logic_vector(19698,AMPL_WIDTH),
conv_std_logic_vector(19700,AMPL_WIDTH),
conv_std_logic_vector(19703,AMPL_WIDTH),
conv_std_logic_vector(19706,AMPL_WIDTH),
conv_std_logic_vector(19708,AMPL_WIDTH),
conv_std_logic_vector(19711,AMPL_WIDTH),
conv_std_logic_vector(19713,AMPL_WIDTH),
conv_std_logic_vector(19716,AMPL_WIDTH),
conv_std_logic_vector(19718,AMPL_WIDTH),
conv_std_logic_vector(19721,AMPL_WIDTH),
conv_std_logic_vector(19723,AMPL_WIDTH),
conv_std_logic_vector(19726,AMPL_WIDTH),
conv_std_logic_vector(19728,AMPL_WIDTH),
conv_std_logic_vector(19731,AMPL_WIDTH),
conv_std_logic_vector(19733,AMPL_WIDTH),
conv_std_logic_vector(19736,AMPL_WIDTH),
conv_std_logic_vector(19738,AMPL_WIDTH),
conv_std_logic_vector(19741,AMPL_WIDTH),
conv_std_logic_vector(19743,AMPL_WIDTH),
conv_std_logic_vector(19746,AMPL_WIDTH),
conv_std_logic_vector(19748,AMPL_WIDTH),
conv_std_logic_vector(19751,AMPL_WIDTH),
conv_std_logic_vector(19753,AMPL_WIDTH),
conv_std_logic_vector(19756,AMPL_WIDTH),
conv_std_logic_vector(19758,AMPL_WIDTH),
conv_std_logic_vector(19761,AMPL_WIDTH),
conv_std_logic_vector(19763,AMPL_WIDTH),
conv_std_logic_vector(19766,AMPL_WIDTH),
conv_std_logic_vector(19768,AMPL_WIDTH),
conv_std_logic_vector(19771,AMPL_WIDTH),
conv_std_logic_vector(19773,AMPL_WIDTH),
conv_std_logic_vector(19776,AMPL_WIDTH),
conv_std_logic_vector(19778,AMPL_WIDTH),
conv_std_logic_vector(19781,AMPL_WIDTH),
conv_std_logic_vector(19783,AMPL_WIDTH),
conv_std_logic_vector(19786,AMPL_WIDTH),
conv_std_logic_vector(19788,AMPL_WIDTH),
conv_std_logic_vector(19791,AMPL_WIDTH),
conv_std_logic_vector(19793,AMPL_WIDTH),
conv_std_logic_vector(19796,AMPL_WIDTH),
conv_std_logic_vector(19798,AMPL_WIDTH),
conv_std_logic_vector(19801,AMPL_WIDTH),
conv_std_logic_vector(19803,AMPL_WIDTH),
conv_std_logic_vector(19806,AMPL_WIDTH),
conv_std_logic_vector(19808,AMPL_WIDTH),
conv_std_logic_vector(19811,AMPL_WIDTH),
conv_std_logic_vector(19813,AMPL_WIDTH),
conv_std_logic_vector(19816,AMPL_WIDTH),
conv_std_logic_vector(19818,AMPL_WIDTH),
conv_std_logic_vector(19821,AMPL_WIDTH),
conv_std_logic_vector(19823,AMPL_WIDTH),
conv_std_logic_vector(19826,AMPL_WIDTH),
conv_std_logic_vector(19828,AMPL_WIDTH),
conv_std_logic_vector(19831,AMPL_WIDTH),
conv_std_logic_vector(19833,AMPL_WIDTH),
conv_std_logic_vector(19836,AMPL_WIDTH),
conv_std_logic_vector(19838,AMPL_WIDTH),
conv_std_logic_vector(19841,AMPL_WIDTH),
conv_std_logic_vector(19843,AMPL_WIDTH),
conv_std_logic_vector(19846,AMPL_WIDTH),
conv_std_logic_vector(19848,AMPL_WIDTH),
conv_std_logic_vector(19851,AMPL_WIDTH),
conv_std_logic_vector(19853,AMPL_WIDTH),
conv_std_logic_vector(19856,AMPL_WIDTH),
conv_std_logic_vector(19858,AMPL_WIDTH),
conv_std_logic_vector(19861,AMPL_WIDTH),
conv_std_logic_vector(19863,AMPL_WIDTH),
conv_std_logic_vector(19866,AMPL_WIDTH),
conv_std_logic_vector(19868,AMPL_WIDTH),
conv_std_logic_vector(19871,AMPL_WIDTH),
conv_std_logic_vector(19873,AMPL_WIDTH),
conv_std_logic_vector(19876,AMPL_WIDTH),
conv_std_logic_vector(19878,AMPL_WIDTH),
conv_std_logic_vector(19881,AMPL_WIDTH),
conv_std_logic_vector(19883,AMPL_WIDTH),
conv_std_logic_vector(19886,AMPL_WIDTH),
conv_std_logic_vector(19888,AMPL_WIDTH),
conv_std_logic_vector(19891,AMPL_WIDTH),
conv_std_logic_vector(19893,AMPL_WIDTH),
conv_std_logic_vector(19896,AMPL_WIDTH),
conv_std_logic_vector(19898,AMPL_WIDTH),
conv_std_logic_vector(19901,AMPL_WIDTH),
conv_std_logic_vector(19903,AMPL_WIDTH),
conv_std_logic_vector(19906,AMPL_WIDTH),
conv_std_logic_vector(19908,AMPL_WIDTH),
conv_std_logic_vector(19911,AMPL_WIDTH),
conv_std_logic_vector(19913,AMPL_WIDTH),
conv_std_logic_vector(19916,AMPL_WIDTH),
conv_std_logic_vector(19918,AMPL_WIDTH),
conv_std_logic_vector(19921,AMPL_WIDTH),
conv_std_logic_vector(19923,AMPL_WIDTH),
conv_std_logic_vector(19926,AMPL_WIDTH),
conv_std_logic_vector(19928,AMPL_WIDTH),
conv_std_logic_vector(19931,AMPL_WIDTH),
conv_std_logic_vector(19933,AMPL_WIDTH),
conv_std_logic_vector(19936,AMPL_WIDTH),
conv_std_logic_vector(19938,AMPL_WIDTH),
conv_std_logic_vector(19941,AMPL_WIDTH),
conv_std_logic_vector(19943,AMPL_WIDTH),
conv_std_logic_vector(19946,AMPL_WIDTH),
conv_std_logic_vector(19948,AMPL_WIDTH),
conv_std_logic_vector(19951,AMPL_WIDTH),
conv_std_logic_vector(19953,AMPL_WIDTH),
conv_std_logic_vector(19956,AMPL_WIDTH),
conv_std_logic_vector(19958,AMPL_WIDTH),
conv_std_logic_vector(19961,AMPL_WIDTH),
conv_std_logic_vector(19963,AMPL_WIDTH),
conv_std_logic_vector(19966,AMPL_WIDTH),
conv_std_logic_vector(19968,AMPL_WIDTH),
conv_std_logic_vector(19971,AMPL_WIDTH),
conv_std_logic_vector(19973,AMPL_WIDTH),
conv_std_logic_vector(19976,AMPL_WIDTH),
conv_std_logic_vector(19978,AMPL_WIDTH),
conv_std_logic_vector(19981,AMPL_WIDTH),
conv_std_logic_vector(19983,AMPL_WIDTH),
conv_std_logic_vector(19985,AMPL_WIDTH),
conv_std_logic_vector(19988,AMPL_WIDTH),
conv_std_logic_vector(19990,AMPL_WIDTH),
conv_std_logic_vector(19993,AMPL_WIDTH),
conv_std_logic_vector(19995,AMPL_WIDTH),
conv_std_logic_vector(19998,AMPL_WIDTH),
conv_std_logic_vector(20000,AMPL_WIDTH),
conv_std_logic_vector(20003,AMPL_WIDTH),
conv_std_logic_vector(20005,AMPL_WIDTH),
conv_std_logic_vector(20008,AMPL_WIDTH),
conv_std_logic_vector(20010,AMPL_WIDTH),
conv_std_logic_vector(20013,AMPL_WIDTH),
conv_std_logic_vector(20015,AMPL_WIDTH),
conv_std_logic_vector(20018,AMPL_WIDTH),
conv_std_logic_vector(20020,AMPL_WIDTH),
conv_std_logic_vector(20023,AMPL_WIDTH),
conv_std_logic_vector(20025,AMPL_WIDTH),
conv_std_logic_vector(20028,AMPL_WIDTH),
conv_std_logic_vector(20030,AMPL_WIDTH),
conv_std_logic_vector(20033,AMPL_WIDTH),
conv_std_logic_vector(20035,AMPL_WIDTH),
conv_std_logic_vector(20038,AMPL_WIDTH),
conv_std_logic_vector(20040,AMPL_WIDTH),
conv_std_logic_vector(20043,AMPL_WIDTH),
conv_std_logic_vector(20045,AMPL_WIDTH),
conv_std_logic_vector(20048,AMPL_WIDTH),
conv_std_logic_vector(20050,AMPL_WIDTH),
conv_std_logic_vector(20053,AMPL_WIDTH),
conv_std_logic_vector(20055,AMPL_WIDTH),
conv_std_logic_vector(20058,AMPL_WIDTH),
conv_std_logic_vector(20060,AMPL_WIDTH),
conv_std_logic_vector(20063,AMPL_WIDTH),
conv_std_logic_vector(20065,AMPL_WIDTH),
conv_std_logic_vector(20068,AMPL_WIDTH),
conv_std_logic_vector(20070,AMPL_WIDTH),
conv_std_logic_vector(20072,AMPL_WIDTH),
conv_std_logic_vector(20075,AMPL_WIDTH),
conv_std_logic_vector(20077,AMPL_WIDTH),
conv_std_logic_vector(20080,AMPL_WIDTH),
conv_std_logic_vector(20082,AMPL_WIDTH),
conv_std_logic_vector(20085,AMPL_WIDTH),
conv_std_logic_vector(20087,AMPL_WIDTH),
conv_std_logic_vector(20090,AMPL_WIDTH),
conv_std_logic_vector(20092,AMPL_WIDTH),
conv_std_logic_vector(20095,AMPL_WIDTH),
conv_std_logic_vector(20097,AMPL_WIDTH),
conv_std_logic_vector(20100,AMPL_WIDTH),
conv_std_logic_vector(20102,AMPL_WIDTH),
conv_std_logic_vector(20105,AMPL_WIDTH),
conv_std_logic_vector(20107,AMPL_WIDTH),
conv_std_logic_vector(20110,AMPL_WIDTH),
conv_std_logic_vector(20112,AMPL_WIDTH),
conv_std_logic_vector(20115,AMPL_WIDTH),
conv_std_logic_vector(20117,AMPL_WIDTH),
conv_std_logic_vector(20120,AMPL_WIDTH),
conv_std_logic_vector(20122,AMPL_WIDTH),
conv_std_logic_vector(20125,AMPL_WIDTH),
conv_std_logic_vector(20127,AMPL_WIDTH),
conv_std_logic_vector(20130,AMPL_WIDTH),
conv_std_logic_vector(20132,AMPL_WIDTH),
conv_std_logic_vector(20135,AMPL_WIDTH),
conv_std_logic_vector(20137,AMPL_WIDTH),
conv_std_logic_vector(20139,AMPL_WIDTH),
conv_std_logic_vector(20142,AMPL_WIDTH),
conv_std_logic_vector(20144,AMPL_WIDTH),
conv_std_logic_vector(20147,AMPL_WIDTH),
conv_std_logic_vector(20149,AMPL_WIDTH),
conv_std_logic_vector(20152,AMPL_WIDTH),
conv_std_logic_vector(20154,AMPL_WIDTH),
conv_std_logic_vector(20157,AMPL_WIDTH),
conv_std_logic_vector(20159,AMPL_WIDTH),
conv_std_logic_vector(20162,AMPL_WIDTH),
conv_std_logic_vector(20164,AMPL_WIDTH),
conv_std_logic_vector(20167,AMPL_WIDTH),
conv_std_logic_vector(20169,AMPL_WIDTH),
conv_std_logic_vector(20172,AMPL_WIDTH),
conv_std_logic_vector(20174,AMPL_WIDTH),
conv_std_logic_vector(20177,AMPL_WIDTH),
conv_std_logic_vector(20179,AMPL_WIDTH),
conv_std_logic_vector(20182,AMPL_WIDTH),
conv_std_logic_vector(20184,AMPL_WIDTH),
conv_std_logic_vector(20187,AMPL_WIDTH),
conv_std_logic_vector(20189,AMPL_WIDTH),
conv_std_logic_vector(20191,AMPL_WIDTH),
conv_std_logic_vector(20194,AMPL_WIDTH),
conv_std_logic_vector(20196,AMPL_WIDTH),
conv_std_logic_vector(20199,AMPL_WIDTH),
conv_std_logic_vector(20201,AMPL_WIDTH),
conv_std_logic_vector(20204,AMPL_WIDTH),
conv_std_logic_vector(20206,AMPL_WIDTH),
conv_std_logic_vector(20209,AMPL_WIDTH),
conv_std_logic_vector(20211,AMPL_WIDTH),
conv_std_logic_vector(20214,AMPL_WIDTH),
conv_std_logic_vector(20216,AMPL_WIDTH),
conv_std_logic_vector(20219,AMPL_WIDTH),
conv_std_logic_vector(20221,AMPL_WIDTH),
conv_std_logic_vector(20224,AMPL_WIDTH),
conv_std_logic_vector(20226,AMPL_WIDTH),
conv_std_logic_vector(20229,AMPL_WIDTH),
conv_std_logic_vector(20231,AMPL_WIDTH),
conv_std_logic_vector(20234,AMPL_WIDTH),
conv_std_logic_vector(20236,AMPL_WIDTH),
conv_std_logic_vector(20238,AMPL_WIDTH),
conv_std_logic_vector(20241,AMPL_WIDTH),
conv_std_logic_vector(20243,AMPL_WIDTH),
conv_std_logic_vector(20246,AMPL_WIDTH),
conv_std_logic_vector(20248,AMPL_WIDTH),
conv_std_logic_vector(20251,AMPL_WIDTH),
conv_std_logic_vector(20253,AMPL_WIDTH),
conv_std_logic_vector(20256,AMPL_WIDTH),
conv_std_logic_vector(20258,AMPL_WIDTH),
conv_std_logic_vector(20261,AMPL_WIDTH),
conv_std_logic_vector(20263,AMPL_WIDTH),
conv_std_logic_vector(20266,AMPL_WIDTH),
conv_std_logic_vector(20268,AMPL_WIDTH),
conv_std_logic_vector(20271,AMPL_WIDTH),
conv_std_logic_vector(20273,AMPL_WIDTH),
conv_std_logic_vector(20275,AMPL_WIDTH),
conv_std_logic_vector(20278,AMPL_WIDTH),
conv_std_logic_vector(20280,AMPL_WIDTH),
conv_std_logic_vector(20283,AMPL_WIDTH),
conv_std_logic_vector(20285,AMPL_WIDTH),
conv_std_logic_vector(20288,AMPL_WIDTH),
conv_std_logic_vector(20290,AMPL_WIDTH),
conv_std_logic_vector(20293,AMPL_WIDTH),
conv_std_logic_vector(20295,AMPL_WIDTH),
conv_std_logic_vector(20298,AMPL_WIDTH),
conv_std_logic_vector(20300,AMPL_WIDTH),
conv_std_logic_vector(20303,AMPL_WIDTH),
conv_std_logic_vector(20305,AMPL_WIDTH),
conv_std_logic_vector(20308,AMPL_WIDTH),
conv_std_logic_vector(20310,AMPL_WIDTH),
conv_std_logic_vector(20312,AMPL_WIDTH),
conv_std_logic_vector(20315,AMPL_WIDTH),
conv_std_logic_vector(20317,AMPL_WIDTH),
conv_std_logic_vector(20320,AMPL_WIDTH),
conv_std_logic_vector(20322,AMPL_WIDTH),
conv_std_logic_vector(20325,AMPL_WIDTH),
conv_std_logic_vector(20327,AMPL_WIDTH),
conv_std_logic_vector(20330,AMPL_WIDTH),
conv_std_logic_vector(20332,AMPL_WIDTH),
conv_std_logic_vector(20335,AMPL_WIDTH),
conv_std_logic_vector(20337,AMPL_WIDTH),
conv_std_logic_vector(20340,AMPL_WIDTH),
conv_std_logic_vector(20342,AMPL_WIDTH),
conv_std_logic_vector(20345,AMPL_WIDTH),
conv_std_logic_vector(20347,AMPL_WIDTH),
conv_std_logic_vector(20349,AMPL_WIDTH),
conv_std_logic_vector(20352,AMPL_WIDTH),
conv_std_logic_vector(20354,AMPL_WIDTH),
conv_std_logic_vector(20357,AMPL_WIDTH),
conv_std_logic_vector(20359,AMPL_WIDTH),
conv_std_logic_vector(20362,AMPL_WIDTH),
conv_std_logic_vector(20364,AMPL_WIDTH),
conv_std_logic_vector(20367,AMPL_WIDTH),
conv_std_logic_vector(20369,AMPL_WIDTH),
conv_std_logic_vector(20372,AMPL_WIDTH),
conv_std_logic_vector(20374,AMPL_WIDTH),
conv_std_logic_vector(20377,AMPL_WIDTH),
conv_std_logic_vector(20379,AMPL_WIDTH),
conv_std_logic_vector(20381,AMPL_WIDTH),
conv_std_logic_vector(20384,AMPL_WIDTH),
conv_std_logic_vector(20386,AMPL_WIDTH),
conv_std_logic_vector(20389,AMPL_WIDTH),
conv_std_logic_vector(20391,AMPL_WIDTH),
conv_std_logic_vector(20394,AMPL_WIDTH),
conv_std_logic_vector(20396,AMPL_WIDTH),
conv_std_logic_vector(20399,AMPL_WIDTH),
conv_std_logic_vector(20401,AMPL_WIDTH),
conv_std_logic_vector(20404,AMPL_WIDTH),
conv_std_logic_vector(20406,AMPL_WIDTH),
conv_std_logic_vector(20408,AMPL_WIDTH),
conv_std_logic_vector(20411,AMPL_WIDTH),
conv_std_logic_vector(20413,AMPL_WIDTH),
conv_std_logic_vector(20416,AMPL_WIDTH),
conv_std_logic_vector(20418,AMPL_WIDTH),
conv_std_logic_vector(20421,AMPL_WIDTH),
conv_std_logic_vector(20423,AMPL_WIDTH),
conv_std_logic_vector(20426,AMPL_WIDTH),
conv_std_logic_vector(20428,AMPL_WIDTH),
conv_std_logic_vector(20431,AMPL_WIDTH),
conv_std_logic_vector(20433,AMPL_WIDTH),
conv_std_logic_vector(20436,AMPL_WIDTH),
conv_std_logic_vector(20438,AMPL_WIDTH),
conv_std_logic_vector(20440,AMPL_WIDTH),
conv_std_logic_vector(20443,AMPL_WIDTH),
conv_std_logic_vector(20445,AMPL_WIDTH),
conv_std_logic_vector(20448,AMPL_WIDTH),
conv_std_logic_vector(20450,AMPL_WIDTH),
conv_std_logic_vector(20453,AMPL_WIDTH),
conv_std_logic_vector(20455,AMPL_WIDTH),
conv_std_logic_vector(20458,AMPL_WIDTH),
conv_std_logic_vector(20460,AMPL_WIDTH),
conv_std_logic_vector(20463,AMPL_WIDTH),
conv_std_logic_vector(20465,AMPL_WIDTH),
conv_std_logic_vector(20467,AMPL_WIDTH),
conv_std_logic_vector(20470,AMPL_WIDTH),
conv_std_logic_vector(20472,AMPL_WIDTH),
conv_std_logic_vector(20475,AMPL_WIDTH),
conv_std_logic_vector(20477,AMPL_WIDTH),
conv_std_logic_vector(20480,AMPL_WIDTH),
conv_std_logic_vector(20482,AMPL_WIDTH),
conv_std_logic_vector(20485,AMPL_WIDTH),
conv_std_logic_vector(20487,AMPL_WIDTH),
conv_std_logic_vector(20489,AMPL_WIDTH),
conv_std_logic_vector(20492,AMPL_WIDTH),
conv_std_logic_vector(20494,AMPL_WIDTH),
conv_std_logic_vector(20497,AMPL_WIDTH),
conv_std_logic_vector(20499,AMPL_WIDTH),
conv_std_logic_vector(20502,AMPL_WIDTH),
conv_std_logic_vector(20504,AMPL_WIDTH),
conv_std_logic_vector(20507,AMPL_WIDTH),
conv_std_logic_vector(20509,AMPL_WIDTH),
conv_std_logic_vector(20512,AMPL_WIDTH),
conv_std_logic_vector(20514,AMPL_WIDTH),
conv_std_logic_vector(20516,AMPL_WIDTH),
conv_std_logic_vector(20519,AMPL_WIDTH),
conv_std_logic_vector(20521,AMPL_WIDTH),
conv_std_logic_vector(20524,AMPL_WIDTH),
conv_std_logic_vector(20526,AMPL_WIDTH),
conv_std_logic_vector(20529,AMPL_WIDTH),
conv_std_logic_vector(20531,AMPL_WIDTH),
conv_std_logic_vector(20534,AMPL_WIDTH),
conv_std_logic_vector(20536,AMPL_WIDTH),
conv_std_logic_vector(20538,AMPL_WIDTH),
conv_std_logic_vector(20541,AMPL_WIDTH),
conv_std_logic_vector(20543,AMPL_WIDTH),
conv_std_logic_vector(20546,AMPL_WIDTH),
conv_std_logic_vector(20548,AMPL_WIDTH),
conv_std_logic_vector(20551,AMPL_WIDTH),
conv_std_logic_vector(20553,AMPL_WIDTH),
conv_std_logic_vector(20556,AMPL_WIDTH),
conv_std_logic_vector(20558,AMPL_WIDTH),
conv_std_logic_vector(20560,AMPL_WIDTH),
conv_std_logic_vector(20563,AMPL_WIDTH),
conv_std_logic_vector(20565,AMPL_WIDTH),
conv_std_logic_vector(20568,AMPL_WIDTH),
conv_std_logic_vector(20570,AMPL_WIDTH),
conv_std_logic_vector(20573,AMPL_WIDTH),
conv_std_logic_vector(20575,AMPL_WIDTH),
conv_std_logic_vector(20578,AMPL_WIDTH),
conv_std_logic_vector(20580,AMPL_WIDTH),
conv_std_logic_vector(20583,AMPL_WIDTH),
conv_std_logic_vector(20585,AMPL_WIDTH),
conv_std_logic_vector(20587,AMPL_WIDTH),
conv_std_logic_vector(20590,AMPL_WIDTH),
conv_std_logic_vector(20592,AMPL_WIDTH),
conv_std_logic_vector(20595,AMPL_WIDTH),
conv_std_logic_vector(20597,AMPL_WIDTH),
conv_std_logic_vector(20600,AMPL_WIDTH),
conv_std_logic_vector(20602,AMPL_WIDTH),
conv_std_logic_vector(20604,AMPL_WIDTH),
conv_std_logic_vector(20607,AMPL_WIDTH),
conv_std_logic_vector(20609,AMPL_WIDTH),
conv_std_logic_vector(20612,AMPL_WIDTH),
conv_std_logic_vector(20614,AMPL_WIDTH),
conv_std_logic_vector(20617,AMPL_WIDTH),
conv_std_logic_vector(20619,AMPL_WIDTH),
conv_std_logic_vector(20622,AMPL_WIDTH),
conv_std_logic_vector(20624,AMPL_WIDTH),
conv_std_logic_vector(20626,AMPL_WIDTH),
conv_std_logic_vector(20629,AMPL_WIDTH),
conv_std_logic_vector(20631,AMPL_WIDTH),
conv_std_logic_vector(20634,AMPL_WIDTH),
conv_std_logic_vector(20636,AMPL_WIDTH),
conv_std_logic_vector(20639,AMPL_WIDTH),
conv_std_logic_vector(20641,AMPL_WIDTH),
conv_std_logic_vector(20644,AMPL_WIDTH),
conv_std_logic_vector(20646,AMPL_WIDTH),
conv_std_logic_vector(20648,AMPL_WIDTH),
conv_std_logic_vector(20651,AMPL_WIDTH),
conv_std_logic_vector(20653,AMPL_WIDTH),
conv_std_logic_vector(20656,AMPL_WIDTH),
conv_std_logic_vector(20658,AMPL_WIDTH),
conv_std_logic_vector(20661,AMPL_WIDTH),
conv_std_logic_vector(20663,AMPL_WIDTH),
conv_std_logic_vector(20666,AMPL_WIDTH),
conv_std_logic_vector(20668,AMPL_WIDTH),
conv_std_logic_vector(20670,AMPL_WIDTH),
conv_std_logic_vector(20673,AMPL_WIDTH),
conv_std_logic_vector(20675,AMPL_WIDTH),
conv_std_logic_vector(20678,AMPL_WIDTH),
conv_std_logic_vector(20680,AMPL_WIDTH),
conv_std_logic_vector(20683,AMPL_WIDTH),
conv_std_logic_vector(20685,AMPL_WIDTH),
conv_std_logic_vector(20687,AMPL_WIDTH),
conv_std_logic_vector(20690,AMPL_WIDTH),
conv_std_logic_vector(20692,AMPL_WIDTH),
conv_std_logic_vector(20695,AMPL_WIDTH),
conv_std_logic_vector(20697,AMPL_WIDTH),
conv_std_logic_vector(20700,AMPL_WIDTH),
conv_std_logic_vector(20702,AMPL_WIDTH),
conv_std_logic_vector(20704,AMPL_WIDTH),
conv_std_logic_vector(20707,AMPL_WIDTH),
conv_std_logic_vector(20709,AMPL_WIDTH),
conv_std_logic_vector(20712,AMPL_WIDTH),
conv_std_logic_vector(20714,AMPL_WIDTH),
conv_std_logic_vector(20717,AMPL_WIDTH),
conv_std_logic_vector(20719,AMPL_WIDTH),
conv_std_logic_vector(20722,AMPL_WIDTH),
conv_std_logic_vector(20724,AMPL_WIDTH),
conv_std_logic_vector(20726,AMPL_WIDTH),
conv_std_logic_vector(20729,AMPL_WIDTH),
conv_std_logic_vector(20731,AMPL_WIDTH),
conv_std_logic_vector(20734,AMPL_WIDTH),
conv_std_logic_vector(20736,AMPL_WIDTH),
conv_std_logic_vector(20739,AMPL_WIDTH),
conv_std_logic_vector(20741,AMPL_WIDTH),
conv_std_logic_vector(20743,AMPL_WIDTH),
conv_std_logic_vector(20746,AMPL_WIDTH),
conv_std_logic_vector(20748,AMPL_WIDTH),
conv_std_logic_vector(20751,AMPL_WIDTH),
conv_std_logic_vector(20753,AMPL_WIDTH),
conv_std_logic_vector(20756,AMPL_WIDTH),
conv_std_logic_vector(20758,AMPL_WIDTH),
conv_std_logic_vector(20760,AMPL_WIDTH),
conv_std_logic_vector(20763,AMPL_WIDTH),
conv_std_logic_vector(20765,AMPL_WIDTH),
conv_std_logic_vector(20768,AMPL_WIDTH),
conv_std_logic_vector(20770,AMPL_WIDTH),
conv_std_logic_vector(20773,AMPL_WIDTH),
conv_std_logic_vector(20775,AMPL_WIDTH),
conv_std_logic_vector(20777,AMPL_WIDTH),
conv_std_logic_vector(20780,AMPL_WIDTH),
conv_std_logic_vector(20782,AMPL_WIDTH),
conv_std_logic_vector(20785,AMPL_WIDTH),
conv_std_logic_vector(20787,AMPL_WIDTH),
conv_std_logic_vector(20790,AMPL_WIDTH),
conv_std_logic_vector(20792,AMPL_WIDTH),
conv_std_logic_vector(20794,AMPL_WIDTH),
conv_std_logic_vector(20797,AMPL_WIDTH),
conv_std_logic_vector(20799,AMPL_WIDTH),
conv_std_logic_vector(20802,AMPL_WIDTH),
conv_std_logic_vector(20804,AMPL_WIDTH),
conv_std_logic_vector(20807,AMPL_WIDTH),
conv_std_logic_vector(20809,AMPL_WIDTH),
conv_std_logic_vector(20811,AMPL_WIDTH),
conv_std_logic_vector(20814,AMPL_WIDTH),
conv_std_logic_vector(20816,AMPL_WIDTH),
conv_std_logic_vector(20819,AMPL_WIDTH),
conv_std_logic_vector(20821,AMPL_WIDTH),
conv_std_logic_vector(20824,AMPL_WIDTH),
conv_std_logic_vector(20826,AMPL_WIDTH),
conv_std_logic_vector(20828,AMPL_WIDTH),
conv_std_logic_vector(20831,AMPL_WIDTH),
conv_std_logic_vector(20833,AMPL_WIDTH),
conv_std_logic_vector(20836,AMPL_WIDTH),
conv_std_logic_vector(20838,AMPL_WIDTH),
conv_std_logic_vector(20841,AMPL_WIDTH),
conv_std_logic_vector(20843,AMPL_WIDTH),
conv_std_logic_vector(20845,AMPL_WIDTH),
conv_std_logic_vector(20848,AMPL_WIDTH),
conv_std_logic_vector(20850,AMPL_WIDTH),
conv_std_logic_vector(20853,AMPL_WIDTH),
conv_std_logic_vector(20855,AMPL_WIDTH),
conv_std_logic_vector(20858,AMPL_WIDTH),
conv_std_logic_vector(20860,AMPL_WIDTH),
conv_std_logic_vector(20862,AMPL_WIDTH),
conv_std_logic_vector(20865,AMPL_WIDTH),
conv_std_logic_vector(20867,AMPL_WIDTH),
conv_std_logic_vector(20870,AMPL_WIDTH),
conv_std_logic_vector(20872,AMPL_WIDTH),
conv_std_logic_vector(20874,AMPL_WIDTH),
conv_std_logic_vector(20877,AMPL_WIDTH),
conv_std_logic_vector(20879,AMPL_WIDTH),
conv_std_logic_vector(20882,AMPL_WIDTH),
conv_std_logic_vector(20884,AMPL_WIDTH),
conv_std_logic_vector(20887,AMPL_WIDTH),
conv_std_logic_vector(20889,AMPL_WIDTH),
conv_std_logic_vector(20891,AMPL_WIDTH),
conv_std_logic_vector(20894,AMPL_WIDTH),
conv_std_logic_vector(20896,AMPL_WIDTH),
conv_std_logic_vector(20899,AMPL_WIDTH),
conv_std_logic_vector(20901,AMPL_WIDTH),
conv_std_logic_vector(20904,AMPL_WIDTH),
conv_std_logic_vector(20906,AMPL_WIDTH),
conv_std_logic_vector(20908,AMPL_WIDTH),
conv_std_logic_vector(20911,AMPL_WIDTH),
conv_std_logic_vector(20913,AMPL_WIDTH),
conv_std_logic_vector(20916,AMPL_WIDTH),
conv_std_logic_vector(20918,AMPL_WIDTH),
conv_std_logic_vector(20920,AMPL_WIDTH),
conv_std_logic_vector(20923,AMPL_WIDTH),
conv_std_logic_vector(20925,AMPL_WIDTH),
conv_std_logic_vector(20928,AMPL_WIDTH),
conv_std_logic_vector(20930,AMPL_WIDTH),
conv_std_logic_vector(20933,AMPL_WIDTH),
conv_std_logic_vector(20935,AMPL_WIDTH),
conv_std_logic_vector(20937,AMPL_WIDTH),
conv_std_logic_vector(20940,AMPL_WIDTH),
conv_std_logic_vector(20942,AMPL_WIDTH),
conv_std_logic_vector(20945,AMPL_WIDTH),
conv_std_logic_vector(20947,AMPL_WIDTH),
conv_std_logic_vector(20949,AMPL_WIDTH),
conv_std_logic_vector(20952,AMPL_WIDTH),
conv_std_logic_vector(20954,AMPL_WIDTH),
conv_std_logic_vector(20957,AMPL_WIDTH),
conv_std_logic_vector(20959,AMPL_WIDTH),
conv_std_logic_vector(20962,AMPL_WIDTH),
conv_std_logic_vector(20964,AMPL_WIDTH),
conv_std_logic_vector(20966,AMPL_WIDTH),
conv_std_logic_vector(20969,AMPL_WIDTH),
conv_std_logic_vector(20971,AMPL_WIDTH),
conv_std_logic_vector(20974,AMPL_WIDTH),
conv_std_logic_vector(20976,AMPL_WIDTH),
conv_std_logic_vector(20978,AMPL_WIDTH),
conv_std_logic_vector(20981,AMPL_WIDTH),
conv_std_logic_vector(20983,AMPL_WIDTH),
conv_std_logic_vector(20986,AMPL_WIDTH),
conv_std_logic_vector(20988,AMPL_WIDTH),
conv_std_logic_vector(20990,AMPL_WIDTH),
conv_std_logic_vector(20993,AMPL_WIDTH),
conv_std_logic_vector(20995,AMPL_WIDTH),
conv_std_logic_vector(20998,AMPL_WIDTH),
conv_std_logic_vector(21000,AMPL_WIDTH),
conv_std_logic_vector(21003,AMPL_WIDTH),
conv_std_logic_vector(21005,AMPL_WIDTH),
conv_std_logic_vector(21007,AMPL_WIDTH),
conv_std_logic_vector(21010,AMPL_WIDTH),
conv_std_logic_vector(21012,AMPL_WIDTH),
conv_std_logic_vector(21015,AMPL_WIDTH),
conv_std_logic_vector(21017,AMPL_WIDTH),
conv_std_logic_vector(21019,AMPL_WIDTH),
conv_std_logic_vector(21022,AMPL_WIDTH),
conv_std_logic_vector(21024,AMPL_WIDTH),
conv_std_logic_vector(21027,AMPL_WIDTH),
conv_std_logic_vector(21029,AMPL_WIDTH),
conv_std_logic_vector(21031,AMPL_WIDTH),
conv_std_logic_vector(21034,AMPL_WIDTH),
conv_std_logic_vector(21036,AMPL_WIDTH),
conv_std_logic_vector(21039,AMPL_WIDTH),
conv_std_logic_vector(21041,AMPL_WIDTH),
conv_std_logic_vector(21043,AMPL_WIDTH),
conv_std_logic_vector(21046,AMPL_WIDTH),
conv_std_logic_vector(21048,AMPL_WIDTH),
conv_std_logic_vector(21051,AMPL_WIDTH),
conv_std_logic_vector(21053,AMPL_WIDTH),
conv_std_logic_vector(21056,AMPL_WIDTH),
conv_std_logic_vector(21058,AMPL_WIDTH),
conv_std_logic_vector(21060,AMPL_WIDTH),
conv_std_logic_vector(21063,AMPL_WIDTH),
conv_std_logic_vector(21065,AMPL_WIDTH),
conv_std_logic_vector(21068,AMPL_WIDTH),
conv_std_logic_vector(21070,AMPL_WIDTH),
conv_std_logic_vector(21072,AMPL_WIDTH),
conv_std_logic_vector(21075,AMPL_WIDTH),
conv_std_logic_vector(21077,AMPL_WIDTH),
conv_std_logic_vector(21080,AMPL_WIDTH),
conv_std_logic_vector(21082,AMPL_WIDTH),
conv_std_logic_vector(21084,AMPL_WIDTH),
conv_std_logic_vector(21087,AMPL_WIDTH),
conv_std_logic_vector(21089,AMPL_WIDTH),
conv_std_logic_vector(21092,AMPL_WIDTH),
conv_std_logic_vector(21094,AMPL_WIDTH),
conv_std_logic_vector(21096,AMPL_WIDTH),
conv_std_logic_vector(21099,AMPL_WIDTH),
conv_std_logic_vector(21101,AMPL_WIDTH),
conv_std_logic_vector(21104,AMPL_WIDTH),
conv_std_logic_vector(21106,AMPL_WIDTH),
conv_std_logic_vector(21108,AMPL_WIDTH),
conv_std_logic_vector(21111,AMPL_WIDTH),
conv_std_logic_vector(21113,AMPL_WIDTH),
conv_std_logic_vector(21116,AMPL_WIDTH),
conv_std_logic_vector(21118,AMPL_WIDTH),
conv_std_logic_vector(21120,AMPL_WIDTH),
conv_std_logic_vector(21123,AMPL_WIDTH),
conv_std_logic_vector(21125,AMPL_WIDTH),
conv_std_logic_vector(21128,AMPL_WIDTH),
conv_std_logic_vector(21130,AMPL_WIDTH),
conv_std_logic_vector(21132,AMPL_WIDTH),
conv_std_logic_vector(21135,AMPL_WIDTH),
conv_std_logic_vector(21137,AMPL_WIDTH),
conv_std_logic_vector(21140,AMPL_WIDTH),
conv_std_logic_vector(21142,AMPL_WIDTH),
conv_std_logic_vector(21144,AMPL_WIDTH),
conv_std_logic_vector(21147,AMPL_WIDTH),
conv_std_logic_vector(21149,AMPL_WIDTH),
conv_std_logic_vector(21152,AMPL_WIDTH),
conv_std_logic_vector(21154,AMPL_WIDTH),
conv_std_logic_vector(21156,AMPL_WIDTH),
conv_std_logic_vector(21159,AMPL_WIDTH),
conv_std_logic_vector(21161,AMPL_WIDTH),
conv_std_logic_vector(21164,AMPL_WIDTH),
conv_std_logic_vector(21166,AMPL_WIDTH),
conv_std_logic_vector(21168,AMPL_WIDTH),
conv_std_logic_vector(21171,AMPL_WIDTH),
conv_std_logic_vector(21173,AMPL_WIDTH),
conv_std_logic_vector(21176,AMPL_WIDTH),
conv_std_logic_vector(21178,AMPL_WIDTH),
conv_std_logic_vector(21180,AMPL_WIDTH),
conv_std_logic_vector(21183,AMPL_WIDTH),
conv_std_logic_vector(21185,AMPL_WIDTH),
conv_std_logic_vector(21188,AMPL_WIDTH),
conv_std_logic_vector(21190,AMPL_WIDTH),
conv_std_logic_vector(21192,AMPL_WIDTH),
conv_std_logic_vector(21195,AMPL_WIDTH),
conv_std_logic_vector(21197,AMPL_WIDTH),
conv_std_logic_vector(21200,AMPL_WIDTH),
conv_std_logic_vector(21202,AMPL_WIDTH),
conv_std_logic_vector(21204,AMPL_WIDTH),
conv_std_logic_vector(21207,AMPL_WIDTH),
conv_std_logic_vector(21209,AMPL_WIDTH),
conv_std_logic_vector(21212,AMPL_WIDTH),
conv_std_logic_vector(21214,AMPL_WIDTH),
conv_std_logic_vector(21216,AMPL_WIDTH),
conv_std_logic_vector(21219,AMPL_WIDTH),
conv_std_logic_vector(21221,AMPL_WIDTH),
conv_std_logic_vector(21224,AMPL_WIDTH),
conv_std_logic_vector(21226,AMPL_WIDTH),
conv_std_logic_vector(21228,AMPL_WIDTH),
conv_std_logic_vector(21231,AMPL_WIDTH),
conv_std_logic_vector(21233,AMPL_WIDTH),
conv_std_logic_vector(21236,AMPL_WIDTH),
conv_std_logic_vector(21238,AMPL_WIDTH),
conv_std_logic_vector(21240,AMPL_WIDTH),
conv_std_logic_vector(21243,AMPL_WIDTH),
conv_std_logic_vector(21245,AMPL_WIDTH),
conv_std_logic_vector(21247,AMPL_WIDTH),
conv_std_logic_vector(21250,AMPL_WIDTH),
conv_std_logic_vector(21252,AMPL_WIDTH),
conv_std_logic_vector(21255,AMPL_WIDTH),
conv_std_logic_vector(21257,AMPL_WIDTH),
conv_std_logic_vector(21259,AMPL_WIDTH),
conv_std_logic_vector(21262,AMPL_WIDTH),
conv_std_logic_vector(21264,AMPL_WIDTH),
conv_std_logic_vector(21267,AMPL_WIDTH),
conv_std_logic_vector(21269,AMPL_WIDTH),
conv_std_logic_vector(21271,AMPL_WIDTH),
conv_std_logic_vector(21274,AMPL_WIDTH),
conv_std_logic_vector(21276,AMPL_WIDTH),
conv_std_logic_vector(21279,AMPL_WIDTH),
conv_std_logic_vector(21281,AMPL_WIDTH),
conv_std_logic_vector(21283,AMPL_WIDTH),
conv_std_logic_vector(21286,AMPL_WIDTH),
conv_std_logic_vector(21288,AMPL_WIDTH),
conv_std_logic_vector(21290,AMPL_WIDTH),
conv_std_logic_vector(21293,AMPL_WIDTH),
conv_std_logic_vector(21295,AMPL_WIDTH),
conv_std_logic_vector(21298,AMPL_WIDTH),
conv_std_logic_vector(21300,AMPL_WIDTH),
conv_std_logic_vector(21302,AMPL_WIDTH),
conv_std_logic_vector(21305,AMPL_WIDTH),
conv_std_logic_vector(21307,AMPL_WIDTH),
conv_std_logic_vector(21310,AMPL_WIDTH),
conv_std_logic_vector(21312,AMPL_WIDTH),
conv_std_logic_vector(21314,AMPL_WIDTH),
conv_std_logic_vector(21317,AMPL_WIDTH),
conv_std_logic_vector(21319,AMPL_WIDTH),
conv_std_logic_vector(21322,AMPL_WIDTH),
conv_std_logic_vector(21324,AMPL_WIDTH),
conv_std_logic_vector(21326,AMPL_WIDTH),
conv_std_logic_vector(21329,AMPL_WIDTH),
conv_std_logic_vector(21331,AMPL_WIDTH),
conv_std_logic_vector(21333,AMPL_WIDTH),
conv_std_logic_vector(21336,AMPL_WIDTH),
conv_std_logic_vector(21338,AMPL_WIDTH),
conv_std_logic_vector(21341,AMPL_WIDTH),
conv_std_logic_vector(21343,AMPL_WIDTH),
conv_std_logic_vector(21345,AMPL_WIDTH),
conv_std_logic_vector(21348,AMPL_WIDTH),
conv_std_logic_vector(21350,AMPL_WIDTH),
conv_std_logic_vector(21353,AMPL_WIDTH),
conv_std_logic_vector(21355,AMPL_WIDTH),
conv_std_logic_vector(21357,AMPL_WIDTH),
conv_std_logic_vector(21360,AMPL_WIDTH),
conv_std_logic_vector(21362,AMPL_WIDTH),
conv_std_logic_vector(21364,AMPL_WIDTH),
conv_std_logic_vector(21367,AMPL_WIDTH),
conv_std_logic_vector(21369,AMPL_WIDTH),
conv_std_logic_vector(21372,AMPL_WIDTH),
conv_std_logic_vector(21374,AMPL_WIDTH),
conv_std_logic_vector(21376,AMPL_WIDTH),
conv_std_logic_vector(21379,AMPL_WIDTH),
conv_std_logic_vector(21381,AMPL_WIDTH),
conv_std_logic_vector(21383,AMPL_WIDTH),
conv_std_logic_vector(21386,AMPL_WIDTH),
conv_std_logic_vector(21388,AMPL_WIDTH),
conv_std_logic_vector(21391,AMPL_WIDTH),
conv_std_logic_vector(21393,AMPL_WIDTH),
conv_std_logic_vector(21395,AMPL_WIDTH),
conv_std_logic_vector(21398,AMPL_WIDTH),
conv_std_logic_vector(21400,AMPL_WIDTH),
conv_std_logic_vector(21403,AMPL_WIDTH),
conv_std_logic_vector(21405,AMPL_WIDTH),
conv_std_logic_vector(21407,AMPL_WIDTH),
conv_std_logic_vector(21410,AMPL_WIDTH),
conv_std_logic_vector(21412,AMPL_WIDTH),
conv_std_logic_vector(21414,AMPL_WIDTH),
conv_std_logic_vector(21417,AMPL_WIDTH),
conv_std_logic_vector(21419,AMPL_WIDTH),
conv_std_logic_vector(21422,AMPL_WIDTH),
conv_std_logic_vector(21424,AMPL_WIDTH),
conv_std_logic_vector(21426,AMPL_WIDTH),
conv_std_logic_vector(21429,AMPL_WIDTH),
conv_std_logic_vector(21431,AMPL_WIDTH),
conv_std_logic_vector(21433,AMPL_WIDTH),
conv_std_logic_vector(21436,AMPL_WIDTH),
conv_std_logic_vector(21438,AMPL_WIDTH),
conv_std_logic_vector(21441,AMPL_WIDTH),
conv_std_logic_vector(21443,AMPL_WIDTH),
conv_std_logic_vector(21445,AMPL_WIDTH),
conv_std_logic_vector(21448,AMPL_WIDTH),
conv_std_logic_vector(21450,AMPL_WIDTH),
conv_std_logic_vector(21452,AMPL_WIDTH),
conv_std_logic_vector(21455,AMPL_WIDTH),
conv_std_logic_vector(21457,AMPL_WIDTH),
conv_std_logic_vector(21460,AMPL_WIDTH),
conv_std_logic_vector(21462,AMPL_WIDTH),
conv_std_logic_vector(21464,AMPL_WIDTH),
conv_std_logic_vector(21467,AMPL_WIDTH),
conv_std_logic_vector(21469,AMPL_WIDTH),
conv_std_logic_vector(21471,AMPL_WIDTH),
conv_std_logic_vector(21474,AMPL_WIDTH),
conv_std_logic_vector(21476,AMPL_WIDTH),
conv_std_logic_vector(21479,AMPL_WIDTH),
conv_std_logic_vector(21481,AMPL_WIDTH),
conv_std_logic_vector(21483,AMPL_WIDTH),
conv_std_logic_vector(21486,AMPL_WIDTH),
conv_std_logic_vector(21488,AMPL_WIDTH),
conv_std_logic_vector(21490,AMPL_WIDTH),
conv_std_logic_vector(21493,AMPL_WIDTH),
conv_std_logic_vector(21495,AMPL_WIDTH),
conv_std_logic_vector(21498,AMPL_WIDTH),
conv_std_logic_vector(21500,AMPL_WIDTH),
conv_std_logic_vector(21502,AMPL_WIDTH),
conv_std_logic_vector(21505,AMPL_WIDTH),
conv_std_logic_vector(21507,AMPL_WIDTH),
conv_std_logic_vector(21509,AMPL_WIDTH),
conv_std_logic_vector(21512,AMPL_WIDTH),
conv_std_logic_vector(21514,AMPL_WIDTH),
conv_std_logic_vector(21516,AMPL_WIDTH),
conv_std_logic_vector(21519,AMPL_WIDTH),
conv_std_logic_vector(21521,AMPL_WIDTH),
conv_std_logic_vector(21524,AMPL_WIDTH),
conv_std_logic_vector(21526,AMPL_WIDTH),
conv_std_logic_vector(21528,AMPL_WIDTH),
conv_std_logic_vector(21531,AMPL_WIDTH),
conv_std_logic_vector(21533,AMPL_WIDTH),
conv_std_logic_vector(21535,AMPL_WIDTH),
conv_std_logic_vector(21538,AMPL_WIDTH),
conv_std_logic_vector(21540,AMPL_WIDTH),
conv_std_logic_vector(21543,AMPL_WIDTH),
conv_std_logic_vector(21545,AMPL_WIDTH),
conv_std_logic_vector(21547,AMPL_WIDTH),
conv_std_logic_vector(21550,AMPL_WIDTH),
conv_std_logic_vector(21552,AMPL_WIDTH),
conv_std_logic_vector(21554,AMPL_WIDTH),
conv_std_logic_vector(21557,AMPL_WIDTH),
conv_std_logic_vector(21559,AMPL_WIDTH),
conv_std_logic_vector(21561,AMPL_WIDTH),
conv_std_logic_vector(21564,AMPL_WIDTH),
conv_std_logic_vector(21566,AMPL_WIDTH),
conv_std_logic_vector(21569,AMPL_WIDTH),
conv_std_logic_vector(21571,AMPL_WIDTH),
conv_std_logic_vector(21573,AMPL_WIDTH),
conv_std_logic_vector(21576,AMPL_WIDTH),
conv_std_logic_vector(21578,AMPL_WIDTH),
conv_std_logic_vector(21580,AMPL_WIDTH),
conv_std_logic_vector(21583,AMPL_WIDTH),
conv_std_logic_vector(21585,AMPL_WIDTH),
conv_std_logic_vector(21587,AMPL_WIDTH),
conv_std_logic_vector(21590,AMPL_WIDTH),
conv_std_logic_vector(21592,AMPL_WIDTH),
conv_std_logic_vector(21595,AMPL_WIDTH),
conv_std_logic_vector(21597,AMPL_WIDTH),
conv_std_logic_vector(21599,AMPL_WIDTH),
conv_std_logic_vector(21602,AMPL_WIDTH),
conv_std_logic_vector(21604,AMPL_WIDTH),
conv_std_logic_vector(21606,AMPL_WIDTH),
conv_std_logic_vector(21609,AMPL_WIDTH),
conv_std_logic_vector(21611,AMPL_WIDTH),
conv_std_logic_vector(21613,AMPL_WIDTH),
conv_std_logic_vector(21616,AMPL_WIDTH),
conv_std_logic_vector(21618,AMPL_WIDTH),
conv_std_logic_vector(21621,AMPL_WIDTH),
conv_std_logic_vector(21623,AMPL_WIDTH),
conv_std_logic_vector(21625,AMPL_WIDTH),
conv_std_logic_vector(21628,AMPL_WIDTH),
conv_std_logic_vector(21630,AMPL_WIDTH),
conv_std_logic_vector(21632,AMPL_WIDTH),
conv_std_logic_vector(21635,AMPL_WIDTH),
conv_std_logic_vector(21637,AMPL_WIDTH),
conv_std_logic_vector(21639,AMPL_WIDTH),
conv_std_logic_vector(21642,AMPL_WIDTH),
conv_std_logic_vector(21644,AMPL_WIDTH),
conv_std_logic_vector(21646,AMPL_WIDTH),
conv_std_logic_vector(21649,AMPL_WIDTH),
conv_std_logic_vector(21651,AMPL_WIDTH),
conv_std_logic_vector(21654,AMPL_WIDTH),
conv_std_logic_vector(21656,AMPL_WIDTH),
conv_std_logic_vector(21658,AMPL_WIDTH),
conv_std_logic_vector(21661,AMPL_WIDTH),
conv_std_logic_vector(21663,AMPL_WIDTH),
conv_std_logic_vector(21665,AMPL_WIDTH),
conv_std_logic_vector(21668,AMPL_WIDTH),
conv_std_logic_vector(21670,AMPL_WIDTH),
conv_std_logic_vector(21672,AMPL_WIDTH),
conv_std_logic_vector(21675,AMPL_WIDTH),
conv_std_logic_vector(21677,AMPL_WIDTH),
conv_std_logic_vector(21679,AMPL_WIDTH),
conv_std_logic_vector(21682,AMPL_WIDTH),
conv_std_logic_vector(21684,AMPL_WIDTH),
conv_std_logic_vector(21687,AMPL_WIDTH),
conv_std_logic_vector(21689,AMPL_WIDTH),
conv_std_logic_vector(21691,AMPL_WIDTH),
conv_std_logic_vector(21694,AMPL_WIDTH),
conv_std_logic_vector(21696,AMPL_WIDTH),
conv_std_logic_vector(21698,AMPL_WIDTH),
conv_std_logic_vector(21701,AMPL_WIDTH),
conv_std_logic_vector(21703,AMPL_WIDTH),
conv_std_logic_vector(21705,AMPL_WIDTH),
conv_std_logic_vector(21708,AMPL_WIDTH),
conv_std_logic_vector(21710,AMPL_WIDTH),
conv_std_logic_vector(21712,AMPL_WIDTH),
conv_std_logic_vector(21715,AMPL_WIDTH),
conv_std_logic_vector(21717,AMPL_WIDTH),
conv_std_logic_vector(21719,AMPL_WIDTH),
conv_std_logic_vector(21722,AMPL_WIDTH),
conv_std_logic_vector(21724,AMPL_WIDTH),
conv_std_logic_vector(21727,AMPL_WIDTH),
conv_std_logic_vector(21729,AMPL_WIDTH),
conv_std_logic_vector(21731,AMPL_WIDTH),
conv_std_logic_vector(21734,AMPL_WIDTH),
conv_std_logic_vector(21736,AMPL_WIDTH),
conv_std_logic_vector(21738,AMPL_WIDTH),
conv_std_logic_vector(21741,AMPL_WIDTH),
conv_std_logic_vector(21743,AMPL_WIDTH),
conv_std_logic_vector(21745,AMPL_WIDTH),
conv_std_logic_vector(21748,AMPL_WIDTH),
conv_std_logic_vector(21750,AMPL_WIDTH),
conv_std_logic_vector(21752,AMPL_WIDTH),
conv_std_logic_vector(21755,AMPL_WIDTH),
conv_std_logic_vector(21757,AMPL_WIDTH),
conv_std_logic_vector(21759,AMPL_WIDTH),
conv_std_logic_vector(21762,AMPL_WIDTH),
conv_std_logic_vector(21764,AMPL_WIDTH),
conv_std_logic_vector(21766,AMPL_WIDTH),
conv_std_logic_vector(21769,AMPL_WIDTH),
conv_std_logic_vector(21771,AMPL_WIDTH),
conv_std_logic_vector(21774,AMPL_WIDTH),
conv_std_logic_vector(21776,AMPL_WIDTH),
conv_std_logic_vector(21778,AMPL_WIDTH),
conv_std_logic_vector(21781,AMPL_WIDTH),
conv_std_logic_vector(21783,AMPL_WIDTH),
conv_std_logic_vector(21785,AMPL_WIDTH),
conv_std_logic_vector(21788,AMPL_WIDTH),
conv_std_logic_vector(21790,AMPL_WIDTH),
conv_std_logic_vector(21792,AMPL_WIDTH),
conv_std_logic_vector(21795,AMPL_WIDTH),
conv_std_logic_vector(21797,AMPL_WIDTH),
conv_std_logic_vector(21799,AMPL_WIDTH),
conv_std_logic_vector(21802,AMPL_WIDTH),
conv_std_logic_vector(21804,AMPL_WIDTH),
conv_std_logic_vector(21806,AMPL_WIDTH),
conv_std_logic_vector(21809,AMPL_WIDTH),
conv_std_logic_vector(21811,AMPL_WIDTH),
conv_std_logic_vector(21813,AMPL_WIDTH),
conv_std_logic_vector(21816,AMPL_WIDTH),
conv_std_logic_vector(21818,AMPL_WIDTH),
conv_std_logic_vector(21820,AMPL_WIDTH),
conv_std_logic_vector(21823,AMPL_WIDTH),
conv_std_logic_vector(21825,AMPL_WIDTH),
conv_std_logic_vector(21827,AMPL_WIDTH),
conv_std_logic_vector(21830,AMPL_WIDTH),
conv_std_logic_vector(21832,AMPL_WIDTH),
conv_std_logic_vector(21835,AMPL_WIDTH),
conv_std_logic_vector(21837,AMPL_WIDTH),
conv_std_logic_vector(21839,AMPL_WIDTH),
conv_std_logic_vector(21842,AMPL_WIDTH),
conv_std_logic_vector(21844,AMPL_WIDTH),
conv_std_logic_vector(21846,AMPL_WIDTH),
conv_std_logic_vector(21849,AMPL_WIDTH),
conv_std_logic_vector(21851,AMPL_WIDTH),
conv_std_logic_vector(21853,AMPL_WIDTH),
conv_std_logic_vector(21856,AMPL_WIDTH),
conv_std_logic_vector(21858,AMPL_WIDTH),
conv_std_logic_vector(21860,AMPL_WIDTH),
conv_std_logic_vector(21863,AMPL_WIDTH),
conv_std_logic_vector(21865,AMPL_WIDTH),
conv_std_logic_vector(21867,AMPL_WIDTH),
conv_std_logic_vector(21870,AMPL_WIDTH),
conv_std_logic_vector(21872,AMPL_WIDTH),
conv_std_logic_vector(21874,AMPL_WIDTH),
conv_std_logic_vector(21877,AMPL_WIDTH),
conv_std_logic_vector(21879,AMPL_WIDTH),
conv_std_logic_vector(21881,AMPL_WIDTH),
conv_std_logic_vector(21884,AMPL_WIDTH),
conv_std_logic_vector(21886,AMPL_WIDTH),
conv_std_logic_vector(21888,AMPL_WIDTH),
conv_std_logic_vector(21891,AMPL_WIDTH),
conv_std_logic_vector(21893,AMPL_WIDTH),
conv_std_logic_vector(21895,AMPL_WIDTH),
conv_std_logic_vector(21898,AMPL_WIDTH),
conv_std_logic_vector(21900,AMPL_WIDTH),
conv_std_logic_vector(21902,AMPL_WIDTH),
conv_std_logic_vector(21905,AMPL_WIDTH),
conv_std_logic_vector(21907,AMPL_WIDTH),
conv_std_logic_vector(21909,AMPL_WIDTH),
conv_std_logic_vector(21912,AMPL_WIDTH),
conv_std_logic_vector(21914,AMPL_WIDTH),
conv_std_logic_vector(21916,AMPL_WIDTH),
conv_std_logic_vector(21919,AMPL_WIDTH),
conv_std_logic_vector(21921,AMPL_WIDTH),
conv_std_logic_vector(21923,AMPL_WIDTH),
conv_std_logic_vector(21926,AMPL_WIDTH),
conv_std_logic_vector(21928,AMPL_WIDTH),
conv_std_logic_vector(21930,AMPL_WIDTH),
conv_std_logic_vector(21933,AMPL_WIDTH),
conv_std_logic_vector(21935,AMPL_WIDTH),
conv_std_logic_vector(21937,AMPL_WIDTH),
conv_std_logic_vector(21940,AMPL_WIDTH),
conv_std_logic_vector(21942,AMPL_WIDTH),
conv_std_logic_vector(21944,AMPL_WIDTH),
conv_std_logic_vector(21947,AMPL_WIDTH),
conv_std_logic_vector(21949,AMPL_WIDTH),
conv_std_logic_vector(21951,AMPL_WIDTH),
conv_std_logic_vector(21954,AMPL_WIDTH),
conv_std_logic_vector(21956,AMPL_WIDTH),
conv_std_logic_vector(21958,AMPL_WIDTH),
conv_std_logic_vector(21961,AMPL_WIDTH),
conv_std_logic_vector(21963,AMPL_WIDTH),
conv_std_logic_vector(21965,AMPL_WIDTH),
conv_std_logic_vector(21968,AMPL_WIDTH),
conv_std_logic_vector(21970,AMPL_WIDTH),
conv_std_logic_vector(21972,AMPL_WIDTH),
conv_std_logic_vector(21975,AMPL_WIDTH),
conv_std_logic_vector(21977,AMPL_WIDTH),
conv_std_logic_vector(21979,AMPL_WIDTH),
conv_std_logic_vector(21982,AMPL_WIDTH),
conv_std_logic_vector(21984,AMPL_WIDTH),
conv_std_logic_vector(21986,AMPL_WIDTH),
conv_std_logic_vector(21989,AMPL_WIDTH),
conv_std_logic_vector(21991,AMPL_WIDTH),
conv_std_logic_vector(21993,AMPL_WIDTH),
conv_std_logic_vector(21996,AMPL_WIDTH),
conv_std_logic_vector(21998,AMPL_WIDTH),
conv_std_logic_vector(22000,AMPL_WIDTH),
conv_std_logic_vector(22003,AMPL_WIDTH),
conv_std_logic_vector(22005,AMPL_WIDTH),
conv_std_logic_vector(22007,AMPL_WIDTH),
conv_std_logic_vector(22010,AMPL_WIDTH),
conv_std_logic_vector(22012,AMPL_WIDTH),
conv_std_logic_vector(22014,AMPL_WIDTH),
conv_std_logic_vector(22017,AMPL_WIDTH),
conv_std_logic_vector(22019,AMPL_WIDTH),
conv_std_logic_vector(22021,AMPL_WIDTH),
conv_std_logic_vector(22024,AMPL_WIDTH),
conv_std_logic_vector(22026,AMPL_WIDTH),
conv_std_logic_vector(22028,AMPL_WIDTH),
conv_std_logic_vector(22031,AMPL_WIDTH),
conv_std_logic_vector(22033,AMPL_WIDTH),
conv_std_logic_vector(22035,AMPL_WIDTH),
conv_std_logic_vector(22038,AMPL_WIDTH),
conv_std_logic_vector(22040,AMPL_WIDTH),
conv_std_logic_vector(22042,AMPL_WIDTH),
conv_std_logic_vector(22045,AMPL_WIDTH),
conv_std_logic_vector(22047,AMPL_WIDTH),
conv_std_logic_vector(22049,AMPL_WIDTH),
conv_std_logic_vector(22051,AMPL_WIDTH),
conv_std_logic_vector(22054,AMPL_WIDTH),
conv_std_logic_vector(22056,AMPL_WIDTH),
conv_std_logic_vector(22058,AMPL_WIDTH),
conv_std_logic_vector(22061,AMPL_WIDTH),
conv_std_logic_vector(22063,AMPL_WIDTH),
conv_std_logic_vector(22065,AMPL_WIDTH),
conv_std_logic_vector(22068,AMPL_WIDTH),
conv_std_logic_vector(22070,AMPL_WIDTH),
conv_std_logic_vector(22072,AMPL_WIDTH),
conv_std_logic_vector(22075,AMPL_WIDTH),
conv_std_logic_vector(22077,AMPL_WIDTH),
conv_std_logic_vector(22079,AMPL_WIDTH),
conv_std_logic_vector(22082,AMPL_WIDTH),
conv_std_logic_vector(22084,AMPL_WIDTH),
conv_std_logic_vector(22086,AMPL_WIDTH),
conv_std_logic_vector(22089,AMPL_WIDTH),
conv_std_logic_vector(22091,AMPL_WIDTH),
conv_std_logic_vector(22093,AMPL_WIDTH),
conv_std_logic_vector(22096,AMPL_WIDTH),
conv_std_logic_vector(22098,AMPL_WIDTH),
conv_std_logic_vector(22100,AMPL_WIDTH),
conv_std_logic_vector(22103,AMPL_WIDTH),
conv_std_logic_vector(22105,AMPL_WIDTH),
conv_std_logic_vector(22107,AMPL_WIDTH),
conv_std_logic_vector(22110,AMPL_WIDTH),
conv_std_logic_vector(22112,AMPL_WIDTH),
conv_std_logic_vector(22114,AMPL_WIDTH),
conv_std_logic_vector(22116,AMPL_WIDTH),
conv_std_logic_vector(22119,AMPL_WIDTH),
conv_std_logic_vector(22121,AMPL_WIDTH),
conv_std_logic_vector(22123,AMPL_WIDTH),
conv_std_logic_vector(22126,AMPL_WIDTH),
conv_std_logic_vector(22128,AMPL_WIDTH),
conv_std_logic_vector(22130,AMPL_WIDTH),
conv_std_logic_vector(22133,AMPL_WIDTH),
conv_std_logic_vector(22135,AMPL_WIDTH),
conv_std_logic_vector(22137,AMPL_WIDTH),
conv_std_logic_vector(22140,AMPL_WIDTH),
conv_std_logic_vector(22142,AMPL_WIDTH),
conv_std_logic_vector(22144,AMPL_WIDTH),
conv_std_logic_vector(22147,AMPL_WIDTH),
conv_std_logic_vector(22149,AMPL_WIDTH),
conv_std_logic_vector(22151,AMPL_WIDTH),
conv_std_logic_vector(22154,AMPL_WIDTH),
conv_std_logic_vector(22156,AMPL_WIDTH),
conv_std_logic_vector(22158,AMPL_WIDTH),
conv_std_logic_vector(22160,AMPL_WIDTH),
conv_std_logic_vector(22163,AMPL_WIDTH),
conv_std_logic_vector(22165,AMPL_WIDTH),
conv_std_logic_vector(22167,AMPL_WIDTH),
conv_std_logic_vector(22170,AMPL_WIDTH),
conv_std_logic_vector(22172,AMPL_WIDTH),
conv_std_logic_vector(22174,AMPL_WIDTH),
conv_std_logic_vector(22177,AMPL_WIDTH),
conv_std_logic_vector(22179,AMPL_WIDTH),
conv_std_logic_vector(22181,AMPL_WIDTH),
conv_std_logic_vector(22184,AMPL_WIDTH),
conv_std_logic_vector(22186,AMPL_WIDTH),
conv_std_logic_vector(22188,AMPL_WIDTH),
conv_std_logic_vector(22191,AMPL_WIDTH),
conv_std_logic_vector(22193,AMPL_WIDTH),
conv_std_logic_vector(22195,AMPL_WIDTH),
conv_std_logic_vector(22197,AMPL_WIDTH),
conv_std_logic_vector(22200,AMPL_WIDTH),
conv_std_logic_vector(22202,AMPL_WIDTH),
conv_std_logic_vector(22204,AMPL_WIDTH),
conv_std_logic_vector(22207,AMPL_WIDTH),
conv_std_logic_vector(22209,AMPL_WIDTH),
conv_std_logic_vector(22211,AMPL_WIDTH),
conv_std_logic_vector(22214,AMPL_WIDTH),
conv_std_logic_vector(22216,AMPL_WIDTH),
conv_std_logic_vector(22218,AMPL_WIDTH),
conv_std_logic_vector(22221,AMPL_WIDTH),
conv_std_logic_vector(22223,AMPL_WIDTH),
conv_std_logic_vector(22225,AMPL_WIDTH),
conv_std_logic_vector(22227,AMPL_WIDTH),
conv_std_logic_vector(22230,AMPL_WIDTH),
conv_std_logic_vector(22232,AMPL_WIDTH),
conv_std_logic_vector(22234,AMPL_WIDTH),
conv_std_logic_vector(22237,AMPL_WIDTH),
conv_std_logic_vector(22239,AMPL_WIDTH),
conv_std_logic_vector(22241,AMPL_WIDTH),
conv_std_logic_vector(22244,AMPL_WIDTH),
conv_std_logic_vector(22246,AMPL_WIDTH),
conv_std_logic_vector(22248,AMPL_WIDTH),
conv_std_logic_vector(22251,AMPL_WIDTH),
conv_std_logic_vector(22253,AMPL_WIDTH),
conv_std_logic_vector(22255,AMPL_WIDTH),
conv_std_logic_vector(22257,AMPL_WIDTH),
conv_std_logic_vector(22260,AMPL_WIDTH),
conv_std_logic_vector(22262,AMPL_WIDTH),
conv_std_logic_vector(22264,AMPL_WIDTH),
conv_std_logic_vector(22267,AMPL_WIDTH),
conv_std_logic_vector(22269,AMPL_WIDTH),
conv_std_logic_vector(22271,AMPL_WIDTH),
conv_std_logic_vector(22274,AMPL_WIDTH),
conv_std_logic_vector(22276,AMPL_WIDTH),
conv_std_logic_vector(22278,AMPL_WIDTH),
conv_std_logic_vector(22281,AMPL_WIDTH),
conv_std_logic_vector(22283,AMPL_WIDTH),
conv_std_logic_vector(22285,AMPL_WIDTH),
conv_std_logic_vector(22287,AMPL_WIDTH),
conv_std_logic_vector(22290,AMPL_WIDTH),
conv_std_logic_vector(22292,AMPL_WIDTH),
conv_std_logic_vector(22294,AMPL_WIDTH),
conv_std_logic_vector(22297,AMPL_WIDTH),
conv_std_logic_vector(22299,AMPL_WIDTH),
conv_std_logic_vector(22301,AMPL_WIDTH),
conv_std_logic_vector(22304,AMPL_WIDTH),
conv_std_logic_vector(22306,AMPL_WIDTH),
conv_std_logic_vector(22308,AMPL_WIDTH),
conv_std_logic_vector(22310,AMPL_WIDTH),
conv_std_logic_vector(22313,AMPL_WIDTH),
conv_std_logic_vector(22315,AMPL_WIDTH),
conv_std_logic_vector(22317,AMPL_WIDTH),
conv_std_logic_vector(22320,AMPL_WIDTH),
conv_std_logic_vector(22322,AMPL_WIDTH),
conv_std_logic_vector(22324,AMPL_WIDTH),
conv_std_logic_vector(22327,AMPL_WIDTH),
conv_std_logic_vector(22329,AMPL_WIDTH),
conv_std_logic_vector(22331,AMPL_WIDTH),
conv_std_logic_vector(22333,AMPL_WIDTH),
conv_std_logic_vector(22336,AMPL_WIDTH),
conv_std_logic_vector(22338,AMPL_WIDTH),
conv_std_logic_vector(22340,AMPL_WIDTH),
conv_std_logic_vector(22343,AMPL_WIDTH),
conv_std_logic_vector(22345,AMPL_WIDTH),
conv_std_logic_vector(22347,AMPL_WIDTH),
conv_std_logic_vector(22350,AMPL_WIDTH),
conv_std_logic_vector(22352,AMPL_WIDTH),
conv_std_logic_vector(22354,AMPL_WIDTH),
conv_std_logic_vector(22356,AMPL_WIDTH),
conv_std_logic_vector(22359,AMPL_WIDTH),
conv_std_logic_vector(22361,AMPL_WIDTH),
conv_std_logic_vector(22363,AMPL_WIDTH),
conv_std_logic_vector(22366,AMPL_WIDTH),
conv_std_logic_vector(22368,AMPL_WIDTH),
conv_std_logic_vector(22370,AMPL_WIDTH),
conv_std_logic_vector(22373,AMPL_WIDTH),
conv_std_logic_vector(22375,AMPL_WIDTH),
conv_std_logic_vector(22377,AMPL_WIDTH),
conv_std_logic_vector(22379,AMPL_WIDTH),
conv_std_logic_vector(22382,AMPL_WIDTH),
conv_std_logic_vector(22384,AMPL_WIDTH),
conv_std_logic_vector(22386,AMPL_WIDTH),
conv_std_logic_vector(22389,AMPL_WIDTH),
conv_std_logic_vector(22391,AMPL_WIDTH),
conv_std_logic_vector(22393,AMPL_WIDTH),
conv_std_logic_vector(22395,AMPL_WIDTH),
conv_std_logic_vector(22398,AMPL_WIDTH),
conv_std_logic_vector(22400,AMPL_WIDTH),
conv_std_logic_vector(22402,AMPL_WIDTH),
conv_std_logic_vector(22405,AMPL_WIDTH),
conv_std_logic_vector(22407,AMPL_WIDTH),
conv_std_logic_vector(22409,AMPL_WIDTH),
conv_std_logic_vector(22411,AMPL_WIDTH),
conv_std_logic_vector(22414,AMPL_WIDTH),
conv_std_logic_vector(22416,AMPL_WIDTH),
conv_std_logic_vector(22418,AMPL_WIDTH),
conv_std_logic_vector(22421,AMPL_WIDTH),
conv_std_logic_vector(22423,AMPL_WIDTH),
conv_std_logic_vector(22425,AMPL_WIDTH),
conv_std_logic_vector(22428,AMPL_WIDTH),
conv_std_logic_vector(22430,AMPL_WIDTH),
conv_std_logic_vector(22432,AMPL_WIDTH),
conv_std_logic_vector(22434,AMPL_WIDTH),
conv_std_logic_vector(22437,AMPL_WIDTH),
conv_std_logic_vector(22439,AMPL_WIDTH),
conv_std_logic_vector(22441,AMPL_WIDTH),
conv_std_logic_vector(22444,AMPL_WIDTH),
conv_std_logic_vector(22446,AMPL_WIDTH),
conv_std_logic_vector(22448,AMPL_WIDTH),
conv_std_logic_vector(22450,AMPL_WIDTH),
conv_std_logic_vector(22453,AMPL_WIDTH),
conv_std_logic_vector(22455,AMPL_WIDTH),
conv_std_logic_vector(22457,AMPL_WIDTH),
conv_std_logic_vector(22460,AMPL_WIDTH),
conv_std_logic_vector(22462,AMPL_WIDTH),
conv_std_logic_vector(22464,AMPL_WIDTH),
conv_std_logic_vector(22466,AMPL_WIDTH),
conv_std_logic_vector(22469,AMPL_WIDTH),
conv_std_logic_vector(22471,AMPL_WIDTH),
conv_std_logic_vector(22473,AMPL_WIDTH),
conv_std_logic_vector(22476,AMPL_WIDTH),
conv_std_logic_vector(22478,AMPL_WIDTH),
conv_std_logic_vector(22480,AMPL_WIDTH),
conv_std_logic_vector(22482,AMPL_WIDTH),
conv_std_logic_vector(22485,AMPL_WIDTH),
conv_std_logic_vector(22487,AMPL_WIDTH),
conv_std_logic_vector(22489,AMPL_WIDTH),
conv_std_logic_vector(22492,AMPL_WIDTH),
conv_std_logic_vector(22494,AMPL_WIDTH),
conv_std_logic_vector(22496,AMPL_WIDTH),
conv_std_logic_vector(22498,AMPL_WIDTH),
conv_std_logic_vector(22501,AMPL_WIDTH),
conv_std_logic_vector(22503,AMPL_WIDTH),
conv_std_logic_vector(22505,AMPL_WIDTH),
conv_std_logic_vector(22508,AMPL_WIDTH),
conv_std_logic_vector(22510,AMPL_WIDTH),
conv_std_logic_vector(22512,AMPL_WIDTH),
conv_std_logic_vector(22514,AMPL_WIDTH),
conv_std_logic_vector(22517,AMPL_WIDTH),
conv_std_logic_vector(22519,AMPL_WIDTH),
conv_std_logic_vector(22521,AMPL_WIDTH),
conv_std_logic_vector(22524,AMPL_WIDTH),
conv_std_logic_vector(22526,AMPL_WIDTH),
conv_std_logic_vector(22528,AMPL_WIDTH),
conv_std_logic_vector(22530,AMPL_WIDTH),
conv_std_logic_vector(22533,AMPL_WIDTH),
conv_std_logic_vector(22535,AMPL_WIDTH),
conv_std_logic_vector(22537,AMPL_WIDTH),
conv_std_logic_vector(22540,AMPL_WIDTH),
conv_std_logic_vector(22542,AMPL_WIDTH),
conv_std_logic_vector(22544,AMPL_WIDTH),
conv_std_logic_vector(22546,AMPL_WIDTH),
conv_std_logic_vector(22549,AMPL_WIDTH),
conv_std_logic_vector(22551,AMPL_WIDTH),
conv_std_logic_vector(22553,AMPL_WIDTH),
conv_std_logic_vector(22555,AMPL_WIDTH),
conv_std_logic_vector(22558,AMPL_WIDTH),
conv_std_logic_vector(22560,AMPL_WIDTH),
conv_std_logic_vector(22562,AMPL_WIDTH),
conv_std_logic_vector(22565,AMPL_WIDTH),
conv_std_logic_vector(22567,AMPL_WIDTH),
conv_std_logic_vector(22569,AMPL_WIDTH),
conv_std_logic_vector(22571,AMPL_WIDTH),
conv_std_logic_vector(22574,AMPL_WIDTH),
conv_std_logic_vector(22576,AMPL_WIDTH),
conv_std_logic_vector(22578,AMPL_WIDTH),
conv_std_logic_vector(22581,AMPL_WIDTH),
conv_std_logic_vector(22583,AMPL_WIDTH),
conv_std_logic_vector(22585,AMPL_WIDTH),
conv_std_logic_vector(22587,AMPL_WIDTH),
conv_std_logic_vector(22590,AMPL_WIDTH),
conv_std_logic_vector(22592,AMPL_WIDTH),
conv_std_logic_vector(22594,AMPL_WIDTH),
conv_std_logic_vector(22596,AMPL_WIDTH),
conv_std_logic_vector(22599,AMPL_WIDTH),
conv_std_logic_vector(22601,AMPL_WIDTH),
conv_std_logic_vector(22603,AMPL_WIDTH),
conv_std_logic_vector(22606,AMPL_WIDTH),
conv_std_logic_vector(22608,AMPL_WIDTH),
conv_std_logic_vector(22610,AMPL_WIDTH),
conv_std_logic_vector(22612,AMPL_WIDTH),
conv_std_logic_vector(22615,AMPL_WIDTH),
conv_std_logic_vector(22617,AMPL_WIDTH),
conv_std_logic_vector(22619,AMPL_WIDTH),
conv_std_logic_vector(22621,AMPL_WIDTH),
conv_std_logic_vector(22624,AMPL_WIDTH),
conv_std_logic_vector(22626,AMPL_WIDTH),
conv_std_logic_vector(22628,AMPL_WIDTH),
conv_std_logic_vector(22631,AMPL_WIDTH),
conv_std_logic_vector(22633,AMPL_WIDTH),
conv_std_logic_vector(22635,AMPL_WIDTH),
conv_std_logic_vector(22637,AMPL_WIDTH),
conv_std_logic_vector(22640,AMPL_WIDTH),
conv_std_logic_vector(22642,AMPL_WIDTH),
conv_std_logic_vector(22644,AMPL_WIDTH),
conv_std_logic_vector(22646,AMPL_WIDTH),
conv_std_logic_vector(22649,AMPL_WIDTH),
conv_std_logic_vector(22651,AMPL_WIDTH),
conv_std_logic_vector(22653,AMPL_WIDTH),
conv_std_logic_vector(22656,AMPL_WIDTH),
conv_std_logic_vector(22658,AMPL_WIDTH),
conv_std_logic_vector(22660,AMPL_WIDTH),
conv_std_logic_vector(22662,AMPL_WIDTH),
conv_std_logic_vector(22665,AMPL_WIDTH),
conv_std_logic_vector(22667,AMPL_WIDTH),
conv_std_logic_vector(22669,AMPL_WIDTH),
conv_std_logic_vector(22671,AMPL_WIDTH),
conv_std_logic_vector(22674,AMPL_WIDTH),
conv_std_logic_vector(22676,AMPL_WIDTH),
conv_std_logic_vector(22678,AMPL_WIDTH),
conv_std_logic_vector(22680,AMPL_WIDTH),
conv_std_logic_vector(22683,AMPL_WIDTH),
conv_std_logic_vector(22685,AMPL_WIDTH),
conv_std_logic_vector(22687,AMPL_WIDTH),
conv_std_logic_vector(22690,AMPL_WIDTH),
conv_std_logic_vector(22692,AMPL_WIDTH),
conv_std_logic_vector(22694,AMPL_WIDTH),
conv_std_logic_vector(22696,AMPL_WIDTH),
conv_std_logic_vector(22699,AMPL_WIDTH),
conv_std_logic_vector(22701,AMPL_WIDTH),
conv_std_logic_vector(22703,AMPL_WIDTH),
conv_std_logic_vector(22705,AMPL_WIDTH),
conv_std_logic_vector(22708,AMPL_WIDTH),
conv_std_logic_vector(22710,AMPL_WIDTH),
conv_std_logic_vector(22712,AMPL_WIDTH),
conv_std_logic_vector(22714,AMPL_WIDTH),
conv_std_logic_vector(22717,AMPL_WIDTH),
conv_std_logic_vector(22719,AMPL_WIDTH),
conv_std_logic_vector(22721,AMPL_WIDTH),
conv_std_logic_vector(22724,AMPL_WIDTH),
conv_std_logic_vector(22726,AMPL_WIDTH),
conv_std_logic_vector(22728,AMPL_WIDTH),
conv_std_logic_vector(22730,AMPL_WIDTH),
conv_std_logic_vector(22733,AMPL_WIDTH),
conv_std_logic_vector(22735,AMPL_WIDTH),
conv_std_logic_vector(22737,AMPL_WIDTH),
conv_std_logic_vector(22739,AMPL_WIDTH),
conv_std_logic_vector(22742,AMPL_WIDTH),
conv_std_logic_vector(22744,AMPL_WIDTH),
conv_std_logic_vector(22746,AMPL_WIDTH),
conv_std_logic_vector(22748,AMPL_WIDTH),
conv_std_logic_vector(22751,AMPL_WIDTH),
conv_std_logic_vector(22753,AMPL_WIDTH),
conv_std_logic_vector(22755,AMPL_WIDTH),
conv_std_logic_vector(22757,AMPL_WIDTH),
conv_std_logic_vector(22760,AMPL_WIDTH),
conv_std_logic_vector(22762,AMPL_WIDTH),
conv_std_logic_vector(22764,AMPL_WIDTH),
conv_std_logic_vector(22766,AMPL_WIDTH),
conv_std_logic_vector(22769,AMPL_WIDTH),
conv_std_logic_vector(22771,AMPL_WIDTH),
conv_std_logic_vector(22773,AMPL_WIDTH),
conv_std_logic_vector(22776,AMPL_WIDTH),
conv_std_logic_vector(22778,AMPL_WIDTH),
conv_std_logic_vector(22780,AMPL_WIDTH),
conv_std_logic_vector(22782,AMPL_WIDTH),
conv_std_logic_vector(22785,AMPL_WIDTH),
conv_std_logic_vector(22787,AMPL_WIDTH),
conv_std_logic_vector(22789,AMPL_WIDTH),
conv_std_logic_vector(22791,AMPL_WIDTH),
conv_std_logic_vector(22794,AMPL_WIDTH),
conv_std_logic_vector(22796,AMPL_WIDTH),
conv_std_logic_vector(22798,AMPL_WIDTH),
conv_std_logic_vector(22800,AMPL_WIDTH),
conv_std_logic_vector(22803,AMPL_WIDTH),
conv_std_logic_vector(22805,AMPL_WIDTH),
conv_std_logic_vector(22807,AMPL_WIDTH),
conv_std_logic_vector(22809,AMPL_WIDTH),
conv_std_logic_vector(22812,AMPL_WIDTH),
conv_std_logic_vector(22814,AMPL_WIDTH),
conv_std_logic_vector(22816,AMPL_WIDTH),
conv_std_logic_vector(22818,AMPL_WIDTH),
conv_std_logic_vector(22821,AMPL_WIDTH),
conv_std_logic_vector(22823,AMPL_WIDTH),
conv_std_logic_vector(22825,AMPL_WIDTH),
conv_std_logic_vector(22827,AMPL_WIDTH),
conv_std_logic_vector(22830,AMPL_WIDTH),
conv_std_logic_vector(22832,AMPL_WIDTH),
conv_std_logic_vector(22834,AMPL_WIDTH),
conv_std_logic_vector(22836,AMPL_WIDTH),
conv_std_logic_vector(22839,AMPL_WIDTH),
conv_std_logic_vector(22841,AMPL_WIDTH),
conv_std_logic_vector(22843,AMPL_WIDTH),
conv_std_logic_vector(22845,AMPL_WIDTH),
conv_std_logic_vector(22848,AMPL_WIDTH),
conv_std_logic_vector(22850,AMPL_WIDTH),
conv_std_logic_vector(22852,AMPL_WIDTH),
conv_std_logic_vector(22854,AMPL_WIDTH),
conv_std_logic_vector(22857,AMPL_WIDTH),
conv_std_logic_vector(22859,AMPL_WIDTH),
conv_std_logic_vector(22861,AMPL_WIDTH),
conv_std_logic_vector(22863,AMPL_WIDTH),
conv_std_logic_vector(22866,AMPL_WIDTH),
conv_std_logic_vector(22868,AMPL_WIDTH),
conv_std_logic_vector(22870,AMPL_WIDTH),
conv_std_logic_vector(22872,AMPL_WIDTH),
conv_std_logic_vector(22875,AMPL_WIDTH),
conv_std_logic_vector(22877,AMPL_WIDTH),
conv_std_logic_vector(22879,AMPL_WIDTH),
conv_std_logic_vector(22881,AMPL_WIDTH),
conv_std_logic_vector(22884,AMPL_WIDTH),
conv_std_logic_vector(22886,AMPL_WIDTH),
conv_std_logic_vector(22888,AMPL_WIDTH),
conv_std_logic_vector(22890,AMPL_WIDTH),
conv_std_logic_vector(22893,AMPL_WIDTH),
conv_std_logic_vector(22895,AMPL_WIDTH),
conv_std_logic_vector(22897,AMPL_WIDTH),
conv_std_logic_vector(22899,AMPL_WIDTH),
conv_std_logic_vector(22902,AMPL_WIDTH),
conv_std_logic_vector(22904,AMPL_WIDTH),
conv_std_logic_vector(22906,AMPL_WIDTH),
conv_std_logic_vector(22908,AMPL_WIDTH),
conv_std_logic_vector(22911,AMPL_WIDTH),
conv_std_logic_vector(22913,AMPL_WIDTH),
conv_std_logic_vector(22915,AMPL_WIDTH),
conv_std_logic_vector(22917,AMPL_WIDTH),
conv_std_logic_vector(22920,AMPL_WIDTH),
conv_std_logic_vector(22922,AMPL_WIDTH),
conv_std_logic_vector(22924,AMPL_WIDTH),
conv_std_logic_vector(22926,AMPL_WIDTH),
conv_std_logic_vector(22929,AMPL_WIDTH),
conv_std_logic_vector(22931,AMPL_WIDTH),
conv_std_logic_vector(22933,AMPL_WIDTH),
conv_std_logic_vector(22935,AMPL_WIDTH),
conv_std_logic_vector(22938,AMPL_WIDTH),
conv_std_logic_vector(22940,AMPL_WIDTH),
conv_std_logic_vector(22942,AMPL_WIDTH),
conv_std_logic_vector(22944,AMPL_WIDTH),
conv_std_logic_vector(22947,AMPL_WIDTH),
conv_std_logic_vector(22949,AMPL_WIDTH),
conv_std_logic_vector(22951,AMPL_WIDTH),
conv_std_logic_vector(22953,AMPL_WIDTH),
conv_std_logic_vector(22956,AMPL_WIDTH),
conv_std_logic_vector(22958,AMPL_WIDTH),
conv_std_logic_vector(22960,AMPL_WIDTH),
conv_std_logic_vector(22962,AMPL_WIDTH),
conv_std_logic_vector(22965,AMPL_WIDTH),
conv_std_logic_vector(22967,AMPL_WIDTH),
conv_std_logic_vector(22969,AMPL_WIDTH),
conv_std_logic_vector(22971,AMPL_WIDTH),
conv_std_logic_vector(22973,AMPL_WIDTH),
conv_std_logic_vector(22976,AMPL_WIDTH),
conv_std_logic_vector(22978,AMPL_WIDTH),
conv_std_logic_vector(22980,AMPL_WIDTH),
conv_std_logic_vector(22982,AMPL_WIDTH),
conv_std_logic_vector(22985,AMPL_WIDTH),
conv_std_logic_vector(22987,AMPL_WIDTH),
conv_std_logic_vector(22989,AMPL_WIDTH),
conv_std_logic_vector(22991,AMPL_WIDTH),
conv_std_logic_vector(22994,AMPL_WIDTH),
conv_std_logic_vector(22996,AMPL_WIDTH),
conv_std_logic_vector(22998,AMPL_WIDTH),
conv_std_logic_vector(23000,AMPL_WIDTH),
conv_std_logic_vector(23003,AMPL_WIDTH),
conv_std_logic_vector(23005,AMPL_WIDTH),
conv_std_logic_vector(23007,AMPL_WIDTH),
conv_std_logic_vector(23009,AMPL_WIDTH),
conv_std_logic_vector(23012,AMPL_WIDTH),
conv_std_logic_vector(23014,AMPL_WIDTH),
conv_std_logic_vector(23016,AMPL_WIDTH),
conv_std_logic_vector(23018,AMPL_WIDTH),
conv_std_logic_vector(23020,AMPL_WIDTH),
conv_std_logic_vector(23023,AMPL_WIDTH),
conv_std_logic_vector(23025,AMPL_WIDTH),
conv_std_logic_vector(23027,AMPL_WIDTH),
conv_std_logic_vector(23029,AMPL_WIDTH),
conv_std_logic_vector(23032,AMPL_WIDTH),
conv_std_logic_vector(23034,AMPL_WIDTH),
conv_std_logic_vector(23036,AMPL_WIDTH),
conv_std_logic_vector(23038,AMPL_WIDTH),
conv_std_logic_vector(23041,AMPL_WIDTH),
conv_std_logic_vector(23043,AMPL_WIDTH),
conv_std_logic_vector(23045,AMPL_WIDTH),
conv_std_logic_vector(23047,AMPL_WIDTH),
conv_std_logic_vector(23050,AMPL_WIDTH),
conv_std_logic_vector(23052,AMPL_WIDTH),
conv_std_logic_vector(23054,AMPL_WIDTH),
conv_std_logic_vector(23056,AMPL_WIDTH),
conv_std_logic_vector(23058,AMPL_WIDTH),
conv_std_logic_vector(23061,AMPL_WIDTH),
conv_std_logic_vector(23063,AMPL_WIDTH),
conv_std_logic_vector(23065,AMPL_WIDTH),
conv_std_logic_vector(23067,AMPL_WIDTH),
conv_std_logic_vector(23070,AMPL_WIDTH),
conv_std_logic_vector(23072,AMPL_WIDTH),
conv_std_logic_vector(23074,AMPL_WIDTH),
conv_std_logic_vector(23076,AMPL_WIDTH),
conv_std_logic_vector(23079,AMPL_WIDTH),
conv_std_logic_vector(23081,AMPL_WIDTH),
conv_std_logic_vector(23083,AMPL_WIDTH),
conv_std_logic_vector(23085,AMPL_WIDTH),
conv_std_logic_vector(23087,AMPL_WIDTH),
conv_std_logic_vector(23090,AMPL_WIDTH),
conv_std_logic_vector(23092,AMPL_WIDTH),
conv_std_logic_vector(23094,AMPL_WIDTH),
conv_std_logic_vector(23096,AMPL_WIDTH),
conv_std_logic_vector(23099,AMPL_WIDTH),
conv_std_logic_vector(23101,AMPL_WIDTH),
conv_std_logic_vector(23103,AMPL_WIDTH),
conv_std_logic_vector(23105,AMPL_WIDTH),
conv_std_logic_vector(23107,AMPL_WIDTH),
conv_std_logic_vector(23110,AMPL_WIDTH),
conv_std_logic_vector(23112,AMPL_WIDTH),
conv_std_logic_vector(23114,AMPL_WIDTH),
conv_std_logic_vector(23116,AMPL_WIDTH),
conv_std_logic_vector(23119,AMPL_WIDTH),
conv_std_logic_vector(23121,AMPL_WIDTH),
conv_std_logic_vector(23123,AMPL_WIDTH),
conv_std_logic_vector(23125,AMPL_WIDTH),
conv_std_logic_vector(23128,AMPL_WIDTH),
conv_std_logic_vector(23130,AMPL_WIDTH),
conv_std_logic_vector(23132,AMPL_WIDTH),
conv_std_logic_vector(23134,AMPL_WIDTH),
conv_std_logic_vector(23136,AMPL_WIDTH),
conv_std_logic_vector(23139,AMPL_WIDTH),
conv_std_logic_vector(23141,AMPL_WIDTH),
conv_std_logic_vector(23143,AMPL_WIDTH),
conv_std_logic_vector(23145,AMPL_WIDTH),
conv_std_logic_vector(23148,AMPL_WIDTH),
conv_std_logic_vector(23150,AMPL_WIDTH),
conv_std_logic_vector(23152,AMPL_WIDTH),
conv_std_logic_vector(23154,AMPL_WIDTH),
conv_std_logic_vector(23156,AMPL_WIDTH),
conv_std_logic_vector(23159,AMPL_WIDTH),
conv_std_logic_vector(23161,AMPL_WIDTH),
conv_std_logic_vector(23163,AMPL_WIDTH),
conv_std_logic_vector(23165,AMPL_WIDTH),
conv_std_logic_vector(23168,AMPL_WIDTH),
conv_std_logic_vector(23170,AMPL_WIDTH),
conv_std_logic_vector(23172,AMPL_WIDTH),
conv_std_logic_vector(23174,AMPL_WIDTH),
conv_std_logic_vector(23176,AMPL_WIDTH),
conv_std_logic_vector(23179,AMPL_WIDTH),
conv_std_logic_vector(23181,AMPL_WIDTH),
conv_std_logic_vector(23183,AMPL_WIDTH),
conv_std_logic_vector(23185,AMPL_WIDTH),
conv_std_logic_vector(23188,AMPL_WIDTH),
conv_std_logic_vector(23190,AMPL_WIDTH),
conv_std_logic_vector(23192,AMPL_WIDTH),
conv_std_logic_vector(23194,AMPL_WIDTH),
conv_std_logic_vector(23196,AMPL_WIDTH),
conv_std_logic_vector(23199,AMPL_WIDTH),
conv_std_logic_vector(23201,AMPL_WIDTH),
conv_std_logic_vector(23203,AMPL_WIDTH),
conv_std_logic_vector(23205,AMPL_WIDTH),
conv_std_logic_vector(23208,AMPL_WIDTH),
conv_std_logic_vector(23210,AMPL_WIDTH),
conv_std_logic_vector(23212,AMPL_WIDTH),
conv_std_logic_vector(23214,AMPL_WIDTH),
conv_std_logic_vector(23216,AMPL_WIDTH),
conv_std_logic_vector(23219,AMPL_WIDTH),
conv_std_logic_vector(23221,AMPL_WIDTH),
conv_std_logic_vector(23223,AMPL_WIDTH),
conv_std_logic_vector(23225,AMPL_WIDTH),
conv_std_logic_vector(23227,AMPL_WIDTH),
conv_std_logic_vector(23230,AMPL_WIDTH),
conv_std_logic_vector(23232,AMPL_WIDTH),
conv_std_logic_vector(23234,AMPL_WIDTH),
conv_std_logic_vector(23236,AMPL_WIDTH),
conv_std_logic_vector(23239,AMPL_WIDTH),
conv_std_logic_vector(23241,AMPL_WIDTH),
conv_std_logic_vector(23243,AMPL_WIDTH),
conv_std_logic_vector(23245,AMPL_WIDTH),
conv_std_logic_vector(23247,AMPL_WIDTH),
conv_std_logic_vector(23250,AMPL_WIDTH),
conv_std_logic_vector(23252,AMPL_WIDTH),
conv_std_logic_vector(23254,AMPL_WIDTH),
conv_std_logic_vector(23256,AMPL_WIDTH),
conv_std_logic_vector(23258,AMPL_WIDTH),
conv_std_logic_vector(23261,AMPL_WIDTH),
conv_std_logic_vector(23263,AMPL_WIDTH),
conv_std_logic_vector(23265,AMPL_WIDTH),
conv_std_logic_vector(23267,AMPL_WIDTH),
conv_std_logic_vector(23270,AMPL_WIDTH),
conv_std_logic_vector(23272,AMPL_WIDTH),
conv_std_logic_vector(23274,AMPL_WIDTH),
conv_std_logic_vector(23276,AMPL_WIDTH),
conv_std_logic_vector(23278,AMPL_WIDTH),
conv_std_logic_vector(23281,AMPL_WIDTH),
conv_std_logic_vector(23283,AMPL_WIDTH),
conv_std_logic_vector(23285,AMPL_WIDTH),
conv_std_logic_vector(23287,AMPL_WIDTH),
conv_std_logic_vector(23289,AMPL_WIDTH),
conv_std_logic_vector(23292,AMPL_WIDTH),
conv_std_logic_vector(23294,AMPL_WIDTH),
conv_std_logic_vector(23296,AMPL_WIDTH),
conv_std_logic_vector(23298,AMPL_WIDTH),
conv_std_logic_vector(23300,AMPL_WIDTH),
conv_std_logic_vector(23303,AMPL_WIDTH),
conv_std_logic_vector(23305,AMPL_WIDTH),
conv_std_logic_vector(23307,AMPL_WIDTH),
conv_std_logic_vector(23309,AMPL_WIDTH),
conv_std_logic_vector(23311,AMPL_WIDTH),
conv_std_logic_vector(23314,AMPL_WIDTH),
conv_std_logic_vector(23316,AMPL_WIDTH),
conv_std_logic_vector(23318,AMPL_WIDTH),
conv_std_logic_vector(23320,AMPL_WIDTH),
conv_std_logic_vector(23323,AMPL_WIDTH),
conv_std_logic_vector(23325,AMPL_WIDTH),
conv_std_logic_vector(23327,AMPL_WIDTH),
conv_std_logic_vector(23329,AMPL_WIDTH),
conv_std_logic_vector(23331,AMPL_WIDTH),
conv_std_logic_vector(23334,AMPL_WIDTH),
conv_std_logic_vector(23336,AMPL_WIDTH),
conv_std_logic_vector(23338,AMPL_WIDTH),
conv_std_logic_vector(23340,AMPL_WIDTH),
conv_std_logic_vector(23342,AMPL_WIDTH),
conv_std_logic_vector(23345,AMPL_WIDTH),
conv_std_logic_vector(23347,AMPL_WIDTH),
conv_std_logic_vector(23349,AMPL_WIDTH),
conv_std_logic_vector(23351,AMPL_WIDTH),
conv_std_logic_vector(23353,AMPL_WIDTH),
conv_std_logic_vector(23356,AMPL_WIDTH),
conv_std_logic_vector(23358,AMPL_WIDTH),
conv_std_logic_vector(23360,AMPL_WIDTH),
conv_std_logic_vector(23362,AMPL_WIDTH),
conv_std_logic_vector(23364,AMPL_WIDTH),
conv_std_logic_vector(23367,AMPL_WIDTH),
conv_std_logic_vector(23369,AMPL_WIDTH),
conv_std_logic_vector(23371,AMPL_WIDTH),
conv_std_logic_vector(23373,AMPL_WIDTH),
conv_std_logic_vector(23375,AMPL_WIDTH),
conv_std_logic_vector(23378,AMPL_WIDTH),
conv_std_logic_vector(23380,AMPL_WIDTH),
conv_std_logic_vector(23382,AMPL_WIDTH),
conv_std_logic_vector(23384,AMPL_WIDTH),
conv_std_logic_vector(23386,AMPL_WIDTH),
conv_std_logic_vector(23389,AMPL_WIDTH),
conv_std_logic_vector(23391,AMPL_WIDTH),
conv_std_logic_vector(23393,AMPL_WIDTH),
conv_std_logic_vector(23395,AMPL_WIDTH),
conv_std_logic_vector(23397,AMPL_WIDTH),
conv_std_logic_vector(23400,AMPL_WIDTH),
conv_std_logic_vector(23402,AMPL_WIDTH),
conv_std_logic_vector(23404,AMPL_WIDTH),
conv_std_logic_vector(23406,AMPL_WIDTH),
conv_std_logic_vector(23408,AMPL_WIDTH),
conv_std_logic_vector(23411,AMPL_WIDTH),
conv_std_logic_vector(23413,AMPL_WIDTH),
conv_std_logic_vector(23415,AMPL_WIDTH),
conv_std_logic_vector(23417,AMPL_WIDTH),
conv_std_logic_vector(23419,AMPL_WIDTH),
conv_std_logic_vector(23422,AMPL_WIDTH),
conv_std_logic_vector(23424,AMPL_WIDTH),
conv_std_logic_vector(23426,AMPL_WIDTH),
conv_std_logic_vector(23428,AMPL_WIDTH),
conv_std_logic_vector(23430,AMPL_WIDTH),
conv_std_logic_vector(23433,AMPL_WIDTH),
conv_std_logic_vector(23435,AMPL_WIDTH),
conv_std_logic_vector(23437,AMPL_WIDTH),
conv_std_logic_vector(23439,AMPL_WIDTH),
conv_std_logic_vector(23441,AMPL_WIDTH),
conv_std_logic_vector(23444,AMPL_WIDTH),
conv_std_logic_vector(23446,AMPL_WIDTH),
conv_std_logic_vector(23448,AMPL_WIDTH),
conv_std_logic_vector(23450,AMPL_WIDTH),
conv_std_logic_vector(23452,AMPL_WIDTH),
conv_std_logic_vector(23455,AMPL_WIDTH),
conv_std_logic_vector(23457,AMPL_WIDTH),
conv_std_logic_vector(23459,AMPL_WIDTH),
conv_std_logic_vector(23461,AMPL_WIDTH),
conv_std_logic_vector(23463,AMPL_WIDTH),
conv_std_logic_vector(23466,AMPL_WIDTH),
conv_std_logic_vector(23468,AMPL_WIDTH),
conv_std_logic_vector(23470,AMPL_WIDTH),
conv_std_logic_vector(23472,AMPL_WIDTH),
conv_std_logic_vector(23474,AMPL_WIDTH),
conv_std_logic_vector(23476,AMPL_WIDTH),
conv_std_logic_vector(23479,AMPL_WIDTH),
conv_std_logic_vector(23481,AMPL_WIDTH),
conv_std_logic_vector(23483,AMPL_WIDTH),
conv_std_logic_vector(23485,AMPL_WIDTH),
conv_std_logic_vector(23487,AMPL_WIDTH),
conv_std_logic_vector(23490,AMPL_WIDTH),
conv_std_logic_vector(23492,AMPL_WIDTH),
conv_std_logic_vector(23494,AMPL_WIDTH),
conv_std_logic_vector(23496,AMPL_WIDTH),
conv_std_logic_vector(23498,AMPL_WIDTH),
conv_std_logic_vector(23501,AMPL_WIDTH),
conv_std_logic_vector(23503,AMPL_WIDTH),
conv_std_logic_vector(23505,AMPL_WIDTH),
conv_std_logic_vector(23507,AMPL_WIDTH),
conv_std_logic_vector(23509,AMPL_WIDTH),
conv_std_logic_vector(23512,AMPL_WIDTH),
conv_std_logic_vector(23514,AMPL_WIDTH),
conv_std_logic_vector(23516,AMPL_WIDTH),
conv_std_logic_vector(23518,AMPL_WIDTH),
conv_std_logic_vector(23520,AMPL_WIDTH),
conv_std_logic_vector(23522,AMPL_WIDTH),
conv_std_logic_vector(23525,AMPL_WIDTH),
conv_std_logic_vector(23527,AMPL_WIDTH),
conv_std_logic_vector(23529,AMPL_WIDTH),
conv_std_logic_vector(23531,AMPL_WIDTH),
conv_std_logic_vector(23533,AMPL_WIDTH),
conv_std_logic_vector(23536,AMPL_WIDTH),
conv_std_logic_vector(23538,AMPL_WIDTH),
conv_std_logic_vector(23540,AMPL_WIDTH),
conv_std_logic_vector(23542,AMPL_WIDTH),
conv_std_logic_vector(23544,AMPL_WIDTH),
conv_std_logic_vector(23546,AMPL_WIDTH),
conv_std_logic_vector(23549,AMPL_WIDTH),
conv_std_logic_vector(23551,AMPL_WIDTH),
conv_std_logic_vector(23553,AMPL_WIDTH),
conv_std_logic_vector(23555,AMPL_WIDTH),
conv_std_logic_vector(23557,AMPL_WIDTH),
conv_std_logic_vector(23560,AMPL_WIDTH),
conv_std_logic_vector(23562,AMPL_WIDTH),
conv_std_logic_vector(23564,AMPL_WIDTH),
conv_std_logic_vector(23566,AMPL_WIDTH),
conv_std_logic_vector(23568,AMPL_WIDTH),
conv_std_logic_vector(23571,AMPL_WIDTH),
conv_std_logic_vector(23573,AMPL_WIDTH),
conv_std_logic_vector(23575,AMPL_WIDTH),
conv_std_logic_vector(23577,AMPL_WIDTH),
conv_std_logic_vector(23579,AMPL_WIDTH),
conv_std_logic_vector(23581,AMPL_WIDTH),
conv_std_logic_vector(23584,AMPL_WIDTH),
conv_std_logic_vector(23586,AMPL_WIDTH),
conv_std_logic_vector(23588,AMPL_WIDTH),
conv_std_logic_vector(23590,AMPL_WIDTH),
conv_std_logic_vector(23592,AMPL_WIDTH),
conv_std_logic_vector(23595,AMPL_WIDTH),
conv_std_logic_vector(23597,AMPL_WIDTH),
conv_std_logic_vector(23599,AMPL_WIDTH),
conv_std_logic_vector(23601,AMPL_WIDTH),
conv_std_logic_vector(23603,AMPL_WIDTH),
conv_std_logic_vector(23605,AMPL_WIDTH),
conv_std_logic_vector(23608,AMPL_WIDTH),
conv_std_logic_vector(23610,AMPL_WIDTH),
conv_std_logic_vector(23612,AMPL_WIDTH),
conv_std_logic_vector(23614,AMPL_WIDTH),
conv_std_logic_vector(23616,AMPL_WIDTH),
conv_std_logic_vector(23618,AMPL_WIDTH),
conv_std_logic_vector(23621,AMPL_WIDTH),
conv_std_logic_vector(23623,AMPL_WIDTH),
conv_std_logic_vector(23625,AMPL_WIDTH),
conv_std_logic_vector(23627,AMPL_WIDTH),
conv_std_logic_vector(23629,AMPL_WIDTH),
conv_std_logic_vector(23632,AMPL_WIDTH),
conv_std_logic_vector(23634,AMPL_WIDTH),
conv_std_logic_vector(23636,AMPL_WIDTH),
conv_std_logic_vector(23638,AMPL_WIDTH),
conv_std_logic_vector(23640,AMPL_WIDTH),
conv_std_logic_vector(23642,AMPL_WIDTH),
conv_std_logic_vector(23645,AMPL_WIDTH),
conv_std_logic_vector(23647,AMPL_WIDTH),
conv_std_logic_vector(23649,AMPL_WIDTH),
conv_std_logic_vector(23651,AMPL_WIDTH),
conv_std_logic_vector(23653,AMPL_WIDTH),
conv_std_logic_vector(23655,AMPL_WIDTH),
conv_std_logic_vector(23658,AMPL_WIDTH),
conv_std_logic_vector(23660,AMPL_WIDTH),
conv_std_logic_vector(23662,AMPL_WIDTH),
conv_std_logic_vector(23664,AMPL_WIDTH),
conv_std_logic_vector(23666,AMPL_WIDTH),
conv_std_logic_vector(23668,AMPL_WIDTH),
conv_std_logic_vector(23671,AMPL_WIDTH),
conv_std_logic_vector(23673,AMPL_WIDTH),
conv_std_logic_vector(23675,AMPL_WIDTH),
conv_std_logic_vector(23677,AMPL_WIDTH),
conv_std_logic_vector(23679,AMPL_WIDTH),
conv_std_logic_vector(23682,AMPL_WIDTH),
conv_std_logic_vector(23684,AMPL_WIDTH),
conv_std_logic_vector(23686,AMPL_WIDTH),
conv_std_logic_vector(23688,AMPL_WIDTH),
conv_std_logic_vector(23690,AMPL_WIDTH),
conv_std_logic_vector(23692,AMPL_WIDTH),
conv_std_logic_vector(23695,AMPL_WIDTH),
conv_std_logic_vector(23697,AMPL_WIDTH),
conv_std_logic_vector(23699,AMPL_WIDTH),
conv_std_logic_vector(23701,AMPL_WIDTH),
conv_std_logic_vector(23703,AMPL_WIDTH),
conv_std_logic_vector(23705,AMPL_WIDTH),
conv_std_logic_vector(23708,AMPL_WIDTH),
conv_std_logic_vector(23710,AMPL_WIDTH),
conv_std_logic_vector(23712,AMPL_WIDTH),
conv_std_logic_vector(23714,AMPL_WIDTH),
conv_std_logic_vector(23716,AMPL_WIDTH),
conv_std_logic_vector(23718,AMPL_WIDTH),
conv_std_logic_vector(23721,AMPL_WIDTH),
conv_std_logic_vector(23723,AMPL_WIDTH),
conv_std_logic_vector(23725,AMPL_WIDTH),
conv_std_logic_vector(23727,AMPL_WIDTH),
conv_std_logic_vector(23729,AMPL_WIDTH),
conv_std_logic_vector(23731,AMPL_WIDTH),
conv_std_logic_vector(23734,AMPL_WIDTH),
conv_std_logic_vector(23736,AMPL_WIDTH),
conv_std_logic_vector(23738,AMPL_WIDTH),
conv_std_logic_vector(23740,AMPL_WIDTH),
conv_std_logic_vector(23742,AMPL_WIDTH),
conv_std_logic_vector(23744,AMPL_WIDTH),
conv_std_logic_vector(23747,AMPL_WIDTH),
conv_std_logic_vector(23749,AMPL_WIDTH),
conv_std_logic_vector(23751,AMPL_WIDTH),
conv_std_logic_vector(23753,AMPL_WIDTH),
conv_std_logic_vector(23755,AMPL_WIDTH),
conv_std_logic_vector(23757,AMPL_WIDTH),
conv_std_logic_vector(23760,AMPL_WIDTH),
conv_std_logic_vector(23762,AMPL_WIDTH),
conv_std_logic_vector(23764,AMPL_WIDTH),
conv_std_logic_vector(23766,AMPL_WIDTH),
conv_std_logic_vector(23768,AMPL_WIDTH),
conv_std_logic_vector(23770,AMPL_WIDTH),
conv_std_logic_vector(23773,AMPL_WIDTH),
conv_std_logic_vector(23775,AMPL_WIDTH),
conv_std_logic_vector(23777,AMPL_WIDTH),
conv_std_logic_vector(23779,AMPL_WIDTH),
conv_std_logic_vector(23781,AMPL_WIDTH),
conv_std_logic_vector(23783,AMPL_WIDTH),
conv_std_logic_vector(23785,AMPL_WIDTH),
conv_std_logic_vector(23788,AMPL_WIDTH),
conv_std_logic_vector(23790,AMPL_WIDTH),
conv_std_logic_vector(23792,AMPL_WIDTH),
conv_std_logic_vector(23794,AMPL_WIDTH),
conv_std_logic_vector(23796,AMPL_WIDTH),
conv_std_logic_vector(23798,AMPL_WIDTH),
conv_std_logic_vector(23801,AMPL_WIDTH),
conv_std_logic_vector(23803,AMPL_WIDTH),
conv_std_logic_vector(23805,AMPL_WIDTH),
conv_std_logic_vector(23807,AMPL_WIDTH),
conv_std_logic_vector(23809,AMPL_WIDTH),
conv_std_logic_vector(23811,AMPL_WIDTH),
conv_std_logic_vector(23814,AMPL_WIDTH),
conv_std_logic_vector(23816,AMPL_WIDTH),
conv_std_logic_vector(23818,AMPL_WIDTH),
conv_std_logic_vector(23820,AMPL_WIDTH),
conv_std_logic_vector(23822,AMPL_WIDTH),
conv_std_logic_vector(23824,AMPL_WIDTH),
conv_std_logic_vector(23827,AMPL_WIDTH),
conv_std_logic_vector(23829,AMPL_WIDTH),
conv_std_logic_vector(23831,AMPL_WIDTH),
conv_std_logic_vector(23833,AMPL_WIDTH),
conv_std_logic_vector(23835,AMPL_WIDTH),
conv_std_logic_vector(23837,AMPL_WIDTH),
conv_std_logic_vector(23839,AMPL_WIDTH),
conv_std_logic_vector(23842,AMPL_WIDTH),
conv_std_logic_vector(23844,AMPL_WIDTH),
conv_std_logic_vector(23846,AMPL_WIDTH),
conv_std_logic_vector(23848,AMPL_WIDTH),
conv_std_logic_vector(23850,AMPL_WIDTH),
conv_std_logic_vector(23852,AMPL_WIDTH),
conv_std_logic_vector(23855,AMPL_WIDTH),
conv_std_logic_vector(23857,AMPL_WIDTH),
conv_std_logic_vector(23859,AMPL_WIDTH),
conv_std_logic_vector(23861,AMPL_WIDTH),
conv_std_logic_vector(23863,AMPL_WIDTH),
conv_std_logic_vector(23865,AMPL_WIDTH),
conv_std_logic_vector(23867,AMPL_WIDTH),
conv_std_logic_vector(23870,AMPL_WIDTH),
conv_std_logic_vector(23872,AMPL_WIDTH),
conv_std_logic_vector(23874,AMPL_WIDTH),
conv_std_logic_vector(23876,AMPL_WIDTH),
conv_std_logic_vector(23878,AMPL_WIDTH),
conv_std_logic_vector(23880,AMPL_WIDTH),
conv_std_logic_vector(23883,AMPL_WIDTH),
conv_std_logic_vector(23885,AMPL_WIDTH),
conv_std_logic_vector(23887,AMPL_WIDTH),
conv_std_logic_vector(23889,AMPL_WIDTH),
conv_std_logic_vector(23891,AMPL_WIDTH),
conv_std_logic_vector(23893,AMPL_WIDTH),
conv_std_logic_vector(23895,AMPL_WIDTH),
conv_std_logic_vector(23898,AMPL_WIDTH),
conv_std_logic_vector(23900,AMPL_WIDTH),
conv_std_logic_vector(23902,AMPL_WIDTH),
conv_std_logic_vector(23904,AMPL_WIDTH),
conv_std_logic_vector(23906,AMPL_WIDTH),
conv_std_logic_vector(23908,AMPL_WIDTH),
conv_std_logic_vector(23910,AMPL_WIDTH),
conv_std_logic_vector(23913,AMPL_WIDTH),
conv_std_logic_vector(23915,AMPL_WIDTH),
conv_std_logic_vector(23917,AMPL_WIDTH),
conv_std_logic_vector(23919,AMPL_WIDTH),
conv_std_logic_vector(23921,AMPL_WIDTH),
conv_std_logic_vector(23923,AMPL_WIDTH),
conv_std_logic_vector(23925,AMPL_WIDTH),
conv_std_logic_vector(23928,AMPL_WIDTH),
conv_std_logic_vector(23930,AMPL_WIDTH),
conv_std_logic_vector(23932,AMPL_WIDTH),
conv_std_logic_vector(23934,AMPL_WIDTH),
conv_std_logic_vector(23936,AMPL_WIDTH),
conv_std_logic_vector(23938,AMPL_WIDTH),
conv_std_logic_vector(23940,AMPL_WIDTH),
conv_std_logic_vector(23943,AMPL_WIDTH),
conv_std_logic_vector(23945,AMPL_WIDTH),
conv_std_logic_vector(23947,AMPL_WIDTH),
conv_std_logic_vector(23949,AMPL_WIDTH),
conv_std_logic_vector(23951,AMPL_WIDTH),
conv_std_logic_vector(23953,AMPL_WIDTH),
conv_std_logic_vector(23956,AMPL_WIDTH),
conv_std_logic_vector(23958,AMPL_WIDTH),
conv_std_logic_vector(23960,AMPL_WIDTH),
conv_std_logic_vector(23962,AMPL_WIDTH),
conv_std_logic_vector(23964,AMPL_WIDTH),
conv_std_logic_vector(23966,AMPL_WIDTH),
conv_std_logic_vector(23968,AMPL_WIDTH),
conv_std_logic_vector(23971,AMPL_WIDTH),
conv_std_logic_vector(23973,AMPL_WIDTH),
conv_std_logic_vector(23975,AMPL_WIDTH),
conv_std_logic_vector(23977,AMPL_WIDTH),
conv_std_logic_vector(23979,AMPL_WIDTH),
conv_std_logic_vector(23981,AMPL_WIDTH),
conv_std_logic_vector(23983,AMPL_WIDTH),
conv_std_logic_vector(23985,AMPL_WIDTH),
conv_std_logic_vector(23988,AMPL_WIDTH),
conv_std_logic_vector(23990,AMPL_WIDTH),
conv_std_logic_vector(23992,AMPL_WIDTH),
conv_std_logic_vector(23994,AMPL_WIDTH),
conv_std_logic_vector(23996,AMPL_WIDTH),
conv_std_logic_vector(23998,AMPL_WIDTH),
conv_std_logic_vector(24000,AMPL_WIDTH),
conv_std_logic_vector(24003,AMPL_WIDTH),
conv_std_logic_vector(24005,AMPL_WIDTH),
conv_std_logic_vector(24007,AMPL_WIDTH),
conv_std_logic_vector(24009,AMPL_WIDTH),
conv_std_logic_vector(24011,AMPL_WIDTH),
conv_std_logic_vector(24013,AMPL_WIDTH),
conv_std_logic_vector(24015,AMPL_WIDTH),
conv_std_logic_vector(24018,AMPL_WIDTH),
conv_std_logic_vector(24020,AMPL_WIDTH),
conv_std_logic_vector(24022,AMPL_WIDTH),
conv_std_logic_vector(24024,AMPL_WIDTH),
conv_std_logic_vector(24026,AMPL_WIDTH),
conv_std_logic_vector(24028,AMPL_WIDTH),
conv_std_logic_vector(24030,AMPL_WIDTH),
conv_std_logic_vector(24033,AMPL_WIDTH),
conv_std_logic_vector(24035,AMPL_WIDTH),
conv_std_logic_vector(24037,AMPL_WIDTH),
conv_std_logic_vector(24039,AMPL_WIDTH),
conv_std_logic_vector(24041,AMPL_WIDTH),
conv_std_logic_vector(24043,AMPL_WIDTH),
conv_std_logic_vector(24045,AMPL_WIDTH),
conv_std_logic_vector(24047,AMPL_WIDTH),
conv_std_logic_vector(24050,AMPL_WIDTH),
conv_std_logic_vector(24052,AMPL_WIDTH),
conv_std_logic_vector(24054,AMPL_WIDTH),
conv_std_logic_vector(24056,AMPL_WIDTH),
conv_std_logic_vector(24058,AMPL_WIDTH),
conv_std_logic_vector(24060,AMPL_WIDTH),
conv_std_logic_vector(24062,AMPL_WIDTH),
conv_std_logic_vector(24065,AMPL_WIDTH),
conv_std_logic_vector(24067,AMPL_WIDTH),
conv_std_logic_vector(24069,AMPL_WIDTH),
conv_std_logic_vector(24071,AMPL_WIDTH),
conv_std_logic_vector(24073,AMPL_WIDTH),
conv_std_logic_vector(24075,AMPL_WIDTH),
conv_std_logic_vector(24077,AMPL_WIDTH),
conv_std_logic_vector(24079,AMPL_WIDTH),
conv_std_logic_vector(24082,AMPL_WIDTH),
conv_std_logic_vector(24084,AMPL_WIDTH),
conv_std_logic_vector(24086,AMPL_WIDTH),
conv_std_logic_vector(24088,AMPL_WIDTH),
conv_std_logic_vector(24090,AMPL_WIDTH),
conv_std_logic_vector(24092,AMPL_WIDTH),
conv_std_logic_vector(24094,AMPL_WIDTH),
conv_std_logic_vector(24096,AMPL_WIDTH),
conv_std_logic_vector(24099,AMPL_WIDTH),
conv_std_logic_vector(24101,AMPL_WIDTH),
conv_std_logic_vector(24103,AMPL_WIDTH),
conv_std_logic_vector(24105,AMPL_WIDTH),
conv_std_logic_vector(24107,AMPL_WIDTH),
conv_std_logic_vector(24109,AMPL_WIDTH),
conv_std_logic_vector(24111,AMPL_WIDTH),
conv_std_logic_vector(24114,AMPL_WIDTH),
conv_std_logic_vector(24116,AMPL_WIDTH),
conv_std_logic_vector(24118,AMPL_WIDTH),
conv_std_logic_vector(24120,AMPL_WIDTH),
conv_std_logic_vector(24122,AMPL_WIDTH),
conv_std_logic_vector(24124,AMPL_WIDTH),
conv_std_logic_vector(24126,AMPL_WIDTH),
conv_std_logic_vector(24128,AMPL_WIDTH),
conv_std_logic_vector(24131,AMPL_WIDTH),
conv_std_logic_vector(24133,AMPL_WIDTH),
conv_std_logic_vector(24135,AMPL_WIDTH),
conv_std_logic_vector(24137,AMPL_WIDTH),
conv_std_logic_vector(24139,AMPL_WIDTH),
conv_std_logic_vector(24141,AMPL_WIDTH),
conv_std_logic_vector(24143,AMPL_WIDTH),
conv_std_logic_vector(24145,AMPL_WIDTH),
conv_std_logic_vector(24148,AMPL_WIDTH),
conv_std_logic_vector(24150,AMPL_WIDTH),
conv_std_logic_vector(24152,AMPL_WIDTH),
conv_std_logic_vector(24154,AMPL_WIDTH),
conv_std_logic_vector(24156,AMPL_WIDTH),
conv_std_logic_vector(24158,AMPL_WIDTH),
conv_std_logic_vector(24160,AMPL_WIDTH),
conv_std_logic_vector(24162,AMPL_WIDTH),
conv_std_logic_vector(24164,AMPL_WIDTH),
conv_std_logic_vector(24167,AMPL_WIDTH),
conv_std_logic_vector(24169,AMPL_WIDTH),
conv_std_logic_vector(24171,AMPL_WIDTH),
conv_std_logic_vector(24173,AMPL_WIDTH),
conv_std_logic_vector(24175,AMPL_WIDTH),
conv_std_logic_vector(24177,AMPL_WIDTH),
conv_std_logic_vector(24179,AMPL_WIDTH),
conv_std_logic_vector(24181,AMPL_WIDTH),
conv_std_logic_vector(24184,AMPL_WIDTH),
conv_std_logic_vector(24186,AMPL_WIDTH),
conv_std_logic_vector(24188,AMPL_WIDTH),
conv_std_logic_vector(24190,AMPL_WIDTH),
conv_std_logic_vector(24192,AMPL_WIDTH),
conv_std_logic_vector(24194,AMPL_WIDTH),
conv_std_logic_vector(24196,AMPL_WIDTH),
conv_std_logic_vector(24198,AMPL_WIDTH),
conv_std_logic_vector(24201,AMPL_WIDTH),
conv_std_logic_vector(24203,AMPL_WIDTH),
conv_std_logic_vector(24205,AMPL_WIDTH),
conv_std_logic_vector(24207,AMPL_WIDTH),
conv_std_logic_vector(24209,AMPL_WIDTH),
conv_std_logic_vector(24211,AMPL_WIDTH),
conv_std_logic_vector(24213,AMPL_WIDTH),
conv_std_logic_vector(24215,AMPL_WIDTH),
conv_std_logic_vector(24217,AMPL_WIDTH),
conv_std_logic_vector(24220,AMPL_WIDTH),
conv_std_logic_vector(24222,AMPL_WIDTH),
conv_std_logic_vector(24224,AMPL_WIDTH),
conv_std_logic_vector(24226,AMPL_WIDTH),
conv_std_logic_vector(24228,AMPL_WIDTH),
conv_std_logic_vector(24230,AMPL_WIDTH),
conv_std_logic_vector(24232,AMPL_WIDTH),
conv_std_logic_vector(24234,AMPL_WIDTH),
conv_std_logic_vector(24237,AMPL_WIDTH),
conv_std_logic_vector(24239,AMPL_WIDTH),
conv_std_logic_vector(24241,AMPL_WIDTH),
conv_std_logic_vector(24243,AMPL_WIDTH),
conv_std_logic_vector(24245,AMPL_WIDTH),
conv_std_logic_vector(24247,AMPL_WIDTH),
conv_std_logic_vector(24249,AMPL_WIDTH),
conv_std_logic_vector(24251,AMPL_WIDTH),
conv_std_logic_vector(24253,AMPL_WIDTH),
conv_std_logic_vector(24256,AMPL_WIDTH),
conv_std_logic_vector(24258,AMPL_WIDTH),
conv_std_logic_vector(24260,AMPL_WIDTH),
conv_std_logic_vector(24262,AMPL_WIDTH),
conv_std_logic_vector(24264,AMPL_WIDTH),
conv_std_logic_vector(24266,AMPL_WIDTH),
conv_std_logic_vector(24268,AMPL_WIDTH),
conv_std_logic_vector(24270,AMPL_WIDTH),
conv_std_logic_vector(24272,AMPL_WIDTH),
conv_std_logic_vector(24275,AMPL_WIDTH),
conv_std_logic_vector(24277,AMPL_WIDTH),
conv_std_logic_vector(24279,AMPL_WIDTH),
conv_std_logic_vector(24281,AMPL_WIDTH),
conv_std_logic_vector(24283,AMPL_WIDTH),
conv_std_logic_vector(24285,AMPL_WIDTH),
conv_std_logic_vector(24287,AMPL_WIDTH),
conv_std_logic_vector(24289,AMPL_WIDTH),
conv_std_logic_vector(24291,AMPL_WIDTH),
conv_std_logic_vector(24294,AMPL_WIDTH),
conv_std_logic_vector(24296,AMPL_WIDTH),
conv_std_logic_vector(24298,AMPL_WIDTH),
conv_std_logic_vector(24300,AMPL_WIDTH),
conv_std_logic_vector(24302,AMPL_WIDTH),
conv_std_logic_vector(24304,AMPL_WIDTH),
conv_std_logic_vector(24306,AMPL_WIDTH),
conv_std_logic_vector(24308,AMPL_WIDTH),
conv_std_logic_vector(24310,AMPL_WIDTH),
conv_std_logic_vector(24312,AMPL_WIDTH),
conv_std_logic_vector(24315,AMPL_WIDTH),
conv_std_logic_vector(24317,AMPL_WIDTH),
conv_std_logic_vector(24319,AMPL_WIDTH),
conv_std_logic_vector(24321,AMPL_WIDTH),
conv_std_logic_vector(24323,AMPL_WIDTH),
conv_std_logic_vector(24325,AMPL_WIDTH),
conv_std_logic_vector(24327,AMPL_WIDTH),
conv_std_logic_vector(24329,AMPL_WIDTH),
conv_std_logic_vector(24331,AMPL_WIDTH),
conv_std_logic_vector(24334,AMPL_WIDTH),
conv_std_logic_vector(24336,AMPL_WIDTH),
conv_std_logic_vector(24338,AMPL_WIDTH),
conv_std_logic_vector(24340,AMPL_WIDTH),
conv_std_logic_vector(24342,AMPL_WIDTH),
conv_std_logic_vector(24344,AMPL_WIDTH),
conv_std_logic_vector(24346,AMPL_WIDTH),
conv_std_logic_vector(24348,AMPL_WIDTH),
conv_std_logic_vector(24350,AMPL_WIDTH),
conv_std_logic_vector(24352,AMPL_WIDTH),
conv_std_logic_vector(24355,AMPL_WIDTH),
conv_std_logic_vector(24357,AMPL_WIDTH),
conv_std_logic_vector(24359,AMPL_WIDTH),
conv_std_logic_vector(24361,AMPL_WIDTH),
conv_std_logic_vector(24363,AMPL_WIDTH),
conv_std_logic_vector(24365,AMPL_WIDTH),
conv_std_logic_vector(24367,AMPL_WIDTH),
conv_std_logic_vector(24369,AMPL_WIDTH),
conv_std_logic_vector(24371,AMPL_WIDTH),
conv_std_logic_vector(24373,AMPL_WIDTH),
conv_std_logic_vector(24376,AMPL_WIDTH),
conv_std_logic_vector(24378,AMPL_WIDTH),
conv_std_logic_vector(24380,AMPL_WIDTH),
conv_std_logic_vector(24382,AMPL_WIDTH),
conv_std_logic_vector(24384,AMPL_WIDTH),
conv_std_logic_vector(24386,AMPL_WIDTH),
conv_std_logic_vector(24388,AMPL_WIDTH),
conv_std_logic_vector(24390,AMPL_WIDTH),
conv_std_logic_vector(24392,AMPL_WIDTH),
conv_std_logic_vector(24394,AMPL_WIDTH),
conv_std_logic_vector(24397,AMPL_WIDTH),
conv_std_logic_vector(24399,AMPL_WIDTH),
conv_std_logic_vector(24401,AMPL_WIDTH),
conv_std_logic_vector(24403,AMPL_WIDTH),
conv_std_logic_vector(24405,AMPL_WIDTH),
conv_std_logic_vector(24407,AMPL_WIDTH),
conv_std_logic_vector(24409,AMPL_WIDTH),
conv_std_logic_vector(24411,AMPL_WIDTH),
conv_std_logic_vector(24413,AMPL_WIDTH),
conv_std_logic_vector(24415,AMPL_WIDTH),
conv_std_logic_vector(24417,AMPL_WIDTH),
conv_std_logic_vector(24420,AMPL_WIDTH),
conv_std_logic_vector(24422,AMPL_WIDTH),
conv_std_logic_vector(24424,AMPL_WIDTH),
conv_std_logic_vector(24426,AMPL_WIDTH),
conv_std_logic_vector(24428,AMPL_WIDTH),
conv_std_logic_vector(24430,AMPL_WIDTH),
conv_std_logic_vector(24432,AMPL_WIDTH),
conv_std_logic_vector(24434,AMPL_WIDTH),
conv_std_logic_vector(24436,AMPL_WIDTH),
conv_std_logic_vector(24438,AMPL_WIDTH),
conv_std_logic_vector(24441,AMPL_WIDTH),
conv_std_logic_vector(24443,AMPL_WIDTH),
conv_std_logic_vector(24445,AMPL_WIDTH),
conv_std_logic_vector(24447,AMPL_WIDTH),
conv_std_logic_vector(24449,AMPL_WIDTH),
conv_std_logic_vector(24451,AMPL_WIDTH),
conv_std_logic_vector(24453,AMPL_WIDTH),
conv_std_logic_vector(24455,AMPL_WIDTH),
conv_std_logic_vector(24457,AMPL_WIDTH),
conv_std_logic_vector(24459,AMPL_WIDTH),
conv_std_logic_vector(24461,AMPL_WIDTH),
conv_std_logic_vector(24464,AMPL_WIDTH),
conv_std_logic_vector(24466,AMPL_WIDTH),
conv_std_logic_vector(24468,AMPL_WIDTH),
conv_std_logic_vector(24470,AMPL_WIDTH),
conv_std_logic_vector(24472,AMPL_WIDTH),
conv_std_logic_vector(24474,AMPL_WIDTH),
conv_std_logic_vector(24476,AMPL_WIDTH),
conv_std_logic_vector(24478,AMPL_WIDTH),
conv_std_logic_vector(24480,AMPL_WIDTH),
conv_std_logic_vector(24482,AMPL_WIDTH),
conv_std_logic_vector(24484,AMPL_WIDTH),
conv_std_logic_vector(24487,AMPL_WIDTH),
conv_std_logic_vector(24489,AMPL_WIDTH),
conv_std_logic_vector(24491,AMPL_WIDTH),
conv_std_logic_vector(24493,AMPL_WIDTH),
conv_std_logic_vector(24495,AMPL_WIDTH),
conv_std_logic_vector(24497,AMPL_WIDTH),
conv_std_logic_vector(24499,AMPL_WIDTH),
conv_std_logic_vector(24501,AMPL_WIDTH),
conv_std_logic_vector(24503,AMPL_WIDTH),
conv_std_logic_vector(24505,AMPL_WIDTH),
conv_std_logic_vector(24507,AMPL_WIDTH),
conv_std_logic_vector(24509,AMPL_WIDTH),
conv_std_logic_vector(24512,AMPL_WIDTH),
conv_std_logic_vector(24514,AMPL_WIDTH),
conv_std_logic_vector(24516,AMPL_WIDTH),
conv_std_logic_vector(24518,AMPL_WIDTH),
conv_std_logic_vector(24520,AMPL_WIDTH),
conv_std_logic_vector(24522,AMPL_WIDTH),
conv_std_logic_vector(24524,AMPL_WIDTH),
conv_std_logic_vector(24526,AMPL_WIDTH),
conv_std_logic_vector(24528,AMPL_WIDTH),
conv_std_logic_vector(24530,AMPL_WIDTH),
conv_std_logic_vector(24532,AMPL_WIDTH),
conv_std_logic_vector(24534,AMPL_WIDTH),
conv_std_logic_vector(24537,AMPL_WIDTH),
conv_std_logic_vector(24539,AMPL_WIDTH),
conv_std_logic_vector(24541,AMPL_WIDTH),
conv_std_logic_vector(24543,AMPL_WIDTH),
conv_std_logic_vector(24545,AMPL_WIDTH),
conv_std_logic_vector(24547,AMPL_WIDTH),
conv_std_logic_vector(24549,AMPL_WIDTH),
conv_std_logic_vector(24551,AMPL_WIDTH),
conv_std_logic_vector(24553,AMPL_WIDTH),
conv_std_logic_vector(24555,AMPL_WIDTH),
conv_std_logic_vector(24557,AMPL_WIDTH),
conv_std_logic_vector(24559,AMPL_WIDTH),
conv_std_logic_vector(24562,AMPL_WIDTH),
conv_std_logic_vector(24564,AMPL_WIDTH),
conv_std_logic_vector(24566,AMPL_WIDTH),
conv_std_logic_vector(24568,AMPL_WIDTH),
conv_std_logic_vector(24570,AMPL_WIDTH),
conv_std_logic_vector(24572,AMPL_WIDTH),
conv_std_logic_vector(24574,AMPL_WIDTH),
conv_std_logic_vector(24576,AMPL_WIDTH),
conv_std_logic_vector(24578,AMPL_WIDTH),
conv_std_logic_vector(24580,AMPL_WIDTH),
conv_std_logic_vector(24582,AMPL_WIDTH),
conv_std_logic_vector(24584,AMPL_WIDTH),
conv_std_logic_vector(24586,AMPL_WIDTH),
conv_std_logic_vector(24589,AMPL_WIDTH),
conv_std_logic_vector(24591,AMPL_WIDTH),
conv_std_logic_vector(24593,AMPL_WIDTH),
conv_std_logic_vector(24595,AMPL_WIDTH),
conv_std_logic_vector(24597,AMPL_WIDTH),
conv_std_logic_vector(24599,AMPL_WIDTH),
conv_std_logic_vector(24601,AMPL_WIDTH),
conv_std_logic_vector(24603,AMPL_WIDTH),
conv_std_logic_vector(24605,AMPL_WIDTH),
conv_std_logic_vector(24607,AMPL_WIDTH),
conv_std_logic_vector(24609,AMPL_WIDTH),
conv_std_logic_vector(24611,AMPL_WIDTH),
conv_std_logic_vector(24613,AMPL_WIDTH),
conv_std_logic_vector(24616,AMPL_WIDTH),
conv_std_logic_vector(24618,AMPL_WIDTH),
conv_std_logic_vector(24620,AMPL_WIDTH),
conv_std_logic_vector(24622,AMPL_WIDTH),
conv_std_logic_vector(24624,AMPL_WIDTH),
conv_std_logic_vector(24626,AMPL_WIDTH),
conv_std_logic_vector(24628,AMPL_WIDTH),
conv_std_logic_vector(24630,AMPL_WIDTH),
conv_std_logic_vector(24632,AMPL_WIDTH),
conv_std_logic_vector(24634,AMPL_WIDTH),
conv_std_logic_vector(24636,AMPL_WIDTH),
conv_std_logic_vector(24638,AMPL_WIDTH),
conv_std_logic_vector(24640,AMPL_WIDTH),
conv_std_logic_vector(24642,AMPL_WIDTH),
conv_std_logic_vector(24645,AMPL_WIDTH),
conv_std_logic_vector(24647,AMPL_WIDTH),
conv_std_logic_vector(24649,AMPL_WIDTH),
conv_std_logic_vector(24651,AMPL_WIDTH),
conv_std_logic_vector(24653,AMPL_WIDTH),
conv_std_logic_vector(24655,AMPL_WIDTH),
conv_std_logic_vector(24657,AMPL_WIDTH),
conv_std_logic_vector(24659,AMPL_WIDTH),
conv_std_logic_vector(24661,AMPL_WIDTH),
conv_std_logic_vector(24663,AMPL_WIDTH),
conv_std_logic_vector(24665,AMPL_WIDTH),
conv_std_logic_vector(24667,AMPL_WIDTH),
conv_std_logic_vector(24669,AMPL_WIDTH),
conv_std_logic_vector(24671,AMPL_WIDTH),
conv_std_logic_vector(24673,AMPL_WIDTH),
conv_std_logic_vector(24676,AMPL_WIDTH),
conv_std_logic_vector(24678,AMPL_WIDTH),
conv_std_logic_vector(24680,AMPL_WIDTH),
conv_std_logic_vector(24682,AMPL_WIDTH),
conv_std_logic_vector(24684,AMPL_WIDTH),
conv_std_logic_vector(24686,AMPL_WIDTH),
conv_std_logic_vector(24688,AMPL_WIDTH),
conv_std_logic_vector(24690,AMPL_WIDTH),
conv_std_logic_vector(24692,AMPL_WIDTH),
conv_std_logic_vector(24694,AMPL_WIDTH),
conv_std_logic_vector(24696,AMPL_WIDTH),
conv_std_logic_vector(24698,AMPL_WIDTH),
conv_std_logic_vector(24700,AMPL_WIDTH),
conv_std_logic_vector(24702,AMPL_WIDTH),
conv_std_logic_vector(24704,AMPL_WIDTH),
conv_std_logic_vector(24707,AMPL_WIDTH),
conv_std_logic_vector(24709,AMPL_WIDTH),
conv_std_logic_vector(24711,AMPL_WIDTH),
conv_std_logic_vector(24713,AMPL_WIDTH),
conv_std_logic_vector(24715,AMPL_WIDTH),
conv_std_logic_vector(24717,AMPL_WIDTH),
conv_std_logic_vector(24719,AMPL_WIDTH),
conv_std_logic_vector(24721,AMPL_WIDTH),
conv_std_logic_vector(24723,AMPL_WIDTH),
conv_std_logic_vector(24725,AMPL_WIDTH),
conv_std_logic_vector(24727,AMPL_WIDTH),
conv_std_logic_vector(24729,AMPL_WIDTH),
conv_std_logic_vector(24731,AMPL_WIDTH),
conv_std_logic_vector(24733,AMPL_WIDTH),
conv_std_logic_vector(24735,AMPL_WIDTH),
conv_std_logic_vector(24737,AMPL_WIDTH),
conv_std_logic_vector(24740,AMPL_WIDTH),
conv_std_logic_vector(24742,AMPL_WIDTH),
conv_std_logic_vector(24744,AMPL_WIDTH),
conv_std_logic_vector(24746,AMPL_WIDTH),
conv_std_logic_vector(24748,AMPL_WIDTH),
conv_std_logic_vector(24750,AMPL_WIDTH),
conv_std_logic_vector(24752,AMPL_WIDTH),
conv_std_logic_vector(24754,AMPL_WIDTH),
conv_std_logic_vector(24756,AMPL_WIDTH),
conv_std_logic_vector(24758,AMPL_WIDTH),
conv_std_logic_vector(24760,AMPL_WIDTH),
conv_std_logic_vector(24762,AMPL_WIDTH),
conv_std_logic_vector(24764,AMPL_WIDTH),
conv_std_logic_vector(24766,AMPL_WIDTH),
conv_std_logic_vector(24768,AMPL_WIDTH),
conv_std_logic_vector(24770,AMPL_WIDTH),
conv_std_logic_vector(24772,AMPL_WIDTH),
conv_std_logic_vector(24774,AMPL_WIDTH),
conv_std_logic_vector(24777,AMPL_WIDTH),
conv_std_logic_vector(24779,AMPL_WIDTH),
conv_std_logic_vector(24781,AMPL_WIDTH),
conv_std_logic_vector(24783,AMPL_WIDTH),
conv_std_logic_vector(24785,AMPL_WIDTH),
conv_std_logic_vector(24787,AMPL_WIDTH),
conv_std_logic_vector(24789,AMPL_WIDTH),
conv_std_logic_vector(24791,AMPL_WIDTH),
conv_std_logic_vector(24793,AMPL_WIDTH),
conv_std_logic_vector(24795,AMPL_WIDTH),
conv_std_logic_vector(24797,AMPL_WIDTH),
conv_std_logic_vector(24799,AMPL_WIDTH),
conv_std_logic_vector(24801,AMPL_WIDTH),
conv_std_logic_vector(24803,AMPL_WIDTH),
conv_std_logic_vector(24805,AMPL_WIDTH),
conv_std_logic_vector(24807,AMPL_WIDTH),
conv_std_logic_vector(24809,AMPL_WIDTH),
conv_std_logic_vector(24811,AMPL_WIDTH),
conv_std_logic_vector(24814,AMPL_WIDTH),
conv_std_logic_vector(24816,AMPL_WIDTH),
conv_std_logic_vector(24818,AMPL_WIDTH),
conv_std_logic_vector(24820,AMPL_WIDTH),
conv_std_logic_vector(24822,AMPL_WIDTH),
conv_std_logic_vector(24824,AMPL_WIDTH),
conv_std_logic_vector(24826,AMPL_WIDTH),
conv_std_logic_vector(24828,AMPL_WIDTH),
conv_std_logic_vector(24830,AMPL_WIDTH),
conv_std_logic_vector(24832,AMPL_WIDTH),
conv_std_logic_vector(24834,AMPL_WIDTH),
conv_std_logic_vector(24836,AMPL_WIDTH),
conv_std_logic_vector(24838,AMPL_WIDTH),
conv_std_logic_vector(24840,AMPL_WIDTH),
conv_std_logic_vector(24842,AMPL_WIDTH),
conv_std_logic_vector(24844,AMPL_WIDTH),
conv_std_logic_vector(24846,AMPL_WIDTH),
conv_std_logic_vector(24848,AMPL_WIDTH),
conv_std_logic_vector(24850,AMPL_WIDTH),
conv_std_logic_vector(24852,AMPL_WIDTH),
conv_std_logic_vector(24855,AMPL_WIDTH),
conv_std_logic_vector(24857,AMPL_WIDTH),
conv_std_logic_vector(24859,AMPL_WIDTH),
conv_std_logic_vector(24861,AMPL_WIDTH),
conv_std_logic_vector(24863,AMPL_WIDTH),
conv_std_logic_vector(24865,AMPL_WIDTH),
conv_std_logic_vector(24867,AMPL_WIDTH),
conv_std_logic_vector(24869,AMPL_WIDTH),
conv_std_logic_vector(24871,AMPL_WIDTH),
conv_std_logic_vector(24873,AMPL_WIDTH),
conv_std_logic_vector(24875,AMPL_WIDTH),
conv_std_logic_vector(24877,AMPL_WIDTH),
conv_std_logic_vector(24879,AMPL_WIDTH),
conv_std_logic_vector(24881,AMPL_WIDTH),
conv_std_logic_vector(24883,AMPL_WIDTH),
conv_std_logic_vector(24885,AMPL_WIDTH),
conv_std_logic_vector(24887,AMPL_WIDTH),
conv_std_logic_vector(24889,AMPL_WIDTH),
conv_std_logic_vector(24891,AMPL_WIDTH),
conv_std_logic_vector(24893,AMPL_WIDTH),
conv_std_logic_vector(24895,AMPL_WIDTH),
conv_std_logic_vector(24897,AMPL_WIDTH),
conv_std_logic_vector(24899,AMPL_WIDTH),
conv_std_logic_vector(24902,AMPL_WIDTH),
conv_std_logic_vector(24904,AMPL_WIDTH),
conv_std_logic_vector(24906,AMPL_WIDTH),
conv_std_logic_vector(24908,AMPL_WIDTH),
conv_std_logic_vector(24910,AMPL_WIDTH),
conv_std_logic_vector(24912,AMPL_WIDTH),
conv_std_logic_vector(24914,AMPL_WIDTH),
conv_std_logic_vector(24916,AMPL_WIDTH),
conv_std_logic_vector(24918,AMPL_WIDTH),
conv_std_logic_vector(24920,AMPL_WIDTH),
conv_std_logic_vector(24922,AMPL_WIDTH),
conv_std_logic_vector(24924,AMPL_WIDTH),
conv_std_logic_vector(24926,AMPL_WIDTH),
conv_std_logic_vector(24928,AMPL_WIDTH),
conv_std_logic_vector(24930,AMPL_WIDTH),
conv_std_logic_vector(24932,AMPL_WIDTH),
conv_std_logic_vector(24934,AMPL_WIDTH),
conv_std_logic_vector(24936,AMPL_WIDTH),
conv_std_logic_vector(24938,AMPL_WIDTH),
conv_std_logic_vector(24940,AMPL_WIDTH),
conv_std_logic_vector(24942,AMPL_WIDTH),
conv_std_logic_vector(24944,AMPL_WIDTH),
conv_std_logic_vector(24946,AMPL_WIDTH),
conv_std_logic_vector(24948,AMPL_WIDTH),
conv_std_logic_vector(24950,AMPL_WIDTH),
conv_std_logic_vector(24953,AMPL_WIDTH),
conv_std_logic_vector(24955,AMPL_WIDTH),
conv_std_logic_vector(24957,AMPL_WIDTH),
conv_std_logic_vector(24959,AMPL_WIDTH),
conv_std_logic_vector(24961,AMPL_WIDTH),
conv_std_logic_vector(24963,AMPL_WIDTH),
conv_std_logic_vector(24965,AMPL_WIDTH),
conv_std_logic_vector(24967,AMPL_WIDTH),
conv_std_logic_vector(24969,AMPL_WIDTH),
conv_std_logic_vector(24971,AMPL_WIDTH),
conv_std_logic_vector(24973,AMPL_WIDTH),
conv_std_logic_vector(24975,AMPL_WIDTH),
conv_std_logic_vector(24977,AMPL_WIDTH),
conv_std_logic_vector(24979,AMPL_WIDTH),
conv_std_logic_vector(24981,AMPL_WIDTH),
conv_std_logic_vector(24983,AMPL_WIDTH),
conv_std_logic_vector(24985,AMPL_WIDTH),
conv_std_logic_vector(24987,AMPL_WIDTH),
conv_std_logic_vector(24989,AMPL_WIDTH),
conv_std_logic_vector(24991,AMPL_WIDTH),
conv_std_logic_vector(24993,AMPL_WIDTH),
conv_std_logic_vector(24995,AMPL_WIDTH),
conv_std_logic_vector(24997,AMPL_WIDTH),
conv_std_logic_vector(24999,AMPL_WIDTH),
conv_std_logic_vector(25001,AMPL_WIDTH),
conv_std_logic_vector(25003,AMPL_WIDTH),
conv_std_logic_vector(25005,AMPL_WIDTH),
conv_std_logic_vector(25007,AMPL_WIDTH),
conv_std_logic_vector(25009,AMPL_WIDTH),
conv_std_logic_vector(25011,AMPL_WIDTH),
conv_std_logic_vector(25013,AMPL_WIDTH),
conv_std_logic_vector(25016,AMPL_WIDTH),
conv_std_logic_vector(25018,AMPL_WIDTH),
conv_std_logic_vector(25020,AMPL_WIDTH),
conv_std_logic_vector(25022,AMPL_WIDTH),
conv_std_logic_vector(25024,AMPL_WIDTH),
conv_std_logic_vector(25026,AMPL_WIDTH),
conv_std_logic_vector(25028,AMPL_WIDTH),
conv_std_logic_vector(25030,AMPL_WIDTH),
conv_std_logic_vector(25032,AMPL_WIDTH),
conv_std_logic_vector(25034,AMPL_WIDTH),
conv_std_logic_vector(25036,AMPL_WIDTH),
conv_std_logic_vector(25038,AMPL_WIDTH),
conv_std_logic_vector(25040,AMPL_WIDTH),
conv_std_logic_vector(25042,AMPL_WIDTH),
conv_std_logic_vector(25044,AMPL_WIDTH),
conv_std_logic_vector(25046,AMPL_WIDTH),
conv_std_logic_vector(25048,AMPL_WIDTH),
conv_std_logic_vector(25050,AMPL_WIDTH),
conv_std_logic_vector(25052,AMPL_WIDTH),
conv_std_logic_vector(25054,AMPL_WIDTH),
conv_std_logic_vector(25056,AMPL_WIDTH),
conv_std_logic_vector(25058,AMPL_WIDTH),
conv_std_logic_vector(25060,AMPL_WIDTH),
conv_std_logic_vector(25062,AMPL_WIDTH),
conv_std_logic_vector(25064,AMPL_WIDTH),
conv_std_logic_vector(25066,AMPL_WIDTH),
conv_std_logic_vector(25068,AMPL_WIDTH),
conv_std_logic_vector(25070,AMPL_WIDTH),
conv_std_logic_vector(25072,AMPL_WIDTH),
conv_std_logic_vector(25074,AMPL_WIDTH),
conv_std_logic_vector(25076,AMPL_WIDTH),
conv_std_logic_vector(25078,AMPL_WIDTH),
conv_std_logic_vector(25080,AMPL_WIDTH),
conv_std_logic_vector(25082,AMPL_WIDTH),
conv_std_logic_vector(25084,AMPL_WIDTH),
conv_std_logic_vector(25086,AMPL_WIDTH),
conv_std_logic_vector(25088,AMPL_WIDTH),
conv_std_logic_vector(25090,AMPL_WIDTH),
conv_std_logic_vector(25092,AMPL_WIDTH),
conv_std_logic_vector(25094,AMPL_WIDTH),
conv_std_logic_vector(25096,AMPL_WIDTH),
conv_std_logic_vector(25099,AMPL_WIDTH),
conv_std_logic_vector(25101,AMPL_WIDTH),
conv_std_logic_vector(25103,AMPL_WIDTH),
conv_std_logic_vector(25105,AMPL_WIDTH),
conv_std_logic_vector(25107,AMPL_WIDTH),
conv_std_logic_vector(25109,AMPL_WIDTH),
conv_std_logic_vector(25111,AMPL_WIDTH),
conv_std_logic_vector(25113,AMPL_WIDTH),
conv_std_logic_vector(25115,AMPL_WIDTH),
conv_std_logic_vector(25117,AMPL_WIDTH),
conv_std_logic_vector(25119,AMPL_WIDTH),
conv_std_logic_vector(25121,AMPL_WIDTH),
conv_std_logic_vector(25123,AMPL_WIDTH),
conv_std_logic_vector(25125,AMPL_WIDTH),
conv_std_logic_vector(25127,AMPL_WIDTH),
conv_std_logic_vector(25129,AMPL_WIDTH),
conv_std_logic_vector(25131,AMPL_WIDTH),
conv_std_logic_vector(25133,AMPL_WIDTH),
conv_std_logic_vector(25135,AMPL_WIDTH),
conv_std_logic_vector(25137,AMPL_WIDTH),
conv_std_logic_vector(25139,AMPL_WIDTH),
conv_std_logic_vector(25141,AMPL_WIDTH),
conv_std_logic_vector(25143,AMPL_WIDTH),
conv_std_logic_vector(25145,AMPL_WIDTH),
conv_std_logic_vector(25147,AMPL_WIDTH),
conv_std_logic_vector(25149,AMPL_WIDTH),
conv_std_logic_vector(25151,AMPL_WIDTH),
conv_std_logic_vector(25153,AMPL_WIDTH),
conv_std_logic_vector(25155,AMPL_WIDTH),
conv_std_logic_vector(25157,AMPL_WIDTH),
conv_std_logic_vector(25159,AMPL_WIDTH),
conv_std_logic_vector(25161,AMPL_WIDTH),
conv_std_logic_vector(25163,AMPL_WIDTH),
conv_std_logic_vector(25165,AMPL_WIDTH),
conv_std_logic_vector(25167,AMPL_WIDTH),
conv_std_logic_vector(25169,AMPL_WIDTH),
conv_std_logic_vector(25171,AMPL_WIDTH),
conv_std_logic_vector(25173,AMPL_WIDTH),
conv_std_logic_vector(25175,AMPL_WIDTH),
conv_std_logic_vector(25177,AMPL_WIDTH),
conv_std_logic_vector(25179,AMPL_WIDTH),
conv_std_logic_vector(25181,AMPL_WIDTH),
conv_std_logic_vector(25183,AMPL_WIDTH),
conv_std_logic_vector(25185,AMPL_WIDTH),
conv_std_logic_vector(25187,AMPL_WIDTH),
conv_std_logic_vector(25189,AMPL_WIDTH),
conv_std_logic_vector(25191,AMPL_WIDTH),
conv_std_logic_vector(25193,AMPL_WIDTH),
conv_std_logic_vector(25195,AMPL_WIDTH),
conv_std_logic_vector(25197,AMPL_WIDTH),
conv_std_logic_vector(25199,AMPL_WIDTH),
conv_std_logic_vector(25201,AMPL_WIDTH),
conv_std_logic_vector(25203,AMPL_WIDTH),
conv_std_logic_vector(25205,AMPL_WIDTH),
conv_std_logic_vector(25207,AMPL_WIDTH),
conv_std_logic_vector(25209,AMPL_WIDTH),
conv_std_logic_vector(25211,AMPL_WIDTH),
conv_std_logic_vector(25213,AMPL_WIDTH),
conv_std_logic_vector(25215,AMPL_WIDTH),
conv_std_logic_vector(25217,AMPL_WIDTH),
conv_std_logic_vector(25219,AMPL_WIDTH),
conv_std_logic_vector(25221,AMPL_WIDTH),
conv_std_logic_vector(25223,AMPL_WIDTH),
conv_std_logic_vector(25225,AMPL_WIDTH),
conv_std_logic_vector(25227,AMPL_WIDTH),
conv_std_logic_vector(25229,AMPL_WIDTH),
conv_std_logic_vector(25231,AMPL_WIDTH),
conv_std_logic_vector(25233,AMPL_WIDTH),
conv_std_logic_vector(25235,AMPL_WIDTH),
conv_std_logic_vector(25237,AMPL_WIDTH),
conv_std_logic_vector(25239,AMPL_WIDTH),
conv_std_logic_vector(25241,AMPL_WIDTH),
conv_std_logic_vector(25243,AMPL_WIDTH),
conv_std_logic_vector(25245,AMPL_WIDTH),
conv_std_logic_vector(25247,AMPL_WIDTH),
conv_std_logic_vector(25249,AMPL_WIDTH),
conv_std_logic_vector(25251,AMPL_WIDTH),
conv_std_logic_vector(25253,AMPL_WIDTH),
conv_std_logic_vector(25255,AMPL_WIDTH),
conv_std_logic_vector(25257,AMPL_WIDTH),
conv_std_logic_vector(25259,AMPL_WIDTH),
conv_std_logic_vector(25261,AMPL_WIDTH),
conv_std_logic_vector(25263,AMPL_WIDTH),
conv_std_logic_vector(25265,AMPL_WIDTH),
conv_std_logic_vector(25267,AMPL_WIDTH),
conv_std_logic_vector(25269,AMPL_WIDTH),
conv_std_logic_vector(25271,AMPL_WIDTH),
conv_std_logic_vector(25273,AMPL_WIDTH),
conv_std_logic_vector(25275,AMPL_WIDTH),
conv_std_logic_vector(25277,AMPL_WIDTH),
conv_std_logic_vector(25279,AMPL_WIDTH),
conv_std_logic_vector(25281,AMPL_WIDTH),
conv_std_logic_vector(25283,AMPL_WIDTH),
conv_std_logic_vector(25285,AMPL_WIDTH),
conv_std_logic_vector(25287,AMPL_WIDTH),
conv_std_logic_vector(25289,AMPL_WIDTH),
conv_std_logic_vector(25291,AMPL_WIDTH),
conv_std_logic_vector(25293,AMPL_WIDTH),
conv_std_logic_vector(25295,AMPL_WIDTH),
conv_std_logic_vector(25297,AMPL_WIDTH),
conv_std_logic_vector(25299,AMPL_WIDTH),
conv_std_logic_vector(25301,AMPL_WIDTH),
conv_std_logic_vector(25303,AMPL_WIDTH),
conv_std_logic_vector(25305,AMPL_WIDTH),
conv_std_logic_vector(25307,AMPL_WIDTH),
conv_std_logic_vector(25309,AMPL_WIDTH),
conv_std_logic_vector(25311,AMPL_WIDTH),
conv_std_logic_vector(25313,AMPL_WIDTH),
conv_std_logic_vector(25315,AMPL_WIDTH),
conv_std_logic_vector(25317,AMPL_WIDTH),
conv_std_logic_vector(25319,AMPL_WIDTH),
conv_std_logic_vector(25321,AMPL_WIDTH),
conv_std_logic_vector(25323,AMPL_WIDTH),
conv_std_logic_vector(25325,AMPL_WIDTH),
conv_std_logic_vector(25327,AMPL_WIDTH),
conv_std_logic_vector(25329,AMPL_WIDTH),
conv_std_logic_vector(25331,AMPL_WIDTH),
conv_std_logic_vector(25333,AMPL_WIDTH),
conv_std_logic_vector(25335,AMPL_WIDTH),
conv_std_logic_vector(25337,AMPL_WIDTH),
conv_std_logic_vector(25339,AMPL_WIDTH),
conv_std_logic_vector(25341,AMPL_WIDTH),
conv_std_logic_vector(25343,AMPL_WIDTH),
conv_std_logic_vector(25345,AMPL_WIDTH),
conv_std_logic_vector(25347,AMPL_WIDTH),
conv_std_logic_vector(25349,AMPL_WIDTH),
conv_std_logic_vector(25351,AMPL_WIDTH),
conv_std_logic_vector(25353,AMPL_WIDTH),
conv_std_logic_vector(25355,AMPL_WIDTH),
conv_std_logic_vector(25357,AMPL_WIDTH),
conv_std_logic_vector(25359,AMPL_WIDTH),
conv_std_logic_vector(25361,AMPL_WIDTH),
conv_std_logic_vector(25363,AMPL_WIDTH),
conv_std_logic_vector(25365,AMPL_WIDTH),
conv_std_logic_vector(25367,AMPL_WIDTH),
conv_std_logic_vector(25369,AMPL_WIDTH),
conv_std_logic_vector(25371,AMPL_WIDTH),
conv_std_logic_vector(25373,AMPL_WIDTH),
conv_std_logic_vector(25375,AMPL_WIDTH),
conv_std_logic_vector(25377,AMPL_WIDTH),
conv_std_logic_vector(25379,AMPL_WIDTH),
conv_std_logic_vector(25381,AMPL_WIDTH),
conv_std_logic_vector(25383,AMPL_WIDTH),
conv_std_logic_vector(25385,AMPL_WIDTH),
conv_std_logic_vector(25387,AMPL_WIDTH),
conv_std_logic_vector(25389,AMPL_WIDTH),
conv_std_logic_vector(25391,AMPL_WIDTH),
conv_std_logic_vector(25393,AMPL_WIDTH),
conv_std_logic_vector(25395,AMPL_WIDTH),
conv_std_logic_vector(25397,AMPL_WIDTH),
conv_std_logic_vector(25399,AMPL_WIDTH),
conv_std_logic_vector(25401,AMPL_WIDTH),
conv_std_logic_vector(25403,AMPL_WIDTH),
conv_std_logic_vector(25405,AMPL_WIDTH),
conv_std_logic_vector(25407,AMPL_WIDTH),
conv_std_logic_vector(25409,AMPL_WIDTH),
conv_std_logic_vector(25411,AMPL_WIDTH),
conv_std_logic_vector(25413,AMPL_WIDTH),
conv_std_logic_vector(25415,AMPL_WIDTH),
conv_std_logic_vector(25417,AMPL_WIDTH),
conv_std_logic_vector(25419,AMPL_WIDTH),
conv_std_logic_vector(25421,AMPL_WIDTH),
conv_std_logic_vector(25423,AMPL_WIDTH),
conv_std_logic_vector(25425,AMPL_WIDTH),
conv_std_logic_vector(25427,AMPL_WIDTH),
conv_std_logic_vector(25429,AMPL_WIDTH),
conv_std_logic_vector(25431,AMPL_WIDTH),
conv_std_logic_vector(25433,AMPL_WIDTH),
conv_std_logic_vector(25435,AMPL_WIDTH),
conv_std_logic_vector(25437,AMPL_WIDTH),
conv_std_logic_vector(25438,AMPL_WIDTH),
conv_std_logic_vector(25440,AMPL_WIDTH),
conv_std_logic_vector(25442,AMPL_WIDTH),
conv_std_logic_vector(25444,AMPL_WIDTH),
conv_std_logic_vector(25446,AMPL_WIDTH),
conv_std_logic_vector(25448,AMPL_WIDTH),
conv_std_logic_vector(25450,AMPL_WIDTH),
conv_std_logic_vector(25452,AMPL_WIDTH),
conv_std_logic_vector(25454,AMPL_WIDTH),
conv_std_logic_vector(25456,AMPL_WIDTH),
conv_std_logic_vector(25458,AMPL_WIDTH),
conv_std_logic_vector(25460,AMPL_WIDTH),
conv_std_logic_vector(25462,AMPL_WIDTH),
conv_std_logic_vector(25464,AMPL_WIDTH),
conv_std_logic_vector(25466,AMPL_WIDTH),
conv_std_logic_vector(25468,AMPL_WIDTH),
conv_std_logic_vector(25470,AMPL_WIDTH),
conv_std_logic_vector(25472,AMPL_WIDTH),
conv_std_logic_vector(25474,AMPL_WIDTH),
conv_std_logic_vector(25476,AMPL_WIDTH),
conv_std_logic_vector(25478,AMPL_WIDTH),
conv_std_logic_vector(25480,AMPL_WIDTH),
conv_std_logic_vector(25482,AMPL_WIDTH),
conv_std_logic_vector(25484,AMPL_WIDTH),
conv_std_logic_vector(25486,AMPL_WIDTH),
conv_std_logic_vector(25488,AMPL_WIDTH),
conv_std_logic_vector(25490,AMPL_WIDTH),
conv_std_logic_vector(25492,AMPL_WIDTH),
conv_std_logic_vector(25494,AMPL_WIDTH),
conv_std_logic_vector(25496,AMPL_WIDTH),
conv_std_logic_vector(25498,AMPL_WIDTH),
conv_std_logic_vector(25500,AMPL_WIDTH),
conv_std_logic_vector(25502,AMPL_WIDTH),
conv_std_logic_vector(25504,AMPL_WIDTH),
conv_std_logic_vector(25506,AMPL_WIDTH),
conv_std_logic_vector(25508,AMPL_WIDTH),
conv_std_logic_vector(25510,AMPL_WIDTH),
conv_std_logic_vector(25512,AMPL_WIDTH),
conv_std_logic_vector(25514,AMPL_WIDTH),
conv_std_logic_vector(25516,AMPL_WIDTH),
conv_std_logic_vector(25518,AMPL_WIDTH),
conv_std_logic_vector(25519,AMPL_WIDTH),
conv_std_logic_vector(25521,AMPL_WIDTH),
conv_std_logic_vector(25523,AMPL_WIDTH),
conv_std_logic_vector(25525,AMPL_WIDTH),
conv_std_logic_vector(25527,AMPL_WIDTH),
conv_std_logic_vector(25529,AMPL_WIDTH),
conv_std_logic_vector(25531,AMPL_WIDTH),
conv_std_logic_vector(25533,AMPL_WIDTH),
conv_std_logic_vector(25535,AMPL_WIDTH),
conv_std_logic_vector(25537,AMPL_WIDTH),
conv_std_logic_vector(25539,AMPL_WIDTH),
conv_std_logic_vector(25541,AMPL_WIDTH),
conv_std_logic_vector(25543,AMPL_WIDTH),
conv_std_logic_vector(25545,AMPL_WIDTH),
conv_std_logic_vector(25547,AMPL_WIDTH),
conv_std_logic_vector(25549,AMPL_WIDTH),
conv_std_logic_vector(25551,AMPL_WIDTH),
conv_std_logic_vector(25553,AMPL_WIDTH),
conv_std_logic_vector(25555,AMPL_WIDTH),
conv_std_logic_vector(25557,AMPL_WIDTH),
conv_std_logic_vector(25559,AMPL_WIDTH),
conv_std_logic_vector(25561,AMPL_WIDTH),
conv_std_logic_vector(25563,AMPL_WIDTH),
conv_std_logic_vector(25565,AMPL_WIDTH),
conv_std_logic_vector(25567,AMPL_WIDTH),
conv_std_logic_vector(25569,AMPL_WIDTH),
conv_std_logic_vector(25571,AMPL_WIDTH),
conv_std_logic_vector(25573,AMPL_WIDTH),
conv_std_logic_vector(25575,AMPL_WIDTH),
conv_std_logic_vector(25577,AMPL_WIDTH),
conv_std_logic_vector(25578,AMPL_WIDTH),
conv_std_logic_vector(25580,AMPL_WIDTH),
conv_std_logic_vector(25582,AMPL_WIDTH),
conv_std_logic_vector(25584,AMPL_WIDTH),
conv_std_logic_vector(25586,AMPL_WIDTH),
conv_std_logic_vector(25588,AMPL_WIDTH),
conv_std_logic_vector(25590,AMPL_WIDTH),
conv_std_logic_vector(25592,AMPL_WIDTH),
conv_std_logic_vector(25594,AMPL_WIDTH),
conv_std_logic_vector(25596,AMPL_WIDTH),
conv_std_logic_vector(25598,AMPL_WIDTH),
conv_std_logic_vector(25600,AMPL_WIDTH),
conv_std_logic_vector(25602,AMPL_WIDTH),
conv_std_logic_vector(25604,AMPL_WIDTH),
conv_std_logic_vector(25606,AMPL_WIDTH),
conv_std_logic_vector(25608,AMPL_WIDTH),
conv_std_logic_vector(25610,AMPL_WIDTH),
conv_std_logic_vector(25612,AMPL_WIDTH),
conv_std_logic_vector(25614,AMPL_WIDTH),
conv_std_logic_vector(25616,AMPL_WIDTH),
conv_std_logic_vector(25618,AMPL_WIDTH),
conv_std_logic_vector(25620,AMPL_WIDTH),
conv_std_logic_vector(25622,AMPL_WIDTH),
conv_std_logic_vector(25624,AMPL_WIDTH),
conv_std_logic_vector(25626,AMPL_WIDTH),
conv_std_logic_vector(25628,AMPL_WIDTH),
conv_std_logic_vector(25629,AMPL_WIDTH),
conv_std_logic_vector(25631,AMPL_WIDTH),
conv_std_logic_vector(25633,AMPL_WIDTH),
conv_std_logic_vector(25635,AMPL_WIDTH),
conv_std_logic_vector(25637,AMPL_WIDTH),
conv_std_logic_vector(25639,AMPL_WIDTH),
conv_std_logic_vector(25641,AMPL_WIDTH),
conv_std_logic_vector(25643,AMPL_WIDTH),
conv_std_logic_vector(25645,AMPL_WIDTH),
conv_std_logic_vector(25647,AMPL_WIDTH),
conv_std_logic_vector(25649,AMPL_WIDTH),
conv_std_logic_vector(25651,AMPL_WIDTH),
conv_std_logic_vector(25653,AMPL_WIDTH),
conv_std_logic_vector(25655,AMPL_WIDTH),
conv_std_logic_vector(25657,AMPL_WIDTH),
conv_std_logic_vector(25659,AMPL_WIDTH),
conv_std_logic_vector(25661,AMPL_WIDTH),
conv_std_logic_vector(25663,AMPL_WIDTH),
conv_std_logic_vector(25665,AMPL_WIDTH),
conv_std_logic_vector(25667,AMPL_WIDTH),
conv_std_logic_vector(25669,AMPL_WIDTH),
conv_std_logic_vector(25671,AMPL_WIDTH),
conv_std_logic_vector(25672,AMPL_WIDTH),
conv_std_logic_vector(25674,AMPL_WIDTH),
conv_std_logic_vector(25676,AMPL_WIDTH),
conv_std_logic_vector(25678,AMPL_WIDTH),
conv_std_logic_vector(25680,AMPL_WIDTH),
conv_std_logic_vector(25682,AMPL_WIDTH),
conv_std_logic_vector(25684,AMPL_WIDTH),
conv_std_logic_vector(25686,AMPL_WIDTH),
conv_std_logic_vector(25688,AMPL_WIDTH),
conv_std_logic_vector(25690,AMPL_WIDTH),
conv_std_logic_vector(25692,AMPL_WIDTH),
conv_std_logic_vector(25694,AMPL_WIDTH),
conv_std_logic_vector(25696,AMPL_WIDTH),
conv_std_logic_vector(25698,AMPL_WIDTH),
conv_std_logic_vector(25700,AMPL_WIDTH),
conv_std_logic_vector(25702,AMPL_WIDTH),
conv_std_logic_vector(25704,AMPL_WIDTH),
conv_std_logic_vector(25706,AMPL_WIDTH),
conv_std_logic_vector(25708,AMPL_WIDTH),
conv_std_logic_vector(25710,AMPL_WIDTH),
conv_std_logic_vector(25711,AMPL_WIDTH),
conv_std_logic_vector(25713,AMPL_WIDTH),
conv_std_logic_vector(25715,AMPL_WIDTH),
conv_std_logic_vector(25717,AMPL_WIDTH),
conv_std_logic_vector(25719,AMPL_WIDTH),
conv_std_logic_vector(25721,AMPL_WIDTH),
conv_std_logic_vector(25723,AMPL_WIDTH),
conv_std_logic_vector(25725,AMPL_WIDTH),
conv_std_logic_vector(25727,AMPL_WIDTH),
conv_std_logic_vector(25729,AMPL_WIDTH),
conv_std_logic_vector(25731,AMPL_WIDTH),
conv_std_logic_vector(25733,AMPL_WIDTH),
conv_std_logic_vector(25735,AMPL_WIDTH),
conv_std_logic_vector(25737,AMPL_WIDTH),
conv_std_logic_vector(25739,AMPL_WIDTH),
conv_std_logic_vector(25741,AMPL_WIDTH),
conv_std_logic_vector(25743,AMPL_WIDTH),
conv_std_logic_vector(25745,AMPL_WIDTH),
conv_std_logic_vector(25746,AMPL_WIDTH),
conv_std_logic_vector(25748,AMPL_WIDTH),
conv_std_logic_vector(25750,AMPL_WIDTH),
conv_std_logic_vector(25752,AMPL_WIDTH),
conv_std_logic_vector(25754,AMPL_WIDTH),
conv_std_logic_vector(25756,AMPL_WIDTH),
conv_std_logic_vector(25758,AMPL_WIDTH),
conv_std_logic_vector(25760,AMPL_WIDTH),
conv_std_logic_vector(25762,AMPL_WIDTH),
conv_std_logic_vector(25764,AMPL_WIDTH),
conv_std_logic_vector(25766,AMPL_WIDTH),
conv_std_logic_vector(25768,AMPL_WIDTH),
conv_std_logic_vector(25770,AMPL_WIDTH),
conv_std_logic_vector(25772,AMPL_WIDTH),
conv_std_logic_vector(25774,AMPL_WIDTH),
conv_std_logic_vector(25776,AMPL_WIDTH),
conv_std_logic_vector(25778,AMPL_WIDTH),
conv_std_logic_vector(25779,AMPL_WIDTH),
conv_std_logic_vector(25781,AMPL_WIDTH),
conv_std_logic_vector(25783,AMPL_WIDTH),
conv_std_logic_vector(25785,AMPL_WIDTH),
conv_std_logic_vector(25787,AMPL_WIDTH),
conv_std_logic_vector(25789,AMPL_WIDTH),
conv_std_logic_vector(25791,AMPL_WIDTH),
conv_std_logic_vector(25793,AMPL_WIDTH),
conv_std_logic_vector(25795,AMPL_WIDTH),
conv_std_logic_vector(25797,AMPL_WIDTH),
conv_std_logic_vector(25799,AMPL_WIDTH),
conv_std_logic_vector(25801,AMPL_WIDTH),
conv_std_logic_vector(25803,AMPL_WIDTH),
conv_std_logic_vector(25805,AMPL_WIDTH),
conv_std_logic_vector(25807,AMPL_WIDTH),
conv_std_logic_vector(25809,AMPL_WIDTH),
conv_std_logic_vector(25810,AMPL_WIDTH),
conv_std_logic_vector(25812,AMPL_WIDTH),
conv_std_logic_vector(25814,AMPL_WIDTH),
conv_std_logic_vector(25816,AMPL_WIDTH),
conv_std_logic_vector(25818,AMPL_WIDTH),
conv_std_logic_vector(25820,AMPL_WIDTH),
conv_std_logic_vector(25822,AMPL_WIDTH),
conv_std_logic_vector(25824,AMPL_WIDTH),
conv_std_logic_vector(25826,AMPL_WIDTH),
conv_std_logic_vector(25828,AMPL_WIDTH),
conv_std_logic_vector(25830,AMPL_WIDTH),
conv_std_logic_vector(25832,AMPL_WIDTH),
conv_std_logic_vector(25834,AMPL_WIDTH),
conv_std_logic_vector(25836,AMPL_WIDTH),
conv_std_logic_vector(25838,AMPL_WIDTH),
conv_std_logic_vector(25839,AMPL_WIDTH),
conv_std_logic_vector(25841,AMPL_WIDTH),
conv_std_logic_vector(25843,AMPL_WIDTH),
conv_std_logic_vector(25845,AMPL_WIDTH),
conv_std_logic_vector(25847,AMPL_WIDTH),
conv_std_logic_vector(25849,AMPL_WIDTH),
conv_std_logic_vector(25851,AMPL_WIDTH),
conv_std_logic_vector(25853,AMPL_WIDTH),
conv_std_logic_vector(25855,AMPL_WIDTH),
conv_std_logic_vector(25857,AMPL_WIDTH),
conv_std_logic_vector(25859,AMPL_WIDTH),
conv_std_logic_vector(25861,AMPL_WIDTH),
conv_std_logic_vector(25863,AMPL_WIDTH),
conv_std_logic_vector(25865,AMPL_WIDTH),
conv_std_logic_vector(25866,AMPL_WIDTH),
conv_std_logic_vector(25868,AMPL_WIDTH),
conv_std_logic_vector(25870,AMPL_WIDTH),
conv_std_logic_vector(25872,AMPL_WIDTH),
conv_std_logic_vector(25874,AMPL_WIDTH),
conv_std_logic_vector(25876,AMPL_WIDTH),
conv_std_logic_vector(25878,AMPL_WIDTH),
conv_std_logic_vector(25880,AMPL_WIDTH),
conv_std_logic_vector(25882,AMPL_WIDTH),
conv_std_logic_vector(25884,AMPL_WIDTH),
conv_std_logic_vector(25886,AMPL_WIDTH),
conv_std_logic_vector(25888,AMPL_WIDTH),
conv_std_logic_vector(25890,AMPL_WIDTH),
conv_std_logic_vector(25892,AMPL_WIDTH),
conv_std_logic_vector(25893,AMPL_WIDTH),
conv_std_logic_vector(25895,AMPL_WIDTH),
conv_std_logic_vector(25897,AMPL_WIDTH),
conv_std_logic_vector(25899,AMPL_WIDTH),
conv_std_logic_vector(25901,AMPL_WIDTH),
conv_std_logic_vector(25903,AMPL_WIDTH),
conv_std_logic_vector(25905,AMPL_WIDTH),
conv_std_logic_vector(25907,AMPL_WIDTH),
conv_std_logic_vector(25909,AMPL_WIDTH),
conv_std_logic_vector(25911,AMPL_WIDTH),
conv_std_logic_vector(25913,AMPL_WIDTH),
conv_std_logic_vector(25915,AMPL_WIDTH),
conv_std_logic_vector(25917,AMPL_WIDTH),
conv_std_logic_vector(25918,AMPL_WIDTH),
conv_std_logic_vector(25920,AMPL_WIDTH),
conv_std_logic_vector(25922,AMPL_WIDTH),
conv_std_logic_vector(25924,AMPL_WIDTH),
conv_std_logic_vector(25926,AMPL_WIDTH),
conv_std_logic_vector(25928,AMPL_WIDTH),
conv_std_logic_vector(25930,AMPL_WIDTH),
conv_std_logic_vector(25932,AMPL_WIDTH),
conv_std_logic_vector(25934,AMPL_WIDTH),
conv_std_logic_vector(25936,AMPL_WIDTH),
conv_std_logic_vector(25938,AMPL_WIDTH),
conv_std_logic_vector(25940,AMPL_WIDTH),
conv_std_logic_vector(25942,AMPL_WIDTH),
conv_std_logic_vector(25943,AMPL_WIDTH),
conv_std_logic_vector(25945,AMPL_WIDTH),
conv_std_logic_vector(25947,AMPL_WIDTH),
conv_std_logic_vector(25949,AMPL_WIDTH),
conv_std_logic_vector(25951,AMPL_WIDTH),
conv_std_logic_vector(25953,AMPL_WIDTH),
conv_std_logic_vector(25955,AMPL_WIDTH),
conv_std_logic_vector(25957,AMPL_WIDTH),
conv_std_logic_vector(25959,AMPL_WIDTH),
conv_std_logic_vector(25961,AMPL_WIDTH),
conv_std_logic_vector(25963,AMPL_WIDTH),
conv_std_logic_vector(25965,AMPL_WIDTH),
conv_std_logic_vector(25966,AMPL_WIDTH),
conv_std_logic_vector(25968,AMPL_WIDTH),
conv_std_logic_vector(25970,AMPL_WIDTH),
conv_std_logic_vector(25972,AMPL_WIDTH),
conv_std_logic_vector(25974,AMPL_WIDTH),
conv_std_logic_vector(25976,AMPL_WIDTH),
conv_std_logic_vector(25978,AMPL_WIDTH),
conv_std_logic_vector(25980,AMPL_WIDTH),
conv_std_logic_vector(25982,AMPL_WIDTH),
conv_std_logic_vector(25984,AMPL_WIDTH),
conv_std_logic_vector(25986,AMPL_WIDTH),
conv_std_logic_vector(25988,AMPL_WIDTH),
conv_std_logic_vector(25989,AMPL_WIDTH),
conv_std_logic_vector(25991,AMPL_WIDTH),
conv_std_logic_vector(25993,AMPL_WIDTH),
conv_std_logic_vector(25995,AMPL_WIDTH),
conv_std_logic_vector(25997,AMPL_WIDTH),
conv_std_logic_vector(25999,AMPL_WIDTH),
conv_std_logic_vector(26001,AMPL_WIDTH),
conv_std_logic_vector(26003,AMPL_WIDTH),
conv_std_logic_vector(26005,AMPL_WIDTH),
conv_std_logic_vector(26007,AMPL_WIDTH),
conv_std_logic_vector(26009,AMPL_WIDTH),
conv_std_logic_vector(26010,AMPL_WIDTH),
conv_std_logic_vector(26012,AMPL_WIDTH),
conv_std_logic_vector(26014,AMPL_WIDTH),
conv_std_logic_vector(26016,AMPL_WIDTH),
conv_std_logic_vector(26018,AMPL_WIDTH),
conv_std_logic_vector(26020,AMPL_WIDTH),
conv_std_logic_vector(26022,AMPL_WIDTH),
conv_std_logic_vector(26024,AMPL_WIDTH),
conv_std_logic_vector(26026,AMPL_WIDTH),
conv_std_logic_vector(26028,AMPL_WIDTH),
conv_std_logic_vector(26030,AMPL_WIDTH),
conv_std_logic_vector(26031,AMPL_WIDTH),
conv_std_logic_vector(26033,AMPL_WIDTH),
conv_std_logic_vector(26035,AMPL_WIDTH),
conv_std_logic_vector(26037,AMPL_WIDTH),
conv_std_logic_vector(26039,AMPL_WIDTH),
conv_std_logic_vector(26041,AMPL_WIDTH),
conv_std_logic_vector(26043,AMPL_WIDTH),
conv_std_logic_vector(26045,AMPL_WIDTH),
conv_std_logic_vector(26047,AMPL_WIDTH),
conv_std_logic_vector(26049,AMPL_WIDTH),
conv_std_logic_vector(26051,AMPL_WIDTH),
conv_std_logic_vector(26052,AMPL_WIDTH),
conv_std_logic_vector(26054,AMPL_WIDTH),
conv_std_logic_vector(26056,AMPL_WIDTH),
conv_std_logic_vector(26058,AMPL_WIDTH),
conv_std_logic_vector(26060,AMPL_WIDTH),
conv_std_logic_vector(26062,AMPL_WIDTH),
conv_std_logic_vector(26064,AMPL_WIDTH),
conv_std_logic_vector(26066,AMPL_WIDTH),
conv_std_logic_vector(26068,AMPL_WIDTH),
conv_std_logic_vector(26070,AMPL_WIDTH),
conv_std_logic_vector(26071,AMPL_WIDTH),
conv_std_logic_vector(26073,AMPL_WIDTH),
conv_std_logic_vector(26075,AMPL_WIDTH),
conv_std_logic_vector(26077,AMPL_WIDTH),
conv_std_logic_vector(26079,AMPL_WIDTH),
conv_std_logic_vector(26081,AMPL_WIDTH),
conv_std_logic_vector(26083,AMPL_WIDTH),
conv_std_logic_vector(26085,AMPL_WIDTH),
conv_std_logic_vector(26087,AMPL_WIDTH),
conv_std_logic_vector(26089,AMPL_WIDTH),
conv_std_logic_vector(26090,AMPL_WIDTH),
conv_std_logic_vector(26092,AMPL_WIDTH),
conv_std_logic_vector(26094,AMPL_WIDTH),
conv_std_logic_vector(26096,AMPL_WIDTH),
conv_std_logic_vector(26098,AMPL_WIDTH),
conv_std_logic_vector(26100,AMPL_WIDTH),
conv_std_logic_vector(26102,AMPL_WIDTH),
conv_std_logic_vector(26104,AMPL_WIDTH),
conv_std_logic_vector(26106,AMPL_WIDTH),
conv_std_logic_vector(26108,AMPL_WIDTH),
conv_std_logic_vector(26109,AMPL_WIDTH),
conv_std_logic_vector(26111,AMPL_WIDTH),
conv_std_logic_vector(26113,AMPL_WIDTH),
conv_std_logic_vector(26115,AMPL_WIDTH),
conv_std_logic_vector(26117,AMPL_WIDTH),
conv_std_logic_vector(26119,AMPL_WIDTH),
conv_std_logic_vector(26121,AMPL_WIDTH),
conv_std_logic_vector(26123,AMPL_WIDTH),
conv_std_logic_vector(26125,AMPL_WIDTH),
conv_std_logic_vector(26127,AMPL_WIDTH),
conv_std_logic_vector(26128,AMPL_WIDTH),
conv_std_logic_vector(26130,AMPL_WIDTH),
conv_std_logic_vector(26132,AMPL_WIDTH),
conv_std_logic_vector(26134,AMPL_WIDTH),
conv_std_logic_vector(26136,AMPL_WIDTH),
conv_std_logic_vector(26138,AMPL_WIDTH),
conv_std_logic_vector(26140,AMPL_WIDTH),
conv_std_logic_vector(26142,AMPL_WIDTH),
conv_std_logic_vector(26144,AMPL_WIDTH),
conv_std_logic_vector(26146,AMPL_WIDTH),
conv_std_logic_vector(26147,AMPL_WIDTH),
conv_std_logic_vector(26149,AMPL_WIDTH),
conv_std_logic_vector(26151,AMPL_WIDTH),
conv_std_logic_vector(26153,AMPL_WIDTH),
conv_std_logic_vector(26155,AMPL_WIDTH),
conv_std_logic_vector(26157,AMPL_WIDTH),
conv_std_logic_vector(26159,AMPL_WIDTH),
conv_std_logic_vector(26161,AMPL_WIDTH),
conv_std_logic_vector(26163,AMPL_WIDTH),
conv_std_logic_vector(26164,AMPL_WIDTH),
conv_std_logic_vector(26166,AMPL_WIDTH),
conv_std_logic_vector(26168,AMPL_WIDTH),
conv_std_logic_vector(26170,AMPL_WIDTH),
conv_std_logic_vector(26172,AMPL_WIDTH),
conv_std_logic_vector(26174,AMPL_WIDTH),
conv_std_logic_vector(26176,AMPL_WIDTH),
conv_std_logic_vector(26178,AMPL_WIDTH),
conv_std_logic_vector(26180,AMPL_WIDTH),
conv_std_logic_vector(26181,AMPL_WIDTH),
conv_std_logic_vector(26183,AMPL_WIDTH),
conv_std_logic_vector(26185,AMPL_WIDTH),
conv_std_logic_vector(26187,AMPL_WIDTH),
conv_std_logic_vector(26189,AMPL_WIDTH),
conv_std_logic_vector(26191,AMPL_WIDTH),
conv_std_logic_vector(26193,AMPL_WIDTH),
conv_std_logic_vector(26195,AMPL_WIDTH),
conv_std_logic_vector(26197,AMPL_WIDTH),
conv_std_logic_vector(26198,AMPL_WIDTH),
conv_std_logic_vector(26200,AMPL_WIDTH),
conv_std_logic_vector(26202,AMPL_WIDTH),
conv_std_logic_vector(26204,AMPL_WIDTH),
conv_std_logic_vector(26206,AMPL_WIDTH),
conv_std_logic_vector(26208,AMPL_WIDTH),
conv_std_logic_vector(26210,AMPL_WIDTH),
conv_std_logic_vector(26212,AMPL_WIDTH),
conv_std_logic_vector(26214,AMPL_WIDTH),
conv_std_logic_vector(26215,AMPL_WIDTH),
conv_std_logic_vector(26217,AMPL_WIDTH),
conv_std_logic_vector(26219,AMPL_WIDTH),
conv_std_logic_vector(26221,AMPL_WIDTH),
conv_std_logic_vector(26223,AMPL_WIDTH),
conv_std_logic_vector(26225,AMPL_WIDTH),
conv_std_logic_vector(26227,AMPL_WIDTH),
conv_std_logic_vector(26229,AMPL_WIDTH),
conv_std_logic_vector(26230,AMPL_WIDTH),
conv_std_logic_vector(26232,AMPL_WIDTH),
conv_std_logic_vector(26234,AMPL_WIDTH),
conv_std_logic_vector(26236,AMPL_WIDTH),
conv_std_logic_vector(26238,AMPL_WIDTH),
conv_std_logic_vector(26240,AMPL_WIDTH),
conv_std_logic_vector(26242,AMPL_WIDTH),
conv_std_logic_vector(26244,AMPL_WIDTH),
conv_std_logic_vector(26246,AMPL_WIDTH),
conv_std_logic_vector(26247,AMPL_WIDTH),
conv_std_logic_vector(26249,AMPL_WIDTH),
conv_std_logic_vector(26251,AMPL_WIDTH),
conv_std_logic_vector(26253,AMPL_WIDTH),
conv_std_logic_vector(26255,AMPL_WIDTH),
conv_std_logic_vector(26257,AMPL_WIDTH),
conv_std_logic_vector(26259,AMPL_WIDTH),
conv_std_logic_vector(26261,AMPL_WIDTH),
conv_std_logic_vector(26262,AMPL_WIDTH),
conv_std_logic_vector(26264,AMPL_WIDTH),
conv_std_logic_vector(26266,AMPL_WIDTH),
conv_std_logic_vector(26268,AMPL_WIDTH),
conv_std_logic_vector(26270,AMPL_WIDTH),
conv_std_logic_vector(26272,AMPL_WIDTH),
conv_std_logic_vector(26274,AMPL_WIDTH),
conv_std_logic_vector(26276,AMPL_WIDTH),
conv_std_logic_vector(26277,AMPL_WIDTH),
conv_std_logic_vector(26279,AMPL_WIDTH),
conv_std_logic_vector(26281,AMPL_WIDTH),
conv_std_logic_vector(26283,AMPL_WIDTH),
conv_std_logic_vector(26285,AMPL_WIDTH),
conv_std_logic_vector(26287,AMPL_WIDTH),
conv_std_logic_vector(26289,AMPL_WIDTH),
conv_std_logic_vector(26291,AMPL_WIDTH),
conv_std_logic_vector(26292,AMPL_WIDTH),
conv_std_logic_vector(26294,AMPL_WIDTH),
conv_std_logic_vector(26296,AMPL_WIDTH),
conv_std_logic_vector(26298,AMPL_WIDTH),
conv_std_logic_vector(26300,AMPL_WIDTH),
conv_std_logic_vector(26302,AMPL_WIDTH),
conv_std_logic_vector(26304,AMPL_WIDTH),
conv_std_logic_vector(26306,AMPL_WIDTH),
conv_std_logic_vector(26307,AMPL_WIDTH),
conv_std_logic_vector(26309,AMPL_WIDTH),
conv_std_logic_vector(26311,AMPL_WIDTH),
conv_std_logic_vector(26313,AMPL_WIDTH),
conv_std_logic_vector(26315,AMPL_WIDTH),
conv_std_logic_vector(26317,AMPL_WIDTH),
conv_std_logic_vector(26319,AMPL_WIDTH),
conv_std_logic_vector(26321,AMPL_WIDTH),
conv_std_logic_vector(26322,AMPL_WIDTH),
conv_std_logic_vector(26324,AMPL_WIDTH),
conv_std_logic_vector(26326,AMPL_WIDTH),
conv_std_logic_vector(26328,AMPL_WIDTH),
conv_std_logic_vector(26330,AMPL_WIDTH),
conv_std_logic_vector(26332,AMPL_WIDTH),
conv_std_logic_vector(26334,AMPL_WIDTH),
conv_std_logic_vector(26336,AMPL_WIDTH),
conv_std_logic_vector(26337,AMPL_WIDTH),
conv_std_logic_vector(26339,AMPL_WIDTH),
conv_std_logic_vector(26341,AMPL_WIDTH),
conv_std_logic_vector(26343,AMPL_WIDTH),
conv_std_logic_vector(26345,AMPL_WIDTH),
conv_std_logic_vector(26347,AMPL_WIDTH),
conv_std_logic_vector(26349,AMPL_WIDTH),
conv_std_logic_vector(26350,AMPL_WIDTH),
conv_std_logic_vector(26352,AMPL_WIDTH),
conv_std_logic_vector(26354,AMPL_WIDTH),
conv_std_logic_vector(26356,AMPL_WIDTH),
conv_std_logic_vector(26358,AMPL_WIDTH),
conv_std_logic_vector(26360,AMPL_WIDTH),
conv_std_logic_vector(26362,AMPL_WIDTH),
conv_std_logic_vector(26364,AMPL_WIDTH),
conv_std_logic_vector(26365,AMPL_WIDTH),
conv_std_logic_vector(26367,AMPL_WIDTH),
conv_std_logic_vector(26369,AMPL_WIDTH),
conv_std_logic_vector(26371,AMPL_WIDTH),
conv_std_logic_vector(26373,AMPL_WIDTH),
conv_std_logic_vector(26375,AMPL_WIDTH),
conv_std_logic_vector(26377,AMPL_WIDTH),
conv_std_logic_vector(26378,AMPL_WIDTH),
conv_std_logic_vector(26380,AMPL_WIDTH),
conv_std_logic_vector(26382,AMPL_WIDTH),
conv_std_logic_vector(26384,AMPL_WIDTH),
conv_std_logic_vector(26386,AMPL_WIDTH),
conv_std_logic_vector(26388,AMPL_WIDTH),
conv_std_logic_vector(26390,AMPL_WIDTH),
conv_std_logic_vector(26392,AMPL_WIDTH),
conv_std_logic_vector(26393,AMPL_WIDTH),
conv_std_logic_vector(26395,AMPL_WIDTH),
conv_std_logic_vector(26397,AMPL_WIDTH),
conv_std_logic_vector(26399,AMPL_WIDTH),
conv_std_logic_vector(26401,AMPL_WIDTH),
conv_std_logic_vector(26403,AMPL_WIDTH),
conv_std_logic_vector(26405,AMPL_WIDTH),
conv_std_logic_vector(26406,AMPL_WIDTH),
conv_std_logic_vector(26408,AMPL_WIDTH),
conv_std_logic_vector(26410,AMPL_WIDTH),
conv_std_logic_vector(26412,AMPL_WIDTH),
conv_std_logic_vector(26414,AMPL_WIDTH),
conv_std_logic_vector(26416,AMPL_WIDTH),
conv_std_logic_vector(26418,AMPL_WIDTH),
conv_std_logic_vector(26419,AMPL_WIDTH),
conv_std_logic_vector(26421,AMPL_WIDTH),
conv_std_logic_vector(26423,AMPL_WIDTH),
conv_std_logic_vector(26425,AMPL_WIDTH),
conv_std_logic_vector(26427,AMPL_WIDTH),
conv_std_logic_vector(26429,AMPL_WIDTH),
conv_std_logic_vector(26431,AMPL_WIDTH),
conv_std_logic_vector(26432,AMPL_WIDTH),
conv_std_logic_vector(26434,AMPL_WIDTH),
conv_std_logic_vector(26436,AMPL_WIDTH),
conv_std_logic_vector(26438,AMPL_WIDTH),
conv_std_logic_vector(26440,AMPL_WIDTH),
conv_std_logic_vector(26442,AMPL_WIDTH),
conv_std_logic_vector(26444,AMPL_WIDTH),
conv_std_logic_vector(26445,AMPL_WIDTH),
conv_std_logic_vector(26447,AMPL_WIDTH),
conv_std_logic_vector(26449,AMPL_WIDTH),
conv_std_logic_vector(26451,AMPL_WIDTH),
conv_std_logic_vector(26453,AMPL_WIDTH),
conv_std_logic_vector(26455,AMPL_WIDTH),
conv_std_logic_vector(26457,AMPL_WIDTH),
conv_std_logic_vector(26458,AMPL_WIDTH),
conv_std_logic_vector(26460,AMPL_WIDTH),
conv_std_logic_vector(26462,AMPL_WIDTH),
conv_std_logic_vector(26464,AMPL_WIDTH),
conv_std_logic_vector(26466,AMPL_WIDTH),
conv_std_logic_vector(26468,AMPL_WIDTH),
conv_std_logic_vector(26469,AMPL_WIDTH),
conv_std_logic_vector(26471,AMPL_WIDTH),
conv_std_logic_vector(26473,AMPL_WIDTH),
conv_std_logic_vector(26475,AMPL_WIDTH),
conv_std_logic_vector(26477,AMPL_WIDTH),
conv_std_logic_vector(26479,AMPL_WIDTH),
conv_std_logic_vector(26481,AMPL_WIDTH),
conv_std_logic_vector(26482,AMPL_WIDTH),
conv_std_logic_vector(26484,AMPL_WIDTH),
conv_std_logic_vector(26486,AMPL_WIDTH),
conv_std_logic_vector(26488,AMPL_WIDTH),
conv_std_logic_vector(26490,AMPL_WIDTH),
conv_std_logic_vector(26492,AMPL_WIDTH),
conv_std_logic_vector(26494,AMPL_WIDTH),
conv_std_logic_vector(26495,AMPL_WIDTH),
conv_std_logic_vector(26497,AMPL_WIDTH),
conv_std_logic_vector(26499,AMPL_WIDTH),
conv_std_logic_vector(26501,AMPL_WIDTH),
conv_std_logic_vector(26503,AMPL_WIDTH),
conv_std_logic_vector(26505,AMPL_WIDTH),
conv_std_logic_vector(26506,AMPL_WIDTH),
conv_std_logic_vector(26508,AMPL_WIDTH),
conv_std_logic_vector(26510,AMPL_WIDTH),
conv_std_logic_vector(26512,AMPL_WIDTH),
conv_std_logic_vector(26514,AMPL_WIDTH),
conv_std_logic_vector(26516,AMPL_WIDTH),
conv_std_logic_vector(26518,AMPL_WIDTH),
conv_std_logic_vector(26519,AMPL_WIDTH),
conv_std_logic_vector(26521,AMPL_WIDTH),
conv_std_logic_vector(26523,AMPL_WIDTH),
conv_std_logic_vector(26525,AMPL_WIDTH),
conv_std_logic_vector(26527,AMPL_WIDTH),
conv_std_logic_vector(26529,AMPL_WIDTH),
conv_std_logic_vector(26530,AMPL_WIDTH),
conv_std_logic_vector(26532,AMPL_WIDTH),
conv_std_logic_vector(26534,AMPL_WIDTH),
conv_std_logic_vector(26536,AMPL_WIDTH),
conv_std_logic_vector(26538,AMPL_WIDTH),
conv_std_logic_vector(26540,AMPL_WIDTH),
conv_std_logic_vector(26542,AMPL_WIDTH),
conv_std_logic_vector(26543,AMPL_WIDTH),
conv_std_logic_vector(26545,AMPL_WIDTH),
conv_std_logic_vector(26547,AMPL_WIDTH),
conv_std_logic_vector(26549,AMPL_WIDTH),
conv_std_logic_vector(26551,AMPL_WIDTH),
conv_std_logic_vector(26553,AMPL_WIDTH),
conv_std_logic_vector(26554,AMPL_WIDTH),
conv_std_logic_vector(26556,AMPL_WIDTH),
conv_std_logic_vector(26558,AMPL_WIDTH),
conv_std_logic_vector(26560,AMPL_WIDTH),
conv_std_logic_vector(26562,AMPL_WIDTH),
conv_std_logic_vector(26564,AMPL_WIDTH),
conv_std_logic_vector(26565,AMPL_WIDTH),
conv_std_logic_vector(26567,AMPL_WIDTH),
conv_std_logic_vector(26569,AMPL_WIDTH),
conv_std_logic_vector(26571,AMPL_WIDTH),
conv_std_logic_vector(26573,AMPL_WIDTH),
conv_std_logic_vector(26575,AMPL_WIDTH),
conv_std_logic_vector(26576,AMPL_WIDTH),
conv_std_logic_vector(26578,AMPL_WIDTH),
conv_std_logic_vector(26580,AMPL_WIDTH),
conv_std_logic_vector(26582,AMPL_WIDTH),
conv_std_logic_vector(26584,AMPL_WIDTH),
conv_std_logic_vector(26586,AMPL_WIDTH),
conv_std_logic_vector(26588,AMPL_WIDTH),
conv_std_logic_vector(26589,AMPL_WIDTH),
conv_std_logic_vector(26591,AMPL_WIDTH),
conv_std_logic_vector(26593,AMPL_WIDTH),
conv_std_logic_vector(26595,AMPL_WIDTH),
conv_std_logic_vector(26597,AMPL_WIDTH),
conv_std_logic_vector(26599,AMPL_WIDTH),
conv_std_logic_vector(26600,AMPL_WIDTH),
conv_std_logic_vector(26602,AMPL_WIDTH),
conv_std_logic_vector(26604,AMPL_WIDTH),
conv_std_logic_vector(26606,AMPL_WIDTH),
conv_std_logic_vector(26608,AMPL_WIDTH),
conv_std_logic_vector(26610,AMPL_WIDTH),
conv_std_logic_vector(26611,AMPL_WIDTH),
conv_std_logic_vector(26613,AMPL_WIDTH),
conv_std_logic_vector(26615,AMPL_WIDTH),
conv_std_logic_vector(26617,AMPL_WIDTH),
conv_std_logic_vector(26619,AMPL_WIDTH),
conv_std_logic_vector(26621,AMPL_WIDTH),
conv_std_logic_vector(26622,AMPL_WIDTH),
conv_std_logic_vector(26624,AMPL_WIDTH),
conv_std_logic_vector(26626,AMPL_WIDTH),
conv_std_logic_vector(26628,AMPL_WIDTH),
conv_std_logic_vector(26630,AMPL_WIDTH),
conv_std_logic_vector(26631,AMPL_WIDTH),
conv_std_logic_vector(26633,AMPL_WIDTH),
conv_std_logic_vector(26635,AMPL_WIDTH),
conv_std_logic_vector(26637,AMPL_WIDTH),
conv_std_logic_vector(26639,AMPL_WIDTH),
conv_std_logic_vector(26641,AMPL_WIDTH),
conv_std_logic_vector(26642,AMPL_WIDTH),
conv_std_logic_vector(26644,AMPL_WIDTH),
conv_std_logic_vector(26646,AMPL_WIDTH),
conv_std_logic_vector(26648,AMPL_WIDTH),
conv_std_logic_vector(26650,AMPL_WIDTH),
conv_std_logic_vector(26652,AMPL_WIDTH),
conv_std_logic_vector(26653,AMPL_WIDTH),
conv_std_logic_vector(26655,AMPL_WIDTH),
conv_std_logic_vector(26657,AMPL_WIDTH),
conv_std_logic_vector(26659,AMPL_WIDTH),
conv_std_logic_vector(26661,AMPL_WIDTH),
conv_std_logic_vector(26663,AMPL_WIDTH),
conv_std_logic_vector(26664,AMPL_WIDTH),
conv_std_logic_vector(26666,AMPL_WIDTH),
conv_std_logic_vector(26668,AMPL_WIDTH),
conv_std_logic_vector(26670,AMPL_WIDTH),
conv_std_logic_vector(26672,AMPL_WIDTH),
conv_std_logic_vector(26674,AMPL_WIDTH),
conv_std_logic_vector(26675,AMPL_WIDTH),
conv_std_logic_vector(26677,AMPL_WIDTH),
conv_std_logic_vector(26679,AMPL_WIDTH),
conv_std_logic_vector(26681,AMPL_WIDTH),
conv_std_logic_vector(26683,AMPL_WIDTH),
conv_std_logic_vector(26684,AMPL_WIDTH),
conv_std_logic_vector(26686,AMPL_WIDTH),
conv_std_logic_vector(26688,AMPL_WIDTH),
conv_std_logic_vector(26690,AMPL_WIDTH),
conv_std_logic_vector(26692,AMPL_WIDTH),
conv_std_logic_vector(26694,AMPL_WIDTH),
conv_std_logic_vector(26695,AMPL_WIDTH),
conv_std_logic_vector(26697,AMPL_WIDTH),
conv_std_logic_vector(26699,AMPL_WIDTH),
conv_std_logic_vector(26701,AMPL_WIDTH),
conv_std_logic_vector(26703,AMPL_WIDTH),
conv_std_logic_vector(26705,AMPL_WIDTH),
conv_std_logic_vector(26706,AMPL_WIDTH),
conv_std_logic_vector(26708,AMPL_WIDTH),
conv_std_logic_vector(26710,AMPL_WIDTH),
conv_std_logic_vector(26712,AMPL_WIDTH),
conv_std_logic_vector(26714,AMPL_WIDTH),
conv_std_logic_vector(26715,AMPL_WIDTH),
conv_std_logic_vector(26717,AMPL_WIDTH),
conv_std_logic_vector(26719,AMPL_WIDTH),
conv_std_logic_vector(26721,AMPL_WIDTH),
conv_std_logic_vector(26723,AMPL_WIDTH),
conv_std_logic_vector(26725,AMPL_WIDTH),
conv_std_logic_vector(26726,AMPL_WIDTH),
conv_std_logic_vector(26728,AMPL_WIDTH),
conv_std_logic_vector(26730,AMPL_WIDTH),
conv_std_logic_vector(26732,AMPL_WIDTH),
conv_std_logic_vector(26734,AMPL_WIDTH),
conv_std_logic_vector(26735,AMPL_WIDTH),
conv_std_logic_vector(26737,AMPL_WIDTH),
conv_std_logic_vector(26739,AMPL_WIDTH),
conv_std_logic_vector(26741,AMPL_WIDTH),
conv_std_logic_vector(26743,AMPL_WIDTH),
conv_std_logic_vector(26745,AMPL_WIDTH),
conv_std_logic_vector(26746,AMPL_WIDTH),
conv_std_logic_vector(26748,AMPL_WIDTH),
conv_std_logic_vector(26750,AMPL_WIDTH),
conv_std_logic_vector(26752,AMPL_WIDTH),
conv_std_logic_vector(26754,AMPL_WIDTH),
conv_std_logic_vector(26755,AMPL_WIDTH),
conv_std_logic_vector(26757,AMPL_WIDTH),
conv_std_logic_vector(26759,AMPL_WIDTH),
conv_std_logic_vector(26761,AMPL_WIDTH),
conv_std_logic_vector(26763,AMPL_WIDTH),
conv_std_logic_vector(26764,AMPL_WIDTH),
conv_std_logic_vector(26766,AMPL_WIDTH),
conv_std_logic_vector(26768,AMPL_WIDTH),
conv_std_logic_vector(26770,AMPL_WIDTH),
conv_std_logic_vector(26772,AMPL_WIDTH),
conv_std_logic_vector(26774,AMPL_WIDTH),
conv_std_logic_vector(26775,AMPL_WIDTH),
conv_std_logic_vector(26777,AMPL_WIDTH),
conv_std_logic_vector(26779,AMPL_WIDTH),
conv_std_logic_vector(26781,AMPL_WIDTH),
conv_std_logic_vector(26783,AMPL_WIDTH),
conv_std_logic_vector(26784,AMPL_WIDTH),
conv_std_logic_vector(26786,AMPL_WIDTH),
conv_std_logic_vector(26788,AMPL_WIDTH),
conv_std_logic_vector(26790,AMPL_WIDTH),
conv_std_logic_vector(26792,AMPL_WIDTH),
conv_std_logic_vector(26793,AMPL_WIDTH),
conv_std_logic_vector(26795,AMPL_WIDTH),
conv_std_logic_vector(26797,AMPL_WIDTH),
conv_std_logic_vector(26799,AMPL_WIDTH),
conv_std_logic_vector(26801,AMPL_WIDTH),
conv_std_logic_vector(26802,AMPL_WIDTH),
conv_std_logic_vector(26804,AMPL_WIDTH),
conv_std_logic_vector(26806,AMPL_WIDTH),
conv_std_logic_vector(26808,AMPL_WIDTH),
conv_std_logic_vector(26810,AMPL_WIDTH),
conv_std_logic_vector(26811,AMPL_WIDTH),
conv_std_logic_vector(26813,AMPL_WIDTH),
conv_std_logic_vector(26815,AMPL_WIDTH),
conv_std_logic_vector(26817,AMPL_WIDTH),
conv_std_logic_vector(26819,AMPL_WIDTH),
conv_std_logic_vector(26821,AMPL_WIDTH),
conv_std_logic_vector(26822,AMPL_WIDTH),
conv_std_logic_vector(26824,AMPL_WIDTH),
conv_std_logic_vector(26826,AMPL_WIDTH),
conv_std_logic_vector(26828,AMPL_WIDTH),
conv_std_logic_vector(26830,AMPL_WIDTH),
conv_std_logic_vector(26831,AMPL_WIDTH),
conv_std_logic_vector(26833,AMPL_WIDTH),
conv_std_logic_vector(26835,AMPL_WIDTH),
conv_std_logic_vector(26837,AMPL_WIDTH),
conv_std_logic_vector(26839,AMPL_WIDTH),
conv_std_logic_vector(26840,AMPL_WIDTH),
conv_std_logic_vector(26842,AMPL_WIDTH),
conv_std_logic_vector(26844,AMPL_WIDTH),
conv_std_logic_vector(26846,AMPL_WIDTH),
conv_std_logic_vector(26848,AMPL_WIDTH),
conv_std_logic_vector(26849,AMPL_WIDTH),
conv_std_logic_vector(26851,AMPL_WIDTH),
conv_std_logic_vector(26853,AMPL_WIDTH),
conv_std_logic_vector(26855,AMPL_WIDTH),
conv_std_logic_vector(26857,AMPL_WIDTH),
conv_std_logic_vector(26858,AMPL_WIDTH),
conv_std_logic_vector(26860,AMPL_WIDTH),
conv_std_logic_vector(26862,AMPL_WIDTH),
conv_std_logic_vector(26864,AMPL_WIDTH),
conv_std_logic_vector(26866,AMPL_WIDTH),
conv_std_logic_vector(26867,AMPL_WIDTH),
conv_std_logic_vector(26869,AMPL_WIDTH),
conv_std_logic_vector(26871,AMPL_WIDTH),
conv_std_logic_vector(26873,AMPL_WIDTH),
conv_std_logic_vector(26875,AMPL_WIDTH),
conv_std_logic_vector(26876,AMPL_WIDTH),
conv_std_logic_vector(26878,AMPL_WIDTH),
conv_std_logic_vector(26880,AMPL_WIDTH),
conv_std_logic_vector(26882,AMPL_WIDTH),
conv_std_logic_vector(26884,AMPL_WIDTH),
conv_std_logic_vector(26885,AMPL_WIDTH),
conv_std_logic_vector(26887,AMPL_WIDTH),
conv_std_logic_vector(26889,AMPL_WIDTH),
conv_std_logic_vector(26891,AMPL_WIDTH),
conv_std_logic_vector(26893,AMPL_WIDTH),
conv_std_logic_vector(26894,AMPL_WIDTH),
conv_std_logic_vector(26896,AMPL_WIDTH),
conv_std_logic_vector(26898,AMPL_WIDTH),
conv_std_logic_vector(26900,AMPL_WIDTH),
conv_std_logic_vector(26901,AMPL_WIDTH),
conv_std_logic_vector(26903,AMPL_WIDTH),
conv_std_logic_vector(26905,AMPL_WIDTH),
conv_std_logic_vector(26907,AMPL_WIDTH),
conv_std_logic_vector(26909,AMPL_WIDTH),
conv_std_logic_vector(26910,AMPL_WIDTH),
conv_std_logic_vector(26912,AMPL_WIDTH),
conv_std_logic_vector(26914,AMPL_WIDTH),
conv_std_logic_vector(26916,AMPL_WIDTH),
conv_std_logic_vector(26918,AMPL_WIDTH),
conv_std_logic_vector(26919,AMPL_WIDTH),
conv_std_logic_vector(26921,AMPL_WIDTH),
conv_std_logic_vector(26923,AMPL_WIDTH),
conv_std_logic_vector(26925,AMPL_WIDTH),
conv_std_logic_vector(26927,AMPL_WIDTH),
conv_std_logic_vector(26928,AMPL_WIDTH),
conv_std_logic_vector(26930,AMPL_WIDTH),
conv_std_logic_vector(26932,AMPL_WIDTH),
conv_std_logic_vector(26934,AMPL_WIDTH),
conv_std_logic_vector(26936,AMPL_WIDTH),
conv_std_logic_vector(26937,AMPL_WIDTH),
conv_std_logic_vector(26939,AMPL_WIDTH),
conv_std_logic_vector(26941,AMPL_WIDTH),
conv_std_logic_vector(26943,AMPL_WIDTH),
conv_std_logic_vector(26944,AMPL_WIDTH),
conv_std_logic_vector(26946,AMPL_WIDTH),
conv_std_logic_vector(26948,AMPL_WIDTH),
conv_std_logic_vector(26950,AMPL_WIDTH),
conv_std_logic_vector(26952,AMPL_WIDTH),
conv_std_logic_vector(26953,AMPL_WIDTH),
conv_std_logic_vector(26955,AMPL_WIDTH),
conv_std_logic_vector(26957,AMPL_WIDTH),
conv_std_logic_vector(26959,AMPL_WIDTH),
conv_std_logic_vector(26961,AMPL_WIDTH),
conv_std_logic_vector(26962,AMPL_WIDTH),
conv_std_logic_vector(26964,AMPL_WIDTH),
conv_std_logic_vector(26966,AMPL_WIDTH),
conv_std_logic_vector(26968,AMPL_WIDTH),
conv_std_logic_vector(26969,AMPL_WIDTH),
conv_std_logic_vector(26971,AMPL_WIDTH),
conv_std_logic_vector(26973,AMPL_WIDTH),
conv_std_logic_vector(26975,AMPL_WIDTH),
conv_std_logic_vector(26977,AMPL_WIDTH),
conv_std_logic_vector(26978,AMPL_WIDTH),
conv_std_logic_vector(26980,AMPL_WIDTH),
conv_std_logic_vector(26982,AMPL_WIDTH),
conv_std_logic_vector(26984,AMPL_WIDTH),
conv_std_logic_vector(26986,AMPL_WIDTH),
conv_std_logic_vector(26987,AMPL_WIDTH),
conv_std_logic_vector(26989,AMPL_WIDTH),
conv_std_logic_vector(26991,AMPL_WIDTH),
conv_std_logic_vector(26993,AMPL_WIDTH),
conv_std_logic_vector(26994,AMPL_WIDTH),
conv_std_logic_vector(26996,AMPL_WIDTH),
conv_std_logic_vector(26998,AMPL_WIDTH),
conv_std_logic_vector(27000,AMPL_WIDTH),
conv_std_logic_vector(27002,AMPL_WIDTH),
conv_std_logic_vector(27003,AMPL_WIDTH),
conv_std_logic_vector(27005,AMPL_WIDTH),
conv_std_logic_vector(27007,AMPL_WIDTH),
conv_std_logic_vector(27009,AMPL_WIDTH),
conv_std_logic_vector(27010,AMPL_WIDTH),
conv_std_logic_vector(27012,AMPL_WIDTH),
conv_std_logic_vector(27014,AMPL_WIDTH),
conv_std_logic_vector(27016,AMPL_WIDTH),
conv_std_logic_vector(27018,AMPL_WIDTH),
conv_std_logic_vector(27019,AMPL_WIDTH),
conv_std_logic_vector(27021,AMPL_WIDTH),
conv_std_logic_vector(27023,AMPL_WIDTH),
conv_std_logic_vector(27025,AMPL_WIDTH),
conv_std_logic_vector(27026,AMPL_WIDTH),
conv_std_logic_vector(27028,AMPL_WIDTH),
conv_std_logic_vector(27030,AMPL_WIDTH),
conv_std_logic_vector(27032,AMPL_WIDTH),
conv_std_logic_vector(27034,AMPL_WIDTH),
conv_std_logic_vector(27035,AMPL_WIDTH),
conv_std_logic_vector(27037,AMPL_WIDTH),
conv_std_logic_vector(27039,AMPL_WIDTH),
conv_std_logic_vector(27041,AMPL_WIDTH),
conv_std_logic_vector(27042,AMPL_WIDTH),
conv_std_logic_vector(27044,AMPL_WIDTH),
conv_std_logic_vector(27046,AMPL_WIDTH),
conv_std_logic_vector(27048,AMPL_WIDTH),
conv_std_logic_vector(27049,AMPL_WIDTH),
conv_std_logic_vector(27051,AMPL_WIDTH),
conv_std_logic_vector(27053,AMPL_WIDTH),
conv_std_logic_vector(27055,AMPL_WIDTH),
conv_std_logic_vector(27057,AMPL_WIDTH),
conv_std_logic_vector(27058,AMPL_WIDTH),
conv_std_logic_vector(27060,AMPL_WIDTH),
conv_std_logic_vector(27062,AMPL_WIDTH),
conv_std_logic_vector(27064,AMPL_WIDTH),
conv_std_logic_vector(27065,AMPL_WIDTH),
conv_std_logic_vector(27067,AMPL_WIDTH),
conv_std_logic_vector(27069,AMPL_WIDTH),
conv_std_logic_vector(27071,AMPL_WIDTH),
conv_std_logic_vector(27073,AMPL_WIDTH),
conv_std_logic_vector(27074,AMPL_WIDTH),
conv_std_logic_vector(27076,AMPL_WIDTH),
conv_std_logic_vector(27078,AMPL_WIDTH),
conv_std_logic_vector(27080,AMPL_WIDTH),
conv_std_logic_vector(27081,AMPL_WIDTH),
conv_std_logic_vector(27083,AMPL_WIDTH),
conv_std_logic_vector(27085,AMPL_WIDTH),
conv_std_logic_vector(27087,AMPL_WIDTH),
conv_std_logic_vector(27088,AMPL_WIDTH),
conv_std_logic_vector(27090,AMPL_WIDTH),
conv_std_logic_vector(27092,AMPL_WIDTH),
conv_std_logic_vector(27094,AMPL_WIDTH),
conv_std_logic_vector(27096,AMPL_WIDTH),
conv_std_logic_vector(27097,AMPL_WIDTH),
conv_std_logic_vector(27099,AMPL_WIDTH),
conv_std_logic_vector(27101,AMPL_WIDTH),
conv_std_logic_vector(27103,AMPL_WIDTH),
conv_std_logic_vector(27104,AMPL_WIDTH),
conv_std_logic_vector(27106,AMPL_WIDTH),
conv_std_logic_vector(27108,AMPL_WIDTH),
conv_std_logic_vector(27110,AMPL_WIDTH),
conv_std_logic_vector(27111,AMPL_WIDTH),
conv_std_logic_vector(27113,AMPL_WIDTH),
conv_std_logic_vector(27115,AMPL_WIDTH),
conv_std_logic_vector(27117,AMPL_WIDTH),
conv_std_logic_vector(27118,AMPL_WIDTH),
conv_std_logic_vector(27120,AMPL_WIDTH),
conv_std_logic_vector(27122,AMPL_WIDTH),
conv_std_logic_vector(27124,AMPL_WIDTH),
conv_std_logic_vector(27126,AMPL_WIDTH),
conv_std_logic_vector(27127,AMPL_WIDTH),
conv_std_logic_vector(27129,AMPL_WIDTH),
conv_std_logic_vector(27131,AMPL_WIDTH),
conv_std_logic_vector(27133,AMPL_WIDTH),
conv_std_logic_vector(27134,AMPL_WIDTH),
conv_std_logic_vector(27136,AMPL_WIDTH),
conv_std_logic_vector(27138,AMPL_WIDTH),
conv_std_logic_vector(27140,AMPL_WIDTH),
conv_std_logic_vector(27141,AMPL_WIDTH),
conv_std_logic_vector(27143,AMPL_WIDTH),
conv_std_logic_vector(27145,AMPL_WIDTH),
conv_std_logic_vector(27147,AMPL_WIDTH),
conv_std_logic_vector(27148,AMPL_WIDTH),
conv_std_logic_vector(27150,AMPL_WIDTH),
conv_std_logic_vector(27152,AMPL_WIDTH),
conv_std_logic_vector(27154,AMPL_WIDTH),
conv_std_logic_vector(27155,AMPL_WIDTH),
conv_std_logic_vector(27157,AMPL_WIDTH),
conv_std_logic_vector(27159,AMPL_WIDTH),
conv_std_logic_vector(27161,AMPL_WIDTH),
conv_std_logic_vector(27162,AMPL_WIDTH),
conv_std_logic_vector(27164,AMPL_WIDTH),
conv_std_logic_vector(27166,AMPL_WIDTH),
conv_std_logic_vector(27168,AMPL_WIDTH),
conv_std_logic_vector(27169,AMPL_WIDTH),
conv_std_logic_vector(27171,AMPL_WIDTH),
conv_std_logic_vector(27173,AMPL_WIDTH),
conv_std_logic_vector(27175,AMPL_WIDTH),
conv_std_logic_vector(27177,AMPL_WIDTH),
conv_std_logic_vector(27178,AMPL_WIDTH),
conv_std_logic_vector(27180,AMPL_WIDTH),
conv_std_logic_vector(27182,AMPL_WIDTH),
conv_std_logic_vector(27184,AMPL_WIDTH),
conv_std_logic_vector(27185,AMPL_WIDTH),
conv_std_logic_vector(27187,AMPL_WIDTH),
conv_std_logic_vector(27189,AMPL_WIDTH),
conv_std_logic_vector(27191,AMPL_WIDTH),
conv_std_logic_vector(27192,AMPL_WIDTH),
conv_std_logic_vector(27194,AMPL_WIDTH),
conv_std_logic_vector(27196,AMPL_WIDTH),
conv_std_logic_vector(27198,AMPL_WIDTH),
conv_std_logic_vector(27199,AMPL_WIDTH),
conv_std_logic_vector(27201,AMPL_WIDTH),
conv_std_logic_vector(27203,AMPL_WIDTH),
conv_std_logic_vector(27205,AMPL_WIDTH),
conv_std_logic_vector(27206,AMPL_WIDTH),
conv_std_logic_vector(27208,AMPL_WIDTH),
conv_std_logic_vector(27210,AMPL_WIDTH),
conv_std_logic_vector(27212,AMPL_WIDTH),
conv_std_logic_vector(27213,AMPL_WIDTH),
conv_std_logic_vector(27215,AMPL_WIDTH),
conv_std_logic_vector(27217,AMPL_WIDTH),
conv_std_logic_vector(27219,AMPL_WIDTH),
conv_std_logic_vector(27220,AMPL_WIDTH),
conv_std_logic_vector(27222,AMPL_WIDTH),
conv_std_logic_vector(27224,AMPL_WIDTH),
conv_std_logic_vector(27226,AMPL_WIDTH),
conv_std_logic_vector(27227,AMPL_WIDTH),
conv_std_logic_vector(27229,AMPL_WIDTH),
conv_std_logic_vector(27231,AMPL_WIDTH),
conv_std_logic_vector(27233,AMPL_WIDTH),
conv_std_logic_vector(27234,AMPL_WIDTH),
conv_std_logic_vector(27236,AMPL_WIDTH),
conv_std_logic_vector(27238,AMPL_WIDTH),
conv_std_logic_vector(27240,AMPL_WIDTH),
conv_std_logic_vector(27241,AMPL_WIDTH),
conv_std_logic_vector(27243,AMPL_WIDTH),
conv_std_logic_vector(27245,AMPL_WIDTH),
conv_std_logic_vector(27247,AMPL_WIDTH),
conv_std_logic_vector(27248,AMPL_WIDTH),
conv_std_logic_vector(27250,AMPL_WIDTH),
conv_std_logic_vector(27252,AMPL_WIDTH),
conv_std_logic_vector(27253,AMPL_WIDTH),
conv_std_logic_vector(27255,AMPL_WIDTH),
conv_std_logic_vector(27257,AMPL_WIDTH),
conv_std_logic_vector(27259,AMPL_WIDTH),
conv_std_logic_vector(27260,AMPL_WIDTH),
conv_std_logic_vector(27262,AMPL_WIDTH),
conv_std_logic_vector(27264,AMPL_WIDTH),
conv_std_logic_vector(27266,AMPL_WIDTH),
conv_std_logic_vector(27267,AMPL_WIDTH),
conv_std_logic_vector(27269,AMPL_WIDTH),
conv_std_logic_vector(27271,AMPL_WIDTH),
conv_std_logic_vector(27273,AMPL_WIDTH),
conv_std_logic_vector(27274,AMPL_WIDTH),
conv_std_logic_vector(27276,AMPL_WIDTH),
conv_std_logic_vector(27278,AMPL_WIDTH),
conv_std_logic_vector(27280,AMPL_WIDTH),
conv_std_logic_vector(27281,AMPL_WIDTH),
conv_std_logic_vector(27283,AMPL_WIDTH),
conv_std_logic_vector(27285,AMPL_WIDTH),
conv_std_logic_vector(27287,AMPL_WIDTH),
conv_std_logic_vector(27288,AMPL_WIDTH),
conv_std_logic_vector(27290,AMPL_WIDTH),
conv_std_logic_vector(27292,AMPL_WIDTH),
conv_std_logic_vector(27294,AMPL_WIDTH),
conv_std_logic_vector(27295,AMPL_WIDTH),
conv_std_logic_vector(27297,AMPL_WIDTH),
conv_std_logic_vector(27299,AMPL_WIDTH),
conv_std_logic_vector(27300,AMPL_WIDTH),
conv_std_logic_vector(27302,AMPL_WIDTH),
conv_std_logic_vector(27304,AMPL_WIDTH),
conv_std_logic_vector(27306,AMPL_WIDTH),
conv_std_logic_vector(27307,AMPL_WIDTH),
conv_std_logic_vector(27309,AMPL_WIDTH),
conv_std_logic_vector(27311,AMPL_WIDTH),
conv_std_logic_vector(27313,AMPL_WIDTH),
conv_std_logic_vector(27314,AMPL_WIDTH),
conv_std_logic_vector(27316,AMPL_WIDTH),
conv_std_logic_vector(27318,AMPL_WIDTH),
conv_std_logic_vector(27320,AMPL_WIDTH),
conv_std_logic_vector(27321,AMPL_WIDTH),
conv_std_logic_vector(27323,AMPL_WIDTH),
conv_std_logic_vector(27325,AMPL_WIDTH),
conv_std_logic_vector(27327,AMPL_WIDTH),
conv_std_logic_vector(27328,AMPL_WIDTH),
conv_std_logic_vector(27330,AMPL_WIDTH),
conv_std_logic_vector(27332,AMPL_WIDTH),
conv_std_logic_vector(27333,AMPL_WIDTH),
conv_std_logic_vector(27335,AMPL_WIDTH),
conv_std_logic_vector(27337,AMPL_WIDTH),
conv_std_logic_vector(27339,AMPL_WIDTH),
conv_std_logic_vector(27340,AMPL_WIDTH),
conv_std_logic_vector(27342,AMPL_WIDTH),
conv_std_logic_vector(27344,AMPL_WIDTH),
conv_std_logic_vector(27346,AMPL_WIDTH),
conv_std_logic_vector(27347,AMPL_WIDTH),
conv_std_logic_vector(27349,AMPL_WIDTH),
conv_std_logic_vector(27351,AMPL_WIDTH),
conv_std_logic_vector(27352,AMPL_WIDTH),
conv_std_logic_vector(27354,AMPL_WIDTH),
conv_std_logic_vector(27356,AMPL_WIDTH),
conv_std_logic_vector(27358,AMPL_WIDTH),
conv_std_logic_vector(27359,AMPL_WIDTH),
conv_std_logic_vector(27361,AMPL_WIDTH),
conv_std_logic_vector(27363,AMPL_WIDTH),
conv_std_logic_vector(27365,AMPL_WIDTH),
conv_std_logic_vector(27366,AMPL_WIDTH),
conv_std_logic_vector(27368,AMPL_WIDTH),
conv_std_logic_vector(27370,AMPL_WIDTH),
conv_std_logic_vector(27372,AMPL_WIDTH),
conv_std_logic_vector(27373,AMPL_WIDTH),
conv_std_logic_vector(27375,AMPL_WIDTH),
conv_std_logic_vector(27377,AMPL_WIDTH),
conv_std_logic_vector(27378,AMPL_WIDTH),
conv_std_logic_vector(27380,AMPL_WIDTH),
conv_std_logic_vector(27382,AMPL_WIDTH),
conv_std_logic_vector(27384,AMPL_WIDTH),
conv_std_logic_vector(27385,AMPL_WIDTH),
conv_std_logic_vector(27387,AMPL_WIDTH),
conv_std_logic_vector(27389,AMPL_WIDTH),
conv_std_logic_vector(27390,AMPL_WIDTH),
conv_std_logic_vector(27392,AMPL_WIDTH),
conv_std_logic_vector(27394,AMPL_WIDTH),
conv_std_logic_vector(27396,AMPL_WIDTH),
conv_std_logic_vector(27397,AMPL_WIDTH),
conv_std_logic_vector(27399,AMPL_WIDTH),
conv_std_logic_vector(27401,AMPL_WIDTH),
conv_std_logic_vector(27403,AMPL_WIDTH),
conv_std_logic_vector(27404,AMPL_WIDTH),
conv_std_logic_vector(27406,AMPL_WIDTH),
conv_std_logic_vector(27408,AMPL_WIDTH),
conv_std_logic_vector(27409,AMPL_WIDTH),
conv_std_logic_vector(27411,AMPL_WIDTH),
conv_std_logic_vector(27413,AMPL_WIDTH),
conv_std_logic_vector(27415,AMPL_WIDTH),
conv_std_logic_vector(27416,AMPL_WIDTH),
conv_std_logic_vector(27418,AMPL_WIDTH),
conv_std_logic_vector(27420,AMPL_WIDTH),
conv_std_logic_vector(27421,AMPL_WIDTH),
conv_std_logic_vector(27423,AMPL_WIDTH),
conv_std_logic_vector(27425,AMPL_WIDTH),
conv_std_logic_vector(27427,AMPL_WIDTH),
conv_std_logic_vector(27428,AMPL_WIDTH),
conv_std_logic_vector(27430,AMPL_WIDTH),
conv_std_logic_vector(27432,AMPL_WIDTH),
conv_std_logic_vector(27434,AMPL_WIDTH),
conv_std_logic_vector(27435,AMPL_WIDTH),
conv_std_logic_vector(27437,AMPL_WIDTH),
conv_std_logic_vector(27439,AMPL_WIDTH),
conv_std_logic_vector(27440,AMPL_WIDTH),
conv_std_logic_vector(27442,AMPL_WIDTH),
conv_std_logic_vector(27444,AMPL_WIDTH),
conv_std_logic_vector(27446,AMPL_WIDTH),
conv_std_logic_vector(27447,AMPL_WIDTH),
conv_std_logic_vector(27449,AMPL_WIDTH),
conv_std_logic_vector(27451,AMPL_WIDTH),
conv_std_logic_vector(27452,AMPL_WIDTH),
conv_std_logic_vector(27454,AMPL_WIDTH),
conv_std_logic_vector(27456,AMPL_WIDTH),
conv_std_logic_vector(27458,AMPL_WIDTH),
conv_std_logic_vector(27459,AMPL_WIDTH),
conv_std_logic_vector(27461,AMPL_WIDTH),
conv_std_logic_vector(27463,AMPL_WIDTH),
conv_std_logic_vector(27464,AMPL_WIDTH),
conv_std_logic_vector(27466,AMPL_WIDTH),
conv_std_logic_vector(27468,AMPL_WIDTH),
conv_std_logic_vector(27470,AMPL_WIDTH),
conv_std_logic_vector(27471,AMPL_WIDTH),
conv_std_logic_vector(27473,AMPL_WIDTH),
conv_std_logic_vector(27475,AMPL_WIDTH),
conv_std_logic_vector(27476,AMPL_WIDTH),
conv_std_logic_vector(27478,AMPL_WIDTH),
conv_std_logic_vector(27480,AMPL_WIDTH),
conv_std_logic_vector(27482,AMPL_WIDTH),
conv_std_logic_vector(27483,AMPL_WIDTH),
conv_std_logic_vector(27485,AMPL_WIDTH),
conv_std_logic_vector(27487,AMPL_WIDTH),
conv_std_logic_vector(27488,AMPL_WIDTH),
conv_std_logic_vector(27490,AMPL_WIDTH),
conv_std_logic_vector(27492,AMPL_WIDTH),
conv_std_logic_vector(27493,AMPL_WIDTH),
conv_std_logic_vector(27495,AMPL_WIDTH),
conv_std_logic_vector(27497,AMPL_WIDTH),
conv_std_logic_vector(27499,AMPL_WIDTH),
conv_std_logic_vector(27500,AMPL_WIDTH),
conv_std_logic_vector(27502,AMPL_WIDTH),
conv_std_logic_vector(27504,AMPL_WIDTH),
conv_std_logic_vector(27505,AMPL_WIDTH),
conv_std_logic_vector(27507,AMPL_WIDTH),
conv_std_logic_vector(27509,AMPL_WIDTH),
conv_std_logic_vector(27511,AMPL_WIDTH),
conv_std_logic_vector(27512,AMPL_WIDTH),
conv_std_logic_vector(27514,AMPL_WIDTH),
conv_std_logic_vector(27516,AMPL_WIDTH),
conv_std_logic_vector(27517,AMPL_WIDTH),
conv_std_logic_vector(27519,AMPL_WIDTH),
conv_std_logic_vector(27521,AMPL_WIDTH),
conv_std_logic_vector(27523,AMPL_WIDTH),
conv_std_logic_vector(27524,AMPL_WIDTH),
conv_std_logic_vector(27526,AMPL_WIDTH),
conv_std_logic_vector(27528,AMPL_WIDTH),
conv_std_logic_vector(27529,AMPL_WIDTH),
conv_std_logic_vector(27531,AMPL_WIDTH),
conv_std_logic_vector(27533,AMPL_WIDTH),
conv_std_logic_vector(27534,AMPL_WIDTH),
conv_std_logic_vector(27536,AMPL_WIDTH),
conv_std_logic_vector(27538,AMPL_WIDTH),
conv_std_logic_vector(27540,AMPL_WIDTH),
conv_std_logic_vector(27541,AMPL_WIDTH),
conv_std_logic_vector(27543,AMPL_WIDTH),
conv_std_logic_vector(27545,AMPL_WIDTH),
conv_std_logic_vector(27546,AMPL_WIDTH),
conv_std_logic_vector(27548,AMPL_WIDTH),
conv_std_logic_vector(27550,AMPL_WIDTH),
conv_std_logic_vector(27551,AMPL_WIDTH),
conv_std_logic_vector(27553,AMPL_WIDTH),
conv_std_logic_vector(27555,AMPL_WIDTH),
conv_std_logic_vector(27557,AMPL_WIDTH),
conv_std_logic_vector(27558,AMPL_WIDTH),
conv_std_logic_vector(27560,AMPL_WIDTH),
conv_std_logic_vector(27562,AMPL_WIDTH),
conv_std_logic_vector(27563,AMPL_WIDTH),
conv_std_logic_vector(27565,AMPL_WIDTH),
conv_std_logic_vector(27567,AMPL_WIDTH),
conv_std_logic_vector(27568,AMPL_WIDTH),
conv_std_logic_vector(27570,AMPL_WIDTH),
conv_std_logic_vector(27572,AMPL_WIDTH),
conv_std_logic_vector(27574,AMPL_WIDTH),
conv_std_logic_vector(27575,AMPL_WIDTH),
conv_std_logic_vector(27577,AMPL_WIDTH),
conv_std_logic_vector(27579,AMPL_WIDTH),
conv_std_logic_vector(27580,AMPL_WIDTH),
conv_std_logic_vector(27582,AMPL_WIDTH),
conv_std_logic_vector(27584,AMPL_WIDTH),
conv_std_logic_vector(27585,AMPL_WIDTH),
conv_std_logic_vector(27587,AMPL_WIDTH),
conv_std_logic_vector(27589,AMPL_WIDTH),
conv_std_logic_vector(27590,AMPL_WIDTH),
conv_std_logic_vector(27592,AMPL_WIDTH),
conv_std_logic_vector(27594,AMPL_WIDTH),
conv_std_logic_vector(27596,AMPL_WIDTH),
conv_std_logic_vector(27597,AMPL_WIDTH),
conv_std_logic_vector(27599,AMPL_WIDTH),
conv_std_logic_vector(27601,AMPL_WIDTH),
conv_std_logic_vector(27602,AMPL_WIDTH),
conv_std_logic_vector(27604,AMPL_WIDTH),
conv_std_logic_vector(27606,AMPL_WIDTH),
conv_std_logic_vector(27607,AMPL_WIDTH),
conv_std_logic_vector(27609,AMPL_WIDTH),
conv_std_logic_vector(27611,AMPL_WIDTH),
conv_std_logic_vector(27613,AMPL_WIDTH),
conv_std_logic_vector(27614,AMPL_WIDTH),
conv_std_logic_vector(27616,AMPL_WIDTH),
conv_std_logic_vector(27618,AMPL_WIDTH),
conv_std_logic_vector(27619,AMPL_WIDTH),
conv_std_logic_vector(27621,AMPL_WIDTH),
conv_std_logic_vector(27623,AMPL_WIDTH),
conv_std_logic_vector(27624,AMPL_WIDTH),
conv_std_logic_vector(27626,AMPL_WIDTH),
conv_std_logic_vector(27628,AMPL_WIDTH),
conv_std_logic_vector(27629,AMPL_WIDTH),
conv_std_logic_vector(27631,AMPL_WIDTH),
conv_std_logic_vector(27633,AMPL_WIDTH),
conv_std_logic_vector(27634,AMPL_WIDTH),
conv_std_logic_vector(27636,AMPL_WIDTH),
conv_std_logic_vector(27638,AMPL_WIDTH),
conv_std_logic_vector(27640,AMPL_WIDTH),
conv_std_logic_vector(27641,AMPL_WIDTH),
conv_std_logic_vector(27643,AMPL_WIDTH),
conv_std_logic_vector(27645,AMPL_WIDTH),
conv_std_logic_vector(27646,AMPL_WIDTH),
conv_std_logic_vector(27648,AMPL_WIDTH),
conv_std_logic_vector(27650,AMPL_WIDTH),
conv_std_logic_vector(27651,AMPL_WIDTH),
conv_std_logic_vector(27653,AMPL_WIDTH),
conv_std_logic_vector(27655,AMPL_WIDTH),
conv_std_logic_vector(27656,AMPL_WIDTH),
conv_std_logic_vector(27658,AMPL_WIDTH),
conv_std_logic_vector(27660,AMPL_WIDTH),
conv_std_logic_vector(27661,AMPL_WIDTH),
conv_std_logic_vector(27663,AMPL_WIDTH),
conv_std_logic_vector(27665,AMPL_WIDTH),
conv_std_logic_vector(27666,AMPL_WIDTH),
conv_std_logic_vector(27668,AMPL_WIDTH),
conv_std_logic_vector(27670,AMPL_WIDTH),
conv_std_logic_vector(27672,AMPL_WIDTH),
conv_std_logic_vector(27673,AMPL_WIDTH),
conv_std_logic_vector(27675,AMPL_WIDTH),
conv_std_logic_vector(27677,AMPL_WIDTH),
conv_std_logic_vector(27678,AMPL_WIDTH),
conv_std_logic_vector(27680,AMPL_WIDTH),
conv_std_logic_vector(27682,AMPL_WIDTH),
conv_std_logic_vector(27683,AMPL_WIDTH),
conv_std_logic_vector(27685,AMPL_WIDTH),
conv_std_logic_vector(27687,AMPL_WIDTH),
conv_std_logic_vector(27688,AMPL_WIDTH),
conv_std_logic_vector(27690,AMPL_WIDTH),
conv_std_logic_vector(27692,AMPL_WIDTH),
conv_std_logic_vector(27693,AMPL_WIDTH),
conv_std_logic_vector(27695,AMPL_WIDTH),
conv_std_logic_vector(27697,AMPL_WIDTH),
conv_std_logic_vector(27698,AMPL_WIDTH),
conv_std_logic_vector(27700,AMPL_WIDTH),
conv_std_logic_vector(27702,AMPL_WIDTH),
conv_std_logic_vector(27703,AMPL_WIDTH),
conv_std_logic_vector(27705,AMPL_WIDTH),
conv_std_logic_vector(27707,AMPL_WIDTH),
conv_std_logic_vector(27708,AMPL_WIDTH),
conv_std_logic_vector(27710,AMPL_WIDTH),
conv_std_logic_vector(27712,AMPL_WIDTH),
conv_std_logic_vector(27714,AMPL_WIDTH),
conv_std_logic_vector(27715,AMPL_WIDTH),
conv_std_logic_vector(27717,AMPL_WIDTH),
conv_std_logic_vector(27719,AMPL_WIDTH),
conv_std_logic_vector(27720,AMPL_WIDTH),
conv_std_logic_vector(27722,AMPL_WIDTH),
conv_std_logic_vector(27724,AMPL_WIDTH),
conv_std_logic_vector(27725,AMPL_WIDTH),
conv_std_logic_vector(27727,AMPL_WIDTH),
conv_std_logic_vector(27729,AMPL_WIDTH),
conv_std_logic_vector(27730,AMPL_WIDTH),
conv_std_logic_vector(27732,AMPL_WIDTH),
conv_std_logic_vector(27734,AMPL_WIDTH),
conv_std_logic_vector(27735,AMPL_WIDTH),
conv_std_logic_vector(27737,AMPL_WIDTH),
conv_std_logic_vector(27739,AMPL_WIDTH),
conv_std_logic_vector(27740,AMPL_WIDTH),
conv_std_logic_vector(27742,AMPL_WIDTH),
conv_std_logic_vector(27744,AMPL_WIDTH),
conv_std_logic_vector(27745,AMPL_WIDTH),
conv_std_logic_vector(27747,AMPL_WIDTH),
conv_std_logic_vector(27749,AMPL_WIDTH),
conv_std_logic_vector(27750,AMPL_WIDTH),
conv_std_logic_vector(27752,AMPL_WIDTH),
conv_std_logic_vector(27754,AMPL_WIDTH),
conv_std_logic_vector(27755,AMPL_WIDTH),
conv_std_logic_vector(27757,AMPL_WIDTH),
conv_std_logic_vector(27759,AMPL_WIDTH),
conv_std_logic_vector(27760,AMPL_WIDTH),
conv_std_logic_vector(27762,AMPL_WIDTH),
conv_std_logic_vector(27764,AMPL_WIDTH),
conv_std_logic_vector(27765,AMPL_WIDTH),
conv_std_logic_vector(27767,AMPL_WIDTH),
conv_std_logic_vector(27769,AMPL_WIDTH),
conv_std_logic_vector(27770,AMPL_WIDTH),
conv_std_logic_vector(27772,AMPL_WIDTH),
conv_std_logic_vector(27774,AMPL_WIDTH),
conv_std_logic_vector(27775,AMPL_WIDTH),
conv_std_logic_vector(27777,AMPL_WIDTH),
conv_std_logic_vector(27779,AMPL_WIDTH),
conv_std_logic_vector(27780,AMPL_WIDTH),
conv_std_logic_vector(27782,AMPL_WIDTH),
conv_std_logic_vector(27784,AMPL_WIDTH),
conv_std_logic_vector(27785,AMPL_WIDTH),
conv_std_logic_vector(27787,AMPL_WIDTH),
conv_std_logic_vector(27789,AMPL_WIDTH),
conv_std_logic_vector(27790,AMPL_WIDTH),
conv_std_logic_vector(27792,AMPL_WIDTH),
conv_std_logic_vector(27794,AMPL_WIDTH),
conv_std_logic_vector(27795,AMPL_WIDTH),
conv_std_logic_vector(27797,AMPL_WIDTH),
conv_std_logic_vector(27799,AMPL_WIDTH),
conv_std_logic_vector(27800,AMPL_WIDTH),
conv_std_logic_vector(27802,AMPL_WIDTH),
conv_std_logic_vector(27804,AMPL_WIDTH),
conv_std_logic_vector(27805,AMPL_WIDTH),
conv_std_logic_vector(27807,AMPL_WIDTH),
conv_std_logic_vector(27809,AMPL_WIDTH),
conv_std_logic_vector(27810,AMPL_WIDTH),
conv_std_logic_vector(27812,AMPL_WIDTH),
conv_std_logic_vector(27814,AMPL_WIDTH),
conv_std_logic_vector(27815,AMPL_WIDTH),
conv_std_logic_vector(27817,AMPL_WIDTH),
conv_std_logic_vector(27819,AMPL_WIDTH),
conv_std_logic_vector(27820,AMPL_WIDTH),
conv_std_logic_vector(27822,AMPL_WIDTH),
conv_std_logic_vector(27824,AMPL_WIDTH),
conv_std_logic_vector(27825,AMPL_WIDTH),
conv_std_logic_vector(27827,AMPL_WIDTH),
conv_std_logic_vector(27829,AMPL_WIDTH),
conv_std_logic_vector(27830,AMPL_WIDTH),
conv_std_logic_vector(27832,AMPL_WIDTH),
conv_std_logic_vector(27834,AMPL_WIDTH),
conv_std_logic_vector(27835,AMPL_WIDTH),
conv_std_logic_vector(27837,AMPL_WIDTH),
conv_std_logic_vector(27839,AMPL_WIDTH),
conv_std_logic_vector(27840,AMPL_WIDTH),
conv_std_logic_vector(27842,AMPL_WIDTH),
conv_std_logic_vector(27843,AMPL_WIDTH),
conv_std_logic_vector(27845,AMPL_WIDTH),
conv_std_logic_vector(27847,AMPL_WIDTH),
conv_std_logic_vector(27848,AMPL_WIDTH),
conv_std_logic_vector(27850,AMPL_WIDTH),
conv_std_logic_vector(27852,AMPL_WIDTH),
conv_std_logic_vector(27853,AMPL_WIDTH),
conv_std_logic_vector(27855,AMPL_WIDTH),
conv_std_logic_vector(27857,AMPL_WIDTH),
conv_std_logic_vector(27858,AMPL_WIDTH),
conv_std_logic_vector(27860,AMPL_WIDTH),
conv_std_logic_vector(27862,AMPL_WIDTH),
conv_std_logic_vector(27863,AMPL_WIDTH),
conv_std_logic_vector(27865,AMPL_WIDTH),
conv_std_logic_vector(27867,AMPL_WIDTH),
conv_std_logic_vector(27868,AMPL_WIDTH),
conv_std_logic_vector(27870,AMPL_WIDTH),
conv_std_logic_vector(27872,AMPL_WIDTH),
conv_std_logic_vector(27873,AMPL_WIDTH),
conv_std_logic_vector(27875,AMPL_WIDTH),
conv_std_logic_vector(27877,AMPL_WIDTH),
conv_std_logic_vector(27878,AMPL_WIDTH),
conv_std_logic_vector(27880,AMPL_WIDTH),
conv_std_logic_vector(27882,AMPL_WIDTH),
conv_std_logic_vector(27883,AMPL_WIDTH),
conv_std_logic_vector(27885,AMPL_WIDTH),
conv_std_logic_vector(27886,AMPL_WIDTH),
conv_std_logic_vector(27888,AMPL_WIDTH),
conv_std_logic_vector(27890,AMPL_WIDTH),
conv_std_logic_vector(27891,AMPL_WIDTH),
conv_std_logic_vector(27893,AMPL_WIDTH),
conv_std_logic_vector(27895,AMPL_WIDTH),
conv_std_logic_vector(27896,AMPL_WIDTH),
conv_std_logic_vector(27898,AMPL_WIDTH),
conv_std_logic_vector(27900,AMPL_WIDTH),
conv_std_logic_vector(27901,AMPL_WIDTH),
conv_std_logic_vector(27903,AMPL_WIDTH),
conv_std_logic_vector(27905,AMPL_WIDTH),
conv_std_logic_vector(27906,AMPL_WIDTH),
conv_std_logic_vector(27908,AMPL_WIDTH),
conv_std_logic_vector(27910,AMPL_WIDTH),
conv_std_logic_vector(27911,AMPL_WIDTH),
conv_std_logic_vector(27913,AMPL_WIDTH),
conv_std_logic_vector(27914,AMPL_WIDTH),
conv_std_logic_vector(27916,AMPL_WIDTH),
conv_std_logic_vector(27918,AMPL_WIDTH),
conv_std_logic_vector(27919,AMPL_WIDTH),
conv_std_logic_vector(27921,AMPL_WIDTH),
conv_std_logic_vector(27923,AMPL_WIDTH),
conv_std_logic_vector(27924,AMPL_WIDTH),
conv_std_logic_vector(27926,AMPL_WIDTH),
conv_std_logic_vector(27928,AMPL_WIDTH),
conv_std_logic_vector(27929,AMPL_WIDTH),
conv_std_logic_vector(27931,AMPL_WIDTH),
conv_std_logic_vector(27933,AMPL_WIDTH),
conv_std_logic_vector(27934,AMPL_WIDTH),
conv_std_logic_vector(27936,AMPL_WIDTH),
conv_std_logic_vector(27937,AMPL_WIDTH),
conv_std_logic_vector(27939,AMPL_WIDTH),
conv_std_logic_vector(27941,AMPL_WIDTH),
conv_std_logic_vector(27942,AMPL_WIDTH),
conv_std_logic_vector(27944,AMPL_WIDTH),
conv_std_logic_vector(27946,AMPL_WIDTH),
conv_std_logic_vector(27947,AMPL_WIDTH),
conv_std_logic_vector(27949,AMPL_WIDTH),
conv_std_logic_vector(27951,AMPL_WIDTH),
conv_std_logic_vector(27952,AMPL_WIDTH),
conv_std_logic_vector(27954,AMPL_WIDTH),
conv_std_logic_vector(27956,AMPL_WIDTH),
conv_std_logic_vector(27957,AMPL_WIDTH),
conv_std_logic_vector(27959,AMPL_WIDTH),
conv_std_logic_vector(27960,AMPL_WIDTH),
conv_std_logic_vector(27962,AMPL_WIDTH),
conv_std_logic_vector(27964,AMPL_WIDTH),
conv_std_logic_vector(27965,AMPL_WIDTH),
conv_std_logic_vector(27967,AMPL_WIDTH),
conv_std_logic_vector(27969,AMPL_WIDTH),
conv_std_logic_vector(27970,AMPL_WIDTH),
conv_std_logic_vector(27972,AMPL_WIDTH),
conv_std_logic_vector(27974,AMPL_WIDTH),
conv_std_logic_vector(27975,AMPL_WIDTH),
conv_std_logic_vector(27977,AMPL_WIDTH),
conv_std_logic_vector(27978,AMPL_WIDTH),
conv_std_logic_vector(27980,AMPL_WIDTH),
conv_std_logic_vector(27982,AMPL_WIDTH),
conv_std_logic_vector(27983,AMPL_WIDTH),
conv_std_logic_vector(27985,AMPL_WIDTH),
conv_std_logic_vector(27987,AMPL_WIDTH),
conv_std_logic_vector(27988,AMPL_WIDTH),
conv_std_logic_vector(27990,AMPL_WIDTH),
conv_std_logic_vector(27992,AMPL_WIDTH),
conv_std_logic_vector(27993,AMPL_WIDTH),
conv_std_logic_vector(27995,AMPL_WIDTH),
conv_std_logic_vector(27996,AMPL_WIDTH),
conv_std_logic_vector(27998,AMPL_WIDTH),
conv_std_logic_vector(28000,AMPL_WIDTH),
conv_std_logic_vector(28001,AMPL_WIDTH),
conv_std_logic_vector(28003,AMPL_WIDTH),
conv_std_logic_vector(28005,AMPL_WIDTH),
conv_std_logic_vector(28006,AMPL_WIDTH),
conv_std_logic_vector(28008,AMPL_WIDTH),
conv_std_logic_vector(28009,AMPL_WIDTH),
conv_std_logic_vector(28011,AMPL_WIDTH),
conv_std_logic_vector(28013,AMPL_WIDTH),
conv_std_logic_vector(28014,AMPL_WIDTH),
conv_std_logic_vector(28016,AMPL_WIDTH),
conv_std_logic_vector(28018,AMPL_WIDTH),
conv_std_logic_vector(28019,AMPL_WIDTH),
conv_std_logic_vector(28021,AMPL_WIDTH),
conv_std_logic_vector(28022,AMPL_WIDTH),
conv_std_logic_vector(28024,AMPL_WIDTH),
conv_std_logic_vector(28026,AMPL_WIDTH),
conv_std_logic_vector(28027,AMPL_WIDTH),
conv_std_logic_vector(28029,AMPL_WIDTH),
conv_std_logic_vector(28031,AMPL_WIDTH),
conv_std_logic_vector(28032,AMPL_WIDTH),
conv_std_logic_vector(28034,AMPL_WIDTH),
conv_std_logic_vector(28036,AMPL_WIDTH),
conv_std_logic_vector(28037,AMPL_WIDTH),
conv_std_logic_vector(28039,AMPL_WIDTH),
conv_std_logic_vector(28040,AMPL_WIDTH),
conv_std_logic_vector(28042,AMPL_WIDTH),
conv_std_logic_vector(28044,AMPL_WIDTH),
conv_std_logic_vector(28045,AMPL_WIDTH),
conv_std_logic_vector(28047,AMPL_WIDTH),
conv_std_logic_vector(28049,AMPL_WIDTH),
conv_std_logic_vector(28050,AMPL_WIDTH),
conv_std_logic_vector(28052,AMPL_WIDTH),
conv_std_logic_vector(28053,AMPL_WIDTH),
conv_std_logic_vector(28055,AMPL_WIDTH),
conv_std_logic_vector(28057,AMPL_WIDTH),
conv_std_logic_vector(28058,AMPL_WIDTH),
conv_std_logic_vector(28060,AMPL_WIDTH),
conv_std_logic_vector(28061,AMPL_WIDTH),
conv_std_logic_vector(28063,AMPL_WIDTH),
conv_std_logic_vector(28065,AMPL_WIDTH),
conv_std_logic_vector(28066,AMPL_WIDTH),
conv_std_logic_vector(28068,AMPL_WIDTH),
conv_std_logic_vector(28070,AMPL_WIDTH),
conv_std_logic_vector(28071,AMPL_WIDTH),
conv_std_logic_vector(28073,AMPL_WIDTH),
conv_std_logic_vector(28074,AMPL_WIDTH),
conv_std_logic_vector(28076,AMPL_WIDTH),
conv_std_logic_vector(28078,AMPL_WIDTH),
conv_std_logic_vector(28079,AMPL_WIDTH),
conv_std_logic_vector(28081,AMPL_WIDTH),
conv_std_logic_vector(28083,AMPL_WIDTH),
conv_std_logic_vector(28084,AMPL_WIDTH),
conv_std_logic_vector(28086,AMPL_WIDTH),
conv_std_logic_vector(28087,AMPL_WIDTH),
conv_std_logic_vector(28089,AMPL_WIDTH),
conv_std_logic_vector(28091,AMPL_WIDTH),
conv_std_logic_vector(28092,AMPL_WIDTH),
conv_std_logic_vector(28094,AMPL_WIDTH),
conv_std_logic_vector(28095,AMPL_WIDTH),
conv_std_logic_vector(28097,AMPL_WIDTH),
conv_std_logic_vector(28099,AMPL_WIDTH),
conv_std_logic_vector(28100,AMPL_WIDTH),
conv_std_logic_vector(28102,AMPL_WIDTH),
conv_std_logic_vector(28104,AMPL_WIDTH),
conv_std_logic_vector(28105,AMPL_WIDTH),
conv_std_logic_vector(28107,AMPL_WIDTH),
conv_std_logic_vector(28108,AMPL_WIDTH),
conv_std_logic_vector(28110,AMPL_WIDTH),
conv_std_logic_vector(28112,AMPL_WIDTH),
conv_std_logic_vector(28113,AMPL_WIDTH),
conv_std_logic_vector(28115,AMPL_WIDTH),
conv_std_logic_vector(28116,AMPL_WIDTH),
conv_std_logic_vector(28118,AMPL_WIDTH),
conv_std_logic_vector(28120,AMPL_WIDTH),
conv_std_logic_vector(28121,AMPL_WIDTH),
conv_std_logic_vector(28123,AMPL_WIDTH),
conv_std_logic_vector(28125,AMPL_WIDTH),
conv_std_logic_vector(28126,AMPL_WIDTH),
conv_std_logic_vector(28128,AMPL_WIDTH),
conv_std_logic_vector(28129,AMPL_WIDTH),
conv_std_logic_vector(28131,AMPL_WIDTH),
conv_std_logic_vector(28133,AMPL_WIDTH),
conv_std_logic_vector(28134,AMPL_WIDTH),
conv_std_logic_vector(28136,AMPL_WIDTH),
conv_std_logic_vector(28137,AMPL_WIDTH),
conv_std_logic_vector(28139,AMPL_WIDTH),
conv_std_logic_vector(28141,AMPL_WIDTH),
conv_std_logic_vector(28142,AMPL_WIDTH),
conv_std_logic_vector(28144,AMPL_WIDTH),
conv_std_logic_vector(28145,AMPL_WIDTH),
conv_std_logic_vector(28147,AMPL_WIDTH),
conv_std_logic_vector(28149,AMPL_WIDTH),
conv_std_logic_vector(28150,AMPL_WIDTH),
conv_std_logic_vector(28152,AMPL_WIDTH),
conv_std_logic_vector(28154,AMPL_WIDTH),
conv_std_logic_vector(28155,AMPL_WIDTH),
conv_std_logic_vector(28157,AMPL_WIDTH),
conv_std_logic_vector(28158,AMPL_WIDTH),
conv_std_logic_vector(28160,AMPL_WIDTH),
conv_std_logic_vector(28162,AMPL_WIDTH),
conv_std_logic_vector(28163,AMPL_WIDTH),
conv_std_logic_vector(28165,AMPL_WIDTH),
conv_std_logic_vector(28166,AMPL_WIDTH),
conv_std_logic_vector(28168,AMPL_WIDTH),
conv_std_logic_vector(28170,AMPL_WIDTH),
conv_std_logic_vector(28171,AMPL_WIDTH),
conv_std_logic_vector(28173,AMPL_WIDTH),
conv_std_logic_vector(28174,AMPL_WIDTH),
conv_std_logic_vector(28176,AMPL_WIDTH),
conv_std_logic_vector(28178,AMPL_WIDTH),
conv_std_logic_vector(28179,AMPL_WIDTH),
conv_std_logic_vector(28181,AMPL_WIDTH),
conv_std_logic_vector(28182,AMPL_WIDTH),
conv_std_logic_vector(28184,AMPL_WIDTH),
conv_std_logic_vector(28186,AMPL_WIDTH),
conv_std_logic_vector(28187,AMPL_WIDTH),
conv_std_logic_vector(28189,AMPL_WIDTH),
conv_std_logic_vector(28190,AMPL_WIDTH),
conv_std_logic_vector(28192,AMPL_WIDTH),
conv_std_logic_vector(28194,AMPL_WIDTH),
conv_std_logic_vector(28195,AMPL_WIDTH),
conv_std_logic_vector(28197,AMPL_WIDTH),
conv_std_logic_vector(28198,AMPL_WIDTH),
conv_std_logic_vector(28200,AMPL_WIDTH),
conv_std_logic_vector(28202,AMPL_WIDTH),
conv_std_logic_vector(28203,AMPL_WIDTH),
conv_std_logic_vector(28205,AMPL_WIDTH),
conv_std_logic_vector(28206,AMPL_WIDTH),
conv_std_logic_vector(28208,AMPL_WIDTH),
conv_std_logic_vector(28210,AMPL_WIDTH),
conv_std_logic_vector(28211,AMPL_WIDTH),
conv_std_logic_vector(28213,AMPL_WIDTH),
conv_std_logic_vector(28214,AMPL_WIDTH),
conv_std_logic_vector(28216,AMPL_WIDTH),
conv_std_logic_vector(28218,AMPL_WIDTH),
conv_std_logic_vector(28219,AMPL_WIDTH),
conv_std_logic_vector(28221,AMPL_WIDTH),
conv_std_logic_vector(28222,AMPL_WIDTH),
conv_std_logic_vector(28224,AMPL_WIDTH),
conv_std_logic_vector(28226,AMPL_WIDTH),
conv_std_logic_vector(28227,AMPL_WIDTH),
conv_std_logic_vector(28229,AMPL_WIDTH),
conv_std_logic_vector(28230,AMPL_WIDTH),
conv_std_logic_vector(28232,AMPL_WIDTH),
conv_std_logic_vector(28234,AMPL_WIDTH),
conv_std_logic_vector(28235,AMPL_WIDTH),
conv_std_logic_vector(28237,AMPL_WIDTH),
conv_std_logic_vector(28238,AMPL_WIDTH),
conv_std_logic_vector(28240,AMPL_WIDTH),
conv_std_logic_vector(28242,AMPL_WIDTH),
conv_std_logic_vector(28243,AMPL_WIDTH),
conv_std_logic_vector(28245,AMPL_WIDTH),
conv_std_logic_vector(28246,AMPL_WIDTH),
conv_std_logic_vector(28248,AMPL_WIDTH),
conv_std_logic_vector(28249,AMPL_WIDTH),
conv_std_logic_vector(28251,AMPL_WIDTH),
conv_std_logic_vector(28253,AMPL_WIDTH),
conv_std_logic_vector(28254,AMPL_WIDTH),
conv_std_logic_vector(28256,AMPL_WIDTH),
conv_std_logic_vector(28257,AMPL_WIDTH),
conv_std_logic_vector(28259,AMPL_WIDTH),
conv_std_logic_vector(28261,AMPL_WIDTH),
conv_std_logic_vector(28262,AMPL_WIDTH),
conv_std_logic_vector(28264,AMPL_WIDTH),
conv_std_logic_vector(28265,AMPL_WIDTH),
conv_std_logic_vector(28267,AMPL_WIDTH),
conv_std_logic_vector(28269,AMPL_WIDTH),
conv_std_logic_vector(28270,AMPL_WIDTH),
conv_std_logic_vector(28272,AMPL_WIDTH),
conv_std_logic_vector(28273,AMPL_WIDTH),
conv_std_logic_vector(28275,AMPL_WIDTH),
conv_std_logic_vector(28277,AMPL_WIDTH),
conv_std_logic_vector(28278,AMPL_WIDTH),
conv_std_logic_vector(28280,AMPL_WIDTH),
conv_std_logic_vector(28281,AMPL_WIDTH),
conv_std_logic_vector(28283,AMPL_WIDTH),
conv_std_logic_vector(28284,AMPL_WIDTH),
conv_std_logic_vector(28286,AMPL_WIDTH),
conv_std_logic_vector(28288,AMPL_WIDTH),
conv_std_logic_vector(28289,AMPL_WIDTH),
conv_std_logic_vector(28291,AMPL_WIDTH),
conv_std_logic_vector(28292,AMPL_WIDTH),
conv_std_logic_vector(28294,AMPL_WIDTH),
conv_std_logic_vector(28296,AMPL_WIDTH),
conv_std_logic_vector(28297,AMPL_WIDTH),
conv_std_logic_vector(28299,AMPL_WIDTH),
conv_std_logic_vector(28300,AMPL_WIDTH),
conv_std_logic_vector(28302,AMPL_WIDTH),
conv_std_logic_vector(28303,AMPL_WIDTH),
conv_std_logic_vector(28305,AMPL_WIDTH),
conv_std_logic_vector(28307,AMPL_WIDTH),
conv_std_logic_vector(28308,AMPL_WIDTH),
conv_std_logic_vector(28310,AMPL_WIDTH),
conv_std_logic_vector(28311,AMPL_WIDTH),
conv_std_logic_vector(28313,AMPL_WIDTH),
conv_std_logic_vector(28315,AMPL_WIDTH),
conv_std_logic_vector(28316,AMPL_WIDTH),
conv_std_logic_vector(28318,AMPL_WIDTH),
conv_std_logic_vector(28319,AMPL_WIDTH),
conv_std_logic_vector(28321,AMPL_WIDTH),
conv_std_logic_vector(28322,AMPL_WIDTH),
conv_std_logic_vector(28324,AMPL_WIDTH),
conv_std_logic_vector(28326,AMPL_WIDTH),
conv_std_logic_vector(28327,AMPL_WIDTH),
conv_std_logic_vector(28329,AMPL_WIDTH),
conv_std_logic_vector(28330,AMPL_WIDTH),
conv_std_logic_vector(28332,AMPL_WIDTH),
conv_std_logic_vector(28333,AMPL_WIDTH),
conv_std_logic_vector(28335,AMPL_WIDTH),
conv_std_logic_vector(28337,AMPL_WIDTH),
conv_std_logic_vector(28338,AMPL_WIDTH),
conv_std_logic_vector(28340,AMPL_WIDTH),
conv_std_logic_vector(28341,AMPL_WIDTH),
conv_std_logic_vector(28343,AMPL_WIDTH),
conv_std_logic_vector(28345,AMPL_WIDTH),
conv_std_logic_vector(28346,AMPL_WIDTH),
conv_std_logic_vector(28348,AMPL_WIDTH),
conv_std_logic_vector(28349,AMPL_WIDTH),
conv_std_logic_vector(28351,AMPL_WIDTH),
conv_std_logic_vector(28352,AMPL_WIDTH),
conv_std_logic_vector(28354,AMPL_WIDTH),
conv_std_logic_vector(28356,AMPL_WIDTH),
conv_std_logic_vector(28357,AMPL_WIDTH),
conv_std_logic_vector(28359,AMPL_WIDTH),
conv_std_logic_vector(28360,AMPL_WIDTH),
conv_std_logic_vector(28362,AMPL_WIDTH),
conv_std_logic_vector(28363,AMPL_WIDTH),
conv_std_logic_vector(28365,AMPL_WIDTH),
conv_std_logic_vector(28367,AMPL_WIDTH),
conv_std_logic_vector(28368,AMPL_WIDTH),
conv_std_logic_vector(28370,AMPL_WIDTH),
conv_std_logic_vector(28371,AMPL_WIDTH),
conv_std_logic_vector(28373,AMPL_WIDTH),
conv_std_logic_vector(28374,AMPL_WIDTH),
conv_std_logic_vector(28376,AMPL_WIDTH),
conv_std_logic_vector(28378,AMPL_WIDTH),
conv_std_logic_vector(28379,AMPL_WIDTH),
conv_std_logic_vector(28381,AMPL_WIDTH),
conv_std_logic_vector(28382,AMPL_WIDTH),
conv_std_logic_vector(28384,AMPL_WIDTH),
conv_std_logic_vector(28385,AMPL_WIDTH),
conv_std_logic_vector(28387,AMPL_WIDTH),
conv_std_logic_vector(28389,AMPL_WIDTH),
conv_std_logic_vector(28390,AMPL_WIDTH),
conv_std_logic_vector(28392,AMPL_WIDTH),
conv_std_logic_vector(28393,AMPL_WIDTH),
conv_std_logic_vector(28395,AMPL_WIDTH),
conv_std_logic_vector(28396,AMPL_WIDTH),
conv_std_logic_vector(28398,AMPL_WIDTH),
conv_std_logic_vector(28400,AMPL_WIDTH),
conv_std_logic_vector(28401,AMPL_WIDTH),
conv_std_logic_vector(28403,AMPL_WIDTH),
conv_std_logic_vector(28404,AMPL_WIDTH),
conv_std_logic_vector(28406,AMPL_WIDTH),
conv_std_logic_vector(28407,AMPL_WIDTH),
conv_std_logic_vector(28409,AMPL_WIDTH),
conv_std_logic_vector(28411,AMPL_WIDTH),
conv_std_logic_vector(28412,AMPL_WIDTH),
conv_std_logic_vector(28414,AMPL_WIDTH),
conv_std_logic_vector(28415,AMPL_WIDTH),
conv_std_logic_vector(28417,AMPL_WIDTH),
conv_std_logic_vector(28418,AMPL_WIDTH),
conv_std_logic_vector(28420,AMPL_WIDTH),
conv_std_logic_vector(28421,AMPL_WIDTH),
conv_std_logic_vector(28423,AMPL_WIDTH),
conv_std_logic_vector(28425,AMPL_WIDTH),
conv_std_logic_vector(28426,AMPL_WIDTH),
conv_std_logic_vector(28428,AMPL_WIDTH),
conv_std_logic_vector(28429,AMPL_WIDTH),
conv_std_logic_vector(28431,AMPL_WIDTH),
conv_std_logic_vector(28432,AMPL_WIDTH),
conv_std_logic_vector(28434,AMPL_WIDTH),
conv_std_logic_vector(28436,AMPL_WIDTH),
conv_std_logic_vector(28437,AMPL_WIDTH),
conv_std_logic_vector(28439,AMPL_WIDTH),
conv_std_logic_vector(28440,AMPL_WIDTH),
conv_std_logic_vector(28442,AMPL_WIDTH),
conv_std_logic_vector(28443,AMPL_WIDTH),
conv_std_logic_vector(28445,AMPL_WIDTH),
conv_std_logic_vector(28446,AMPL_WIDTH),
conv_std_logic_vector(28448,AMPL_WIDTH),
conv_std_logic_vector(28450,AMPL_WIDTH),
conv_std_logic_vector(28451,AMPL_WIDTH),
conv_std_logic_vector(28453,AMPL_WIDTH),
conv_std_logic_vector(28454,AMPL_WIDTH),
conv_std_logic_vector(28456,AMPL_WIDTH),
conv_std_logic_vector(28457,AMPL_WIDTH),
conv_std_logic_vector(28459,AMPL_WIDTH),
conv_std_logic_vector(28460,AMPL_WIDTH),
conv_std_logic_vector(28462,AMPL_WIDTH),
conv_std_logic_vector(28464,AMPL_WIDTH),
conv_std_logic_vector(28465,AMPL_WIDTH),
conv_std_logic_vector(28467,AMPL_WIDTH),
conv_std_logic_vector(28468,AMPL_WIDTH),
conv_std_logic_vector(28470,AMPL_WIDTH),
conv_std_logic_vector(28471,AMPL_WIDTH),
conv_std_logic_vector(28473,AMPL_WIDTH),
conv_std_logic_vector(28474,AMPL_WIDTH),
conv_std_logic_vector(28476,AMPL_WIDTH),
conv_std_logic_vector(28478,AMPL_WIDTH),
conv_std_logic_vector(28479,AMPL_WIDTH),
conv_std_logic_vector(28481,AMPL_WIDTH),
conv_std_logic_vector(28482,AMPL_WIDTH),
conv_std_logic_vector(28484,AMPL_WIDTH),
conv_std_logic_vector(28485,AMPL_WIDTH),
conv_std_logic_vector(28487,AMPL_WIDTH),
conv_std_logic_vector(28488,AMPL_WIDTH),
conv_std_logic_vector(28490,AMPL_WIDTH),
conv_std_logic_vector(28492,AMPL_WIDTH),
conv_std_logic_vector(28493,AMPL_WIDTH),
conv_std_logic_vector(28495,AMPL_WIDTH),
conv_std_logic_vector(28496,AMPL_WIDTH),
conv_std_logic_vector(28498,AMPL_WIDTH),
conv_std_logic_vector(28499,AMPL_WIDTH),
conv_std_logic_vector(28501,AMPL_WIDTH),
conv_std_logic_vector(28502,AMPL_WIDTH),
conv_std_logic_vector(28504,AMPL_WIDTH),
conv_std_logic_vector(28505,AMPL_WIDTH),
conv_std_logic_vector(28507,AMPL_WIDTH),
conv_std_logic_vector(28509,AMPL_WIDTH),
conv_std_logic_vector(28510,AMPL_WIDTH),
conv_std_logic_vector(28512,AMPL_WIDTH),
conv_std_logic_vector(28513,AMPL_WIDTH),
conv_std_logic_vector(28515,AMPL_WIDTH),
conv_std_logic_vector(28516,AMPL_WIDTH),
conv_std_logic_vector(28518,AMPL_WIDTH),
conv_std_logic_vector(28519,AMPL_WIDTH),
conv_std_logic_vector(28521,AMPL_WIDTH),
conv_std_logic_vector(28523,AMPL_WIDTH),
conv_std_logic_vector(28524,AMPL_WIDTH),
conv_std_logic_vector(28526,AMPL_WIDTH),
conv_std_logic_vector(28527,AMPL_WIDTH),
conv_std_logic_vector(28529,AMPL_WIDTH),
conv_std_logic_vector(28530,AMPL_WIDTH),
conv_std_logic_vector(28532,AMPL_WIDTH),
conv_std_logic_vector(28533,AMPL_WIDTH),
conv_std_logic_vector(28535,AMPL_WIDTH),
conv_std_logic_vector(28536,AMPL_WIDTH),
conv_std_logic_vector(28538,AMPL_WIDTH),
conv_std_logic_vector(28540,AMPL_WIDTH),
conv_std_logic_vector(28541,AMPL_WIDTH),
conv_std_logic_vector(28543,AMPL_WIDTH),
conv_std_logic_vector(28544,AMPL_WIDTH),
conv_std_logic_vector(28546,AMPL_WIDTH),
conv_std_logic_vector(28547,AMPL_WIDTH),
conv_std_logic_vector(28549,AMPL_WIDTH),
conv_std_logic_vector(28550,AMPL_WIDTH),
conv_std_logic_vector(28552,AMPL_WIDTH),
conv_std_logic_vector(28553,AMPL_WIDTH),
conv_std_logic_vector(28555,AMPL_WIDTH),
conv_std_logic_vector(28556,AMPL_WIDTH),
conv_std_logic_vector(28558,AMPL_WIDTH),
conv_std_logic_vector(28560,AMPL_WIDTH),
conv_std_logic_vector(28561,AMPL_WIDTH),
conv_std_logic_vector(28563,AMPL_WIDTH),
conv_std_logic_vector(28564,AMPL_WIDTH),
conv_std_logic_vector(28566,AMPL_WIDTH),
conv_std_logic_vector(28567,AMPL_WIDTH),
conv_std_logic_vector(28569,AMPL_WIDTH),
conv_std_logic_vector(28570,AMPL_WIDTH),
conv_std_logic_vector(28572,AMPL_WIDTH),
conv_std_logic_vector(28573,AMPL_WIDTH),
conv_std_logic_vector(28575,AMPL_WIDTH),
conv_std_logic_vector(28576,AMPL_WIDTH),
conv_std_logic_vector(28578,AMPL_WIDTH),
conv_std_logic_vector(28580,AMPL_WIDTH),
conv_std_logic_vector(28581,AMPL_WIDTH),
conv_std_logic_vector(28583,AMPL_WIDTH),
conv_std_logic_vector(28584,AMPL_WIDTH),
conv_std_logic_vector(28586,AMPL_WIDTH),
conv_std_logic_vector(28587,AMPL_WIDTH),
conv_std_logic_vector(28589,AMPL_WIDTH),
conv_std_logic_vector(28590,AMPL_WIDTH),
conv_std_logic_vector(28592,AMPL_WIDTH),
conv_std_logic_vector(28593,AMPL_WIDTH),
conv_std_logic_vector(28595,AMPL_WIDTH),
conv_std_logic_vector(28596,AMPL_WIDTH),
conv_std_logic_vector(28598,AMPL_WIDTH),
conv_std_logic_vector(28600,AMPL_WIDTH),
conv_std_logic_vector(28601,AMPL_WIDTH),
conv_std_logic_vector(28603,AMPL_WIDTH),
conv_std_logic_vector(28604,AMPL_WIDTH),
conv_std_logic_vector(28606,AMPL_WIDTH),
conv_std_logic_vector(28607,AMPL_WIDTH),
conv_std_logic_vector(28609,AMPL_WIDTH),
conv_std_logic_vector(28610,AMPL_WIDTH),
conv_std_logic_vector(28612,AMPL_WIDTH),
conv_std_logic_vector(28613,AMPL_WIDTH),
conv_std_logic_vector(28615,AMPL_WIDTH),
conv_std_logic_vector(28616,AMPL_WIDTH),
conv_std_logic_vector(28618,AMPL_WIDTH),
conv_std_logic_vector(28619,AMPL_WIDTH),
conv_std_logic_vector(28621,AMPL_WIDTH),
conv_std_logic_vector(28622,AMPL_WIDTH),
conv_std_logic_vector(28624,AMPL_WIDTH),
conv_std_logic_vector(28626,AMPL_WIDTH),
conv_std_logic_vector(28627,AMPL_WIDTH),
conv_std_logic_vector(28629,AMPL_WIDTH),
conv_std_logic_vector(28630,AMPL_WIDTH),
conv_std_logic_vector(28632,AMPL_WIDTH),
conv_std_logic_vector(28633,AMPL_WIDTH),
conv_std_logic_vector(28635,AMPL_WIDTH),
conv_std_logic_vector(28636,AMPL_WIDTH),
conv_std_logic_vector(28638,AMPL_WIDTH),
conv_std_logic_vector(28639,AMPL_WIDTH),
conv_std_logic_vector(28641,AMPL_WIDTH),
conv_std_logic_vector(28642,AMPL_WIDTH),
conv_std_logic_vector(28644,AMPL_WIDTH),
conv_std_logic_vector(28645,AMPL_WIDTH),
conv_std_logic_vector(28647,AMPL_WIDTH),
conv_std_logic_vector(28648,AMPL_WIDTH),
conv_std_logic_vector(28650,AMPL_WIDTH),
conv_std_logic_vector(28651,AMPL_WIDTH),
conv_std_logic_vector(28653,AMPL_WIDTH),
conv_std_logic_vector(28655,AMPL_WIDTH),
conv_std_logic_vector(28656,AMPL_WIDTH),
conv_std_logic_vector(28658,AMPL_WIDTH),
conv_std_logic_vector(28659,AMPL_WIDTH),
conv_std_logic_vector(28661,AMPL_WIDTH),
conv_std_logic_vector(28662,AMPL_WIDTH),
conv_std_logic_vector(28664,AMPL_WIDTH),
conv_std_logic_vector(28665,AMPL_WIDTH),
conv_std_logic_vector(28667,AMPL_WIDTH),
conv_std_logic_vector(28668,AMPL_WIDTH),
conv_std_logic_vector(28670,AMPL_WIDTH),
conv_std_logic_vector(28671,AMPL_WIDTH),
conv_std_logic_vector(28673,AMPL_WIDTH),
conv_std_logic_vector(28674,AMPL_WIDTH),
conv_std_logic_vector(28676,AMPL_WIDTH),
conv_std_logic_vector(28677,AMPL_WIDTH),
conv_std_logic_vector(28679,AMPL_WIDTH),
conv_std_logic_vector(28680,AMPL_WIDTH),
conv_std_logic_vector(28682,AMPL_WIDTH),
conv_std_logic_vector(28683,AMPL_WIDTH),
conv_std_logic_vector(28685,AMPL_WIDTH),
conv_std_logic_vector(28686,AMPL_WIDTH),
conv_std_logic_vector(28688,AMPL_WIDTH),
conv_std_logic_vector(28690,AMPL_WIDTH),
conv_std_logic_vector(28691,AMPL_WIDTH),
conv_std_logic_vector(28693,AMPL_WIDTH),
conv_std_logic_vector(28694,AMPL_WIDTH),
conv_std_logic_vector(28696,AMPL_WIDTH),
conv_std_logic_vector(28697,AMPL_WIDTH),
conv_std_logic_vector(28699,AMPL_WIDTH),
conv_std_logic_vector(28700,AMPL_WIDTH),
conv_std_logic_vector(28702,AMPL_WIDTH),
conv_std_logic_vector(28703,AMPL_WIDTH),
conv_std_logic_vector(28705,AMPL_WIDTH),
conv_std_logic_vector(28706,AMPL_WIDTH),
conv_std_logic_vector(28708,AMPL_WIDTH),
conv_std_logic_vector(28709,AMPL_WIDTH),
conv_std_logic_vector(28711,AMPL_WIDTH),
conv_std_logic_vector(28712,AMPL_WIDTH),
conv_std_logic_vector(28714,AMPL_WIDTH),
conv_std_logic_vector(28715,AMPL_WIDTH),
conv_std_logic_vector(28717,AMPL_WIDTH),
conv_std_logic_vector(28718,AMPL_WIDTH),
conv_std_logic_vector(28720,AMPL_WIDTH),
conv_std_logic_vector(28721,AMPL_WIDTH),
conv_std_logic_vector(28723,AMPL_WIDTH),
conv_std_logic_vector(28724,AMPL_WIDTH),
conv_std_logic_vector(28726,AMPL_WIDTH),
conv_std_logic_vector(28727,AMPL_WIDTH),
conv_std_logic_vector(28729,AMPL_WIDTH),
conv_std_logic_vector(28730,AMPL_WIDTH),
conv_std_logic_vector(28732,AMPL_WIDTH),
conv_std_logic_vector(28733,AMPL_WIDTH),
conv_std_logic_vector(28735,AMPL_WIDTH),
conv_std_logic_vector(28736,AMPL_WIDTH),
conv_std_logic_vector(28738,AMPL_WIDTH),
conv_std_logic_vector(28739,AMPL_WIDTH),
conv_std_logic_vector(28741,AMPL_WIDTH),
conv_std_logic_vector(28742,AMPL_WIDTH),
conv_std_logic_vector(28744,AMPL_WIDTH),
conv_std_logic_vector(28745,AMPL_WIDTH),
conv_std_logic_vector(28747,AMPL_WIDTH),
conv_std_logic_vector(28748,AMPL_WIDTH),
conv_std_logic_vector(28750,AMPL_WIDTH),
conv_std_logic_vector(28752,AMPL_WIDTH),
conv_std_logic_vector(28753,AMPL_WIDTH),
conv_std_logic_vector(28755,AMPL_WIDTH),
conv_std_logic_vector(28756,AMPL_WIDTH),
conv_std_logic_vector(28758,AMPL_WIDTH),
conv_std_logic_vector(28759,AMPL_WIDTH),
conv_std_logic_vector(28761,AMPL_WIDTH),
conv_std_logic_vector(28762,AMPL_WIDTH),
conv_std_logic_vector(28764,AMPL_WIDTH),
conv_std_logic_vector(28765,AMPL_WIDTH),
conv_std_logic_vector(28767,AMPL_WIDTH),
conv_std_logic_vector(28768,AMPL_WIDTH),
conv_std_logic_vector(28770,AMPL_WIDTH),
conv_std_logic_vector(28771,AMPL_WIDTH),
conv_std_logic_vector(28773,AMPL_WIDTH),
conv_std_logic_vector(28774,AMPL_WIDTH),
conv_std_logic_vector(28776,AMPL_WIDTH),
conv_std_logic_vector(28777,AMPL_WIDTH),
conv_std_logic_vector(28779,AMPL_WIDTH),
conv_std_logic_vector(28780,AMPL_WIDTH),
conv_std_logic_vector(28782,AMPL_WIDTH),
conv_std_logic_vector(28783,AMPL_WIDTH),
conv_std_logic_vector(28785,AMPL_WIDTH),
conv_std_logic_vector(28786,AMPL_WIDTH),
conv_std_logic_vector(28788,AMPL_WIDTH),
conv_std_logic_vector(28789,AMPL_WIDTH),
conv_std_logic_vector(28791,AMPL_WIDTH),
conv_std_logic_vector(28792,AMPL_WIDTH),
conv_std_logic_vector(28794,AMPL_WIDTH),
conv_std_logic_vector(28795,AMPL_WIDTH),
conv_std_logic_vector(28797,AMPL_WIDTH),
conv_std_logic_vector(28798,AMPL_WIDTH),
conv_std_logic_vector(28800,AMPL_WIDTH),
conv_std_logic_vector(28801,AMPL_WIDTH),
conv_std_logic_vector(28803,AMPL_WIDTH),
conv_std_logic_vector(28804,AMPL_WIDTH),
conv_std_logic_vector(28806,AMPL_WIDTH),
conv_std_logic_vector(28807,AMPL_WIDTH),
conv_std_logic_vector(28809,AMPL_WIDTH),
conv_std_logic_vector(28810,AMPL_WIDTH),
conv_std_logic_vector(28812,AMPL_WIDTH),
conv_std_logic_vector(28813,AMPL_WIDTH),
conv_std_logic_vector(28815,AMPL_WIDTH),
conv_std_logic_vector(28816,AMPL_WIDTH),
conv_std_logic_vector(28818,AMPL_WIDTH),
conv_std_logic_vector(28819,AMPL_WIDTH),
conv_std_logic_vector(28821,AMPL_WIDTH),
conv_std_logic_vector(28822,AMPL_WIDTH),
conv_std_logic_vector(28824,AMPL_WIDTH),
conv_std_logic_vector(28825,AMPL_WIDTH),
conv_std_logic_vector(28827,AMPL_WIDTH),
conv_std_logic_vector(28828,AMPL_WIDTH),
conv_std_logic_vector(28830,AMPL_WIDTH),
conv_std_logic_vector(28831,AMPL_WIDTH),
conv_std_logic_vector(28832,AMPL_WIDTH),
conv_std_logic_vector(28834,AMPL_WIDTH),
conv_std_logic_vector(28835,AMPL_WIDTH),
conv_std_logic_vector(28837,AMPL_WIDTH),
conv_std_logic_vector(28838,AMPL_WIDTH),
conv_std_logic_vector(28840,AMPL_WIDTH),
conv_std_logic_vector(28841,AMPL_WIDTH),
conv_std_logic_vector(28843,AMPL_WIDTH),
conv_std_logic_vector(28844,AMPL_WIDTH),
conv_std_logic_vector(28846,AMPL_WIDTH),
conv_std_logic_vector(28847,AMPL_WIDTH),
conv_std_logic_vector(28849,AMPL_WIDTH),
conv_std_logic_vector(28850,AMPL_WIDTH),
conv_std_logic_vector(28852,AMPL_WIDTH),
conv_std_logic_vector(28853,AMPL_WIDTH),
conv_std_logic_vector(28855,AMPL_WIDTH),
conv_std_logic_vector(28856,AMPL_WIDTH),
conv_std_logic_vector(28858,AMPL_WIDTH),
conv_std_logic_vector(28859,AMPL_WIDTH),
conv_std_logic_vector(28861,AMPL_WIDTH),
conv_std_logic_vector(28862,AMPL_WIDTH),
conv_std_logic_vector(28864,AMPL_WIDTH),
conv_std_logic_vector(28865,AMPL_WIDTH),
conv_std_logic_vector(28867,AMPL_WIDTH),
conv_std_logic_vector(28868,AMPL_WIDTH),
conv_std_logic_vector(28870,AMPL_WIDTH),
conv_std_logic_vector(28871,AMPL_WIDTH),
conv_std_logic_vector(28873,AMPL_WIDTH),
conv_std_logic_vector(28874,AMPL_WIDTH),
conv_std_logic_vector(28876,AMPL_WIDTH),
conv_std_logic_vector(28877,AMPL_WIDTH),
conv_std_logic_vector(28879,AMPL_WIDTH),
conv_std_logic_vector(28880,AMPL_WIDTH),
conv_std_logic_vector(28882,AMPL_WIDTH),
conv_std_logic_vector(28883,AMPL_WIDTH),
conv_std_logic_vector(28885,AMPL_WIDTH),
conv_std_logic_vector(28886,AMPL_WIDTH),
conv_std_logic_vector(28888,AMPL_WIDTH),
conv_std_logic_vector(28889,AMPL_WIDTH),
conv_std_logic_vector(28891,AMPL_WIDTH),
conv_std_logic_vector(28892,AMPL_WIDTH),
conv_std_logic_vector(28893,AMPL_WIDTH),
conv_std_logic_vector(28895,AMPL_WIDTH),
conv_std_logic_vector(28896,AMPL_WIDTH),
conv_std_logic_vector(28898,AMPL_WIDTH),
conv_std_logic_vector(28899,AMPL_WIDTH),
conv_std_logic_vector(28901,AMPL_WIDTH),
conv_std_logic_vector(28902,AMPL_WIDTH),
conv_std_logic_vector(28904,AMPL_WIDTH),
conv_std_logic_vector(28905,AMPL_WIDTH),
conv_std_logic_vector(28907,AMPL_WIDTH),
conv_std_logic_vector(28908,AMPL_WIDTH),
conv_std_logic_vector(28910,AMPL_WIDTH),
conv_std_logic_vector(28911,AMPL_WIDTH),
conv_std_logic_vector(28913,AMPL_WIDTH),
conv_std_logic_vector(28914,AMPL_WIDTH),
conv_std_logic_vector(28916,AMPL_WIDTH),
conv_std_logic_vector(28917,AMPL_WIDTH),
conv_std_logic_vector(28919,AMPL_WIDTH),
conv_std_logic_vector(28920,AMPL_WIDTH),
conv_std_logic_vector(28922,AMPL_WIDTH),
conv_std_logic_vector(28923,AMPL_WIDTH),
conv_std_logic_vector(28925,AMPL_WIDTH),
conv_std_logic_vector(28926,AMPL_WIDTH),
conv_std_logic_vector(28927,AMPL_WIDTH),
conv_std_logic_vector(28929,AMPL_WIDTH),
conv_std_logic_vector(28930,AMPL_WIDTH),
conv_std_logic_vector(28932,AMPL_WIDTH),
conv_std_logic_vector(28933,AMPL_WIDTH),
conv_std_logic_vector(28935,AMPL_WIDTH),
conv_std_logic_vector(28936,AMPL_WIDTH),
conv_std_logic_vector(28938,AMPL_WIDTH),
conv_std_logic_vector(28939,AMPL_WIDTH),
conv_std_logic_vector(28941,AMPL_WIDTH),
conv_std_logic_vector(28942,AMPL_WIDTH),
conv_std_logic_vector(28944,AMPL_WIDTH),
conv_std_logic_vector(28945,AMPL_WIDTH),
conv_std_logic_vector(28947,AMPL_WIDTH),
conv_std_logic_vector(28948,AMPL_WIDTH),
conv_std_logic_vector(28950,AMPL_WIDTH),
conv_std_logic_vector(28951,AMPL_WIDTH),
conv_std_logic_vector(28953,AMPL_WIDTH),
conv_std_logic_vector(28954,AMPL_WIDTH),
conv_std_logic_vector(28955,AMPL_WIDTH),
conv_std_logic_vector(28957,AMPL_WIDTH),
conv_std_logic_vector(28958,AMPL_WIDTH),
conv_std_logic_vector(28960,AMPL_WIDTH),
conv_std_logic_vector(28961,AMPL_WIDTH),
conv_std_logic_vector(28963,AMPL_WIDTH),
conv_std_logic_vector(28964,AMPL_WIDTH),
conv_std_logic_vector(28966,AMPL_WIDTH),
conv_std_logic_vector(28967,AMPL_WIDTH),
conv_std_logic_vector(28969,AMPL_WIDTH),
conv_std_logic_vector(28970,AMPL_WIDTH),
conv_std_logic_vector(28972,AMPL_WIDTH),
conv_std_logic_vector(28973,AMPL_WIDTH),
conv_std_logic_vector(28975,AMPL_WIDTH),
conv_std_logic_vector(28976,AMPL_WIDTH),
conv_std_logic_vector(28977,AMPL_WIDTH),
conv_std_logic_vector(28979,AMPL_WIDTH),
conv_std_logic_vector(28980,AMPL_WIDTH),
conv_std_logic_vector(28982,AMPL_WIDTH),
conv_std_logic_vector(28983,AMPL_WIDTH),
conv_std_logic_vector(28985,AMPL_WIDTH),
conv_std_logic_vector(28986,AMPL_WIDTH),
conv_std_logic_vector(28988,AMPL_WIDTH),
conv_std_logic_vector(28989,AMPL_WIDTH),
conv_std_logic_vector(28991,AMPL_WIDTH),
conv_std_logic_vector(28992,AMPL_WIDTH),
conv_std_logic_vector(28994,AMPL_WIDTH),
conv_std_logic_vector(28995,AMPL_WIDTH),
conv_std_logic_vector(28997,AMPL_WIDTH),
conv_std_logic_vector(28998,AMPL_WIDTH),
conv_std_logic_vector(28999,AMPL_WIDTH),
conv_std_logic_vector(29001,AMPL_WIDTH),
conv_std_logic_vector(29002,AMPL_WIDTH),
conv_std_logic_vector(29004,AMPL_WIDTH),
conv_std_logic_vector(29005,AMPL_WIDTH),
conv_std_logic_vector(29007,AMPL_WIDTH),
conv_std_logic_vector(29008,AMPL_WIDTH),
conv_std_logic_vector(29010,AMPL_WIDTH),
conv_std_logic_vector(29011,AMPL_WIDTH),
conv_std_logic_vector(29013,AMPL_WIDTH),
conv_std_logic_vector(29014,AMPL_WIDTH),
conv_std_logic_vector(29016,AMPL_WIDTH),
conv_std_logic_vector(29017,AMPL_WIDTH),
conv_std_logic_vector(29018,AMPL_WIDTH),
conv_std_logic_vector(29020,AMPL_WIDTH),
conv_std_logic_vector(29021,AMPL_WIDTH),
conv_std_logic_vector(29023,AMPL_WIDTH),
conv_std_logic_vector(29024,AMPL_WIDTH),
conv_std_logic_vector(29026,AMPL_WIDTH),
conv_std_logic_vector(29027,AMPL_WIDTH),
conv_std_logic_vector(29029,AMPL_WIDTH),
conv_std_logic_vector(29030,AMPL_WIDTH),
conv_std_logic_vector(29032,AMPL_WIDTH),
conv_std_logic_vector(29033,AMPL_WIDTH),
conv_std_logic_vector(29034,AMPL_WIDTH),
conv_std_logic_vector(29036,AMPL_WIDTH),
conv_std_logic_vector(29037,AMPL_WIDTH),
conv_std_logic_vector(29039,AMPL_WIDTH),
conv_std_logic_vector(29040,AMPL_WIDTH),
conv_std_logic_vector(29042,AMPL_WIDTH),
conv_std_logic_vector(29043,AMPL_WIDTH),
conv_std_logic_vector(29045,AMPL_WIDTH),
conv_std_logic_vector(29046,AMPL_WIDTH),
conv_std_logic_vector(29048,AMPL_WIDTH),
conv_std_logic_vector(29049,AMPL_WIDTH),
conv_std_logic_vector(29050,AMPL_WIDTH),
conv_std_logic_vector(29052,AMPL_WIDTH),
conv_std_logic_vector(29053,AMPL_WIDTH),
conv_std_logic_vector(29055,AMPL_WIDTH),
conv_std_logic_vector(29056,AMPL_WIDTH),
conv_std_logic_vector(29058,AMPL_WIDTH),
conv_std_logic_vector(29059,AMPL_WIDTH),
conv_std_logic_vector(29061,AMPL_WIDTH),
conv_std_logic_vector(29062,AMPL_WIDTH),
conv_std_logic_vector(29064,AMPL_WIDTH),
conv_std_logic_vector(29065,AMPL_WIDTH),
conv_std_logic_vector(29066,AMPL_WIDTH),
conv_std_logic_vector(29068,AMPL_WIDTH),
conv_std_logic_vector(29069,AMPL_WIDTH),
conv_std_logic_vector(29071,AMPL_WIDTH),
conv_std_logic_vector(29072,AMPL_WIDTH),
conv_std_logic_vector(29074,AMPL_WIDTH),
conv_std_logic_vector(29075,AMPL_WIDTH),
conv_std_logic_vector(29077,AMPL_WIDTH),
conv_std_logic_vector(29078,AMPL_WIDTH),
conv_std_logic_vector(29079,AMPL_WIDTH),
conv_std_logic_vector(29081,AMPL_WIDTH),
conv_std_logic_vector(29082,AMPL_WIDTH),
conv_std_logic_vector(29084,AMPL_WIDTH),
conv_std_logic_vector(29085,AMPL_WIDTH),
conv_std_logic_vector(29087,AMPL_WIDTH),
conv_std_logic_vector(29088,AMPL_WIDTH),
conv_std_logic_vector(29090,AMPL_WIDTH),
conv_std_logic_vector(29091,AMPL_WIDTH),
conv_std_logic_vector(29093,AMPL_WIDTH),
conv_std_logic_vector(29094,AMPL_WIDTH),
conv_std_logic_vector(29095,AMPL_WIDTH),
conv_std_logic_vector(29097,AMPL_WIDTH),
conv_std_logic_vector(29098,AMPL_WIDTH),
conv_std_logic_vector(29100,AMPL_WIDTH),
conv_std_logic_vector(29101,AMPL_WIDTH),
conv_std_logic_vector(29103,AMPL_WIDTH),
conv_std_logic_vector(29104,AMPL_WIDTH),
conv_std_logic_vector(29106,AMPL_WIDTH),
conv_std_logic_vector(29107,AMPL_WIDTH),
conv_std_logic_vector(29108,AMPL_WIDTH),
conv_std_logic_vector(29110,AMPL_WIDTH),
conv_std_logic_vector(29111,AMPL_WIDTH),
conv_std_logic_vector(29113,AMPL_WIDTH),
conv_std_logic_vector(29114,AMPL_WIDTH),
conv_std_logic_vector(29116,AMPL_WIDTH),
conv_std_logic_vector(29117,AMPL_WIDTH),
conv_std_logic_vector(29118,AMPL_WIDTH),
conv_std_logic_vector(29120,AMPL_WIDTH),
conv_std_logic_vector(29121,AMPL_WIDTH),
conv_std_logic_vector(29123,AMPL_WIDTH),
conv_std_logic_vector(29124,AMPL_WIDTH),
conv_std_logic_vector(29126,AMPL_WIDTH),
conv_std_logic_vector(29127,AMPL_WIDTH),
conv_std_logic_vector(29129,AMPL_WIDTH),
conv_std_logic_vector(29130,AMPL_WIDTH),
conv_std_logic_vector(29131,AMPL_WIDTH),
conv_std_logic_vector(29133,AMPL_WIDTH),
conv_std_logic_vector(29134,AMPL_WIDTH),
conv_std_logic_vector(29136,AMPL_WIDTH),
conv_std_logic_vector(29137,AMPL_WIDTH),
conv_std_logic_vector(29139,AMPL_WIDTH),
conv_std_logic_vector(29140,AMPL_WIDTH),
conv_std_logic_vector(29142,AMPL_WIDTH),
conv_std_logic_vector(29143,AMPL_WIDTH),
conv_std_logic_vector(29144,AMPL_WIDTH),
conv_std_logic_vector(29146,AMPL_WIDTH),
conv_std_logic_vector(29147,AMPL_WIDTH),
conv_std_logic_vector(29149,AMPL_WIDTH),
conv_std_logic_vector(29150,AMPL_WIDTH),
conv_std_logic_vector(29152,AMPL_WIDTH),
conv_std_logic_vector(29153,AMPL_WIDTH),
conv_std_logic_vector(29154,AMPL_WIDTH),
conv_std_logic_vector(29156,AMPL_WIDTH),
conv_std_logic_vector(29157,AMPL_WIDTH),
conv_std_logic_vector(29159,AMPL_WIDTH),
conv_std_logic_vector(29160,AMPL_WIDTH),
conv_std_logic_vector(29162,AMPL_WIDTH),
conv_std_logic_vector(29163,AMPL_WIDTH),
conv_std_logic_vector(29164,AMPL_WIDTH),
conv_std_logic_vector(29166,AMPL_WIDTH),
conv_std_logic_vector(29167,AMPL_WIDTH),
conv_std_logic_vector(29169,AMPL_WIDTH),
conv_std_logic_vector(29170,AMPL_WIDTH),
conv_std_logic_vector(29172,AMPL_WIDTH),
conv_std_logic_vector(29173,AMPL_WIDTH),
conv_std_logic_vector(29174,AMPL_WIDTH),
conv_std_logic_vector(29176,AMPL_WIDTH),
conv_std_logic_vector(29177,AMPL_WIDTH),
conv_std_logic_vector(29179,AMPL_WIDTH),
conv_std_logic_vector(29180,AMPL_WIDTH),
conv_std_logic_vector(29182,AMPL_WIDTH),
conv_std_logic_vector(29183,AMPL_WIDTH),
conv_std_logic_vector(29184,AMPL_WIDTH),
conv_std_logic_vector(29186,AMPL_WIDTH),
conv_std_logic_vector(29187,AMPL_WIDTH),
conv_std_logic_vector(29189,AMPL_WIDTH),
conv_std_logic_vector(29190,AMPL_WIDTH),
conv_std_logic_vector(29192,AMPL_WIDTH),
conv_std_logic_vector(29193,AMPL_WIDTH),
conv_std_logic_vector(29194,AMPL_WIDTH),
conv_std_logic_vector(29196,AMPL_WIDTH),
conv_std_logic_vector(29197,AMPL_WIDTH),
conv_std_logic_vector(29199,AMPL_WIDTH),
conv_std_logic_vector(29200,AMPL_WIDTH),
conv_std_logic_vector(29202,AMPL_WIDTH),
conv_std_logic_vector(29203,AMPL_WIDTH),
conv_std_logic_vector(29204,AMPL_WIDTH),
conv_std_logic_vector(29206,AMPL_WIDTH),
conv_std_logic_vector(29207,AMPL_WIDTH),
conv_std_logic_vector(29209,AMPL_WIDTH),
conv_std_logic_vector(29210,AMPL_WIDTH),
conv_std_logic_vector(29212,AMPL_WIDTH),
conv_std_logic_vector(29213,AMPL_WIDTH),
conv_std_logic_vector(29214,AMPL_WIDTH),
conv_std_logic_vector(29216,AMPL_WIDTH),
conv_std_logic_vector(29217,AMPL_WIDTH),
conv_std_logic_vector(29219,AMPL_WIDTH),
conv_std_logic_vector(29220,AMPL_WIDTH),
conv_std_logic_vector(29222,AMPL_WIDTH),
conv_std_logic_vector(29223,AMPL_WIDTH),
conv_std_logic_vector(29224,AMPL_WIDTH),
conv_std_logic_vector(29226,AMPL_WIDTH),
conv_std_logic_vector(29227,AMPL_WIDTH),
conv_std_logic_vector(29229,AMPL_WIDTH),
conv_std_logic_vector(29230,AMPL_WIDTH),
conv_std_logic_vector(29231,AMPL_WIDTH),
conv_std_logic_vector(29233,AMPL_WIDTH),
conv_std_logic_vector(29234,AMPL_WIDTH),
conv_std_logic_vector(29236,AMPL_WIDTH),
conv_std_logic_vector(29237,AMPL_WIDTH),
conv_std_logic_vector(29239,AMPL_WIDTH),
conv_std_logic_vector(29240,AMPL_WIDTH),
conv_std_logic_vector(29241,AMPL_WIDTH),
conv_std_logic_vector(29243,AMPL_WIDTH),
conv_std_logic_vector(29244,AMPL_WIDTH),
conv_std_logic_vector(29246,AMPL_WIDTH),
conv_std_logic_vector(29247,AMPL_WIDTH),
conv_std_logic_vector(29248,AMPL_WIDTH),
conv_std_logic_vector(29250,AMPL_WIDTH),
conv_std_logic_vector(29251,AMPL_WIDTH),
conv_std_logic_vector(29253,AMPL_WIDTH),
conv_std_logic_vector(29254,AMPL_WIDTH),
conv_std_logic_vector(29256,AMPL_WIDTH),
conv_std_logic_vector(29257,AMPL_WIDTH),
conv_std_logic_vector(29258,AMPL_WIDTH),
conv_std_logic_vector(29260,AMPL_WIDTH),
conv_std_logic_vector(29261,AMPL_WIDTH),
conv_std_logic_vector(29263,AMPL_WIDTH),
conv_std_logic_vector(29264,AMPL_WIDTH),
conv_std_logic_vector(29265,AMPL_WIDTH),
conv_std_logic_vector(29267,AMPL_WIDTH),
conv_std_logic_vector(29268,AMPL_WIDTH),
conv_std_logic_vector(29270,AMPL_WIDTH),
conv_std_logic_vector(29271,AMPL_WIDTH),
conv_std_logic_vector(29273,AMPL_WIDTH),
conv_std_logic_vector(29274,AMPL_WIDTH),
conv_std_logic_vector(29275,AMPL_WIDTH),
conv_std_logic_vector(29277,AMPL_WIDTH),
conv_std_logic_vector(29278,AMPL_WIDTH),
conv_std_logic_vector(29280,AMPL_WIDTH),
conv_std_logic_vector(29281,AMPL_WIDTH),
conv_std_logic_vector(29282,AMPL_WIDTH),
conv_std_logic_vector(29284,AMPL_WIDTH),
conv_std_logic_vector(29285,AMPL_WIDTH),
conv_std_logic_vector(29287,AMPL_WIDTH),
conv_std_logic_vector(29288,AMPL_WIDTH),
conv_std_logic_vector(29289,AMPL_WIDTH),
conv_std_logic_vector(29291,AMPL_WIDTH),
conv_std_logic_vector(29292,AMPL_WIDTH),
conv_std_logic_vector(29294,AMPL_WIDTH),
conv_std_logic_vector(29295,AMPL_WIDTH),
conv_std_logic_vector(29296,AMPL_WIDTH),
conv_std_logic_vector(29298,AMPL_WIDTH),
conv_std_logic_vector(29299,AMPL_WIDTH),
conv_std_logic_vector(29301,AMPL_WIDTH),
conv_std_logic_vector(29302,AMPL_WIDTH),
conv_std_logic_vector(29304,AMPL_WIDTH),
conv_std_logic_vector(29305,AMPL_WIDTH),
conv_std_logic_vector(29306,AMPL_WIDTH),
conv_std_logic_vector(29308,AMPL_WIDTH),
conv_std_logic_vector(29309,AMPL_WIDTH),
conv_std_logic_vector(29311,AMPL_WIDTH),
conv_std_logic_vector(29312,AMPL_WIDTH),
conv_std_logic_vector(29313,AMPL_WIDTH),
conv_std_logic_vector(29315,AMPL_WIDTH),
conv_std_logic_vector(29316,AMPL_WIDTH),
conv_std_logic_vector(29318,AMPL_WIDTH),
conv_std_logic_vector(29319,AMPL_WIDTH),
conv_std_logic_vector(29320,AMPL_WIDTH),
conv_std_logic_vector(29322,AMPL_WIDTH),
conv_std_logic_vector(29323,AMPL_WIDTH),
conv_std_logic_vector(29325,AMPL_WIDTH),
conv_std_logic_vector(29326,AMPL_WIDTH),
conv_std_logic_vector(29327,AMPL_WIDTH),
conv_std_logic_vector(29329,AMPL_WIDTH),
conv_std_logic_vector(29330,AMPL_WIDTH),
conv_std_logic_vector(29332,AMPL_WIDTH),
conv_std_logic_vector(29333,AMPL_WIDTH),
conv_std_logic_vector(29334,AMPL_WIDTH),
conv_std_logic_vector(29336,AMPL_WIDTH),
conv_std_logic_vector(29337,AMPL_WIDTH),
conv_std_logic_vector(29339,AMPL_WIDTH),
conv_std_logic_vector(29340,AMPL_WIDTH),
conv_std_logic_vector(29341,AMPL_WIDTH),
conv_std_logic_vector(29343,AMPL_WIDTH),
conv_std_logic_vector(29344,AMPL_WIDTH),
conv_std_logic_vector(29346,AMPL_WIDTH),
conv_std_logic_vector(29347,AMPL_WIDTH),
conv_std_logic_vector(29348,AMPL_WIDTH),
conv_std_logic_vector(29350,AMPL_WIDTH),
conv_std_logic_vector(29351,AMPL_WIDTH),
conv_std_logic_vector(29353,AMPL_WIDTH),
conv_std_logic_vector(29354,AMPL_WIDTH),
conv_std_logic_vector(29355,AMPL_WIDTH),
conv_std_logic_vector(29357,AMPL_WIDTH),
conv_std_logic_vector(29358,AMPL_WIDTH),
conv_std_logic_vector(29360,AMPL_WIDTH),
conv_std_logic_vector(29361,AMPL_WIDTH),
conv_std_logic_vector(29362,AMPL_WIDTH),
conv_std_logic_vector(29364,AMPL_WIDTH),
conv_std_logic_vector(29365,AMPL_WIDTH),
conv_std_logic_vector(29366,AMPL_WIDTH),
conv_std_logic_vector(29368,AMPL_WIDTH),
conv_std_logic_vector(29369,AMPL_WIDTH),
conv_std_logic_vector(29371,AMPL_WIDTH),
conv_std_logic_vector(29372,AMPL_WIDTH),
conv_std_logic_vector(29373,AMPL_WIDTH),
conv_std_logic_vector(29375,AMPL_WIDTH),
conv_std_logic_vector(29376,AMPL_WIDTH),
conv_std_logic_vector(29378,AMPL_WIDTH),
conv_std_logic_vector(29379,AMPL_WIDTH),
conv_std_logic_vector(29380,AMPL_WIDTH),
conv_std_logic_vector(29382,AMPL_WIDTH),
conv_std_logic_vector(29383,AMPL_WIDTH),
conv_std_logic_vector(29385,AMPL_WIDTH),
conv_std_logic_vector(29386,AMPL_WIDTH),
conv_std_logic_vector(29387,AMPL_WIDTH),
conv_std_logic_vector(29389,AMPL_WIDTH),
conv_std_logic_vector(29390,AMPL_WIDTH),
conv_std_logic_vector(29392,AMPL_WIDTH),
conv_std_logic_vector(29393,AMPL_WIDTH),
conv_std_logic_vector(29394,AMPL_WIDTH),
conv_std_logic_vector(29396,AMPL_WIDTH),
conv_std_logic_vector(29397,AMPL_WIDTH),
conv_std_logic_vector(29398,AMPL_WIDTH),
conv_std_logic_vector(29400,AMPL_WIDTH),
conv_std_logic_vector(29401,AMPL_WIDTH),
conv_std_logic_vector(29403,AMPL_WIDTH),
conv_std_logic_vector(29404,AMPL_WIDTH),
conv_std_logic_vector(29405,AMPL_WIDTH),
conv_std_logic_vector(29407,AMPL_WIDTH),
conv_std_logic_vector(29408,AMPL_WIDTH),
conv_std_logic_vector(29410,AMPL_WIDTH),
conv_std_logic_vector(29411,AMPL_WIDTH),
conv_std_logic_vector(29412,AMPL_WIDTH),
conv_std_logic_vector(29414,AMPL_WIDTH),
conv_std_logic_vector(29415,AMPL_WIDTH),
conv_std_logic_vector(29416,AMPL_WIDTH),
conv_std_logic_vector(29418,AMPL_WIDTH),
conv_std_logic_vector(29419,AMPL_WIDTH),
conv_std_logic_vector(29421,AMPL_WIDTH),
conv_std_logic_vector(29422,AMPL_WIDTH),
conv_std_logic_vector(29423,AMPL_WIDTH),
conv_std_logic_vector(29425,AMPL_WIDTH),
conv_std_logic_vector(29426,AMPL_WIDTH),
conv_std_logic_vector(29428,AMPL_WIDTH),
conv_std_logic_vector(29429,AMPL_WIDTH),
conv_std_logic_vector(29430,AMPL_WIDTH),
conv_std_logic_vector(29432,AMPL_WIDTH),
conv_std_logic_vector(29433,AMPL_WIDTH),
conv_std_logic_vector(29434,AMPL_WIDTH),
conv_std_logic_vector(29436,AMPL_WIDTH),
conv_std_logic_vector(29437,AMPL_WIDTH),
conv_std_logic_vector(29439,AMPL_WIDTH),
conv_std_logic_vector(29440,AMPL_WIDTH),
conv_std_logic_vector(29441,AMPL_WIDTH),
conv_std_logic_vector(29443,AMPL_WIDTH),
conv_std_logic_vector(29444,AMPL_WIDTH),
conv_std_logic_vector(29445,AMPL_WIDTH),
conv_std_logic_vector(29447,AMPL_WIDTH),
conv_std_logic_vector(29448,AMPL_WIDTH),
conv_std_logic_vector(29450,AMPL_WIDTH),
conv_std_logic_vector(29451,AMPL_WIDTH),
conv_std_logic_vector(29452,AMPL_WIDTH),
conv_std_logic_vector(29454,AMPL_WIDTH),
conv_std_logic_vector(29455,AMPL_WIDTH),
conv_std_logic_vector(29457,AMPL_WIDTH),
conv_std_logic_vector(29458,AMPL_WIDTH),
conv_std_logic_vector(29459,AMPL_WIDTH),
conv_std_logic_vector(29461,AMPL_WIDTH),
conv_std_logic_vector(29462,AMPL_WIDTH),
conv_std_logic_vector(29463,AMPL_WIDTH),
conv_std_logic_vector(29465,AMPL_WIDTH),
conv_std_logic_vector(29466,AMPL_WIDTH),
conv_std_logic_vector(29468,AMPL_WIDTH),
conv_std_logic_vector(29469,AMPL_WIDTH),
conv_std_logic_vector(29470,AMPL_WIDTH),
conv_std_logic_vector(29472,AMPL_WIDTH),
conv_std_logic_vector(29473,AMPL_WIDTH),
conv_std_logic_vector(29474,AMPL_WIDTH),
conv_std_logic_vector(29476,AMPL_WIDTH),
conv_std_logic_vector(29477,AMPL_WIDTH),
conv_std_logic_vector(29478,AMPL_WIDTH),
conv_std_logic_vector(29480,AMPL_WIDTH),
conv_std_logic_vector(29481,AMPL_WIDTH),
conv_std_logic_vector(29483,AMPL_WIDTH),
conv_std_logic_vector(29484,AMPL_WIDTH),
conv_std_logic_vector(29485,AMPL_WIDTH),
conv_std_logic_vector(29487,AMPL_WIDTH),
conv_std_logic_vector(29488,AMPL_WIDTH),
conv_std_logic_vector(29489,AMPL_WIDTH),
conv_std_logic_vector(29491,AMPL_WIDTH),
conv_std_logic_vector(29492,AMPL_WIDTH),
conv_std_logic_vector(29494,AMPL_WIDTH),
conv_std_logic_vector(29495,AMPL_WIDTH),
conv_std_logic_vector(29496,AMPL_WIDTH),
conv_std_logic_vector(29498,AMPL_WIDTH),
conv_std_logic_vector(29499,AMPL_WIDTH),
conv_std_logic_vector(29500,AMPL_WIDTH),
conv_std_logic_vector(29502,AMPL_WIDTH),
conv_std_logic_vector(29503,AMPL_WIDTH),
conv_std_logic_vector(29504,AMPL_WIDTH),
conv_std_logic_vector(29506,AMPL_WIDTH),
conv_std_logic_vector(29507,AMPL_WIDTH),
conv_std_logic_vector(29509,AMPL_WIDTH),
conv_std_logic_vector(29510,AMPL_WIDTH),
conv_std_logic_vector(29511,AMPL_WIDTH),
conv_std_logic_vector(29513,AMPL_WIDTH),
conv_std_logic_vector(29514,AMPL_WIDTH),
conv_std_logic_vector(29515,AMPL_WIDTH),
conv_std_logic_vector(29517,AMPL_WIDTH),
conv_std_logic_vector(29518,AMPL_WIDTH),
conv_std_logic_vector(29520,AMPL_WIDTH),
conv_std_logic_vector(29521,AMPL_WIDTH),
conv_std_logic_vector(29522,AMPL_WIDTH),
conv_std_logic_vector(29524,AMPL_WIDTH),
conv_std_logic_vector(29525,AMPL_WIDTH),
conv_std_logic_vector(29526,AMPL_WIDTH),
conv_std_logic_vector(29528,AMPL_WIDTH),
conv_std_logic_vector(29529,AMPL_WIDTH),
conv_std_logic_vector(29530,AMPL_WIDTH),
conv_std_logic_vector(29532,AMPL_WIDTH),
conv_std_logic_vector(29533,AMPL_WIDTH),
conv_std_logic_vector(29534,AMPL_WIDTH),
conv_std_logic_vector(29536,AMPL_WIDTH),
conv_std_logic_vector(29537,AMPL_WIDTH),
conv_std_logic_vector(29539,AMPL_WIDTH),
conv_std_logic_vector(29540,AMPL_WIDTH),
conv_std_logic_vector(29541,AMPL_WIDTH),
conv_std_logic_vector(29543,AMPL_WIDTH),
conv_std_logic_vector(29544,AMPL_WIDTH),
conv_std_logic_vector(29545,AMPL_WIDTH),
conv_std_logic_vector(29547,AMPL_WIDTH),
conv_std_logic_vector(29548,AMPL_WIDTH),
conv_std_logic_vector(29549,AMPL_WIDTH),
conv_std_logic_vector(29551,AMPL_WIDTH),
conv_std_logic_vector(29552,AMPL_WIDTH),
conv_std_logic_vector(29554,AMPL_WIDTH),
conv_std_logic_vector(29555,AMPL_WIDTH),
conv_std_logic_vector(29556,AMPL_WIDTH),
conv_std_logic_vector(29558,AMPL_WIDTH),
conv_std_logic_vector(29559,AMPL_WIDTH),
conv_std_logic_vector(29560,AMPL_WIDTH),
conv_std_logic_vector(29562,AMPL_WIDTH),
conv_std_logic_vector(29563,AMPL_WIDTH),
conv_std_logic_vector(29564,AMPL_WIDTH),
conv_std_logic_vector(29566,AMPL_WIDTH),
conv_std_logic_vector(29567,AMPL_WIDTH),
conv_std_logic_vector(29568,AMPL_WIDTH),
conv_std_logic_vector(29570,AMPL_WIDTH),
conv_std_logic_vector(29571,AMPL_WIDTH),
conv_std_logic_vector(29572,AMPL_WIDTH),
conv_std_logic_vector(29574,AMPL_WIDTH),
conv_std_logic_vector(29575,AMPL_WIDTH),
conv_std_logic_vector(29577,AMPL_WIDTH),
conv_std_logic_vector(29578,AMPL_WIDTH),
conv_std_logic_vector(29579,AMPL_WIDTH),
conv_std_logic_vector(29581,AMPL_WIDTH),
conv_std_logic_vector(29582,AMPL_WIDTH),
conv_std_logic_vector(29583,AMPL_WIDTH),
conv_std_logic_vector(29585,AMPL_WIDTH),
conv_std_logic_vector(29586,AMPL_WIDTH),
conv_std_logic_vector(29587,AMPL_WIDTH),
conv_std_logic_vector(29589,AMPL_WIDTH),
conv_std_logic_vector(29590,AMPL_WIDTH),
conv_std_logic_vector(29591,AMPL_WIDTH),
conv_std_logic_vector(29593,AMPL_WIDTH),
conv_std_logic_vector(29594,AMPL_WIDTH),
conv_std_logic_vector(29595,AMPL_WIDTH),
conv_std_logic_vector(29597,AMPL_WIDTH),
conv_std_logic_vector(29598,AMPL_WIDTH),
conv_std_logic_vector(29599,AMPL_WIDTH),
conv_std_logic_vector(29601,AMPL_WIDTH),
conv_std_logic_vector(29602,AMPL_WIDTH),
conv_std_logic_vector(29604,AMPL_WIDTH),
conv_std_logic_vector(29605,AMPL_WIDTH),
conv_std_logic_vector(29606,AMPL_WIDTH),
conv_std_logic_vector(29608,AMPL_WIDTH),
conv_std_logic_vector(29609,AMPL_WIDTH),
conv_std_logic_vector(29610,AMPL_WIDTH),
conv_std_logic_vector(29612,AMPL_WIDTH),
conv_std_logic_vector(29613,AMPL_WIDTH),
conv_std_logic_vector(29614,AMPL_WIDTH),
conv_std_logic_vector(29616,AMPL_WIDTH),
conv_std_logic_vector(29617,AMPL_WIDTH),
conv_std_logic_vector(29618,AMPL_WIDTH),
conv_std_logic_vector(29620,AMPL_WIDTH),
conv_std_logic_vector(29621,AMPL_WIDTH),
conv_std_logic_vector(29622,AMPL_WIDTH),
conv_std_logic_vector(29624,AMPL_WIDTH),
conv_std_logic_vector(29625,AMPL_WIDTH),
conv_std_logic_vector(29626,AMPL_WIDTH),
conv_std_logic_vector(29628,AMPL_WIDTH),
conv_std_logic_vector(29629,AMPL_WIDTH),
conv_std_logic_vector(29630,AMPL_WIDTH),
conv_std_logic_vector(29632,AMPL_WIDTH),
conv_std_logic_vector(29633,AMPL_WIDTH),
conv_std_logic_vector(29634,AMPL_WIDTH),
conv_std_logic_vector(29636,AMPL_WIDTH),
conv_std_logic_vector(29637,AMPL_WIDTH),
conv_std_logic_vector(29638,AMPL_WIDTH),
conv_std_logic_vector(29640,AMPL_WIDTH),
conv_std_logic_vector(29641,AMPL_WIDTH),
conv_std_logic_vector(29642,AMPL_WIDTH),
conv_std_logic_vector(29644,AMPL_WIDTH),
conv_std_logic_vector(29645,AMPL_WIDTH),
conv_std_logic_vector(29646,AMPL_WIDTH),
conv_std_logic_vector(29648,AMPL_WIDTH),
conv_std_logic_vector(29649,AMPL_WIDTH),
conv_std_logic_vector(29651,AMPL_WIDTH),
conv_std_logic_vector(29652,AMPL_WIDTH),
conv_std_logic_vector(29653,AMPL_WIDTH),
conv_std_logic_vector(29655,AMPL_WIDTH),
conv_std_logic_vector(29656,AMPL_WIDTH),
conv_std_logic_vector(29657,AMPL_WIDTH),
conv_std_logic_vector(29659,AMPL_WIDTH),
conv_std_logic_vector(29660,AMPL_WIDTH),
conv_std_logic_vector(29661,AMPL_WIDTH),
conv_std_logic_vector(29663,AMPL_WIDTH),
conv_std_logic_vector(29664,AMPL_WIDTH),
conv_std_logic_vector(29665,AMPL_WIDTH),
conv_std_logic_vector(29667,AMPL_WIDTH),
conv_std_logic_vector(29668,AMPL_WIDTH),
conv_std_logic_vector(29669,AMPL_WIDTH),
conv_std_logic_vector(29671,AMPL_WIDTH),
conv_std_logic_vector(29672,AMPL_WIDTH),
conv_std_logic_vector(29673,AMPL_WIDTH),
conv_std_logic_vector(29675,AMPL_WIDTH),
conv_std_logic_vector(29676,AMPL_WIDTH),
conv_std_logic_vector(29677,AMPL_WIDTH),
conv_std_logic_vector(29679,AMPL_WIDTH),
conv_std_logic_vector(29680,AMPL_WIDTH),
conv_std_logic_vector(29681,AMPL_WIDTH),
conv_std_logic_vector(29683,AMPL_WIDTH),
conv_std_logic_vector(29684,AMPL_WIDTH),
conv_std_logic_vector(29685,AMPL_WIDTH),
conv_std_logic_vector(29687,AMPL_WIDTH),
conv_std_logic_vector(29688,AMPL_WIDTH),
conv_std_logic_vector(29689,AMPL_WIDTH),
conv_std_logic_vector(29690,AMPL_WIDTH),
conv_std_logic_vector(29692,AMPL_WIDTH),
conv_std_logic_vector(29693,AMPL_WIDTH),
conv_std_logic_vector(29694,AMPL_WIDTH),
conv_std_logic_vector(29696,AMPL_WIDTH),
conv_std_logic_vector(29697,AMPL_WIDTH),
conv_std_logic_vector(29698,AMPL_WIDTH),
conv_std_logic_vector(29700,AMPL_WIDTH),
conv_std_logic_vector(29701,AMPL_WIDTH),
conv_std_logic_vector(29702,AMPL_WIDTH),
conv_std_logic_vector(29704,AMPL_WIDTH),
conv_std_logic_vector(29705,AMPL_WIDTH),
conv_std_logic_vector(29706,AMPL_WIDTH),
conv_std_logic_vector(29708,AMPL_WIDTH),
conv_std_logic_vector(29709,AMPL_WIDTH),
conv_std_logic_vector(29710,AMPL_WIDTH),
conv_std_logic_vector(29712,AMPL_WIDTH),
conv_std_logic_vector(29713,AMPL_WIDTH),
conv_std_logic_vector(29714,AMPL_WIDTH),
conv_std_logic_vector(29716,AMPL_WIDTH),
conv_std_logic_vector(29717,AMPL_WIDTH),
conv_std_logic_vector(29718,AMPL_WIDTH),
conv_std_logic_vector(29720,AMPL_WIDTH),
conv_std_logic_vector(29721,AMPL_WIDTH),
conv_std_logic_vector(29722,AMPL_WIDTH),
conv_std_logic_vector(29724,AMPL_WIDTH),
conv_std_logic_vector(29725,AMPL_WIDTH),
conv_std_logic_vector(29726,AMPL_WIDTH),
conv_std_logic_vector(29728,AMPL_WIDTH),
conv_std_logic_vector(29729,AMPL_WIDTH),
conv_std_logic_vector(29730,AMPL_WIDTH),
conv_std_logic_vector(29732,AMPL_WIDTH),
conv_std_logic_vector(29733,AMPL_WIDTH),
conv_std_logic_vector(29734,AMPL_WIDTH),
conv_std_logic_vector(29736,AMPL_WIDTH),
conv_std_logic_vector(29737,AMPL_WIDTH),
conv_std_logic_vector(29738,AMPL_WIDTH),
conv_std_logic_vector(29739,AMPL_WIDTH),
conv_std_logic_vector(29741,AMPL_WIDTH),
conv_std_logic_vector(29742,AMPL_WIDTH),
conv_std_logic_vector(29743,AMPL_WIDTH),
conv_std_logic_vector(29745,AMPL_WIDTH),
conv_std_logic_vector(29746,AMPL_WIDTH),
conv_std_logic_vector(29747,AMPL_WIDTH),
conv_std_logic_vector(29749,AMPL_WIDTH),
conv_std_logic_vector(29750,AMPL_WIDTH),
conv_std_logic_vector(29751,AMPL_WIDTH),
conv_std_logic_vector(29753,AMPL_WIDTH),
conv_std_logic_vector(29754,AMPL_WIDTH),
conv_std_logic_vector(29755,AMPL_WIDTH),
conv_std_logic_vector(29757,AMPL_WIDTH),
conv_std_logic_vector(29758,AMPL_WIDTH),
conv_std_logic_vector(29759,AMPL_WIDTH),
conv_std_logic_vector(29761,AMPL_WIDTH),
conv_std_logic_vector(29762,AMPL_WIDTH),
conv_std_logic_vector(29763,AMPL_WIDTH),
conv_std_logic_vector(29764,AMPL_WIDTH),
conv_std_logic_vector(29766,AMPL_WIDTH),
conv_std_logic_vector(29767,AMPL_WIDTH),
conv_std_logic_vector(29768,AMPL_WIDTH),
conv_std_logic_vector(29770,AMPL_WIDTH),
conv_std_logic_vector(29771,AMPL_WIDTH),
conv_std_logic_vector(29772,AMPL_WIDTH),
conv_std_logic_vector(29774,AMPL_WIDTH),
conv_std_logic_vector(29775,AMPL_WIDTH),
conv_std_logic_vector(29776,AMPL_WIDTH),
conv_std_logic_vector(29778,AMPL_WIDTH),
conv_std_logic_vector(29779,AMPL_WIDTH),
conv_std_logic_vector(29780,AMPL_WIDTH),
conv_std_logic_vector(29782,AMPL_WIDTH),
conv_std_logic_vector(29783,AMPL_WIDTH),
conv_std_logic_vector(29784,AMPL_WIDTH),
conv_std_logic_vector(29785,AMPL_WIDTH),
conv_std_logic_vector(29787,AMPL_WIDTH),
conv_std_logic_vector(29788,AMPL_WIDTH),
conv_std_logic_vector(29789,AMPL_WIDTH),
conv_std_logic_vector(29791,AMPL_WIDTH),
conv_std_logic_vector(29792,AMPL_WIDTH),
conv_std_logic_vector(29793,AMPL_WIDTH),
conv_std_logic_vector(29795,AMPL_WIDTH),
conv_std_logic_vector(29796,AMPL_WIDTH),
conv_std_logic_vector(29797,AMPL_WIDTH),
conv_std_logic_vector(29799,AMPL_WIDTH),
conv_std_logic_vector(29800,AMPL_WIDTH),
conv_std_logic_vector(29801,AMPL_WIDTH),
conv_std_logic_vector(29802,AMPL_WIDTH),
conv_std_logic_vector(29804,AMPL_WIDTH),
conv_std_logic_vector(29805,AMPL_WIDTH),
conv_std_logic_vector(29806,AMPL_WIDTH),
conv_std_logic_vector(29808,AMPL_WIDTH),
conv_std_logic_vector(29809,AMPL_WIDTH),
conv_std_logic_vector(29810,AMPL_WIDTH),
conv_std_logic_vector(29812,AMPL_WIDTH),
conv_std_logic_vector(29813,AMPL_WIDTH),
conv_std_logic_vector(29814,AMPL_WIDTH),
conv_std_logic_vector(29816,AMPL_WIDTH),
conv_std_logic_vector(29817,AMPL_WIDTH),
conv_std_logic_vector(29818,AMPL_WIDTH),
conv_std_logic_vector(29819,AMPL_WIDTH),
conv_std_logic_vector(29821,AMPL_WIDTH),
conv_std_logic_vector(29822,AMPL_WIDTH),
conv_std_logic_vector(29823,AMPL_WIDTH),
conv_std_logic_vector(29825,AMPL_WIDTH),
conv_std_logic_vector(29826,AMPL_WIDTH),
conv_std_logic_vector(29827,AMPL_WIDTH),
conv_std_logic_vector(29829,AMPL_WIDTH),
conv_std_logic_vector(29830,AMPL_WIDTH),
conv_std_logic_vector(29831,AMPL_WIDTH),
conv_std_logic_vector(29832,AMPL_WIDTH),
conv_std_logic_vector(29834,AMPL_WIDTH),
conv_std_logic_vector(29835,AMPL_WIDTH),
conv_std_logic_vector(29836,AMPL_WIDTH),
conv_std_logic_vector(29838,AMPL_WIDTH),
conv_std_logic_vector(29839,AMPL_WIDTH),
conv_std_logic_vector(29840,AMPL_WIDTH),
conv_std_logic_vector(29842,AMPL_WIDTH),
conv_std_logic_vector(29843,AMPL_WIDTH),
conv_std_logic_vector(29844,AMPL_WIDTH),
conv_std_logic_vector(29845,AMPL_WIDTH),
conv_std_logic_vector(29847,AMPL_WIDTH),
conv_std_logic_vector(29848,AMPL_WIDTH),
conv_std_logic_vector(29849,AMPL_WIDTH),
conv_std_logic_vector(29851,AMPL_WIDTH),
conv_std_logic_vector(29852,AMPL_WIDTH),
conv_std_logic_vector(29853,AMPL_WIDTH),
conv_std_logic_vector(29854,AMPL_WIDTH),
conv_std_logic_vector(29856,AMPL_WIDTH),
conv_std_logic_vector(29857,AMPL_WIDTH),
conv_std_logic_vector(29858,AMPL_WIDTH),
conv_std_logic_vector(29860,AMPL_WIDTH),
conv_std_logic_vector(29861,AMPL_WIDTH),
conv_std_logic_vector(29862,AMPL_WIDTH),
conv_std_logic_vector(29864,AMPL_WIDTH),
conv_std_logic_vector(29865,AMPL_WIDTH),
conv_std_logic_vector(29866,AMPL_WIDTH),
conv_std_logic_vector(29867,AMPL_WIDTH),
conv_std_logic_vector(29869,AMPL_WIDTH),
conv_std_logic_vector(29870,AMPL_WIDTH),
conv_std_logic_vector(29871,AMPL_WIDTH),
conv_std_logic_vector(29873,AMPL_WIDTH),
conv_std_logic_vector(29874,AMPL_WIDTH),
conv_std_logic_vector(29875,AMPL_WIDTH),
conv_std_logic_vector(29876,AMPL_WIDTH),
conv_std_logic_vector(29878,AMPL_WIDTH),
conv_std_logic_vector(29879,AMPL_WIDTH),
conv_std_logic_vector(29880,AMPL_WIDTH),
conv_std_logic_vector(29882,AMPL_WIDTH),
conv_std_logic_vector(29883,AMPL_WIDTH),
conv_std_logic_vector(29884,AMPL_WIDTH),
conv_std_logic_vector(29885,AMPL_WIDTH),
conv_std_logic_vector(29887,AMPL_WIDTH),
conv_std_logic_vector(29888,AMPL_WIDTH),
conv_std_logic_vector(29889,AMPL_WIDTH),
conv_std_logic_vector(29891,AMPL_WIDTH),
conv_std_logic_vector(29892,AMPL_WIDTH),
conv_std_logic_vector(29893,AMPL_WIDTH),
conv_std_logic_vector(29894,AMPL_WIDTH),
conv_std_logic_vector(29896,AMPL_WIDTH),
conv_std_logic_vector(29897,AMPL_WIDTH),
conv_std_logic_vector(29898,AMPL_WIDTH),
conv_std_logic_vector(29900,AMPL_WIDTH),
conv_std_logic_vector(29901,AMPL_WIDTH),
conv_std_logic_vector(29902,AMPL_WIDTH),
conv_std_logic_vector(29903,AMPL_WIDTH),
conv_std_logic_vector(29905,AMPL_WIDTH),
conv_std_logic_vector(29906,AMPL_WIDTH),
conv_std_logic_vector(29907,AMPL_WIDTH),
conv_std_logic_vector(29909,AMPL_WIDTH),
conv_std_logic_vector(29910,AMPL_WIDTH),
conv_std_logic_vector(29911,AMPL_WIDTH),
conv_std_logic_vector(29912,AMPL_WIDTH),
conv_std_logic_vector(29914,AMPL_WIDTH),
conv_std_logic_vector(29915,AMPL_WIDTH),
conv_std_logic_vector(29916,AMPL_WIDTH),
conv_std_logic_vector(29918,AMPL_WIDTH),
conv_std_logic_vector(29919,AMPL_WIDTH),
conv_std_logic_vector(29920,AMPL_WIDTH),
conv_std_logic_vector(29921,AMPL_WIDTH),
conv_std_logic_vector(29923,AMPL_WIDTH),
conv_std_logic_vector(29924,AMPL_WIDTH),
conv_std_logic_vector(29925,AMPL_WIDTH),
conv_std_logic_vector(29927,AMPL_WIDTH),
conv_std_logic_vector(29928,AMPL_WIDTH),
conv_std_logic_vector(29929,AMPL_WIDTH),
conv_std_logic_vector(29930,AMPL_WIDTH),
conv_std_logic_vector(29932,AMPL_WIDTH),
conv_std_logic_vector(29933,AMPL_WIDTH),
conv_std_logic_vector(29934,AMPL_WIDTH),
conv_std_logic_vector(29936,AMPL_WIDTH),
conv_std_logic_vector(29937,AMPL_WIDTH),
conv_std_logic_vector(29938,AMPL_WIDTH),
conv_std_logic_vector(29939,AMPL_WIDTH),
conv_std_logic_vector(29941,AMPL_WIDTH),
conv_std_logic_vector(29942,AMPL_WIDTH),
conv_std_logic_vector(29943,AMPL_WIDTH),
conv_std_logic_vector(29944,AMPL_WIDTH),
conv_std_logic_vector(29946,AMPL_WIDTH),
conv_std_logic_vector(29947,AMPL_WIDTH),
conv_std_logic_vector(29948,AMPL_WIDTH),
conv_std_logic_vector(29950,AMPL_WIDTH),
conv_std_logic_vector(29951,AMPL_WIDTH),
conv_std_logic_vector(29952,AMPL_WIDTH),
conv_std_logic_vector(29953,AMPL_WIDTH),
conv_std_logic_vector(29955,AMPL_WIDTH),
conv_std_logic_vector(29956,AMPL_WIDTH),
conv_std_logic_vector(29957,AMPL_WIDTH),
conv_std_logic_vector(29958,AMPL_WIDTH),
conv_std_logic_vector(29960,AMPL_WIDTH),
conv_std_logic_vector(29961,AMPL_WIDTH),
conv_std_logic_vector(29962,AMPL_WIDTH),
conv_std_logic_vector(29964,AMPL_WIDTH),
conv_std_logic_vector(29965,AMPL_WIDTH),
conv_std_logic_vector(29966,AMPL_WIDTH),
conv_std_logic_vector(29967,AMPL_WIDTH),
conv_std_logic_vector(29969,AMPL_WIDTH),
conv_std_logic_vector(29970,AMPL_WIDTH),
conv_std_logic_vector(29971,AMPL_WIDTH),
conv_std_logic_vector(29972,AMPL_WIDTH),
conv_std_logic_vector(29974,AMPL_WIDTH),
conv_std_logic_vector(29975,AMPL_WIDTH),
conv_std_logic_vector(29976,AMPL_WIDTH),
conv_std_logic_vector(29978,AMPL_WIDTH),
conv_std_logic_vector(29979,AMPL_WIDTH),
conv_std_logic_vector(29980,AMPL_WIDTH),
conv_std_logic_vector(29981,AMPL_WIDTH),
conv_std_logic_vector(29983,AMPL_WIDTH),
conv_std_logic_vector(29984,AMPL_WIDTH),
conv_std_logic_vector(29985,AMPL_WIDTH),
conv_std_logic_vector(29986,AMPL_WIDTH),
conv_std_logic_vector(29988,AMPL_WIDTH),
conv_std_logic_vector(29989,AMPL_WIDTH),
conv_std_logic_vector(29990,AMPL_WIDTH),
conv_std_logic_vector(29991,AMPL_WIDTH),
conv_std_logic_vector(29993,AMPL_WIDTH),
conv_std_logic_vector(29994,AMPL_WIDTH),
conv_std_logic_vector(29995,AMPL_WIDTH),
conv_std_logic_vector(29997,AMPL_WIDTH),
conv_std_logic_vector(29998,AMPL_WIDTH),
conv_std_logic_vector(29999,AMPL_WIDTH),
conv_std_logic_vector(30000,AMPL_WIDTH),
conv_std_logic_vector(30002,AMPL_WIDTH),
conv_std_logic_vector(30003,AMPL_WIDTH),
conv_std_logic_vector(30004,AMPL_WIDTH),
conv_std_logic_vector(30005,AMPL_WIDTH),
conv_std_logic_vector(30007,AMPL_WIDTH),
conv_std_logic_vector(30008,AMPL_WIDTH),
conv_std_logic_vector(30009,AMPL_WIDTH),
conv_std_logic_vector(30010,AMPL_WIDTH),
conv_std_logic_vector(30012,AMPL_WIDTH),
conv_std_logic_vector(30013,AMPL_WIDTH),
conv_std_logic_vector(30014,AMPL_WIDTH),
conv_std_logic_vector(30015,AMPL_WIDTH),
conv_std_logic_vector(30017,AMPL_WIDTH),
conv_std_logic_vector(30018,AMPL_WIDTH),
conv_std_logic_vector(30019,AMPL_WIDTH),
conv_std_logic_vector(30020,AMPL_WIDTH),
conv_std_logic_vector(30022,AMPL_WIDTH),
conv_std_logic_vector(30023,AMPL_WIDTH),
conv_std_logic_vector(30024,AMPL_WIDTH),
conv_std_logic_vector(30026,AMPL_WIDTH),
conv_std_logic_vector(30027,AMPL_WIDTH),
conv_std_logic_vector(30028,AMPL_WIDTH),
conv_std_logic_vector(30029,AMPL_WIDTH),
conv_std_logic_vector(30031,AMPL_WIDTH),
conv_std_logic_vector(30032,AMPL_WIDTH),
conv_std_logic_vector(30033,AMPL_WIDTH),
conv_std_logic_vector(30034,AMPL_WIDTH),
conv_std_logic_vector(30036,AMPL_WIDTH),
conv_std_logic_vector(30037,AMPL_WIDTH),
conv_std_logic_vector(30038,AMPL_WIDTH),
conv_std_logic_vector(30039,AMPL_WIDTH),
conv_std_logic_vector(30041,AMPL_WIDTH),
conv_std_logic_vector(30042,AMPL_WIDTH),
conv_std_logic_vector(30043,AMPL_WIDTH),
conv_std_logic_vector(30044,AMPL_WIDTH),
conv_std_logic_vector(30046,AMPL_WIDTH),
conv_std_logic_vector(30047,AMPL_WIDTH),
conv_std_logic_vector(30048,AMPL_WIDTH),
conv_std_logic_vector(30049,AMPL_WIDTH),
conv_std_logic_vector(30051,AMPL_WIDTH),
conv_std_logic_vector(30052,AMPL_WIDTH),
conv_std_logic_vector(30053,AMPL_WIDTH),
conv_std_logic_vector(30054,AMPL_WIDTH),
conv_std_logic_vector(30056,AMPL_WIDTH),
conv_std_logic_vector(30057,AMPL_WIDTH),
conv_std_logic_vector(30058,AMPL_WIDTH),
conv_std_logic_vector(30059,AMPL_WIDTH),
conv_std_logic_vector(30061,AMPL_WIDTH),
conv_std_logic_vector(30062,AMPL_WIDTH),
conv_std_logic_vector(30063,AMPL_WIDTH),
conv_std_logic_vector(30064,AMPL_WIDTH),
conv_std_logic_vector(30066,AMPL_WIDTH),
conv_std_logic_vector(30067,AMPL_WIDTH),
conv_std_logic_vector(30068,AMPL_WIDTH),
conv_std_logic_vector(30069,AMPL_WIDTH),
conv_std_logic_vector(30071,AMPL_WIDTH),
conv_std_logic_vector(30072,AMPL_WIDTH),
conv_std_logic_vector(30073,AMPL_WIDTH),
conv_std_logic_vector(30074,AMPL_WIDTH),
conv_std_logic_vector(30076,AMPL_WIDTH),
conv_std_logic_vector(30077,AMPL_WIDTH),
conv_std_logic_vector(30078,AMPL_WIDTH),
conv_std_logic_vector(30079,AMPL_WIDTH),
conv_std_logic_vector(30081,AMPL_WIDTH),
conv_std_logic_vector(30082,AMPL_WIDTH),
conv_std_logic_vector(30083,AMPL_WIDTH),
conv_std_logic_vector(30084,AMPL_WIDTH),
conv_std_logic_vector(30086,AMPL_WIDTH),
conv_std_logic_vector(30087,AMPL_WIDTH),
conv_std_logic_vector(30088,AMPL_WIDTH),
conv_std_logic_vector(30089,AMPL_WIDTH),
conv_std_logic_vector(30091,AMPL_WIDTH),
conv_std_logic_vector(30092,AMPL_WIDTH),
conv_std_logic_vector(30093,AMPL_WIDTH),
conv_std_logic_vector(30094,AMPL_WIDTH),
conv_std_logic_vector(30096,AMPL_WIDTH),
conv_std_logic_vector(30097,AMPL_WIDTH),
conv_std_logic_vector(30098,AMPL_WIDTH),
conv_std_logic_vector(30099,AMPL_WIDTH),
conv_std_logic_vector(30100,AMPL_WIDTH),
conv_std_logic_vector(30102,AMPL_WIDTH),
conv_std_logic_vector(30103,AMPL_WIDTH),
conv_std_logic_vector(30104,AMPL_WIDTH),
conv_std_logic_vector(30105,AMPL_WIDTH),
conv_std_logic_vector(30107,AMPL_WIDTH),
conv_std_logic_vector(30108,AMPL_WIDTH),
conv_std_logic_vector(30109,AMPL_WIDTH),
conv_std_logic_vector(30110,AMPL_WIDTH),
conv_std_logic_vector(30112,AMPL_WIDTH),
conv_std_logic_vector(30113,AMPL_WIDTH),
conv_std_logic_vector(30114,AMPL_WIDTH),
conv_std_logic_vector(30115,AMPL_WIDTH),
conv_std_logic_vector(30117,AMPL_WIDTH),
conv_std_logic_vector(30118,AMPL_WIDTH),
conv_std_logic_vector(30119,AMPL_WIDTH),
conv_std_logic_vector(30120,AMPL_WIDTH),
conv_std_logic_vector(30122,AMPL_WIDTH),
conv_std_logic_vector(30123,AMPL_WIDTH),
conv_std_logic_vector(30124,AMPL_WIDTH),
conv_std_logic_vector(30125,AMPL_WIDTH),
conv_std_logic_vector(30126,AMPL_WIDTH),
conv_std_logic_vector(30128,AMPL_WIDTH),
conv_std_logic_vector(30129,AMPL_WIDTH),
conv_std_logic_vector(30130,AMPL_WIDTH),
conv_std_logic_vector(30131,AMPL_WIDTH),
conv_std_logic_vector(30133,AMPL_WIDTH),
conv_std_logic_vector(30134,AMPL_WIDTH),
conv_std_logic_vector(30135,AMPL_WIDTH),
conv_std_logic_vector(30136,AMPL_WIDTH),
conv_std_logic_vector(30138,AMPL_WIDTH),
conv_std_logic_vector(30139,AMPL_WIDTH),
conv_std_logic_vector(30140,AMPL_WIDTH),
conv_std_logic_vector(30141,AMPL_WIDTH),
conv_std_logic_vector(30143,AMPL_WIDTH),
conv_std_logic_vector(30144,AMPL_WIDTH),
conv_std_logic_vector(30145,AMPL_WIDTH),
conv_std_logic_vector(30146,AMPL_WIDTH),
conv_std_logic_vector(30147,AMPL_WIDTH),
conv_std_logic_vector(30149,AMPL_WIDTH),
conv_std_logic_vector(30150,AMPL_WIDTH),
conv_std_logic_vector(30151,AMPL_WIDTH),
conv_std_logic_vector(30152,AMPL_WIDTH),
conv_std_logic_vector(30154,AMPL_WIDTH),
conv_std_logic_vector(30155,AMPL_WIDTH),
conv_std_logic_vector(30156,AMPL_WIDTH),
conv_std_logic_vector(30157,AMPL_WIDTH),
conv_std_logic_vector(30159,AMPL_WIDTH),
conv_std_logic_vector(30160,AMPL_WIDTH),
conv_std_logic_vector(30161,AMPL_WIDTH),
conv_std_logic_vector(30162,AMPL_WIDTH),
conv_std_logic_vector(30163,AMPL_WIDTH),
conv_std_logic_vector(30165,AMPL_WIDTH),
conv_std_logic_vector(30166,AMPL_WIDTH),
conv_std_logic_vector(30167,AMPL_WIDTH),
conv_std_logic_vector(30168,AMPL_WIDTH),
conv_std_logic_vector(30170,AMPL_WIDTH),
conv_std_logic_vector(30171,AMPL_WIDTH),
conv_std_logic_vector(30172,AMPL_WIDTH),
conv_std_logic_vector(30173,AMPL_WIDTH),
conv_std_logic_vector(30174,AMPL_WIDTH),
conv_std_logic_vector(30176,AMPL_WIDTH),
conv_std_logic_vector(30177,AMPL_WIDTH),
conv_std_logic_vector(30178,AMPL_WIDTH),
conv_std_logic_vector(30179,AMPL_WIDTH),
conv_std_logic_vector(30181,AMPL_WIDTH),
conv_std_logic_vector(30182,AMPL_WIDTH),
conv_std_logic_vector(30183,AMPL_WIDTH),
conv_std_logic_vector(30184,AMPL_WIDTH),
conv_std_logic_vector(30185,AMPL_WIDTH),
conv_std_logic_vector(30187,AMPL_WIDTH),
conv_std_logic_vector(30188,AMPL_WIDTH),
conv_std_logic_vector(30189,AMPL_WIDTH),
conv_std_logic_vector(30190,AMPL_WIDTH),
conv_std_logic_vector(30192,AMPL_WIDTH),
conv_std_logic_vector(30193,AMPL_WIDTH),
conv_std_logic_vector(30194,AMPL_WIDTH),
conv_std_logic_vector(30195,AMPL_WIDTH),
conv_std_logic_vector(30196,AMPL_WIDTH),
conv_std_logic_vector(30198,AMPL_WIDTH),
conv_std_logic_vector(30199,AMPL_WIDTH),
conv_std_logic_vector(30200,AMPL_WIDTH),
conv_std_logic_vector(30201,AMPL_WIDTH),
conv_std_logic_vector(30203,AMPL_WIDTH),
conv_std_logic_vector(30204,AMPL_WIDTH),
conv_std_logic_vector(30205,AMPL_WIDTH),
conv_std_logic_vector(30206,AMPL_WIDTH),
conv_std_logic_vector(30207,AMPL_WIDTH),
conv_std_logic_vector(30209,AMPL_WIDTH),
conv_std_logic_vector(30210,AMPL_WIDTH),
conv_std_logic_vector(30211,AMPL_WIDTH),
conv_std_logic_vector(30212,AMPL_WIDTH),
conv_std_logic_vector(30214,AMPL_WIDTH),
conv_std_logic_vector(30215,AMPL_WIDTH),
conv_std_logic_vector(30216,AMPL_WIDTH),
conv_std_logic_vector(30217,AMPL_WIDTH),
conv_std_logic_vector(30218,AMPL_WIDTH),
conv_std_logic_vector(30220,AMPL_WIDTH),
conv_std_logic_vector(30221,AMPL_WIDTH),
conv_std_logic_vector(30222,AMPL_WIDTH),
conv_std_logic_vector(30223,AMPL_WIDTH),
conv_std_logic_vector(30224,AMPL_WIDTH),
conv_std_logic_vector(30226,AMPL_WIDTH),
conv_std_logic_vector(30227,AMPL_WIDTH),
conv_std_logic_vector(30228,AMPL_WIDTH),
conv_std_logic_vector(30229,AMPL_WIDTH),
conv_std_logic_vector(30231,AMPL_WIDTH),
conv_std_logic_vector(30232,AMPL_WIDTH),
conv_std_logic_vector(30233,AMPL_WIDTH),
conv_std_logic_vector(30234,AMPL_WIDTH),
conv_std_logic_vector(30235,AMPL_WIDTH),
conv_std_logic_vector(30237,AMPL_WIDTH),
conv_std_logic_vector(30238,AMPL_WIDTH),
conv_std_logic_vector(30239,AMPL_WIDTH),
conv_std_logic_vector(30240,AMPL_WIDTH),
conv_std_logic_vector(30241,AMPL_WIDTH),
conv_std_logic_vector(30243,AMPL_WIDTH),
conv_std_logic_vector(30244,AMPL_WIDTH),
conv_std_logic_vector(30245,AMPL_WIDTH),
conv_std_logic_vector(30246,AMPL_WIDTH),
conv_std_logic_vector(30247,AMPL_WIDTH),
conv_std_logic_vector(30249,AMPL_WIDTH),
conv_std_logic_vector(30250,AMPL_WIDTH),
conv_std_logic_vector(30251,AMPL_WIDTH),
conv_std_logic_vector(30252,AMPL_WIDTH),
conv_std_logic_vector(30253,AMPL_WIDTH),
conv_std_logic_vector(30255,AMPL_WIDTH),
conv_std_logic_vector(30256,AMPL_WIDTH),
conv_std_logic_vector(30257,AMPL_WIDTH),
conv_std_logic_vector(30258,AMPL_WIDTH),
conv_std_logic_vector(30260,AMPL_WIDTH),
conv_std_logic_vector(30261,AMPL_WIDTH),
conv_std_logic_vector(30262,AMPL_WIDTH),
conv_std_logic_vector(30263,AMPL_WIDTH),
conv_std_logic_vector(30264,AMPL_WIDTH),
conv_std_logic_vector(30266,AMPL_WIDTH),
conv_std_logic_vector(30267,AMPL_WIDTH),
conv_std_logic_vector(30268,AMPL_WIDTH),
conv_std_logic_vector(30269,AMPL_WIDTH),
conv_std_logic_vector(30270,AMPL_WIDTH),
conv_std_logic_vector(30272,AMPL_WIDTH),
conv_std_logic_vector(30273,AMPL_WIDTH),
conv_std_logic_vector(30274,AMPL_WIDTH),
conv_std_logic_vector(30275,AMPL_WIDTH),
conv_std_logic_vector(30276,AMPL_WIDTH),
conv_std_logic_vector(30278,AMPL_WIDTH),
conv_std_logic_vector(30279,AMPL_WIDTH),
conv_std_logic_vector(30280,AMPL_WIDTH),
conv_std_logic_vector(30281,AMPL_WIDTH),
conv_std_logic_vector(30282,AMPL_WIDTH),
conv_std_logic_vector(30284,AMPL_WIDTH),
conv_std_logic_vector(30285,AMPL_WIDTH),
conv_std_logic_vector(30286,AMPL_WIDTH),
conv_std_logic_vector(30287,AMPL_WIDTH),
conv_std_logic_vector(30288,AMPL_WIDTH),
conv_std_logic_vector(30290,AMPL_WIDTH),
conv_std_logic_vector(30291,AMPL_WIDTH),
conv_std_logic_vector(30292,AMPL_WIDTH),
conv_std_logic_vector(30293,AMPL_WIDTH),
conv_std_logic_vector(30294,AMPL_WIDTH),
conv_std_logic_vector(30296,AMPL_WIDTH),
conv_std_logic_vector(30297,AMPL_WIDTH),
conv_std_logic_vector(30298,AMPL_WIDTH),
conv_std_logic_vector(30299,AMPL_WIDTH),
conv_std_logic_vector(30300,AMPL_WIDTH),
conv_std_logic_vector(30302,AMPL_WIDTH),
conv_std_logic_vector(30303,AMPL_WIDTH),
conv_std_logic_vector(30304,AMPL_WIDTH),
conv_std_logic_vector(30305,AMPL_WIDTH),
conv_std_logic_vector(30306,AMPL_WIDTH),
conv_std_logic_vector(30308,AMPL_WIDTH),
conv_std_logic_vector(30309,AMPL_WIDTH),
conv_std_logic_vector(30310,AMPL_WIDTH),
conv_std_logic_vector(30311,AMPL_WIDTH),
conv_std_logic_vector(30312,AMPL_WIDTH),
conv_std_logic_vector(30313,AMPL_WIDTH),
conv_std_logic_vector(30315,AMPL_WIDTH),
conv_std_logic_vector(30316,AMPL_WIDTH),
conv_std_logic_vector(30317,AMPL_WIDTH),
conv_std_logic_vector(30318,AMPL_WIDTH),
conv_std_logic_vector(30319,AMPL_WIDTH),
conv_std_logic_vector(30321,AMPL_WIDTH),
conv_std_logic_vector(30322,AMPL_WIDTH),
conv_std_logic_vector(30323,AMPL_WIDTH),
conv_std_logic_vector(30324,AMPL_WIDTH),
conv_std_logic_vector(30325,AMPL_WIDTH),
conv_std_logic_vector(30327,AMPL_WIDTH),
conv_std_logic_vector(30328,AMPL_WIDTH),
conv_std_logic_vector(30329,AMPL_WIDTH),
conv_std_logic_vector(30330,AMPL_WIDTH),
conv_std_logic_vector(30331,AMPL_WIDTH),
conv_std_logic_vector(30333,AMPL_WIDTH),
conv_std_logic_vector(30334,AMPL_WIDTH),
conv_std_logic_vector(30335,AMPL_WIDTH),
conv_std_logic_vector(30336,AMPL_WIDTH),
conv_std_logic_vector(30337,AMPL_WIDTH),
conv_std_logic_vector(30338,AMPL_WIDTH),
conv_std_logic_vector(30340,AMPL_WIDTH),
conv_std_logic_vector(30341,AMPL_WIDTH),
conv_std_logic_vector(30342,AMPL_WIDTH),
conv_std_logic_vector(30343,AMPL_WIDTH),
conv_std_logic_vector(30344,AMPL_WIDTH),
conv_std_logic_vector(30346,AMPL_WIDTH),
conv_std_logic_vector(30347,AMPL_WIDTH),
conv_std_logic_vector(30348,AMPL_WIDTH),
conv_std_logic_vector(30349,AMPL_WIDTH),
conv_std_logic_vector(30350,AMPL_WIDTH),
conv_std_logic_vector(30351,AMPL_WIDTH),
conv_std_logic_vector(30353,AMPL_WIDTH),
conv_std_logic_vector(30354,AMPL_WIDTH),
conv_std_logic_vector(30355,AMPL_WIDTH),
conv_std_logic_vector(30356,AMPL_WIDTH),
conv_std_logic_vector(30357,AMPL_WIDTH),
conv_std_logic_vector(30359,AMPL_WIDTH),
conv_std_logic_vector(30360,AMPL_WIDTH),
conv_std_logic_vector(30361,AMPL_WIDTH),
conv_std_logic_vector(30362,AMPL_WIDTH),
conv_std_logic_vector(30363,AMPL_WIDTH),
conv_std_logic_vector(30365,AMPL_WIDTH),
conv_std_logic_vector(30366,AMPL_WIDTH),
conv_std_logic_vector(30367,AMPL_WIDTH),
conv_std_logic_vector(30368,AMPL_WIDTH),
conv_std_logic_vector(30369,AMPL_WIDTH),
conv_std_logic_vector(30370,AMPL_WIDTH),
conv_std_logic_vector(30372,AMPL_WIDTH),
conv_std_logic_vector(30373,AMPL_WIDTH),
conv_std_logic_vector(30374,AMPL_WIDTH),
conv_std_logic_vector(30375,AMPL_WIDTH),
conv_std_logic_vector(30376,AMPL_WIDTH),
conv_std_logic_vector(30377,AMPL_WIDTH),
conv_std_logic_vector(30379,AMPL_WIDTH),
conv_std_logic_vector(30380,AMPL_WIDTH),
conv_std_logic_vector(30381,AMPL_WIDTH),
conv_std_logic_vector(30382,AMPL_WIDTH),
conv_std_logic_vector(30383,AMPL_WIDTH),
conv_std_logic_vector(30385,AMPL_WIDTH),
conv_std_logic_vector(30386,AMPL_WIDTH),
conv_std_logic_vector(30387,AMPL_WIDTH),
conv_std_logic_vector(30388,AMPL_WIDTH),
conv_std_logic_vector(30389,AMPL_WIDTH),
conv_std_logic_vector(30390,AMPL_WIDTH),
conv_std_logic_vector(30392,AMPL_WIDTH),
conv_std_logic_vector(30393,AMPL_WIDTH),
conv_std_logic_vector(30394,AMPL_WIDTH),
conv_std_logic_vector(30395,AMPL_WIDTH),
conv_std_logic_vector(30396,AMPL_WIDTH),
conv_std_logic_vector(30397,AMPL_WIDTH),
conv_std_logic_vector(30399,AMPL_WIDTH),
conv_std_logic_vector(30400,AMPL_WIDTH),
conv_std_logic_vector(30401,AMPL_WIDTH),
conv_std_logic_vector(30402,AMPL_WIDTH),
conv_std_logic_vector(30403,AMPL_WIDTH),
conv_std_logic_vector(30404,AMPL_WIDTH),
conv_std_logic_vector(30406,AMPL_WIDTH),
conv_std_logic_vector(30407,AMPL_WIDTH),
conv_std_logic_vector(30408,AMPL_WIDTH),
conv_std_logic_vector(30409,AMPL_WIDTH),
conv_std_logic_vector(30410,AMPL_WIDTH),
conv_std_logic_vector(30412,AMPL_WIDTH),
conv_std_logic_vector(30413,AMPL_WIDTH),
conv_std_logic_vector(30414,AMPL_WIDTH),
conv_std_logic_vector(30415,AMPL_WIDTH),
conv_std_logic_vector(30416,AMPL_WIDTH),
conv_std_logic_vector(30417,AMPL_WIDTH),
conv_std_logic_vector(30419,AMPL_WIDTH),
conv_std_logic_vector(30420,AMPL_WIDTH),
conv_std_logic_vector(30421,AMPL_WIDTH),
conv_std_logic_vector(30422,AMPL_WIDTH),
conv_std_logic_vector(30423,AMPL_WIDTH),
conv_std_logic_vector(30424,AMPL_WIDTH),
conv_std_logic_vector(30426,AMPL_WIDTH),
conv_std_logic_vector(30427,AMPL_WIDTH),
conv_std_logic_vector(30428,AMPL_WIDTH),
conv_std_logic_vector(30429,AMPL_WIDTH),
conv_std_logic_vector(30430,AMPL_WIDTH),
conv_std_logic_vector(30431,AMPL_WIDTH),
conv_std_logic_vector(30433,AMPL_WIDTH),
conv_std_logic_vector(30434,AMPL_WIDTH),
conv_std_logic_vector(30435,AMPL_WIDTH),
conv_std_logic_vector(30436,AMPL_WIDTH),
conv_std_logic_vector(30437,AMPL_WIDTH),
conv_std_logic_vector(30438,AMPL_WIDTH),
conv_std_logic_vector(30439,AMPL_WIDTH),
conv_std_logic_vector(30441,AMPL_WIDTH),
conv_std_logic_vector(30442,AMPL_WIDTH),
conv_std_logic_vector(30443,AMPL_WIDTH),
conv_std_logic_vector(30444,AMPL_WIDTH),
conv_std_logic_vector(30445,AMPL_WIDTH),
conv_std_logic_vector(30446,AMPL_WIDTH),
conv_std_logic_vector(30448,AMPL_WIDTH),
conv_std_logic_vector(30449,AMPL_WIDTH),
conv_std_logic_vector(30450,AMPL_WIDTH),
conv_std_logic_vector(30451,AMPL_WIDTH),
conv_std_logic_vector(30452,AMPL_WIDTH),
conv_std_logic_vector(30453,AMPL_WIDTH),
conv_std_logic_vector(30455,AMPL_WIDTH),
conv_std_logic_vector(30456,AMPL_WIDTH),
conv_std_logic_vector(30457,AMPL_WIDTH),
conv_std_logic_vector(30458,AMPL_WIDTH),
conv_std_logic_vector(30459,AMPL_WIDTH),
conv_std_logic_vector(30460,AMPL_WIDTH),
conv_std_logic_vector(30462,AMPL_WIDTH),
conv_std_logic_vector(30463,AMPL_WIDTH),
conv_std_logic_vector(30464,AMPL_WIDTH),
conv_std_logic_vector(30465,AMPL_WIDTH),
conv_std_logic_vector(30466,AMPL_WIDTH),
conv_std_logic_vector(30467,AMPL_WIDTH),
conv_std_logic_vector(30468,AMPL_WIDTH),
conv_std_logic_vector(30470,AMPL_WIDTH),
conv_std_logic_vector(30471,AMPL_WIDTH),
conv_std_logic_vector(30472,AMPL_WIDTH),
conv_std_logic_vector(30473,AMPL_WIDTH),
conv_std_logic_vector(30474,AMPL_WIDTH),
conv_std_logic_vector(30475,AMPL_WIDTH),
conv_std_logic_vector(30477,AMPL_WIDTH),
conv_std_logic_vector(30478,AMPL_WIDTH),
conv_std_logic_vector(30479,AMPL_WIDTH),
conv_std_logic_vector(30480,AMPL_WIDTH),
conv_std_logic_vector(30481,AMPL_WIDTH),
conv_std_logic_vector(30482,AMPL_WIDTH),
conv_std_logic_vector(30483,AMPL_WIDTH),
conv_std_logic_vector(30485,AMPL_WIDTH),
conv_std_logic_vector(30486,AMPL_WIDTH),
conv_std_logic_vector(30487,AMPL_WIDTH),
conv_std_logic_vector(30488,AMPL_WIDTH),
conv_std_logic_vector(30489,AMPL_WIDTH),
conv_std_logic_vector(30490,AMPL_WIDTH),
conv_std_logic_vector(30492,AMPL_WIDTH),
conv_std_logic_vector(30493,AMPL_WIDTH),
conv_std_logic_vector(30494,AMPL_WIDTH),
conv_std_logic_vector(30495,AMPL_WIDTH),
conv_std_logic_vector(30496,AMPL_WIDTH),
conv_std_logic_vector(30497,AMPL_WIDTH),
conv_std_logic_vector(30498,AMPL_WIDTH),
conv_std_logic_vector(30500,AMPL_WIDTH),
conv_std_logic_vector(30501,AMPL_WIDTH),
conv_std_logic_vector(30502,AMPL_WIDTH),
conv_std_logic_vector(30503,AMPL_WIDTH),
conv_std_logic_vector(30504,AMPL_WIDTH),
conv_std_logic_vector(30505,AMPL_WIDTH),
conv_std_logic_vector(30506,AMPL_WIDTH),
conv_std_logic_vector(30508,AMPL_WIDTH),
conv_std_logic_vector(30509,AMPL_WIDTH),
conv_std_logic_vector(30510,AMPL_WIDTH),
conv_std_logic_vector(30511,AMPL_WIDTH),
conv_std_logic_vector(30512,AMPL_WIDTH),
conv_std_logic_vector(30513,AMPL_WIDTH),
conv_std_logic_vector(30514,AMPL_WIDTH),
conv_std_logic_vector(30516,AMPL_WIDTH),
conv_std_logic_vector(30517,AMPL_WIDTH),
conv_std_logic_vector(30518,AMPL_WIDTH),
conv_std_logic_vector(30519,AMPL_WIDTH),
conv_std_logic_vector(30520,AMPL_WIDTH),
conv_std_logic_vector(30521,AMPL_WIDTH),
conv_std_logic_vector(30522,AMPL_WIDTH),
conv_std_logic_vector(30524,AMPL_WIDTH),
conv_std_logic_vector(30525,AMPL_WIDTH),
conv_std_logic_vector(30526,AMPL_WIDTH),
conv_std_logic_vector(30527,AMPL_WIDTH),
conv_std_logic_vector(30528,AMPL_WIDTH),
conv_std_logic_vector(30529,AMPL_WIDTH),
conv_std_logic_vector(30530,AMPL_WIDTH),
conv_std_logic_vector(30532,AMPL_WIDTH),
conv_std_logic_vector(30533,AMPL_WIDTH),
conv_std_logic_vector(30534,AMPL_WIDTH),
conv_std_logic_vector(30535,AMPL_WIDTH),
conv_std_logic_vector(30536,AMPL_WIDTH),
conv_std_logic_vector(30537,AMPL_WIDTH),
conv_std_logic_vector(30538,AMPL_WIDTH),
conv_std_logic_vector(30540,AMPL_WIDTH),
conv_std_logic_vector(30541,AMPL_WIDTH),
conv_std_logic_vector(30542,AMPL_WIDTH),
conv_std_logic_vector(30543,AMPL_WIDTH),
conv_std_logic_vector(30544,AMPL_WIDTH),
conv_std_logic_vector(30545,AMPL_WIDTH),
conv_std_logic_vector(30546,AMPL_WIDTH),
conv_std_logic_vector(30548,AMPL_WIDTH),
conv_std_logic_vector(30549,AMPL_WIDTH),
conv_std_logic_vector(30550,AMPL_WIDTH),
conv_std_logic_vector(30551,AMPL_WIDTH),
conv_std_logic_vector(30552,AMPL_WIDTH),
conv_std_logic_vector(30553,AMPL_WIDTH),
conv_std_logic_vector(30554,AMPL_WIDTH),
conv_std_logic_vector(30556,AMPL_WIDTH),
conv_std_logic_vector(30557,AMPL_WIDTH),
conv_std_logic_vector(30558,AMPL_WIDTH),
conv_std_logic_vector(30559,AMPL_WIDTH),
conv_std_logic_vector(30560,AMPL_WIDTH),
conv_std_logic_vector(30561,AMPL_WIDTH),
conv_std_logic_vector(30562,AMPL_WIDTH),
conv_std_logic_vector(30563,AMPL_WIDTH),
conv_std_logic_vector(30565,AMPL_WIDTH),
conv_std_logic_vector(30566,AMPL_WIDTH),
conv_std_logic_vector(30567,AMPL_WIDTH),
conv_std_logic_vector(30568,AMPL_WIDTH),
conv_std_logic_vector(30569,AMPL_WIDTH),
conv_std_logic_vector(30570,AMPL_WIDTH),
conv_std_logic_vector(30571,AMPL_WIDTH),
conv_std_logic_vector(30573,AMPL_WIDTH),
conv_std_logic_vector(30574,AMPL_WIDTH),
conv_std_logic_vector(30575,AMPL_WIDTH),
conv_std_logic_vector(30576,AMPL_WIDTH),
conv_std_logic_vector(30577,AMPL_WIDTH),
conv_std_logic_vector(30578,AMPL_WIDTH),
conv_std_logic_vector(30579,AMPL_WIDTH),
conv_std_logic_vector(30580,AMPL_WIDTH),
conv_std_logic_vector(30582,AMPL_WIDTH),
conv_std_logic_vector(30583,AMPL_WIDTH),
conv_std_logic_vector(30584,AMPL_WIDTH),
conv_std_logic_vector(30585,AMPL_WIDTH),
conv_std_logic_vector(30586,AMPL_WIDTH),
conv_std_logic_vector(30587,AMPL_WIDTH),
conv_std_logic_vector(30588,AMPL_WIDTH),
conv_std_logic_vector(30589,AMPL_WIDTH),
conv_std_logic_vector(30591,AMPL_WIDTH),
conv_std_logic_vector(30592,AMPL_WIDTH),
conv_std_logic_vector(30593,AMPL_WIDTH),
conv_std_logic_vector(30594,AMPL_WIDTH),
conv_std_logic_vector(30595,AMPL_WIDTH),
conv_std_logic_vector(30596,AMPL_WIDTH),
conv_std_logic_vector(30597,AMPL_WIDTH),
conv_std_logic_vector(30598,AMPL_WIDTH),
conv_std_logic_vector(30600,AMPL_WIDTH),
conv_std_logic_vector(30601,AMPL_WIDTH),
conv_std_logic_vector(30602,AMPL_WIDTH),
conv_std_logic_vector(30603,AMPL_WIDTH),
conv_std_logic_vector(30604,AMPL_WIDTH),
conv_std_logic_vector(30605,AMPL_WIDTH),
conv_std_logic_vector(30606,AMPL_WIDTH),
conv_std_logic_vector(30607,AMPL_WIDTH),
conv_std_logic_vector(30609,AMPL_WIDTH),
conv_std_logic_vector(30610,AMPL_WIDTH),
conv_std_logic_vector(30611,AMPL_WIDTH),
conv_std_logic_vector(30612,AMPL_WIDTH),
conv_std_logic_vector(30613,AMPL_WIDTH),
conv_std_logic_vector(30614,AMPL_WIDTH),
conv_std_logic_vector(30615,AMPL_WIDTH),
conv_std_logic_vector(30616,AMPL_WIDTH),
conv_std_logic_vector(30617,AMPL_WIDTH),
conv_std_logic_vector(30619,AMPL_WIDTH),
conv_std_logic_vector(30620,AMPL_WIDTH),
conv_std_logic_vector(30621,AMPL_WIDTH),
conv_std_logic_vector(30622,AMPL_WIDTH),
conv_std_logic_vector(30623,AMPL_WIDTH),
conv_std_logic_vector(30624,AMPL_WIDTH),
conv_std_logic_vector(30625,AMPL_WIDTH),
conv_std_logic_vector(30626,AMPL_WIDTH),
conv_std_logic_vector(30628,AMPL_WIDTH),
conv_std_logic_vector(30629,AMPL_WIDTH),
conv_std_logic_vector(30630,AMPL_WIDTH),
conv_std_logic_vector(30631,AMPL_WIDTH),
conv_std_logic_vector(30632,AMPL_WIDTH),
conv_std_logic_vector(30633,AMPL_WIDTH),
conv_std_logic_vector(30634,AMPL_WIDTH),
conv_std_logic_vector(30635,AMPL_WIDTH),
conv_std_logic_vector(30636,AMPL_WIDTH),
conv_std_logic_vector(30638,AMPL_WIDTH),
conv_std_logic_vector(30639,AMPL_WIDTH),
conv_std_logic_vector(30640,AMPL_WIDTH),
conv_std_logic_vector(30641,AMPL_WIDTH),
conv_std_logic_vector(30642,AMPL_WIDTH),
conv_std_logic_vector(30643,AMPL_WIDTH),
conv_std_logic_vector(30644,AMPL_WIDTH),
conv_std_logic_vector(30645,AMPL_WIDTH),
conv_std_logic_vector(30646,AMPL_WIDTH),
conv_std_logic_vector(30648,AMPL_WIDTH),
conv_std_logic_vector(30649,AMPL_WIDTH),
conv_std_logic_vector(30650,AMPL_WIDTH),
conv_std_logic_vector(30651,AMPL_WIDTH),
conv_std_logic_vector(30652,AMPL_WIDTH),
conv_std_logic_vector(30653,AMPL_WIDTH),
conv_std_logic_vector(30654,AMPL_WIDTH),
conv_std_logic_vector(30655,AMPL_WIDTH),
conv_std_logic_vector(30656,AMPL_WIDTH),
conv_std_logic_vector(30658,AMPL_WIDTH),
conv_std_logic_vector(30659,AMPL_WIDTH),
conv_std_logic_vector(30660,AMPL_WIDTH),
conv_std_logic_vector(30661,AMPL_WIDTH),
conv_std_logic_vector(30662,AMPL_WIDTH),
conv_std_logic_vector(30663,AMPL_WIDTH),
conv_std_logic_vector(30664,AMPL_WIDTH),
conv_std_logic_vector(30665,AMPL_WIDTH),
conv_std_logic_vector(30666,AMPL_WIDTH),
conv_std_logic_vector(30668,AMPL_WIDTH),
conv_std_logic_vector(30669,AMPL_WIDTH),
conv_std_logic_vector(30670,AMPL_WIDTH),
conv_std_logic_vector(30671,AMPL_WIDTH),
conv_std_logic_vector(30672,AMPL_WIDTH),
conv_std_logic_vector(30673,AMPL_WIDTH),
conv_std_logic_vector(30674,AMPL_WIDTH),
conv_std_logic_vector(30675,AMPL_WIDTH),
conv_std_logic_vector(30676,AMPL_WIDTH),
conv_std_logic_vector(30678,AMPL_WIDTH),
conv_std_logic_vector(30679,AMPL_WIDTH),
conv_std_logic_vector(30680,AMPL_WIDTH),
conv_std_logic_vector(30681,AMPL_WIDTH),
conv_std_logic_vector(30682,AMPL_WIDTH),
conv_std_logic_vector(30683,AMPL_WIDTH),
conv_std_logic_vector(30684,AMPL_WIDTH),
conv_std_logic_vector(30685,AMPL_WIDTH),
conv_std_logic_vector(30686,AMPL_WIDTH),
conv_std_logic_vector(30687,AMPL_WIDTH),
conv_std_logic_vector(30689,AMPL_WIDTH),
conv_std_logic_vector(30690,AMPL_WIDTH),
conv_std_logic_vector(30691,AMPL_WIDTH),
conv_std_logic_vector(30692,AMPL_WIDTH),
conv_std_logic_vector(30693,AMPL_WIDTH),
conv_std_logic_vector(30694,AMPL_WIDTH),
conv_std_logic_vector(30695,AMPL_WIDTH),
conv_std_logic_vector(30696,AMPL_WIDTH),
conv_std_logic_vector(30697,AMPL_WIDTH),
conv_std_logic_vector(30698,AMPL_WIDTH),
conv_std_logic_vector(30700,AMPL_WIDTH),
conv_std_logic_vector(30701,AMPL_WIDTH),
conv_std_logic_vector(30702,AMPL_WIDTH),
conv_std_logic_vector(30703,AMPL_WIDTH),
conv_std_logic_vector(30704,AMPL_WIDTH),
conv_std_logic_vector(30705,AMPL_WIDTH),
conv_std_logic_vector(30706,AMPL_WIDTH),
conv_std_logic_vector(30707,AMPL_WIDTH),
conv_std_logic_vector(30708,AMPL_WIDTH),
conv_std_logic_vector(30709,AMPL_WIDTH),
conv_std_logic_vector(30711,AMPL_WIDTH),
conv_std_logic_vector(30712,AMPL_WIDTH),
conv_std_logic_vector(30713,AMPL_WIDTH),
conv_std_logic_vector(30714,AMPL_WIDTH),
conv_std_logic_vector(30715,AMPL_WIDTH),
conv_std_logic_vector(30716,AMPL_WIDTH),
conv_std_logic_vector(30717,AMPL_WIDTH),
conv_std_logic_vector(30718,AMPL_WIDTH),
conv_std_logic_vector(30719,AMPL_WIDTH),
conv_std_logic_vector(30720,AMPL_WIDTH),
conv_std_logic_vector(30721,AMPL_WIDTH),
conv_std_logic_vector(30723,AMPL_WIDTH),
conv_std_logic_vector(30724,AMPL_WIDTH),
conv_std_logic_vector(30725,AMPL_WIDTH),
conv_std_logic_vector(30726,AMPL_WIDTH),
conv_std_logic_vector(30727,AMPL_WIDTH),
conv_std_logic_vector(30728,AMPL_WIDTH),
conv_std_logic_vector(30729,AMPL_WIDTH),
conv_std_logic_vector(30730,AMPL_WIDTH),
conv_std_logic_vector(30731,AMPL_WIDTH),
conv_std_logic_vector(30732,AMPL_WIDTH),
conv_std_logic_vector(30733,AMPL_WIDTH),
conv_std_logic_vector(30735,AMPL_WIDTH),
conv_std_logic_vector(30736,AMPL_WIDTH),
conv_std_logic_vector(30737,AMPL_WIDTH),
conv_std_logic_vector(30738,AMPL_WIDTH),
conv_std_logic_vector(30739,AMPL_WIDTH),
conv_std_logic_vector(30740,AMPL_WIDTH),
conv_std_logic_vector(30741,AMPL_WIDTH),
conv_std_logic_vector(30742,AMPL_WIDTH),
conv_std_logic_vector(30743,AMPL_WIDTH),
conv_std_logic_vector(30744,AMPL_WIDTH),
conv_std_logic_vector(30745,AMPL_WIDTH),
conv_std_logic_vector(30746,AMPL_WIDTH),
conv_std_logic_vector(30748,AMPL_WIDTH),
conv_std_logic_vector(30749,AMPL_WIDTH),
conv_std_logic_vector(30750,AMPL_WIDTH),
conv_std_logic_vector(30751,AMPL_WIDTH),
conv_std_logic_vector(30752,AMPL_WIDTH),
conv_std_logic_vector(30753,AMPL_WIDTH),
conv_std_logic_vector(30754,AMPL_WIDTH),
conv_std_logic_vector(30755,AMPL_WIDTH),
conv_std_logic_vector(30756,AMPL_WIDTH),
conv_std_logic_vector(30757,AMPL_WIDTH),
conv_std_logic_vector(30758,AMPL_WIDTH),
conv_std_logic_vector(30760,AMPL_WIDTH),
conv_std_logic_vector(30761,AMPL_WIDTH),
conv_std_logic_vector(30762,AMPL_WIDTH),
conv_std_logic_vector(30763,AMPL_WIDTH),
conv_std_logic_vector(30764,AMPL_WIDTH),
conv_std_logic_vector(30765,AMPL_WIDTH),
conv_std_logic_vector(30766,AMPL_WIDTH),
conv_std_logic_vector(30767,AMPL_WIDTH),
conv_std_logic_vector(30768,AMPL_WIDTH),
conv_std_logic_vector(30769,AMPL_WIDTH),
conv_std_logic_vector(30770,AMPL_WIDTH),
conv_std_logic_vector(30771,AMPL_WIDTH),
conv_std_logic_vector(30772,AMPL_WIDTH),
conv_std_logic_vector(30774,AMPL_WIDTH),
conv_std_logic_vector(30775,AMPL_WIDTH),
conv_std_logic_vector(30776,AMPL_WIDTH),
conv_std_logic_vector(30777,AMPL_WIDTH),
conv_std_logic_vector(30778,AMPL_WIDTH),
conv_std_logic_vector(30779,AMPL_WIDTH),
conv_std_logic_vector(30780,AMPL_WIDTH),
conv_std_logic_vector(30781,AMPL_WIDTH),
conv_std_logic_vector(30782,AMPL_WIDTH),
conv_std_logic_vector(30783,AMPL_WIDTH),
conv_std_logic_vector(30784,AMPL_WIDTH),
conv_std_logic_vector(30785,AMPL_WIDTH),
conv_std_logic_vector(30786,AMPL_WIDTH),
conv_std_logic_vector(30788,AMPL_WIDTH),
conv_std_logic_vector(30789,AMPL_WIDTH),
conv_std_logic_vector(30790,AMPL_WIDTH),
conv_std_logic_vector(30791,AMPL_WIDTH),
conv_std_logic_vector(30792,AMPL_WIDTH),
conv_std_logic_vector(30793,AMPL_WIDTH),
conv_std_logic_vector(30794,AMPL_WIDTH),
conv_std_logic_vector(30795,AMPL_WIDTH),
conv_std_logic_vector(30796,AMPL_WIDTH),
conv_std_logic_vector(30797,AMPL_WIDTH),
conv_std_logic_vector(30798,AMPL_WIDTH),
conv_std_logic_vector(30799,AMPL_WIDTH),
conv_std_logic_vector(30800,AMPL_WIDTH),
conv_std_logic_vector(30802,AMPL_WIDTH),
conv_std_logic_vector(30803,AMPL_WIDTH),
conv_std_logic_vector(30804,AMPL_WIDTH),
conv_std_logic_vector(30805,AMPL_WIDTH),
conv_std_logic_vector(30806,AMPL_WIDTH),
conv_std_logic_vector(30807,AMPL_WIDTH),
conv_std_logic_vector(30808,AMPL_WIDTH),
conv_std_logic_vector(30809,AMPL_WIDTH),
conv_std_logic_vector(30810,AMPL_WIDTH),
conv_std_logic_vector(30811,AMPL_WIDTH),
conv_std_logic_vector(30812,AMPL_WIDTH),
conv_std_logic_vector(30813,AMPL_WIDTH),
conv_std_logic_vector(30814,AMPL_WIDTH),
conv_std_logic_vector(30815,AMPL_WIDTH),
conv_std_logic_vector(30816,AMPL_WIDTH),
conv_std_logic_vector(30818,AMPL_WIDTH),
conv_std_logic_vector(30819,AMPL_WIDTH),
conv_std_logic_vector(30820,AMPL_WIDTH),
conv_std_logic_vector(30821,AMPL_WIDTH),
conv_std_logic_vector(30822,AMPL_WIDTH),
conv_std_logic_vector(30823,AMPL_WIDTH),
conv_std_logic_vector(30824,AMPL_WIDTH),
conv_std_logic_vector(30825,AMPL_WIDTH),
conv_std_logic_vector(30826,AMPL_WIDTH),
conv_std_logic_vector(30827,AMPL_WIDTH),
conv_std_logic_vector(30828,AMPL_WIDTH),
conv_std_logic_vector(30829,AMPL_WIDTH),
conv_std_logic_vector(30830,AMPL_WIDTH),
conv_std_logic_vector(30831,AMPL_WIDTH),
conv_std_logic_vector(30832,AMPL_WIDTH),
conv_std_logic_vector(30834,AMPL_WIDTH),
conv_std_logic_vector(30835,AMPL_WIDTH),
conv_std_logic_vector(30836,AMPL_WIDTH),
conv_std_logic_vector(30837,AMPL_WIDTH),
conv_std_logic_vector(30838,AMPL_WIDTH),
conv_std_logic_vector(30839,AMPL_WIDTH),
conv_std_logic_vector(30840,AMPL_WIDTH),
conv_std_logic_vector(30841,AMPL_WIDTH),
conv_std_logic_vector(30842,AMPL_WIDTH),
conv_std_logic_vector(30843,AMPL_WIDTH),
conv_std_logic_vector(30844,AMPL_WIDTH),
conv_std_logic_vector(30845,AMPL_WIDTH),
conv_std_logic_vector(30846,AMPL_WIDTH),
conv_std_logic_vector(30847,AMPL_WIDTH),
conv_std_logic_vector(30848,AMPL_WIDTH),
conv_std_logic_vector(30849,AMPL_WIDTH),
conv_std_logic_vector(30851,AMPL_WIDTH),
conv_std_logic_vector(30852,AMPL_WIDTH),
conv_std_logic_vector(30853,AMPL_WIDTH),
conv_std_logic_vector(30854,AMPL_WIDTH),
conv_std_logic_vector(30855,AMPL_WIDTH),
conv_std_logic_vector(30856,AMPL_WIDTH),
conv_std_logic_vector(30857,AMPL_WIDTH),
conv_std_logic_vector(30858,AMPL_WIDTH),
conv_std_logic_vector(30859,AMPL_WIDTH),
conv_std_logic_vector(30860,AMPL_WIDTH),
conv_std_logic_vector(30861,AMPL_WIDTH),
conv_std_logic_vector(30862,AMPL_WIDTH),
conv_std_logic_vector(30863,AMPL_WIDTH),
conv_std_logic_vector(30864,AMPL_WIDTH),
conv_std_logic_vector(30865,AMPL_WIDTH),
conv_std_logic_vector(30866,AMPL_WIDTH),
conv_std_logic_vector(30867,AMPL_WIDTH),
conv_std_logic_vector(30868,AMPL_WIDTH),
conv_std_logic_vector(30870,AMPL_WIDTH),
conv_std_logic_vector(30871,AMPL_WIDTH),
conv_std_logic_vector(30872,AMPL_WIDTH),
conv_std_logic_vector(30873,AMPL_WIDTH),
conv_std_logic_vector(30874,AMPL_WIDTH),
conv_std_logic_vector(30875,AMPL_WIDTH),
conv_std_logic_vector(30876,AMPL_WIDTH),
conv_std_logic_vector(30877,AMPL_WIDTH),
conv_std_logic_vector(30878,AMPL_WIDTH),
conv_std_logic_vector(30879,AMPL_WIDTH),
conv_std_logic_vector(30880,AMPL_WIDTH),
conv_std_logic_vector(30881,AMPL_WIDTH),
conv_std_logic_vector(30882,AMPL_WIDTH),
conv_std_logic_vector(30883,AMPL_WIDTH),
conv_std_logic_vector(30884,AMPL_WIDTH),
conv_std_logic_vector(30885,AMPL_WIDTH),
conv_std_logic_vector(30886,AMPL_WIDTH),
conv_std_logic_vector(30887,AMPL_WIDTH),
conv_std_logic_vector(30888,AMPL_WIDTH),
conv_std_logic_vector(30889,AMPL_WIDTH),
conv_std_logic_vector(30891,AMPL_WIDTH),
conv_std_logic_vector(30892,AMPL_WIDTH),
conv_std_logic_vector(30893,AMPL_WIDTH),
conv_std_logic_vector(30894,AMPL_WIDTH),
conv_std_logic_vector(30895,AMPL_WIDTH),
conv_std_logic_vector(30896,AMPL_WIDTH),
conv_std_logic_vector(30897,AMPL_WIDTH),
conv_std_logic_vector(30898,AMPL_WIDTH),
conv_std_logic_vector(30899,AMPL_WIDTH),
conv_std_logic_vector(30900,AMPL_WIDTH),
conv_std_logic_vector(30901,AMPL_WIDTH),
conv_std_logic_vector(30902,AMPL_WIDTH),
conv_std_logic_vector(30903,AMPL_WIDTH),
conv_std_logic_vector(30904,AMPL_WIDTH),
conv_std_logic_vector(30905,AMPL_WIDTH),
conv_std_logic_vector(30906,AMPL_WIDTH),
conv_std_logic_vector(30907,AMPL_WIDTH),
conv_std_logic_vector(30908,AMPL_WIDTH),
conv_std_logic_vector(30909,AMPL_WIDTH),
conv_std_logic_vector(30910,AMPL_WIDTH),
conv_std_logic_vector(30911,AMPL_WIDTH),
conv_std_logic_vector(30912,AMPL_WIDTH),
conv_std_logic_vector(30914,AMPL_WIDTH),
conv_std_logic_vector(30915,AMPL_WIDTH),
conv_std_logic_vector(30916,AMPL_WIDTH),
conv_std_logic_vector(30917,AMPL_WIDTH),
conv_std_logic_vector(30918,AMPL_WIDTH),
conv_std_logic_vector(30919,AMPL_WIDTH),
conv_std_logic_vector(30920,AMPL_WIDTH),
conv_std_logic_vector(30921,AMPL_WIDTH),
conv_std_logic_vector(30922,AMPL_WIDTH),
conv_std_logic_vector(30923,AMPL_WIDTH),
conv_std_logic_vector(30924,AMPL_WIDTH),
conv_std_logic_vector(30925,AMPL_WIDTH),
conv_std_logic_vector(30926,AMPL_WIDTH),
conv_std_logic_vector(30927,AMPL_WIDTH),
conv_std_logic_vector(30928,AMPL_WIDTH),
conv_std_logic_vector(30929,AMPL_WIDTH),
conv_std_logic_vector(30930,AMPL_WIDTH),
conv_std_logic_vector(30931,AMPL_WIDTH),
conv_std_logic_vector(30932,AMPL_WIDTH),
conv_std_logic_vector(30933,AMPL_WIDTH),
conv_std_logic_vector(30934,AMPL_WIDTH),
conv_std_logic_vector(30935,AMPL_WIDTH),
conv_std_logic_vector(30936,AMPL_WIDTH),
conv_std_logic_vector(30937,AMPL_WIDTH),
conv_std_logic_vector(30938,AMPL_WIDTH),
conv_std_logic_vector(30939,AMPL_WIDTH),
conv_std_logic_vector(30941,AMPL_WIDTH),
conv_std_logic_vector(30942,AMPL_WIDTH),
conv_std_logic_vector(30943,AMPL_WIDTH),
conv_std_logic_vector(30944,AMPL_WIDTH),
conv_std_logic_vector(30945,AMPL_WIDTH),
conv_std_logic_vector(30946,AMPL_WIDTH),
conv_std_logic_vector(30947,AMPL_WIDTH),
conv_std_logic_vector(30948,AMPL_WIDTH),
conv_std_logic_vector(30949,AMPL_WIDTH),
conv_std_logic_vector(30950,AMPL_WIDTH),
conv_std_logic_vector(30951,AMPL_WIDTH),
conv_std_logic_vector(30952,AMPL_WIDTH),
conv_std_logic_vector(30953,AMPL_WIDTH),
conv_std_logic_vector(30954,AMPL_WIDTH),
conv_std_logic_vector(30955,AMPL_WIDTH),
conv_std_logic_vector(30956,AMPL_WIDTH),
conv_std_logic_vector(30957,AMPL_WIDTH),
conv_std_logic_vector(30958,AMPL_WIDTH),
conv_std_logic_vector(30959,AMPL_WIDTH),
conv_std_logic_vector(30960,AMPL_WIDTH),
conv_std_logic_vector(30961,AMPL_WIDTH),
conv_std_logic_vector(30962,AMPL_WIDTH),
conv_std_logic_vector(30963,AMPL_WIDTH),
conv_std_logic_vector(30964,AMPL_WIDTH),
conv_std_logic_vector(30965,AMPL_WIDTH),
conv_std_logic_vector(30966,AMPL_WIDTH),
conv_std_logic_vector(30967,AMPL_WIDTH),
conv_std_logic_vector(30968,AMPL_WIDTH),
conv_std_logic_vector(30969,AMPL_WIDTH),
conv_std_logic_vector(30970,AMPL_WIDTH),
conv_std_logic_vector(30971,AMPL_WIDTH),
conv_std_logic_vector(30972,AMPL_WIDTH),
conv_std_logic_vector(30973,AMPL_WIDTH),
conv_std_logic_vector(30974,AMPL_WIDTH),
conv_std_logic_vector(30976,AMPL_WIDTH),
conv_std_logic_vector(30977,AMPL_WIDTH),
conv_std_logic_vector(30978,AMPL_WIDTH),
conv_std_logic_vector(30979,AMPL_WIDTH),
conv_std_logic_vector(30980,AMPL_WIDTH),
conv_std_logic_vector(30981,AMPL_WIDTH),
conv_std_logic_vector(30982,AMPL_WIDTH),
conv_std_logic_vector(30983,AMPL_WIDTH),
conv_std_logic_vector(30984,AMPL_WIDTH),
conv_std_logic_vector(30985,AMPL_WIDTH),
conv_std_logic_vector(30986,AMPL_WIDTH),
conv_std_logic_vector(30987,AMPL_WIDTH),
conv_std_logic_vector(30988,AMPL_WIDTH),
conv_std_logic_vector(30989,AMPL_WIDTH),
conv_std_logic_vector(30990,AMPL_WIDTH),
conv_std_logic_vector(30991,AMPL_WIDTH),
conv_std_logic_vector(30992,AMPL_WIDTH),
conv_std_logic_vector(30993,AMPL_WIDTH),
conv_std_logic_vector(30994,AMPL_WIDTH),
conv_std_logic_vector(30995,AMPL_WIDTH),
conv_std_logic_vector(30996,AMPL_WIDTH),
conv_std_logic_vector(30997,AMPL_WIDTH),
conv_std_logic_vector(30998,AMPL_WIDTH),
conv_std_logic_vector(30999,AMPL_WIDTH),
conv_std_logic_vector(31000,AMPL_WIDTH),
conv_std_logic_vector(31001,AMPL_WIDTH),
conv_std_logic_vector(31002,AMPL_WIDTH),
conv_std_logic_vector(31003,AMPL_WIDTH),
conv_std_logic_vector(31004,AMPL_WIDTH),
conv_std_logic_vector(31005,AMPL_WIDTH),
conv_std_logic_vector(31006,AMPL_WIDTH),
conv_std_logic_vector(31007,AMPL_WIDTH),
conv_std_logic_vector(31008,AMPL_WIDTH),
conv_std_logic_vector(31009,AMPL_WIDTH),
conv_std_logic_vector(31010,AMPL_WIDTH),
conv_std_logic_vector(31011,AMPL_WIDTH),
conv_std_logic_vector(31012,AMPL_WIDTH),
conv_std_logic_vector(31013,AMPL_WIDTH),
conv_std_logic_vector(31014,AMPL_WIDTH),
conv_std_logic_vector(31015,AMPL_WIDTH),
conv_std_logic_vector(31016,AMPL_WIDTH),
conv_std_logic_vector(31017,AMPL_WIDTH),
conv_std_logic_vector(31018,AMPL_WIDTH),
conv_std_logic_vector(31019,AMPL_WIDTH),
conv_std_logic_vector(31020,AMPL_WIDTH),
conv_std_logic_vector(31021,AMPL_WIDTH),
conv_std_logic_vector(31022,AMPL_WIDTH),
conv_std_logic_vector(31023,AMPL_WIDTH),
conv_std_logic_vector(31024,AMPL_WIDTH),
conv_std_logic_vector(31025,AMPL_WIDTH),
conv_std_logic_vector(31026,AMPL_WIDTH),
conv_std_logic_vector(31027,AMPL_WIDTH),
conv_std_logic_vector(31028,AMPL_WIDTH),
conv_std_logic_vector(31029,AMPL_WIDTH),
conv_std_logic_vector(31030,AMPL_WIDTH),
conv_std_logic_vector(31031,AMPL_WIDTH),
conv_std_logic_vector(31032,AMPL_WIDTH),
conv_std_logic_vector(31033,AMPL_WIDTH),
conv_std_logic_vector(31034,AMPL_WIDTH),
conv_std_logic_vector(31035,AMPL_WIDTH),
conv_std_logic_vector(31036,AMPL_WIDTH),
conv_std_logic_vector(31037,AMPL_WIDTH),
conv_std_logic_vector(31038,AMPL_WIDTH),
conv_std_logic_vector(31039,AMPL_WIDTH),
conv_std_logic_vector(31040,AMPL_WIDTH),
conv_std_logic_vector(31041,AMPL_WIDTH),
conv_std_logic_vector(31043,AMPL_WIDTH),
conv_std_logic_vector(31044,AMPL_WIDTH),
conv_std_logic_vector(31045,AMPL_WIDTH),
conv_std_logic_vector(31046,AMPL_WIDTH),
conv_std_logic_vector(31047,AMPL_WIDTH),
conv_std_logic_vector(31048,AMPL_WIDTH),
conv_std_logic_vector(31049,AMPL_WIDTH),
conv_std_logic_vector(31050,AMPL_WIDTH),
conv_std_logic_vector(31051,AMPL_WIDTH),
conv_std_logic_vector(31052,AMPL_WIDTH),
conv_std_logic_vector(31053,AMPL_WIDTH),
conv_std_logic_vector(31054,AMPL_WIDTH),
conv_std_logic_vector(31055,AMPL_WIDTH),
conv_std_logic_vector(31056,AMPL_WIDTH),
conv_std_logic_vector(31057,AMPL_WIDTH),
conv_std_logic_vector(31058,AMPL_WIDTH),
conv_std_logic_vector(31059,AMPL_WIDTH),
conv_std_logic_vector(31060,AMPL_WIDTH),
conv_std_logic_vector(31061,AMPL_WIDTH),
conv_std_logic_vector(31062,AMPL_WIDTH),
conv_std_logic_vector(31063,AMPL_WIDTH),
conv_std_logic_vector(31064,AMPL_WIDTH),
conv_std_logic_vector(31065,AMPL_WIDTH),
conv_std_logic_vector(31066,AMPL_WIDTH),
conv_std_logic_vector(31067,AMPL_WIDTH),
conv_std_logic_vector(31068,AMPL_WIDTH),
conv_std_logic_vector(31069,AMPL_WIDTH),
conv_std_logic_vector(31070,AMPL_WIDTH),
conv_std_logic_vector(31071,AMPL_WIDTH),
conv_std_logic_vector(31072,AMPL_WIDTH),
conv_std_logic_vector(31073,AMPL_WIDTH),
conv_std_logic_vector(31074,AMPL_WIDTH),
conv_std_logic_vector(31075,AMPL_WIDTH),
conv_std_logic_vector(31076,AMPL_WIDTH),
conv_std_logic_vector(31077,AMPL_WIDTH),
conv_std_logic_vector(31078,AMPL_WIDTH),
conv_std_logic_vector(31079,AMPL_WIDTH),
conv_std_logic_vector(31080,AMPL_WIDTH),
conv_std_logic_vector(31081,AMPL_WIDTH),
conv_std_logic_vector(31082,AMPL_WIDTH),
conv_std_logic_vector(31083,AMPL_WIDTH),
conv_std_logic_vector(31083,AMPL_WIDTH),
conv_std_logic_vector(31084,AMPL_WIDTH),
conv_std_logic_vector(31085,AMPL_WIDTH),
conv_std_logic_vector(31086,AMPL_WIDTH),
conv_std_logic_vector(31087,AMPL_WIDTH),
conv_std_logic_vector(31088,AMPL_WIDTH),
conv_std_logic_vector(31089,AMPL_WIDTH),
conv_std_logic_vector(31090,AMPL_WIDTH),
conv_std_logic_vector(31091,AMPL_WIDTH),
conv_std_logic_vector(31092,AMPL_WIDTH),
conv_std_logic_vector(31093,AMPL_WIDTH),
conv_std_logic_vector(31094,AMPL_WIDTH),
conv_std_logic_vector(31095,AMPL_WIDTH),
conv_std_logic_vector(31096,AMPL_WIDTH),
conv_std_logic_vector(31097,AMPL_WIDTH),
conv_std_logic_vector(31098,AMPL_WIDTH),
conv_std_logic_vector(31099,AMPL_WIDTH),
conv_std_logic_vector(31100,AMPL_WIDTH),
conv_std_logic_vector(31101,AMPL_WIDTH),
conv_std_logic_vector(31102,AMPL_WIDTH),
conv_std_logic_vector(31103,AMPL_WIDTH),
conv_std_logic_vector(31104,AMPL_WIDTH),
conv_std_logic_vector(31105,AMPL_WIDTH),
conv_std_logic_vector(31106,AMPL_WIDTH),
conv_std_logic_vector(31107,AMPL_WIDTH),
conv_std_logic_vector(31108,AMPL_WIDTH),
conv_std_logic_vector(31109,AMPL_WIDTH),
conv_std_logic_vector(31110,AMPL_WIDTH),
conv_std_logic_vector(31111,AMPL_WIDTH),
conv_std_logic_vector(31112,AMPL_WIDTH),
conv_std_logic_vector(31113,AMPL_WIDTH),
conv_std_logic_vector(31114,AMPL_WIDTH),
conv_std_logic_vector(31115,AMPL_WIDTH),
conv_std_logic_vector(31116,AMPL_WIDTH),
conv_std_logic_vector(31117,AMPL_WIDTH),
conv_std_logic_vector(31118,AMPL_WIDTH),
conv_std_logic_vector(31119,AMPL_WIDTH),
conv_std_logic_vector(31120,AMPL_WIDTH),
conv_std_logic_vector(31121,AMPL_WIDTH),
conv_std_logic_vector(31122,AMPL_WIDTH),
conv_std_logic_vector(31123,AMPL_WIDTH),
conv_std_logic_vector(31124,AMPL_WIDTH),
conv_std_logic_vector(31125,AMPL_WIDTH),
conv_std_logic_vector(31126,AMPL_WIDTH),
conv_std_logic_vector(31127,AMPL_WIDTH),
conv_std_logic_vector(31128,AMPL_WIDTH),
conv_std_logic_vector(31129,AMPL_WIDTH),
conv_std_logic_vector(31130,AMPL_WIDTH),
conv_std_logic_vector(31131,AMPL_WIDTH),
conv_std_logic_vector(31132,AMPL_WIDTH),
conv_std_logic_vector(31133,AMPL_WIDTH),
conv_std_logic_vector(31134,AMPL_WIDTH),
conv_std_logic_vector(31135,AMPL_WIDTH),
conv_std_logic_vector(31136,AMPL_WIDTH),
conv_std_logic_vector(31137,AMPL_WIDTH),
conv_std_logic_vector(31138,AMPL_WIDTH),
conv_std_logic_vector(31139,AMPL_WIDTH),
conv_std_logic_vector(31140,AMPL_WIDTH),
conv_std_logic_vector(31141,AMPL_WIDTH),
conv_std_logic_vector(31142,AMPL_WIDTH),
conv_std_logic_vector(31143,AMPL_WIDTH),
conv_std_logic_vector(31144,AMPL_WIDTH),
conv_std_logic_vector(31145,AMPL_WIDTH),
conv_std_logic_vector(31146,AMPL_WIDTH),
conv_std_logic_vector(31147,AMPL_WIDTH),
conv_std_logic_vector(31148,AMPL_WIDTH),
conv_std_logic_vector(31148,AMPL_WIDTH),
conv_std_logic_vector(31149,AMPL_WIDTH),
conv_std_logic_vector(31150,AMPL_WIDTH),
conv_std_logic_vector(31151,AMPL_WIDTH),
conv_std_logic_vector(31152,AMPL_WIDTH),
conv_std_logic_vector(31153,AMPL_WIDTH),
conv_std_logic_vector(31154,AMPL_WIDTH),
conv_std_logic_vector(31155,AMPL_WIDTH),
conv_std_logic_vector(31156,AMPL_WIDTH),
conv_std_logic_vector(31157,AMPL_WIDTH),
conv_std_logic_vector(31158,AMPL_WIDTH),
conv_std_logic_vector(31159,AMPL_WIDTH),
conv_std_logic_vector(31160,AMPL_WIDTH),
conv_std_logic_vector(31161,AMPL_WIDTH),
conv_std_logic_vector(31162,AMPL_WIDTH),
conv_std_logic_vector(31163,AMPL_WIDTH),
conv_std_logic_vector(31164,AMPL_WIDTH),
conv_std_logic_vector(31165,AMPL_WIDTH),
conv_std_logic_vector(31166,AMPL_WIDTH),
conv_std_logic_vector(31167,AMPL_WIDTH),
conv_std_logic_vector(31168,AMPL_WIDTH),
conv_std_logic_vector(31169,AMPL_WIDTH),
conv_std_logic_vector(31170,AMPL_WIDTH),
conv_std_logic_vector(31171,AMPL_WIDTH),
conv_std_logic_vector(31172,AMPL_WIDTH),
conv_std_logic_vector(31173,AMPL_WIDTH),
conv_std_logic_vector(31174,AMPL_WIDTH),
conv_std_logic_vector(31175,AMPL_WIDTH),
conv_std_logic_vector(31176,AMPL_WIDTH),
conv_std_logic_vector(31177,AMPL_WIDTH),
conv_std_logic_vector(31178,AMPL_WIDTH),
conv_std_logic_vector(31179,AMPL_WIDTH),
conv_std_logic_vector(31180,AMPL_WIDTH),
conv_std_logic_vector(31181,AMPL_WIDTH),
conv_std_logic_vector(31181,AMPL_WIDTH),
conv_std_logic_vector(31182,AMPL_WIDTH),
conv_std_logic_vector(31183,AMPL_WIDTH),
conv_std_logic_vector(31184,AMPL_WIDTH),
conv_std_logic_vector(31185,AMPL_WIDTH),
conv_std_logic_vector(31186,AMPL_WIDTH),
conv_std_logic_vector(31187,AMPL_WIDTH),
conv_std_logic_vector(31188,AMPL_WIDTH),
conv_std_logic_vector(31189,AMPL_WIDTH),
conv_std_logic_vector(31190,AMPL_WIDTH),
conv_std_logic_vector(31191,AMPL_WIDTH),
conv_std_logic_vector(31192,AMPL_WIDTH),
conv_std_logic_vector(31193,AMPL_WIDTH),
conv_std_logic_vector(31194,AMPL_WIDTH),
conv_std_logic_vector(31195,AMPL_WIDTH),
conv_std_logic_vector(31196,AMPL_WIDTH),
conv_std_logic_vector(31197,AMPL_WIDTH),
conv_std_logic_vector(31198,AMPL_WIDTH),
conv_std_logic_vector(31199,AMPL_WIDTH),
conv_std_logic_vector(31200,AMPL_WIDTH),
conv_std_logic_vector(31201,AMPL_WIDTH),
conv_std_logic_vector(31202,AMPL_WIDTH),
conv_std_logic_vector(31203,AMPL_WIDTH),
conv_std_logic_vector(31204,AMPL_WIDTH),
conv_std_logic_vector(31205,AMPL_WIDTH),
conv_std_logic_vector(31206,AMPL_WIDTH),
conv_std_logic_vector(31206,AMPL_WIDTH),
conv_std_logic_vector(31207,AMPL_WIDTH),
conv_std_logic_vector(31208,AMPL_WIDTH),
conv_std_logic_vector(31209,AMPL_WIDTH),
conv_std_logic_vector(31210,AMPL_WIDTH),
conv_std_logic_vector(31211,AMPL_WIDTH),
conv_std_logic_vector(31212,AMPL_WIDTH),
conv_std_logic_vector(31213,AMPL_WIDTH),
conv_std_logic_vector(31214,AMPL_WIDTH),
conv_std_logic_vector(31215,AMPL_WIDTH),
conv_std_logic_vector(31216,AMPL_WIDTH),
conv_std_logic_vector(31217,AMPL_WIDTH),
conv_std_logic_vector(31218,AMPL_WIDTH),
conv_std_logic_vector(31219,AMPL_WIDTH),
conv_std_logic_vector(31220,AMPL_WIDTH),
conv_std_logic_vector(31221,AMPL_WIDTH),
conv_std_logic_vector(31222,AMPL_WIDTH),
conv_std_logic_vector(31223,AMPL_WIDTH),
conv_std_logic_vector(31224,AMPL_WIDTH),
conv_std_logic_vector(31225,AMPL_WIDTH),
conv_std_logic_vector(31226,AMPL_WIDTH),
conv_std_logic_vector(31227,AMPL_WIDTH),
conv_std_logic_vector(31227,AMPL_WIDTH),
conv_std_logic_vector(31228,AMPL_WIDTH),
conv_std_logic_vector(31229,AMPL_WIDTH),
conv_std_logic_vector(31230,AMPL_WIDTH),
conv_std_logic_vector(31231,AMPL_WIDTH),
conv_std_logic_vector(31232,AMPL_WIDTH),
conv_std_logic_vector(31233,AMPL_WIDTH),
conv_std_logic_vector(31234,AMPL_WIDTH),
conv_std_logic_vector(31235,AMPL_WIDTH),
conv_std_logic_vector(31236,AMPL_WIDTH),
conv_std_logic_vector(31237,AMPL_WIDTH),
conv_std_logic_vector(31238,AMPL_WIDTH),
conv_std_logic_vector(31239,AMPL_WIDTH),
conv_std_logic_vector(31240,AMPL_WIDTH),
conv_std_logic_vector(31241,AMPL_WIDTH),
conv_std_logic_vector(31242,AMPL_WIDTH),
conv_std_logic_vector(31243,AMPL_WIDTH),
conv_std_logic_vector(31244,AMPL_WIDTH),
conv_std_logic_vector(31245,AMPL_WIDTH),
conv_std_logic_vector(31246,AMPL_WIDTH),
conv_std_logic_vector(31246,AMPL_WIDTH),
conv_std_logic_vector(31247,AMPL_WIDTH),
conv_std_logic_vector(31248,AMPL_WIDTH),
conv_std_logic_vector(31249,AMPL_WIDTH),
conv_std_logic_vector(31250,AMPL_WIDTH),
conv_std_logic_vector(31251,AMPL_WIDTH),
conv_std_logic_vector(31252,AMPL_WIDTH),
conv_std_logic_vector(31253,AMPL_WIDTH),
conv_std_logic_vector(31254,AMPL_WIDTH),
conv_std_logic_vector(31255,AMPL_WIDTH),
conv_std_logic_vector(31256,AMPL_WIDTH),
conv_std_logic_vector(31257,AMPL_WIDTH),
conv_std_logic_vector(31258,AMPL_WIDTH),
conv_std_logic_vector(31259,AMPL_WIDTH),
conv_std_logic_vector(31260,AMPL_WIDTH),
conv_std_logic_vector(31261,AMPL_WIDTH),
conv_std_logic_vector(31262,AMPL_WIDTH),
conv_std_logic_vector(31262,AMPL_WIDTH),
conv_std_logic_vector(31263,AMPL_WIDTH),
conv_std_logic_vector(31264,AMPL_WIDTH),
conv_std_logic_vector(31265,AMPL_WIDTH),
conv_std_logic_vector(31266,AMPL_WIDTH),
conv_std_logic_vector(31267,AMPL_WIDTH),
conv_std_logic_vector(31268,AMPL_WIDTH),
conv_std_logic_vector(31269,AMPL_WIDTH),
conv_std_logic_vector(31270,AMPL_WIDTH),
conv_std_logic_vector(31271,AMPL_WIDTH),
conv_std_logic_vector(31272,AMPL_WIDTH),
conv_std_logic_vector(31273,AMPL_WIDTH),
conv_std_logic_vector(31274,AMPL_WIDTH),
conv_std_logic_vector(31275,AMPL_WIDTH),
conv_std_logic_vector(31276,AMPL_WIDTH),
conv_std_logic_vector(31277,AMPL_WIDTH),
conv_std_logic_vector(31278,AMPL_WIDTH),
conv_std_logic_vector(31278,AMPL_WIDTH),
conv_std_logic_vector(31279,AMPL_WIDTH),
conv_std_logic_vector(31280,AMPL_WIDTH),
conv_std_logic_vector(31281,AMPL_WIDTH),
conv_std_logic_vector(31282,AMPL_WIDTH),
conv_std_logic_vector(31283,AMPL_WIDTH),
conv_std_logic_vector(31284,AMPL_WIDTH),
conv_std_logic_vector(31285,AMPL_WIDTH),
conv_std_logic_vector(31286,AMPL_WIDTH),
conv_std_logic_vector(31287,AMPL_WIDTH),
conv_std_logic_vector(31288,AMPL_WIDTH),
conv_std_logic_vector(31289,AMPL_WIDTH),
conv_std_logic_vector(31290,AMPL_WIDTH),
conv_std_logic_vector(31291,AMPL_WIDTH),
conv_std_logic_vector(31292,AMPL_WIDTH),
conv_std_logic_vector(31292,AMPL_WIDTH),
conv_std_logic_vector(31293,AMPL_WIDTH),
conv_std_logic_vector(31294,AMPL_WIDTH),
conv_std_logic_vector(31295,AMPL_WIDTH),
conv_std_logic_vector(31296,AMPL_WIDTH),
conv_std_logic_vector(31297,AMPL_WIDTH),
conv_std_logic_vector(31298,AMPL_WIDTH),
conv_std_logic_vector(31299,AMPL_WIDTH),
conv_std_logic_vector(31300,AMPL_WIDTH),
conv_std_logic_vector(31301,AMPL_WIDTH),
conv_std_logic_vector(31302,AMPL_WIDTH),
conv_std_logic_vector(31303,AMPL_WIDTH),
conv_std_logic_vector(31304,AMPL_WIDTH),
conv_std_logic_vector(31305,AMPL_WIDTH),
conv_std_logic_vector(31305,AMPL_WIDTH),
conv_std_logic_vector(31306,AMPL_WIDTH),
conv_std_logic_vector(31307,AMPL_WIDTH),
conv_std_logic_vector(31308,AMPL_WIDTH),
conv_std_logic_vector(31309,AMPL_WIDTH),
conv_std_logic_vector(31310,AMPL_WIDTH),
conv_std_logic_vector(31311,AMPL_WIDTH),
conv_std_logic_vector(31312,AMPL_WIDTH),
conv_std_logic_vector(31313,AMPL_WIDTH),
conv_std_logic_vector(31314,AMPL_WIDTH),
conv_std_logic_vector(31315,AMPL_WIDTH),
conv_std_logic_vector(31316,AMPL_WIDTH),
conv_std_logic_vector(31317,AMPL_WIDTH),
conv_std_logic_vector(31318,AMPL_WIDTH),
conv_std_logic_vector(31318,AMPL_WIDTH),
conv_std_logic_vector(31319,AMPL_WIDTH),
conv_std_logic_vector(31320,AMPL_WIDTH),
conv_std_logic_vector(31321,AMPL_WIDTH),
conv_std_logic_vector(31322,AMPL_WIDTH),
conv_std_logic_vector(31323,AMPL_WIDTH),
conv_std_logic_vector(31324,AMPL_WIDTH),
conv_std_logic_vector(31325,AMPL_WIDTH),
conv_std_logic_vector(31326,AMPL_WIDTH),
conv_std_logic_vector(31327,AMPL_WIDTH),
conv_std_logic_vector(31328,AMPL_WIDTH),
conv_std_logic_vector(31329,AMPL_WIDTH),
conv_std_logic_vector(31329,AMPL_WIDTH),
conv_std_logic_vector(31330,AMPL_WIDTH),
conv_std_logic_vector(31331,AMPL_WIDTH),
conv_std_logic_vector(31332,AMPL_WIDTH),
conv_std_logic_vector(31333,AMPL_WIDTH),
conv_std_logic_vector(31334,AMPL_WIDTH),
conv_std_logic_vector(31335,AMPL_WIDTH),
conv_std_logic_vector(31336,AMPL_WIDTH),
conv_std_logic_vector(31337,AMPL_WIDTH),
conv_std_logic_vector(31338,AMPL_WIDTH),
conv_std_logic_vector(31339,AMPL_WIDTH),
conv_std_logic_vector(31340,AMPL_WIDTH),
conv_std_logic_vector(31341,AMPL_WIDTH),
conv_std_logic_vector(31341,AMPL_WIDTH),
conv_std_logic_vector(31342,AMPL_WIDTH),
conv_std_logic_vector(31343,AMPL_WIDTH),
conv_std_logic_vector(31344,AMPL_WIDTH),
conv_std_logic_vector(31345,AMPL_WIDTH),
conv_std_logic_vector(31346,AMPL_WIDTH),
conv_std_logic_vector(31347,AMPL_WIDTH),
conv_std_logic_vector(31348,AMPL_WIDTH),
conv_std_logic_vector(31349,AMPL_WIDTH),
conv_std_logic_vector(31350,AMPL_WIDTH),
conv_std_logic_vector(31351,AMPL_WIDTH),
conv_std_logic_vector(31352,AMPL_WIDTH),
conv_std_logic_vector(31352,AMPL_WIDTH),
conv_std_logic_vector(31353,AMPL_WIDTH),
conv_std_logic_vector(31354,AMPL_WIDTH),
conv_std_logic_vector(31355,AMPL_WIDTH),
conv_std_logic_vector(31356,AMPL_WIDTH),
conv_std_logic_vector(31357,AMPL_WIDTH),
conv_std_logic_vector(31358,AMPL_WIDTH),
conv_std_logic_vector(31359,AMPL_WIDTH),
conv_std_logic_vector(31360,AMPL_WIDTH),
conv_std_logic_vector(31361,AMPL_WIDTH),
conv_std_logic_vector(31362,AMPL_WIDTH),
conv_std_logic_vector(31362,AMPL_WIDTH),
conv_std_logic_vector(31363,AMPL_WIDTH),
conv_std_logic_vector(31364,AMPL_WIDTH),
conv_std_logic_vector(31365,AMPL_WIDTH),
conv_std_logic_vector(31366,AMPL_WIDTH),
conv_std_logic_vector(31367,AMPL_WIDTH),
conv_std_logic_vector(31368,AMPL_WIDTH),
conv_std_logic_vector(31369,AMPL_WIDTH),
conv_std_logic_vector(31370,AMPL_WIDTH),
conv_std_logic_vector(31371,AMPL_WIDTH),
conv_std_logic_vector(31372,AMPL_WIDTH),
conv_std_logic_vector(31372,AMPL_WIDTH),
conv_std_logic_vector(31373,AMPL_WIDTH),
conv_std_logic_vector(31374,AMPL_WIDTH),
conv_std_logic_vector(31375,AMPL_WIDTH),
conv_std_logic_vector(31376,AMPL_WIDTH),
conv_std_logic_vector(31377,AMPL_WIDTH),
conv_std_logic_vector(31378,AMPL_WIDTH),
conv_std_logic_vector(31379,AMPL_WIDTH),
conv_std_logic_vector(31380,AMPL_WIDTH),
conv_std_logic_vector(31381,AMPL_WIDTH),
conv_std_logic_vector(31381,AMPL_WIDTH),
conv_std_logic_vector(31382,AMPL_WIDTH),
conv_std_logic_vector(31383,AMPL_WIDTH),
conv_std_logic_vector(31384,AMPL_WIDTH),
conv_std_logic_vector(31385,AMPL_WIDTH),
conv_std_logic_vector(31386,AMPL_WIDTH),
conv_std_logic_vector(31387,AMPL_WIDTH),
conv_std_logic_vector(31388,AMPL_WIDTH),
conv_std_logic_vector(31389,AMPL_WIDTH),
conv_std_logic_vector(31390,AMPL_WIDTH),
conv_std_logic_vector(31391,AMPL_WIDTH),
conv_std_logic_vector(31391,AMPL_WIDTH),
conv_std_logic_vector(31392,AMPL_WIDTH),
conv_std_logic_vector(31393,AMPL_WIDTH),
conv_std_logic_vector(31394,AMPL_WIDTH),
conv_std_logic_vector(31395,AMPL_WIDTH),
conv_std_logic_vector(31396,AMPL_WIDTH),
conv_std_logic_vector(31397,AMPL_WIDTH),
conv_std_logic_vector(31398,AMPL_WIDTH),
conv_std_logic_vector(31399,AMPL_WIDTH),
conv_std_logic_vector(31400,AMPL_WIDTH),
conv_std_logic_vector(31400,AMPL_WIDTH),
conv_std_logic_vector(31401,AMPL_WIDTH),
conv_std_logic_vector(31402,AMPL_WIDTH),
conv_std_logic_vector(31403,AMPL_WIDTH),
conv_std_logic_vector(31404,AMPL_WIDTH),
conv_std_logic_vector(31405,AMPL_WIDTH),
conv_std_logic_vector(31406,AMPL_WIDTH),
conv_std_logic_vector(31407,AMPL_WIDTH),
conv_std_logic_vector(31408,AMPL_WIDTH),
conv_std_logic_vector(31408,AMPL_WIDTH),
conv_std_logic_vector(31409,AMPL_WIDTH),
conv_std_logic_vector(31410,AMPL_WIDTH),
conv_std_logic_vector(31411,AMPL_WIDTH),
conv_std_logic_vector(31412,AMPL_WIDTH),
conv_std_logic_vector(31413,AMPL_WIDTH),
conv_std_logic_vector(31414,AMPL_WIDTH),
conv_std_logic_vector(31415,AMPL_WIDTH),
conv_std_logic_vector(31416,AMPL_WIDTH),
conv_std_logic_vector(31417,AMPL_WIDTH),
conv_std_logic_vector(31417,AMPL_WIDTH),
conv_std_logic_vector(31418,AMPL_WIDTH),
conv_std_logic_vector(31419,AMPL_WIDTH),
conv_std_logic_vector(31420,AMPL_WIDTH),
conv_std_logic_vector(31421,AMPL_WIDTH),
conv_std_logic_vector(31422,AMPL_WIDTH),
conv_std_logic_vector(31423,AMPL_WIDTH),
conv_std_logic_vector(31424,AMPL_WIDTH),
conv_std_logic_vector(31425,AMPL_WIDTH),
conv_std_logic_vector(31425,AMPL_WIDTH),
conv_std_logic_vector(31426,AMPL_WIDTH),
conv_std_logic_vector(31427,AMPL_WIDTH),
conv_std_logic_vector(31428,AMPL_WIDTH),
conv_std_logic_vector(31429,AMPL_WIDTH),
conv_std_logic_vector(31430,AMPL_WIDTH),
conv_std_logic_vector(31431,AMPL_WIDTH),
conv_std_logic_vector(31432,AMPL_WIDTH),
conv_std_logic_vector(31433,AMPL_WIDTH),
conv_std_logic_vector(31433,AMPL_WIDTH),
conv_std_logic_vector(31434,AMPL_WIDTH),
conv_std_logic_vector(31435,AMPL_WIDTH),
conv_std_logic_vector(31436,AMPL_WIDTH),
conv_std_logic_vector(31437,AMPL_WIDTH),
conv_std_logic_vector(31438,AMPL_WIDTH),
conv_std_logic_vector(31439,AMPL_WIDTH),
conv_std_logic_vector(31440,AMPL_WIDTH),
conv_std_logic_vector(31441,AMPL_WIDTH),
conv_std_logic_vector(31441,AMPL_WIDTH),
conv_std_logic_vector(31442,AMPL_WIDTH),
conv_std_logic_vector(31443,AMPL_WIDTH),
conv_std_logic_vector(31444,AMPL_WIDTH),
conv_std_logic_vector(31445,AMPL_WIDTH),
conv_std_logic_vector(31446,AMPL_WIDTH),
conv_std_logic_vector(31447,AMPL_WIDTH),
conv_std_logic_vector(31448,AMPL_WIDTH),
conv_std_logic_vector(31448,AMPL_WIDTH),
conv_std_logic_vector(31449,AMPL_WIDTH),
conv_std_logic_vector(31450,AMPL_WIDTH),
conv_std_logic_vector(31451,AMPL_WIDTH),
conv_std_logic_vector(31452,AMPL_WIDTH),
conv_std_logic_vector(31453,AMPL_WIDTH),
conv_std_logic_vector(31454,AMPL_WIDTH),
conv_std_logic_vector(31455,AMPL_WIDTH),
conv_std_logic_vector(31456,AMPL_WIDTH),
conv_std_logic_vector(31456,AMPL_WIDTH),
conv_std_logic_vector(31457,AMPL_WIDTH),
conv_std_logic_vector(31458,AMPL_WIDTH),
conv_std_logic_vector(31459,AMPL_WIDTH),
conv_std_logic_vector(31460,AMPL_WIDTH),
conv_std_logic_vector(31461,AMPL_WIDTH),
conv_std_logic_vector(31462,AMPL_WIDTH),
conv_std_logic_vector(31463,AMPL_WIDTH),
conv_std_logic_vector(31463,AMPL_WIDTH),
conv_std_logic_vector(31464,AMPL_WIDTH),
conv_std_logic_vector(31465,AMPL_WIDTH),
conv_std_logic_vector(31466,AMPL_WIDTH),
conv_std_logic_vector(31467,AMPL_WIDTH),
conv_std_logic_vector(31468,AMPL_WIDTH),
conv_std_logic_vector(31469,AMPL_WIDTH),
conv_std_logic_vector(31470,AMPL_WIDTH),
conv_std_logic_vector(31470,AMPL_WIDTH),
conv_std_logic_vector(31471,AMPL_WIDTH),
conv_std_logic_vector(31472,AMPL_WIDTH),
conv_std_logic_vector(31473,AMPL_WIDTH),
conv_std_logic_vector(31474,AMPL_WIDTH),
conv_std_logic_vector(31475,AMPL_WIDTH),
conv_std_logic_vector(31476,AMPL_WIDTH),
conv_std_logic_vector(31477,AMPL_WIDTH),
conv_std_logic_vector(31477,AMPL_WIDTH),
conv_std_logic_vector(31478,AMPL_WIDTH),
conv_std_logic_vector(31479,AMPL_WIDTH),
conv_std_logic_vector(31480,AMPL_WIDTH),
conv_std_logic_vector(31481,AMPL_WIDTH),
conv_std_logic_vector(31482,AMPL_WIDTH),
conv_std_logic_vector(31483,AMPL_WIDTH),
conv_std_logic_vector(31484,AMPL_WIDTH),
conv_std_logic_vector(31484,AMPL_WIDTH),
conv_std_logic_vector(31485,AMPL_WIDTH),
conv_std_logic_vector(31486,AMPL_WIDTH),
conv_std_logic_vector(31487,AMPL_WIDTH),
conv_std_logic_vector(31488,AMPL_WIDTH),
conv_std_logic_vector(31489,AMPL_WIDTH),
conv_std_logic_vector(31490,AMPL_WIDTH),
conv_std_logic_vector(31490,AMPL_WIDTH),
conv_std_logic_vector(31491,AMPL_WIDTH),
conv_std_logic_vector(31492,AMPL_WIDTH),
conv_std_logic_vector(31493,AMPL_WIDTH),
conv_std_logic_vector(31494,AMPL_WIDTH),
conv_std_logic_vector(31495,AMPL_WIDTH),
conv_std_logic_vector(31496,AMPL_WIDTH),
conv_std_logic_vector(31497,AMPL_WIDTH),
conv_std_logic_vector(31497,AMPL_WIDTH),
conv_std_logic_vector(31498,AMPL_WIDTH),
conv_std_logic_vector(31499,AMPL_WIDTH),
conv_std_logic_vector(31500,AMPL_WIDTH),
conv_std_logic_vector(31501,AMPL_WIDTH),
conv_std_logic_vector(31502,AMPL_WIDTH),
conv_std_logic_vector(31503,AMPL_WIDTH),
conv_std_logic_vector(31503,AMPL_WIDTH),
conv_std_logic_vector(31504,AMPL_WIDTH),
conv_std_logic_vector(31505,AMPL_WIDTH),
conv_std_logic_vector(31506,AMPL_WIDTH),
conv_std_logic_vector(31507,AMPL_WIDTH),
conv_std_logic_vector(31508,AMPL_WIDTH),
conv_std_logic_vector(31509,AMPL_WIDTH),
conv_std_logic_vector(31510,AMPL_WIDTH),
conv_std_logic_vector(31510,AMPL_WIDTH),
conv_std_logic_vector(31511,AMPL_WIDTH),
conv_std_logic_vector(31512,AMPL_WIDTH),
conv_std_logic_vector(31513,AMPL_WIDTH),
conv_std_logic_vector(31514,AMPL_WIDTH),
conv_std_logic_vector(31515,AMPL_WIDTH),
conv_std_logic_vector(31516,AMPL_WIDTH),
conv_std_logic_vector(31516,AMPL_WIDTH),
conv_std_logic_vector(31517,AMPL_WIDTH),
conv_std_logic_vector(31518,AMPL_WIDTH),
conv_std_logic_vector(31519,AMPL_WIDTH),
conv_std_logic_vector(31520,AMPL_WIDTH),
conv_std_logic_vector(31521,AMPL_WIDTH),
conv_std_logic_vector(31522,AMPL_WIDTH),
conv_std_logic_vector(31522,AMPL_WIDTH),
conv_std_logic_vector(31523,AMPL_WIDTH),
conv_std_logic_vector(31524,AMPL_WIDTH),
conv_std_logic_vector(31525,AMPL_WIDTH),
conv_std_logic_vector(31526,AMPL_WIDTH),
conv_std_logic_vector(31527,AMPL_WIDTH),
conv_std_logic_vector(31528,AMPL_WIDTH),
conv_std_logic_vector(31528,AMPL_WIDTH),
conv_std_logic_vector(31529,AMPL_WIDTH),
conv_std_logic_vector(31530,AMPL_WIDTH),
conv_std_logic_vector(31531,AMPL_WIDTH),
conv_std_logic_vector(31532,AMPL_WIDTH),
conv_std_logic_vector(31533,AMPL_WIDTH),
conv_std_logic_vector(31534,AMPL_WIDTH),
conv_std_logic_vector(31534,AMPL_WIDTH),
conv_std_logic_vector(31535,AMPL_WIDTH),
conv_std_logic_vector(31536,AMPL_WIDTH),
conv_std_logic_vector(31537,AMPL_WIDTH),
conv_std_logic_vector(31538,AMPL_WIDTH),
conv_std_logic_vector(31539,AMPL_WIDTH),
conv_std_logic_vector(31539,AMPL_WIDTH),
conv_std_logic_vector(31540,AMPL_WIDTH),
conv_std_logic_vector(31541,AMPL_WIDTH),
conv_std_logic_vector(31542,AMPL_WIDTH),
conv_std_logic_vector(31543,AMPL_WIDTH),
conv_std_logic_vector(31544,AMPL_WIDTH),
conv_std_logic_vector(31545,AMPL_WIDTH),
conv_std_logic_vector(31545,AMPL_WIDTH),
conv_std_logic_vector(31546,AMPL_WIDTH),
conv_std_logic_vector(31547,AMPL_WIDTH),
conv_std_logic_vector(31548,AMPL_WIDTH),
conv_std_logic_vector(31549,AMPL_WIDTH),
conv_std_logic_vector(31550,AMPL_WIDTH),
conv_std_logic_vector(31551,AMPL_WIDTH),
conv_std_logic_vector(31551,AMPL_WIDTH),
conv_std_logic_vector(31552,AMPL_WIDTH),
conv_std_logic_vector(31553,AMPL_WIDTH),
conv_std_logic_vector(31554,AMPL_WIDTH),
conv_std_logic_vector(31555,AMPL_WIDTH),
conv_std_logic_vector(31556,AMPL_WIDTH),
conv_std_logic_vector(31556,AMPL_WIDTH),
conv_std_logic_vector(31557,AMPL_WIDTH),
conv_std_logic_vector(31558,AMPL_WIDTH),
conv_std_logic_vector(31559,AMPL_WIDTH),
conv_std_logic_vector(31560,AMPL_WIDTH),
conv_std_logic_vector(31561,AMPL_WIDTH),
conv_std_logic_vector(31562,AMPL_WIDTH),
conv_std_logic_vector(31562,AMPL_WIDTH),
conv_std_logic_vector(31563,AMPL_WIDTH),
conv_std_logic_vector(31564,AMPL_WIDTH),
conv_std_logic_vector(31565,AMPL_WIDTH),
conv_std_logic_vector(31566,AMPL_WIDTH),
conv_std_logic_vector(31567,AMPL_WIDTH),
conv_std_logic_vector(31567,AMPL_WIDTH),
conv_std_logic_vector(31568,AMPL_WIDTH),
conv_std_logic_vector(31569,AMPL_WIDTH),
conv_std_logic_vector(31570,AMPL_WIDTH),
conv_std_logic_vector(31571,AMPL_WIDTH),
conv_std_logic_vector(31572,AMPL_WIDTH),
conv_std_logic_vector(31572,AMPL_WIDTH),
conv_std_logic_vector(31573,AMPL_WIDTH),
conv_std_logic_vector(31574,AMPL_WIDTH),
conv_std_logic_vector(31575,AMPL_WIDTH),
conv_std_logic_vector(31576,AMPL_WIDTH),
conv_std_logic_vector(31577,AMPL_WIDTH),
conv_std_logic_vector(31578,AMPL_WIDTH),
conv_std_logic_vector(31578,AMPL_WIDTH),
conv_std_logic_vector(31579,AMPL_WIDTH),
conv_std_logic_vector(31580,AMPL_WIDTH),
conv_std_logic_vector(31581,AMPL_WIDTH),
conv_std_logic_vector(31582,AMPL_WIDTH),
conv_std_logic_vector(31583,AMPL_WIDTH),
conv_std_logic_vector(31583,AMPL_WIDTH),
conv_std_logic_vector(31584,AMPL_WIDTH),
conv_std_logic_vector(31585,AMPL_WIDTH),
conv_std_logic_vector(31586,AMPL_WIDTH),
conv_std_logic_vector(31587,AMPL_WIDTH),
conv_std_logic_vector(31588,AMPL_WIDTH),
conv_std_logic_vector(31588,AMPL_WIDTH),
conv_std_logic_vector(31589,AMPL_WIDTH),
conv_std_logic_vector(31590,AMPL_WIDTH),
conv_std_logic_vector(31591,AMPL_WIDTH),
conv_std_logic_vector(31592,AMPL_WIDTH),
conv_std_logic_vector(31593,AMPL_WIDTH),
conv_std_logic_vector(31593,AMPL_WIDTH),
conv_std_logic_vector(31594,AMPL_WIDTH),
conv_std_logic_vector(31595,AMPL_WIDTH),
conv_std_logic_vector(31596,AMPL_WIDTH),
conv_std_logic_vector(31597,AMPL_WIDTH),
conv_std_logic_vector(31598,AMPL_WIDTH),
conv_std_logic_vector(31598,AMPL_WIDTH),
conv_std_logic_vector(31599,AMPL_WIDTH),
conv_std_logic_vector(31600,AMPL_WIDTH),
conv_std_logic_vector(31601,AMPL_WIDTH),
conv_std_logic_vector(31602,AMPL_WIDTH),
conv_std_logic_vector(31603,AMPL_WIDTH),
conv_std_logic_vector(31603,AMPL_WIDTH),
conv_std_logic_vector(31604,AMPL_WIDTH),
conv_std_logic_vector(31605,AMPL_WIDTH),
conv_std_logic_vector(31606,AMPL_WIDTH),
conv_std_logic_vector(31607,AMPL_WIDTH),
conv_std_logic_vector(31608,AMPL_WIDTH),
conv_std_logic_vector(31608,AMPL_WIDTH),
conv_std_logic_vector(31609,AMPL_WIDTH),
conv_std_logic_vector(31610,AMPL_WIDTH),
conv_std_logic_vector(31611,AMPL_WIDTH),
conv_std_logic_vector(31612,AMPL_WIDTH),
conv_std_logic_vector(31613,AMPL_WIDTH),
conv_std_logic_vector(31613,AMPL_WIDTH),
conv_std_logic_vector(31614,AMPL_WIDTH),
conv_std_logic_vector(31615,AMPL_WIDTH),
conv_std_logic_vector(31616,AMPL_WIDTH),
conv_std_logic_vector(31617,AMPL_WIDTH),
conv_std_logic_vector(31617,AMPL_WIDTH),
conv_std_logic_vector(31618,AMPL_WIDTH),
conv_std_logic_vector(31619,AMPL_WIDTH),
conv_std_logic_vector(31620,AMPL_WIDTH),
conv_std_logic_vector(31621,AMPL_WIDTH),
conv_std_logic_vector(31622,AMPL_WIDTH),
conv_std_logic_vector(31622,AMPL_WIDTH),
conv_std_logic_vector(31623,AMPL_WIDTH),
conv_std_logic_vector(31624,AMPL_WIDTH),
conv_std_logic_vector(31625,AMPL_WIDTH),
conv_std_logic_vector(31626,AMPL_WIDTH),
conv_std_logic_vector(31627,AMPL_WIDTH),
conv_std_logic_vector(31627,AMPL_WIDTH),
conv_std_logic_vector(31628,AMPL_WIDTH),
conv_std_logic_vector(31629,AMPL_WIDTH),
conv_std_logic_vector(31630,AMPL_WIDTH),
conv_std_logic_vector(31631,AMPL_WIDTH),
conv_std_logic_vector(31631,AMPL_WIDTH),
conv_std_logic_vector(31632,AMPL_WIDTH),
conv_std_logic_vector(31633,AMPL_WIDTH),
conv_std_logic_vector(31634,AMPL_WIDTH),
conv_std_logic_vector(31635,AMPL_WIDTH),
conv_std_logic_vector(31636,AMPL_WIDTH),
conv_std_logic_vector(31636,AMPL_WIDTH),
conv_std_logic_vector(31637,AMPL_WIDTH),
conv_std_logic_vector(31638,AMPL_WIDTH),
conv_std_logic_vector(31639,AMPL_WIDTH),
conv_std_logic_vector(31640,AMPL_WIDTH),
conv_std_logic_vector(31640,AMPL_WIDTH),
conv_std_logic_vector(31641,AMPL_WIDTH),
conv_std_logic_vector(31642,AMPL_WIDTH),
conv_std_logic_vector(31643,AMPL_WIDTH),
conv_std_logic_vector(31644,AMPL_WIDTH),
conv_std_logic_vector(31645,AMPL_WIDTH),
conv_std_logic_vector(31645,AMPL_WIDTH),
conv_std_logic_vector(31646,AMPL_WIDTH),
conv_std_logic_vector(31647,AMPL_WIDTH),
conv_std_logic_vector(31648,AMPL_WIDTH),
conv_std_logic_vector(31649,AMPL_WIDTH),
conv_std_logic_vector(31649,AMPL_WIDTH),
conv_std_logic_vector(31650,AMPL_WIDTH),
conv_std_logic_vector(31651,AMPL_WIDTH),
conv_std_logic_vector(31652,AMPL_WIDTH),
conv_std_logic_vector(31653,AMPL_WIDTH),
conv_std_logic_vector(31653,AMPL_WIDTH),
conv_std_logic_vector(31654,AMPL_WIDTH),
conv_std_logic_vector(31655,AMPL_WIDTH),
conv_std_logic_vector(31656,AMPL_WIDTH),
conv_std_logic_vector(31657,AMPL_WIDTH),
conv_std_logic_vector(31658,AMPL_WIDTH),
conv_std_logic_vector(31658,AMPL_WIDTH),
conv_std_logic_vector(31659,AMPL_WIDTH),
conv_std_logic_vector(31660,AMPL_WIDTH),
conv_std_logic_vector(31661,AMPL_WIDTH),
conv_std_logic_vector(31662,AMPL_WIDTH),
conv_std_logic_vector(31662,AMPL_WIDTH),
conv_std_logic_vector(31663,AMPL_WIDTH),
conv_std_logic_vector(31664,AMPL_WIDTH),
conv_std_logic_vector(31665,AMPL_WIDTH),
conv_std_logic_vector(31666,AMPL_WIDTH),
conv_std_logic_vector(31666,AMPL_WIDTH),
conv_std_logic_vector(31667,AMPL_WIDTH),
conv_std_logic_vector(31668,AMPL_WIDTH),
conv_std_logic_vector(31669,AMPL_WIDTH),
conv_std_logic_vector(31670,AMPL_WIDTH),
conv_std_logic_vector(31670,AMPL_WIDTH),
conv_std_logic_vector(31671,AMPL_WIDTH),
conv_std_logic_vector(31672,AMPL_WIDTH),
conv_std_logic_vector(31673,AMPL_WIDTH),
conv_std_logic_vector(31674,AMPL_WIDTH),
conv_std_logic_vector(31674,AMPL_WIDTH),
conv_std_logic_vector(31675,AMPL_WIDTH),
conv_std_logic_vector(31676,AMPL_WIDTH),
conv_std_logic_vector(31677,AMPL_WIDTH),
conv_std_logic_vector(31678,AMPL_WIDTH),
conv_std_logic_vector(31679,AMPL_WIDTH),
conv_std_logic_vector(31679,AMPL_WIDTH),
conv_std_logic_vector(31680,AMPL_WIDTH),
conv_std_logic_vector(31681,AMPL_WIDTH),
conv_std_logic_vector(31682,AMPL_WIDTH),
conv_std_logic_vector(31683,AMPL_WIDTH),
conv_std_logic_vector(31683,AMPL_WIDTH),
conv_std_logic_vector(31684,AMPL_WIDTH),
conv_std_logic_vector(31685,AMPL_WIDTH),
conv_std_logic_vector(31686,AMPL_WIDTH),
conv_std_logic_vector(31687,AMPL_WIDTH),
conv_std_logic_vector(31687,AMPL_WIDTH),
conv_std_logic_vector(31688,AMPL_WIDTH),
conv_std_logic_vector(31689,AMPL_WIDTH),
conv_std_logic_vector(31690,AMPL_WIDTH),
conv_std_logic_vector(31691,AMPL_WIDTH),
conv_std_logic_vector(31691,AMPL_WIDTH),
conv_std_logic_vector(31692,AMPL_WIDTH),
conv_std_logic_vector(31693,AMPL_WIDTH),
conv_std_logic_vector(31694,AMPL_WIDTH),
conv_std_logic_vector(31695,AMPL_WIDTH),
conv_std_logic_vector(31695,AMPL_WIDTH),
conv_std_logic_vector(31696,AMPL_WIDTH),
conv_std_logic_vector(31697,AMPL_WIDTH),
conv_std_logic_vector(31698,AMPL_WIDTH),
conv_std_logic_vector(31698,AMPL_WIDTH),
conv_std_logic_vector(31699,AMPL_WIDTH),
conv_std_logic_vector(31700,AMPL_WIDTH),
conv_std_logic_vector(31701,AMPL_WIDTH),
conv_std_logic_vector(31702,AMPL_WIDTH),
conv_std_logic_vector(31702,AMPL_WIDTH),
conv_std_logic_vector(31703,AMPL_WIDTH),
conv_std_logic_vector(31704,AMPL_WIDTH),
conv_std_logic_vector(31705,AMPL_WIDTH),
conv_std_logic_vector(31706,AMPL_WIDTH),
conv_std_logic_vector(31706,AMPL_WIDTH),
conv_std_logic_vector(31707,AMPL_WIDTH),
conv_std_logic_vector(31708,AMPL_WIDTH),
conv_std_logic_vector(31709,AMPL_WIDTH),
conv_std_logic_vector(31710,AMPL_WIDTH),
conv_std_logic_vector(31710,AMPL_WIDTH),
conv_std_logic_vector(31711,AMPL_WIDTH),
conv_std_logic_vector(31712,AMPL_WIDTH),
conv_std_logic_vector(31713,AMPL_WIDTH),
conv_std_logic_vector(31714,AMPL_WIDTH),
conv_std_logic_vector(31714,AMPL_WIDTH),
conv_std_logic_vector(31715,AMPL_WIDTH),
conv_std_logic_vector(31716,AMPL_WIDTH),
conv_std_logic_vector(31717,AMPL_WIDTH),
conv_std_logic_vector(31718,AMPL_WIDTH),
conv_std_logic_vector(31718,AMPL_WIDTH),
conv_std_logic_vector(31719,AMPL_WIDTH),
conv_std_logic_vector(31720,AMPL_WIDTH),
conv_std_logic_vector(31721,AMPL_WIDTH),
conv_std_logic_vector(31721,AMPL_WIDTH),
conv_std_logic_vector(31722,AMPL_WIDTH),
conv_std_logic_vector(31723,AMPL_WIDTH),
conv_std_logic_vector(31724,AMPL_WIDTH),
conv_std_logic_vector(31725,AMPL_WIDTH),
conv_std_logic_vector(31725,AMPL_WIDTH),
conv_std_logic_vector(31726,AMPL_WIDTH),
conv_std_logic_vector(31727,AMPL_WIDTH),
conv_std_logic_vector(31728,AMPL_WIDTH),
conv_std_logic_vector(31729,AMPL_WIDTH),
conv_std_logic_vector(31729,AMPL_WIDTH),
conv_std_logic_vector(31730,AMPL_WIDTH),
conv_std_logic_vector(31731,AMPL_WIDTH),
conv_std_logic_vector(31732,AMPL_WIDTH),
conv_std_logic_vector(31732,AMPL_WIDTH),
conv_std_logic_vector(31733,AMPL_WIDTH),
conv_std_logic_vector(31734,AMPL_WIDTH),
conv_std_logic_vector(31735,AMPL_WIDTH),
conv_std_logic_vector(31736,AMPL_WIDTH),
conv_std_logic_vector(31736,AMPL_WIDTH),
conv_std_logic_vector(31737,AMPL_WIDTH),
conv_std_logic_vector(31738,AMPL_WIDTH),
conv_std_logic_vector(31739,AMPL_WIDTH),
conv_std_logic_vector(31739,AMPL_WIDTH),
conv_std_logic_vector(31740,AMPL_WIDTH),
conv_std_logic_vector(31741,AMPL_WIDTH),
conv_std_logic_vector(31742,AMPL_WIDTH),
conv_std_logic_vector(31743,AMPL_WIDTH),
conv_std_logic_vector(31743,AMPL_WIDTH),
conv_std_logic_vector(31744,AMPL_WIDTH),
conv_std_logic_vector(31745,AMPL_WIDTH),
conv_std_logic_vector(31746,AMPL_WIDTH),
conv_std_logic_vector(31746,AMPL_WIDTH),
conv_std_logic_vector(31747,AMPL_WIDTH),
conv_std_logic_vector(31748,AMPL_WIDTH),
conv_std_logic_vector(31749,AMPL_WIDTH),
conv_std_logic_vector(31750,AMPL_WIDTH),
conv_std_logic_vector(31750,AMPL_WIDTH),
conv_std_logic_vector(31751,AMPL_WIDTH),
conv_std_logic_vector(31752,AMPL_WIDTH),
conv_std_logic_vector(31753,AMPL_WIDTH),
conv_std_logic_vector(31753,AMPL_WIDTH),
conv_std_logic_vector(31754,AMPL_WIDTH),
conv_std_logic_vector(31755,AMPL_WIDTH),
conv_std_logic_vector(31756,AMPL_WIDTH),
conv_std_logic_vector(31757,AMPL_WIDTH),
conv_std_logic_vector(31757,AMPL_WIDTH),
conv_std_logic_vector(31758,AMPL_WIDTH),
conv_std_logic_vector(31759,AMPL_WIDTH),
conv_std_logic_vector(31760,AMPL_WIDTH),
conv_std_logic_vector(31760,AMPL_WIDTH),
conv_std_logic_vector(31761,AMPL_WIDTH),
conv_std_logic_vector(31762,AMPL_WIDTH),
conv_std_logic_vector(31763,AMPL_WIDTH),
conv_std_logic_vector(31764,AMPL_WIDTH),
conv_std_logic_vector(31764,AMPL_WIDTH),
conv_std_logic_vector(31765,AMPL_WIDTH),
conv_std_logic_vector(31766,AMPL_WIDTH),
conv_std_logic_vector(31767,AMPL_WIDTH),
conv_std_logic_vector(31767,AMPL_WIDTH),
conv_std_logic_vector(31768,AMPL_WIDTH),
conv_std_logic_vector(31769,AMPL_WIDTH),
conv_std_logic_vector(31770,AMPL_WIDTH),
conv_std_logic_vector(31770,AMPL_WIDTH),
conv_std_logic_vector(31771,AMPL_WIDTH),
conv_std_logic_vector(31772,AMPL_WIDTH),
conv_std_logic_vector(31773,AMPL_WIDTH),
conv_std_logic_vector(31774,AMPL_WIDTH),
conv_std_logic_vector(31774,AMPL_WIDTH),
conv_std_logic_vector(31775,AMPL_WIDTH),
conv_std_logic_vector(31776,AMPL_WIDTH),
conv_std_logic_vector(31777,AMPL_WIDTH),
conv_std_logic_vector(31777,AMPL_WIDTH),
conv_std_logic_vector(31778,AMPL_WIDTH),
conv_std_logic_vector(31779,AMPL_WIDTH),
conv_std_logic_vector(31780,AMPL_WIDTH),
conv_std_logic_vector(31780,AMPL_WIDTH),
conv_std_logic_vector(31781,AMPL_WIDTH),
conv_std_logic_vector(31782,AMPL_WIDTH),
conv_std_logic_vector(31783,AMPL_WIDTH),
conv_std_logic_vector(31783,AMPL_WIDTH),
conv_std_logic_vector(31784,AMPL_WIDTH),
conv_std_logic_vector(31785,AMPL_WIDTH),
conv_std_logic_vector(31786,AMPL_WIDTH),
conv_std_logic_vector(31787,AMPL_WIDTH),
conv_std_logic_vector(31787,AMPL_WIDTH),
conv_std_logic_vector(31788,AMPL_WIDTH),
conv_std_logic_vector(31789,AMPL_WIDTH),
conv_std_logic_vector(31790,AMPL_WIDTH),
conv_std_logic_vector(31790,AMPL_WIDTH),
conv_std_logic_vector(31791,AMPL_WIDTH),
conv_std_logic_vector(31792,AMPL_WIDTH),
conv_std_logic_vector(31793,AMPL_WIDTH),
conv_std_logic_vector(31793,AMPL_WIDTH),
conv_std_logic_vector(31794,AMPL_WIDTH),
conv_std_logic_vector(31795,AMPL_WIDTH),
conv_std_logic_vector(31796,AMPL_WIDTH),
conv_std_logic_vector(31796,AMPL_WIDTH),
conv_std_logic_vector(31797,AMPL_WIDTH),
conv_std_logic_vector(31798,AMPL_WIDTH),
conv_std_logic_vector(31799,AMPL_WIDTH),
conv_std_logic_vector(31799,AMPL_WIDTH),
conv_std_logic_vector(31800,AMPL_WIDTH),
conv_std_logic_vector(31801,AMPL_WIDTH),
conv_std_logic_vector(31802,AMPL_WIDTH),
conv_std_logic_vector(31802,AMPL_WIDTH),
conv_std_logic_vector(31803,AMPL_WIDTH),
conv_std_logic_vector(31804,AMPL_WIDTH),
conv_std_logic_vector(31805,AMPL_WIDTH),
conv_std_logic_vector(31806,AMPL_WIDTH),
conv_std_logic_vector(31806,AMPL_WIDTH),
conv_std_logic_vector(31807,AMPL_WIDTH),
conv_std_logic_vector(31808,AMPL_WIDTH),
conv_std_logic_vector(31809,AMPL_WIDTH),
conv_std_logic_vector(31809,AMPL_WIDTH),
conv_std_logic_vector(31810,AMPL_WIDTH),
conv_std_logic_vector(31811,AMPL_WIDTH),
conv_std_logic_vector(31812,AMPL_WIDTH),
conv_std_logic_vector(31812,AMPL_WIDTH),
conv_std_logic_vector(31813,AMPL_WIDTH),
conv_std_logic_vector(31814,AMPL_WIDTH),
conv_std_logic_vector(31815,AMPL_WIDTH),
conv_std_logic_vector(31815,AMPL_WIDTH),
conv_std_logic_vector(31816,AMPL_WIDTH),
conv_std_logic_vector(31817,AMPL_WIDTH),
conv_std_logic_vector(31818,AMPL_WIDTH),
conv_std_logic_vector(31818,AMPL_WIDTH),
conv_std_logic_vector(31819,AMPL_WIDTH),
conv_std_logic_vector(31820,AMPL_WIDTH),
conv_std_logic_vector(31821,AMPL_WIDTH),
conv_std_logic_vector(31821,AMPL_WIDTH),
conv_std_logic_vector(31822,AMPL_WIDTH),
conv_std_logic_vector(31823,AMPL_WIDTH),
conv_std_logic_vector(31824,AMPL_WIDTH),
conv_std_logic_vector(31824,AMPL_WIDTH),
conv_std_logic_vector(31825,AMPL_WIDTH),
conv_std_logic_vector(31826,AMPL_WIDTH),
conv_std_logic_vector(31827,AMPL_WIDTH),
conv_std_logic_vector(31827,AMPL_WIDTH),
conv_std_logic_vector(31828,AMPL_WIDTH),
conv_std_logic_vector(31829,AMPL_WIDTH),
conv_std_logic_vector(31830,AMPL_WIDTH),
conv_std_logic_vector(31830,AMPL_WIDTH),
conv_std_logic_vector(31831,AMPL_WIDTH),
conv_std_logic_vector(31832,AMPL_WIDTH),
conv_std_logic_vector(31833,AMPL_WIDTH),
conv_std_logic_vector(31833,AMPL_WIDTH),
conv_std_logic_vector(31834,AMPL_WIDTH),
conv_std_logic_vector(31835,AMPL_WIDTH),
conv_std_logic_vector(31836,AMPL_WIDTH),
conv_std_logic_vector(31836,AMPL_WIDTH),
conv_std_logic_vector(31837,AMPL_WIDTH),
conv_std_logic_vector(31838,AMPL_WIDTH),
conv_std_logic_vector(31838,AMPL_WIDTH),
conv_std_logic_vector(31839,AMPL_WIDTH),
conv_std_logic_vector(31840,AMPL_WIDTH),
conv_std_logic_vector(31841,AMPL_WIDTH),
conv_std_logic_vector(31841,AMPL_WIDTH),
conv_std_logic_vector(31842,AMPL_WIDTH),
conv_std_logic_vector(31843,AMPL_WIDTH),
conv_std_logic_vector(31844,AMPL_WIDTH),
conv_std_logic_vector(31844,AMPL_WIDTH),
conv_std_logic_vector(31845,AMPL_WIDTH),
conv_std_logic_vector(31846,AMPL_WIDTH),
conv_std_logic_vector(31847,AMPL_WIDTH),
conv_std_logic_vector(31847,AMPL_WIDTH),
conv_std_logic_vector(31848,AMPL_WIDTH),
conv_std_logic_vector(31849,AMPL_WIDTH),
conv_std_logic_vector(31850,AMPL_WIDTH),
conv_std_logic_vector(31850,AMPL_WIDTH),
conv_std_logic_vector(31851,AMPL_WIDTH),
conv_std_logic_vector(31852,AMPL_WIDTH),
conv_std_logic_vector(31853,AMPL_WIDTH),
conv_std_logic_vector(31853,AMPL_WIDTH),
conv_std_logic_vector(31854,AMPL_WIDTH),
conv_std_logic_vector(31855,AMPL_WIDTH),
conv_std_logic_vector(31855,AMPL_WIDTH),
conv_std_logic_vector(31856,AMPL_WIDTH),
conv_std_logic_vector(31857,AMPL_WIDTH),
conv_std_logic_vector(31858,AMPL_WIDTH),
conv_std_logic_vector(31858,AMPL_WIDTH),
conv_std_logic_vector(31859,AMPL_WIDTH),
conv_std_logic_vector(31860,AMPL_WIDTH),
conv_std_logic_vector(31861,AMPL_WIDTH),
conv_std_logic_vector(31861,AMPL_WIDTH),
conv_std_logic_vector(31862,AMPL_WIDTH),
conv_std_logic_vector(31863,AMPL_WIDTH),
conv_std_logic_vector(31864,AMPL_WIDTH),
conv_std_logic_vector(31864,AMPL_WIDTH),
conv_std_logic_vector(31865,AMPL_WIDTH),
conv_std_logic_vector(31866,AMPL_WIDTH),
conv_std_logic_vector(31866,AMPL_WIDTH),
conv_std_logic_vector(31867,AMPL_WIDTH),
conv_std_logic_vector(31868,AMPL_WIDTH),
conv_std_logic_vector(31869,AMPL_WIDTH),
conv_std_logic_vector(31869,AMPL_WIDTH),
conv_std_logic_vector(31870,AMPL_WIDTH),
conv_std_logic_vector(31871,AMPL_WIDTH),
conv_std_logic_vector(31872,AMPL_WIDTH),
conv_std_logic_vector(31872,AMPL_WIDTH),
conv_std_logic_vector(31873,AMPL_WIDTH),
conv_std_logic_vector(31874,AMPL_WIDTH),
conv_std_logic_vector(31875,AMPL_WIDTH),
conv_std_logic_vector(31875,AMPL_WIDTH),
conv_std_logic_vector(31876,AMPL_WIDTH),
conv_std_logic_vector(31877,AMPL_WIDTH),
conv_std_logic_vector(31877,AMPL_WIDTH),
conv_std_logic_vector(31878,AMPL_WIDTH),
conv_std_logic_vector(31879,AMPL_WIDTH),
conv_std_logic_vector(31880,AMPL_WIDTH),
conv_std_logic_vector(31880,AMPL_WIDTH),
conv_std_logic_vector(31881,AMPL_WIDTH),
conv_std_logic_vector(31882,AMPL_WIDTH),
conv_std_logic_vector(31882,AMPL_WIDTH),
conv_std_logic_vector(31883,AMPL_WIDTH),
conv_std_logic_vector(31884,AMPL_WIDTH),
conv_std_logic_vector(31885,AMPL_WIDTH),
conv_std_logic_vector(31885,AMPL_WIDTH),
conv_std_logic_vector(31886,AMPL_WIDTH),
conv_std_logic_vector(31887,AMPL_WIDTH),
conv_std_logic_vector(31888,AMPL_WIDTH),
conv_std_logic_vector(31888,AMPL_WIDTH),
conv_std_logic_vector(31889,AMPL_WIDTH),
conv_std_logic_vector(31890,AMPL_WIDTH),
conv_std_logic_vector(31890,AMPL_WIDTH),
conv_std_logic_vector(31891,AMPL_WIDTH),
conv_std_logic_vector(31892,AMPL_WIDTH),
conv_std_logic_vector(31893,AMPL_WIDTH),
conv_std_logic_vector(31893,AMPL_WIDTH),
conv_std_logic_vector(31894,AMPL_WIDTH),
conv_std_logic_vector(31895,AMPL_WIDTH),
conv_std_logic_vector(31896,AMPL_WIDTH),
conv_std_logic_vector(31896,AMPL_WIDTH),
conv_std_logic_vector(31897,AMPL_WIDTH),
conv_std_logic_vector(31898,AMPL_WIDTH),
conv_std_logic_vector(31898,AMPL_WIDTH),
conv_std_logic_vector(31899,AMPL_WIDTH),
conv_std_logic_vector(31900,AMPL_WIDTH),
conv_std_logic_vector(31901,AMPL_WIDTH),
conv_std_logic_vector(31901,AMPL_WIDTH),
conv_std_logic_vector(31902,AMPL_WIDTH),
conv_std_logic_vector(31903,AMPL_WIDTH),
conv_std_logic_vector(31903,AMPL_WIDTH),
conv_std_logic_vector(31904,AMPL_WIDTH),
conv_std_logic_vector(31905,AMPL_WIDTH),
conv_std_logic_vector(31906,AMPL_WIDTH),
conv_std_logic_vector(31906,AMPL_WIDTH),
conv_std_logic_vector(31907,AMPL_WIDTH),
conv_std_logic_vector(31908,AMPL_WIDTH),
conv_std_logic_vector(31908,AMPL_WIDTH),
conv_std_logic_vector(31909,AMPL_WIDTH),
conv_std_logic_vector(31910,AMPL_WIDTH),
conv_std_logic_vector(31911,AMPL_WIDTH),
conv_std_logic_vector(31911,AMPL_WIDTH),
conv_std_logic_vector(31912,AMPL_WIDTH),
conv_std_logic_vector(31913,AMPL_WIDTH),
conv_std_logic_vector(31913,AMPL_WIDTH),
conv_std_logic_vector(31914,AMPL_WIDTH),
conv_std_logic_vector(31915,AMPL_WIDTH),
conv_std_logic_vector(31916,AMPL_WIDTH),
conv_std_logic_vector(31916,AMPL_WIDTH),
conv_std_logic_vector(31917,AMPL_WIDTH),
conv_std_logic_vector(31918,AMPL_WIDTH),
conv_std_logic_vector(31918,AMPL_WIDTH),
conv_std_logic_vector(31919,AMPL_WIDTH),
conv_std_logic_vector(31920,AMPL_WIDTH),
conv_std_logic_vector(31921,AMPL_WIDTH),
conv_std_logic_vector(31921,AMPL_WIDTH),
conv_std_logic_vector(31922,AMPL_WIDTH),
conv_std_logic_vector(31923,AMPL_WIDTH),
conv_std_logic_vector(31923,AMPL_WIDTH),
conv_std_logic_vector(31924,AMPL_WIDTH),
conv_std_logic_vector(31925,AMPL_WIDTH),
conv_std_logic_vector(31925,AMPL_WIDTH),
conv_std_logic_vector(31926,AMPL_WIDTH),
conv_std_logic_vector(31927,AMPL_WIDTH),
conv_std_logic_vector(31928,AMPL_WIDTH),
conv_std_logic_vector(31928,AMPL_WIDTH),
conv_std_logic_vector(31929,AMPL_WIDTH),
conv_std_logic_vector(31930,AMPL_WIDTH),
conv_std_logic_vector(31930,AMPL_WIDTH),
conv_std_logic_vector(31931,AMPL_WIDTH),
conv_std_logic_vector(31932,AMPL_WIDTH),
conv_std_logic_vector(31933,AMPL_WIDTH),
conv_std_logic_vector(31933,AMPL_WIDTH),
conv_std_logic_vector(31934,AMPL_WIDTH),
conv_std_logic_vector(31935,AMPL_WIDTH),
conv_std_logic_vector(31935,AMPL_WIDTH),
conv_std_logic_vector(31936,AMPL_WIDTH),
conv_std_logic_vector(31937,AMPL_WIDTH),
conv_std_logic_vector(31937,AMPL_WIDTH),
conv_std_logic_vector(31938,AMPL_WIDTH),
conv_std_logic_vector(31939,AMPL_WIDTH),
conv_std_logic_vector(31940,AMPL_WIDTH),
conv_std_logic_vector(31940,AMPL_WIDTH),
conv_std_logic_vector(31941,AMPL_WIDTH),
conv_std_logic_vector(31942,AMPL_WIDTH),
conv_std_logic_vector(31942,AMPL_WIDTH),
conv_std_logic_vector(31943,AMPL_WIDTH),
conv_std_logic_vector(31944,AMPL_WIDTH),
conv_std_logic_vector(31944,AMPL_WIDTH),
conv_std_logic_vector(31945,AMPL_WIDTH),
conv_std_logic_vector(31946,AMPL_WIDTH),
conv_std_logic_vector(31947,AMPL_WIDTH),
conv_std_logic_vector(31947,AMPL_WIDTH),
conv_std_logic_vector(31948,AMPL_WIDTH),
conv_std_logic_vector(31949,AMPL_WIDTH),
conv_std_logic_vector(31949,AMPL_WIDTH),
conv_std_logic_vector(31950,AMPL_WIDTH),
conv_std_logic_vector(31951,AMPL_WIDTH),
conv_std_logic_vector(31951,AMPL_WIDTH),
conv_std_logic_vector(31952,AMPL_WIDTH),
conv_std_logic_vector(31953,AMPL_WIDTH),
conv_std_logic_vector(31954,AMPL_WIDTH),
conv_std_logic_vector(31954,AMPL_WIDTH),
conv_std_logic_vector(31955,AMPL_WIDTH),
conv_std_logic_vector(31956,AMPL_WIDTH),
conv_std_logic_vector(31956,AMPL_WIDTH),
conv_std_logic_vector(31957,AMPL_WIDTH),
conv_std_logic_vector(31958,AMPL_WIDTH),
conv_std_logic_vector(31958,AMPL_WIDTH),
conv_std_logic_vector(31959,AMPL_WIDTH),
conv_std_logic_vector(31960,AMPL_WIDTH),
conv_std_logic_vector(31960,AMPL_WIDTH),
conv_std_logic_vector(31961,AMPL_WIDTH),
conv_std_logic_vector(31962,AMPL_WIDTH),
conv_std_logic_vector(31963,AMPL_WIDTH),
conv_std_logic_vector(31963,AMPL_WIDTH),
conv_std_logic_vector(31964,AMPL_WIDTH),
conv_std_logic_vector(31965,AMPL_WIDTH),
conv_std_logic_vector(31965,AMPL_WIDTH),
conv_std_logic_vector(31966,AMPL_WIDTH),
conv_std_logic_vector(31967,AMPL_WIDTH),
conv_std_logic_vector(31967,AMPL_WIDTH),
conv_std_logic_vector(31968,AMPL_WIDTH),
conv_std_logic_vector(31969,AMPL_WIDTH),
conv_std_logic_vector(31969,AMPL_WIDTH),
conv_std_logic_vector(31970,AMPL_WIDTH),
conv_std_logic_vector(31971,AMPL_WIDTH),
conv_std_logic_vector(31972,AMPL_WIDTH),
conv_std_logic_vector(31972,AMPL_WIDTH),
conv_std_logic_vector(31973,AMPL_WIDTH),
conv_std_logic_vector(31974,AMPL_WIDTH),
conv_std_logic_vector(31974,AMPL_WIDTH),
conv_std_logic_vector(31975,AMPL_WIDTH),
conv_std_logic_vector(31976,AMPL_WIDTH),
conv_std_logic_vector(31976,AMPL_WIDTH),
conv_std_logic_vector(31977,AMPL_WIDTH),
conv_std_logic_vector(31978,AMPL_WIDTH),
conv_std_logic_vector(31978,AMPL_WIDTH),
conv_std_logic_vector(31979,AMPL_WIDTH),
conv_std_logic_vector(31980,AMPL_WIDTH),
conv_std_logic_vector(31980,AMPL_WIDTH),
conv_std_logic_vector(31981,AMPL_WIDTH),
conv_std_logic_vector(31982,AMPL_WIDTH),
conv_std_logic_vector(31982,AMPL_WIDTH),
conv_std_logic_vector(31983,AMPL_WIDTH),
conv_std_logic_vector(31984,AMPL_WIDTH),
conv_std_logic_vector(31985,AMPL_WIDTH),
conv_std_logic_vector(31985,AMPL_WIDTH),
conv_std_logic_vector(31986,AMPL_WIDTH),
conv_std_logic_vector(31987,AMPL_WIDTH),
conv_std_logic_vector(31987,AMPL_WIDTH),
conv_std_logic_vector(31988,AMPL_WIDTH),
conv_std_logic_vector(31989,AMPL_WIDTH),
conv_std_logic_vector(31989,AMPL_WIDTH),
conv_std_logic_vector(31990,AMPL_WIDTH),
conv_std_logic_vector(31991,AMPL_WIDTH),
conv_std_logic_vector(31991,AMPL_WIDTH),
conv_std_logic_vector(31992,AMPL_WIDTH),
conv_std_logic_vector(31993,AMPL_WIDTH),
conv_std_logic_vector(31993,AMPL_WIDTH),
conv_std_logic_vector(31994,AMPL_WIDTH),
conv_std_logic_vector(31995,AMPL_WIDTH),
conv_std_logic_vector(31995,AMPL_WIDTH),
conv_std_logic_vector(31996,AMPL_WIDTH),
conv_std_logic_vector(31997,AMPL_WIDTH),
conv_std_logic_vector(31997,AMPL_WIDTH),
conv_std_logic_vector(31998,AMPL_WIDTH),
conv_std_logic_vector(31999,AMPL_WIDTH),
conv_std_logic_vector(31999,AMPL_WIDTH),
conv_std_logic_vector(32000,AMPL_WIDTH),
conv_std_logic_vector(32001,AMPL_WIDTH),
conv_std_logic_vector(32002,AMPL_WIDTH),
conv_std_logic_vector(32002,AMPL_WIDTH),
conv_std_logic_vector(32003,AMPL_WIDTH),
conv_std_logic_vector(32004,AMPL_WIDTH),
conv_std_logic_vector(32004,AMPL_WIDTH),
conv_std_logic_vector(32005,AMPL_WIDTH),
conv_std_logic_vector(32006,AMPL_WIDTH),
conv_std_logic_vector(32006,AMPL_WIDTH),
conv_std_logic_vector(32007,AMPL_WIDTH),
conv_std_logic_vector(32008,AMPL_WIDTH),
conv_std_logic_vector(32008,AMPL_WIDTH),
conv_std_logic_vector(32009,AMPL_WIDTH),
conv_std_logic_vector(32010,AMPL_WIDTH),
conv_std_logic_vector(32010,AMPL_WIDTH),
conv_std_logic_vector(32011,AMPL_WIDTH),
conv_std_logic_vector(32012,AMPL_WIDTH),
conv_std_logic_vector(32012,AMPL_WIDTH),
conv_std_logic_vector(32013,AMPL_WIDTH),
conv_std_logic_vector(32014,AMPL_WIDTH),
conv_std_logic_vector(32014,AMPL_WIDTH),
conv_std_logic_vector(32015,AMPL_WIDTH),
conv_std_logic_vector(32016,AMPL_WIDTH),
conv_std_logic_vector(32016,AMPL_WIDTH),
conv_std_logic_vector(32017,AMPL_WIDTH),
conv_std_logic_vector(32018,AMPL_WIDTH),
conv_std_logic_vector(32018,AMPL_WIDTH),
conv_std_logic_vector(32019,AMPL_WIDTH),
conv_std_logic_vector(32020,AMPL_WIDTH),
conv_std_logic_vector(32020,AMPL_WIDTH),
conv_std_logic_vector(32021,AMPL_WIDTH),
conv_std_logic_vector(32022,AMPL_WIDTH),
conv_std_logic_vector(32022,AMPL_WIDTH),
conv_std_logic_vector(32023,AMPL_WIDTH),
conv_std_logic_vector(32024,AMPL_WIDTH),
conv_std_logic_vector(32024,AMPL_WIDTH),
conv_std_logic_vector(32025,AMPL_WIDTH),
conv_std_logic_vector(32026,AMPL_WIDTH),
conv_std_logic_vector(32026,AMPL_WIDTH),
conv_std_logic_vector(32027,AMPL_WIDTH),
conv_std_logic_vector(32028,AMPL_WIDTH),
conv_std_logic_vector(32028,AMPL_WIDTH),
conv_std_logic_vector(32029,AMPL_WIDTH),
conv_std_logic_vector(32030,AMPL_WIDTH),
conv_std_logic_vector(32030,AMPL_WIDTH),
conv_std_logic_vector(32031,AMPL_WIDTH),
conv_std_logic_vector(32032,AMPL_WIDTH),
conv_std_logic_vector(32032,AMPL_WIDTH),
conv_std_logic_vector(32033,AMPL_WIDTH),
conv_std_logic_vector(32034,AMPL_WIDTH),
conv_std_logic_vector(32034,AMPL_WIDTH),
conv_std_logic_vector(32035,AMPL_WIDTH),
conv_std_logic_vector(32036,AMPL_WIDTH),
conv_std_logic_vector(32036,AMPL_WIDTH),
conv_std_logic_vector(32037,AMPL_WIDTH),
conv_std_logic_vector(32038,AMPL_WIDTH),
conv_std_logic_vector(32038,AMPL_WIDTH),
conv_std_logic_vector(32039,AMPL_WIDTH),
conv_std_logic_vector(32040,AMPL_WIDTH),
conv_std_logic_vector(32040,AMPL_WIDTH),
conv_std_logic_vector(32041,AMPL_WIDTH),
conv_std_logic_vector(32041,AMPL_WIDTH),
conv_std_logic_vector(32042,AMPL_WIDTH),
conv_std_logic_vector(32043,AMPL_WIDTH),
conv_std_logic_vector(32043,AMPL_WIDTH),
conv_std_logic_vector(32044,AMPL_WIDTH),
conv_std_logic_vector(32045,AMPL_WIDTH),
conv_std_logic_vector(32045,AMPL_WIDTH),
conv_std_logic_vector(32046,AMPL_WIDTH),
conv_std_logic_vector(32047,AMPL_WIDTH),
conv_std_logic_vector(32047,AMPL_WIDTH),
conv_std_logic_vector(32048,AMPL_WIDTH),
conv_std_logic_vector(32049,AMPL_WIDTH),
conv_std_logic_vector(32049,AMPL_WIDTH),
conv_std_logic_vector(32050,AMPL_WIDTH),
conv_std_logic_vector(32051,AMPL_WIDTH),
conv_std_logic_vector(32051,AMPL_WIDTH),
conv_std_logic_vector(32052,AMPL_WIDTH),
conv_std_logic_vector(32053,AMPL_WIDTH),
conv_std_logic_vector(32053,AMPL_WIDTH),
conv_std_logic_vector(32054,AMPL_WIDTH),
conv_std_logic_vector(32055,AMPL_WIDTH),
conv_std_logic_vector(32055,AMPL_WIDTH),
conv_std_logic_vector(32056,AMPL_WIDTH),
conv_std_logic_vector(32057,AMPL_WIDTH),
conv_std_logic_vector(32057,AMPL_WIDTH),
conv_std_logic_vector(32058,AMPL_WIDTH),
conv_std_logic_vector(32058,AMPL_WIDTH),
conv_std_logic_vector(32059,AMPL_WIDTH),
conv_std_logic_vector(32060,AMPL_WIDTH),
conv_std_logic_vector(32060,AMPL_WIDTH),
conv_std_logic_vector(32061,AMPL_WIDTH),
conv_std_logic_vector(32062,AMPL_WIDTH),
conv_std_logic_vector(32062,AMPL_WIDTH),
conv_std_logic_vector(32063,AMPL_WIDTH),
conv_std_logic_vector(32064,AMPL_WIDTH),
conv_std_logic_vector(32064,AMPL_WIDTH),
conv_std_logic_vector(32065,AMPL_WIDTH),
conv_std_logic_vector(32066,AMPL_WIDTH),
conv_std_logic_vector(32066,AMPL_WIDTH),
conv_std_logic_vector(32067,AMPL_WIDTH),
conv_std_logic_vector(32068,AMPL_WIDTH),
conv_std_logic_vector(32068,AMPL_WIDTH),
conv_std_logic_vector(32069,AMPL_WIDTH),
conv_std_logic_vector(32069,AMPL_WIDTH),
conv_std_logic_vector(32070,AMPL_WIDTH),
conv_std_logic_vector(32071,AMPL_WIDTH),
conv_std_logic_vector(32071,AMPL_WIDTH),
conv_std_logic_vector(32072,AMPL_WIDTH),
conv_std_logic_vector(32073,AMPL_WIDTH),
conv_std_logic_vector(32073,AMPL_WIDTH),
conv_std_logic_vector(32074,AMPL_WIDTH),
conv_std_logic_vector(32075,AMPL_WIDTH),
conv_std_logic_vector(32075,AMPL_WIDTH),
conv_std_logic_vector(32076,AMPL_WIDTH),
conv_std_logic_vector(32077,AMPL_WIDTH),
conv_std_logic_vector(32077,AMPL_WIDTH),
conv_std_logic_vector(32078,AMPL_WIDTH),
conv_std_logic_vector(32078,AMPL_WIDTH),
conv_std_logic_vector(32079,AMPL_WIDTH),
conv_std_logic_vector(32080,AMPL_WIDTH),
conv_std_logic_vector(32080,AMPL_WIDTH),
conv_std_logic_vector(32081,AMPL_WIDTH),
conv_std_logic_vector(32082,AMPL_WIDTH),
conv_std_logic_vector(32082,AMPL_WIDTH),
conv_std_logic_vector(32083,AMPL_WIDTH),
conv_std_logic_vector(32084,AMPL_WIDTH),
conv_std_logic_vector(32084,AMPL_WIDTH),
conv_std_logic_vector(32085,AMPL_WIDTH),
conv_std_logic_vector(32086,AMPL_WIDTH),
conv_std_logic_vector(32086,AMPL_WIDTH),
conv_std_logic_vector(32087,AMPL_WIDTH),
conv_std_logic_vector(32087,AMPL_WIDTH),
conv_std_logic_vector(32088,AMPL_WIDTH),
conv_std_logic_vector(32089,AMPL_WIDTH),
conv_std_logic_vector(32089,AMPL_WIDTH),
conv_std_logic_vector(32090,AMPL_WIDTH),
conv_std_logic_vector(32091,AMPL_WIDTH),
conv_std_logic_vector(32091,AMPL_WIDTH),
conv_std_logic_vector(32092,AMPL_WIDTH),
conv_std_logic_vector(32092,AMPL_WIDTH),
conv_std_logic_vector(32093,AMPL_WIDTH),
conv_std_logic_vector(32094,AMPL_WIDTH),
conv_std_logic_vector(32094,AMPL_WIDTH),
conv_std_logic_vector(32095,AMPL_WIDTH),
conv_std_logic_vector(32096,AMPL_WIDTH),
conv_std_logic_vector(32096,AMPL_WIDTH),
conv_std_logic_vector(32097,AMPL_WIDTH),
conv_std_logic_vector(32098,AMPL_WIDTH),
conv_std_logic_vector(32098,AMPL_WIDTH),
conv_std_logic_vector(32099,AMPL_WIDTH),
conv_std_logic_vector(32099,AMPL_WIDTH),
conv_std_logic_vector(32100,AMPL_WIDTH),
conv_std_logic_vector(32101,AMPL_WIDTH),
conv_std_logic_vector(32101,AMPL_WIDTH),
conv_std_logic_vector(32102,AMPL_WIDTH),
conv_std_logic_vector(32103,AMPL_WIDTH),
conv_std_logic_vector(32103,AMPL_WIDTH),
conv_std_logic_vector(32104,AMPL_WIDTH),
conv_std_logic_vector(32104,AMPL_WIDTH),
conv_std_logic_vector(32105,AMPL_WIDTH),
conv_std_logic_vector(32106,AMPL_WIDTH),
conv_std_logic_vector(32106,AMPL_WIDTH),
conv_std_logic_vector(32107,AMPL_WIDTH),
conv_std_logic_vector(32108,AMPL_WIDTH),
conv_std_logic_vector(32108,AMPL_WIDTH),
conv_std_logic_vector(32109,AMPL_WIDTH),
conv_std_logic_vector(32110,AMPL_WIDTH),
conv_std_logic_vector(32110,AMPL_WIDTH),
conv_std_logic_vector(32111,AMPL_WIDTH),
conv_std_logic_vector(32111,AMPL_WIDTH),
conv_std_logic_vector(32112,AMPL_WIDTH),
conv_std_logic_vector(32113,AMPL_WIDTH),
conv_std_logic_vector(32113,AMPL_WIDTH),
conv_std_logic_vector(32114,AMPL_WIDTH),
conv_std_logic_vector(32115,AMPL_WIDTH),
conv_std_logic_vector(32115,AMPL_WIDTH),
conv_std_logic_vector(32116,AMPL_WIDTH),
conv_std_logic_vector(32116,AMPL_WIDTH),
conv_std_logic_vector(32117,AMPL_WIDTH),
conv_std_logic_vector(32118,AMPL_WIDTH),
conv_std_logic_vector(32118,AMPL_WIDTH),
conv_std_logic_vector(32119,AMPL_WIDTH),
conv_std_logic_vector(32119,AMPL_WIDTH),
conv_std_logic_vector(32120,AMPL_WIDTH),
conv_std_logic_vector(32121,AMPL_WIDTH),
conv_std_logic_vector(32121,AMPL_WIDTH),
conv_std_logic_vector(32122,AMPL_WIDTH),
conv_std_logic_vector(32123,AMPL_WIDTH),
conv_std_logic_vector(32123,AMPL_WIDTH),
conv_std_logic_vector(32124,AMPL_WIDTH),
conv_std_logic_vector(32124,AMPL_WIDTH),
conv_std_logic_vector(32125,AMPL_WIDTH),
conv_std_logic_vector(32126,AMPL_WIDTH),
conv_std_logic_vector(32126,AMPL_WIDTH),
conv_std_logic_vector(32127,AMPL_WIDTH),
conv_std_logic_vector(32128,AMPL_WIDTH),
conv_std_logic_vector(32128,AMPL_WIDTH),
conv_std_logic_vector(32129,AMPL_WIDTH),
conv_std_logic_vector(32129,AMPL_WIDTH),
conv_std_logic_vector(32130,AMPL_WIDTH),
conv_std_logic_vector(32131,AMPL_WIDTH),
conv_std_logic_vector(32131,AMPL_WIDTH),
conv_std_logic_vector(32132,AMPL_WIDTH),
conv_std_logic_vector(32132,AMPL_WIDTH),
conv_std_logic_vector(32133,AMPL_WIDTH),
conv_std_logic_vector(32134,AMPL_WIDTH),
conv_std_logic_vector(32134,AMPL_WIDTH),
conv_std_logic_vector(32135,AMPL_WIDTH),
conv_std_logic_vector(32136,AMPL_WIDTH),
conv_std_logic_vector(32136,AMPL_WIDTH),
conv_std_logic_vector(32137,AMPL_WIDTH),
conv_std_logic_vector(32137,AMPL_WIDTH),
conv_std_logic_vector(32138,AMPL_WIDTH),
conv_std_logic_vector(32139,AMPL_WIDTH),
conv_std_logic_vector(32139,AMPL_WIDTH),
conv_std_logic_vector(32140,AMPL_WIDTH),
conv_std_logic_vector(32140,AMPL_WIDTH),
conv_std_logic_vector(32141,AMPL_WIDTH),
conv_std_logic_vector(32142,AMPL_WIDTH),
conv_std_logic_vector(32142,AMPL_WIDTH),
conv_std_logic_vector(32143,AMPL_WIDTH),
conv_std_logic_vector(32144,AMPL_WIDTH),
conv_std_logic_vector(32144,AMPL_WIDTH),
conv_std_logic_vector(32145,AMPL_WIDTH),
conv_std_logic_vector(32145,AMPL_WIDTH),
conv_std_logic_vector(32146,AMPL_WIDTH),
conv_std_logic_vector(32147,AMPL_WIDTH),
conv_std_logic_vector(32147,AMPL_WIDTH),
conv_std_logic_vector(32148,AMPL_WIDTH),
conv_std_logic_vector(32148,AMPL_WIDTH),
conv_std_logic_vector(32149,AMPL_WIDTH),
conv_std_logic_vector(32150,AMPL_WIDTH),
conv_std_logic_vector(32150,AMPL_WIDTH),
conv_std_logic_vector(32151,AMPL_WIDTH),
conv_std_logic_vector(32151,AMPL_WIDTH),
conv_std_logic_vector(32152,AMPL_WIDTH),
conv_std_logic_vector(32153,AMPL_WIDTH),
conv_std_logic_vector(32153,AMPL_WIDTH),
conv_std_logic_vector(32154,AMPL_WIDTH),
conv_std_logic_vector(32154,AMPL_WIDTH),
conv_std_logic_vector(32155,AMPL_WIDTH),
conv_std_logic_vector(32156,AMPL_WIDTH),
conv_std_logic_vector(32156,AMPL_WIDTH),
conv_std_logic_vector(32157,AMPL_WIDTH),
conv_std_logic_vector(32157,AMPL_WIDTH),
conv_std_logic_vector(32158,AMPL_WIDTH),
conv_std_logic_vector(32159,AMPL_WIDTH),
conv_std_logic_vector(32159,AMPL_WIDTH),
conv_std_logic_vector(32160,AMPL_WIDTH),
conv_std_logic_vector(32160,AMPL_WIDTH),
conv_std_logic_vector(32161,AMPL_WIDTH),
conv_std_logic_vector(32162,AMPL_WIDTH),
conv_std_logic_vector(32162,AMPL_WIDTH),
conv_std_logic_vector(32163,AMPL_WIDTH),
conv_std_logic_vector(32163,AMPL_WIDTH),
conv_std_logic_vector(32164,AMPL_WIDTH),
conv_std_logic_vector(32165,AMPL_WIDTH),
conv_std_logic_vector(32165,AMPL_WIDTH),
conv_std_logic_vector(32166,AMPL_WIDTH),
conv_std_logic_vector(32166,AMPL_WIDTH),
conv_std_logic_vector(32167,AMPL_WIDTH),
conv_std_logic_vector(32168,AMPL_WIDTH),
conv_std_logic_vector(32168,AMPL_WIDTH),
conv_std_logic_vector(32169,AMPL_WIDTH),
conv_std_logic_vector(32169,AMPL_WIDTH),
conv_std_logic_vector(32170,AMPL_WIDTH),
conv_std_logic_vector(32171,AMPL_WIDTH),
conv_std_logic_vector(32171,AMPL_WIDTH),
conv_std_logic_vector(32172,AMPL_WIDTH),
conv_std_logic_vector(32172,AMPL_WIDTH),
conv_std_logic_vector(32173,AMPL_WIDTH),
conv_std_logic_vector(32174,AMPL_WIDTH),
conv_std_logic_vector(32174,AMPL_WIDTH),
conv_std_logic_vector(32175,AMPL_WIDTH),
conv_std_logic_vector(32175,AMPL_WIDTH),
conv_std_logic_vector(32176,AMPL_WIDTH),
conv_std_logic_vector(32177,AMPL_WIDTH),
conv_std_logic_vector(32177,AMPL_WIDTH),
conv_std_logic_vector(32178,AMPL_WIDTH),
conv_std_logic_vector(32178,AMPL_WIDTH),
conv_std_logic_vector(32179,AMPL_WIDTH),
conv_std_logic_vector(32180,AMPL_WIDTH),
conv_std_logic_vector(32180,AMPL_WIDTH),
conv_std_logic_vector(32181,AMPL_WIDTH),
conv_std_logic_vector(32181,AMPL_WIDTH),
conv_std_logic_vector(32182,AMPL_WIDTH),
conv_std_logic_vector(32183,AMPL_WIDTH),
conv_std_logic_vector(32183,AMPL_WIDTH),
conv_std_logic_vector(32184,AMPL_WIDTH),
conv_std_logic_vector(32184,AMPL_WIDTH),
conv_std_logic_vector(32185,AMPL_WIDTH),
conv_std_logic_vector(32185,AMPL_WIDTH),
conv_std_logic_vector(32186,AMPL_WIDTH),
conv_std_logic_vector(32187,AMPL_WIDTH),
conv_std_logic_vector(32187,AMPL_WIDTH),
conv_std_logic_vector(32188,AMPL_WIDTH),
conv_std_logic_vector(32188,AMPL_WIDTH),
conv_std_logic_vector(32189,AMPL_WIDTH),
conv_std_logic_vector(32190,AMPL_WIDTH),
conv_std_logic_vector(32190,AMPL_WIDTH),
conv_std_logic_vector(32191,AMPL_WIDTH),
conv_std_logic_vector(32191,AMPL_WIDTH),
conv_std_logic_vector(32192,AMPL_WIDTH),
conv_std_logic_vector(32193,AMPL_WIDTH),
conv_std_logic_vector(32193,AMPL_WIDTH),
conv_std_logic_vector(32194,AMPL_WIDTH),
conv_std_logic_vector(32194,AMPL_WIDTH),
conv_std_logic_vector(32195,AMPL_WIDTH),
conv_std_logic_vector(32195,AMPL_WIDTH),
conv_std_logic_vector(32196,AMPL_WIDTH),
conv_std_logic_vector(32197,AMPL_WIDTH),
conv_std_logic_vector(32197,AMPL_WIDTH),
conv_std_logic_vector(32198,AMPL_WIDTH),
conv_std_logic_vector(32198,AMPL_WIDTH),
conv_std_logic_vector(32199,AMPL_WIDTH),
conv_std_logic_vector(32200,AMPL_WIDTH),
conv_std_logic_vector(32200,AMPL_WIDTH),
conv_std_logic_vector(32201,AMPL_WIDTH),
conv_std_logic_vector(32201,AMPL_WIDTH),
conv_std_logic_vector(32202,AMPL_WIDTH),
conv_std_logic_vector(32202,AMPL_WIDTH),
conv_std_logic_vector(32203,AMPL_WIDTH),
conv_std_logic_vector(32204,AMPL_WIDTH),
conv_std_logic_vector(32204,AMPL_WIDTH),
conv_std_logic_vector(32205,AMPL_WIDTH),
conv_std_logic_vector(32205,AMPL_WIDTH),
conv_std_logic_vector(32206,AMPL_WIDTH),
conv_std_logic_vector(32206,AMPL_WIDTH),
conv_std_logic_vector(32207,AMPL_WIDTH),
conv_std_logic_vector(32208,AMPL_WIDTH),
conv_std_logic_vector(32208,AMPL_WIDTH),
conv_std_logic_vector(32209,AMPL_WIDTH),
conv_std_logic_vector(32209,AMPL_WIDTH),
conv_std_logic_vector(32210,AMPL_WIDTH),
conv_std_logic_vector(32211,AMPL_WIDTH),
conv_std_logic_vector(32211,AMPL_WIDTH),
conv_std_logic_vector(32212,AMPL_WIDTH),
conv_std_logic_vector(32212,AMPL_WIDTH),
conv_std_logic_vector(32213,AMPL_WIDTH),
conv_std_logic_vector(32213,AMPL_WIDTH),
conv_std_logic_vector(32214,AMPL_WIDTH),
conv_std_logic_vector(32215,AMPL_WIDTH),
conv_std_logic_vector(32215,AMPL_WIDTH),
conv_std_logic_vector(32216,AMPL_WIDTH),
conv_std_logic_vector(32216,AMPL_WIDTH),
conv_std_logic_vector(32217,AMPL_WIDTH),
conv_std_logic_vector(32217,AMPL_WIDTH),
conv_std_logic_vector(32218,AMPL_WIDTH),
conv_std_logic_vector(32219,AMPL_WIDTH),
conv_std_logic_vector(32219,AMPL_WIDTH),
conv_std_logic_vector(32220,AMPL_WIDTH),
conv_std_logic_vector(32220,AMPL_WIDTH),
conv_std_logic_vector(32221,AMPL_WIDTH),
conv_std_logic_vector(32221,AMPL_WIDTH),
conv_std_logic_vector(32222,AMPL_WIDTH),
conv_std_logic_vector(32223,AMPL_WIDTH),
conv_std_logic_vector(32223,AMPL_WIDTH),
conv_std_logic_vector(32224,AMPL_WIDTH),
conv_std_logic_vector(32224,AMPL_WIDTH),
conv_std_logic_vector(32225,AMPL_WIDTH),
conv_std_logic_vector(32225,AMPL_WIDTH),
conv_std_logic_vector(32226,AMPL_WIDTH),
conv_std_logic_vector(32227,AMPL_WIDTH),
conv_std_logic_vector(32227,AMPL_WIDTH),
conv_std_logic_vector(32228,AMPL_WIDTH),
conv_std_logic_vector(32228,AMPL_WIDTH),
conv_std_logic_vector(32229,AMPL_WIDTH),
conv_std_logic_vector(32229,AMPL_WIDTH),
conv_std_logic_vector(32230,AMPL_WIDTH),
conv_std_logic_vector(32231,AMPL_WIDTH),
conv_std_logic_vector(32231,AMPL_WIDTH),
conv_std_logic_vector(32232,AMPL_WIDTH),
conv_std_logic_vector(32232,AMPL_WIDTH),
conv_std_logic_vector(32233,AMPL_WIDTH),
conv_std_logic_vector(32233,AMPL_WIDTH),
conv_std_logic_vector(32234,AMPL_WIDTH),
conv_std_logic_vector(32234,AMPL_WIDTH),
conv_std_logic_vector(32235,AMPL_WIDTH),
conv_std_logic_vector(32236,AMPL_WIDTH),
conv_std_logic_vector(32236,AMPL_WIDTH),
conv_std_logic_vector(32237,AMPL_WIDTH),
conv_std_logic_vector(32237,AMPL_WIDTH),
conv_std_logic_vector(32238,AMPL_WIDTH),
conv_std_logic_vector(32238,AMPL_WIDTH),
conv_std_logic_vector(32239,AMPL_WIDTH),
conv_std_logic_vector(32240,AMPL_WIDTH),
conv_std_logic_vector(32240,AMPL_WIDTH),
conv_std_logic_vector(32241,AMPL_WIDTH),
conv_std_logic_vector(32241,AMPL_WIDTH),
conv_std_logic_vector(32242,AMPL_WIDTH),
conv_std_logic_vector(32242,AMPL_WIDTH),
conv_std_logic_vector(32243,AMPL_WIDTH),
conv_std_logic_vector(32243,AMPL_WIDTH),
conv_std_logic_vector(32244,AMPL_WIDTH),
conv_std_logic_vector(32245,AMPL_WIDTH),
conv_std_logic_vector(32245,AMPL_WIDTH),
conv_std_logic_vector(32246,AMPL_WIDTH),
conv_std_logic_vector(32246,AMPL_WIDTH),
conv_std_logic_vector(32247,AMPL_WIDTH),
conv_std_logic_vector(32247,AMPL_WIDTH),
conv_std_logic_vector(32248,AMPL_WIDTH),
conv_std_logic_vector(32248,AMPL_WIDTH),
conv_std_logic_vector(32249,AMPL_WIDTH),
conv_std_logic_vector(32250,AMPL_WIDTH),
conv_std_logic_vector(32250,AMPL_WIDTH),
conv_std_logic_vector(32251,AMPL_WIDTH),
conv_std_logic_vector(32251,AMPL_WIDTH),
conv_std_logic_vector(32252,AMPL_WIDTH),
conv_std_logic_vector(32252,AMPL_WIDTH),
conv_std_logic_vector(32253,AMPL_WIDTH),
conv_std_logic_vector(32253,AMPL_WIDTH),
conv_std_logic_vector(32254,AMPL_WIDTH),
conv_std_logic_vector(32255,AMPL_WIDTH),
conv_std_logic_vector(32255,AMPL_WIDTH),
conv_std_logic_vector(32256,AMPL_WIDTH),
conv_std_logic_vector(32256,AMPL_WIDTH),
conv_std_logic_vector(32257,AMPL_WIDTH),
conv_std_logic_vector(32257,AMPL_WIDTH),
conv_std_logic_vector(32258,AMPL_WIDTH),
conv_std_logic_vector(32258,AMPL_WIDTH),
conv_std_logic_vector(32259,AMPL_WIDTH),
conv_std_logic_vector(32260,AMPL_WIDTH),
conv_std_logic_vector(32260,AMPL_WIDTH),
conv_std_logic_vector(32261,AMPL_WIDTH),
conv_std_logic_vector(32261,AMPL_WIDTH),
conv_std_logic_vector(32262,AMPL_WIDTH),
conv_std_logic_vector(32262,AMPL_WIDTH),
conv_std_logic_vector(32263,AMPL_WIDTH),
conv_std_logic_vector(32263,AMPL_WIDTH),
conv_std_logic_vector(32264,AMPL_WIDTH),
conv_std_logic_vector(32265,AMPL_WIDTH),
conv_std_logic_vector(32265,AMPL_WIDTH),
conv_std_logic_vector(32266,AMPL_WIDTH),
conv_std_logic_vector(32266,AMPL_WIDTH),
conv_std_logic_vector(32267,AMPL_WIDTH),
conv_std_logic_vector(32267,AMPL_WIDTH),
conv_std_logic_vector(32268,AMPL_WIDTH),
conv_std_logic_vector(32268,AMPL_WIDTH),
conv_std_logic_vector(32269,AMPL_WIDTH),
conv_std_logic_vector(32269,AMPL_WIDTH),
conv_std_logic_vector(32270,AMPL_WIDTH),
conv_std_logic_vector(32271,AMPL_WIDTH),
conv_std_logic_vector(32271,AMPL_WIDTH),
conv_std_logic_vector(32272,AMPL_WIDTH),
conv_std_logic_vector(32272,AMPL_WIDTH),
conv_std_logic_vector(32273,AMPL_WIDTH),
conv_std_logic_vector(32273,AMPL_WIDTH),
conv_std_logic_vector(32274,AMPL_WIDTH),
conv_std_logic_vector(32274,AMPL_WIDTH),
conv_std_logic_vector(32275,AMPL_WIDTH),
conv_std_logic_vector(32275,AMPL_WIDTH),
conv_std_logic_vector(32276,AMPL_WIDTH),
conv_std_logic_vector(32277,AMPL_WIDTH),
conv_std_logic_vector(32277,AMPL_WIDTH),
conv_std_logic_vector(32278,AMPL_WIDTH),
conv_std_logic_vector(32278,AMPL_WIDTH),
conv_std_logic_vector(32279,AMPL_WIDTH),
conv_std_logic_vector(32279,AMPL_WIDTH),
conv_std_logic_vector(32280,AMPL_WIDTH),
conv_std_logic_vector(32280,AMPL_WIDTH),
conv_std_logic_vector(32281,AMPL_WIDTH),
conv_std_logic_vector(32281,AMPL_WIDTH),
conv_std_logic_vector(32282,AMPL_WIDTH),
conv_std_logic_vector(32282,AMPL_WIDTH),
conv_std_logic_vector(32283,AMPL_WIDTH),
conv_std_logic_vector(32284,AMPL_WIDTH),
conv_std_logic_vector(32284,AMPL_WIDTH),
conv_std_logic_vector(32285,AMPL_WIDTH),
conv_std_logic_vector(32285,AMPL_WIDTH),
conv_std_logic_vector(32286,AMPL_WIDTH),
conv_std_logic_vector(32286,AMPL_WIDTH),
conv_std_logic_vector(32287,AMPL_WIDTH),
conv_std_logic_vector(32287,AMPL_WIDTH),
conv_std_logic_vector(32288,AMPL_WIDTH),
conv_std_logic_vector(32288,AMPL_WIDTH),
conv_std_logic_vector(32289,AMPL_WIDTH),
conv_std_logic_vector(32289,AMPL_WIDTH),
conv_std_logic_vector(32290,AMPL_WIDTH),
conv_std_logic_vector(32290,AMPL_WIDTH),
conv_std_logic_vector(32291,AMPL_WIDTH),
conv_std_logic_vector(32292,AMPL_WIDTH),
conv_std_logic_vector(32292,AMPL_WIDTH),
conv_std_logic_vector(32293,AMPL_WIDTH),
conv_std_logic_vector(32293,AMPL_WIDTH),
conv_std_logic_vector(32294,AMPL_WIDTH),
conv_std_logic_vector(32294,AMPL_WIDTH),
conv_std_logic_vector(32295,AMPL_WIDTH),
conv_std_logic_vector(32295,AMPL_WIDTH),
conv_std_logic_vector(32296,AMPL_WIDTH),
conv_std_logic_vector(32296,AMPL_WIDTH),
conv_std_logic_vector(32297,AMPL_WIDTH),
conv_std_logic_vector(32297,AMPL_WIDTH),
conv_std_logic_vector(32298,AMPL_WIDTH),
conv_std_logic_vector(32298,AMPL_WIDTH),
conv_std_logic_vector(32299,AMPL_WIDTH),
conv_std_logic_vector(32300,AMPL_WIDTH),
conv_std_logic_vector(32300,AMPL_WIDTH),
conv_std_logic_vector(32301,AMPL_WIDTH),
conv_std_logic_vector(32301,AMPL_WIDTH),
conv_std_logic_vector(32302,AMPL_WIDTH),
conv_std_logic_vector(32302,AMPL_WIDTH),
conv_std_logic_vector(32303,AMPL_WIDTH),
conv_std_logic_vector(32303,AMPL_WIDTH),
conv_std_logic_vector(32304,AMPL_WIDTH),
conv_std_logic_vector(32304,AMPL_WIDTH),
conv_std_logic_vector(32305,AMPL_WIDTH),
conv_std_logic_vector(32305,AMPL_WIDTH),
conv_std_logic_vector(32306,AMPL_WIDTH),
conv_std_logic_vector(32306,AMPL_WIDTH),
conv_std_logic_vector(32307,AMPL_WIDTH),
conv_std_logic_vector(32307,AMPL_WIDTH),
conv_std_logic_vector(32308,AMPL_WIDTH),
conv_std_logic_vector(32308,AMPL_WIDTH),
conv_std_logic_vector(32309,AMPL_WIDTH),
conv_std_logic_vector(32310,AMPL_WIDTH),
conv_std_logic_vector(32310,AMPL_WIDTH),
conv_std_logic_vector(32311,AMPL_WIDTH),
conv_std_logic_vector(32311,AMPL_WIDTH),
conv_std_logic_vector(32312,AMPL_WIDTH),
conv_std_logic_vector(32312,AMPL_WIDTH),
conv_std_logic_vector(32313,AMPL_WIDTH),
conv_std_logic_vector(32313,AMPL_WIDTH),
conv_std_logic_vector(32314,AMPL_WIDTH),
conv_std_logic_vector(32314,AMPL_WIDTH),
conv_std_logic_vector(32315,AMPL_WIDTH),
conv_std_logic_vector(32315,AMPL_WIDTH),
conv_std_logic_vector(32316,AMPL_WIDTH),
conv_std_logic_vector(32316,AMPL_WIDTH),
conv_std_logic_vector(32317,AMPL_WIDTH),
conv_std_logic_vector(32317,AMPL_WIDTH),
conv_std_logic_vector(32318,AMPL_WIDTH),
conv_std_logic_vector(32318,AMPL_WIDTH),
conv_std_logic_vector(32319,AMPL_WIDTH),
conv_std_logic_vector(32319,AMPL_WIDTH),
conv_std_logic_vector(32320,AMPL_WIDTH),
conv_std_logic_vector(32320,AMPL_WIDTH),
conv_std_logic_vector(32321,AMPL_WIDTH),
conv_std_logic_vector(32321,AMPL_WIDTH),
conv_std_logic_vector(32322,AMPL_WIDTH),
conv_std_logic_vector(32322,AMPL_WIDTH),
conv_std_logic_vector(32323,AMPL_WIDTH),
conv_std_logic_vector(32324,AMPL_WIDTH),
conv_std_logic_vector(32324,AMPL_WIDTH),
conv_std_logic_vector(32325,AMPL_WIDTH),
conv_std_logic_vector(32325,AMPL_WIDTH),
conv_std_logic_vector(32326,AMPL_WIDTH),
conv_std_logic_vector(32326,AMPL_WIDTH),
conv_std_logic_vector(32327,AMPL_WIDTH),
conv_std_logic_vector(32327,AMPL_WIDTH),
conv_std_logic_vector(32328,AMPL_WIDTH),
conv_std_logic_vector(32328,AMPL_WIDTH),
conv_std_logic_vector(32329,AMPL_WIDTH),
conv_std_logic_vector(32329,AMPL_WIDTH),
conv_std_logic_vector(32330,AMPL_WIDTH),
conv_std_logic_vector(32330,AMPL_WIDTH),
conv_std_logic_vector(32331,AMPL_WIDTH),
conv_std_logic_vector(32331,AMPL_WIDTH),
conv_std_logic_vector(32332,AMPL_WIDTH),
conv_std_logic_vector(32332,AMPL_WIDTH),
conv_std_logic_vector(32333,AMPL_WIDTH),
conv_std_logic_vector(32333,AMPL_WIDTH),
conv_std_logic_vector(32334,AMPL_WIDTH),
conv_std_logic_vector(32334,AMPL_WIDTH),
conv_std_logic_vector(32335,AMPL_WIDTH),
conv_std_logic_vector(32335,AMPL_WIDTH),
conv_std_logic_vector(32336,AMPL_WIDTH),
conv_std_logic_vector(32336,AMPL_WIDTH),
conv_std_logic_vector(32337,AMPL_WIDTH),
conv_std_logic_vector(32337,AMPL_WIDTH),
conv_std_logic_vector(32338,AMPL_WIDTH),
conv_std_logic_vector(32338,AMPL_WIDTH),
conv_std_logic_vector(32339,AMPL_WIDTH),
conv_std_logic_vector(32339,AMPL_WIDTH),
conv_std_logic_vector(32340,AMPL_WIDTH),
conv_std_logic_vector(32340,AMPL_WIDTH),
conv_std_logic_vector(32341,AMPL_WIDTH),
conv_std_logic_vector(32341,AMPL_WIDTH),
conv_std_logic_vector(32342,AMPL_WIDTH),
conv_std_logic_vector(32342,AMPL_WIDTH),
conv_std_logic_vector(32343,AMPL_WIDTH),
conv_std_logic_vector(32343,AMPL_WIDTH),
conv_std_logic_vector(32344,AMPL_WIDTH),
conv_std_logic_vector(32344,AMPL_WIDTH),
conv_std_logic_vector(32345,AMPL_WIDTH),
conv_std_logic_vector(32345,AMPL_WIDTH),
conv_std_logic_vector(32346,AMPL_WIDTH),
conv_std_logic_vector(32346,AMPL_WIDTH),
conv_std_logic_vector(32347,AMPL_WIDTH),
conv_std_logic_vector(32347,AMPL_WIDTH),
conv_std_logic_vector(32348,AMPL_WIDTH),
conv_std_logic_vector(32348,AMPL_WIDTH),
conv_std_logic_vector(32349,AMPL_WIDTH),
conv_std_logic_vector(32349,AMPL_WIDTH),
conv_std_logic_vector(32350,AMPL_WIDTH),
conv_std_logic_vector(32350,AMPL_WIDTH),
conv_std_logic_vector(32351,AMPL_WIDTH),
conv_std_logic_vector(32351,AMPL_WIDTH),
conv_std_logic_vector(32352,AMPL_WIDTH),
conv_std_logic_vector(32352,AMPL_WIDTH),
conv_std_logic_vector(32353,AMPL_WIDTH),
conv_std_logic_vector(32353,AMPL_WIDTH),
conv_std_logic_vector(32354,AMPL_WIDTH),
conv_std_logic_vector(32354,AMPL_WIDTH),
conv_std_logic_vector(32355,AMPL_WIDTH),
conv_std_logic_vector(32355,AMPL_WIDTH),
conv_std_logic_vector(32356,AMPL_WIDTH),
conv_std_logic_vector(32356,AMPL_WIDTH),
conv_std_logic_vector(32357,AMPL_WIDTH),
conv_std_logic_vector(32357,AMPL_WIDTH),
conv_std_logic_vector(32358,AMPL_WIDTH),
conv_std_logic_vector(32358,AMPL_WIDTH),
conv_std_logic_vector(32359,AMPL_WIDTH),
conv_std_logic_vector(32359,AMPL_WIDTH),
conv_std_logic_vector(32360,AMPL_WIDTH),
conv_std_logic_vector(32360,AMPL_WIDTH),
conv_std_logic_vector(32361,AMPL_WIDTH),
conv_std_logic_vector(32361,AMPL_WIDTH),
conv_std_logic_vector(32362,AMPL_WIDTH),
conv_std_logic_vector(32362,AMPL_WIDTH),
conv_std_logic_vector(32363,AMPL_WIDTH),
conv_std_logic_vector(32363,AMPL_WIDTH),
conv_std_logic_vector(32364,AMPL_WIDTH),
conv_std_logic_vector(32364,AMPL_WIDTH),
conv_std_logic_vector(32365,AMPL_WIDTH),
conv_std_logic_vector(32365,AMPL_WIDTH),
conv_std_logic_vector(32366,AMPL_WIDTH),
conv_std_logic_vector(32366,AMPL_WIDTH),
conv_std_logic_vector(32367,AMPL_WIDTH),
conv_std_logic_vector(32367,AMPL_WIDTH),
conv_std_logic_vector(32368,AMPL_WIDTH),
conv_std_logic_vector(32368,AMPL_WIDTH),
conv_std_logic_vector(32369,AMPL_WIDTH),
conv_std_logic_vector(32369,AMPL_WIDTH),
conv_std_logic_vector(32370,AMPL_WIDTH),
conv_std_logic_vector(32370,AMPL_WIDTH),
conv_std_logic_vector(32371,AMPL_WIDTH),
conv_std_logic_vector(32371,AMPL_WIDTH),
conv_std_logic_vector(32372,AMPL_WIDTH),
conv_std_logic_vector(32372,AMPL_WIDTH),
conv_std_logic_vector(32373,AMPL_WIDTH),
conv_std_logic_vector(32373,AMPL_WIDTH),
conv_std_logic_vector(32374,AMPL_WIDTH),
conv_std_logic_vector(32374,AMPL_WIDTH),
conv_std_logic_vector(32375,AMPL_WIDTH),
conv_std_logic_vector(32375,AMPL_WIDTH),
conv_std_logic_vector(32375,AMPL_WIDTH),
conv_std_logic_vector(32376,AMPL_WIDTH),
conv_std_logic_vector(32376,AMPL_WIDTH),
conv_std_logic_vector(32377,AMPL_WIDTH),
conv_std_logic_vector(32377,AMPL_WIDTH),
conv_std_logic_vector(32378,AMPL_WIDTH),
conv_std_logic_vector(32378,AMPL_WIDTH),
conv_std_logic_vector(32379,AMPL_WIDTH),
conv_std_logic_vector(32379,AMPL_WIDTH),
conv_std_logic_vector(32380,AMPL_WIDTH),
conv_std_logic_vector(32380,AMPL_WIDTH),
conv_std_logic_vector(32381,AMPL_WIDTH),
conv_std_logic_vector(32381,AMPL_WIDTH),
conv_std_logic_vector(32382,AMPL_WIDTH),
conv_std_logic_vector(32382,AMPL_WIDTH),
conv_std_logic_vector(32383,AMPL_WIDTH),
conv_std_logic_vector(32383,AMPL_WIDTH),
conv_std_logic_vector(32384,AMPL_WIDTH),
conv_std_logic_vector(32384,AMPL_WIDTH),
conv_std_logic_vector(32385,AMPL_WIDTH),
conv_std_logic_vector(32385,AMPL_WIDTH),
conv_std_logic_vector(32386,AMPL_WIDTH),
conv_std_logic_vector(32386,AMPL_WIDTH),
conv_std_logic_vector(32387,AMPL_WIDTH),
conv_std_logic_vector(32387,AMPL_WIDTH),
conv_std_logic_vector(32387,AMPL_WIDTH),
conv_std_logic_vector(32388,AMPL_WIDTH),
conv_std_logic_vector(32388,AMPL_WIDTH),
conv_std_logic_vector(32389,AMPL_WIDTH),
conv_std_logic_vector(32389,AMPL_WIDTH),
conv_std_logic_vector(32390,AMPL_WIDTH),
conv_std_logic_vector(32390,AMPL_WIDTH),
conv_std_logic_vector(32391,AMPL_WIDTH),
conv_std_logic_vector(32391,AMPL_WIDTH),
conv_std_logic_vector(32392,AMPL_WIDTH),
conv_std_logic_vector(32392,AMPL_WIDTH),
conv_std_logic_vector(32393,AMPL_WIDTH),
conv_std_logic_vector(32393,AMPL_WIDTH),
conv_std_logic_vector(32394,AMPL_WIDTH),
conv_std_logic_vector(32394,AMPL_WIDTH),
conv_std_logic_vector(32395,AMPL_WIDTH),
conv_std_logic_vector(32395,AMPL_WIDTH),
conv_std_logic_vector(32396,AMPL_WIDTH),
conv_std_logic_vector(32396,AMPL_WIDTH),
conv_std_logic_vector(32397,AMPL_WIDTH),
conv_std_logic_vector(32397,AMPL_WIDTH),
conv_std_logic_vector(32397,AMPL_WIDTH),
conv_std_logic_vector(32398,AMPL_WIDTH),
conv_std_logic_vector(32398,AMPL_WIDTH),
conv_std_logic_vector(32399,AMPL_WIDTH),
conv_std_logic_vector(32399,AMPL_WIDTH),
conv_std_logic_vector(32400,AMPL_WIDTH),
conv_std_logic_vector(32400,AMPL_WIDTH),
conv_std_logic_vector(32401,AMPL_WIDTH),
conv_std_logic_vector(32401,AMPL_WIDTH),
conv_std_logic_vector(32402,AMPL_WIDTH),
conv_std_logic_vector(32402,AMPL_WIDTH),
conv_std_logic_vector(32403,AMPL_WIDTH),
conv_std_logic_vector(32403,AMPL_WIDTH),
conv_std_logic_vector(32404,AMPL_WIDTH),
conv_std_logic_vector(32404,AMPL_WIDTH),
conv_std_logic_vector(32404,AMPL_WIDTH),
conv_std_logic_vector(32405,AMPL_WIDTH),
conv_std_logic_vector(32405,AMPL_WIDTH),
conv_std_logic_vector(32406,AMPL_WIDTH),
conv_std_logic_vector(32406,AMPL_WIDTH),
conv_std_logic_vector(32407,AMPL_WIDTH),
conv_std_logic_vector(32407,AMPL_WIDTH),
conv_std_logic_vector(32408,AMPL_WIDTH),
conv_std_logic_vector(32408,AMPL_WIDTH),
conv_std_logic_vector(32409,AMPL_WIDTH),
conv_std_logic_vector(32409,AMPL_WIDTH),
conv_std_logic_vector(32410,AMPL_WIDTH),
conv_std_logic_vector(32410,AMPL_WIDTH),
conv_std_logic_vector(32411,AMPL_WIDTH),
conv_std_logic_vector(32411,AMPL_WIDTH),
conv_std_logic_vector(32411,AMPL_WIDTH),
conv_std_logic_vector(32412,AMPL_WIDTH),
conv_std_logic_vector(32412,AMPL_WIDTH),
conv_std_logic_vector(32413,AMPL_WIDTH),
conv_std_logic_vector(32413,AMPL_WIDTH),
conv_std_logic_vector(32414,AMPL_WIDTH),
conv_std_logic_vector(32414,AMPL_WIDTH),
conv_std_logic_vector(32415,AMPL_WIDTH),
conv_std_logic_vector(32415,AMPL_WIDTH),
conv_std_logic_vector(32416,AMPL_WIDTH),
conv_std_logic_vector(32416,AMPL_WIDTH),
conv_std_logic_vector(32416,AMPL_WIDTH),
conv_std_logic_vector(32417,AMPL_WIDTH),
conv_std_logic_vector(32417,AMPL_WIDTH),
conv_std_logic_vector(32418,AMPL_WIDTH),
conv_std_logic_vector(32418,AMPL_WIDTH),
conv_std_logic_vector(32419,AMPL_WIDTH),
conv_std_logic_vector(32419,AMPL_WIDTH),
conv_std_logic_vector(32420,AMPL_WIDTH),
conv_std_logic_vector(32420,AMPL_WIDTH),
conv_std_logic_vector(32421,AMPL_WIDTH),
conv_std_logic_vector(32421,AMPL_WIDTH),
conv_std_logic_vector(32422,AMPL_WIDTH),
conv_std_logic_vector(32422,AMPL_WIDTH),
conv_std_logic_vector(32422,AMPL_WIDTH),
conv_std_logic_vector(32423,AMPL_WIDTH),
conv_std_logic_vector(32423,AMPL_WIDTH),
conv_std_logic_vector(32424,AMPL_WIDTH),
conv_std_logic_vector(32424,AMPL_WIDTH),
conv_std_logic_vector(32425,AMPL_WIDTH),
conv_std_logic_vector(32425,AMPL_WIDTH),
conv_std_logic_vector(32426,AMPL_WIDTH),
conv_std_logic_vector(32426,AMPL_WIDTH),
conv_std_logic_vector(32426,AMPL_WIDTH),
conv_std_logic_vector(32427,AMPL_WIDTH),
conv_std_logic_vector(32427,AMPL_WIDTH),
conv_std_logic_vector(32428,AMPL_WIDTH),
conv_std_logic_vector(32428,AMPL_WIDTH),
conv_std_logic_vector(32429,AMPL_WIDTH),
conv_std_logic_vector(32429,AMPL_WIDTH),
conv_std_logic_vector(32430,AMPL_WIDTH),
conv_std_logic_vector(32430,AMPL_WIDTH),
conv_std_logic_vector(32431,AMPL_WIDTH),
conv_std_logic_vector(32431,AMPL_WIDTH),
conv_std_logic_vector(32431,AMPL_WIDTH),
conv_std_logic_vector(32432,AMPL_WIDTH),
conv_std_logic_vector(32432,AMPL_WIDTH),
conv_std_logic_vector(32433,AMPL_WIDTH),
conv_std_logic_vector(32433,AMPL_WIDTH),
conv_std_logic_vector(32434,AMPL_WIDTH),
conv_std_logic_vector(32434,AMPL_WIDTH),
conv_std_logic_vector(32435,AMPL_WIDTH),
conv_std_logic_vector(32435,AMPL_WIDTH),
conv_std_logic_vector(32435,AMPL_WIDTH),
conv_std_logic_vector(32436,AMPL_WIDTH),
conv_std_logic_vector(32436,AMPL_WIDTH),
conv_std_logic_vector(32437,AMPL_WIDTH),
conv_std_logic_vector(32437,AMPL_WIDTH),
conv_std_logic_vector(32438,AMPL_WIDTH),
conv_std_logic_vector(32438,AMPL_WIDTH),
conv_std_logic_vector(32439,AMPL_WIDTH),
conv_std_logic_vector(32439,AMPL_WIDTH),
conv_std_logic_vector(32439,AMPL_WIDTH),
conv_std_logic_vector(32440,AMPL_WIDTH),
conv_std_logic_vector(32440,AMPL_WIDTH),
conv_std_logic_vector(32441,AMPL_WIDTH),
conv_std_logic_vector(32441,AMPL_WIDTH),
conv_std_logic_vector(32442,AMPL_WIDTH),
conv_std_logic_vector(32442,AMPL_WIDTH),
conv_std_logic_vector(32443,AMPL_WIDTH),
conv_std_logic_vector(32443,AMPL_WIDTH),
conv_std_logic_vector(32443,AMPL_WIDTH),
conv_std_logic_vector(32444,AMPL_WIDTH),
conv_std_logic_vector(32444,AMPL_WIDTH),
conv_std_logic_vector(32445,AMPL_WIDTH),
conv_std_logic_vector(32445,AMPL_WIDTH),
conv_std_logic_vector(32446,AMPL_WIDTH),
conv_std_logic_vector(32446,AMPL_WIDTH),
conv_std_logic_vector(32447,AMPL_WIDTH),
conv_std_logic_vector(32447,AMPL_WIDTH),
conv_std_logic_vector(32447,AMPL_WIDTH),
conv_std_logic_vector(32448,AMPL_WIDTH),
conv_std_logic_vector(32448,AMPL_WIDTH),
conv_std_logic_vector(32449,AMPL_WIDTH),
conv_std_logic_vector(32449,AMPL_WIDTH),
conv_std_logic_vector(32450,AMPL_WIDTH),
conv_std_logic_vector(32450,AMPL_WIDTH),
conv_std_logic_vector(32450,AMPL_WIDTH),
conv_std_logic_vector(32451,AMPL_WIDTH),
conv_std_logic_vector(32451,AMPL_WIDTH),
conv_std_logic_vector(32452,AMPL_WIDTH),
conv_std_logic_vector(32452,AMPL_WIDTH),
conv_std_logic_vector(32453,AMPL_WIDTH),
conv_std_logic_vector(32453,AMPL_WIDTH),
conv_std_logic_vector(32453,AMPL_WIDTH),
conv_std_logic_vector(32454,AMPL_WIDTH),
conv_std_logic_vector(32454,AMPL_WIDTH),
conv_std_logic_vector(32455,AMPL_WIDTH),
conv_std_logic_vector(32455,AMPL_WIDTH),
conv_std_logic_vector(32456,AMPL_WIDTH),
conv_std_logic_vector(32456,AMPL_WIDTH),
conv_std_logic_vector(32457,AMPL_WIDTH),
conv_std_logic_vector(32457,AMPL_WIDTH),
conv_std_logic_vector(32457,AMPL_WIDTH),
conv_std_logic_vector(32458,AMPL_WIDTH),
conv_std_logic_vector(32458,AMPL_WIDTH),
conv_std_logic_vector(32459,AMPL_WIDTH),
conv_std_logic_vector(32459,AMPL_WIDTH),
conv_std_logic_vector(32460,AMPL_WIDTH),
conv_std_logic_vector(32460,AMPL_WIDTH),
conv_std_logic_vector(32460,AMPL_WIDTH),
conv_std_logic_vector(32461,AMPL_WIDTH),
conv_std_logic_vector(32461,AMPL_WIDTH),
conv_std_logic_vector(32462,AMPL_WIDTH),
conv_std_logic_vector(32462,AMPL_WIDTH),
conv_std_logic_vector(32463,AMPL_WIDTH),
conv_std_logic_vector(32463,AMPL_WIDTH),
conv_std_logic_vector(32463,AMPL_WIDTH),
conv_std_logic_vector(32464,AMPL_WIDTH),
conv_std_logic_vector(32464,AMPL_WIDTH),
conv_std_logic_vector(32465,AMPL_WIDTH),
conv_std_logic_vector(32465,AMPL_WIDTH),
conv_std_logic_vector(32466,AMPL_WIDTH),
conv_std_logic_vector(32466,AMPL_WIDTH),
conv_std_logic_vector(32466,AMPL_WIDTH),
conv_std_logic_vector(32467,AMPL_WIDTH),
conv_std_logic_vector(32467,AMPL_WIDTH),
conv_std_logic_vector(32468,AMPL_WIDTH),
conv_std_logic_vector(32468,AMPL_WIDTH),
conv_std_logic_vector(32468,AMPL_WIDTH),
conv_std_logic_vector(32469,AMPL_WIDTH),
conv_std_logic_vector(32469,AMPL_WIDTH),
conv_std_logic_vector(32470,AMPL_WIDTH),
conv_std_logic_vector(32470,AMPL_WIDTH),
conv_std_logic_vector(32471,AMPL_WIDTH),
conv_std_logic_vector(32471,AMPL_WIDTH),
conv_std_logic_vector(32471,AMPL_WIDTH),
conv_std_logic_vector(32472,AMPL_WIDTH),
conv_std_logic_vector(32472,AMPL_WIDTH),
conv_std_logic_vector(32473,AMPL_WIDTH),
conv_std_logic_vector(32473,AMPL_WIDTH),
conv_std_logic_vector(32474,AMPL_WIDTH),
conv_std_logic_vector(32474,AMPL_WIDTH),
conv_std_logic_vector(32474,AMPL_WIDTH),
conv_std_logic_vector(32475,AMPL_WIDTH),
conv_std_logic_vector(32475,AMPL_WIDTH),
conv_std_logic_vector(32476,AMPL_WIDTH),
conv_std_logic_vector(32476,AMPL_WIDTH),
conv_std_logic_vector(32476,AMPL_WIDTH),
conv_std_logic_vector(32477,AMPL_WIDTH),
conv_std_logic_vector(32477,AMPL_WIDTH),
conv_std_logic_vector(32478,AMPL_WIDTH),
conv_std_logic_vector(32478,AMPL_WIDTH),
conv_std_logic_vector(32479,AMPL_WIDTH),
conv_std_logic_vector(32479,AMPL_WIDTH),
conv_std_logic_vector(32479,AMPL_WIDTH),
conv_std_logic_vector(32480,AMPL_WIDTH),
conv_std_logic_vector(32480,AMPL_WIDTH),
conv_std_logic_vector(32481,AMPL_WIDTH),
conv_std_logic_vector(32481,AMPL_WIDTH),
conv_std_logic_vector(32481,AMPL_WIDTH),
conv_std_logic_vector(32482,AMPL_WIDTH),
conv_std_logic_vector(32482,AMPL_WIDTH),
conv_std_logic_vector(32483,AMPL_WIDTH),
conv_std_logic_vector(32483,AMPL_WIDTH),
conv_std_logic_vector(32484,AMPL_WIDTH),
conv_std_logic_vector(32484,AMPL_WIDTH),
conv_std_logic_vector(32484,AMPL_WIDTH),
conv_std_logic_vector(32485,AMPL_WIDTH),
conv_std_logic_vector(32485,AMPL_WIDTH),
conv_std_logic_vector(32486,AMPL_WIDTH),
conv_std_logic_vector(32486,AMPL_WIDTH),
conv_std_logic_vector(32486,AMPL_WIDTH),
conv_std_logic_vector(32487,AMPL_WIDTH),
conv_std_logic_vector(32487,AMPL_WIDTH),
conv_std_logic_vector(32488,AMPL_WIDTH),
conv_std_logic_vector(32488,AMPL_WIDTH),
conv_std_logic_vector(32488,AMPL_WIDTH),
conv_std_logic_vector(32489,AMPL_WIDTH),
conv_std_logic_vector(32489,AMPL_WIDTH),
conv_std_logic_vector(32490,AMPL_WIDTH),
conv_std_logic_vector(32490,AMPL_WIDTH),
conv_std_logic_vector(32490,AMPL_WIDTH),
conv_std_logic_vector(32491,AMPL_WIDTH),
conv_std_logic_vector(32491,AMPL_WIDTH),
conv_std_logic_vector(32492,AMPL_WIDTH),
conv_std_logic_vector(32492,AMPL_WIDTH),
conv_std_logic_vector(32493,AMPL_WIDTH),
conv_std_logic_vector(32493,AMPL_WIDTH),
conv_std_logic_vector(32493,AMPL_WIDTH),
conv_std_logic_vector(32494,AMPL_WIDTH),
conv_std_logic_vector(32494,AMPL_WIDTH),
conv_std_logic_vector(32495,AMPL_WIDTH),
conv_std_logic_vector(32495,AMPL_WIDTH),
conv_std_logic_vector(32495,AMPL_WIDTH),
conv_std_logic_vector(32496,AMPL_WIDTH),
conv_std_logic_vector(32496,AMPL_WIDTH),
conv_std_logic_vector(32497,AMPL_WIDTH),
conv_std_logic_vector(32497,AMPL_WIDTH),
conv_std_logic_vector(32497,AMPL_WIDTH),
conv_std_logic_vector(32498,AMPL_WIDTH),
conv_std_logic_vector(32498,AMPL_WIDTH),
conv_std_logic_vector(32499,AMPL_WIDTH),
conv_std_logic_vector(32499,AMPL_WIDTH),
conv_std_logic_vector(32499,AMPL_WIDTH),
conv_std_logic_vector(32500,AMPL_WIDTH),
conv_std_logic_vector(32500,AMPL_WIDTH),
conv_std_logic_vector(32501,AMPL_WIDTH),
conv_std_logic_vector(32501,AMPL_WIDTH),
conv_std_logic_vector(32501,AMPL_WIDTH),
conv_std_logic_vector(32502,AMPL_WIDTH),
conv_std_logic_vector(32502,AMPL_WIDTH),
conv_std_logic_vector(32503,AMPL_WIDTH),
conv_std_logic_vector(32503,AMPL_WIDTH),
conv_std_logic_vector(32503,AMPL_WIDTH),
conv_std_logic_vector(32504,AMPL_WIDTH),
conv_std_logic_vector(32504,AMPL_WIDTH),
conv_std_logic_vector(32505,AMPL_WIDTH),
conv_std_logic_vector(32505,AMPL_WIDTH),
conv_std_logic_vector(32505,AMPL_WIDTH),
conv_std_logic_vector(32506,AMPL_WIDTH),
conv_std_logic_vector(32506,AMPL_WIDTH),
conv_std_logic_vector(32507,AMPL_WIDTH),
conv_std_logic_vector(32507,AMPL_WIDTH),
conv_std_logic_vector(32507,AMPL_WIDTH),
conv_std_logic_vector(32508,AMPL_WIDTH),
conv_std_logic_vector(32508,AMPL_WIDTH),
conv_std_logic_vector(32509,AMPL_WIDTH),
conv_std_logic_vector(32509,AMPL_WIDTH),
conv_std_logic_vector(32509,AMPL_WIDTH),
conv_std_logic_vector(32510,AMPL_WIDTH),
conv_std_logic_vector(32510,AMPL_WIDTH),
conv_std_logic_vector(32510,AMPL_WIDTH),
conv_std_logic_vector(32511,AMPL_WIDTH),
conv_std_logic_vector(32511,AMPL_WIDTH),
conv_std_logic_vector(32512,AMPL_WIDTH),
conv_std_logic_vector(32512,AMPL_WIDTH),
conv_std_logic_vector(32512,AMPL_WIDTH),
conv_std_logic_vector(32513,AMPL_WIDTH),
conv_std_logic_vector(32513,AMPL_WIDTH),
conv_std_logic_vector(32514,AMPL_WIDTH),
conv_std_logic_vector(32514,AMPL_WIDTH),
conv_std_logic_vector(32514,AMPL_WIDTH),
conv_std_logic_vector(32515,AMPL_WIDTH),
conv_std_logic_vector(32515,AMPL_WIDTH),
conv_std_logic_vector(32516,AMPL_WIDTH),
conv_std_logic_vector(32516,AMPL_WIDTH),
conv_std_logic_vector(32516,AMPL_WIDTH),
conv_std_logic_vector(32517,AMPL_WIDTH),
conv_std_logic_vector(32517,AMPL_WIDTH),
conv_std_logic_vector(32517,AMPL_WIDTH),
conv_std_logic_vector(32518,AMPL_WIDTH),
conv_std_logic_vector(32518,AMPL_WIDTH),
conv_std_logic_vector(32519,AMPL_WIDTH),
conv_std_logic_vector(32519,AMPL_WIDTH),
conv_std_logic_vector(32519,AMPL_WIDTH),
conv_std_logic_vector(32520,AMPL_WIDTH),
conv_std_logic_vector(32520,AMPL_WIDTH),
conv_std_logic_vector(32521,AMPL_WIDTH),
conv_std_logic_vector(32521,AMPL_WIDTH),
conv_std_logic_vector(32521,AMPL_WIDTH),
conv_std_logic_vector(32522,AMPL_WIDTH),
conv_std_logic_vector(32522,AMPL_WIDTH),
conv_std_logic_vector(32522,AMPL_WIDTH),
conv_std_logic_vector(32523,AMPL_WIDTH),
conv_std_logic_vector(32523,AMPL_WIDTH),
conv_std_logic_vector(32524,AMPL_WIDTH),
conv_std_logic_vector(32524,AMPL_WIDTH),
conv_std_logic_vector(32524,AMPL_WIDTH),
conv_std_logic_vector(32525,AMPL_WIDTH),
conv_std_logic_vector(32525,AMPL_WIDTH),
conv_std_logic_vector(32526,AMPL_WIDTH),
conv_std_logic_vector(32526,AMPL_WIDTH),
conv_std_logic_vector(32526,AMPL_WIDTH),
conv_std_logic_vector(32527,AMPL_WIDTH),
conv_std_logic_vector(32527,AMPL_WIDTH),
conv_std_logic_vector(32527,AMPL_WIDTH),
conv_std_logic_vector(32528,AMPL_WIDTH),
conv_std_logic_vector(32528,AMPL_WIDTH),
conv_std_logic_vector(32529,AMPL_WIDTH),
conv_std_logic_vector(32529,AMPL_WIDTH),
conv_std_logic_vector(32529,AMPL_WIDTH),
conv_std_logic_vector(32530,AMPL_WIDTH),
conv_std_logic_vector(32530,AMPL_WIDTH),
conv_std_logic_vector(32530,AMPL_WIDTH),
conv_std_logic_vector(32531,AMPL_WIDTH),
conv_std_logic_vector(32531,AMPL_WIDTH),
conv_std_logic_vector(32532,AMPL_WIDTH),
conv_std_logic_vector(32532,AMPL_WIDTH),
conv_std_logic_vector(32532,AMPL_WIDTH),
conv_std_logic_vector(32533,AMPL_WIDTH),
conv_std_logic_vector(32533,AMPL_WIDTH),
conv_std_logic_vector(32533,AMPL_WIDTH),
conv_std_logic_vector(32534,AMPL_WIDTH),
conv_std_logic_vector(32534,AMPL_WIDTH),
conv_std_logic_vector(32535,AMPL_WIDTH),
conv_std_logic_vector(32535,AMPL_WIDTH),
conv_std_logic_vector(32535,AMPL_WIDTH),
conv_std_logic_vector(32536,AMPL_WIDTH),
conv_std_logic_vector(32536,AMPL_WIDTH),
conv_std_logic_vector(32536,AMPL_WIDTH),
conv_std_logic_vector(32537,AMPL_WIDTH),
conv_std_logic_vector(32537,AMPL_WIDTH),
conv_std_logic_vector(32538,AMPL_WIDTH),
conv_std_logic_vector(32538,AMPL_WIDTH),
conv_std_logic_vector(32538,AMPL_WIDTH),
conv_std_logic_vector(32539,AMPL_WIDTH),
conv_std_logic_vector(32539,AMPL_WIDTH),
conv_std_logic_vector(32539,AMPL_WIDTH),
conv_std_logic_vector(32540,AMPL_WIDTH),
conv_std_logic_vector(32540,AMPL_WIDTH),
conv_std_logic_vector(32541,AMPL_WIDTH),
conv_std_logic_vector(32541,AMPL_WIDTH),
conv_std_logic_vector(32541,AMPL_WIDTH),
conv_std_logic_vector(32542,AMPL_WIDTH),
conv_std_logic_vector(32542,AMPL_WIDTH),
conv_std_logic_vector(32542,AMPL_WIDTH),
conv_std_logic_vector(32543,AMPL_WIDTH),
conv_std_logic_vector(32543,AMPL_WIDTH),
conv_std_logic_vector(32543,AMPL_WIDTH),
conv_std_logic_vector(32544,AMPL_WIDTH),
conv_std_logic_vector(32544,AMPL_WIDTH),
conv_std_logic_vector(32545,AMPL_WIDTH),
conv_std_logic_vector(32545,AMPL_WIDTH),
conv_std_logic_vector(32545,AMPL_WIDTH),
conv_std_logic_vector(32546,AMPL_WIDTH),
conv_std_logic_vector(32546,AMPL_WIDTH),
conv_std_logic_vector(32546,AMPL_WIDTH),
conv_std_logic_vector(32547,AMPL_WIDTH),
conv_std_logic_vector(32547,AMPL_WIDTH),
conv_std_logic_vector(32547,AMPL_WIDTH),
conv_std_logic_vector(32548,AMPL_WIDTH),
conv_std_logic_vector(32548,AMPL_WIDTH),
conv_std_logic_vector(32549,AMPL_WIDTH),
conv_std_logic_vector(32549,AMPL_WIDTH),
conv_std_logic_vector(32549,AMPL_WIDTH),
conv_std_logic_vector(32550,AMPL_WIDTH),
conv_std_logic_vector(32550,AMPL_WIDTH),
conv_std_logic_vector(32550,AMPL_WIDTH),
conv_std_logic_vector(32551,AMPL_WIDTH),
conv_std_logic_vector(32551,AMPL_WIDTH),
conv_std_logic_vector(32551,AMPL_WIDTH),
conv_std_logic_vector(32552,AMPL_WIDTH),
conv_std_logic_vector(32552,AMPL_WIDTH),
conv_std_logic_vector(32553,AMPL_WIDTH),
conv_std_logic_vector(32553,AMPL_WIDTH),
conv_std_logic_vector(32553,AMPL_WIDTH),
conv_std_logic_vector(32554,AMPL_WIDTH),
conv_std_logic_vector(32554,AMPL_WIDTH),
conv_std_logic_vector(32554,AMPL_WIDTH),
conv_std_logic_vector(32555,AMPL_WIDTH),
conv_std_logic_vector(32555,AMPL_WIDTH),
conv_std_logic_vector(32555,AMPL_WIDTH),
conv_std_logic_vector(32556,AMPL_WIDTH),
conv_std_logic_vector(32556,AMPL_WIDTH),
conv_std_logic_vector(32556,AMPL_WIDTH),
conv_std_logic_vector(32557,AMPL_WIDTH),
conv_std_logic_vector(32557,AMPL_WIDTH),
conv_std_logic_vector(32558,AMPL_WIDTH),
conv_std_logic_vector(32558,AMPL_WIDTH),
conv_std_logic_vector(32558,AMPL_WIDTH),
conv_std_logic_vector(32559,AMPL_WIDTH),
conv_std_logic_vector(32559,AMPL_WIDTH),
conv_std_logic_vector(32559,AMPL_WIDTH),
conv_std_logic_vector(32560,AMPL_WIDTH),
conv_std_logic_vector(32560,AMPL_WIDTH),
conv_std_logic_vector(32560,AMPL_WIDTH),
conv_std_logic_vector(32561,AMPL_WIDTH),
conv_std_logic_vector(32561,AMPL_WIDTH),
conv_std_logic_vector(32561,AMPL_WIDTH),
conv_std_logic_vector(32562,AMPL_WIDTH),
conv_std_logic_vector(32562,AMPL_WIDTH),
conv_std_logic_vector(32562,AMPL_WIDTH),
conv_std_logic_vector(32563,AMPL_WIDTH),
conv_std_logic_vector(32563,AMPL_WIDTH),
conv_std_logic_vector(32564,AMPL_WIDTH),
conv_std_logic_vector(32564,AMPL_WIDTH),
conv_std_logic_vector(32564,AMPL_WIDTH),
conv_std_logic_vector(32565,AMPL_WIDTH),
conv_std_logic_vector(32565,AMPL_WIDTH),
conv_std_logic_vector(32565,AMPL_WIDTH),
conv_std_logic_vector(32566,AMPL_WIDTH),
conv_std_logic_vector(32566,AMPL_WIDTH),
conv_std_logic_vector(32566,AMPL_WIDTH),
conv_std_logic_vector(32567,AMPL_WIDTH),
conv_std_logic_vector(32567,AMPL_WIDTH),
conv_std_logic_vector(32567,AMPL_WIDTH),
conv_std_logic_vector(32568,AMPL_WIDTH),
conv_std_logic_vector(32568,AMPL_WIDTH),
conv_std_logic_vector(32568,AMPL_WIDTH),
conv_std_logic_vector(32569,AMPL_WIDTH),
conv_std_logic_vector(32569,AMPL_WIDTH),
conv_std_logic_vector(32569,AMPL_WIDTH),
conv_std_logic_vector(32570,AMPL_WIDTH),
conv_std_logic_vector(32570,AMPL_WIDTH),
conv_std_logic_vector(32570,AMPL_WIDTH),
conv_std_logic_vector(32571,AMPL_WIDTH),
conv_std_logic_vector(32571,AMPL_WIDTH),
conv_std_logic_vector(32571,AMPL_WIDTH),
conv_std_logic_vector(32572,AMPL_WIDTH),
conv_std_logic_vector(32572,AMPL_WIDTH),
conv_std_logic_vector(32573,AMPL_WIDTH),
conv_std_logic_vector(32573,AMPL_WIDTH),
conv_std_logic_vector(32573,AMPL_WIDTH),
conv_std_logic_vector(32574,AMPL_WIDTH),
conv_std_logic_vector(32574,AMPL_WIDTH),
conv_std_logic_vector(32574,AMPL_WIDTH),
conv_std_logic_vector(32575,AMPL_WIDTH),
conv_std_logic_vector(32575,AMPL_WIDTH),
conv_std_logic_vector(32575,AMPL_WIDTH),
conv_std_logic_vector(32576,AMPL_WIDTH),
conv_std_logic_vector(32576,AMPL_WIDTH),
conv_std_logic_vector(32576,AMPL_WIDTH),
conv_std_logic_vector(32577,AMPL_WIDTH),
conv_std_logic_vector(32577,AMPL_WIDTH),
conv_std_logic_vector(32577,AMPL_WIDTH),
conv_std_logic_vector(32578,AMPL_WIDTH),
conv_std_logic_vector(32578,AMPL_WIDTH),
conv_std_logic_vector(32578,AMPL_WIDTH),
conv_std_logic_vector(32579,AMPL_WIDTH),
conv_std_logic_vector(32579,AMPL_WIDTH),
conv_std_logic_vector(32579,AMPL_WIDTH),
conv_std_logic_vector(32580,AMPL_WIDTH),
conv_std_logic_vector(32580,AMPL_WIDTH),
conv_std_logic_vector(32580,AMPL_WIDTH),
conv_std_logic_vector(32581,AMPL_WIDTH),
conv_std_logic_vector(32581,AMPL_WIDTH),
conv_std_logic_vector(32581,AMPL_WIDTH),
conv_std_logic_vector(32582,AMPL_WIDTH),
conv_std_logic_vector(32582,AMPL_WIDTH),
conv_std_logic_vector(32582,AMPL_WIDTH),
conv_std_logic_vector(32583,AMPL_WIDTH),
conv_std_logic_vector(32583,AMPL_WIDTH),
conv_std_logic_vector(32583,AMPL_WIDTH),
conv_std_logic_vector(32584,AMPL_WIDTH),
conv_std_logic_vector(32584,AMPL_WIDTH),
conv_std_logic_vector(32584,AMPL_WIDTH),
conv_std_logic_vector(32585,AMPL_WIDTH),
conv_std_logic_vector(32585,AMPL_WIDTH),
conv_std_logic_vector(32585,AMPL_WIDTH),
conv_std_logic_vector(32586,AMPL_WIDTH),
conv_std_logic_vector(32586,AMPL_WIDTH),
conv_std_logic_vector(32586,AMPL_WIDTH),
conv_std_logic_vector(32587,AMPL_WIDTH),
conv_std_logic_vector(32587,AMPL_WIDTH),
conv_std_logic_vector(32587,AMPL_WIDTH),
conv_std_logic_vector(32588,AMPL_WIDTH),
conv_std_logic_vector(32588,AMPL_WIDTH),
conv_std_logic_vector(32588,AMPL_WIDTH),
conv_std_logic_vector(32589,AMPL_WIDTH),
conv_std_logic_vector(32589,AMPL_WIDTH),
conv_std_logic_vector(32589,AMPL_WIDTH),
conv_std_logic_vector(32590,AMPL_WIDTH),
conv_std_logic_vector(32590,AMPL_WIDTH),
conv_std_logic_vector(32590,AMPL_WIDTH),
conv_std_logic_vector(32591,AMPL_WIDTH),
conv_std_logic_vector(32591,AMPL_WIDTH),
conv_std_logic_vector(32591,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32593,AMPL_WIDTH),
conv_std_logic_vector(32593,AMPL_WIDTH),
conv_std_logic_vector(32593,AMPL_WIDTH),
conv_std_logic_vector(32594,AMPL_WIDTH),
conv_std_logic_vector(32594,AMPL_WIDTH),
conv_std_logic_vector(32594,AMPL_WIDTH),
conv_std_logic_vector(32595,AMPL_WIDTH),
conv_std_logic_vector(32595,AMPL_WIDTH),
conv_std_logic_vector(32595,AMPL_WIDTH),
conv_std_logic_vector(32596,AMPL_WIDTH),
conv_std_logic_vector(32596,AMPL_WIDTH),
conv_std_logic_vector(32596,AMPL_WIDTH),
conv_std_logic_vector(32597,AMPL_WIDTH),
conv_std_logic_vector(32597,AMPL_WIDTH),
conv_std_logic_vector(32597,AMPL_WIDTH),
conv_std_logic_vector(32598,AMPL_WIDTH),
conv_std_logic_vector(32598,AMPL_WIDTH),
conv_std_logic_vector(32598,AMPL_WIDTH),
conv_std_logic_vector(32599,AMPL_WIDTH),
conv_std_logic_vector(32599,AMPL_WIDTH),
conv_std_logic_vector(32599,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32601,AMPL_WIDTH),
conv_std_logic_vector(32601,AMPL_WIDTH),
conv_std_logic_vector(32601,AMPL_WIDTH),
conv_std_logic_vector(32602,AMPL_WIDTH),
conv_std_logic_vector(32602,AMPL_WIDTH),
conv_std_logic_vector(32602,AMPL_WIDTH),
conv_std_logic_vector(32603,AMPL_WIDTH),
conv_std_logic_vector(32603,AMPL_WIDTH),
conv_std_logic_vector(32603,AMPL_WIDTH),
conv_std_logic_vector(32604,AMPL_WIDTH),
conv_std_logic_vector(32604,AMPL_WIDTH),
conv_std_logic_vector(32604,AMPL_WIDTH),
conv_std_logic_vector(32605,AMPL_WIDTH),
conv_std_logic_vector(32605,AMPL_WIDTH),
conv_std_logic_vector(32605,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32607,AMPL_WIDTH),
conv_std_logic_vector(32607,AMPL_WIDTH),
conv_std_logic_vector(32607,AMPL_WIDTH),
conv_std_logic_vector(32608,AMPL_WIDTH),
conv_std_logic_vector(32608,AMPL_WIDTH),
conv_std_logic_vector(32608,AMPL_WIDTH),
conv_std_logic_vector(32609,AMPL_WIDTH),
conv_std_logic_vector(32609,AMPL_WIDTH),
conv_std_logic_vector(32609,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32611,AMPL_WIDTH),
conv_std_logic_vector(32611,AMPL_WIDTH),
conv_std_logic_vector(32611,AMPL_WIDTH),
conv_std_logic_vector(32612,AMPL_WIDTH),
conv_std_logic_vector(32612,AMPL_WIDTH),
conv_std_logic_vector(32612,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32614,AMPL_WIDTH),
conv_std_logic_vector(32614,AMPL_WIDTH),
conv_std_logic_vector(32614,AMPL_WIDTH),
conv_std_logic_vector(32615,AMPL_WIDTH),
conv_std_logic_vector(32615,AMPL_WIDTH),
conv_std_logic_vector(32615,AMPL_WIDTH),
conv_std_logic_vector(32616,AMPL_WIDTH),
conv_std_logic_vector(32616,AMPL_WIDTH),
conv_std_logic_vector(32616,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32618,AMPL_WIDTH),
conv_std_logic_vector(32618,AMPL_WIDTH),
conv_std_logic_vector(32618,AMPL_WIDTH),
conv_std_logic_vector(32619,AMPL_WIDTH),
conv_std_logic_vector(32619,AMPL_WIDTH),
conv_std_logic_vector(32619,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32621,AMPL_WIDTH),
conv_std_logic_vector(32621,AMPL_WIDTH),
conv_std_logic_vector(32621,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32623,AMPL_WIDTH),
conv_std_logic_vector(32623,AMPL_WIDTH),
conv_std_logic_vector(32623,AMPL_WIDTH),
conv_std_logic_vector(32624,AMPL_WIDTH),
conv_std_logic_vector(32624,AMPL_WIDTH),
conv_std_logic_vector(32624,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32626,AMPL_WIDTH),
conv_std_logic_vector(32626,AMPL_WIDTH),
conv_std_logic_vector(32626,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32628,AMPL_WIDTH),
conv_std_logic_vector(32628,AMPL_WIDTH),
conv_std_logic_vector(32628,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32630,AMPL_WIDTH),
conv_std_logic_vector(32630,AMPL_WIDTH),
conv_std_logic_vector(32630,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32632,AMPL_WIDTH),
conv_std_logic_vector(32632,AMPL_WIDTH),
conv_std_logic_vector(32632,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32634,AMPL_WIDTH),
conv_std_logic_vector(32634,AMPL_WIDTH),
conv_std_logic_vector(32634,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32636,AMPL_WIDTH),
conv_std_logic_vector(32636,AMPL_WIDTH),
conv_std_logic_vector(32636,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32638,AMPL_WIDTH),
conv_std_logic_vector(32638,AMPL_WIDTH),
conv_std_logic_vector(32638,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32641,AMPL_WIDTH),
conv_std_logic_vector(32641,AMPL_WIDTH),
conv_std_logic_vector(32641,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32644,AMPL_WIDTH),
conv_std_logic_vector(32644,AMPL_WIDTH),
conv_std_logic_vector(32644,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32647,AMPL_WIDTH),
conv_std_logic_vector(32647,AMPL_WIDTH),
conv_std_logic_vector(32647,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32651,AMPL_WIDTH),
conv_std_logic_vector(32651,AMPL_WIDTH),
conv_std_logic_vector(32651,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32658,AMPL_WIDTH),
conv_std_logic_vector(32658,AMPL_WIDTH),
conv_std_logic_vector(32658,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
-- This file is automatically generated by a matlab script
--
-- Do not modify directly!
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_signed.all;
package sine_lut_pkg is
constant PHASE_WIDTH : integer := 16;
constant AMPL_WIDTH : integer := 16;
type lut_type is array(0 to 2**(PHASE_WIDTH-2)-1) of std_logic_vector(AMPL_WIDTH-1 downto 0);
constant sine_lut : lut_type := (
conv_std_logic_vector(0,AMPL_WIDTH),
conv_std_logic_vector(3,AMPL_WIDTH),
conv_std_logic_vector(6,AMPL_WIDTH),
conv_std_logic_vector(9,AMPL_WIDTH),
conv_std_logic_vector(13,AMPL_WIDTH),
conv_std_logic_vector(16,AMPL_WIDTH),
conv_std_logic_vector(19,AMPL_WIDTH),
conv_std_logic_vector(22,AMPL_WIDTH),
conv_std_logic_vector(25,AMPL_WIDTH),
conv_std_logic_vector(28,AMPL_WIDTH),
conv_std_logic_vector(31,AMPL_WIDTH),
conv_std_logic_vector(35,AMPL_WIDTH),
conv_std_logic_vector(38,AMPL_WIDTH),
conv_std_logic_vector(41,AMPL_WIDTH),
conv_std_logic_vector(44,AMPL_WIDTH),
conv_std_logic_vector(47,AMPL_WIDTH),
conv_std_logic_vector(50,AMPL_WIDTH),
conv_std_logic_vector(53,AMPL_WIDTH),
conv_std_logic_vector(57,AMPL_WIDTH),
conv_std_logic_vector(60,AMPL_WIDTH),
conv_std_logic_vector(63,AMPL_WIDTH),
conv_std_logic_vector(66,AMPL_WIDTH),
conv_std_logic_vector(69,AMPL_WIDTH),
conv_std_logic_vector(72,AMPL_WIDTH),
conv_std_logic_vector(75,AMPL_WIDTH),
conv_std_logic_vector(79,AMPL_WIDTH),
conv_std_logic_vector(82,AMPL_WIDTH),
conv_std_logic_vector(85,AMPL_WIDTH),
conv_std_logic_vector(88,AMPL_WIDTH),
conv_std_logic_vector(91,AMPL_WIDTH),
conv_std_logic_vector(94,AMPL_WIDTH),
conv_std_logic_vector(97,AMPL_WIDTH),
conv_std_logic_vector(101,AMPL_WIDTH),
conv_std_logic_vector(104,AMPL_WIDTH),
conv_std_logic_vector(107,AMPL_WIDTH),
conv_std_logic_vector(110,AMPL_WIDTH),
conv_std_logic_vector(113,AMPL_WIDTH),
conv_std_logic_vector(116,AMPL_WIDTH),
conv_std_logic_vector(119,AMPL_WIDTH),
conv_std_logic_vector(123,AMPL_WIDTH),
conv_std_logic_vector(126,AMPL_WIDTH),
conv_std_logic_vector(129,AMPL_WIDTH),
conv_std_logic_vector(132,AMPL_WIDTH),
conv_std_logic_vector(135,AMPL_WIDTH),
conv_std_logic_vector(138,AMPL_WIDTH),
conv_std_logic_vector(141,AMPL_WIDTH),
conv_std_logic_vector(145,AMPL_WIDTH),
conv_std_logic_vector(148,AMPL_WIDTH),
conv_std_logic_vector(151,AMPL_WIDTH),
conv_std_logic_vector(154,AMPL_WIDTH),
conv_std_logic_vector(157,AMPL_WIDTH),
conv_std_logic_vector(160,AMPL_WIDTH),
conv_std_logic_vector(163,AMPL_WIDTH),
conv_std_logic_vector(166,AMPL_WIDTH),
conv_std_logic_vector(170,AMPL_WIDTH),
conv_std_logic_vector(173,AMPL_WIDTH),
conv_std_logic_vector(176,AMPL_WIDTH),
conv_std_logic_vector(179,AMPL_WIDTH),
conv_std_logic_vector(182,AMPL_WIDTH),
conv_std_logic_vector(185,AMPL_WIDTH),
conv_std_logic_vector(188,AMPL_WIDTH),
conv_std_logic_vector(192,AMPL_WIDTH),
conv_std_logic_vector(195,AMPL_WIDTH),
conv_std_logic_vector(198,AMPL_WIDTH),
conv_std_logic_vector(201,AMPL_WIDTH),
conv_std_logic_vector(204,AMPL_WIDTH),
conv_std_logic_vector(207,AMPL_WIDTH),
conv_std_logic_vector(210,AMPL_WIDTH),
conv_std_logic_vector(214,AMPL_WIDTH),
conv_std_logic_vector(217,AMPL_WIDTH),
conv_std_logic_vector(220,AMPL_WIDTH),
conv_std_logic_vector(223,AMPL_WIDTH),
conv_std_logic_vector(226,AMPL_WIDTH),
conv_std_logic_vector(229,AMPL_WIDTH),
conv_std_logic_vector(232,AMPL_WIDTH),
conv_std_logic_vector(236,AMPL_WIDTH),
conv_std_logic_vector(239,AMPL_WIDTH),
conv_std_logic_vector(242,AMPL_WIDTH),
conv_std_logic_vector(245,AMPL_WIDTH),
conv_std_logic_vector(248,AMPL_WIDTH),
conv_std_logic_vector(251,AMPL_WIDTH),
conv_std_logic_vector(254,AMPL_WIDTH),
conv_std_logic_vector(258,AMPL_WIDTH),
conv_std_logic_vector(261,AMPL_WIDTH),
conv_std_logic_vector(264,AMPL_WIDTH),
conv_std_logic_vector(267,AMPL_WIDTH),
conv_std_logic_vector(270,AMPL_WIDTH),
conv_std_logic_vector(273,AMPL_WIDTH),
conv_std_logic_vector(276,AMPL_WIDTH),
conv_std_logic_vector(280,AMPL_WIDTH),
conv_std_logic_vector(283,AMPL_WIDTH),
conv_std_logic_vector(286,AMPL_WIDTH),
conv_std_logic_vector(289,AMPL_WIDTH),
conv_std_logic_vector(292,AMPL_WIDTH),
conv_std_logic_vector(295,AMPL_WIDTH),
conv_std_logic_vector(298,AMPL_WIDTH),
conv_std_logic_vector(302,AMPL_WIDTH),
conv_std_logic_vector(305,AMPL_WIDTH),
conv_std_logic_vector(308,AMPL_WIDTH),
conv_std_logic_vector(311,AMPL_WIDTH),
conv_std_logic_vector(314,AMPL_WIDTH),
conv_std_logic_vector(317,AMPL_WIDTH),
conv_std_logic_vector(320,AMPL_WIDTH),
conv_std_logic_vector(324,AMPL_WIDTH),
conv_std_logic_vector(327,AMPL_WIDTH),
conv_std_logic_vector(330,AMPL_WIDTH),
conv_std_logic_vector(333,AMPL_WIDTH),
conv_std_logic_vector(336,AMPL_WIDTH),
conv_std_logic_vector(339,AMPL_WIDTH),
conv_std_logic_vector(342,AMPL_WIDTH),
conv_std_logic_vector(346,AMPL_WIDTH),
conv_std_logic_vector(349,AMPL_WIDTH),
conv_std_logic_vector(352,AMPL_WIDTH),
conv_std_logic_vector(355,AMPL_WIDTH),
conv_std_logic_vector(358,AMPL_WIDTH),
conv_std_logic_vector(361,AMPL_WIDTH),
conv_std_logic_vector(364,AMPL_WIDTH),
conv_std_logic_vector(368,AMPL_WIDTH),
conv_std_logic_vector(371,AMPL_WIDTH),
conv_std_logic_vector(374,AMPL_WIDTH),
conv_std_logic_vector(377,AMPL_WIDTH),
conv_std_logic_vector(380,AMPL_WIDTH),
conv_std_logic_vector(383,AMPL_WIDTH),
conv_std_logic_vector(386,AMPL_WIDTH),
conv_std_logic_vector(390,AMPL_WIDTH),
conv_std_logic_vector(393,AMPL_WIDTH),
conv_std_logic_vector(396,AMPL_WIDTH),
conv_std_logic_vector(399,AMPL_WIDTH),
conv_std_logic_vector(402,AMPL_WIDTH),
conv_std_logic_vector(405,AMPL_WIDTH),
conv_std_logic_vector(408,AMPL_WIDTH),
conv_std_logic_vector(412,AMPL_WIDTH),
conv_std_logic_vector(415,AMPL_WIDTH),
conv_std_logic_vector(418,AMPL_WIDTH),
conv_std_logic_vector(421,AMPL_WIDTH),
conv_std_logic_vector(424,AMPL_WIDTH),
conv_std_logic_vector(427,AMPL_WIDTH),
conv_std_logic_vector(430,AMPL_WIDTH),
conv_std_logic_vector(434,AMPL_WIDTH),
conv_std_logic_vector(437,AMPL_WIDTH),
conv_std_logic_vector(440,AMPL_WIDTH),
conv_std_logic_vector(443,AMPL_WIDTH),
conv_std_logic_vector(446,AMPL_WIDTH),
conv_std_logic_vector(449,AMPL_WIDTH),
conv_std_logic_vector(452,AMPL_WIDTH),
conv_std_logic_vector(456,AMPL_WIDTH),
conv_std_logic_vector(459,AMPL_WIDTH),
conv_std_logic_vector(462,AMPL_WIDTH),
conv_std_logic_vector(465,AMPL_WIDTH),
conv_std_logic_vector(468,AMPL_WIDTH),
conv_std_logic_vector(471,AMPL_WIDTH),
conv_std_logic_vector(474,AMPL_WIDTH),
conv_std_logic_vector(477,AMPL_WIDTH),
conv_std_logic_vector(481,AMPL_WIDTH),
conv_std_logic_vector(484,AMPL_WIDTH),
conv_std_logic_vector(487,AMPL_WIDTH),
conv_std_logic_vector(490,AMPL_WIDTH),
conv_std_logic_vector(493,AMPL_WIDTH),
conv_std_logic_vector(496,AMPL_WIDTH),
conv_std_logic_vector(499,AMPL_WIDTH),
conv_std_logic_vector(503,AMPL_WIDTH),
conv_std_logic_vector(506,AMPL_WIDTH),
conv_std_logic_vector(509,AMPL_WIDTH),
conv_std_logic_vector(512,AMPL_WIDTH),
conv_std_logic_vector(515,AMPL_WIDTH),
conv_std_logic_vector(518,AMPL_WIDTH),
conv_std_logic_vector(521,AMPL_WIDTH),
conv_std_logic_vector(525,AMPL_WIDTH),
conv_std_logic_vector(528,AMPL_WIDTH),
conv_std_logic_vector(531,AMPL_WIDTH),
conv_std_logic_vector(534,AMPL_WIDTH),
conv_std_logic_vector(537,AMPL_WIDTH),
conv_std_logic_vector(540,AMPL_WIDTH),
conv_std_logic_vector(543,AMPL_WIDTH),
conv_std_logic_vector(547,AMPL_WIDTH),
conv_std_logic_vector(550,AMPL_WIDTH),
conv_std_logic_vector(553,AMPL_WIDTH),
conv_std_logic_vector(556,AMPL_WIDTH),
conv_std_logic_vector(559,AMPL_WIDTH),
conv_std_logic_vector(562,AMPL_WIDTH),
conv_std_logic_vector(565,AMPL_WIDTH),
conv_std_logic_vector(569,AMPL_WIDTH),
conv_std_logic_vector(572,AMPL_WIDTH),
conv_std_logic_vector(575,AMPL_WIDTH),
conv_std_logic_vector(578,AMPL_WIDTH),
conv_std_logic_vector(581,AMPL_WIDTH),
conv_std_logic_vector(584,AMPL_WIDTH),
conv_std_logic_vector(587,AMPL_WIDTH),
conv_std_logic_vector(591,AMPL_WIDTH),
conv_std_logic_vector(594,AMPL_WIDTH),
conv_std_logic_vector(597,AMPL_WIDTH),
conv_std_logic_vector(600,AMPL_WIDTH),
conv_std_logic_vector(603,AMPL_WIDTH),
conv_std_logic_vector(606,AMPL_WIDTH),
conv_std_logic_vector(609,AMPL_WIDTH),
conv_std_logic_vector(613,AMPL_WIDTH),
conv_std_logic_vector(616,AMPL_WIDTH),
conv_std_logic_vector(619,AMPL_WIDTH),
conv_std_logic_vector(622,AMPL_WIDTH),
conv_std_logic_vector(625,AMPL_WIDTH),
conv_std_logic_vector(628,AMPL_WIDTH),
conv_std_logic_vector(631,AMPL_WIDTH),
conv_std_logic_vector(635,AMPL_WIDTH),
conv_std_logic_vector(638,AMPL_WIDTH),
conv_std_logic_vector(641,AMPL_WIDTH),
conv_std_logic_vector(644,AMPL_WIDTH),
conv_std_logic_vector(647,AMPL_WIDTH),
conv_std_logic_vector(650,AMPL_WIDTH),
conv_std_logic_vector(653,AMPL_WIDTH),
conv_std_logic_vector(657,AMPL_WIDTH),
conv_std_logic_vector(660,AMPL_WIDTH),
conv_std_logic_vector(663,AMPL_WIDTH),
conv_std_logic_vector(666,AMPL_WIDTH),
conv_std_logic_vector(669,AMPL_WIDTH),
conv_std_logic_vector(672,AMPL_WIDTH),
conv_std_logic_vector(675,AMPL_WIDTH),
conv_std_logic_vector(679,AMPL_WIDTH),
conv_std_logic_vector(682,AMPL_WIDTH),
conv_std_logic_vector(685,AMPL_WIDTH),
conv_std_logic_vector(688,AMPL_WIDTH),
conv_std_logic_vector(691,AMPL_WIDTH),
conv_std_logic_vector(694,AMPL_WIDTH),
conv_std_logic_vector(697,AMPL_WIDTH),
conv_std_logic_vector(701,AMPL_WIDTH),
conv_std_logic_vector(704,AMPL_WIDTH),
conv_std_logic_vector(707,AMPL_WIDTH),
conv_std_logic_vector(710,AMPL_WIDTH),
conv_std_logic_vector(713,AMPL_WIDTH),
conv_std_logic_vector(716,AMPL_WIDTH),
conv_std_logic_vector(719,AMPL_WIDTH),
conv_std_logic_vector(722,AMPL_WIDTH),
conv_std_logic_vector(726,AMPL_WIDTH),
conv_std_logic_vector(729,AMPL_WIDTH),
conv_std_logic_vector(732,AMPL_WIDTH),
conv_std_logic_vector(735,AMPL_WIDTH),
conv_std_logic_vector(738,AMPL_WIDTH),
conv_std_logic_vector(741,AMPL_WIDTH),
conv_std_logic_vector(744,AMPL_WIDTH),
conv_std_logic_vector(748,AMPL_WIDTH),
conv_std_logic_vector(751,AMPL_WIDTH),
conv_std_logic_vector(754,AMPL_WIDTH),
conv_std_logic_vector(757,AMPL_WIDTH),
conv_std_logic_vector(760,AMPL_WIDTH),
conv_std_logic_vector(763,AMPL_WIDTH),
conv_std_logic_vector(766,AMPL_WIDTH),
conv_std_logic_vector(770,AMPL_WIDTH),
conv_std_logic_vector(773,AMPL_WIDTH),
conv_std_logic_vector(776,AMPL_WIDTH),
conv_std_logic_vector(779,AMPL_WIDTH),
conv_std_logic_vector(782,AMPL_WIDTH),
conv_std_logic_vector(785,AMPL_WIDTH),
conv_std_logic_vector(788,AMPL_WIDTH),
conv_std_logic_vector(792,AMPL_WIDTH),
conv_std_logic_vector(795,AMPL_WIDTH),
conv_std_logic_vector(798,AMPL_WIDTH),
conv_std_logic_vector(801,AMPL_WIDTH),
conv_std_logic_vector(804,AMPL_WIDTH),
conv_std_logic_vector(807,AMPL_WIDTH),
conv_std_logic_vector(810,AMPL_WIDTH),
conv_std_logic_vector(814,AMPL_WIDTH),
conv_std_logic_vector(817,AMPL_WIDTH),
conv_std_logic_vector(820,AMPL_WIDTH),
conv_std_logic_vector(823,AMPL_WIDTH),
conv_std_logic_vector(826,AMPL_WIDTH),
conv_std_logic_vector(829,AMPL_WIDTH),
conv_std_logic_vector(832,AMPL_WIDTH),
conv_std_logic_vector(836,AMPL_WIDTH),
conv_std_logic_vector(839,AMPL_WIDTH),
conv_std_logic_vector(842,AMPL_WIDTH),
conv_std_logic_vector(845,AMPL_WIDTH),
conv_std_logic_vector(848,AMPL_WIDTH),
conv_std_logic_vector(851,AMPL_WIDTH),
conv_std_logic_vector(854,AMPL_WIDTH),
conv_std_logic_vector(858,AMPL_WIDTH),
conv_std_logic_vector(861,AMPL_WIDTH),
conv_std_logic_vector(864,AMPL_WIDTH),
conv_std_logic_vector(867,AMPL_WIDTH),
conv_std_logic_vector(870,AMPL_WIDTH),
conv_std_logic_vector(873,AMPL_WIDTH),
conv_std_logic_vector(876,AMPL_WIDTH),
conv_std_logic_vector(880,AMPL_WIDTH),
conv_std_logic_vector(883,AMPL_WIDTH),
conv_std_logic_vector(886,AMPL_WIDTH),
conv_std_logic_vector(889,AMPL_WIDTH),
conv_std_logic_vector(892,AMPL_WIDTH),
conv_std_logic_vector(895,AMPL_WIDTH),
conv_std_logic_vector(898,AMPL_WIDTH),
conv_std_logic_vector(901,AMPL_WIDTH),
conv_std_logic_vector(905,AMPL_WIDTH),
conv_std_logic_vector(908,AMPL_WIDTH),
conv_std_logic_vector(911,AMPL_WIDTH),
conv_std_logic_vector(914,AMPL_WIDTH),
conv_std_logic_vector(917,AMPL_WIDTH),
conv_std_logic_vector(920,AMPL_WIDTH),
conv_std_logic_vector(923,AMPL_WIDTH),
conv_std_logic_vector(927,AMPL_WIDTH),
conv_std_logic_vector(930,AMPL_WIDTH),
conv_std_logic_vector(933,AMPL_WIDTH),
conv_std_logic_vector(936,AMPL_WIDTH),
conv_std_logic_vector(939,AMPL_WIDTH),
conv_std_logic_vector(942,AMPL_WIDTH),
conv_std_logic_vector(945,AMPL_WIDTH),
conv_std_logic_vector(949,AMPL_WIDTH),
conv_std_logic_vector(952,AMPL_WIDTH),
conv_std_logic_vector(955,AMPL_WIDTH),
conv_std_logic_vector(958,AMPL_WIDTH),
conv_std_logic_vector(961,AMPL_WIDTH),
conv_std_logic_vector(964,AMPL_WIDTH),
conv_std_logic_vector(967,AMPL_WIDTH),
conv_std_logic_vector(971,AMPL_WIDTH),
conv_std_logic_vector(974,AMPL_WIDTH),
conv_std_logic_vector(977,AMPL_WIDTH),
conv_std_logic_vector(980,AMPL_WIDTH),
conv_std_logic_vector(983,AMPL_WIDTH),
conv_std_logic_vector(986,AMPL_WIDTH),
conv_std_logic_vector(989,AMPL_WIDTH),
conv_std_logic_vector(993,AMPL_WIDTH),
conv_std_logic_vector(996,AMPL_WIDTH),
conv_std_logic_vector(999,AMPL_WIDTH),
conv_std_logic_vector(1002,AMPL_WIDTH),
conv_std_logic_vector(1005,AMPL_WIDTH),
conv_std_logic_vector(1008,AMPL_WIDTH),
conv_std_logic_vector(1011,AMPL_WIDTH),
conv_std_logic_vector(1015,AMPL_WIDTH),
conv_std_logic_vector(1018,AMPL_WIDTH),
conv_std_logic_vector(1021,AMPL_WIDTH),
conv_std_logic_vector(1024,AMPL_WIDTH),
conv_std_logic_vector(1027,AMPL_WIDTH),
conv_std_logic_vector(1030,AMPL_WIDTH),
conv_std_logic_vector(1033,AMPL_WIDTH),
conv_std_logic_vector(1037,AMPL_WIDTH),
conv_std_logic_vector(1040,AMPL_WIDTH),
conv_std_logic_vector(1043,AMPL_WIDTH),
conv_std_logic_vector(1046,AMPL_WIDTH),
conv_std_logic_vector(1049,AMPL_WIDTH),
conv_std_logic_vector(1052,AMPL_WIDTH),
conv_std_logic_vector(1055,AMPL_WIDTH),
conv_std_logic_vector(1059,AMPL_WIDTH),
conv_std_logic_vector(1062,AMPL_WIDTH),
conv_std_logic_vector(1065,AMPL_WIDTH),
conv_std_logic_vector(1068,AMPL_WIDTH),
conv_std_logic_vector(1071,AMPL_WIDTH),
conv_std_logic_vector(1074,AMPL_WIDTH),
conv_std_logic_vector(1077,AMPL_WIDTH),
conv_std_logic_vector(1080,AMPL_WIDTH),
conv_std_logic_vector(1084,AMPL_WIDTH),
conv_std_logic_vector(1087,AMPL_WIDTH),
conv_std_logic_vector(1090,AMPL_WIDTH),
conv_std_logic_vector(1093,AMPL_WIDTH),
conv_std_logic_vector(1096,AMPL_WIDTH),
conv_std_logic_vector(1099,AMPL_WIDTH),
conv_std_logic_vector(1102,AMPL_WIDTH),
conv_std_logic_vector(1106,AMPL_WIDTH),
conv_std_logic_vector(1109,AMPL_WIDTH),
conv_std_logic_vector(1112,AMPL_WIDTH),
conv_std_logic_vector(1115,AMPL_WIDTH),
conv_std_logic_vector(1118,AMPL_WIDTH),
conv_std_logic_vector(1121,AMPL_WIDTH),
conv_std_logic_vector(1124,AMPL_WIDTH),
conv_std_logic_vector(1128,AMPL_WIDTH),
conv_std_logic_vector(1131,AMPL_WIDTH),
conv_std_logic_vector(1134,AMPL_WIDTH),
conv_std_logic_vector(1137,AMPL_WIDTH),
conv_std_logic_vector(1140,AMPL_WIDTH),
conv_std_logic_vector(1143,AMPL_WIDTH),
conv_std_logic_vector(1146,AMPL_WIDTH),
conv_std_logic_vector(1150,AMPL_WIDTH),
conv_std_logic_vector(1153,AMPL_WIDTH),
conv_std_logic_vector(1156,AMPL_WIDTH),
conv_std_logic_vector(1159,AMPL_WIDTH),
conv_std_logic_vector(1162,AMPL_WIDTH),
conv_std_logic_vector(1165,AMPL_WIDTH),
conv_std_logic_vector(1168,AMPL_WIDTH),
conv_std_logic_vector(1172,AMPL_WIDTH),
conv_std_logic_vector(1175,AMPL_WIDTH),
conv_std_logic_vector(1178,AMPL_WIDTH),
conv_std_logic_vector(1181,AMPL_WIDTH),
conv_std_logic_vector(1184,AMPL_WIDTH),
conv_std_logic_vector(1187,AMPL_WIDTH),
conv_std_logic_vector(1190,AMPL_WIDTH),
conv_std_logic_vector(1194,AMPL_WIDTH),
conv_std_logic_vector(1197,AMPL_WIDTH),
conv_std_logic_vector(1200,AMPL_WIDTH),
conv_std_logic_vector(1203,AMPL_WIDTH),
conv_std_logic_vector(1206,AMPL_WIDTH),
conv_std_logic_vector(1209,AMPL_WIDTH),
conv_std_logic_vector(1212,AMPL_WIDTH),
conv_std_logic_vector(1215,AMPL_WIDTH),
conv_std_logic_vector(1219,AMPL_WIDTH),
conv_std_logic_vector(1222,AMPL_WIDTH),
conv_std_logic_vector(1225,AMPL_WIDTH),
conv_std_logic_vector(1228,AMPL_WIDTH),
conv_std_logic_vector(1231,AMPL_WIDTH),
conv_std_logic_vector(1234,AMPL_WIDTH),
conv_std_logic_vector(1237,AMPL_WIDTH),
conv_std_logic_vector(1241,AMPL_WIDTH),
conv_std_logic_vector(1244,AMPL_WIDTH),
conv_std_logic_vector(1247,AMPL_WIDTH),
conv_std_logic_vector(1250,AMPL_WIDTH),
conv_std_logic_vector(1253,AMPL_WIDTH),
conv_std_logic_vector(1256,AMPL_WIDTH),
conv_std_logic_vector(1259,AMPL_WIDTH),
conv_std_logic_vector(1263,AMPL_WIDTH),
conv_std_logic_vector(1266,AMPL_WIDTH),
conv_std_logic_vector(1269,AMPL_WIDTH),
conv_std_logic_vector(1272,AMPL_WIDTH),
conv_std_logic_vector(1275,AMPL_WIDTH),
conv_std_logic_vector(1278,AMPL_WIDTH),
conv_std_logic_vector(1281,AMPL_WIDTH),
conv_std_logic_vector(1285,AMPL_WIDTH),
conv_std_logic_vector(1288,AMPL_WIDTH),
conv_std_logic_vector(1291,AMPL_WIDTH),
conv_std_logic_vector(1294,AMPL_WIDTH),
conv_std_logic_vector(1297,AMPL_WIDTH),
conv_std_logic_vector(1300,AMPL_WIDTH),
conv_std_logic_vector(1303,AMPL_WIDTH),
conv_std_logic_vector(1307,AMPL_WIDTH),
conv_std_logic_vector(1310,AMPL_WIDTH),
conv_std_logic_vector(1313,AMPL_WIDTH),
conv_std_logic_vector(1316,AMPL_WIDTH),
conv_std_logic_vector(1319,AMPL_WIDTH),
conv_std_logic_vector(1322,AMPL_WIDTH),
conv_std_logic_vector(1325,AMPL_WIDTH),
conv_std_logic_vector(1328,AMPL_WIDTH),
conv_std_logic_vector(1332,AMPL_WIDTH),
conv_std_logic_vector(1335,AMPL_WIDTH),
conv_std_logic_vector(1338,AMPL_WIDTH),
conv_std_logic_vector(1341,AMPL_WIDTH),
conv_std_logic_vector(1344,AMPL_WIDTH),
conv_std_logic_vector(1347,AMPL_WIDTH),
conv_std_logic_vector(1350,AMPL_WIDTH),
conv_std_logic_vector(1354,AMPL_WIDTH),
conv_std_logic_vector(1357,AMPL_WIDTH),
conv_std_logic_vector(1360,AMPL_WIDTH),
conv_std_logic_vector(1363,AMPL_WIDTH),
conv_std_logic_vector(1366,AMPL_WIDTH),
conv_std_logic_vector(1369,AMPL_WIDTH),
conv_std_logic_vector(1372,AMPL_WIDTH),
conv_std_logic_vector(1376,AMPL_WIDTH),
conv_std_logic_vector(1379,AMPL_WIDTH),
conv_std_logic_vector(1382,AMPL_WIDTH),
conv_std_logic_vector(1385,AMPL_WIDTH),
conv_std_logic_vector(1388,AMPL_WIDTH),
conv_std_logic_vector(1391,AMPL_WIDTH),
conv_std_logic_vector(1394,AMPL_WIDTH),
conv_std_logic_vector(1398,AMPL_WIDTH),
conv_std_logic_vector(1401,AMPL_WIDTH),
conv_std_logic_vector(1404,AMPL_WIDTH),
conv_std_logic_vector(1407,AMPL_WIDTH),
conv_std_logic_vector(1410,AMPL_WIDTH),
conv_std_logic_vector(1413,AMPL_WIDTH),
conv_std_logic_vector(1416,AMPL_WIDTH),
conv_std_logic_vector(1420,AMPL_WIDTH),
conv_std_logic_vector(1423,AMPL_WIDTH),
conv_std_logic_vector(1426,AMPL_WIDTH),
conv_std_logic_vector(1429,AMPL_WIDTH),
conv_std_logic_vector(1432,AMPL_WIDTH),
conv_std_logic_vector(1435,AMPL_WIDTH),
conv_std_logic_vector(1438,AMPL_WIDTH),
conv_std_logic_vector(1441,AMPL_WIDTH),
conv_std_logic_vector(1445,AMPL_WIDTH),
conv_std_logic_vector(1448,AMPL_WIDTH),
conv_std_logic_vector(1451,AMPL_WIDTH),
conv_std_logic_vector(1454,AMPL_WIDTH),
conv_std_logic_vector(1457,AMPL_WIDTH),
conv_std_logic_vector(1460,AMPL_WIDTH),
conv_std_logic_vector(1463,AMPL_WIDTH),
conv_std_logic_vector(1467,AMPL_WIDTH),
conv_std_logic_vector(1470,AMPL_WIDTH),
conv_std_logic_vector(1473,AMPL_WIDTH),
conv_std_logic_vector(1476,AMPL_WIDTH),
conv_std_logic_vector(1479,AMPL_WIDTH),
conv_std_logic_vector(1482,AMPL_WIDTH),
conv_std_logic_vector(1485,AMPL_WIDTH),
conv_std_logic_vector(1489,AMPL_WIDTH),
conv_std_logic_vector(1492,AMPL_WIDTH),
conv_std_logic_vector(1495,AMPL_WIDTH),
conv_std_logic_vector(1498,AMPL_WIDTH),
conv_std_logic_vector(1501,AMPL_WIDTH),
conv_std_logic_vector(1504,AMPL_WIDTH),
conv_std_logic_vector(1507,AMPL_WIDTH),
conv_std_logic_vector(1511,AMPL_WIDTH),
conv_std_logic_vector(1514,AMPL_WIDTH),
conv_std_logic_vector(1517,AMPL_WIDTH),
conv_std_logic_vector(1520,AMPL_WIDTH),
conv_std_logic_vector(1523,AMPL_WIDTH),
conv_std_logic_vector(1526,AMPL_WIDTH),
conv_std_logic_vector(1529,AMPL_WIDTH),
conv_std_logic_vector(1532,AMPL_WIDTH),
conv_std_logic_vector(1536,AMPL_WIDTH),
conv_std_logic_vector(1539,AMPL_WIDTH),
conv_std_logic_vector(1542,AMPL_WIDTH),
conv_std_logic_vector(1545,AMPL_WIDTH),
conv_std_logic_vector(1548,AMPL_WIDTH),
conv_std_logic_vector(1551,AMPL_WIDTH),
conv_std_logic_vector(1554,AMPL_WIDTH),
conv_std_logic_vector(1558,AMPL_WIDTH),
conv_std_logic_vector(1561,AMPL_WIDTH),
conv_std_logic_vector(1564,AMPL_WIDTH),
conv_std_logic_vector(1567,AMPL_WIDTH),
conv_std_logic_vector(1570,AMPL_WIDTH),
conv_std_logic_vector(1573,AMPL_WIDTH),
conv_std_logic_vector(1576,AMPL_WIDTH),
conv_std_logic_vector(1580,AMPL_WIDTH),
conv_std_logic_vector(1583,AMPL_WIDTH),
conv_std_logic_vector(1586,AMPL_WIDTH),
conv_std_logic_vector(1589,AMPL_WIDTH),
conv_std_logic_vector(1592,AMPL_WIDTH),
conv_std_logic_vector(1595,AMPL_WIDTH),
conv_std_logic_vector(1598,AMPL_WIDTH),
conv_std_logic_vector(1602,AMPL_WIDTH),
conv_std_logic_vector(1605,AMPL_WIDTH),
conv_std_logic_vector(1608,AMPL_WIDTH),
conv_std_logic_vector(1611,AMPL_WIDTH),
conv_std_logic_vector(1614,AMPL_WIDTH),
conv_std_logic_vector(1617,AMPL_WIDTH),
conv_std_logic_vector(1620,AMPL_WIDTH),
conv_std_logic_vector(1623,AMPL_WIDTH),
conv_std_logic_vector(1627,AMPL_WIDTH),
conv_std_logic_vector(1630,AMPL_WIDTH),
conv_std_logic_vector(1633,AMPL_WIDTH),
conv_std_logic_vector(1636,AMPL_WIDTH),
conv_std_logic_vector(1639,AMPL_WIDTH),
conv_std_logic_vector(1642,AMPL_WIDTH),
conv_std_logic_vector(1645,AMPL_WIDTH),
conv_std_logic_vector(1649,AMPL_WIDTH),
conv_std_logic_vector(1652,AMPL_WIDTH),
conv_std_logic_vector(1655,AMPL_WIDTH),
conv_std_logic_vector(1658,AMPL_WIDTH),
conv_std_logic_vector(1661,AMPL_WIDTH),
conv_std_logic_vector(1664,AMPL_WIDTH),
conv_std_logic_vector(1667,AMPL_WIDTH),
conv_std_logic_vector(1671,AMPL_WIDTH),
conv_std_logic_vector(1674,AMPL_WIDTH),
conv_std_logic_vector(1677,AMPL_WIDTH),
conv_std_logic_vector(1680,AMPL_WIDTH),
conv_std_logic_vector(1683,AMPL_WIDTH),
conv_std_logic_vector(1686,AMPL_WIDTH),
conv_std_logic_vector(1689,AMPL_WIDTH),
conv_std_logic_vector(1693,AMPL_WIDTH),
conv_std_logic_vector(1696,AMPL_WIDTH),
conv_std_logic_vector(1699,AMPL_WIDTH),
conv_std_logic_vector(1702,AMPL_WIDTH),
conv_std_logic_vector(1705,AMPL_WIDTH),
conv_std_logic_vector(1708,AMPL_WIDTH),
conv_std_logic_vector(1711,AMPL_WIDTH),
conv_std_logic_vector(1714,AMPL_WIDTH),
conv_std_logic_vector(1718,AMPL_WIDTH),
conv_std_logic_vector(1721,AMPL_WIDTH),
conv_std_logic_vector(1724,AMPL_WIDTH),
conv_std_logic_vector(1727,AMPL_WIDTH),
conv_std_logic_vector(1730,AMPL_WIDTH),
conv_std_logic_vector(1733,AMPL_WIDTH),
conv_std_logic_vector(1736,AMPL_WIDTH),
conv_std_logic_vector(1740,AMPL_WIDTH),
conv_std_logic_vector(1743,AMPL_WIDTH),
conv_std_logic_vector(1746,AMPL_WIDTH),
conv_std_logic_vector(1749,AMPL_WIDTH),
conv_std_logic_vector(1752,AMPL_WIDTH),
conv_std_logic_vector(1755,AMPL_WIDTH),
conv_std_logic_vector(1758,AMPL_WIDTH),
conv_std_logic_vector(1762,AMPL_WIDTH),
conv_std_logic_vector(1765,AMPL_WIDTH),
conv_std_logic_vector(1768,AMPL_WIDTH),
conv_std_logic_vector(1771,AMPL_WIDTH),
conv_std_logic_vector(1774,AMPL_WIDTH),
conv_std_logic_vector(1777,AMPL_WIDTH),
conv_std_logic_vector(1780,AMPL_WIDTH),
conv_std_logic_vector(1783,AMPL_WIDTH),
conv_std_logic_vector(1787,AMPL_WIDTH),
conv_std_logic_vector(1790,AMPL_WIDTH),
conv_std_logic_vector(1793,AMPL_WIDTH),
conv_std_logic_vector(1796,AMPL_WIDTH),
conv_std_logic_vector(1799,AMPL_WIDTH),
conv_std_logic_vector(1802,AMPL_WIDTH),
conv_std_logic_vector(1805,AMPL_WIDTH),
conv_std_logic_vector(1809,AMPL_WIDTH),
conv_std_logic_vector(1812,AMPL_WIDTH),
conv_std_logic_vector(1815,AMPL_WIDTH),
conv_std_logic_vector(1818,AMPL_WIDTH),
conv_std_logic_vector(1821,AMPL_WIDTH),
conv_std_logic_vector(1824,AMPL_WIDTH),
conv_std_logic_vector(1827,AMPL_WIDTH),
conv_std_logic_vector(1831,AMPL_WIDTH),
conv_std_logic_vector(1834,AMPL_WIDTH),
conv_std_logic_vector(1837,AMPL_WIDTH),
conv_std_logic_vector(1840,AMPL_WIDTH),
conv_std_logic_vector(1843,AMPL_WIDTH),
conv_std_logic_vector(1846,AMPL_WIDTH),
conv_std_logic_vector(1849,AMPL_WIDTH),
conv_std_logic_vector(1852,AMPL_WIDTH),
conv_std_logic_vector(1856,AMPL_WIDTH),
conv_std_logic_vector(1859,AMPL_WIDTH),
conv_std_logic_vector(1862,AMPL_WIDTH),
conv_std_logic_vector(1865,AMPL_WIDTH),
conv_std_logic_vector(1868,AMPL_WIDTH),
conv_std_logic_vector(1871,AMPL_WIDTH),
conv_std_logic_vector(1874,AMPL_WIDTH),
conv_std_logic_vector(1878,AMPL_WIDTH),
conv_std_logic_vector(1881,AMPL_WIDTH),
conv_std_logic_vector(1884,AMPL_WIDTH),
conv_std_logic_vector(1887,AMPL_WIDTH),
conv_std_logic_vector(1890,AMPL_WIDTH),
conv_std_logic_vector(1893,AMPL_WIDTH),
conv_std_logic_vector(1896,AMPL_WIDTH),
conv_std_logic_vector(1900,AMPL_WIDTH),
conv_std_logic_vector(1903,AMPL_WIDTH),
conv_std_logic_vector(1906,AMPL_WIDTH),
conv_std_logic_vector(1909,AMPL_WIDTH),
conv_std_logic_vector(1912,AMPL_WIDTH),
conv_std_logic_vector(1915,AMPL_WIDTH),
conv_std_logic_vector(1918,AMPL_WIDTH),
conv_std_logic_vector(1921,AMPL_WIDTH),
conv_std_logic_vector(1925,AMPL_WIDTH),
conv_std_logic_vector(1928,AMPL_WIDTH),
conv_std_logic_vector(1931,AMPL_WIDTH),
conv_std_logic_vector(1934,AMPL_WIDTH),
conv_std_logic_vector(1937,AMPL_WIDTH),
conv_std_logic_vector(1940,AMPL_WIDTH),
conv_std_logic_vector(1943,AMPL_WIDTH),
conv_std_logic_vector(1947,AMPL_WIDTH),
conv_std_logic_vector(1950,AMPL_WIDTH),
conv_std_logic_vector(1953,AMPL_WIDTH),
conv_std_logic_vector(1956,AMPL_WIDTH),
conv_std_logic_vector(1959,AMPL_WIDTH),
conv_std_logic_vector(1962,AMPL_WIDTH),
conv_std_logic_vector(1965,AMPL_WIDTH),
conv_std_logic_vector(1969,AMPL_WIDTH),
conv_std_logic_vector(1972,AMPL_WIDTH),
conv_std_logic_vector(1975,AMPL_WIDTH),
conv_std_logic_vector(1978,AMPL_WIDTH),
conv_std_logic_vector(1981,AMPL_WIDTH),
conv_std_logic_vector(1984,AMPL_WIDTH),
conv_std_logic_vector(1987,AMPL_WIDTH),
conv_std_logic_vector(1990,AMPL_WIDTH),
conv_std_logic_vector(1994,AMPL_WIDTH),
conv_std_logic_vector(1997,AMPL_WIDTH),
conv_std_logic_vector(2000,AMPL_WIDTH),
conv_std_logic_vector(2003,AMPL_WIDTH),
conv_std_logic_vector(2006,AMPL_WIDTH),
conv_std_logic_vector(2009,AMPL_WIDTH),
conv_std_logic_vector(2012,AMPL_WIDTH),
conv_std_logic_vector(2016,AMPL_WIDTH),
conv_std_logic_vector(2019,AMPL_WIDTH),
conv_std_logic_vector(2022,AMPL_WIDTH),
conv_std_logic_vector(2025,AMPL_WIDTH),
conv_std_logic_vector(2028,AMPL_WIDTH),
conv_std_logic_vector(2031,AMPL_WIDTH),
conv_std_logic_vector(2034,AMPL_WIDTH),
conv_std_logic_vector(2038,AMPL_WIDTH),
conv_std_logic_vector(2041,AMPL_WIDTH),
conv_std_logic_vector(2044,AMPL_WIDTH),
conv_std_logic_vector(2047,AMPL_WIDTH),
conv_std_logic_vector(2050,AMPL_WIDTH),
conv_std_logic_vector(2053,AMPL_WIDTH),
conv_std_logic_vector(2056,AMPL_WIDTH),
conv_std_logic_vector(2059,AMPL_WIDTH),
conv_std_logic_vector(2063,AMPL_WIDTH),
conv_std_logic_vector(2066,AMPL_WIDTH),
conv_std_logic_vector(2069,AMPL_WIDTH),
conv_std_logic_vector(2072,AMPL_WIDTH),
conv_std_logic_vector(2075,AMPL_WIDTH),
conv_std_logic_vector(2078,AMPL_WIDTH),
conv_std_logic_vector(2081,AMPL_WIDTH),
conv_std_logic_vector(2085,AMPL_WIDTH),
conv_std_logic_vector(2088,AMPL_WIDTH),
conv_std_logic_vector(2091,AMPL_WIDTH),
conv_std_logic_vector(2094,AMPL_WIDTH),
conv_std_logic_vector(2097,AMPL_WIDTH),
conv_std_logic_vector(2100,AMPL_WIDTH),
conv_std_logic_vector(2103,AMPL_WIDTH),
conv_std_logic_vector(2106,AMPL_WIDTH),
conv_std_logic_vector(2110,AMPL_WIDTH),
conv_std_logic_vector(2113,AMPL_WIDTH),
conv_std_logic_vector(2116,AMPL_WIDTH),
conv_std_logic_vector(2119,AMPL_WIDTH),
conv_std_logic_vector(2122,AMPL_WIDTH),
conv_std_logic_vector(2125,AMPL_WIDTH),
conv_std_logic_vector(2128,AMPL_WIDTH),
conv_std_logic_vector(2132,AMPL_WIDTH),
conv_std_logic_vector(2135,AMPL_WIDTH),
conv_std_logic_vector(2138,AMPL_WIDTH),
conv_std_logic_vector(2141,AMPL_WIDTH),
conv_std_logic_vector(2144,AMPL_WIDTH),
conv_std_logic_vector(2147,AMPL_WIDTH),
conv_std_logic_vector(2150,AMPL_WIDTH),
conv_std_logic_vector(2154,AMPL_WIDTH),
conv_std_logic_vector(2157,AMPL_WIDTH),
conv_std_logic_vector(2160,AMPL_WIDTH),
conv_std_logic_vector(2163,AMPL_WIDTH),
conv_std_logic_vector(2166,AMPL_WIDTH),
conv_std_logic_vector(2169,AMPL_WIDTH),
conv_std_logic_vector(2172,AMPL_WIDTH),
conv_std_logic_vector(2175,AMPL_WIDTH),
conv_std_logic_vector(2179,AMPL_WIDTH),
conv_std_logic_vector(2182,AMPL_WIDTH),
conv_std_logic_vector(2185,AMPL_WIDTH),
conv_std_logic_vector(2188,AMPL_WIDTH),
conv_std_logic_vector(2191,AMPL_WIDTH),
conv_std_logic_vector(2194,AMPL_WIDTH),
conv_std_logic_vector(2197,AMPL_WIDTH),
conv_std_logic_vector(2201,AMPL_WIDTH),
conv_std_logic_vector(2204,AMPL_WIDTH),
conv_std_logic_vector(2207,AMPL_WIDTH),
conv_std_logic_vector(2210,AMPL_WIDTH),
conv_std_logic_vector(2213,AMPL_WIDTH),
conv_std_logic_vector(2216,AMPL_WIDTH),
conv_std_logic_vector(2219,AMPL_WIDTH),
conv_std_logic_vector(2222,AMPL_WIDTH),
conv_std_logic_vector(2226,AMPL_WIDTH),
conv_std_logic_vector(2229,AMPL_WIDTH),
conv_std_logic_vector(2232,AMPL_WIDTH),
conv_std_logic_vector(2235,AMPL_WIDTH),
conv_std_logic_vector(2238,AMPL_WIDTH),
conv_std_logic_vector(2241,AMPL_WIDTH),
conv_std_logic_vector(2244,AMPL_WIDTH),
conv_std_logic_vector(2248,AMPL_WIDTH),
conv_std_logic_vector(2251,AMPL_WIDTH),
conv_std_logic_vector(2254,AMPL_WIDTH),
conv_std_logic_vector(2257,AMPL_WIDTH),
conv_std_logic_vector(2260,AMPL_WIDTH),
conv_std_logic_vector(2263,AMPL_WIDTH),
conv_std_logic_vector(2266,AMPL_WIDTH),
conv_std_logic_vector(2269,AMPL_WIDTH),
conv_std_logic_vector(2273,AMPL_WIDTH),
conv_std_logic_vector(2276,AMPL_WIDTH),
conv_std_logic_vector(2279,AMPL_WIDTH),
conv_std_logic_vector(2282,AMPL_WIDTH),
conv_std_logic_vector(2285,AMPL_WIDTH),
conv_std_logic_vector(2288,AMPL_WIDTH),
conv_std_logic_vector(2291,AMPL_WIDTH),
conv_std_logic_vector(2295,AMPL_WIDTH),
conv_std_logic_vector(2298,AMPL_WIDTH),
conv_std_logic_vector(2301,AMPL_WIDTH),
conv_std_logic_vector(2304,AMPL_WIDTH),
conv_std_logic_vector(2307,AMPL_WIDTH),
conv_std_logic_vector(2310,AMPL_WIDTH),
conv_std_logic_vector(2313,AMPL_WIDTH),
conv_std_logic_vector(2316,AMPL_WIDTH),
conv_std_logic_vector(2320,AMPL_WIDTH),
conv_std_logic_vector(2323,AMPL_WIDTH),
conv_std_logic_vector(2326,AMPL_WIDTH),
conv_std_logic_vector(2329,AMPL_WIDTH),
conv_std_logic_vector(2332,AMPL_WIDTH),
conv_std_logic_vector(2335,AMPL_WIDTH),
conv_std_logic_vector(2338,AMPL_WIDTH),
conv_std_logic_vector(2342,AMPL_WIDTH),
conv_std_logic_vector(2345,AMPL_WIDTH),
conv_std_logic_vector(2348,AMPL_WIDTH),
conv_std_logic_vector(2351,AMPL_WIDTH),
conv_std_logic_vector(2354,AMPL_WIDTH),
conv_std_logic_vector(2357,AMPL_WIDTH),
conv_std_logic_vector(2360,AMPL_WIDTH),
conv_std_logic_vector(2363,AMPL_WIDTH),
conv_std_logic_vector(2367,AMPL_WIDTH),
conv_std_logic_vector(2370,AMPL_WIDTH),
conv_std_logic_vector(2373,AMPL_WIDTH),
conv_std_logic_vector(2376,AMPL_WIDTH),
conv_std_logic_vector(2379,AMPL_WIDTH),
conv_std_logic_vector(2382,AMPL_WIDTH),
conv_std_logic_vector(2385,AMPL_WIDTH),
conv_std_logic_vector(2389,AMPL_WIDTH),
conv_std_logic_vector(2392,AMPL_WIDTH),
conv_std_logic_vector(2395,AMPL_WIDTH),
conv_std_logic_vector(2398,AMPL_WIDTH),
conv_std_logic_vector(2401,AMPL_WIDTH),
conv_std_logic_vector(2404,AMPL_WIDTH),
conv_std_logic_vector(2407,AMPL_WIDTH),
conv_std_logic_vector(2410,AMPL_WIDTH),
conv_std_logic_vector(2414,AMPL_WIDTH),
conv_std_logic_vector(2417,AMPL_WIDTH),
conv_std_logic_vector(2420,AMPL_WIDTH),
conv_std_logic_vector(2423,AMPL_WIDTH),
conv_std_logic_vector(2426,AMPL_WIDTH),
conv_std_logic_vector(2429,AMPL_WIDTH),
conv_std_logic_vector(2432,AMPL_WIDTH),
conv_std_logic_vector(2436,AMPL_WIDTH),
conv_std_logic_vector(2439,AMPL_WIDTH),
conv_std_logic_vector(2442,AMPL_WIDTH),
conv_std_logic_vector(2445,AMPL_WIDTH),
conv_std_logic_vector(2448,AMPL_WIDTH),
conv_std_logic_vector(2451,AMPL_WIDTH),
conv_std_logic_vector(2454,AMPL_WIDTH),
conv_std_logic_vector(2457,AMPL_WIDTH),
conv_std_logic_vector(2461,AMPL_WIDTH),
conv_std_logic_vector(2464,AMPL_WIDTH),
conv_std_logic_vector(2467,AMPL_WIDTH),
conv_std_logic_vector(2470,AMPL_WIDTH),
conv_std_logic_vector(2473,AMPL_WIDTH),
conv_std_logic_vector(2476,AMPL_WIDTH),
conv_std_logic_vector(2479,AMPL_WIDTH),
conv_std_logic_vector(2483,AMPL_WIDTH),
conv_std_logic_vector(2486,AMPL_WIDTH),
conv_std_logic_vector(2489,AMPL_WIDTH),
conv_std_logic_vector(2492,AMPL_WIDTH),
conv_std_logic_vector(2495,AMPL_WIDTH),
conv_std_logic_vector(2498,AMPL_WIDTH),
conv_std_logic_vector(2501,AMPL_WIDTH),
conv_std_logic_vector(2504,AMPL_WIDTH),
conv_std_logic_vector(2508,AMPL_WIDTH),
conv_std_logic_vector(2511,AMPL_WIDTH),
conv_std_logic_vector(2514,AMPL_WIDTH),
conv_std_logic_vector(2517,AMPL_WIDTH),
conv_std_logic_vector(2520,AMPL_WIDTH),
conv_std_logic_vector(2523,AMPL_WIDTH),
conv_std_logic_vector(2526,AMPL_WIDTH),
conv_std_logic_vector(2530,AMPL_WIDTH),
conv_std_logic_vector(2533,AMPL_WIDTH),
conv_std_logic_vector(2536,AMPL_WIDTH),
conv_std_logic_vector(2539,AMPL_WIDTH),
conv_std_logic_vector(2542,AMPL_WIDTH),
conv_std_logic_vector(2545,AMPL_WIDTH),
conv_std_logic_vector(2548,AMPL_WIDTH),
conv_std_logic_vector(2551,AMPL_WIDTH),
conv_std_logic_vector(2555,AMPL_WIDTH),
conv_std_logic_vector(2558,AMPL_WIDTH),
conv_std_logic_vector(2561,AMPL_WIDTH),
conv_std_logic_vector(2564,AMPL_WIDTH),
conv_std_logic_vector(2567,AMPL_WIDTH),
conv_std_logic_vector(2570,AMPL_WIDTH),
conv_std_logic_vector(2573,AMPL_WIDTH),
conv_std_logic_vector(2577,AMPL_WIDTH),
conv_std_logic_vector(2580,AMPL_WIDTH),
conv_std_logic_vector(2583,AMPL_WIDTH),
conv_std_logic_vector(2586,AMPL_WIDTH),
conv_std_logic_vector(2589,AMPL_WIDTH),
conv_std_logic_vector(2592,AMPL_WIDTH),
conv_std_logic_vector(2595,AMPL_WIDTH),
conv_std_logic_vector(2598,AMPL_WIDTH),
conv_std_logic_vector(2602,AMPL_WIDTH),
conv_std_logic_vector(2605,AMPL_WIDTH),
conv_std_logic_vector(2608,AMPL_WIDTH),
conv_std_logic_vector(2611,AMPL_WIDTH),
conv_std_logic_vector(2614,AMPL_WIDTH),
conv_std_logic_vector(2617,AMPL_WIDTH),
conv_std_logic_vector(2620,AMPL_WIDTH),
conv_std_logic_vector(2623,AMPL_WIDTH),
conv_std_logic_vector(2627,AMPL_WIDTH),
conv_std_logic_vector(2630,AMPL_WIDTH),
conv_std_logic_vector(2633,AMPL_WIDTH),
conv_std_logic_vector(2636,AMPL_WIDTH),
conv_std_logic_vector(2639,AMPL_WIDTH),
conv_std_logic_vector(2642,AMPL_WIDTH),
conv_std_logic_vector(2645,AMPL_WIDTH),
conv_std_logic_vector(2649,AMPL_WIDTH),
conv_std_logic_vector(2652,AMPL_WIDTH),
conv_std_logic_vector(2655,AMPL_WIDTH),
conv_std_logic_vector(2658,AMPL_WIDTH),
conv_std_logic_vector(2661,AMPL_WIDTH),
conv_std_logic_vector(2664,AMPL_WIDTH),
conv_std_logic_vector(2667,AMPL_WIDTH),
conv_std_logic_vector(2670,AMPL_WIDTH),
conv_std_logic_vector(2674,AMPL_WIDTH),
conv_std_logic_vector(2677,AMPL_WIDTH),
conv_std_logic_vector(2680,AMPL_WIDTH),
conv_std_logic_vector(2683,AMPL_WIDTH),
conv_std_logic_vector(2686,AMPL_WIDTH),
conv_std_logic_vector(2689,AMPL_WIDTH),
conv_std_logic_vector(2692,AMPL_WIDTH),
conv_std_logic_vector(2695,AMPL_WIDTH),
conv_std_logic_vector(2699,AMPL_WIDTH),
conv_std_logic_vector(2702,AMPL_WIDTH),
conv_std_logic_vector(2705,AMPL_WIDTH),
conv_std_logic_vector(2708,AMPL_WIDTH),
conv_std_logic_vector(2711,AMPL_WIDTH),
conv_std_logic_vector(2714,AMPL_WIDTH),
conv_std_logic_vector(2717,AMPL_WIDTH),
conv_std_logic_vector(2721,AMPL_WIDTH),
conv_std_logic_vector(2724,AMPL_WIDTH),
conv_std_logic_vector(2727,AMPL_WIDTH),
conv_std_logic_vector(2730,AMPL_WIDTH),
conv_std_logic_vector(2733,AMPL_WIDTH),
conv_std_logic_vector(2736,AMPL_WIDTH),
conv_std_logic_vector(2739,AMPL_WIDTH),
conv_std_logic_vector(2742,AMPL_WIDTH),
conv_std_logic_vector(2746,AMPL_WIDTH),
conv_std_logic_vector(2749,AMPL_WIDTH),
conv_std_logic_vector(2752,AMPL_WIDTH),
conv_std_logic_vector(2755,AMPL_WIDTH),
conv_std_logic_vector(2758,AMPL_WIDTH),
conv_std_logic_vector(2761,AMPL_WIDTH),
conv_std_logic_vector(2764,AMPL_WIDTH),
conv_std_logic_vector(2767,AMPL_WIDTH),
conv_std_logic_vector(2771,AMPL_WIDTH),
conv_std_logic_vector(2774,AMPL_WIDTH),
conv_std_logic_vector(2777,AMPL_WIDTH),
conv_std_logic_vector(2780,AMPL_WIDTH),
conv_std_logic_vector(2783,AMPL_WIDTH),
conv_std_logic_vector(2786,AMPL_WIDTH),
conv_std_logic_vector(2789,AMPL_WIDTH),
conv_std_logic_vector(2793,AMPL_WIDTH),
conv_std_logic_vector(2796,AMPL_WIDTH),
conv_std_logic_vector(2799,AMPL_WIDTH),
conv_std_logic_vector(2802,AMPL_WIDTH),
conv_std_logic_vector(2805,AMPL_WIDTH),
conv_std_logic_vector(2808,AMPL_WIDTH),
conv_std_logic_vector(2811,AMPL_WIDTH),
conv_std_logic_vector(2814,AMPL_WIDTH),
conv_std_logic_vector(2818,AMPL_WIDTH),
conv_std_logic_vector(2821,AMPL_WIDTH),
conv_std_logic_vector(2824,AMPL_WIDTH),
conv_std_logic_vector(2827,AMPL_WIDTH),
conv_std_logic_vector(2830,AMPL_WIDTH),
conv_std_logic_vector(2833,AMPL_WIDTH),
conv_std_logic_vector(2836,AMPL_WIDTH),
conv_std_logic_vector(2839,AMPL_WIDTH),
conv_std_logic_vector(2843,AMPL_WIDTH),
conv_std_logic_vector(2846,AMPL_WIDTH),
conv_std_logic_vector(2849,AMPL_WIDTH),
conv_std_logic_vector(2852,AMPL_WIDTH),
conv_std_logic_vector(2855,AMPL_WIDTH),
conv_std_logic_vector(2858,AMPL_WIDTH),
conv_std_logic_vector(2861,AMPL_WIDTH),
conv_std_logic_vector(2865,AMPL_WIDTH),
conv_std_logic_vector(2868,AMPL_WIDTH),
conv_std_logic_vector(2871,AMPL_WIDTH),
conv_std_logic_vector(2874,AMPL_WIDTH),
conv_std_logic_vector(2877,AMPL_WIDTH),
conv_std_logic_vector(2880,AMPL_WIDTH),
conv_std_logic_vector(2883,AMPL_WIDTH),
conv_std_logic_vector(2886,AMPL_WIDTH),
conv_std_logic_vector(2890,AMPL_WIDTH),
conv_std_logic_vector(2893,AMPL_WIDTH),
conv_std_logic_vector(2896,AMPL_WIDTH),
conv_std_logic_vector(2899,AMPL_WIDTH),
conv_std_logic_vector(2902,AMPL_WIDTH),
conv_std_logic_vector(2905,AMPL_WIDTH),
conv_std_logic_vector(2908,AMPL_WIDTH),
conv_std_logic_vector(2911,AMPL_WIDTH),
conv_std_logic_vector(2915,AMPL_WIDTH),
conv_std_logic_vector(2918,AMPL_WIDTH),
conv_std_logic_vector(2921,AMPL_WIDTH),
conv_std_logic_vector(2924,AMPL_WIDTH),
conv_std_logic_vector(2927,AMPL_WIDTH),
conv_std_logic_vector(2930,AMPL_WIDTH),
conv_std_logic_vector(2933,AMPL_WIDTH),
conv_std_logic_vector(2936,AMPL_WIDTH),
conv_std_logic_vector(2940,AMPL_WIDTH),
conv_std_logic_vector(2943,AMPL_WIDTH),
conv_std_logic_vector(2946,AMPL_WIDTH),
conv_std_logic_vector(2949,AMPL_WIDTH),
conv_std_logic_vector(2952,AMPL_WIDTH),
conv_std_logic_vector(2955,AMPL_WIDTH),
conv_std_logic_vector(2958,AMPL_WIDTH),
conv_std_logic_vector(2962,AMPL_WIDTH),
conv_std_logic_vector(2965,AMPL_WIDTH),
conv_std_logic_vector(2968,AMPL_WIDTH),
conv_std_logic_vector(2971,AMPL_WIDTH),
conv_std_logic_vector(2974,AMPL_WIDTH),
conv_std_logic_vector(2977,AMPL_WIDTH),
conv_std_logic_vector(2980,AMPL_WIDTH),
conv_std_logic_vector(2983,AMPL_WIDTH),
conv_std_logic_vector(2987,AMPL_WIDTH),
conv_std_logic_vector(2990,AMPL_WIDTH),
conv_std_logic_vector(2993,AMPL_WIDTH),
conv_std_logic_vector(2996,AMPL_WIDTH),
conv_std_logic_vector(2999,AMPL_WIDTH),
conv_std_logic_vector(3002,AMPL_WIDTH),
conv_std_logic_vector(3005,AMPL_WIDTH),
conv_std_logic_vector(3008,AMPL_WIDTH),
conv_std_logic_vector(3012,AMPL_WIDTH),
conv_std_logic_vector(3015,AMPL_WIDTH),
conv_std_logic_vector(3018,AMPL_WIDTH),
conv_std_logic_vector(3021,AMPL_WIDTH),
conv_std_logic_vector(3024,AMPL_WIDTH),
conv_std_logic_vector(3027,AMPL_WIDTH),
conv_std_logic_vector(3030,AMPL_WIDTH),
conv_std_logic_vector(3033,AMPL_WIDTH),
conv_std_logic_vector(3037,AMPL_WIDTH),
conv_std_logic_vector(3040,AMPL_WIDTH),
conv_std_logic_vector(3043,AMPL_WIDTH),
conv_std_logic_vector(3046,AMPL_WIDTH),
conv_std_logic_vector(3049,AMPL_WIDTH),
conv_std_logic_vector(3052,AMPL_WIDTH),
conv_std_logic_vector(3055,AMPL_WIDTH),
conv_std_logic_vector(3059,AMPL_WIDTH),
conv_std_logic_vector(3062,AMPL_WIDTH),
conv_std_logic_vector(3065,AMPL_WIDTH),
conv_std_logic_vector(3068,AMPL_WIDTH),
conv_std_logic_vector(3071,AMPL_WIDTH),
conv_std_logic_vector(3074,AMPL_WIDTH),
conv_std_logic_vector(3077,AMPL_WIDTH),
conv_std_logic_vector(3080,AMPL_WIDTH),
conv_std_logic_vector(3084,AMPL_WIDTH),
conv_std_logic_vector(3087,AMPL_WIDTH),
conv_std_logic_vector(3090,AMPL_WIDTH),
conv_std_logic_vector(3093,AMPL_WIDTH),
conv_std_logic_vector(3096,AMPL_WIDTH),
conv_std_logic_vector(3099,AMPL_WIDTH),
conv_std_logic_vector(3102,AMPL_WIDTH),
conv_std_logic_vector(3105,AMPL_WIDTH),
conv_std_logic_vector(3109,AMPL_WIDTH),
conv_std_logic_vector(3112,AMPL_WIDTH),
conv_std_logic_vector(3115,AMPL_WIDTH),
conv_std_logic_vector(3118,AMPL_WIDTH),
conv_std_logic_vector(3121,AMPL_WIDTH),
conv_std_logic_vector(3124,AMPL_WIDTH),
conv_std_logic_vector(3127,AMPL_WIDTH),
conv_std_logic_vector(3130,AMPL_WIDTH),
conv_std_logic_vector(3134,AMPL_WIDTH),
conv_std_logic_vector(3137,AMPL_WIDTH),
conv_std_logic_vector(3140,AMPL_WIDTH),
conv_std_logic_vector(3143,AMPL_WIDTH),
conv_std_logic_vector(3146,AMPL_WIDTH),
conv_std_logic_vector(3149,AMPL_WIDTH),
conv_std_logic_vector(3152,AMPL_WIDTH),
conv_std_logic_vector(3155,AMPL_WIDTH),
conv_std_logic_vector(3159,AMPL_WIDTH),
conv_std_logic_vector(3162,AMPL_WIDTH),
conv_std_logic_vector(3165,AMPL_WIDTH),
conv_std_logic_vector(3168,AMPL_WIDTH),
conv_std_logic_vector(3171,AMPL_WIDTH),
conv_std_logic_vector(3174,AMPL_WIDTH),
conv_std_logic_vector(3177,AMPL_WIDTH),
conv_std_logic_vector(3180,AMPL_WIDTH),
conv_std_logic_vector(3184,AMPL_WIDTH),
conv_std_logic_vector(3187,AMPL_WIDTH),
conv_std_logic_vector(3190,AMPL_WIDTH),
conv_std_logic_vector(3193,AMPL_WIDTH),
conv_std_logic_vector(3196,AMPL_WIDTH),
conv_std_logic_vector(3199,AMPL_WIDTH),
conv_std_logic_vector(3202,AMPL_WIDTH),
conv_std_logic_vector(3205,AMPL_WIDTH),
conv_std_logic_vector(3209,AMPL_WIDTH),
conv_std_logic_vector(3212,AMPL_WIDTH),
conv_std_logic_vector(3215,AMPL_WIDTH),
conv_std_logic_vector(3218,AMPL_WIDTH),
conv_std_logic_vector(3221,AMPL_WIDTH),
conv_std_logic_vector(3224,AMPL_WIDTH),
conv_std_logic_vector(3227,AMPL_WIDTH),
conv_std_logic_vector(3230,AMPL_WIDTH),
conv_std_logic_vector(3234,AMPL_WIDTH),
conv_std_logic_vector(3237,AMPL_WIDTH),
conv_std_logic_vector(3240,AMPL_WIDTH),
conv_std_logic_vector(3243,AMPL_WIDTH),
conv_std_logic_vector(3246,AMPL_WIDTH),
conv_std_logic_vector(3249,AMPL_WIDTH),
conv_std_logic_vector(3252,AMPL_WIDTH),
conv_std_logic_vector(3255,AMPL_WIDTH),
conv_std_logic_vector(3259,AMPL_WIDTH),
conv_std_logic_vector(3262,AMPL_WIDTH),
conv_std_logic_vector(3265,AMPL_WIDTH),
conv_std_logic_vector(3268,AMPL_WIDTH),
conv_std_logic_vector(3271,AMPL_WIDTH),
conv_std_logic_vector(3274,AMPL_WIDTH),
conv_std_logic_vector(3277,AMPL_WIDTH),
conv_std_logic_vector(3281,AMPL_WIDTH),
conv_std_logic_vector(3284,AMPL_WIDTH),
conv_std_logic_vector(3287,AMPL_WIDTH),
conv_std_logic_vector(3290,AMPL_WIDTH),
conv_std_logic_vector(3293,AMPL_WIDTH),
conv_std_logic_vector(3296,AMPL_WIDTH),
conv_std_logic_vector(3299,AMPL_WIDTH),
conv_std_logic_vector(3302,AMPL_WIDTH),
conv_std_logic_vector(3306,AMPL_WIDTH),
conv_std_logic_vector(3309,AMPL_WIDTH),
conv_std_logic_vector(3312,AMPL_WIDTH),
conv_std_logic_vector(3315,AMPL_WIDTH),
conv_std_logic_vector(3318,AMPL_WIDTH),
conv_std_logic_vector(3321,AMPL_WIDTH),
conv_std_logic_vector(3324,AMPL_WIDTH),
conv_std_logic_vector(3327,AMPL_WIDTH),
conv_std_logic_vector(3331,AMPL_WIDTH),
conv_std_logic_vector(3334,AMPL_WIDTH),
conv_std_logic_vector(3337,AMPL_WIDTH),
conv_std_logic_vector(3340,AMPL_WIDTH),
conv_std_logic_vector(3343,AMPL_WIDTH),
conv_std_logic_vector(3346,AMPL_WIDTH),
conv_std_logic_vector(3349,AMPL_WIDTH),
conv_std_logic_vector(3352,AMPL_WIDTH),
conv_std_logic_vector(3356,AMPL_WIDTH),
conv_std_logic_vector(3359,AMPL_WIDTH),
conv_std_logic_vector(3362,AMPL_WIDTH),
conv_std_logic_vector(3365,AMPL_WIDTH),
conv_std_logic_vector(3368,AMPL_WIDTH),
conv_std_logic_vector(3371,AMPL_WIDTH),
conv_std_logic_vector(3374,AMPL_WIDTH),
conv_std_logic_vector(3377,AMPL_WIDTH),
conv_std_logic_vector(3381,AMPL_WIDTH),
conv_std_logic_vector(3384,AMPL_WIDTH),
conv_std_logic_vector(3387,AMPL_WIDTH),
conv_std_logic_vector(3390,AMPL_WIDTH),
conv_std_logic_vector(3393,AMPL_WIDTH),
conv_std_logic_vector(3396,AMPL_WIDTH),
conv_std_logic_vector(3399,AMPL_WIDTH),
conv_std_logic_vector(3402,AMPL_WIDTH),
conv_std_logic_vector(3406,AMPL_WIDTH),
conv_std_logic_vector(3409,AMPL_WIDTH),
conv_std_logic_vector(3412,AMPL_WIDTH),
conv_std_logic_vector(3415,AMPL_WIDTH),
conv_std_logic_vector(3418,AMPL_WIDTH),
conv_std_logic_vector(3421,AMPL_WIDTH),
conv_std_logic_vector(3424,AMPL_WIDTH),
conv_std_logic_vector(3427,AMPL_WIDTH),
conv_std_logic_vector(3430,AMPL_WIDTH),
conv_std_logic_vector(3434,AMPL_WIDTH),
conv_std_logic_vector(3437,AMPL_WIDTH),
conv_std_logic_vector(3440,AMPL_WIDTH),
conv_std_logic_vector(3443,AMPL_WIDTH),
conv_std_logic_vector(3446,AMPL_WIDTH),
conv_std_logic_vector(3449,AMPL_WIDTH),
conv_std_logic_vector(3452,AMPL_WIDTH),
conv_std_logic_vector(3455,AMPL_WIDTH),
conv_std_logic_vector(3459,AMPL_WIDTH),
conv_std_logic_vector(3462,AMPL_WIDTH),
conv_std_logic_vector(3465,AMPL_WIDTH),
conv_std_logic_vector(3468,AMPL_WIDTH),
conv_std_logic_vector(3471,AMPL_WIDTH),
conv_std_logic_vector(3474,AMPL_WIDTH),
conv_std_logic_vector(3477,AMPL_WIDTH),
conv_std_logic_vector(3480,AMPL_WIDTH),
conv_std_logic_vector(3484,AMPL_WIDTH),
conv_std_logic_vector(3487,AMPL_WIDTH),
conv_std_logic_vector(3490,AMPL_WIDTH),
conv_std_logic_vector(3493,AMPL_WIDTH),
conv_std_logic_vector(3496,AMPL_WIDTH),
conv_std_logic_vector(3499,AMPL_WIDTH),
conv_std_logic_vector(3502,AMPL_WIDTH),
conv_std_logic_vector(3505,AMPL_WIDTH),
conv_std_logic_vector(3509,AMPL_WIDTH),
conv_std_logic_vector(3512,AMPL_WIDTH),
conv_std_logic_vector(3515,AMPL_WIDTH),
conv_std_logic_vector(3518,AMPL_WIDTH),
conv_std_logic_vector(3521,AMPL_WIDTH),
conv_std_logic_vector(3524,AMPL_WIDTH),
conv_std_logic_vector(3527,AMPL_WIDTH),
conv_std_logic_vector(3530,AMPL_WIDTH),
conv_std_logic_vector(3534,AMPL_WIDTH),
conv_std_logic_vector(3537,AMPL_WIDTH),
conv_std_logic_vector(3540,AMPL_WIDTH),
conv_std_logic_vector(3543,AMPL_WIDTH),
conv_std_logic_vector(3546,AMPL_WIDTH),
conv_std_logic_vector(3549,AMPL_WIDTH),
conv_std_logic_vector(3552,AMPL_WIDTH),
conv_std_logic_vector(3555,AMPL_WIDTH),
conv_std_logic_vector(3559,AMPL_WIDTH),
conv_std_logic_vector(3562,AMPL_WIDTH),
conv_std_logic_vector(3565,AMPL_WIDTH),
conv_std_logic_vector(3568,AMPL_WIDTH),
conv_std_logic_vector(3571,AMPL_WIDTH),
conv_std_logic_vector(3574,AMPL_WIDTH),
conv_std_logic_vector(3577,AMPL_WIDTH),
conv_std_logic_vector(3580,AMPL_WIDTH),
conv_std_logic_vector(3584,AMPL_WIDTH),
conv_std_logic_vector(3587,AMPL_WIDTH),
conv_std_logic_vector(3590,AMPL_WIDTH),
conv_std_logic_vector(3593,AMPL_WIDTH),
conv_std_logic_vector(3596,AMPL_WIDTH),
conv_std_logic_vector(3599,AMPL_WIDTH),
conv_std_logic_vector(3602,AMPL_WIDTH),
conv_std_logic_vector(3605,AMPL_WIDTH),
conv_std_logic_vector(3609,AMPL_WIDTH),
conv_std_logic_vector(3612,AMPL_WIDTH),
conv_std_logic_vector(3615,AMPL_WIDTH),
conv_std_logic_vector(3618,AMPL_WIDTH),
conv_std_logic_vector(3621,AMPL_WIDTH),
conv_std_logic_vector(3624,AMPL_WIDTH),
conv_std_logic_vector(3627,AMPL_WIDTH),
conv_std_logic_vector(3630,AMPL_WIDTH),
conv_std_logic_vector(3634,AMPL_WIDTH),
conv_std_logic_vector(3637,AMPL_WIDTH),
conv_std_logic_vector(3640,AMPL_WIDTH),
conv_std_logic_vector(3643,AMPL_WIDTH),
conv_std_logic_vector(3646,AMPL_WIDTH),
conv_std_logic_vector(3649,AMPL_WIDTH),
conv_std_logic_vector(3652,AMPL_WIDTH),
conv_std_logic_vector(3655,AMPL_WIDTH),
conv_std_logic_vector(3658,AMPL_WIDTH),
conv_std_logic_vector(3662,AMPL_WIDTH),
conv_std_logic_vector(3665,AMPL_WIDTH),
conv_std_logic_vector(3668,AMPL_WIDTH),
conv_std_logic_vector(3671,AMPL_WIDTH),
conv_std_logic_vector(3674,AMPL_WIDTH),
conv_std_logic_vector(3677,AMPL_WIDTH),
conv_std_logic_vector(3680,AMPL_WIDTH),
conv_std_logic_vector(3683,AMPL_WIDTH),
conv_std_logic_vector(3687,AMPL_WIDTH),
conv_std_logic_vector(3690,AMPL_WIDTH),
conv_std_logic_vector(3693,AMPL_WIDTH),
conv_std_logic_vector(3696,AMPL_WIDTH),
conv_std_logic_vector(3699,AMPL_WIDTH),
conv_std_logic_vector(3702,AMPL_WIDTH),
conv_std_logic_vector(3705,AMPL_WIDTH),
conv_std_logic_vector(3708,AMPL_WIDTH),
conv_std_logic_vector(3712,AMPL_WIDTH),
conv_std_logic_vector(3715,AMPL_WIDTH),
conv_std_logic_vector(3718,AMPL_WIDTH),
conv_std_logic_vector(3721,AMPL_WIDTH),
conv_std_logic_vector(3724,AMPL_WIDTH),
conv_std_logic_vector(3727,AMPL_WIDTH),
conv_std_logic_vector(3730,AMPL_WIDTH),
conv_std_logic_vector(3733,AMPL_WIDTH),
conv_std_logic_vector(3737,AMPL_WIDTH),
conv_std_logic_vector(3740,AMPL_WIDTH),
conv_std_logic_vector(3743,AMPL_WIDTH),
conv_std_logic_vector(3746,AMPL_WIDTH),
conv_std_logic_vector(3749,AMPL_WIDTH),
conv_std_logic_vector(3752,AMPL_WIDTH),
conv_std_logic_vector(3755,AMPL_WIDTH),
conv_std_logic_vector(3758,AMPL_WIDTH),
conv_std_logic_vector(3761,AMPL_WIDTH),
conv_std_logic_vector(3765,AMPL_WIDTH),
conv_std_logic_vector(3768,AMPL_WIDTH),
conv_std_logic_vector(3771,AMPL_WIDTH),
conv_std_logic_vector(3774,AMPL_WIDTH),
conv_std_logic_vector(3777,AMPL_WIDTH),
conv_std_logic_vector(3780,AMPL_WIDTH),
conv_std_logic_vector(3783,AMPL_WIDTH),
conv_std_logic_vector(3786,AMPL_WIDTH),
conv_std_logic_vector(3790,AMPL_WIDTH),
conv_std_logic_vector(3793,AMPL_WIDTH),
conv_std_logic_vector(3796,AMPL_WIDTH),
conv_std_logic_vector(3799,AMPL_WIDTH),
conv_std_logic_vector(3802,AMPL_WIDTH),
conv_std_logic_vector(3805,AMPL_WIDTH),
conv_std_logic_vector(3808,AMPL_WIDTH),
conv_std_logic_vector(3811,AMPL_WIDTH),
conv_std_logic_vector(3815,AMPL_WIDTH),
conv_std_logic_vector(3818,AMPL_WIDTH),
conv_std_logic_vector(3821,AMPL_WIDTH),
conv_std_logic_vector(3824,AMPL_WIDTH),
conv_std_logic_vector(3827,AMPL_WIDTH),
conv_std_logic_vector(3830,AMPL_WIDTH),
conv_std_logic_vector(3833,AMPL_WIDTH),
conv_std_logic_vector(3836,AMPL_WIDTH),
conv_std_logic_vector(3839,AMPL_WIDTH),
conv_std_logic_vector(3843,AMPL_WIDTH),
conv_std_logic_vector(3846,AMPL_WIDTH),
conv_std_logic_vector(3849,AMPL_WIDTH),
conv_std_logic_vector(3852,AMPL_WIDTH),
conv_std_logic_vector(3855,AMPL_WIDTH),
conv_std_logic_vector(3858,AMPL_WIDTH),
conv_std_logic_vector(3861,AMPL_WIDTH),
conv_std_logic_vector(3864,AMPL_WIDTH),
conv_std_logic_vector(3868,AMPL_WIDTH),
conv_std_logic_vector(3871,AMPL_WIDTH),
conv_std_logic_vector(3874,AMPL_WIDTH),
conv_std_logic_vector(3877,AMPL_WIDTH),
conv_std_logic_vector(3880,AMPL_WIDTH),
conv_std_logic_vector(3883,AMPL_WIDTH),
conv_std_logic_vector(3886,AMPL_WIDTH),
conv_std_logic_vector(3889,AMPL_WIDTH),
conv_std_logic_vector(3893,AMPL_WIDTH),
conv_std_logic_vector(3896,AMPL_WIDTH),
conv_std_logic_vector(3899,AMPL_WIDTH),
conv_std_logic_vector(3902,AMPL_WIDTH),
conv_std_logic_vector(3905,AMPL_WIDTH),
conv_std_logic_vector(3908,AMPL_WIDTH),
conv_std_logic_vector(3911,AMPL_WIDTH),
conv_std_logic_vector(3914,AMPL_WIDTH),
conv_std_logic_vector(3917,AMPL_WIDTH),
conv_std_logic_vector(3921,AMPL_WIDTH),
conv_std_logic_vector(3924,AMPL_WIDTH),
conv_std_logic_vector(3927,AMPL_WIDTH),
conv_std_logic_vector(3930,AMPL_WIDTH),
conv_std_logic_vector(3933,AMPL_WIDTH),
conv_std_logic_vector(3936,AMPL_WIDTH),
conv_std_logic_vector(3939,AMPL_WIDTH),
conv_std_logic_vector(3942,AMPL_WIDTH),
conv_std_logic_vector(3946,AMPL_WIDTH),
conv_std_logic_vector(3949,AMPL_WIDTH),
conv_std_logic_vector(3952,AMPL_WIDTH),
conv_std_logic_vector(3955,AMPL_WIDTH),
conv_std_logic_vector(3958,AMPL_WIDTH),
conv_std_logic_vector(3961,AMPL_WIDTH),
conv_std_logic_vector(3964,AMPL_WIDTH),
conv_std_logic_vector(3967,AMPL_WIDTH),
conv_std_logic_vector(3970,AMPL_WIDTH),
conv_std_logic_vector(3974,AMPL_WIDTH),
conv_std_logic_vector(3977,AMPL_WIDTH),
conv_std_logic_vector(3980,AMPL_WIDTH),
conv_std_logic_vector(3983,AMPL_WIDTH),
conv_std_logic_vector(3986,AMPL_WIDTH),
conv_std_logic_vector(3989,AMPL_WIDTH),
conv_std_logic_vector(3992,AMPL_WIDTH),
conv_std_logic_vector(3995,AMPL_WIDTH),
conv_std_logic_vector(3999,AMPL_WIDTH),
conv_std_logic_vector(4002,AMPL_WIDTH),
conv_std_logic_vector(4005,AMPL_WIDTH),
conv_std_logic_vector(4008,AMPL_WIDTH),
conv_std_logic_vector(4011,AMPL_WIDTH),
conv_std_logic_vector(4014,AMPL_WIDTH),
conv_std_logic_vector(4017,AMPL_WIDTH),
conv_std_logic_vector(4020,AMPL_WIDTH),
conv_std_logic_vector(4024,AMPL_WIDTH),
conv_std_logic_vector(4027,AMPL_WIDTH),
conv_std_logic_vector(4030,AMPL_WIDTH),
conv_std_logic_vector(4033,AMPL_WIDTH),
conv_std_logic_vector(4036,AMPL_WIDTH),
conv_std_logic_vector(4039,AMPL_WIDTH),
conv_std_logic_vector(4042,AMPL_WIDTH),
conv_std_logic_vector(4045,AMPL_WIDTH),
conv_std_logic_vector(4048,AMPL_WIDTH),
conv_std_logic_vector(4052,AMPL_WIDTH),
conv_std_logic_vector(4055,AMPL_WIDTH),
conv_std_logic_vector(4058,AMPL_WIDTH),
conv_std_logic_vector(4061,AMPL_WIDTH),
conv_std_logic_vector(4064,AMPL_WIDTH),
conv_std_logic_vector(4067,AMPL_WIDTH),
conv_std_logic_vector(4070,AMPL_WIDTH),
conv_std_logic_vector(4073,AMPL_WIDTH),
conv_std_logic_vector(4076,AMPL_WIDTH),
conv_std_logic_vector(4080,AMPL_WIDTH),
conv_std_logic_vector(4083,AMPL_WIDTH),
conv_std_logic_vector(4086,AMPL_WIDTH),
conv_std_logic_vector(4089,AMPL_WIDTH),
conv_std_logic_vector(4092,AMPL_WIDTH),
conv_std_logic_vector(4095,AMPL_WIDTH),
conv_std_logic_vector(4098,AMPL_WIDTH),
conv_std_logic_vector(4101,AMPL_WIDTH),
conv_std_logic_vector(4105,AMPL_WIDTH),
conv_std_logic_vector(4108,AMPL_WIDTH),
conv_std_logic_vector(4111,AMPL_WIDTH),
conv_std_logic_vector(4114,AMPL_WIDTH),
conv_std_logic_vector(4117,AMPL_WIDTH),
conv_std_logic_vector(4120,AMPL_WIDTH),
conv_std_logic_vector(4123,AMPL_WIDTH),
conv_std_logic_vector(4126,AMPL_WIDTH),
conv_std_logic_vector(4129,AMPL_WIDTH),
conv_std_logic_vector(4133,AMPL_WIDTH),
conv_std_logic_vector(4136,AMPL_WIDTH),
conv_std_logic_vector(4139,AMPL_WIDTH),
conv_std_logic_vector(4142,AMPL_WIDTH),
conv_std_logic_vector(4145,AMPL_WIDTH),
conv_std_logic_vector(4148,AMPL_WIDTH),
conv_std_logic_vector(4151,AMPL_WIDTH),
conv_std_logic_vector(4154,AMPL_WIDTH),
conv_std_logic_vector(4158,AMPL_WIDTH),
conv_std_logic_vector(4161,AMPL_WIDTH),
conv_std_logic_vector(4164,AMPL_WIDTH),
conv_std_logic_vector(4167,AMPL_WIDTH),
conv_std_logic_vector(4170,AMPL_WIDTH),
conv_std_logic_vector(4173,AMPL_WIDTH),
conv_std_logic_vector(4176,AMPL_WIDTH),
conv_std_logic_vector(4179,AMPL_WIDTH),
conv_std_logic_vector(4182,AMPL_WIDTH),
conv_std_logic_vector(4186,AMPL_WIDTH),
conv_std_logic_vector(4189,AMPL_WIDTH),
conv_std_logic_vector(4192,AMPL_WIDTH),
conv_std_logic_vector(4195,AMPL_WIDTH),
conv_std_logic_vector(4198,AMPL_WIDTH),
conv_std_logic_vector(4201,AMPL_WIDTH),
conv_std_logic_vector(4204,AMPL_WIDTH),
conv_std_logic_vector(4207,AMPL_WIDTH),
conv_std_logic_vector(4210,AMPL_WIDTH),
conv_std_logic_vector(4214,AMPL_WIDTH),
conv_std_logic_vector(4217,AMPL_WIDTH),
conv_std_logic_vector(4220,AMPL_WIDTH),
conv_std_logic_vector(4223,AMPL_WIDTH),
conv_std_logic_vector(4226,AMPL_WIDTH),
conv_std_logic_vector(4229,AMPL_WIDTH),
conv_std_logic_vector(4232,AMPL_WIDTH),
conv_std_logic_vector(4235,AMPL_WIDTH),
conv_std_logic_vector(4239,AMPL_WIDTH),
conv_std_logic_vector(4242,AMPL_WIDTH),
conv_std_logic_vector(4245,AMPL_WIDTH),
conv_std_logic_vector(4248,AMPL_WIDTH),
conv_std_logic_vector(4251,AMPL_WIDTH),
conv_std_logic_vector(4254,AMPL_WIDTH),
conv_std_logic_vector(4257,AMPL_WIDTH),
conv_std_logic_vector(4260,AMPL_WIDTH),
conv_std_logic_vector(4263,AMPL_WIDTH),
conv_std_logic_vector(4267,AMPL_WIDTH),
conv_std_logic_vector(4270,AMPL_WIDTH),
conv_std_logic_vector(4273,AMPL_WIDTH),
conv_std_logic_vector(4276,AMPL_WIDTH),
conv_std_logic_vector(4279,AMPL_WIDTH),
conv_std_logic_vector(4282,AMPL_WIDTH),
conv_std_logic_vector(4285,AMPL_WIDTH),
conv_std_logic_vector(4288,AMPL_WIDTH),
conv_std_logic_vector(4291,AMPL_WIDTH),
conv_std_logic_vector(4295,AMPL_WIDTH),
conv_std_logic_vector(4298,AMPL_WIDTH),
conv_std_logic_vector(4301,AMPL_WIDTH),
conv_std_logic_vector(4304,AMPL_WIDTH),
conv_std_logic_vector(4307,AMPL_WIDTH),
conv_std_logic_vector(4310,AMPL_WIDTH),
conv_std_logic_vector(4313,AMPL_WIDTH),
conv_std_logic_vector(4316,AMPL_WIDTH),
conv_std_logic_vector(4320,AMPL_WIDTH),
conv_std_logic_vector(4323,AMPL_WIDTH),
conv_std_logic_vector(4326,AMPL_WIDTH),
conv_std_logic_vector(4329,AMPL_WIDTH),
conv_std_logic_vector(4332,AMPL_WIDTH),
conv_std_logic_vector(4335,AMPL_WIDTH),
conv_std_logic_vector(4338,AMPL_WIDTH),
conv_std_logic_vector(4341,AMPL_WIDTH),
conv_std_logic_vector(4344,AMPL_WIDTH),
conv_std_logic_vector(4348,AMPL_WIDTH),
conv_std_logic_vector(4351,AMPL_WIDTH),
conv_std_logic_vector(4354,AMPL_WIDTH),
conv_std_logic_vector(4357,AMPL_WIDTH),
conv_std_logic_vector(4360,AMPL_WIDTH),
conv_std_logic_vector(4363,AMPL_WIDTH),
conv_std_logic_vector(4366,AMPL_WIDTH),
conv_std_logic_vector(4369,AMPL_WIDTH),
conv_std_logic_vector(4372,AMPL_WIDTH),
conv_std_logic_vector(4376,AMPL_WIDTH),
conv_std_logic_vector(4379,AMPL_WIDTH),
conv_std_logic_vector(4382,AMPL_WIDTH),
conv_std_logic_vector(4385,AMPL_WIDTH),
conv_std_logic_vector(4388,AMPL_WIDTH),
conv_std_logic_vector(4391,AMPL_WIDTH),
conv_std_logic_vector(4394,AMPL_WIDTH),
conv_std_logic_vector(4397,AMPL_WIDTH),
conv_std_logic_vector(4400,AMPL_WIDTH),
conv_std_logic_vector(4404,AMPL_WIDTH),
conv_std_logic_vector(4407,AMPL_WIDTH),
conv_std_logic_vector(4410,AMPL_WIDTH),
conv_std_logic_vector(4413,AMPL_WIDTH),
conv_std_logic_vector(4416,AMPL_WIDTH),
conv_std_logic_vector(4419,AMPL_WIDTH),
conv_std_logic_vector(4422,AMPL_WIDTH),
conv_std_logic_vector(4425,AMPL_WIDTH),
conv_std_logic_vector(4428,AMPL_WIDTH),
conv_std_logic_vector(4432,AMPL_WIDTH),
conv_std_logic_vector(4435,AMPL_WIDTH),
conv_std_logic_vector(4438,AMPL_WIDTH),
conv_std_logic_vector(4441,AMPL_WIDTH),
conv_std_logic_vector(4444,AMPL_WIDTH),
conv_std_logic_vector(4447,AMPL_WIDTH),
conv_std_logic_vector(4450,AMPL_WIDTH),
conv_std_logic_vector(4453,AMPL_WIDTH),
conv_std_logic_vector(4456,AMPL_WIDTH),
conv_std_logic_vector(4460,AMPL_WIDTH),
conv_std_logic_vector(4463,AMPL_WIDTH),
conv_std_logic_vector(4466,AMPL_WIDTH),
conv_std_logic_vector(4469,AMPL_WIDTH),
conv_std_logic_vector(4472,AMPL_WIDTH),
conv_std_logic_vector(4475,AMPL_WIDTH),
conv_std_logic_vector(4478,AMPL_WIDTH),
conv_std_logic_vector(4481,AMPL_WIDTH),
conv_std_logic_vector(4485,AMPL_WIDTH),
conv_std_logic_vector(4488,AMPL_WIDTH),
conv_std_logic_vector(4491,AMPL_WIDTH),
conv_std_logic_vector(4494,AMPL_WIDTH),
conv_std_logic_vector(4497,AMPL_WIDTH),
conv_std_logic_vector(4500,AMPL_WIDTH),
conv_std_logic_vector(4503,AMPL_WIDTH),
conv_std_logic_vector(4506,AMPL_WIDTH),
conv_std_logic_vector(4509,AMPL_WIDTH),
conv_std_logic_vector(4513,AMPL_WIDTH),
conv_std_logic_vector(4516,AMPL_WIDTH),
conv_std_logic_vector(4519,AMPL_WIDTH),
conv_std_logic_vector(4522,AMPL_WIDTH),
conv_std_logic_vector(4525,AMPL_WIDTH),
conv_std_logic_vector(4528,AMPL_WIDTH),
conv_std_logic_vector(4531,AMPL_WIDTH),
conv_std_logic_vector(4534,AMPL_WIDTH),
conv_std_logic_vector(4537,AMPL_WIDTH),
conv_std_logic_vector(4541,AMPL_WIDTH),
conv_std_logic_vector(4544,AMPL_WIDTH),
conv_std_logic_vector(4547,AMPL_WIDTH),
conv_std_logic_vector(4550,AMPL_WIDTH),
conv_std_logic_vector(4553,AMPL_WIDTH),
conv_std_logic_vector(4556,AMPL_WIDTH),
conv_std_logic_vector(4559,AMPL_WIDTH),
conv_std_logic_vector(4562,AMPL_WIDTH),
conv_std_logic_vector(4565,AMPL_WIDTH),
conv_std_logic_vector(4569,AMPL_WIDTH),
conv_std_logic_vector(4572,AMPL_WIDTH),
conv_std_logic_vector(4575,AMPL_WIDTH),
conv_std_logic_vector(4578,AMPL_WIDTH),
conv_std_logic_vector(4581,AMPL_WIDTH),
conv_std_logic_vector(4584,AMPL_WIDTH),
conv_std_logic_vector(4587,AMPL_WIDTH),
conv_std_logic_vector(4590,AMPL_WIDTH),
conv_std_logic_vector(4593,AMPL_WIDTH),
conv_std_logic_vector(4597,AMPL_WIDTH),
conv_std_logic_vector(4600,AMPL_WIDTH),
conv_std_logic_vector(4603,AMPL_WIDTH),
conv_std_logic_vector(4606,AMPL_WIDTH),
conv_std_logic_vector(4609,AMPL_WIDTH),
conv_std_logic_vector(4612,AMPL_WIDTH),
conv_std_logic_vector(4615,AMPL_WIDTH),
conv_std_logic_vector(4618,AMPL_WIDTH),
conv_std_logic_vector(4621,AMPL_WIDTH),
conv_std_logic_vector(4624,AMPL_WIDTH),
conv_std_logic_vector(4628,AMPL_WIDTH),
conv_std_logic_vector(4631,AMPL_WIDTH),
conv_std_logic_vector(4634,AMPL_WIDTH),
conv_std_logic_vector(4637,AMPL_WIDTH),
conv_std_logic_vector(4640,AMPL_WIDTH),
conv_std_logic_vector(4643,AMPL_WIDTH),
conv_std_logic_vector(4646,AMPL_WIDTH),
conv_std_logic_vector(4649,AMPL_WIDTH),
conv_std_logic_vector(4652,AMPL_WIDTH),
conv_std_logic_vector(4656,AMPL_WIDTH),
conv_std_logic_vector(4659,AMPL_WIDTH),
conv_std_logic_vector(4662,AMPL_WIDTH),
conv_std_logic_vector(4665,AMPL_WIDTH),
conv_std_logic_vector(4668,AMPL_WIDTH),
conv_std_logic_vector(4671,AMPL_WIDTH),
conv_std_logic_vector(4674,AMPL_WIDTH),
conv_std_logic_vector(4677,AMPL_WIDTH),
conv_std_logic_vector(4680,AMPL_WIDTH),
conv_std_logic_vector(4684,AMPL_WIDTH),
conv_std_logic_vector(4687,AMPL_WIDTH),
conv_std_logic_vector(4690,AMPL_WIDTH),
conv_std_logic_vector(4693,AMPL_WIDTH),
conv_std_logic_vector(4696,AMPL_WIDTH),
conv_std_logic_vector(4699,AMPL_WIDTH),
conv_std_logic_vector(4702,AMPL_WIDTH),
conv_std_logic_vector(4705,AMPL_WIDTH),
conv_std_logic_vector(4708,AMPL_WIDTH),
conv_std_logic_vector(4712,AMPL_WIDTH),
conv_std_logic_vector(4715,AMPL_WIDTH),
conv_std_logic_vector(4718,AMPL_WIDTH),
conv_std_logic_vector(4721,AMPL_WIDTH),
conv_std_logic_vector(4724,AMPL_WIDTH),
conv_std_logic_vector(4727,AMPL_WIDTH),
conv_std_logic_vector(4730,AMPL_WIDTH),
conv_std_logic_vector(4733,AMPL_WIDTH),
conv_std_logic_vector(4736,AMPL_WIDTH),
conv_std_logic_vector(4740,AMPL_WIDTH),
conv_std_logic_vector(4743,AMPL_WIDTH),
conv_std_logic_vector(4746,AMPL_WIDTH),
conv_std_logic_vector(4749,AMPL_WIDTH),
conv_std_logic_vector(4752,AMPL_WIDTH),
conv_std_logic_vector(4755,AMPL_WIDTH),
conv_std_logic_vector(4758,AMPL_WIDTH),
conv_std_logic_vector(4761,AMPL_WIDTH),
conv_std_logic_vector(4764,AMPL_WIDTH),
conv_std_logic_vector(4768,AMPL_WIDTH),
conv_std_logic_vector(4771,AMPL_WIDTH),
conv_std_logic_vector(4774,AMPL_WIDTH),
conv_std_logic_vector(4777,AMPL_WIDTH),
conv_std_logic_vector(4780,AMPL_WIDTH),
conv_std_logic_vector(4783,AMPL_WIDTH),
conv_std_logic_vector(4786,AMPL_WIDTH),
conv_std_logic_vector(4789,AMPL_WIDTH),
conv_std_logic_vector(4792,AMPL_WIDTH),
conv_std_logic_vector(4795,AMPL_WIDTH),
conv_std_logic_vector(4799,AMPL_WIDTH),
conv_std_logic_vector(4802,AMPL_WIDTH),
conv_std_logic_vector(4805,AMPL_WIDTH),
conv_std_logic_vector(4808,AMPL_WIDTH),
conv_std_logic_vector(4811,AMPL_WIDTH),
conv_std_logic_vector(4814,AMPL_WIDTH),
conv_std_logic_vector(4817,AMPL_WIDTH),
conv_std_logic_vector(4820,AMPL_WIDTH),
conv_std_logic_vector(4823,AMPL_WIDTH),
conv_std_logic_vector(4827,AMPL_WIDTH),
conv_std_logic_vector(4830,AMPL_WIDTH),
conv_std_logic_vector(4833,AMPL_WIDTH),
conv_std_logic_vector(4836,AMPL_WIDTH),
conv_std_logic_vector(4839,AMPL_WIDTH),
conv_std_logic_vector(4842,AMPL_WIDTH),
conv_std_logic_vector(4845,AMPL_WIDTH),
conv_std_logic_vector(4848,AMPL_WIDTH),
conv_std_logic_vector(4851,AMPL_WIDTH),
conv_std_logic_vector(4855,AMPL_WIDTH),
conv_std_logic_vector(4858,AMPL_WIDTH),
conv_std_logic_vector(4861,AMPL_WIDTH),
conv_std_logic_vector(4864,AMPL_WIDTH),
conv_std_logic_vector(4867,AMPL_WIDTH),
conv_std_logic_vector(4870,AMPL_WIDTH),
conv_std_logic_vector(4873,AMPL_WIDTH),
conv_std_logic_vector(4876,AMPL_WIDTH),
conv_std_logic_vector(4879,AMPL_WIDTH),
conv_std_logic_vector(4882,AMPL_WIDTH),
conv_std_logic_vector(4886,AMPL_WIDTH),
conv_std_logic_vector(4889,AMPL_WIDTH),
conv_std_logic_vector(4892,AMPL_WIDTH),
conv_std_logic_vector(4895,AMPL_WIDTH),
conv_std_logic_vector(4898,AMPL_WIDTH),
conv_std_logic_vector(4901,AMPL_WIDTH),
conv_std_logic_vector(4904,AMPL_WIDTH),
conv_std_logic_vector(4907,AMPL_WIDTH),
conv_std_logic_vector(4910,AMPL_WIDTH),
conv_std_logic_vector(4914,AMPL_WIDTH),
conv_std_logic_vector(4917,AMPL_WIDTH),
conv_std_logic_vector(4920,AMPL_WIDTH),
conv_std_logic_vector(4923,AMPL_WIDTH),
conv_std_logic_vector(4926,AMPL_WIDTH),
conv_std_logic_vector(4929,AMPL_WIDTH),
conv_std_logic_vector(4932,AMPL_WIDTH),
conv_std_logic_vector(4935,AMPL_WIDTH),
conv_std_logic_vector(4938,AMPL_WIDTH),
conv_std_logic_vector(4941,AMPL_WIDTH),
conv_std_logic_vector(4945,AMPL_WIDTH),
conv_std_logic_vector(4948,AMPL_WIDTH),
conv_std_logic_vector(4951,AMPL_WIDTH),
conv_std_logic_vector(4954,AMPL_WIDTH),
conv_std_logic_vector(4957,AMPL_WIDTH),
conv_std_logic_vector(4960,AMPL_WIDTH),
conv_std_logic_vector(4963,AMPL_WIDTH),
conv_std_logic_vector(4966,AMPL_WIDTH),
conv_std_logic_vector(4969,AMPL_WIDTH),
conv_std_logic_vector(4973,AMPL_WIDTH),
conv_std_logic_vector(4976,AMPL_WIDTH),
conv_std_logic_vector(4979,AMPL_WIDTH),
conv_std_logic_vector(4982,AMPL_WIDTH),
conv_std_logic_vector(4985,AMPL_WIDTH),
conv_std_logic_vector(4988,AMPL_WIDTH),
conv_std_logic_vector(4991,AMPL_WIDTH),
conv_std_logic_vector(4994,AMPL_WIDTH),
conv_std_logic_vector(4997,AMPL_WIDTH),
conv_std_logic_vector(5000,AMPL_WIDTH),
conv_std_logic_vector(5004,AMPL_WIDTH),
conv_std_logic_vector(5007,AMPL_WIDTH),
conv_std_logic_vector(5010,AMPL_WIDTH),
conv_std_logic_vector(5013,AMPL_WIDTH),
conv_std_logic_vector(5016,AMPL_WIDTH),
conv_std_logic_vector(5019,AMPL_WIDTH),
conv_std_logic_vector(5022,AMPL_WIDTH),
conv_std_logic_vector(5025,AMPL_WIDTH),
conv_std_logic_vector(5028,AMPL_WIDTH),
conv_std_logic_vector(5032,AMPL_WIDTH),
conv_std_logic_vector(5035,AMPL_WIDTH),
conv_std_logic_vector(5038,AMPL_WIDTH),
conv_std_logic_vector(5041,AMPL_WIDTH),
conv_std_logic_vector(5044,AMPL_WIDTH),
conv_std_logic_vector(5047,AMPL_WIDTH),
conv_std_logic_vector(5050,AMPL_WIDTH),
conv_std_logic_vector(5053,AMPL_WIDTH),
conv_std_logic_vector(5056,AMPL_WIDTH),
conv_std_logic_vector(5059,AMPL_WIDTH),
conv_std_logic_vector(5063,AMPL_WIDTH),
conv_std_logic_vector(5066,AMPL_WIDTH),
conv_std_logic_vector(5069,AMPL_WIDTH),
conv_std_logic_vector(5072,AMPL_WIDTH),
conv_std_logic_vector(5075,AMPL_WIDTH),
conv_std_logic_vector(5078,AMPL_WIDTH),
conv_std_logic_vector(5081,AMPL_WIDTH),
conv_std_logic_vector(5084,AMPL_WIDTH),
conv_std_logic_vector(5087,AMPL_WIDTH),
conv_std_logic_vector(5091,AMPL_WIDTH),
conv_std_logic_vector(5094,AMPL_WIDTH),
conv_std_logic_vector(5097,AMPL_WIDTH),
conv_std_logic_vector(5100,AMPL_WIDTH),
conv_std_logic_vector(5103,AMPL_WIDTH),
conv_std_logic_vector(5106,AMPL_WIDTH),
conv_std_logic_vector(5109,AMPL_WIDTH),
conv_std_logic_vector(5112,AMPL_WIDTH),
conv_std_logic_vector(5115,AMPL_WIDTH),
conv_std_logic_vector(5118,AMPL_WIDTH),
conv_std_logic_vector(5122,AMPL_WIDTH),
conv_std_logic_vector(5125,AMPL_WIDTH),
conv_std_logic_vector(5128,AMPL_WIDTH),
conv_std_logic_vector(5131,AMPL_WIDTH),
conv_std_logic_vector(5134,AMPL_WIDTH),
conv_std_logic_vector(5137,AMPL_WIDTH),
conv_std_logic_vector(5140,AMPL_WIDTH),
conv_std_logic_vector(5143,AMPL_WIDTH),
conv_std_logic_vector(5146,AMPL_WIDTH),
conv_std_logic_vector(5149,AMPL_WIDTH),
conv_std_logic_vector(5153,AMPL_WIDTH),
conv_std_logic_vector(5156,AMPL_WIDTH),
conv_std_logic_vector(5159,AMPL_WIDTH),
conv_std_logic_vector(5162,AMPL_WIDTH),
conv_std_logic_vector(5165,AMPL_WIDTH),
conv_std_logic_vector(5168,AMPL_WIDTH),
conv_std_logic_vector(5171,AMPL_WIDTH),
conv_std_logic_vector(5174,AMPL_WIDTH),
conv_std_logic_vector(5177,AMPL_WIDTH),
conv_std_logic_vector(5180,AMPL_WIDTH),
conv_std_logic_vector(5184,AMPL_WIDTH),
conv_std_logic_vector(5187,AMPL_WIDTH),
conv_std_logic_vector(5190,AMPL_WIDTH),
conv_std_logic_vector(5193,AMPL_WIDTH),
conv_std_logic_vector(5196,AMPL_WIDTH),
conv_std_logic_vector(5199,AMPL_WIDTH),
conv_std_logic_vector(5202,AMPL_WIDTH),
conv_std_logic_vector(5205,AMPL_WIDTH),
conv_std_logic_vector(5208,AMPL_WIDTH),
conv_std_logic_vector(5212,AMPL_WIDTH),
conv_std_logic_vector(5215,AMPL_WIDTH),
conv_std_logic_vector(5218,AMPL_WIDTH),
conv_std_logic_vector(5221,AMPL_WIDTH),
conv_std_logic_vector(5224,AMPL_WIDTH),
conv_std_logic_vector(5227,AMPL_WIDTH),
conv_std_logic_vector(5230,AMPL_WIDTH),
conv_std_logic_vector(5233,AMPL_WIDTH),
conv_std_logic_vector(5236,AMPL_WIDTH),
conv_std_logic_vector(5239,AMPL_WIDTH),
conv_std_logic_vector(5243,AMPL_WIDTH),
conv_std_logic_vector(5246,AMPL_WIDTH),
conv_std_logic_vector(5249,AMPL_WIDTH),
conv_std_logic_vector(5252,AMPL_WIDTH),
conv_std_logic_vector(5255,AMPL_WIDTH),
conv_std_logic_vector(5258,AMPL_WIDTH),
conv_std_logic_vector(5261,AMPL_WIDTH),
conv_std_logic_vector(5264,AMPL_WIDTH),
conv_std_logic_vector(5267,AMPL_WIDTH),
conv_std_logic_vector(5270,AMPL_WIDTH),
conv_std_logic_vector(5274,AMPL_WIDTH),
conv_std_logic_vector(5277,AMPL_WIDTH),
conv_std_logic_vector(5280,AMPL_WIDTH),
conv_std_logic_vector(5283,AMPL_WIDTH),
conv_std_logic_vector(5286,AMPL_WIDTH),
conv_std_logic_vector(5289,AMPL_WIDTH),
conv_std_logic_vector(5292,AMPL_WIDTH),
conv_std_logic_vector(5295,AMPL_WIDTH),
conv_std_logic_vector(5298,AMPL_WIDTH),
conv_std_logic_vector(5301,AMPL_WIDTH),
conv_std_logic_vector(5305,AMPL_WIDTH),
conv_std_logic_vector(5308,AMPL_WIDTH),
conv_std_logic_vector(5311,AMPL_WIDTH),
conv_std_logic_vector(5314,AMPL_WIDTH),
conv_std_logic_vector(5317,AMPL_WIDTH),
conv_std_logic_vector(5320,AMPL_WIDTH),
conv_std_logic_vector(5323,AMPL_WIDTH),
conv_std_logic_vector(5326,AMPL_WIDTH),
conv_std_logic_vector(5329,AMPL_WIDTH),
conv_std_logic_vector(5332,AMPL_WIDTH),
conv_std_logic_vector(5336,AMPL_WIDTH),
conv_std_logic_vector(5339,AMPL_WIDTH),
conv_std_logic_vector(5342,AMPL_WIDTH),
conv_std_logic_vector(5345,AMPL_WIDTH),
conv_std_logic_vector(5348,AMPL_WIDTH),
conv_std_logic_vector(5351,AMPL_WIDTH),
conv_std_logic_vector(5354,AMPL_WIDTH),
conv_std_logic_vector(5357,AMPL_WIDTH),
conv_std_logic_vector(5360,AMPL_WIDTH),
conv_std_logic_vector(5363,AMPL_WIDTH),
conv_std_logic_vector(5367,AMPL_WIDTH),
conv_std_logic_vector(5370,AMPL_WIDTH),
conv_std_logic_vector(5373,AMPL_WIDTH),
conv_std_logic_vector(5376,AMPL_WIDTH),
conv_std_logic_vector(5379,AMPL_WIDTH),
conv_std_logic_vector(5382,AMPL_WIDTH),
conv_std_logic_vector(5385,AMPL_WIDTH),
conv_std_logic_vector(5388,AMPL_WIDTH),
conv_std_logic_vector(5391,AMPL_WIDTH),
conv_std_logic_vector(5394,AMPL_WIDTH),
conv_std_logic_vector(5398,AMPL_WIDTH),
conv_std_logic_vector(5401,AMPL_WIDTH),
conv_std_logic_vector(5404,AMPL_WIDTH),
conv_std_logic_vector(5407,AMPL_WIDTH),
conv_std_logic_vector(5410,AMPL_WIDTH),
conv_std_logic_vector(5413,AMPL_WIDTH),
conv_std_logic_vector(5416,AMPL_WIDTH),
conv_std_logic_vector(5419,AMPL_WIDTH),
conv_std_logic_vector(5422,AMPL_WIDTH),
conv_std_logic_vector(5425,AMPL_WIDTH),
conv_std_logic_vector(5428,AMPL_WIDTH),
conv_std_logic_vector(5432,AMPL_WIDTH),
conv_std_logic_vector(5435,AMPL_WIDTH),
conv_std_logic_vector(5438,AMPL_WIDTH),
conv_std_logic_vector(5441,AMPL_WIDTH),
conv_std_logic_vector(5444,AMPL_WIDTH),
conv_std_logic_vector(5447,AMPL_WIDTH),
conv_std_logic_vector(5450,AMPL_WIDTH),
conv_std_logic_vector(5453,AMPL_WIDTH),
conv_std_logic_vector(5456,AMPL_WIDTH),
conv_std_logic_vector(5459,AMPL_WIDTH),
conv_std_logic_vector(5463,AMPL_WIDTH),
conv_std_logic_vector(5466,AMPL_WIDTH),
conv_std_logic_vector(5469,AMPL_WIDTH),
conv_std_logic_vector(5472,AMPL_WIDTH),
conv_std_logic_vector(5475,AMPL_WIDTH),
conv_std_logic_vector(5478,AMPL_WIDTH),
conv_std_logic_vector(5481,AMPL_WIDTH),
conv_std_logic_vector(5484,AMPL_WIDTH),
conv_std_logic_vector(5487,AMPL_WIDTH),
conv_std_logic_vector(5490,AMPL_WIDTH),
conv_std_logic_vector(5494,AMPL_WIDTH),
conv_std_logic_vector(5497,AMPL_WIDTH),
conv_std_logic_vector(5500,AMPL_WIDTH),
conv_std_logic_vector(5503,AMPL_WIDTH),
conv_std_logic_vector(5506,AMPL_WIDTH),
conv_std_logic_vector(5509,AMPL_WIDTH),
conv_std_logic_vector(5512,AMPL_WIDTH),
conv_std_logic_vector(5515,AMPL_WIDTH),
conv_std_logic_vector(5518,AMPL_WIDTH),
conv_std_logic_vector(5521,AMPL_WIDTH),
conv_std_logic_vector(5525,AMPL_WIDTH),
conv_std_logic_vector(5528,AMPL_WIDTH),
conv_std_logic_vector(5531,AMPL_WIDTH),
conv_std_logic_vector(5534,AMPL_WIDTH),
conv_std_logic_vector(5537,AMPL_WIDTH),
conv_std_logic_vector(5540,AMPL_WIDTH),
conv_std_logic_vector(5543,AMPL_WIDTH),
conv_std_logic_vector(5546,AMPL_WIDTH),
conv_std_logic_vector(5549,AMPL_WIDTH),
conv_std_logic_vector(5552,AMPL_WIDTH),
conv_std_logic_vector(5555,AMPL_WIDTH),
conv_std_logic_vector(5559,AMPL_WIDTH),
conv_std_logic_vector(5562,AMPL_WIDTH),
conv_std_logic_vector(5565,AMPL_WIDTH),
conv_std_logic_vector(5568,AMPL_WIDTH),
conv_std_logic_vector(5571,AMPL_WIDTH),
conv_std_logic_vector(5574,AMPL_WIDTH),
conv_std_logic_vector(5577,AMPL_WIDTH),
conv_std_logic_vector(5580,AMPL_WIDTH),
conv_std_logic_vector(5583,AMPL_WIDTH),
conv_std_logic_vector(5586,AMPL_WIDTH),
conv_std_logic_vector(5590,AMPL_WIDTH),
conv_std_logic_vector(5593,AMPL_WIDTH),
conv_std_logic_vector(5596,AMPL_WIDTH),
conv_std_logic_vector(5599,AMPL_WIDTH),
conv_std_logic_vector(5602,AMPL_WIDTH),
conv_std_logic_vector(5605,AMPL_WIDTH),
conv_std_logic_vector(5608,AMPL_WIDTH),
conv_std_logic_vector(5611,AMPL_WIDTH),
conv_std_logic_vector(5614,AMPL_WIDTH),
conv_std_logic_vector(5617,AMPL_WIDTH),
conv_std_logic_vector(5620,AMPL_WIDTH),
conv_std_logic_vector(5624,AMPL_WIDTH),
conv_std_logic_vector(5627,AMPL_WIDTH),
conv_std_logic_vector(5630,AMPL_WIDTH),
conv_std_logic_vector(5633,AMPL_WIDTH),
conv_std_logic_vector(5636,AMPL_WIDTH),
conv_std_logic_vector(5639,AMPL_WIDTH),
conv_std_logic_vector(5642,AMPL_WIDTH),
conv_std_logic_vector(5645,AMPL_WIDTH),
conv_std_logic_vector(5648,AMPL_WIDTH),
conv_std_logic_vector(5651,AMPL_WIDTH),
conv_std_logic_vector(5655,AMPL_WIDTH),
conv_std_logic_vector(5658,AMPL_WIDTH),
conv_std_logic_vector(5661,AMPL_WIDTH),
conv_std_logic_vector(5664,AMPL_WIDTH),
conv_std_logic_vector(5667,AMPL_WIDTH),
conv_std_logic_vector(5670,AMPL_WIDTH),
conv_std_logic_vector(5673,AMPL_WIDTH),
conv_std_logic_vector(5676,AMPL_WIDTH),
conv_std_logic_vector(5679,AMPL_WIDTH),
conv_std_logic_vector(5682,AMPL_WIDTH),
conv_std_logic_vector(5685,AMPL_WIDTH),
conv_std_logic_vector(5689,AMPL_WIDTH),
conv_std_logic_vector(5692,AMPL_WIDTH),
conv_std_logic_vector(5695,AMPL_WIDTH),
conv_std_logic_vector(5698,AMPL_WIDTH),
conv_std_logic_vector(5701,AMPL_WIDTH),
conv_std_logic_vector(5704,AMPL_WIDTH),
conv_std_logic_vector(5707,AMPL_WIDTH),
conv_std_logic_vector(5710,AMPL_WIDTH),
conv_std_logic_vector(5713,AMPL_WIDTH),
conv_std_logic_vector(5716,AMPL_WIDTH),
conv_std_logic_vector(5719,AMPL_WIDTH),
conv_std_logic_vector(5723,AMPL_WIDTH),
conv_std_logic_vector(5726,AMPL_WIDTH),
conv_std_logic_vector(5729,AMPL_WIDTH),
conv_std_logic_vector(5732,AMPL_WIDTH),
conv_std_logic_vector(5735,AMPL_WIDTH),
conv_std_logic_vector(5738,AMPL_WIDTH),
conv_std_logic_vector(5741,AMPL_WIDTH),
conv_std_logic_vector(5744,AMPL_WIDTH),
conv_std_logic_vector(5747,AMPL_WIDTH),
conv_std_logic_vector(5750,AMPL_WIDTH),
conv_std_logic_vector(5754,AMPL_WIDTH),
conv_std_logic_vector(5757,AMPL_WIDTH),
conv_std_logic_vector(5760,AMPL_WIDTH),
conv_std_logic_vector(5763,AMPL_WIDTH),
conv_std_logic_vector(5766,AMPL_WIDTH),
conv_std_logic_vector(5769,AMPL_WIDTH),
conv_std_logic_vector(5772,AMPL_WIDTH),
conv_std_logic_vector(5775,AMPL_WIDTH),
conv_std_logic_vector(5778,AMPL_WIDTH),
conv_std_logic_vector(5781,AMPL_WIDTH),
conv_std_logic_vector(5784,AMPL_WIDTH),
conv_std_logic_vector(5788,AMPL_WIDTH),
conv_std_logic_vector(5791,AMPL_WIDTH),
conv_std_logic_vector(5794,AMPL_WIDTH),
conv_std_logic_vector(5797,AMPL_WIDTH),
conv_std_logic_vector(5800,AMPL_WIDTH),
conv_std_logic_vector(5803,AMPL_WIDTH),
conv_std_logic_vector(5806,AMPL_WIDTH),
conv_std_logic_vector(5809,AMPL_WIDTH),
conv_std_logic_vector(5812,AMPL_WIDTH),
conv_std_logic_vector(5815,AMPL_WIDTH),
conv_std_logic_vector(5818,AMPL_WIDTH),
conv_std_logic_vector(5822,AMPL_WIDTH),
conv_std_logic_vector(5825,AMPL_WIDTH),
conv_std_logic_vector(5828,AMPL_WIDTH),
conv_std_logic_vector(5831,AMPL_WIDTH),
conv_std_logic_vector(5834,AMPL_WIDTH),
conv_std_logic_vector(5837,AMPL_WIDTH),
conv_std_logic_vector(5840,AMPL_WIDTH),
conv_std_logic_vector(5843,AMPL_WIDTH),
conv_std_logic_vector(5846,AMPL_WIDTH),
conv_std_logic_vector(5849,AMPL_WIDTH),
conv_std_logic_vector(5852,AMPL_WIDTH),
conv_std_logic_vector(5856,AMPL_WIDTH),
conv_std_logic_vector(5859,AMPL_WIDTH),
conv_std_logic_vector(5862,AMPL_WIDTH),
conv_std_logic_vector(5865,AMPL_WIDTH),
conv_std_logic_vector(5868,AMPL_WIDTH),
conv_std_logic_vector(5871,AMPL_WIDTH),
conv_std_logic_vector(5874,AMPL_WIDTH),
conv_std_logic_vector(5877,AMPL_WIDTH),
conv_std_logic_vector(5880,AMPL_WIDTH),
conv_std_logic_vector(5883,AMPL_WIDTH),
conv_std_logic_vector(5886,AMPL_WIDTH),
conv_std_logic_vector(5890,AMPL_WIDTH),
conv_std_logic_vector(5893,AMPL_WIDTH),
conv_std_logic_vector(5896,AMPL_WIDTH),
conv_std_logic_vector(5899,AMPL_WIDTH),
conv_std_logic_vector(5902,AMPL_WIDTH),
conv_std_logic_vector(5905,AMPL_WIDTH),
conv_std_logic_vector(5908,AMPL_WIDTH),
conv_std_logic_vector(5911,AMPL_WIDTH),
conv_std_logic_vector(5914,AMPL_WIDTH),
conv_std_logic_vector(5917,AMPL_WIDTH),
conv_std_logic_vector(5920,AMPL_WIDTH),
conv_std_logic_vector(5924,AMPL_WIDTH),
conv_std_logic_vector(5927,AMPL_WIDTH),
conv_std_logic_vector(5930,AMPL_WIDTH),
conv_std_logic_vector(5933,AMPL_WIDTH),
conv_std_logic_vector(5936,AMPL_WIDTH),
conv_std_logic_vector(5939,AMPL_WIDTH),
conv_std_logic_vector(5942,AMPL_WIDTH),
conv_std_logic_vector(5945,AMPL_WIDTH),
conv_std_logic_vector(5948,AMPL_WIDTH),
conv_std_logic_vector(5951,AMPL_WIDTH),
conv_std_logic_vector(5954,AMPL_WIDTH),
conv_std_logic_vector(5958,AMPL_WIDTH),
conv_std_logic_vector(5961,AMPL_WIDTH),
conv_std_logic_vector(5964,AMPL_WIDTH),
conv_std_logic_vector(5967,AMPL_WIDTH),
conv_std_logic_vector(5970,AMPL_WIDTH),
conv_std_logic_vector(5973,AMPL_WIDTH),
conv_std_logic_vector(5976,AMPL_WIDTH),
conv_std_logic_vector(5979,AMPL_WIDTH),
conv_std_logic_vector(5982,AMPL_WIDTH),
conv_std_logic_vector(5985,AMPL_WIDTH),
conv_std_logic_vector(5988,AMPL_WIDTH),
conv_std_logic_vector(5991,AMPL_WIDTH),
conv_std_logic_vector(5995,AMPL_WIDTH),
conv_std_logic_vector(5998,AMPL_WIDTH),
conv_std_logic_vector(6001,AMPL_WIDTH),
conv_std_logic_vector(6004,AMPL_WIDTH),
conv_std_logic_vector(6007,AMPL_WIDTH),
conv_std_logic_vector(6010,AMPL_WIDTH),
conv_std_logic_vector(6013,AMPL_WIDTH),
conv_std_logic_vector(6016,AMPL_WIDTH),
conv_std_logic_vector(6019,AMPL_WIDTH),
conv_std_logic_vector(6022,AMPL_WIDTH),
conv_std_logic_vector(6025,AMPL_WIDTH),
conv_std_logic_vector(6029,AMPL_WIDTH),
conv_std_logic_vector(6032,AMPL_WIDTH),
conv_std_logic_vector(6035,AMPL_WIDTH),
conv_std_logic_vector(6038,AMPL_WIDTH),
conv_std_logic_vector(6041,AMPL_WIDTH),
conv_std_logic_vector(6044,AMPL_WIDTH),
conv_std_logic_vector(6047,AMPL_WIDTH),
conv_std_logic_vector(6050,AMPL_WIDTH),
conv_std_logic_vector(6053,AMPL_WIDTH),
conv_std_logic_vector(6056,AMPL_WIDTH),
conv_std_logic_vector(6059,AMPL_WIDTH),
conv_std_logic_vector(6063,AMPL_WIDTH),
conv_std_logic_vector(6066,AMPL_WIDTH),
conv_std_logic_vector(6069,AMPL_WIDTH),
conv_std_logic_vector(6072,AMPL_WIDTH),
conv_std_logic_vector(6075,AMPL_WIDTH),
conv_std_logic_vector(6078,AMPL_WIDTH),
conv_std_logic_vector(6081,AMPL_WIDTH),
conv_std_logic_vector(6084,AMPL_WIDTH),
conv_std_logic_vector(6087,AMPL_WIDTH),
conv_std_logic_vector(6090,AMPL_WIDTH),
conv_std_logic_vector(6093,AMPL_WIDTH),
conv_std_logic_vector(6096,AMPL_WIDTH),
conv_std_logic_vector(6100,AMPL_WIDTH),
conv_std_logic_vector(6103,AMPL_WIDTH),
conv_std_logic_vector(6106,AMPL_WIDTH),
conv_std_logic_vector(6109,AMPL_WIDTH),
conv_std_logic_vector(6112,AMPL_WIDTH),
conv_std_logic_vector(6115,AMPL_WIDTH),
conv_std_logic_vector(6118,AMPL_WIDTH),
conv_std_logic_vector(6121,AMPL_WIDTH),
conv_std_logic_vector(6124,AMPL_WIDTH),
conv_std_logic_vector(6127,AMPL_WIDTH),
conv_std_logic_vector(6130,AMPL_WIDTH),
conv_std_logic_vector(6134,AMPL_WIDTH),
conv_std_logic_vector(6137,AMPL_WIDTH),
conv_std_logic_vector(6140,AMPL_WIDTH),
conv_std_logic_vector(6143,AMPL_WIDTH),
conv_std_logic_vector(6146,AMPL_WIDTH),
conv_std_logic_vector(6149,AMPL_WIDTH),
conv_std_logic_vector(6152,AMPL_WIDTH),
conv_std_logic_vector(6155,AMPL_WIDTH),
conv_std_logic_vector(6158,AMPL_WIDTH),
conv_std_logic_vector(6161,AMPL_WIDTH),
conv_std_logic_vector(6164,AMPL_WIDTH),
conv_std_logic_vector(6167,AMPL_WIDTH),
conv_std_logic_vector(6171,AMPL_WIDTH),
conv_std_logic_vector(6174,AMPL_WIDTH),
conv_std_logic_vector(6177,AMPL_WIDTH),
conv_std_logic_vector(6180,AMPL_WIDTH),
conv_std_logic_vector(6183,AMPL_WIDTH),
conv_std_logic_vector(6186,AMPL_WIDTH),
conv_std_logic_vector(6189,AMPL_WIDTH),
conv_std_logic_vector(6192,AMPL_WIDTH),
conv_std_logic_vector(6195,AMPL_WIDTH),
conv_std_logic_vector(6198,AMPL_WIDTH),
conv_std_logic_vector(6201,AMPL_WIDTH),
conv_std_logic_vector(6204,AMPL_WIDTH),
conv_std_logic_vector(6208,AMPL_WIDTH),
conv_std_logic_vector(6211,AMPL_WIDTH),
conv_std_logic_vector(6214,AMPL_WIDTH),
conv_std_logic_vector(6217,AMPL_WIDTH),
conv_std_logic_vector(6220,AMPL_WIDTH),
conv_std_logic_vector(6223,AMPL_WIDTH),
conv_std_logic_vector(6226,AMPL_WIDTH),
conv_std_logic_vector(6229,AMPL_WIDTH),
conv_std_logic_vector(6232,AMPL_WIDTH),
conv_std_logic_vector(6235,AMPL_WIDTH),
conv_std_logic_vector(6238,AMPL_WIDTH),
conv_std_logic_vector(6241,AMPL_WIDTH),
conv_std_logic_vector(6245,AMPL_WIDTH),
conv_std_logic_vector(6248,AMPL_WIDTH),
conv_std_logic_vector(6251,AMPL_WIDTH),
conv_std_logic_vector(6254,AMPL_WIDTH),
conv_std_logic_vector(6257,AMPL_WIDTH),
conv_std_logic_vector(6260,AMPL_WIDTH),
conv_std_logic_vector(6263,AMPL_WIDTH),
conv_std_logic_vector(6266,AMPL_WIDTH),
conv_std_logic_vector(6269,AMPL_WIDTH),
conv_std_logic_vector(6272,AMPL_WIDTH),
conv_std_logic_vector(6275,AMPL_WIDTH),
conv_std_logic_vector(6278,AMPL_WIDTH),
conv_std_logic_vector(6282,AMPL_WIDTH),
conv_std_logic_vector(6285,AMPL_WIDTH),
conv_std_logic_vector(6288,AMPL_WIDTH),
conv_std_logic_vector(6291,AMPL_WIDTH),
conv_std_logic_vector(6294,AMPL_WIDTH),
conv_std_logic_vector(6297,AMPL_WIDTH),
conv_std_logic_vector(6300,AMPL_WIDTH),
conv_std_logic_vector(6303,AMPL_WIDTH),
conv_std_logic_vector(6306,AMPL_WIDTH),
conv_std_logic_vector(6309,AMPL_WIDTH),
conv_std_logic_vector(6312,AMPL_WIDTH),
conv_std_logic_vector(6315,AMPL_WIDTH),
conv_std_logic_vector(6319,AMPL_WIDTH),
conv_std_logic_vector(6322,AMPL_WIDTH),
conv_std_logic_vector(6325,AMPL_WIDTH),
conv_std_logic_vector(6328,AMPL_WIDTH),
conv_std_logic_vector(6331,AMPL_WIDTH),
conv_std_logic_vector(6334,AMPL_WIDTH),
conv_std_logic_vector(6337,AMPL_WIDTH),
conv_std_logic_vector(6340,AMPL_WIDTH),
conv_std_logic_vector(6343,AMPL_WIDTH),
conv_std_logic_vector(6346,AMPL_WIDTH),
conv_std_logic_vector(6349,AMPL_WIDTH),
conv_std_logic_vector(6352,AMPL_WIDTH),
conv_std_logic_vector(6356,AMPL_WIDTH),
conv_std_logic_vector(6359,AMPL_WIDTH),
conv_std_logic_vector(6362,AMPL_WIDTH),
conv_std_logic_vector(6365,AMPL_WIDTH),
conv_std_logic_vector(6368,AMPL_WIDTH),
conv_std_logic_vector(6371,AMPL_WIDTH),
conv_std_logic_vector(6374,AMPL_WIDTH),
conv_std_logic_vector(6377,AMPL_WIDTH),
conv_std_logic_vector(6380,AMPL_WIDTH),
conv_std_logic_vector(6383,AMPL_WIDTH),
conv_std_logic_vector(6386,AMPL_WIDTH),
conv_std_logic_vector(6389,AMPL_WIDTH),
conv_std_logic_vector(6393,AMPL_WIDTH),
conv_std_logic_vector(6396,AMPL_WIDTH),
conv_std_logic_vector(6399,AMPL_WIDTH),
conv_std_logic_vector(6402,AMPL_WIDTH),
conv_std_logic_vector(6405,AMPL_WIDTH),
conv_std_logic_vector(6408,AMPL_WIDTH),
conv_std_logic_vector(6411,AMPL_WIDTH),
conv_std_logic_vector(6414,AMPL_WIDTH),
conv_std_logic_vector(6417,AMPL_WIDTH),
conv_std_logic_vector(6420,AMPL_WIDTH),
conv_std_logic_vector(6423,AMPL_WIDTH),
conv_std_logic_vector(6426,AMPL_WIDTH),
conv_std_logic_vector(6429,AMPL_WIDTH),
conv_std_logic_vector(6433,AMPL_WIDTH),
conv_std_logic_vector(6436,AMPL_WIDTH),
conv_std_logic_vector(6439,AMPL_WIDTH),
conv_std_logic_vector(6442,AMPL_WIDTH),
conv_std_logic_vector(6445,AMPL_WIDTH),
conv_std_logic_vector(6448,AMPL_WIDTH),
conv_std_logic_vector(6451,AMPL_WIDTH),
conv_std_logic_vector(6454,AMPL_WIDTH),
conv_std_logic_vector(6457,AMPL_WIDTH),
conv_std_logic_vector(6460,AMPL_WIDTH),
conv_std_logic_vector(6463,AMPL_WIDTH),
conv_std_logic_vector(6466,AMPL_WIDTH),
conv_std_logic_vector(6470,AMPL_WIDTH),
conv_std_logic_vector(6473,AMPL_WIDTH),
conv_std_logic_vector(6476,AMPL_WIDTH),
conv_std_logic_vector(6479,AMPL_WIDTH),
conv_std_logic_vector(6482,AMPL_WIDTH),
conv_std_logic_vector(6485,AMPL_WIDTH),
conv_std_logic_vector(6488,AMPL_WIDTH),
conv_std_logic_vector(6491,AMPL_WIDTH),
conv_std_logic_vector(6494,AMPL_WIDTH),
conv_std_logic_vector(6497,AMPL_WIDTH),
conv_std_logic_vector(6500,AMPL_WIDTH),
conv_std_logic_vector(6503,AMPL_WIDTH),
conv_std_logic_vector(6506,AMPL_WIDTH),
conv_std_logic_vector(6510,AMPL_WIDTH),
conv_std_logic_vector(6513,AMPL_WIDTH),
conv_std_logic_vector(6516,AMPL_WIDTH),
conv_std_logic_vector(6519,AMPL_WIDTH),
conv_std_logic_vector(6522,AMPL_WIDTH),
conv_std_logic_vector(6525,AMPL_WIDTH),
conv_std_logic_vector(6528,AMPL_WIDTH),
conv_std_logic_vector(6531,AMPL_WIDTH),
conv_std_logic_vector(6534,AMPL_WIDTH),
conv_std_logic_vector(6537,AMPL_WIDTH),
conv_std_logic_vector(6540,AMPL_WIDTH),
conv_std_logic_vector(6543,AMPL_WIDTH),
conv_std_logic_vector(6547,AMPL_WIDTH),
conv_std_logic_vector(6550,AMPL_WIDTH),
conv_std_logic_vector(6553,AMPL_WIDTH),
conv_std_logic_vector(6556,AMPL_WIDTH),
conv_std_logic_vector(6559,AMPL_WIDTH),
conv_std_logic_vector(6562,AMPL_WIDTH),
conv_std_logic_vector(6565,AMPL_WIDTH),
conv_std_logic_vector(6568,AMPL_WIDTH),
conv_std_logic_vector(6571,AMPL_WIDTH),
conv_std_logic_vector(6574,AMPL_WIDTH),
conv_std_logic_vector(6577,AMPL_WIDTH),
conv_std_logic_vector(6580,AMPL_WIDTH),
conv_std_logic_vector(6583,AMPL_WIDTH),
conv_std_logic_vector(6587,AMPL_WIDTH),
conv_std_logic_vector(6590,AMPL_WIDTH),
conv_std_logic_vector(6593,AMPL_WIDTH),
conv_std_logic_vector(6596,AMPL_WIDTH),
conv_std_logic_vector(6599,AMPL_WIDTH),
conv_std_logic_vector(6602,AMPL_WIDTH),
conv_std_logic_vector(6605,AMPL_WIDTH),
conv_std_logic_vector(6608,AMPL_WIDTH),
conv_std_logic_vector(6611,AMPL_WIDTH),
conv_std_logic_vector(6614,AMPL_WIDTH),
conv_std_logic_vector(6617,AMPL_WIDTH),
conv_std_logic_vector(6620,AMPL_WIDTH),
conv_std_logic_vector(6623,AMPL_WIDTH),
conv_std_logic_vector(6627,AMPL_WIDTH),
conv_std_logic_vector(6630,AMPL_WIDTH),
conv_std_logic_vector(6633,AMPL_WIDTH),
conv_std_logic_vector(6636,AMPL_WIDTH),
conv_std_logic_vector(6639,AMPL_WIDTH),
conv_std_logic_vector(6642,AMPL_WIDTH),
conv_std_logic_vector(6645,AMPL_WIDTH),
conv_std_logic_vector(6648,AMPL_WIDTH),
conv_std_logic_vector(6651,AMPL_WIDTH),
conv_std_logic_vector(6654,AMPL_WIDTH),
conv_std_logic_vector(6657,AMPL_WIDTH),
conv_std_logic_vector(6660,AMPL_WIDTH),
conv_std_logic_vector(6663,AMPL_WIDTH),
conv_std_logic_vector(6667,AMPL_WIDTH),
conv_std_logic_vector(6670,AMPL_WIDTH),
conv_std_logic_vector(6673,AMPL_WIDTH),
conv_std_logic_vector(6676,AMPL_WIDTH),
conv_std_logic_vector(6679,AMPL_WIDTH),
conv_std_logic_vector(6682,AMPL_WIDTH),
conv_std_logic_vector(6685,AMPL_WIDTH),
conv_std_logic_vector(6688,AMPL_WIDTH),
conv_std_logic_vector(6691,AMPL_WIDTH),
conv_std_logic_vector(6694,AMPL_WIDTH),
conv_std_logic_vector(6697,AMPL_WIDTH),
conv_std_logic_vector(6700,AMPL_WIDTH),
conv_std_logic_vector(6703,AMPL_WIDTH),
conv_std_logic_vector(6706,AMPL_WIDTH),
conv_std_logic_vector(6710,AMPL_WIDTH),
conv_std_logic_vector(6713,AMPL_WIDTH),
conv_std_logic_vector(6716,AMPL_WIDTH),
conv_std_logic_vector(6719,AMPL_WIDTH),
conv_std_logic_vector(6722,AMPL_WIDTH),
conv_std_logic_vector(6725,AMPL_WIDTH),
conv_std_logic_vector(6728,AMPL_WIDTH),
conv_std_logic_vector(6731,AMPL_WIDTH),
conv_std_logic_vector(6734,AMPL_WIDTH),
conv_std_logic_vector(6737,AMPL_WIDTH),
conv_std_logic_vector(6740,AMPL_WIDTH),
conv_std_logic_vector(6743,AMPL_WIDTH),
conv_std_logic_vector(6746,AMPL_WIDTH),
conv_std_logic_vector(6750,AMPL_WIDTH),
conv_std_logic_vector(6753,AMPL_WIDTH),
conv_std_logic_vector(6756,AMPL_WIDTH),
conv_std_logic_vector(6759,AMPL_WIDTH),
conv_std_logic_vector(6762,AMPL_WIDTH),
conv_std_logic_vector(6765,AMPL_WIDTH),
conv_std_logic_vector(6768,AMPL_WIDTH),
conv_std_logic_vector(6771,AMPL_WIDTH),
conv_std_logic_vector(6774,AMPL_WIDTH),
conv_std_logic_vector(6777,AMPL_WIDTH),
conv_std_logic_vector(6780,AMPL_WIDTH),
conv_std_logic_vector(6783,AMPL_WIDTH),
conv_std_logic_vector(6786,AMPL_WIDTH),
conv_std_logic_vector(6789,AMPL_WIDTH),
conv_std_logic_vector(6793,AMPL_WIDTH),
conv_std_logic_vector(6796,AMPL_WIDTH),
conv_std_logic_vector(6799,AMPL_WIDTH),
conv_std_logic_vector(6802,AMPL_WIDTH),
conv_std_logic_vector(6805,AMPL_WIDTH),
conv_std_logic_vector(6808,AMPL_WIDTH),
conv_std_logic_vector(6811,AMPL_WIDTH),
conv_std_logic_vector(6814,AMPL_WIDTH),
conv_std_logic_vector(6817,AMPL_WIDTH),
conv_std_logic_vector(6820,AMPL_WIDTH),
conv_std_logic_vector(6823,AMPL_WIDTH),
conv_std_logic_vector(6826,AMPL_WIDTH),
conv_std_logic_vector(6829,AMPL_WIDTH),
conv_std_logic_vector(6833,AMPL_WIDTH),
conv_std_logic_vector(6836,AMPL_WIDTH),
conv_std_logic_vector(6839,AMPL_WIDTH),
conv_std_logic_vector(6842,AMPL_WIDTH),
conv_std_logic_vector(6845,AMPL_WIDTH),
conv_std_logic_vector(6848,AMPL_WIDTH),
conv_std_logic_vector(6851,AMPL_WIDTH),
conv_std_logic_vector(6854,AMPL_WIDTH),
conv_std_logic_vector(6857,AMPL_WIDTH),
conv_std_logic_vector(6860,AMPL_WIDTH),
conv_std_logic_vector(6863,AMPL_WIDTH),
conv_std_logic_vector(6866,AMPL_WIDTH),
conv_std_logic_vector(6869,AMPL_WIDTH),
conv_std_logic_vector(6872,AMPL_WIDTH),
conv_std_logic_vector(6876,AMPL_WIDTH),
conv_std_logic_vector(6879,AMPL_WIDTH),
conv_std_logic_vector(6882,AMPL_WIDTH),
conv_std_logic_vector(6885,AMPL_WIDTH),
conv_std_logic_vector(6888,AMPL_WIDTH),
conv_std_logic_vector(6891,AMPL_WIDTH),
conv_std_logic_vector(6894,AMPL_WIDTH),
conv_std_logic_vector(6897,AMPL_WIDTH),
conv_std_logic_vector(6900,AMPL_WIDTH),
conv_std_logic_vector(6903,AMPL_WIDTH),
conv_std_logic_vector(6906,AMPL_WIDTH),
conv_std_logic_vector(6909,AMPL_WIDTH),
conv_std_logic_vector(6912,AMPL_WIDTH),
conv_std_logic_vector(6915,AMPL_WIDTH),
conv_std_logic_vector(6919,AMPL_WIDTH),
conv_std_logic_vector(6922,AMPL_WIDTH),
conv_std_logic_vector(6925,AMPL_WIDTH),
conv_std_logic_vector(6928,AMPL_WIDTH),
conv_std_logic_vector(6931,AMPL_WIDTH),
conv_std_logic_vector(6934,AMPL_WIDTH),
conv_std_logic_vector(6937,AMPL_WIDTH),
conv_std_logic_vector(6940,AMPL_WIDTH),
conv_std_logic_vector(6943,AMPL_WIDTH),
conv_std_logic_vector(6946,AMPL_WIDTH),
conv_std_logic_vector(6949,AMPL_WIDTH),
conv_std_logic_vector(6952,AMPL_WIDTH),
conv_std_logic_vector(6955,AMPL_WIDTH),
conv_std_logic_vector(6958,AMPL_WIDTH),
conv_std_logic_vector(6961,AMPL_WIDTH),
conv_std_logic_vector(6965,AMPL_WIDTH),
conv_std_logic_vector(6968,AMPL_WIDTH),
conv_std_logic_vector(6971,AMPL_WIDTH),
conv_std_logic_vector(6974,AMPL_WIDTH),
conv_std_logic_vector(6977,AMPL_WIDTH),
conv_std_logic_vector(6980,AMPL_WIDTH),
conv_std_logic_vector(6983,AMPL_WIDTH),
conv_std_logic_vector(6986,AMPL_WIDTH),
conv_std_logic_vector(6989,AMPL_WIDTH),
conv_std_logic_vector(6992,AMPL_WIDTH),
conv_std_logic_vector(6995,AMPL_WIDTH),
conv_std_logic_vector(6998,AMPL_WIDTH),
conv_std_logic_vector(7001,AMPL_WIDTH),
conv_std_logic_vector(7004,AMPL_WIDTH),
conv_std_logic_vector(7008,AMPL_WIDTH),
conv_std_logic_vector(7011,AMPL_WIDTH),
conv_std_logic_vector(7014,AMPL_WIDTH),
conv_std_logic_vector(7017,AMPL_WIDTH),
conv_std_logic_vector(7020,AMPL_WIDTH),
conv_std_logic_vector(7023,AMPL_WIDTH),
conv_std_logic_vector(7026,AMPL_WIDTH),
conv_std_logic_vector(7029,AMPL_WIDTH),
conv_std_logic_vector(7032,AMPL_WIDTH),
conv_std_logic_vector(7035,AMPL_WIDTH),
conv_std_logic_vector(7038,AMPL_WIDTH),
conv_std_logic_vector(7041,AMPL_WIDTH),
conv_std_logic_vector(7044,AMPL_WIDTH),
conv_std_logic_vector(7047,AMPL_WIDTH),
conv_std_logic_vector(7050,AMPL_WIDTH),
conv_std_logic_vector(7054,AMPL_WIDTH),
conv_std_logic_vector(7057,AMPL_WIDTH),
conv_std_logic_vector(7060,AMPL_WIDTH),
conv_std_logic_vector(7063,AMPL_WIDTH),
conv_std_logic_vector(7066,AMPL_WIDTH),
conv_std_logic_vector(7069,AMPL_WIDTH),
conv_std_logic_vector(7072,AMPL_WIDTH),
conv_std_logic_vector(7075,AMPL_WIDTH),
conv_std_logic_vector(7078,AMPL_WIDTH),
conv_std_logic_vector(7081,AMPL_WIDTH),
conv_std_logic_vector(7084,AMPL_WIDTH),
conv_std_logic_vector(7087,AMPL_WIDTH),
conv_std_logic_vector(7090,AMPL_WIDTH),
conv_std_logic_vector(7093,AMPL_WIDTH),
conv_std_logic_vector(7097,AMPL_WIDTH),
conv_std_logic_vector(7100,AMPL_WIDTH),
conv_std_logic_vector(7103,AMPL_WIDTH),
conv_std_logic_vector(7106,AMPL_WIDTH),
conv_std_logic_vector(7109,AMPL_WIDTH),
conv_std_logic_vector(7112,AMPL_WIDTH),
conv_std_logic_vector(7115,AMPL_WIDTH),
conv_std_logic_vector(7118,AMPL_WIDTH),
conv_std_logic_vector(7121,AMPL_WIDTH),
conv_std_logic_vector(7124,AMPL_WIDTH),
conv_std_logic_vector(7127,AMPL_WIDTH),
conv_std_logic_vector(7130,AMPL_WIDTH),
conv_std_logic_vector(7133,AMPL_WIDTH),
conv_std_logic_vector(7136,AMPL_WIDTH),
conv_std_logic_vector(7139,AMPL_WIDTH),
conv_std_logic_vector(7143,AMPL_WIDTH),
conv_std_logic_vector(7146,AMPL_WIDTH),
conv_std_logic_vector(7149,AMPL_WIDTH),
conv_std_logic_vector(7152,AMPL_WIDTH),
conv_std_logic_vector(7155,AMPL_WIDTH),
conv_std_logic_vector(7158,AMPL_WIDTH),
conv_std_logic_vector(7161,AMPL_WIDTH),
conv_std_logic_vector(7164,AMPL_WIDTH),
conv_std_logic_vector(7167,AMPL_WIDTH),
conv_std_logic_vector(7170,AMPL_WIDTH),
conv_std_logic_vector(7173,AMPL_WIDTH),
conv_std_logic_vector(7176,AMPL_WIDTH),
conv_std_logic_vector(7179,AMPL_WIDTH),
conv_std_logic_vector(7182,AMPL_WIDTH),
conv_std_logic_vector(7185,AMPL_WIDTH),
conv_std_logic_vector(7188,AMPL_WIDTH),
conv_std_logic_vector(7192,AMPL_WIDTH),
conv_std_logic_vector(7195,AMPL_WIDTH),
conv_std_logic_vector(7198,AMPL_WIDTH),
conv_std_logic_vector(7201,AMPL_WIDTH),
conv_std_logic_vector(7204,AMPL_WIDTH),
conv_std_logic_vector(7207,AMPL_WIDTH),
conv_std_logic_vector(7210,AMPL_WIDTH),
conv_std_logic_vector(7213,AMPL_WIDTH),
conv_std_logic_vector(7216,AMPL_WIDTH),
conv_std_logic_vector(7219,AMPL_WIDTH),
conv_std_logic_vector(7222,AMPL_WIDTH),
conv_std_logic_vector(7225,AMPL_WIDTH),
conv_std_logic_vector(7228,AMPL_WIDTH),
conv_std_logic_vector(7231,AMPL_WIDTH),
conv_std_logic_vector(7234,AMPL_WIDTH),
conv_std_logic_vector(7238,AMPL_WIDTH),
conv_std_logic_vector(7241,AMPL_WIDTH),
conv_std_logic_vector(7244,AMPL_WIDTH),
conv_std_logic_vector(7247,AMPL_WIDTH),
conv_std_logic_vector(7250,AMPL_WIDTH),
conv_std_logic_vector(7253,AMPL_WIDTH),
conv_std_logic_vector(7256,AMPL_WIDTH),
conv_std_logic_vector(7259,AMPL_WIDTH),
conv_std_logic_vector(7262,AMPL_WIDTH),
conv_std_logic_vector(7265,AMPL_WIDTH),
conv_std_logic_vector(7268,AMPL_WIDTH),
conv_std_logic_vector(7271,AMPL_WIDTH),
conv_std_logic_vector(7274,AMPL_WIDTH),
conv_std_logic_vector(7277,AMPL_WIDTH),
conv_std_logic_vector(7280,AMPL_WIDTH),
conv_std_logic_vector(7283,AMPL_WIDTH),
conv_std_logic_vector(7287,AMPL_WIDTH),
conv_std_logic_vector(7290,AMPL_WIDTH),
conv_std_logic_vector(7293,AMPL_WIDTH),
conv_std_logic_vector(7296,AMPL_WIDTH),
conv_std_logic_vector(7299,AMPL_WIDTH),
conv_std_logic_vector(7302,AMPL_WIDTH),
conv_std_logic_vector(7305,AMPL_WIDTH),
conv_std_logic_vector(7308,AMPL_WIDTH),
conv_std_logic_vector(7311,AMPL_WIDTH),
conv_std_logic_vector(7314,AMPL_WIDTH),
conv_std_logic_vector(7317,AMPL_WIDTH),
conv_std_logic_vector(7320,AMPL_WIDTH),
conv_std_logic_vector(7323,AMPL_WIDTH),
conv_std_logic_vector(7326,AMPL_WIDTH),
conv_std_logic_vector(7329,AMPL_WIDTH),
conv_std_logic_vector(7332,AMPL_WIDTH),
conv_std_logic_vector(7336,AMPL_WIDTH),
conv_std_logic_vector(7339,AMPL_WIDTH),
conv_std_logic_vector(7342,AMPL_WIDTH),
conv_std_logic_vector(7345,AMPL_WIDTH),
conv_std_logic_vector(7348,AMPL_WIDTH),
conv_std_logic_vector(7351,AMPL_WIDTH),
conv_std_logic_vector(7354,AMPL_WIDTH),
conv_std_logic_vector(7357,AMPL_WIDTH),
conv_std_logic_vector(7360,AMPL_WIDTH),
conv_std_logic_vector(7363,AMPL_WIDTH),
conv_std_logic_vector(7366,AMPL_WIDTH),
conv_std_logic_vector(7369,AMPL_WIDTH),
conv_std_logic_vector(7372,AMPL_WIDTH),
conv_std_logic_vector(7375,AMPL_WIDTH),
conv_std_logic_vector(7378,AMPL_WIDTH),
conv_std_logic_vector(7381,AMPL_WIDTH),
conv_std_logic_vector(7385,AMPL_WIDTH),
conv_std_logic_vector(7388,AMPL_WIDTH),
conv_std_logic_vector(7391,AMPL_WIDTH),
conv_std_logic_vector(7394,AMPL_WIDTH),
conv_std_logic_vector(7397,AMPL_WIDTH),
conv_std_logic_vector(7400,AMPL_WIDTH),
conv_std_logic_vector(7403,AMPL_WIDTH),
conv_std_logic_vector(7406,AMPL_WIDTH),
conv_std_logic_vector(7409,AMPL_WIDTH),
conv_std_logic_vector(7412,AMPL_WIDTH),
conv_std_logic_vector(7415,AMPL_WIDTH),
conv_std_logic_vector(7418,AMPL_WIDTH),
conv_std_logic_vector(7421,AMPL_WIDTH),
conv_std_logic_vector(7424,AMPL_WIDTH),
conv_std_logic_vector(7427,AMPL_WIDTH),
conv_std_logic_vector(7430,AMPL_WIDTH),
conv_std_logic_vector(7433,AMPL_WIDTH),
conv_std_logic_vector(7437,AMPL_WIDTH),
conv_std_logic_vector(7440,AMPL_WIDTH),
conv_std_logic_vector(7443,AMPL_WIDTH),
conv_std_logic_vector(7446,AMPL_WIDTH),
conv_std_logic_vector(7449,AMPL_WIDTH),
conv_std_logic_vector(7452,AMPL_WIDTH),
conv_std_logic_vector(7455,AMPL_WIDTH),
conv_std_logic_vector(7458,AMPL_WIDTH),
conv_std_logic_vector(7461,AMPL_WIDTH),
conv_std_logic_vector(7464,AMPL_WIDTH),
conv_std_logic_vector(7467,AMPL_WIDTH),
conv_std_logic_vector(7470,AMPL_WIDTH),
conv_std_logic_vector(7473,AMPL_WIDTH),
conv_std_logic_vector(7476,AMPL_WIDTH),
conv_std_logic_vector(7479,AMPL_WIDTH),
conv_std_logic_vector(7482,AMPL_WIDTH),
conv_std_logic_vector(7485,AMPL_WIDTH),
conv_std_logic_vector(7489,AMPL_WIDTH),
conv_std_logic_vector(7492,AMPL_WIDTH),
conv_std_logic_vector(7495,AMPL_WIDTH),
conv_std_logic_vector(7498,AMPL_WIDTH),
conv_std_logic_vector(7501,AMPL_WIDTH),
conv_std_logic_vector(7504,AMPL_WIDTH),
conv_std_logic_vector(7507,AMPL_WIDTH),
conv_std_logic_vector(7510,AMPL_WIDTH),
conv_std_logic_vector(7513,AMPL_WIDTH),
conv_std_logic_vector(7516,AMPL_WIDTH),
conv_std_logic_vector(7519,AMPL_WIDTH),
conv_std_logic_vector(7522,AMPL_WIDTH),
conv_std_logic_vector(7525,AMPL_WIDTH),
conv_std_logic_vector(7528,AMPL_WIDTH),
conv_std_logic_vector(7531,AMPL_WIDTH),
conv_std_logic_vector(7534,AMPL_WIDTH),
conv_std_logic_vector(7537,AMPL_WIDTH),
conv_std_logic_vector(7541,AMPL_WIDTH),
conv_std_logic_vector(7544,AMPL_WIDTH),
conv_std_logic_vector(7547,AMPL_WIDTH),
conv_std_logic_vector(7550,AMPL_WIDTH),
conv_std_logic_vector(7553,AMPL_WIDTH),
conv_std_logic_vector(7556,AMPL_WIDTH),
conv_std_logic_vector(7559,AMPL_WIDTH),
conv_std_logic_vector(7562,AMPL_WIDTH),
conv_std_logic_vector(7565,AMPL_WIDTH),
conv_std_logic_vector(7568,AMPL_WIDTH),
conv_std_logic_vector(7571,AMPL_WIDTH),
conv_std_logic_vector(7574,AMPL_WIDTH),
conv_std_logic_vector(7577,AMPL_WIDTH),
conv_std_logic_vector(7580,AMPL_WIDTH),
conv_std_logic_vector(7583,AMPL_WIDTH),
conv_std_logic_vector(7586,AMPL_WIDTH),
conv_std_logic_vector(7589,AMPL_WIDTH),
conv_std_logic_vector(7592,AMPL_WIDTH),
conv_std_logic_vector(7596,AMPL_WIDTH),
conv_std_logic_vector(7599,AMPL_WIDTH),
conv_std_logic_vector(7602,AMPL_WIDTH),
conv_std_logic_vector(7605,AMPL_WIDTH),
conv_std_logic_vector(7608,AMPL_WIDTH),
conv_std_logic_vector(7611,AMPL_WIDTH),
conv_std_logic_vector(7614,AMPL_WIDTH),
conv_std_logic_vector(7617,AMPL_WIDTH),
conv_std_logic_vector(7620,AMPL_WIDTH),
conv_std_logic_vector(7623,AMPL_WIDTH),
conv_std_logic_vector(7626,AMPL_WIDTH),
conv_std_logic_vector(7629,AMPL_WIDTH),
conv_std_logic_vector(7632,AMPL_WIDTH),
conv_std_logic_vector(7635,AMPL_WIDTH),
conv_std_logic_vector(7638,AMPL_WIDTH),
conv_std_logic_vector(7641,AMPL_WIDTH),
conv_std_logic_vector(7644,AMPL_WIDTH),
conv_std_logic_vector(7647,AMPL_WIDTH),
conv_std_logic_vector(7651,AMPL_WIDTH),
conv_std_logic_vector(7654,AMPL_WIDTH),
conv_std_logic_vector(7657,AMPL_WIDTH),
conv_std_logic_vector(7660,AMPL_WIDTH),
conv_std_logic_vector(7663,AMPL_WIDTH),
conv_std_logic_vector(7666,AMPL_WIDTH),
conv_std_logic_vector(7669,AMPL_WIDTH),
conv_std_logic_vector(7672,AMPL_WIDTH),
conv_std_logic_vector(7675,AMPL_WIDTH),
conv_std_logic_vector(7678,AMPL_WIDTH),
conv_std_logic_vector(7681,AMPL_WIDTH),
conv_std_logic_vector(7684,AMPL_WIDTH),
conv_std_logic_vector(7687,AMPL_WIDTH),
conv_std_logic_vector(7690,AMPL_WIDTH),
conv_std_logic_vector(7693,AMPL_WIDTH),
conv_std_logic_vector(7696,AMPL_WIDTH),
conv_std_logic_vector(7699,AMPL_WIDTH),
conv_std_logic_vector(7702,AMPL_WIDTH),
conv_std_logic_vector(7705,AMPL_WIDTH),
conv_std_logic_vector(7709,AMPL_WIDTH),
conv_std_logic_vector(7712,AMPL_WIDTH),
conv_std_logic_vector(7715,AMPL_WIDTH),
conv_std_logic_vector(7718,AMPL_WIDTH),
conv_std_logic_vector(7721,AMPL_WIDTH),
conv_std_logic_vector(7724,AMPL_WIDTH),
conv_std_logic_vector(7727,AMPL_WIDTH),
conv_std_logic_vector(7730,AMPL_WIDTH),
conv_std_logic_vector(7733,AMPL_WIDTH),
conv_std_logic_vector(7736,AMPL_WIDTH),
conv_std_logic_vector(7739,AMPL_WIDTH),
conv_std_logic_vector(7742,AMPL_WIDTH),
conv_std_logic_vector(7745,AMPL_WIDTH),
conv_std_logic_vector(7748,AMPL_WIDTH),
conv_std_logic_vector(7751,AMPL_WIDTH),
conv_std_logic_vector(7754,AMPL_WIDTH),
conv_std_logic_vector(7757,AMPL_WIDTH),
conv_std_logic_vector(7760,AMPL_WIDTH),
conv_std_logic_vector(7764,AMPL_WIDTH),
conv_std_logic_vector(7767,AMPL_WIDTH),
conv_std_logic_vector(7770,AMPL_WIDTH),
conv_std_logic_vector(7773,AMPL_WIDTH),
conv_std_logic_vector(7776,AMPL_WIDTH),
conv_std_logic_vector(7779,AMPL_WIDTH),
conv_std_logic_vector(7782,AMPL_WIDTH),
conv_std_logic_vector(7785,AMPL_WIDTH),
conv_std_logic_vector(7788,AMPL_WIDTH),
conv_std_logic_vector(7791,AMPL_WIDTH),
conv_std_logic_vector(7794,AMPL_WIDTH),
conv_std_logic_vector(7797,AMPL_WIDTH),
conv_std_logic_vector(7800,AMPL_WIDTH),
conv_std_logic_vector(7803,AMPL_WIDTH),
conv_std_logic_vector(7806,AMPL_WIDTH),
conv_std_logic_vector(7809,AMPL_WIDTH),
conv_std_logic_vector(7812,AMPL_WIDTH),
conv_std_logic_vector(7815,AMPL_WIDTH),
conv_std_logic_vector(7818,AMPL_WIDTH),
conv_std_logic_vector(7821,AMPL_WIDTH),
conv_std_logic_vector(7825,AMPL_WIDTH),
conv_std_logic_vector(7828,AMPL_WIDTH),
conv_std_logic_vector(7831,AMPL_WIDTH),
conv_std_logic_vector(7834,AMPL_WIDTH),
conv_std_logic_vector(7837,AMPL_WIDTH),
conv_std_logic_vector(7840,AMPL_WIDTH),
conv_std_logic_vector(7843,AMPL_WIDTH),
conv_std_logic_vector(7846,AMPL_WIDTH),
conv_std_logic_vector(7849,AMPL_WIDTH),
conv_std_logic_vector(7852,AMPL_WIDTH),
conv_std_logic_vector(7855,AMPL_WIDTH),
conv_std_logic_vector(7858,AMPL_WIDTH),
conv_std_logic_vector(7861,AMPL_WIDTH),
conv_std_logic_vector(7864,AMPL_WIDTH),
conv_std_logic_vector(7867,AMPL_WIDTH),
conv_std_logic_vector(7870,AMPL_WIDTH),
conv_std_logic_vector(7873,AMPL_WIDTH),
conv_std_logic_vector(7876,AMPL_WIDTH),
conv_std_logic_vector(7879,AMPL_WIDTH),
conv_std_logic_vector(7882,AMPL_WIDTH),
conv_std_logic_vector(7886,AMPL_WIDTH),
conv_std_logic_vector(7889,AMPL_WIDTH),
conv_std_logic_vector(7892,AMPL_WIDTH),
conv_std_logic_vector(7895,AMPL_WIDTH),
conv_std_logic_vector(7898,AMPL_WIDTH),
conv_std_logic_vector(7901,AMPL_WIDTH),
conv_std_logic_vector(7904,AMPL_WIDTH),
conv_std_logic_vector(7907,AMPL_WIDTH),
conv_std_logic_vector(7910,AMPL_WIDTH),
conv_std_logic_vector(7913,AMPL_WIDTH),
conv_std_logic_vector(7916,AMPL_WIDTH),
conv_std_logic_vector(7919,AMPL_WIDTH),
conv_std_logic_vector(7922,AMPL_WIDTH),
conv_std_logic_vector(7925,AMPL_WIDTH),
conv_std_logic_vector(7928,AMPL_WIDTH),
conv_std_logic_vector(7931,AMPL_WIDTH),
conv_std_logic_vector(7934,AMPL_WIDTH),
conv_std_logic_vector(7937,AMPL_WIDTH),
conv_std_logic_vector(7940,AMPL_WIDTH),
conv_std_logic_vector(7943,AMPL_WIDTH),
conv_std_logic_vector(7946,AMPL_WIDTH),
conv_std_logic_vector(7950,AMPL_WIDTH),
conv_std_logic_vector(7953,AMPL_WIDTH),
conv_std_logic_vector(7956,AMPL_WIDTH),
conv_std_logic_vector(7959,AMPL_WIDTH),
conv_std_logic_vector(7962,AMPL_WIDTH),
conv_std_logic_vector(7965,AMPL_WIDTH),
conv_std_logic_vector(7968,AMPL_WIDTH),
conv_std_logic_vector(7971,AMPL_WIDTH),
conv_std_logic_vector(7974,AMPL_WIDTH),
conv_std_logic_vector(7977,AMPL_WIDTH),
conv_std_logic_vector(7980,AMPL_WIDTH),
conv_std_logic_vector(7983,AMPL_WIDTH),
conv_std_logic_vector(7986,AMPL_WIDTH),
conv_std_logic_vector(7989,AMPL_WIDTH),
conv_std_logic_vector(7992,AMPL_WIDTH),
conv_std_logic_vector(7995,AMPL_WIDTH),
conv_std_logic_vector(7998,AMPL_WIDTH),
conv_std_logic_vector(8001,AMPL_WIDTH),
conv_std_logic_vector(8004,AMPL_WIDTH),
conv_std_logic_vector(8007,AMPL_WIDTH),
conv_std_logic_vector(8010,AMPL_WIDTH),
conv_std_logic_vector(8014,AMPL_WIDTH),
conv_std_logic_vector(8017,AMPL_WIDTH),
conv_std_logic_vector(8020,AMPL_WIDTH),
conv_std_logic_vector(8023,AMPL_WIDTH),
conv_std_logic_vector(8026,AMPL_WIDTH),
conv_std_logic_vector(8029,AMPL_WIDTH),
conv_std_logic_vector(8032,AMPL_WIDTH),
conv_std_logic_vector(8035,AMPL_WIDTH),
conv_std_logic_vector(8038,AMPL_WIDTH),
conv_std_logic_vector(8041,AMPL_WIDTH),
conv_std_logic_vector(8044,AMPL_WIDTH),
conv_std_logic_vector(8047,AMPL_WIDTH),
conv_std_logic_vector(8050,AMPL_WIDTH),
conv_std_logic_vector(8053,AMPL_WIDTH),
conv_std_logic_vector(8056,AMPL_WIDTH),
conv_std_logic_vector(8059,AMPL_WIDTH),
conv_std_logic_vector(8062,AMPL_WIDTH),
conv_std_logic_vector(8065,AMPL_WIDTH),
conv_std_logic_vector(8068,AMPL_WIDTH),
conv_std_logic_vector(8071,AMPL_WIDTH),
conv_std_logic_vector(8074,AMPL_WIDTH),
conv_std_logic_vector(8077,AMPL_WIDTH),
conv_std_logic_vector(8081,AMPL_WIDTH),
conv_std_logic_vector(8084,AMPL_WIDTH),
conv_std_logic_vector(8087,AMPL_WIDTH),
conv_std_logic_vector(8090,AMPL_WIDTH),
conv_std_logic_vector(8093,AMPL_WIDTH),
conv_std_logic_vector(8096,AMPL_WIDTH),
conv_std_logic_vector(8099,AMPL_WIDTH),
conv_std_logic_vector(8102,AMPL_WIDTH),
conv_std_logic_vector(8105,AMPL_WIDTH),
conv_std_logic_vector(8108,AMPL_WIDTH),
conv_std_logic_vector(8111,AMPL_WIDTH),
conv_std_logic_vector(8114,AMPL_WIDTH),
conv_std_logic_vector(8117,AMPL_WIDTH),
conv_std_logic_vector(8120,AMPL_WIDTH),
conv_std_logic_vector(8123,AMPL_WIDTH),
conv_std_logic_vector(8126,AMPL_WIDTH),
conv_std_logic_vector(8129,AMPL_WIDTH),
conv_std_logic_vector(8132,AMPL_WIDTH),
conv_std_logic_vector(8135,AMPL_WIDTH),
conv_std_logic_vector(8138,AMPL_WIDTH),
conv_std_logic_vector(8141,AMPL_WIDTH),
conv_std_logic_vector(8144,AMPL_WIDTH),
conv_std_logic_vector(8147,AMPL_WIDTH),
conv_std_logic_vector(8151,AMPL_WIDTH),
conv_std_logic_vector(8154,AMPL_WIDTH),
conv_std_logic_vector(8157,AMPL_WIDTH),
conv_std_logic_vector(8160,AMPL_WIDTH),
conv_std_logic_vector(8163,AMPL_WIDTH),
conv_std_logic_vector(8166,AMPL_WIDTH),
conv_std_logic_vector(8169,AMPL_WIDTH),
conv_std_logic_vector(8172,AMPL_WIDTH),
conv_std_logic_vector(8175,AMPL_WIDTH),
conv_std_logic_vector(8178,AMPL_WIDTH),
conv_std_logic_vector(8181,AMPL_WIDTH),
conv_std_logic_vector(8184,AMPL_WIDTH),
conv_std_logic_vector(8187,AMPL_WIDTH),
conv_std_logic_vector(8190,AMPL_WIDTH),
conv_std_logic_vector(8193,AMPL_WIDTH),
conv_std_logic_vector(8196,AMPL_WIDTH),
conv_std_logic_vector(8199,AMPL_WIDTH),
conv_std_logic_vector(8202,AMPL_WIDTH),
conv_std_logic_vector(8205,AMPL_WIDTH),
conv_std_logic_vector(8208,AMPL_WIDTH),
conv_std_logic_vector(8211,AMPL_WIDTH),
conv_std_logic_vector(8214,AMPL_WIDTH),
conv_std_logic_vector(8217,AMPL_WIDTH),
conv_std_logic_vector(8220,AMPL_WIDTH),
conv_std_logic_vector(8224,AMPL_WIDTH),
conv_std_logic_vector(8227,AMPL_WIDTH),
conv_std_logic_vector(8230,AMPL_WIDTH),
conv_std_logic_vector(8233,AMPL_WIDTH),
conv_std_logic_vector(8236,AMPL_WIDTH),
conv_std_logic_vector(8239,AMPL_WIDTH),
conv_std_logic_vector(8242,AMPL_WIDTH),
conv_std_logic_vector(8245,AMPL_WIDTH),
conv_std_logic_vector(8248,AMPL_WIDTH),
conv_std_logic_vector(8251,AMPL_WIDTH),
conv_std_logic_vector(8254,AMPL_WIDTH),
conv_std_logic_vector(8257,AMPL_WIDTH),
conv_std_logic_vector(8260,AMPL_WIDTH),
conv_std_logic_vector(8263,AMPL_WIDTH),
conv_std_logic_vector(8266,AMPL_WIDTH),
conv_std_logic_vector(8269,AMPL_WIDTH),
conv_std_logic_vector(8272,AMPL_WIDTH),
conv_std_logic_vector(8275,AMPL_WIDTH),
conv_std_logic_vector(8278,AMPL_WIDTH),
conv_std_logic_vector(8281,AMPL_WIDTH),
conv_std_logic_vector(8284,AMPL_WIDTH),
conv_std_logic_vector(8287,AMPL_WIDTH),
conv_std_logic_vector(8290,AMPL_WIDTH),
conv_std_logic_vector(8293,AMPL_WIDTH),
conv_std_logic_vector(8296,AMPL_WIDTH),
conv_std_logic_vector(8300,AMPL_WIDTH),
conv_std_logic_vector(8303,AMPL_WIDTH),
conv_std_logic_vector(8306,AMPL_WIDTH),
conv_std_logic_vector(8309,AMPL_WIDTH),
conv_std_logic_vector(8312,AMPL_WIDTH),
conv_std_logic_vector(8315,AMPL_WIDTH),
conv_std_logic_vector(8318,AMPL_WIDTH),
conv_std_logic_vector(8321,AMPL_WIDTH),
conv_std_logic_vector(8324,AMPL_WIDTH),
conv_std_logic_vector(8327,AMPL_WIDTH),
conv_std_logic_vector(8330,AMPL_WIDTH),
conv_std_logic_vector(8333,AMPL_WIDTH),
conv_std_logic_vector(8336,AMPL_WIDTH),
conv_std_logic_vector(8339,AMPL_WIDTH),
conv_std_logic_vector(8342,AMPL_WIDTH),
conv_std_logic_vector(8345,AMPL_WIDTH),
conv_std_logic_vector(8348,AMPL_WIDTH),
conv_std_logic_vector(8351,AMPL_WIDTH),
conv_std_logic_vector(8354,AMPL_WIDTH),
conv_std_logic_vector(8357,AMPL_WIDTH),
conv_std_logic_vector(8360,AMPL_WIDTH),
conv_std_logic_vector(8363,AMPL_WIDTH),
conv_std_logic_vector(8366,AMPL_WIDTH),
conv_std_logic_vector(8369,AMPL_WIDTH),
conv_std_logic_vector(8372,AMPL_WIDTH),
conv_std_logic_vector(8375,AMPL_WIDTH),
conv_std_logic_vector(8379,AMPL_WIDTH),
conv_std_logic_vector(8382,AMPL_WIDTH),
conv_std_logic_vector(8385,AMPL_WIDTH),
conv_std_logic_vector(8388,AMPL_WIDTH),
conv_std_logic_vector(8391,AMPL_WIDTH),
conv_std_logic_vector(8394,AMPL_WIDTH),
conv_std_logic_vector(8397,AMPL_WIDTH),
conv_std_logic_vector(8400,AMPL_WIDTH),
conv_std_logic_vector(8403,AMPL_WIDTH),
conv_std_logic_vector(8406,AMPL_WIDTH),
conv_std_logic_vector(8409,AMPL_WIDTH),
conv_std_logic_vector(8412,AMPL_WIDTH),
conv_std_logic_vector(8415,AMPL_WIDTH),
conv_std_logic_vector(8418,AMPL_WIDTH),
conv_std_logic_vector(8421,AMPL_WIDTH),
conv_std_logic_vector(8424,AMPL_WIDTH),
conv_std_logic_vector(8427,AMPL_WIDTH),
conv_std_logic_vector(8430,AMPL_WIDTH),
conv_std_logic_vector(8433,AMPL_WIDTH),
conv_std_logic_vector(8436,AMPL_WIDTH),
conv_std_logic_vector(8439,AMPL_WIDTH),
conv_std_logic_vector(8442,AMPL_WIDTH),
conv_std_logic_vector(8445,AMPL_WIDTH),
conv_std_logic_vector(8448,AMPL_WIDTH),
conv_std_logic_vector(8451,AMPL_WIDTH),
conv_std_logic_vector(8454,AMPL_WIDTH),
conv_std_logic_vector(8457,AMPL_WIDTH),
conv_std_logic_vector(8460,AMPL_WIDTH),
conv_std_logic_vector(8464,AMPL_WIDTH),
conv_std_logic_vector(8467,AMPL_WIDTH),
conv_std_logic_vector(8470,AMPL_WIDTH),
conv_std_logic_vector(8473,AMPL_WIDTH),
conv_std_logic_vector(8476,AMPL_WIDTH),
conv_std_logic_vector(8479,AMPL_WIDTH),
conv_std_logic_vector(8482,AMPL_WIDTH),
conv_std_logic_vector(8485,AMPL_WIDTH),
conv_std_logic_vector(8488,AMPL_WIDTH),
conv_std_logic_vector(8491,AMPL_WIDTH),
conv_std_logic_vector(8494,AMPL_WIDTH),
conv_std_logic_vector(8497,AMPL_WIDTH),
conv_std_logic_vector(8500,AMPL_WIDTH),
conv_std_logic_vector(8503,AMPL_WIDTH),
conv_std_logic_vector(8506,AMPL_WIDTH),
conv_std_logic_vector(8509,AMPL_WIDTH),
conv_std_logic_vector(8512,AMPL_WIDTH),
conv_std_logic_vector(8515,AMPL_WIDTH),
conv_std_logic_vector(8518,AMPL_WIDTH),
conv_std_logic_vector(8521,AMPL_WIDTH),
conv_std_logic_vector(8524,AMPL_WIDTH),
conv_std_logic_vector(8527,AMPL_WIDTH),
conv_std_logic_vector(8530,AMPL_WIDTH),
conv_std_logic_vector(8533,AMPL_WIDTH),
conv_std_logic_vector(8536,AMPL_WIDTH),
conv_std_logic_vector(8539,AMPL_WIDTH),
conv_std_logic_vector(8542,AMPL_WIDTH),
conv_std_logic_vector(8545,AMPL_WIDTH),
conv_std_logic_vector(8548,AMPL_WIDTH),
conv_std_logic_vector(8552,AMPL_WIDTH),
conv_std_logic_vector(8555,AMPL_WIDTH),
conv_std_logic_vector(8558,AMPL_WIDTH),
conv_std_logic_vector(8561,AMPL_WIDTH),
conv_std_logic_vector(8564,AMPL_WIDTH),
conv_std_logic_vector(8567,AMPL_WIDTH),
conv_std_logic_vector(8570,AMPL_WIDTH),
conv_std_logic_vector(8573,AMPL_WIDTH),
conv_std_logic_vector(8576,AMPL_WIDTH),
conv_std_logic_vector(8579,AMPL_WIDTH),
conv_std_logic_vector(8582,AMPL_WIDTH),
conv_std_logic_vector(8585,AMPL_WIDTH),
conv_std_logic_vector(8588,AMPL_WIDTH),
conv_std_logic_vector(8591,AMPL_WIDTH),
conv_std_logic_vector(8594,AMPL_WIDTH),
conv_std_logic_vector(8597,AMPL_WIDTH),
conv_std_logic_vector(8600,AMPL_WIDTH),
conv_std_logic_vector(8603,AMPL_WIDTH),
conv_std_logic_vector(8606,AMPL_WIDTH),
conv_std_logic_vector(8609,AMPL_WIDTH),
conv_std_logic_vector(8612,AMPL_WIDTH),
conv_std_logic_vector(8615,AMPL_WIDTH),
conv_std_logic_vector(8618,AMPL_WIDTH),
conv_std_logic_vector(8621,AMPL_WIDTH),
conv_std_logic_vector(8624,AMPL_WIDTH),
conv_std_logic_vector(8627,AMPL_WIDTH),
conv_std_logic_vector(8630,AMPL_WIDTH),
conv_std_logic_vector(8633,AMPL_WIDTH),
conv_std_logic_vector(8636,AMPL_WIDTH),
conv_std_logic_vector(8639,AMPL_WIDTH),
conv_std_logic_vector(8642,AMPL_WIDTH),
conv_std_logic_vector(8645,AMPL_WIDTH),
conv_std_logic_vector(8649,AMPL_WIDTH),
conv_std_logic_vector(8652,AMPL_WIDTH),
conv_std_logic_vector(8655,AMPL_WIDTH),
conv_std_logic_vector(8658,AMPL_WIDTH),
conv_std_logic_vector(8661,AMPL_WIDTH),
conv_std_logic_vector(8664,AMPL_WIDTH),
conv_std_logic_vector(8667,AMPL_WIDTH),
conv_std_logic_vector(8670,AMPL_WIDTH),
conv_std_logic_vector(8673,AMPL_WIDTH),
conv_std_logic_vector(8676,AMPL_WIDTH),
conv_std_logic_vector(8679,AMPL_WIDTH),
conv_std_logic_vector(8682,AMPL_WIDTH),
conv_std_logic_vector(8685,AMPL_WIDTH),
conv_std_logic_vector(8688,AMPL_WIDTH),
conv_std_logic_vector(8691,AMPL_WIDTH),
conv_std_logic_vector(8694,AMPL_WIDTH),
conv_std_logic_vector(8697,AMPL_WIDTH),
conv_std_logic_vector(8700,AMPL_WIDTH),
conv_std_logic_vector(8703,AMPL_WIDTH),
conv_std_logic_vector(8706,AMPL_WIDTH),
conv_std_logic_vector(8709,AMPL_WIDTH),
conv_std_logic_vector(8712,AMPL_WIDTH),
conv_std_logic_vector(8715,AMPL_WIDTH),
conv_std_logic_vector(8718,AMPL_WIDTH),
conv_std_logic_vector(8721,AMPL_WIDTH),
conv_std_logic_vector(8724,AMPL_WIDTH),
conv_std_logic_vector(8727,AMPL_WIDTH),
conv_std_logic_vector(8730,AMPL_WIDTH),
conv_std_logic_vector(8733,AMPL_WIDTH),
conv_std_logic_vector(8736,AMPL_WIDTH),
conv_std_logic_vector(8739,AMPL_WIDTH),
conv_std_logic_vector(8742,AMPL_WIDTH),
conv_std_logic_vector(8745,AMPL_WIDTH),
conv_std_logic_vector(8748,AMPL_WIDTH),
conv_std_logic_vector(8751,AMPL_WIDTH),
conv_std_logic_vector(8755,AMPL_WIDTH),
conv_std_logic_vector(8758,AMPL_WIDTH),
conv_std_logic_vector(8761,AMPL_WIDTH),
conv_std_logic_vector(8764,AMPL_WIDTH),
conv_std_logic_vector(8767,AMPL_WIDTH),
conv_std_logic_vector(8770,AMPL_WIDTH),
conv_std_logic_vector(8773,AMPL_WIDTH),
conv_std_logic_vector(8776,AMPL_WIDTH),
conv_std_logic_vector(8779,AMPL_WIDTH),
conv_std_logic_vector(8782,AMPL_WIDTH),
conv_std_logic_vector(8785,AMPL_WIDTH),
conv_std_logic_vector(8788,AMPL_WIDTH),
conv_std_logic_vector(8791,AMPL_WIDTH),
conv_std_logic_vector(8794,AMPL_WIDTH),
conv_std_logic_vector(8797,AMPL_WIDTH),
conv_std_logic_vector(8800,AMPL_WIDTH),
conv_std_logic_vector(8803,AMPL_WIDTH),
conv_std_logic_vector(8806,AMPL_WIDTH),
conv_std_logic_vector(8809,AMPL_WIDTH),
conv_std_logic_vector(8812,AMPL_WIDTH),
conv_std_logic_vector(8815,AMPL_WIDTH),
conv_std_logic_vector(8818,AMPL_WIDTH),
conv_std_logic_vector(8821,AMPL_WIDTH),
conv_std_logic_vector(8824,AMPL_WIDTH),
conv_std_logic_vector(8827,AMPL_WIDTH),
conv_std_logic_vector(8830,AMPL_WIDTH),
conv_std_logic_vector(8833,AMPL_WIDTH),
conv_std_logic_vector(8836,AMPL_WIDTH),
conv_std_logic_vector(8839,AMPL_WIDTH),
conv_std_logic_vector(8842,AMPL_WIDTH),
conv_std_logic_vector(8845,AMPL_WIDTH),
conv_std_logic_vector(8848,AMPL_WIDTH),
conv_std_logic_vector(8851,AMPL_WIDTH),
conv_std_logic_vector(8854,AMPL_WIDTH),
conv_std_logic_vector(8857,AMPL_WIDTH),
conv_std_logic_vector(8860,AMPL_WIDTH),
conv_std_logic_vector(8863,AMPL_WIDTH),
conv_std_logic_vector(8866,AMPL_WIDTH),
conv_std_logic_vector(8869,AMPL_WIDTH),
conv_std_logic_vector(8873,AMPL_WIDTH),
conv_std_logic_vector(8876,AMPL_WIDTH),
conv_std_logic_vector(8879,AMPL_WIDTH),
conv_std_logic_vector(8882,AMPL_WIDTH),
conv_std_logic_vector(8885,AMPL_WIDTH),
conv_std_logic_vector(8888,AMPL_WIDTH),
conv_std_logic_vector(8891,AMPL_WIDTH),
conv_std_logic_vector(8894,AMPL_WIDTH),
conv_std_logic_vector(8897,AMPL_WIDTH),
conv_std_logic_vector(8900,AMPL_WIDTH),
conv_std_logic_vector(8903,AMPL_WIDTH),
conv_std_logic_vector(8906,AMPL_WIDTH),
conv_std_logic_vector(8909,AMPL_WIDTH),
conv_std_logic_vector(8912,AMPL_WIDTH),
conv_std_logic_vector(8915,AMPL_WIDTH),
conv_std_logic_vector(8918,AMPL_WIDTH),
conv_std_logic_vector(8921,AMPL_WIDTH),
conv_std_logic_vector(8924,AMPL_WIDTH),
conv_std_logic_vector(8927,AMPL_WIDTH),
conv_std_logic_vector(8930,AMPL_WIDTH),
conv_std_logic_vector(8933,AMPL_WIDTH),
conv_std_logic_vector(8936,AMPL_WIDTH),
conv_std_logic_vector(8939,AMPL_WIDTH),
conv_std_logic_vector(8942,AMPL_WIDTH),
conv_std_logic_vector(8945,AMPL_WIDTH),
conv_std_logic_vector(8948,AMPL_WIDTH),
conv_std_logic_vector(8951,AMPL_WIDTH),
conv_std_logic_vector(8954,AMPL_WIDTH),
conv_std_logic_vector(8957,AMPL_WIDTH),
conv_std_logic_vector(8960,AMPL_WIDTH),
conv_std_logic_vector(8963,AMPL_WIDTH),
conv_std_logic_vector(8966,AMPL_WIDTH),
conv_std_logic_vector(8969,AMPL_WIDTH),
conv_std_logic_vector(8972,AMPL_WIDTH),
conv_std_logic_vector(8975,AMPL_WIDTH),
conv_std_logic_vector(8978,AMPL_WIDTH),
conv_std_logic_vector(8981,AMPL_WIDTH),
conv_std_logic_vector(8984,AMPL_WIDTH),
conv_std_logic_vector(8987,AMPL_WIDTH),
conv_std_logic_vector(8990,AMPL_WIDTH),
conv_std_logic_vector(8993,AMPL_WIDTH),
conv_std_logic_vector(8996,AMPL_WIDTH),
conv_std_logic_vector(8999,AMPL_WIDTH),
conv_std_logic_vector(9002,AMPL_WIDTH),
conv_std_logic_vector(9006,AMPL_WIDTH),
conv_std_logic_vector(9009,AMPL_WIDTH),
conv_std_logic_vector(9012,AMPL_WIDTH),
conv_std_logic_vector(9015,AMPL_WIDTH),
conv_std_logic_vector(9018,AMPL_WIDTH),
conv_std_logic_vector(9021,AMPL_WIDTH),
conv_std_logic_vector(9024,AMPL_WIDTH),
conv_std_logic_vector(9027,AMPL_WIDTH),
conv_std_logic_vector(9030,AMPL_WIDTH),
conv_std_logic_vector(9033,AMPL_WIDTH),
conv_std_logic_vector(9036,AMPL_WIDTH),
conv_std_logic_vector(9039,AMPL_WIDTH),
conv_std_logic_vector(9042,AMPL_WIDTH),
conv_std_logic_vector(9045,AMPL_WIDTH),
conv_std_logic_vector(9048,AMPL_WIDTH),
conv_std_logic_vector(9051,AMPL_WIDTH),
conv_std_logic_vector(9054,AMPL_WIDTH),
conv_std_logic_vector(9057,AMPL_WIDTH),
conv_std_logic_vector(9060,AMPL_WIDTH),
conv_std_logic_vector(9063,AMPL_WIDTH),
conv_std_logic_vector(9066,AMPL_WIDTH),
conv_std_logic_vector(9069,AMPL_WIDTH),
conv_std_logic_vector(9072,AMPL_WIDTH),
conv_std_logic_vector(9075,AMPL_WIDTH),
conv_std_logic_vector(9078,AMPL_WIDTH),
conv_std_logic_vector(9081,AMPL_WIDTH),
conv_std_logic_vector(9084,AMPL_WIDTH),
conv_std_logic_vector(9087,AMPL_WIDTH),
conv_std_logic_vector(9090,AMPL_WIDTH),
conv_std_logic_vector(9093,AMPL_WIDTH),
conv_std_logic_vector(9096,AMPL_WIDTH),
conv_std_logic_vector(9099,AMPL_WIDTH),
conv_std_logic_vector(9102,AMPL_WIDTH),
conv_std_logic_vector(9105,AMPL_WIDTH),
conv_std_logic_vector(9108,AMPL_WIDTH),
conv_std_logic_vector(9111,AMPL_WIDTH),
conv_std_logic_vector(9114,AMPL_WIDTH),
conv_std_logic_vector(9117,AMPL_WIDTH),
conv_std_logic_vector(9120,AMPL_WIDTH),
conv_std_logic_vector(9123,AMPL_WIDTH),
conv_std_logic_vector(9126,AMPL_WIDTH),
conv_std_logic_vector(9129,AMPL_WIDTH),
conv_std_logic_vector(9132,AMPL_WIDTH),
conv_std_logic_vector(9135,AMPL_WIDTH),
conv_std_logic_vector(9138,AMPL_WIDTH),
conv_std_logic_vector(9141,AMPL_WIDTH),
conv_std_logic_vector(9144,AMPL_WIDTH),
conv_std_logic_vector(9147,AMPL_WIDTH),
conv_std_logic_vector(9150,AMPL_WIDTH),
conv_std_logic_vector(9153,AMPL_WIDTH),
conv_std_logic_vector(9156,AMPL_WIDTH),
conv_std_logic_vector(9159,AMPL_WIDTH),
conv_std_logic_vector(9162,AMPL_WIDTH),
conv_std_logic_vector(9165,AMPL_WIDTH),
conv_std_logic_vector(9168,AMPL_WIDTH),
conv_std_logic_vector(9172,AMPL_WIDTH),
conv_std_logic_vector(9175,AMPL_WIDTH),
conv_std_logic_vector(9178,AMPL_WIDTH),
conv_std_logic_vector(9181,AMPL_WIDTH),
conv_std_logic_vector(9184,AMPL_WIDTH),
conv_std_logic_vector(9187,AMPL_WIDTH),
conv_std_logic_vector(9190,AMPL_WIDTH),
conv_std_logic_vector(9193,AMPL_WIDTH),
conv_std_logic_vector(9196,AMPL_WIDTH),
conv_std_logic_vector(9199,AMPL_WIDTH),
conv_std_logic_vector(9202,AMPL_WIDTH),
conv_std_logic_vector(9205,AMPL_WIDTH),
conv_std_logic_vector(9208,AMPL_WIDTH),
conv_std_logic_vector(9211,AMPL_WIDTH),
conv_std_logic_vector(9214,AMPL_WIDTH),
conv_std_logic_vector(9217,AMPL_WIDTH),
conv_std_logic_vector(9220,AMPL_WIDTH),
conv_std_logic_vector(9223,AMPL_WIDTH),
conv_std_logic_vector(9226,AMPL_WIDTH),
conv_std_logic_vector(9229,AMPL_WIDTH),
conv_std_logic_vector(9232,AMPL_WIDTH),
conv_std_logic_vector(9235,AMPL_WIDTH),
conv_std_logic_vector(9238,AMPL_WIDTH),
conv_std_logic_vector(9241,AMPL_WIDTH),
conv_std_logic_vector(9244,AMPL_WIDTH),
conv_std_logic_vector(9247,AMPL_WIDTH),
conv_std_logic_vector(9250,AMPL_WIDTH),
conv_std_logic_vector(9253,AMPL_WIDTH),
conv_std_logic_vector(9256,AMPL_WIDTH),
conv_std_logic_vector(9259,AMPL_WIDTH),
conv_std_logic_vector(9262,AMPL_WIDTH),
conv_std_logic_vector(9265,AMPL_WIDTH),
conv_std_logic_vector(9268,AMPL_WIDTH),
conv_std_logic_vector(9271,AMPL_WIDTH),
conv_std_logic_vector(9274,AMPL_WIDTH),
conv_std_logic_vector(9277,AMPL_WIDTH),
conv_std_logic_vector(9280,AMPL_WIDTH),
conv_std_logic_vector(9283,AMPL_WIDTH),
conv_std_logic_vector(9286,AMPL_WIDTH),
conv_std_logic_vector(9289,AMPL_WIDTH),
conv_std_logic_vector(9292,AMPL_WIDTH),
conv_std_logic_vector(9295,AMPL_WIDTH),
conv_std_logic_vector(9298,AMPL_WIDTH),
conv_std_logic_vector(9301,AMPL_WIDTH),
conv_std_logic_vector(9304,AMPL_WIDTH),
conv_std_logic_vector(9307,AMPL_WIDTH),
conv_std_logic_vector(9310,AMPL_WIDTH),
conv_std_logic_vector(9313,AMPL_WIDTH),
conv_std_logic_vector(9316,AMPL_WIDTH),
conv_std_logic_vector(9319,AMPL_WIDTH),
conv_std_logic_vector(9322,AMPL_WIDTH),
conv_std_logic_vector(9325,AMPL_WIDTH),
conv_std_logic_vector(9328,AMPL_WIDTH),
conv_std_logic_vector(9331,AMPL_WIDTH),
conv_std_logic_vector(9334,AMPL_WIDTH),
conv_std_logic_vector(9337,AMPL_WIDTH),
conv_std_logic_vector(9340,AMPL_WIDTH),
conv_std_logic_vector(9343,AMPL_WIDTH),
conv_std_logic_vector(9346,AMPL_WIDTH),
conv_std_logic_vector(9349,AMPL_WIDTH),
conv_std_logic_vector(9352,AMPL_WIDTH),
conv_std_logic_vector(9355,AMPL_WIDTH),
conv_std_logic_vector(9358,AMPL_WIDTH),
conv_std_logic_vector(9361,AMPL_WIDTH),
conv_std_logic_vector(9364,AMPL_WIDTH),
conv_std_logic_vector(9367,AMPL_WIDTH),
conv_std_logic_vector(9370,AMPL_WIDTH),
conv_std_logic_vector(9373,AMPL_WIDTH),
conv_std_logic_vector(9376,AMPL_WIDTH),
conv_std_logic_vector(9379,AMPL_WIDTH),
conv_std_logic_vector(9382,AMPL_WIDTH),
conv_std_logic_vector(9385,AMPL_WIDTH),
conv_std_logic_vector(9388,AMPL_WIDTH),
conv_std_logic_vector(9391,AMPL_WIDTH),
conv_std_logic_vector(9394,AMPL_WIDTH),
conv_std_logic_vector(9397,AMPL_WIDTH),
conv_std_logic_vector(9400,AMPL_WIDTH),
conv_std_logic_vector(9403,AMPL_WIDTH),
conv_std_logic_vector(9406,AMPL_WIDTH),
conv_std_logic_vector(9409,AMPL_WIDTH),
conv_std_logic_vector(9413,AMPL_WIDTH),
conv_std_logic_vector(9416,AMPL_WIDTH),
conv_std_logic_vector(9419,AMPL_WIDTH),
conv_std_logic_vector(9422,AMPL_WIDTH),
conv_std_logic_vector(9425,AMPL_WIDTH),
conv_std_logic_vector(9428,AMPL_WIDTH),
conv_std_logic_vector(9431,AMPL_WIDTH),
conv_std_logic_vector(9434,AMPL_WIDTH),
conv_std_logic_vector(9437,AMPL_WIDTH),
conv_std_logic_vector(9440,AMPL_WIDTH),
conv_std_logic_vector(9443,AMPL_WIDTH),
conv_std_logic_vector(9446,AMPL_WIDTH),
conv_std_logic_vector(9449,AMPL_WIDTH),
conv_std_logic_vector(9452,AMPL_WIDTH),
conv_std_logic_vector(9455,AMPL_WIDTH),
conv_std_logic_vector(9458,AMPL_WIDTH),
conv_std_logic_vector(9461,AMPL_WIDTH),
conv_std_logic_vector(9464,AMPL_WIDTH),
conv_std_logic_vector(9467,AMPL_WIDTH),
conv_std_logic_vector(9470,AMPL_WIDTH),
conv_std_logic_vector(9473,AMPL_WIDTH),
conv_std_logic_vector(9476,AMPL_WIDTH),
conv_std_logic_vector(9479,AMPL_WIDTH),
conv_std_logic_vector(9482,AMPL_WIDTH),
conv_std_logic_vector(9485,AMPL_WIDTH),
conv_std_logic_vector(9488,AMPL_WIDTH),
conv_std_logic_vector(9491,AMPL_WIDTH),
conv_std_logic_vector(9494,AMPL_WIDTH),
conv_std_logic_vector(9497,AMPL_WIDTH),
conv_std_logic_vector(9500,AMPL_WIDTH),
conv_std_logic_vector(9503,AMPL_WIDTH),
conv_std_logic_vector(9506,AMPL_WIDTH),
conv_std_logic_vector(9509,AMPL_WIDTH),
conv_std_logic_vector(9512,AMPL_WIDTH),
conv_std_logic_vector(9515,AMPL_WIDTH),
conv_std_logic_vector(9518,AMPL_WIDTH),
conv_std_logic_vector(9521,AMPL_WIDTH),
conv_std_logic_vector(9524,AMPL_WIDTH),
conv_std_logic_vector(9527,AMPL_WIDTH),
conv_std_logic_vector(9530,AMPL_WIDTH),
conv_std_logic_vector(9533,AMPL_WIDTH),
conv_std_logic_vector(9536,AMPL_WIDTH),
conv_std_logic_vector(9539,AMPL_WIDTH),
conv_std_logic_vector(9542,AMPL_WIDTH),
conv_std_logic_vector(9545,AMPL_WIDTH),
conv_std_logic_vector(9548,AMPL_WIDTH),
conv_std_logic_vector(9551,AMPL_WIDTH),
conv_std_logic_vector(9554,AMPL_WIDTH),
conv_std_logic_vector(9557,AMPL_WIDTH),
conv_std_logic_vector(9560,AMPL_WIDTH),
conv_std_logic_vector(9563,AMPL_WIDTH),
conv_std_logic_vector(9566,AMPL_WIDTH),
conv_std_logic_vector(9569,AMPL_WIDTH),
conv_std_logic_vector(9572,AMPL_WIDTH),
conv_std_logic_vector(9575,AMPL_WIDTH),
conv_std_logic_vector(9578,AMPL_WIDTH),
conv_std_logic_vector(9581,AMPL_WIDTH),
conv_std_logic_vector(9584,AMPL_WIDTH),
conv_std_logic_vector(9587,AMPL_WIDTH),
conv_std_logic_vector(9590,AMPL_WIDTH),
conv_std_logic_vector(9593,AMPL_WIDTH),
conv_std_logic_vector(9596,AMPL_WIDTH),
conv_std_logic_vector(9599,AMPL_WIDTH),
conv_std_logic_vector(9602,AMPL_WIDTH),
conv_std_logic_vector(9605,AMPL_WIDTH),
conv_std_logic_vector(9608,AMPL_WIDTH),
conv_std_logic_vector(9611,AMPL_WIDTH),
conv_std_logic_vector(9614,AMPL_WIDTH),
conv_std_logic_vector(9617,AMPL_WIDTH),
conv_std_logic_vector(9620,AMPL_WIDTH),
conv_std_logic_vector(9623,AMPL_WIDTH),
conv_std_logic_vector(9626,AMPL_WIDTH),
conv_std_logic_vector(9629,AMPL_WIDTH),
conv_std_logic_vector(9632,AMPL_WIDTH),
conv_std_logic_vector(9635,AMPL_WIDTH),
conv_std_logic_vector(9638,AMPL_WIDTH),
conv_std_logic_vector(9641,AMPL_WIDTH),
conv_std_logic_vector(9644,AMPL_WIDTH),
conv_std_logic_vector(9647,AMPL_WIDTH),
conv_std_logic_vector(9650,AMPL_WIDTH),
conv_std_logic_vector(9653,AMPL_WIDTH),
conv_std_logic_vector(9656,AMPL_WIDTH),
conv_std_logic_vector(9659,AMPL_WIDTH),
conv_std_logic_vector(9662,AMPL_WIDTH),
conv_std_logic_vector(9665,AMPL_WIDTH),
conv_std_logic_vector(9668,AMPL_WIDTH),
conv_std_logic_vector(9671,AMPL_WIDTH),
conv_std_logic_vector(9674,AMPL_WIDTH),
conv_std_logic_vector(9677,AMPL_WIDTH),
conv_std_logic_vector(9680,AMPL_WIDTH),
conv_std_logic_vector(9683,AMPL_WIDTH),
conv_std_logic_vector(9686,AMPL_WIDTH),
conv_std_logic_vector(9689,AMPL_WIDTH),
conv_std_logic_vector(9692,AMPL_WIDTH),
conv_std_logic_vector(9695,AMPL_WIDTH),
conv_std_logic_vector(9698,AMPL_WIDTH),
conv_std_logic_vector(9701,AMPL_WIDTH),
conv_std_logic_vector(9704,AMPL_WIDTH),
conv_std_logic_vector(9707,AMPL_WIDTH),
conv_std_logic_vector(9710,AMPL_WIDTH),
conv_std_logic_vector(9713,AMPL_WIDTH),
conv_std_logic_vector(9716,AMPL_WIDTH),
conv_std_logic_vector(9719,AMPL_WIDTH),
conv_std_logic_vector(9722,AMPL_WIDTH),
conv_std_logic_vector(9725,AMPL_WIDTH),
conv_std_logic_vector(9728,AMPL_WIDTH),
conv_std_logic_vector(9731,AMPL_WIDTH),
conv_std_logic_vector(9734,AMPL_WIDTH),
conv_std_logic_vector(9737,AMPL_WIDTH),
conv_std_logic_vector(9740,AMPL_WIDTH),
conv_std_logic_vector(9743,AMPL_WIDTH),
conv_std_logic_vector(9746,AMPL_WIDTH),
conv_std_logic_vector(9749,AMPL_WIDTH),
conv_std_logic_vector(9752,AMPL_WIDTH),
conv_std_logic_vector(9755,AMPL_WIDTH),
conv_std_logic_vector(9758,AMPL_WIDTH),
conv_std_logic_vector(9761,AMPL_WIDTH),
conv_std_logic_vector(9764,AMPL_WIDTH),
conv_std_logic_vector(9767,AMPL_WIDTH),
conv_std_logic_vector(9770,AMPL_WIDTH),
conv_std_logic_vector(9773,AMPL_WIDTH),
conv_std_logic_vector(9776,AMPL_WIDTH),
conv_std_logic_vector(9779,AMPL_WIDTH),
conv_std_logic_vector(9782,AMPL_WIDTH),
conv_std_logic_vector(9785,AMPL_WIDTH),
conv_std_logic_vector(9788,AMPL_WIDTH),
conv_std_logic_vector(9791,AMPL_WIDTH),
conv_std_logic_vector(9794,AMPL_WIDTH),
conv_std_logic_vector(9797,AMPL_WIDTH),
conv_std_logic_vector(9800,AMPL_WIDTH),
conv_std_logic_vector(9803,AMPL_WIDTH),
conv_std_logic_vector(9806,AMPL_WIDTH),
conv_std_logic_vector(9809,AMPL_WIDTH),
conv_std_logic_vector(9812,AMPL_WIDTH),
conv_std_logic_vector(9815,AMPL_WIDTH),
conv_std_logic_vector(9818,AMPL_WIDTH),
conv_std_logic_vector(9821,AMPL_WIDTH),
conv_std_logic_vector(9824,AMPL_WIDTH),
conv_std_logic_vector(9827,AMPL_WIDTH),
conv_std_logic_vector(9830,AMPL_WIDTH),
conv_std_logic_vector(9833,AMPL_WIDTH),
conv_std_logic_vector(9836,AMPL_WIDTH),
conv_std_logic_vector(9839,AMPL_WIDTH),
conv_std_logic_vector(9842,AMPL_WIDTH),
conv_std_logic_vector(9845,AMPL_WIDTH),
conv_std_logic_vector(9848,AMPL_WIDTH),
conv_std_logic_vector(9851,AMPL_WIDTH),
conv_std_logic_vector(9854,AMPL_WIDTH),
conv_std_logic_vector(9857,AMPL_WIDTH),
conv_std_logic_vector(9860,AMPL_WIDTH),
conv_std_logic_vector(9863,AMPL_WIDTH),
conv_std_logic_vector(9866,AMPL_WIDTH),
conv_std_logic_vector(9869,AMPL_WIDTH),
conv_std_logic_vector(9872,AMPL_WIDTH),
conv_std_logic_vector(9875,AMPL_WIDTH),
conv_std_logic_vector(9878,AMPL_WIDTH),
conv_std_logic_vector(9881,AMPL_WIDTH),
conv_std_logic_vector(9884,AMPL_WIDTH),
conv_std_logic_vector(9887,AMPL_WIDTH),
conv_std_logic_vector(9890,AMPL_WIDTH),
conv_std_logic_vector(9893,AMPL_WIDTH),
conv_std_logic_vector(9896,AMPL_WIDTH),
conv_std_logic_vector(9899,AMPL_WIDTH),
conv_std_logic_vector(9902,AMPL_WIDTH),
conv_std_logic_vector(9905,AMPL_WIDTH),
conv_std_logic_vector(9908,AMPL_WIDTH),
conv_std_logic_vector(9911,AMPL_WIDTH),
conv_std_logic_vector(9914,AMPL_WIDTH),
conv_std_logic_vector(9917,AMPL_WIDTH),
conv_std_logic_vector(9920,AMPL_WIDTH),
conv_std_logic_vector(9923,AMPL_WIDTH),
conv_std_logic_vector(9926,AMPL_WIDTH),
conv_std_logic_vector(9929,AMPL_WIDTH),
conv_std_logic_vector(9932,AMPL_WIDTH),
conv_std_logic_vector(9935,AMPL_WIDTH),
conv_std_logic_vector(9938,AMPL_WIDTH),
conv_std_logic_vector(9941,AMPL_WIDTH),
conv_std_logic_vector(9944,AMPL_WIDTH),
conv_std_logic_vector(9947,AMPL_WIDTH),
conv_std_logic_vector(9950,AMPL_WIDTH),
conv_std_logic_vector(9953,AMPL_WIDTH),
conv_std_logic_vector(9956,AMPL_WIDTH),
conv_std_logic_vector(9959,AMPL_WIDTH),
conv_std_logic_vector(9962,AMPL_WIDTH),
conv_std_logic_vector(9965,AMPL_WIDTH),
conv_std_logic_vector(9968,AMPL_WIDTH),
conv_std_logic_vector(9971,AMPL_WIDTH),
conv_std_logic_vector(9974,AMPL_WIDTH),
conv_std_logic_vector(9977,AMPL_WIDTH),
conv_std_logic_vector(9980,AMPL_WIDTH),
conv_std_logic_vector(9983,AMPL_WIDTH),
conv_std_logic_vector(9986,AMPL_WIDTH),
conv_std_logic_vector(9989,AMPL_WIDTH),
conv_std_logic_vector(9992,AMPL_WIDTH),
conv_std_logic_vector(9995,AMPL_WIDTH),
conv_std_logic_vector(9998,AMPL_WIDTH),
conv_std_logic_vector(10001,AMPL_WIDTH),
conv_std_logic_vector(10004,AMPL_WIDTH),
conv_std_logic_vector(10007,AMPL_WIDTH),
conv_std_logic_vector(10010,AMPL_WIDTH),
conv_std_logic_vector(10013,AMPL_WIDTH),
conv_std_logic_vector(10016,AMPL_WIDTH),
conv_std_logic_vector(10019,AMPL_WIDTH),
conv_std_logic_vector(10022,AMPL_WIDTH),
conv_std_logic_vector(10025,AMPL_WIDTH),
conv_std_logic_vector(10028,AMPL_WIDTH),
conv_std_logic_vector(10031,AMPL_WIDTH),
conv_std_logic_vector(10033,AMPL_WIDTH),
conv_std_logic_vector(10036,AMPL_WIDTH),
conv_std_logic_vector(10039,AMPL_WIDTH),
conv_std_logic_vector(10042,AMPL_WIDTH),
conv_std_logic_vector(10045,AMPL_WIDTH),
conv_std_logic_vector(10048,AMPL_WIDTH),
conv_std_logic_vector(10051,AMPL_WIDTH),
conv_std_logic_vector(10054,AMPL_WIDTH),
conv_std_logic_vector(10057,AMPL_WIDTH),
conv_std_logic_vector(10060,AMPL_WIDTH),
conv_std_logic_vector(10063,AMPL_WIDTH),
conv_std_logic_vector(10066,AMPL_WIDTH),
conv_std_logic_vector(10069,AMPL_WIDTH),
conv_std_logic_vector(10072,AMPL_WIDTH),
conv_std_logic_vector(10075,AMPL_WIDTH),
conv_std_logic_vector(10078,AMPL_WIDTH),
conv_std_logic_vector(10081,AMPL_WIDTH),
conv_std_logic_vector(10084,AMPL_WIDTH),
conv_std_logic_vector(10087,AMPL_WIDTH),
conv_std_logic_vector(10090,AMPL_WIDTH),
conv_std_logic_vector(10093,AMPL_WIDTH),
conv_std_logic_vector(10096,AMPL_WIDTH),
conv_std_logic_vector(10099,AMPL_WIDTH),
conv_std_logic_vector(10102,AMPL_WIDTH),
conv_std_logic_vector(10105,AMPL_WIDTH),
conv_std_logic_vector(10108,AMPL_WIDTH),
conv_std_logic_vector(10111,AMPL_WIDTH),
conv_std_logic_vector(10114,AMPL_WIDTH),
conv_std_logic_vector(10117,AMPL_WIDTH),
conv_std_logic_vector(10120,AMPL_WIDTH),
conv_std_logic_vector(10123,AMPL_WIDTH),
conv_std_logic_vector(10126,AMPL_WIDTH),
conv_std_logic_vector(10129,AMPL_WIDTH),
conv_std_logic_vector(10132,AMPL_WIDTH),
conv_std_logic_vector(10135,AMPL_WIDTH),
conv_std_logic_vector(10138,AMPL_WIDTH),
conv_std_logic_vector(10141,AMPL_WIDTH),
conv_std_logic_vector(10144,AMPL_WIDTH),
conv_std_logic_vector(10147,AMPL_WIDTH),
conv_std_logic_vector(10150,AMPL_WIDTH),
conv_std_logic_vector(10153,AMPL_WIDTH),
conv_std_logic_vector(10156,AMPL_WIDTH),
conv_std_logic_vector(10159,AMPL_WIDTH),
conv_std_logic_vector(10162,AMPL_WIDTH),
conv_std_logic_vector(10165,AMPL_WIDTH),
conv_std_logic_vector(10168,AMPL_WIDTH),
conv_std_logic_vector(10171,AMPL_WIDTH),
conv_std_logic_vector(10174,AMPL_WIDTH),
conv_std_logic_vector(10177,AMPL_WIDTH),
conv_std_logic_vector(10180,AMPL_WIDTH),
conv_std_logic_vector(10183,AMPL_WIDTH),
conv_std_logic_vector(10186,AMPL_WIDTH),
conv_std_logic_vector(10189,AMPL_WIDTH),
conv_std_logic_vector(10192,AMPL_WIDTH),
conv_std_logic_vector(10195,AMPL_WIDTH),
conv_std_logic_vector(10198,AMPL_WIDTH),
conv_std_logic_vector(10201,AMPL_WIDTH),
conv_std_logic_vector(10204,AMPL_WIDTH),
conv_std_logic_vector(10207,AMPL_WIDTH),
conv_std_logic_vector(10210,AMPL_WIDTH),
conv_std_logic_vector(10213,AMPL_WIDTH),
conv_std_logic_vector(10216,AMPL_WIDTH),
conv_std_logic_vector(10219,AMPL_WIDTH),
conv_std_logic_vector(10222,AMPL_WIDTH),
conv_std_logic_vector(10225,AMPL_WIDTH),
conv_std_logic_vector(10228,AMPL_WIDTH),
conv_std_logic_vector(10231,AMPL_WIDTH),
conv_std_logic_vector(10234,AMPL_WIDTH),
conv_std_logic_vector(10237,AMPL_WIDTH),
conv_std_logic_vector(10240,AMPL_WIDTH),
conv_std_logic_vector(10243,AMPL_WIDTH),
conv_std_logic_vector(10246,AMPL_WIDTH),
conv_std_logic_vector(10249,AMPL_WIDTH),
conv_std_logic_vector(10252,AMPL_WIDTH),
conv_std_logic_vector(10255,AMPL_WIDTH),
conv_std_logic_vector(10258,AMPL_WIDTH),
conv_std_logic_vector(10261,AMPL_WIDTH),
conv_std_logic_vector(10263,AMPL_WIDTH),
conv_std_logic_vector(10266,AMPL_WIDTH),
conv_std_logic_vector(10269,AMPL_WIDTH),
conv_std_logic_vector(10272,AMPL_WIDTH),
conv_std_logic_vector(10275,AMPL_WIDTH),
conv_std_logic_vector(10278,AMPL_WIDTH),
conv_std_logic_vector(10281,AMPL_WIDTH),
conv_std_logic_vector(10284,AMPL_WIDTH),
conv_std_logic_vector(10287,AMPL_WIDTH),
conv_std_logic_vector(10290,AMPL_WIDTH),
conv_std_logic_vector(10293,AMPL_WIDTH),
conv_std_logic_vector(10296,AMPL_WIDTH),
conv_std_logic_vector(10299,AMPL_WIDTH),
conv_std_logic_vector(10302,AMPL_WIDTH),
conv_std_logic_vector(10305,AMPL_WIDTH),
conv_std_logic_vector(10308,AMPL_WIDTH),
conv_std_logic_vector(10311,AMPL_WIDTH),
conv_std_logic_vector(10314,AMPL_WIDTH),
conv_std_logic_vector(10317,AMPL_WIDTH),
conv_std_logic_vector(10320,AMPL_WIDTH),
conv_std_logic_vector(10323,AMPL_WIDTH),
conv_std_logic_vector(10326,AMPL_WIDTH),
conv_std_logic_vector(10329,AMPL_WIDTH),
conv_std_logic_vector(10332,AMPL_WIDTH),
conv_std_logic_vector(10335,AMPL_WIDTH),
conv_std_logic_vector(10338,AMPL_WIDTH),
conv_std_logic_vector(10341,AMPL_WIDTH),
conv_std_logic_vector(10344,AMPL_WIDTH),
conv_std_logic_vector(10347,AMPL_WIDTH),
conv_std_logic_vector(10350,AMPL_WIDTH),
conv_std_logic_vector(10353,AMPL_WIDTH),
conv_std_logic_vector(10356,AMPL_WIDTH),
conv_std_logic_vector(10359,AMPL_WIDTH),
conv_std_logic_vector(10362,AMPL_WIDTH),
conv_std_logic_vector(10365,AMPL_WIDTH),
conv_std_logic_vector(10368,AMPL_WIDTH),
conv_std_logic_vector(10371,AMPL_WIDTH),
conv_std_logic_vector(10374,AMPL_WIDTH),
conv_std_logic_vector(10377,AMPL_WIDTH),
conv_std_logic_vector(10380,AMPL_WIDTH),
conv_std_logic_vector(10383,AMPL_WIDTH),
conv_std_logic_vector(10386,AMPL_WIDTH),
conv_std_logic_vector(10389,AMPL_WIDTH),
conv_std_logic_vector(10392,AMPL_WIDTH),
conv_std_logic_vector(10395,AMPL_WIDTH),
conv_std_logic_vector(10398,AMPL_WIDTH),
conv_std_logic_vector(10401,AMPL_WIDTH),
conv_std_logic_vector(10404,AMPL_WIDTH),
conv_std_logic_vector(10407,AMPL_WIDTH),
conv_std_logic_vector(10410,AMPL_WIDTH),
conv_std_logic_vector(10413,AMPL_WIDTH),
conv_std_logic_vector(10416,AMPL_WIDTH),
conv_std_logic_vector(10419,AMPL_WIDTH),
conv_std_logic_vector(10421,AMPL_WIDTH),
conv_std_logic_vector(10424,AMPL_WIDTH),
conv_std_logic_vector(10427,AMPL_WIDTH),
conv_std_logic_vector(10430,AMPL_WIDTH),
conv_std_logic_vector(10433,AMPL_WIDTH),
conv_std_logic_vector(10436,AMPL_WIDTH),
conv_std_logic_vector(10439,AMPL_WIDTH),
conv_std_logic_vector(10442,AMPL_WIDTH),
conv_std_logic_vector(10445,AMPL_WIDTH),
conv_std_logic_vector(10448,AMPL_WIDTH),
conv_std_logic_vector(10451,AMPL_WIDTH),
conv_std_logic_vector(10454,AMPL_WIDTH),
conv_std_logic_vector(10457,AMPL_WIDTH),
conv_std_logic_vector(10460,AMPL_WIDTH),
conv_std_logic_vector(10463,AMPL_WIDTH),
conv_std_logic_vector(10466,AMPL_WIDTH),
conv_std_logic_vector(10469,AMPL_WIDTH),
conv_std_logic_vector(10472,AMPL_WIDTH),
conv_std_logic_vector(10475,AMPL_WIDTH),
conv_std_logic_vector(10478,AMPL_WIDTH),
conv_std_logic_vector(10481,AMPL_WIDTH),
conv_std_logic_vector(10484,AMPL_WIDTH),
conv_std_logic_vector(10487,AMPL_WIDTH),
conv_std_logic_vector(10490,AMPL_WIDTH),
conv_std_logic_vector(10493,AMPL_WIDTH),
conv_std_logic_vector(10496,AMPL_WIDTH),
conv_std_logic_vector(10499,AMPL_WIDTH),
conv_std_logic_vector(10502,AMPL_WIDTH),
conv_std_logic_vector(10505,AMPL_WIDTH),
conv_std_logic_vector(10508,AMPL_WIDTH),
conv_std_logic_vector(10511,AMPL_WIDTH),
conv_std_logic_vector(10514,AMPL_WIDTH),
conv_std_logic_vector(10517,AMPL_WIDTH),
conv_std_logic_vector(10520,AMPL_WIDTH),
conv_std_logic_vector(10523,AMPL_WIDTH),
conv_std_logic_vector(10526,AMPL_WIDTH),
conv_std_logic_vector(10529,AMPL_WIDTH),
conv_std_logic_vector(10532,AMPL_WIDTH),
conv_std_logic_vector(10535,AMPL_WIDTH),
conv_std_logic_vector(10538,AMPL_WIDTH),
conv_std_logic_vector(10541,AMPL_WIDTH),
conv_std_logic_vector(10544,AMPL_WIDTH),
conv_std_logic_vector(10546,AMPL_WIDTH),
conv_std_logic_vector(10549,AMPL_WIDTH),
conv_std_logic_vector(10552,AMPL_WIDTH),
conv_std_logic_vector(10555,AMPL_WIDTH),
conv_std_logic_vector(10558,AMPL_WIDTH),
conv_std_logic_vector(10561,AMPL_WIDTH),
conv_std_logic_vector(10564,AMPL_WIDTH),
conv_std_logic_vector(10567,AMPL_WIDTH),
conv_std_logic_vector(10570,AMPL_WIDTH),
conv_std_logic_vector(10573,AMPL_WIDTH),
conv_std_logic_vector(10576,AMPL_WIDTH),
conv_std_logic_vector(10579,AMPL_WIDTH),
conv_std_logic_vector(10582,AMPL_WIDTH),
conv_std_logic_vector(10585,AMPL_WIDTH),
conv_std_logic_vector(10588,AMPL_WIDTH),
conv_std_logic_vector(10591,AMPL_WIDTH),
conv_std_logic_vector(10594,AMPL_WIDTH),
conv_std_logic_vector(10597,AMPL_WIDTH),
conv_std_logic_vector(10600,AMPL_WIDTH),
conv_std_logic_vector(10603,AMPL_WIDTH),
conv_std_logic_vector(10606,AMPL_WIDTH),
conv_std_logic_vector(10609,AMPL_WIDTH),
conv_std_logic_vector(10612,AMPL_WIDTH),
conv_std_logic_vector(10615,AMPL_WIDTH),
conv_std_logic_vector(10618,AMPL_WIDTH),
conv_std_logic_vector(10621,AMPL_WIDTH),
conv_std_logic_vector(10624,AMPL_WIDTH),
conv_std_logic_vector(10627,AMPL_WIDTH),
conv_std_logic_vector(10630,AMPL_WIDTH),
conv_std_logic_vector(10633,AMPL_WIDTH),
conv_std_logic_vector(10636,AMPL_WIDTH),
conv_std_logic_vector(10639,AMPL_WIDTH),
conv_std_logic_vector(10642,AMPL_WIDTH),
conv_std_logic_vector(10645,AMPL_WIDTH),
conv_std_logic_vector(10648,AMPL_WIDTH),
conv_std_logic_vector(10651,AMPL_WIDTH),
conv_std_logic_vector(10654,AMPL_WIDTH),
conv_std_logic_vector(10656,AMPL_WIDTH),
conv_std_logic_vector(10659,AMPL_WIDTH),
conv_std_logic_vector(10662,AMPL_WIDTH),
conv_std_logic_vector(10665,AMPL_WIDTH),
conv_std_logic_vector(10668,AMPL_WIDTH),
conv_std_logic_vector(10671,AMPL_WIDTH),
conv_std_logic_vector(10674,AMPL_WIDTH),
conv_std_logic_vector(10677,AMPL_WIDTH),
conv_std_logic_vector(10680,AMPL_WIDTH),
conv_std_logic_vector(10683,AMPL_WIDTH),
conv_std_logic_vector(10686,AMPL_WIDTH),
conv_std_logic_vector(10689,AMPL_WIDTH),
conv_std_logic_vector(10692,AMPL_WIDTH),
conv_std_logic_vector(10695,AMPL_WIDTH),
conv_std_logic_vector(10698,AMPL_WIDTH),
conv_std_logic_vector(10701,AMPL_WIDTH),
conv_std_logic_vector(10704,AMPL_WIDTH),
conv_std_logic_vector(10707,AMPL_WIDTH),
conv_std_logic_vector(10710,AMPL_WIDTH),
conv_std_logic_vector(10713,AMPL_WIDTH),
conv_std_logic_vector(10716,AMPL_WIDTH),
conv_std_logic_vector(10719,AMPL_WIDTH),
conv_std_logic_vector(10722,AMPL_WIDTH),
conv_std_logic_vector(10725,AMPL_WIDTH),
conv_std_logic_vector(10728,AMPL_WIDTH),
conv_std_logic_vector(10731,AMPL_WIDTH),
conv_std_logic_vector(10734,AMPL_WIDTH),
conv_std_logic_vector(10737,AMPL_WIDTH),
conv_std_logic_vector(10740,AMPL_WIDTH),
conv_std_logic_vector(10743,AMPL_WIDTH),
conv_std_logic_vector(10746,AMPL_WIDTH),
conv_std_logic_vector(10749,AMPL_WIDTH),
conv_std_logic_vector(10751,AMPL_WIDTH),
conv_std_logic_vector(10754,AMPL_WIDTH),
conv_std_logic_vector(10757,AMPL_WIDTH),
conv_std_logic_vector(10760,AMPL_WIDTH),
conv_std_logic_vector(10763,AMPL_WIDTH),
conv_std_logic_vector(10766,AMPL_WIDTH),
conv_std_logic_vector(10769,AMPL_WIDTH),
conv_std_logic_vector(10772,AMPL_WIDTH),
conv_std_logic_vector(10775,AMPL_WIDTH),
conv_std_logic_vector(10778,AMPL_WIDTH),
conv_std_logic_vector(10781,AMPL_WIDTH),
conv_std_logic_vector(10784,AMPL_WIDTH),
conv_std_logic_vector(10787,AMPL_WIDTH),
conv_std_logic_vector(10790,AMPL_WIDTH),
conv_std_logic_vector(10793,AMPL_WIDTH),
conv_std_logic_vector(10796,AMPL_WIDTH),
conv_std_logic_vector(10799,AMPL_WIDTH),
conv_std_logic_vector(10802,AMPL_WIDTH),
conv_std_logic_vector(10805,AMPL_WIDTH),
conv_std_logic_vector(10808,AMPL_WIDTH),
conv_std_logic_vector(10811,AMPL_WIDTH),
conv_std_logic_vector(10814,AMPL_WIDTH),
conv_std_logic_vector(10817,AMPL_WIDTH),
conv_std_logic_vector(10820,AMPL_WIDTH),
conv_std_logic_vector(10823,AMPL_WIDTH),
conv_std_logic_vector(10826,AMPL_WIDTH),
conv_std_logic_vector(10829,AMPL_WIDTH),
conv_std_logic_vector(10832,AMPL_WIDTH),
conv_std_logic_vector(10835,AMPL_WIDTH),
conv_std_logic_vector(10838,AMPL_WIDTH),
conv_std_logic_vector(10840,AMPL_WIDTH),
conv_std_logic_vector(10843,AMPL_WIDTH),
conv_std_logic_vector(10846,AMPL_WIDTH),
conv_std_logic_vector(10849,AMPL_WIDTH),
conv_std_logic_vector(10852,AMPL_WIDTH),
conv_std_logic_vector(10855,AMPL_WIDTH),
conv_std_logic_vector(10858,AMPL_WIDTH),
conv_std_logic_vector(10861,AMPL_WIDTH),
conv_std_logic_vector(10864,AMPL_WIDTH),
conv_std_logic_vector(10867,AMPL_WIDTH),
conv_std_logic_vector(10870,AMPL_WIDTH),
conv_std_logic_vector(10873,AMPL_WIDTH),
conv_std_logic_vector(10876,AMPL_WIDTH),
conv_std_logic_vector(10879,AMPL_WIDTH),
conv_std_logic_vector(10882,AMPL_WIDTH),
conv_std_logic_vector(10885,AMPL_WIDTH),
conv_std_logic_vector(10888,AMPL_WIDTH),
conv_std_logic_vector(10891,AMPL_WIDTH),
conv_std_logic_vector(10894,AMPL_WIDTH),
conv_std_logic_vector(10897,AMPL_WIDTH),
conv_std_logic_vector(10900,AMPL_WIDTH),
conv_std_logic_vector(10903,AMPL_WIDTH),
conv_std_logic_vector(10906,AMPL_WIDTH),
conv_std_logic_vector(10909,AMPL_WIDTH),
conv_std_logic_vector(10912,AMPL_WIDTH),
conv_std_logic_vector(10915,AMPL_WIDTH),
conv_std_logic_vector(10918,AMPL_WIDTH),
conv_std_logic_vector(10920,AMPL_WIDTH),
conv_std_logic_vector(10923,AMPL_WIDTH),
conv_std_logic_vector(10926,AMPL_WIDTH),
conv_std_logic_vector(10929,AMPL_WIDTH),
conv_std_logic_vector(10932,AMPL_WIDTH),
conv_std_logic_vector(10935,AMPL_WIDTH),
conv_std_logic_vector(10938,AMPL_WIDTH),
conv_std_logic_vector(10941,AMPL_WIDTH),
conv_std_logic_vector(10944,AMPL_WIDTH),
conv_std_logic_vector(10947,AMPL_WIDTH),
conv_std_logic_vector(10950,AMPL_WIDTH),
conv_std_logic_vector(10953,AMPL_WIDTH),
conv_std_logic_vector(10956,AMPL_WIDTH),
conv_std_logic_vector(10959,AMPL_WIDTH),
conv_std_logic_vector(10962,AMPL_WIDTH),
conv_std_logic_vector(10965,AMPL_WIDTH),
conv_std_logic_vector(10968,AMPL_WIDTH),
conv_std_logic_vector(10971,AMPL_WIDTH),
conv_std_logic_vector(10974,AMPL_WIDTH),
conv_std_logic_vector(10977,AMPL_WIDTH),
conv_std_logic_vector(10980,AMPL_WIDTH),
conv_std_logic_vector(10983,AMPL_WIDTH),
conv_std_logic_vector(10986,AMPL_WIDTH),
conv_std_logic_vector(10989,AMPL_WIDTH),
conv_std_logic_vector(10992,AMPL_WIDTH),
conv_std_logic_vector(10994,AMPL_WIDTH),
conv_std_logic_vector(10997,AMPL_WIDTH),
conv_std_logic_vector(11000,AMPL_WIDTH),
conv_std_logic_vector(11003,AMPL_WIDTH),
conv_std_logic_vector(11006,AMPL_WIDTH),
conv_std_logic_vector(11009,AMPL_WIDTH),
conv_std_logic_vector(11012,AMPL_WIDTH),
conv_std_logic_vector(11015,AMPL_WIDTH),
conv_std_logic_vector(11018,AMPL_WIDTH),
conv_std_logic_vector(11021,AMPL_WIDTH),
conv_std_logic_vector(11024,AMPL_WIDTH),
conv_std_logic_vector(11027,AMPL_WIDTH),
conv_std_logic_vector(11030,AMPL_WIDTH),
conv_std_logic_vector(11033,AMPL_WIDTH),
conv_std_logic_vector(11036,AMPL_WIDTH),
conv_std_logic_vector(11039,AMPL_WIDTH),
conv_std_logic_vector(11042,AMPL_WIDTH),
conv_std_logic_vector(11045,AMPL_WIDTH),
conv_std_logic_vector(11048,AMPL_WIDTH),
conv_std_logic_vector(11051,AMPL_WIDTH),
conv_std_logic_vector(11054,AMPL_WIDTH),
conv_std_logic_vector(11057,AMPL_WIDTH),
conv_std_logic_vector(11060,AMPL_WIDTH),
conv_std_logic_vector(11063,AMPL_WIDTH),
conv_std_logic_vector(11065,AMPL_WIDTH),
conv_std_logic_vector(11068,AMPL_WIDTH),
conv_std_logic_vector(11071,AMPL_WIDTH),
conv_std_logic_vector(11074,AMPL_WIDTH),
conv_std_logic_vector(11077,AMPL_WIDTH),
conv_std_logic_vector(11080,AMPL_WIDTH),
conv_std_logic_vector(11083,AMPL_WIDTH),
conv_std_logic_vector(11086,AMPL_WIDTH),
conv_std_logic_vector(11089,AMPL_WIDTH),
conv_std_logic_vector(11092,AMPL_WIDTH),
conv_std_logic_vector(11095,AMPL_WIDTH),
conv_std_logic_vector(11098,AMPL_WIDTH),
conv_std_logic_vector(11101,AMPL_WIDTH),
conv_std_logic_vector(11104,AMPL_WIDTH),
conv_std_logic_vector(11107,AMPL_WIDTH),
conv_std_logic_vector(11110,AMPL_WIDTH),
conv_std_logic_vector(11113,AMPL_WIDTH),
conv_std_logic_vector(11116,AMPL_WIDTH),
conv_std_logic_vector(11119,AMPL_WIDTH),
conv_std_logic_vector(11122,AMPL_WIDTH),
conv_std_logic_vector(11125,AMPL_WIDTH),
conv_std_logic_vector(11128,AMPL_WIDTH),
conv_std_logic_vector(11131,AMPL_WIDTH),
conv_std_logic_vector(11133,AMPL_WIDTH),
conv_std_logic_vector(11136,AMPL_WIDTH),
conv_std_logic_vector(11139,AMPL_WIDTH),
conv_std_logic_vector(11142,AMPL_WIDTH),
conv_std_logic_vector(11145,AMPL_WIDTH),
conv_std_logic_vector(11148,AMPL_WIDTH),
conv_std_logic_vector(11151,AMPL_WIDTH),
conv_std_logic_vector(11154,AMPL_WIDTH),
conv_std_logic_vector(11157,AMPL_WIDTH),
conv_std_logic_vector(11160,AMPL_WIDTH),
conv_std_logic_vector(11163,AMPL_WIDTH),
conv_std_logic_vector(11166,AMPL_WIDTH),
conv_std_logic_vector(11169,AMPL_WIDTH),
conv_std_logic_vector(11172,AMPL_WIDTH),
conv_std_logic_vector(11175,AMPL_WIDTH),
conv_std_logic_vector(11178,AMPL_WIDTH),
conv_std_logic_vector(11181,AMPL_WIDTH),
conv_std_logic_vector(11184,AMPL_WIDTH),
conv_std_logic_vector(11187,AMPL_WIDTH),
conv_std_logic_vector(11190,AMPL_WIDTH),
conv_std_logic_vector(11193,AMPL_WIDTH),
conv_std_logic_vector(11195,AMPL_WIDTH),
conv_std_logic_vector(11198,AMPL_WIDTH),
conv_std_logic_vector(11201,AMPL_WIDTH),
conv_std_logic_vector(11204,AMPL_WIDTH),
conv_std_logic_vector(11207,AMPL_WIDTH),
conv_std_logic_vector(11210,AMPL_WIDTH),
conv_std_logic_vector(11213,AMPL_WIDTH),
conv_std_logic_vector(11216,AMPL_WIDTH),
conv_std_logic_vector(11219,AMPL_WIDTH),
conv_std_logic_vector(11222,AMPL_WIDTH),
conv_std_logic_vector(11225,AMPL_WIDTH),
conv_std_logic_vector(11228,AMPL_WIDTH),
conv_std_logic_vector(11231,AMPL_WIDTH),
conv_std_logic_vector(11234,AMPL_WIDTH),
conv_std_logic_vector(11237,AMPL_WIDTH),
conv_std_logic_vector(11240,AMPL_WIDTH),
conv_std_logic_vector(11243,AMPL_WIDTH),
conv_std_logic_vector(11246,AMPL_WIDTH),
conv_std_logic_vector(11249,AMPL_WIDTH),
conv_std_logic_vector(11252,AMPL_WIDTH),
conv_std_logic_vector(11255,AMPL_WIDTH),
conv_std_logic_vector(11257,AMPL_WIDTH),
conv_std_logic_vector(11260,AMPL_WIDTH),
conv_std_logic_vector(11263,AMPL_WIDTH),
conv_std_logic_vector(11266,AMPL_WIDTH),
conv_std_logic_vector(11269,AMPL_WIDTH),
conv_std_logic_vector(11272,AMPL_WIDTH),
conv_std_logic_vector(11275,AMPL_WIDTH),
conv_std_logic_vector(11278,AMPL_WIDTH),
conv_std_logic_vector(11281,AMPL_WIDTH),
conv_std_logic_vector(11284,AMPL_WIDTH),
conv_std_logic_vector(11287,AMPL_WIDTH),
conv_std_logic_vector(11290,AMPL_WIDTH),
conv_std_logic_vector(11293,AMPL_WIDTH),
conv_std_logic_vector(11296,AMPL_WIDTH),
conv_std_logic_vector(11299,AMPL_WIDTH),
conv_std_logic_vector(11302,AMPL_WIDTH),
conv_std_logic_vector(11305,AMPL_WIDTH),
conv_std_logic_vector(11308,AMPL_WIDTH),
conv_std_logic_vector(11311,AMPL_WIDTH),
conv_std_logic_vector(11314,AMPL_WIDTH),
conv_std_logic_vector(11316,AMPL_WIDTH),
conv_std_logic_vector(11319,AMPL_WIDTH),
conv_std_logic_vector(11322,AMPL_WIDTH),
conv_std_logic_vector(11325,AMPL_WIDTH),
conv_std_logic_vector(11328,AMPL_WIDTH),
conv_std_logic_vector(11331,AMPL_WIDTH),
conv_std_logic_vector(11334,AMPL_WIDTH),
conv_std_logic_vector(11337,AMPL_WIDTH),
conv_std_logic_vector(11340,AMPL_WIDTH),
conv_std_logic_vector(11343,AMPL_WIDTH),
conv_std_logic_vector(11346,AMPL_WIDTH),
conv_std_logic_vector(11349,AMPL_WIDTH),
conv_std_logic_vector(11352,AMPL_WIDTH),
conv_std_logic_vector(11355,AMPL_WIDTH),
conv_std_logic_vector(11358,AMPL_WIDTH),
conv_std_logic_vector(11361,AMPL_WIDTH),
conv_std_logic_vector(11364,AMPL_WIDTH),
conv_std_logic_vector(11367,AMPL_WIDTH),
conv_std_logic_vector(11370,AMPL_WIDTH),
conv_std_logic_vector(11372,AMPL_WIDTH),
conv_std_logic_vector(11375,AMPL_WIDTH),
conv_std_logic_vector(11378,AMPL_WIDTH),
conv_std_logic_vector(11381,AMPL_WIDTH),
conv_std_logic_vector(11384,AMPL_WIDTH),
conv_std_logic_vector(11387,AMPL_WIDTH),
conv_std_logic_vector(11390,AMPL_WIDTH),
conv_std_logic_vector(11393,AMPL_WIDTH),
conv_std_logic_vector(11396,AMPL_WIDTH),
conv_std_logic_vector(11399,AMPL_WIDTH),
conv_std_logic_vector(11402,AMPL_WIDTH),
conv_std_logic_vector(11405,AMPL_WIDTH),
conv_std_logic_vector(11408,AMPL_WIDTH),
conv_std_logic_vector(11411,AMPL_WIDTH),
conv_std_logic_vector(11414,AMPL_WIDTH),
conv_std_logic_vector(11417,AMPL_WIDTH),
conv_std_logic_vector(11420,AMPL_WIDTH),
conv_std_logic_vector(11423,AMPL_WIDTH),
conv_std_logic_vector(11425,AMPL_WIDTH),
conv_std_logic_vector(11428,AMPL_WIDTH),
conv_std_logic_vector(11431,AMPL_WIDTH),
conv_std_logic_vector(11434,AMPL_WIDTH),
conv_std_logic_vector(11437,AMPL_WIDTH),
conv_std_logic_vector(11440,AMPL_WIDTH),
conv_std_logic_vector(11443,AMPL_WIDTH),
conv_std_logic_vector(11446,AMPL_WIDTH),
conv_std_logic_vector(11449,AMPL_WIDTH),
conv_std_logic_vector(11452,AMPL_WIDTH),
conv_std_logic_vector(11455,AMPL_WIDTH),
conv_std_logic_vector(11458,AMPL_WIDTH),
conv_std_logic_vector(11461,AMPL_WIDTH),
conv_std_logic_vector(11464,AMPL_WIDTH),
conv_std_logic_vector(11467,AMPL_WIDTH),
conv_std_logic_vector(11470,AMPL_WIDTH),
conv_std_logic_vector(11473,AMPL_WIDTH),
conv_std_logic_vector(11476,AMPL_WIDTH),
conv_std_logic_vector(11478,AMPL_WIDTH),
conv_std_logic_vector(11481,AMPL_WIDTH),
conv_std_logic_vector(11484,AMPL_WIDTH),
conv_std_logic_vector(11487,AMPL_WIDTH),
conv_std_logic_vector(11490,AMPL_WIDTH),
conv_std_logic_vector(11493,AMPL_WIDTH),
conv_std_logic_vector(11496,AMPL_WIDTH),
conv_std_logic_vector(11499,AMPL_WIDTH),
conv_std_logic_vector(11502,AMPL_WIDTH),
conv_std_logic_vector(11505,AMPL_WIDTH),
conv_std_logic_vector(11508,AMPL_WIDTH),
conv_std_logic_vector(11511,AMPL_WIDTH),
conv_std_logic_vector(11514,AMPL_WIDTH),
conv_std_logic_vector(11517,AMPL_WIDTH),
conv_std_logic_vector(11520,AMPL_WIDTH),
conv_std_logic_vector(11523,AMPL_WIDTH),
conv_std_logic_vector(11526,AMPL_WIDTH),
conv_std_logic_vector(11528,AMPL_WIDTH),
conv_std_logic_vector(11531,AMPL_WIDTH),
conv_std_logic_vector(11534,AMPL_WIDTH),
conv_std_logic_vector(11537,AMPL_WIDTH),
conv_std_logic_vector(11540,AMPL_WIDTH),
conv_std_logic_vector(11543,AMPL_WIDTH),
conv_std_logic_vector(11546,AMPL_WIDTH),
conv_std_logic_vector(11549,AMPL_WIDTH),
conv_std_logic_vector(11552,AMPL_WIDTH),
conv_std_logic_vector(11555,AMPL_WIDTH),
conv_std_logic_vector(11558,AMPL_WIDTH),
conv_std_logic_vector(11561,AMPL_WIDTH),
conv_std_logic_vector(11564,AMPL_WIDTH),
conv_std_logic_vector(11567,AMPL_WIDTH),
conv_std_logic_vector(11570,AMPL_WIDTH),
conv_std_logic_vector(11573,AMPL_WIDTH),
conv_std_logic_vector(11575,AMPL_WIDTH),
conv_std_logic_vector(11578,AMPL_WIDTH),
conv_std_logic_vector(11581,AMPL_WIDTH),
conv_std_logic_vector(11584,AMPL_WIDTH),
conv_std_logic_vector(11587,AMPL_WIDTH),
conv_std_logic_vector(11590,AMPL_WIDTH),
conv_std_logic_vector(11593,AMPL_WIDTH),
conv_std_logic_vector(11596,AMPL_WIDTH),
conv_std_logic_vector(11599,AMPL_WIDTH),
conv_std_logic_vector(11602,AMPL_WIDTH),
conv_std_logic_vector(11605,AMPL_WIDTH),
conv_std_logic_vector(11608,AMPL_WIDTH),
conv_std_logic_vector(11611,AMPL_WIDTH),
conv_std_logic_vector(11614,AMPL_WIDTH),
conv_std_logic_vector(11617,AMPL_WIDTH),
conv_std_logic_vector(11620,AMPL_WIDTH),
conv_std_logic_vector(11623,AMPL_WIDTH),
conv_std_logic_vector(11625,AMPL_WIDTH),
conv_std_logic_vector(11628,AMPL_WIDTH),
conv_std_logic_vector(11631,AMPL_WIDTH),
conv_std_logic_vector(11634,AMPL_WIDTH),
conv_std_logic_vector(11637,AMPL_WIDTH),
conv_std_logic_vector(11640,AMPL_WIDTH),
conv_std_logic_vector(11643,AMPL_WIDTH),
conv_std_logic_vector(11646,AMPL_WIDTH),
conv_std_logic_vector(11649,AMPL_WIDTH),
conv_std_logic_vector(11652,AMPL_WIDTH),
conv_std_logic_vector(11655,AMPL_WIDTH),
conv_std_logic_vector(11658,AMPL_WIDTH),
conv_std_logic_vector(11661,AMPL_WIDTH),
conv_std_logic_vector(11664,AMPL_WIDTH),
conv_std_logic_vector(11667,AMPL_WIDTH),
conv_std_logic_vector(11669,AMPL_WIDTH),
conv_std_logic_vector(11672,AMPL_WIDTH),
conv_std_logic_vector(11675,AMPL_WIDTH),
conv_std_logic_vector(11678,AMPL_WIDTH),
conv_std_logic_vector(11681,AMPL_WIDTH),
conv_std_logic_vector(11684,AMPL_WIDTH),
conv_std_logic_vector(11687,AMPL_WIDTH),
conv_std_logic_vector(11690,AMPL_WIDTH),
conv_std_logic_vector(11693,AMPL_WIDTH),
conv_std_logic_vector(11696,AMPL_WIDTH),
conv_std_logic_vector(11699,AMPL_WIDTH),
conv_std_logic_vector(11702,AMPL_WIDTH),
conv_std_logic_vector(11705,AMPL_WIDTH),
conv_std_logic_vector(11708,AMPL_WIDTH),
conv_std_logic_vector(11711,AMPL_WIDTH),
conv_std_logic_vector(11714,AMPL_WIDTH),
conv_std_logic_vector(11716,AMPL_WIDTH),
conv_std_logic_vector(11719,AMPL_WIDTH),
conv_std_logic_vector(11722,AMPL_WIDTH),
conv_std_logic_vector(11725,AMPL_WIDTH),
conv_std_logic_vector(11728,AMPL_WIDTH),
conv_std_logic_vector(11731,AMPL_WIDTH),
conv_std_logic_vector(11734,AMPL_WIDTH),
conv_std_logic_vector(11737,AMPL_WIDTH),
conv_std_logic_vector(11740,AMPL_WIDTH),
conv_std_logic_vector(11743,AMPL_WIDTH),
conv_std_logic_vector(11746,AMPL_WIDTH),
conv_std_logic_vector(11749,AMPL_WIDTH),
conv_std_logic_vector(11752,AMPL_WIDTH),
conv_std_logic_vector(11755,AMPL_WIDTH),
conv_std_logic_vector(11758,AMPL_WIDTH),
conv_std_logic_vector(11760,AMPL_WIDTH),
conv_std_logic_vector(11763,AMPL_WIDTH),
conv_std_logic_vector(11766,AMPL_WIDTH),
conv_std_logic_vector(11769,AMPL_WIDTH),
conv_std_logic_vector(11772,AMPL_WIDTH),
conv_std_logic_vector(11775,AMPL_WIDTH),
conv_std_logic_vector(11778,AMPL_WIDTH),
conv_std_logic_vector(11781,AMPL_WIDTH),
conv_std_logic_vector(11784,AMPL_WIDTH),
conv_std_logic_vector(11787,AMPL_WIDTH),
conv_std_logic_vector(11790,AMPL_WIDTH),
conv_std_logic_vector(11793,AMPL_WIDTH),
conv_std_logic_vector(11796,AMPL_WIDTH),
conv_std_logic_vector(11799,AMPL_WIDTH),
conv_std_logic_vector(11801,AMPL_WIDTH),
conv_std_logic_vector(11804,AMPL_WIDTH),
conv_std_logic_vector(11807,AMPL_WIDTH),
conv_std_logic_vector(11810,AMPL_WIDTH),
conv_std_logic_vector(11813,AMPL_WIDTH),
conv_std_logic_vector(11816,AMPL_WIDTH),
conv_std_logic_vector(11819,AMPL_WIDTH),
conv_std_logic_vector(11822,AMPL_WIDTH),
conv_std_logic_vector(11825,AMPL_WIDTH),
conv_std_logic_vector(11828,AMPL_WIDTH),
conv_std_logic_vector(11831,AMPL_WIDTH),
conv_std_logic_vector(11834,AMPL_WIDTH),
conv_std_logic_vector(11837,AMPL_WIDTH),
conv_std_logic_vector(11840,AMPL_WIDTH),
conv_std_logic_vector(11842,AMPL_WIDTH),
conv_std_logic_vector(11845,AMPL_WIDTH),
conv_std_logic_vector(11848,AMPL_WIDTH),
conv_std_logic_vector(11851,AMPL_WIDTH),
conv_std_logic_vector(11854,AMPL_WIDTH),
conv_std_logic_vector(11857,AMPL_WIDTH),
conv_std_logic_vector(11860,AMPL_WIDTH),
conv_std_logic_vector(11863,AMPL_WIDTH),
conv_std_logic_vector(11866,AMPL_WIDTH),
conv_std_logic_vector(11869,AMPL_WIDTH),
conv_std_logic_vector(11872,AMPL_WIDTH),
conv_std_logic_vector(11875,AMPL_WIDTH),
conv_std_logic_vector(11878,AMPL_WIDTH),
conv_std_logic_vector(11881,AMPL_WIDTH),
conv_std_logic_vector(11883,AMPL_WIDTH),
conv_std_logic_vector(11886,AMPL_WIDTH),
conv_std_logic_vector(11889,AMPL_WIDTH),
conv_std_logic_vector(11892,AMPL_WIDTH),
conv_std_logic_vector(11895,AMPL_WIDTH),
conv_std_logic_vector(11898,AMPL_WIDTH),
conv_std_logic_vector(11901,AMPL_WIDTH),
conv_std_logic_vector(11904,AMPL_WIDTH),
conv_std_logic_vector(11907,AMPL_WIDTH),
conv_std_logic_vector(11910,AMPL_WIDTH),
conv_std_logic_vector(11913,AMPL_WIDTH),
conv_std_logic_vector(11916,AMPL_WIDTH),
conv_std_logic_vector(11919,AMPL_WIDTH),
conv_std_logic_vector(11922,AMPL_WIDTH),
conv_std_logic_vector(11924,AMPL_WIDTH),
conv_std_logic_vector(11927,AMPL_WIDTH),
conv_std_logic_vector(11930,AMPL_WIDTH),
conv_std_logic_vector(11933,AMPL_WIDTH),
conv_std_logic_vector(11936,AMPL_WIDTH),
conv_std_logic_vector(11939,AMPL_WIDTH),
conv_std_logic_vector(11942,AMPL_WIDTH),
conv_std_logic_vector(11945,AMPL_WIDTH),
conv_std_logic_vector(11948,AMPL_WIDTH),
conv_std_logic_vector(11951,AMPL_WIDTH),
conv_std_logic_vector(11954,AMPL_WIDTH),
conv_std_logic_vector(11957,AMPL_WIDTH),
conv_std_logic_vector(11960,AMPL_WIDTH),
conv_std_logic_vector(11962,AMPL_WIDTH),
conv_std_logic_vector(11965,AMPL_WIDTH),
conv_std_logic_vector(11968,AMPL_WIDTH),
conv_std_logic_vector(11971,AMPL_WIDTH),
conv_std_logic_vector(11974,AMPL_WIDTH),
conv_std_logic_vector(11977,AMPL_WIDTH),
conv_std_logic_vector(11980,AMPL_WIDTH),
conv_std_logic_vector(11983,AMPL_WIDTH),
conv_std_logic_vector(11986,AMPL_WIDTH),
conv_std_logic_vector(11989,AMPL_WIDTH),
conv_std_logic_vector(11992,AMPL_WIDTH),
conv_std_logic_vector(11995,AMPL_WIDTH),
conv_std_logic_vector(11998,AMPL_WIDTH),
conv_std_logic_vector(12001,AMPL_WIDTH),
conv_std_logic_vector(12003,AMPL_WIDTH),
conv_std_logic_vector(12006,AMPL_WIDTH),
conv_std_logic_vector(12009,AMPL_WIDTH),
conv_std_logic_vector(12012,AMPL_WIDTH),
conv_std_logic_vector(12015,AMPL_WIDTH),
conv_std_logic_vector(12018,AMPL_WIDTH),
conv_std_logic_vector(12021,AMPL_WIDTH),
conv_std_logic_vector(12024,AMPL_WIDTH),
conv_std_logic_vector(12027,AMPL_WIDTH),
conv_std_logic_vector(12030,AMPL_WIDTH),
conv_std_logic_vector(12033,AMPL_WIDTH),
conv_std_logic_vector(12036,AMPL_WIDTH),
conv_std_logic_vector(12038,AMPL_WIDTH),
conv_std_logic_vector(12041,AMPL_WIDTH),
conv_std_logic_vector(12044,AMPL_WIDTH),
conv_std_logic_vector(12047,AMPL_WIDTH),
conv_std_logic_vector(12050,AMPL_WIDTH),
conv_std_logic_vector(12053,AMPL_WIDTH),
conv_std_logic_vector(12056,AMPL_WIDTH),
conv_std_logic_vector(12059,AMPL_WIDTH),
conv_std_logic_vector(12062,AMPL_WIDTH),
conv_std_logic_vector(12065,AMPL_WIDTH),
conv_std_logic_vector(12068,AMPL_WIDTH),
conv_std_logic_vector(12071,AMPL_WIDTH),
conv_std_logic_vector(12074,AMPL_WIDTH),
conv_std_logic_vector(12076,AMPL_WIDTH),
conv_std_logic_vector(12079,AMPL_WIDTH),
conv_std_logic_vector(12082,AMPL_WIDTH),
conv_std_logic_vector(12085,AMPL_WIDTH),
conv_std_logic_vector(12088,AMPL_WIDTH),
conv_std_logic_vector(12091,AMPL_WIDTH),
conv_std_logic_vector(12094,AMPL_WIDTH),
conv_std_logic_vector(12097,AMPL_WIDTH),
conv_std_logic_vector(12100,AMPL_WIDTH),
conv_std_logic_vector(12103,AMPL_WIDTH),
conv_std_logic_vector(12106,AMPL_WIDTH),
conv_std_logic_vector(12109,AMPL_WIDTH),
conv_std_logic_vector(12112,AMPL_WIDTH),
conv_std_logic_vector(12114,AMPL_WIDTH),
conv_std_logic_vector(12117,AMPL_WIDTH),
conv_std_logic_vector(12120,AMPL_WIDTH),
conv_std_logic_vector(12123,AMPL_WIDTH),
conv_std_logic_vector(12126,AMPL_WIDTH),
conv_std_logic_vector(12129,AMPL_WIDTH),
conv_std_logic_vector(12132,AMPL_WIDTH),
conv_std_logic_vector(12135,AMPL_WIDTH),
conv_std_logic_vector(12138,AMPL_WIDTH),
conv_std_logic_vector(12141,AMPL_WIDTH),
conv_std_logic_vector(12144,AMPL_WIDTH),
conv_std_logic_vector(12147,AMPL_WIDTH),
conv_std_logic_vector(12149,AMPL_WIDTH),
conv_std_logic_vector(12152,AMPL_WIDTH),
conv_std_logic_vector(12155,AMPL_WIDTH),
conv_std_logic_vector(12158,AMPL_WIDTH),
conv_std_logic_vector(12161,AMPL_WIDTH),
conv_std_logic_vector(12164,AMPL_WIDTH),
conv_std_logic_vector(12167,AMPL_WIDTH),
conv_std_logic_vector(12170,AMPL_WIDTH),
conv_std_logic_vector(12173,AMPL_WIDTH),
conv_std_logic_vector(12176,AMPL_WIDTH),
conv_std_logic_vector(12179,AMPL_WIDTH),
conv_std_logic_vector(12182,AMPL_WIDTH),
conv_std_logic_vector(12184,AMPL_WIDTH),
conv_std_logic_vector(12187,AMPL_WIDTH),
conv_std_logic_vector(12190,AMPL_WIDTH),
conv_std_logic_vector(12193,AMPL_WIDTH),
conv_std_logic_vector(12196,AMPL_WIDTH),
conv_std_logic_vector(12199,AMPL_WIDTH),
conv_std_logic_vector(12202,AMPL_WIDTH),
conv_std_logic_vector(12205,AMPL_WIDTH),
conv_std_logic_vector(12208,AMPL_WIDTH),
conv_std_logic_vector(12211,AMPL_WIDTH),
conv_std_logic_vector(12214,AMPL_WIDTH),
conv_std_logic_vector(12217,AMPL_WIDTH),
conv_std_logic_vector(12219,AMPL_WIDTH),
conv_std_logic_vector(12222,AMPL_WIDTH),
conv_std_logic_vector(12225,AMPL_WIDTH),
conv_std_logic_vector(12228,AMPL_WIDTH),
conv_std_logic_vector(12231,AMPL_WIDTH),
conv_std_logic_vector(12234,AMPL_WIDTH),
conv_std_logic_vector(12237,AMPL_WIDTH),
conv_std_logic_vector(12240,AMPL_WIDTH),
conv_std_logic_vector(12243,AMPL_WIDTH),
conv_std_logic_vector(12246,AMPL_WIDTH),
conv_std_logic_vector(12249,AMPL_WIDTH),
conv_std_logic_vector(12251,AMPL_WIDTH),
conv_std_logic_vector(12254,AMPL_WIDTH),
conv_std_logic_vector(12257,AMPL_WIDTH),
conv_std_logic_vector(12260,AMPL_WIDTH),
conv_std_logic_vector(12263,AMPL_WIDTH),
conv_std_logic_vector(12266,AMPL_WIDTH),
conv_std_logic_vector(12269,AMPL_WIDTH),
conv_std_logic_vector(12272,AMPL_WIDTH),
conv_std_logic_vector(12275,AMPL_WIDTH),
conv_std_logic_vector(12278,AMPL_WIDTH),
conv_std_logic_vector(12281,AMPL_WIDTH),
conv_std_logic_vector(12284,AMPL_WIDTH),
conv_std_logic_vector(12286,AMPL_WIDTH),
conv_std_logic_vector(12289,AMPL_WIDTH),
conv_std_logic_vector(12292,AMPL_WIDTH),
conv_std_logic_vector(12295,AMPL_WIDTH),
conv_std_logic_vector(12298,AMPL_WIDTH),
conv_std_logic_vector(12301,AMPL_WIDTH),
conv_std_logic_vector(12304,AMPL_WIDTH),
conv_std_logic_vector(12307,AMPL_WIDTH),
conv_std_logic_vector(12310,AMPL_WIDTH),
conv_std_logic_vector(12313,AMPL_WIDTH),
conv_std_logic_vector(12316,AMPL_WIDTH),
conv_std_logic_vector(12318,AMPL_WIDTH),
conv_std_logic_vector(12321,AMPL_WIDTH),
conv_std_logic_vector(12324,AMPL_WIDTH),
conv_std_logic_vector(12327,AMPL_WIDTH),
conv_std_logic_vector(12330,AMPL_WIDTH),
conv_std_logic_vector(12333,AMPL_WIDTH),
conv_std_logic_vector(12336,AMPL_WIDTH),
conv_std_logic_vector(12339,AMPL_WIDTH),
conv_std_logic_vector(12342,AMPL_WIDTH),
conv_std_logic_vector(12345,AMPL_WIDTH),
conv_std_logic_vector(12348,AMPL_WIDTH),
conv_std_logic_vector(12350,AMPL_WIDTH),
conv_std_logic_vector(12353,AMPL_WIDTH),
conv_std_logic_vector(12356,AMPL_WIDTH),
conv_std_logic_vector(12359,AMPL_WIDTH),
conv_std_logic_vector(12362,AMPL_WIDTH),
conv_std_logic_vector(12365,AMPL_WIDTH),
conv_std_logic_vector(12368,AMPL_WIDTH),
conv_std_logic_vector(12371,AMPL_WIDTH),
conv_std_logic_vector(12374,AMPL_WIDTH),
conv_std_logic_vector(12377,AMPL_WIDTH),
conv_std_logic_vector(12380,AMPL_WIDTH),
conv_std_logic_vector(12382,AMPL_WIDTH),
conv_std_logic_vector(12385,AMPL_WIDTH),
conv_std_logic_vector(12388,AMPL_WIDTH),
conv_std_logic_vector(12391,AMPL_WIDTH),
conv_std_logic_vector(12394,AMPL_WIDTH),
conv_std_logic_vector(12397,AMPL_WIDTH),
conv_std_logic_vector(12400,AMPL_WIDTH),
conv_std_logic_vector(12403,AMPL_WIDTH),
conv_std_logic_vector(12406,AMPL_WIDTH),
conv_std_logic_vector(12409,AMPL_WIDTH),
conv_std_logic_vector(12412,AMPL_WIDTH),
conv_std_logic_vector(12414,AMPL_WIDTH),
conv_std_logic_vector(12417,AMPL_WIDTH),
conv_std_logic_vector(12420,AMPL_WIDTH),
conv_std_logic_vector(12423,AMPL_WIDTH),
conv_std_logic_vector(12426,AMPL_WIDTH),
conv_std_logic_vector(12429,AMPL_WIDTH),
conv_std_logic_vector(12432,AMPL_WIDTH),
conv_std_logic_vector(12435,AMPL_WIDTH),
conv_std_logic_vector(12438,AMPL_WIDTH),
conv_std_logic_vector(12441,AMPL_WIDTH),
conv_std_logic_vector(12444,AMPL_WIDTH),
conv_std_logic_vector(12446,AMPL_WIDTH),
conv_std_logic_vector(12449,AMPL_WIDTH),
conv_std_logic_vector(12452,AMPL_WIDTH),
conv_std_logic_vector(12455,AMPL_WIDTH),
conv_std_logic_vector(12458,AMPL_WIDTH),
conv_std_logic_vector(12461,AMPL_WIDTH),
conv_std_logic_vector(12464,AMPL_WIDTH),
conv_std_logic_vector(12467,AMPL_WIDTH),
conv_std_logic_vector(12470,AMPL_WIDTH),
conv_std_logic_vector(12473,AMPL_WIDTH),
conv_std_logic_vector(12476,AMPL_WIDTH),
conv_std_logic_vector(12478,AMPL_WIDTH),
conv_std_logic_vector(12481,AMPL_WIDTH),
conv_std_logic_vector(12484,AMPL_WIDTH),
conv_std_logic_vector(12487,AMPL_WIDTH),
conv_std_logic_vector(12490,AMPL_WIDTH),
conv_std_logic_vector(12493,AMPL_WIDTH),
conv_std_logic_vector(12496,AMPL_WIDTH),
conv_std_logic_vector(12499,AMPL_WIDTH),
conv_std_logic_vector(12502,AMPL_WIDTH),
conv_std_logic_vector(12505,AMPL_WIDTH),
conv_std_logic_vector(12507,AMPL_WIDTH),
conv_std_logic_vector(12510,AMPL_WIDTH),
conv_std_logic_vector(12513,AMPL_WIDTH),
conv_std_logic_vector(12516,AMPL_WIDTH),
conv_std_logic_vector(12519,AMPL_WIDTH),
conv_std_logic_vector(12522,AMPL_WIDTH),
conv_std_logic_vector(12525,AMPL_WIDTH),
conv_std_logic_vector(12528,AMPL_WIDTH),
conv_std_logic_vector(12531,AMPL_WIDTH),
conv_std_logic_vector(12534,AMPL_WIDTH),
conv_std_logic_vector(12536,AMPL_WIDTH),
conv_std_logic_vector(12539,AMPL_WIDTH),
conv_std_logic_vector(12542,AMPL_WIDTH),
conv_std_logic_vector(12545,AMPL_WIDTH),
conv_std_logic_vector(12548,AMPL_WIDTH),
conv_std_logic_vector(12551,AMPL_WIDTH),
conv_std_logic_vector(12554,AMPL_WIDTH),
conv_std_logic_vector(12557,AMPL_WIDTH),
conv_std_logic_vector(12560,AMPL_WIDTH),
conv_std_logic_vector(12563,AMPL_WIDTH),
conv_std_logic_vector(12566,AMPL_WIDTH),
conv_std_logic_vector(12568,AMPL_WIDTH),
conv_std_logic_vector(12571,AMPL_WIDTH),
conv_std_logic_vector(12574,AMPL_WIDTH),
conv_std_logic_vector(12577,AMPL_WIDTH),
conv_std_logic_vector(12580,AMPL_WIDTH),
conv_std_logic_vector(12583,AMPL_WIDTH),
conv_std_logic_vector(12586,AMPL_WIDTH),
conv_std_logic_vector(12589,AMPL_WIDTH),
conv_std_logic_vector(12592,AMPL_WIDTH),
conv_std_logic_vector(12595,AMPL_WIDTH),
conv_std_logic_vector(12597,AMPL_WIDTH),
conv_std_logic_vector(12600,AMPL_WIDTH),
conv_std_logic_vector(12603,AMPL_WIDTH),
conv_std_logic_vector(12606,AMPL_WIDTH),
conv_std_logic_vector(12609,AMPL_WIDTH),
conv_std_logic_vector(12612,AMPL_WIDTH),
conv_std_logic_vector(12615,AMPL_WIDTH),
conv_std_logic_vector(12618,AMPL_WIDTH),
conv_std_logic_vector(12621,AMPL_WIDTH),
conv_std_logic_vector(12624,AMPL_WIDTH),
conv_std_logic_vector(12626,AMPL_WIDTH),
conv_std_logic_vector(12629,AMPL_WIDTH),
conv_std_logic_vector(12632,AMPL_WIDTH),
conv_std_logic_vector(12635,AMPL_WIDTH),
conv_std_logic_vector(12638,AMPL_WIDTH),
conv_std_logic_vector(12641,AMPL_WIDTH),
conv_std_logic_vector(12644,AMPL_WIDTH),
conv_std_logic_vector(12647,AMPL_WIDTH),
conv_std_logic_vector(12650,AMPL_WIDTH),
conv_std_logic_vector(12652,AMPL_WIDTH),
conv_std_logic_vector(12655,AMPL_WIDTH),
conv_std_logic_vector(12658,AMPL_WIDTH),
conv_std_logic_vector(12661,AMPL_WIDTH),
conv_std_logic_vector(12664,AMPL_WIDTH),
conv_std_logic_vector(12667,AMPL_WIDTH),
conv_std_logic_vector(12670,AMPL_WIDTH),
conv_std_logic_vector(12673,AMPL_WIDTH),
conv_std_logic_vector(12676,AMPL_WIDTH),
conv_std_logic_vector(12679,AMPL_WIDTH),
conv_std_logic_vector(12681,AMPL_WIDTH),
conv_std_logic_vector(12684,AMPL_WIDTH),
conv_std_logic_vector(12687,AMPL_WIDTH),
conv_std_logic_vector(12690,AMPL_WIDTH),
conv_std_logic_vector(12693,AMPL_WIDTH),
conv_std_logic_vector(12696,AMPL_WIDTH),
conv_std_logic_vector(12699,AMPL_WIDTH),
conv_std_logic_vector(12702,AMPL_WIDTH),
conv_std_logic_vector(12705,AMPL_WIDTH),
conv_std_logic_vector(12708,AMPL_WIDTH),
conv_std_logic_vector(12710,AMPL_WIDTH),
conv_std_logic_vector(12713,AMPL_WIDTH),
conv_std_logic_vector(12716,AMPL_WIDTH),
conv_std_logic_vector(12719,AMPL_WIDTH),
conv_std_logic_vector(12722,AMPL_WIDTH),
conv_std_logic_vector(12725,AMPL_WIDTH),
conv_std_logic_vector(12728,AMPL_WIDTH),
conv_std_logic_vector(12731,AMPL_WIDTH),
conv_std_logic_vector(12734,AMPL_WIDTH),
conv_std_logic_vector(12736,AMPL_WIDTH),
conv_std_logic_vector(12739,AMPL_WIDTH),
conv_std_logic_vector(12742,AMPL_WIDTH),
conv_std_logic_vector(12745,AMPL_WIDTH),
conv_std_logic_vector(12748,AMPL_WIDTH),
conv_std_logic_vector(12751,AMPL_WIDTH),
conv_std_logic_vector(12754,AMPL_WIDTH),
conv_std_logic_vector(12757,AMPL_WIDTH),
conv_std_logic_vector(12760,AMPL_WIDTH),
conv_std_logic_vector(12763,AMPL_WIDTH),
conv_std_logic_vector(12765,AMPL_WIDTH),
conv_std_logic_vector(12768,AMPL_WIDTH),
conv_std_logic_vector(12771,AMPL_WIDTH),
conv_std_logic_vector(12774,AMPL_WIDTH),
conv_std_logic_vector(12777,AMPL_WIDTH),
conv_std_logic_vector(12780,AMPL_WIDTH),
conv_std_logic_vector(12783,AMPL_WIDTH),
conv_std_logic_vector(12786,AMPL_WIDTH),
conv_std_logic_vector(12789,AMPL_WIDTH),
conv_std_logic_vector(12791,AMPL_WIDTH),
conv_std_logic_vector(12794,AMPL_WIDTH),
conv_std_logic_vector(12797,AMPL_WIDTH),
conv_std_logic_vector(12800,AMPL_WIDTH),
conv_std_logic_vector(12803,AMPL_WIDTH),
conv_std_logic_vector(12806,AMPL_WIDTH),
conv_std_logic_vector(12809,AMPL_WIDTH),
conv_std_logic_vector(12812,AMPL_WIDTH),
conv_std_logic_vector(12815,AMPL_WIDTH),
conv_std_logic_vector(12817,AMPL_WIDTH),
conv_std_logic_vector(12820,AMPL_WIDTH),
conv_std_logic_vector(12823,AMPL_WIDTH),
conv_std_logic_vector(12826,AMPL_WIDTH),
conv_std_logic_vector(12829,AMPL_WIDTH),
conv_std_logic_vector(12832,AMPL_WIDTH),
conv_std_logic_vector(12835,AMPL_WIDTH),
conv_std_logic_vector(12838,AMPL_WIDTH),
conv_std_logic_vector(12841,AMPL_WIDTH),
conv_std_logic_vector(12843,AMPL_WIDTH),
conv_std_logic_vector(12846,AMPL_WIDTH),
conv_std_logic_vector(12849,AMPL_WIDTH),
conv_std_logic_vector(12852,AMPL_WIDTH),
conv_std_logic_vector(12855,AMPL_WIDTH),
conv_std_logic_vector(12858,AMPL_WIDTH),
conv_std_logic_vector(12861,AMPL_WIDTH),
conv_std_logic_vector(12864,AMPL_WIDTH),
conv_std_logic_vector(12867,AMPL_WIDTH),
conv_std_logic_vector(12870,AMPL_WIDTH),
conv_std_logic_vector(12872,AMPL_WIDTH),
conv_std_logic_vector(12875,AMPL_WIDTH),
conv_std_logic_vector(12878,AMPL_WIDTH),
conv_std_logic_vector(12881,AMPL_WIDTH),
conv_std_logic_vector(12884,AMPL_WIDTH),
conv_std_logic_vector(12887,AMPL_WIDTH),
conv_std_logic_vector(12890,AMPL_WIDTH),
conv_std_logic_vector(12893,AMPL_WIDTH),
conv_std_logic_vector(12895,AMPL_WIDTH),
conv_std_logic_vector(12898,AMPL_WIDTH),
conv_std_logic_vector(12901,AMPL_WIDTH),
conv_std_logic_vector(12904,AMPL_WIDTH),
conv_std_logic_vector(12907,AMPL_WIDTH),
conv_std_logic_vector(12910,AMPL_WIDTH),
conv_std_logic_vector(12913,AMPL_WIDTH),
conv_std_logic_vector(12916,AMPL_WIDTH),
conv_std_logic_vector(12919,AMPL_WIDTH),
conv_std_logic_vector(12921,AMPL_WIDTH),
conv_std_logic_vector(12924,AMPL_WIDTH),
conv_std_logic_vector(12927,AMPL_WIDTH),
conv_std_logic_vector(12930,AMPL_WIDTH),
conv_std_logic_vector(12933,AMPL_WIDTH),
conv_std_logic_vector(12936,AMPL_WIDTH),
conv_std_logic_vector(12939,AMPL_WIDTH),
conv_std_logic_vector(12942,AMPL_WIDTH),
conv_std_logic_vector(12945,AMPL_WIDTH),
conv_std_logic_vector(12947,AMPL_WIDTH),
conv_std_logic_vector(12950,AMPL_WIDTH),
conv_std_logic_vector(12953,AMPL_WIDTH),
conv_std_logic_vector(12956,AMPL_WIDTH),
conv_std_logic_vector(12959,AMPL_WIDTH),
conv_std_logic_vector(12962,AMPL_WIDTH),
conv_std_logic_vector(12965,AMPL_WIDTH),
conv_std_logic_vector(12968,AMPL_WIDTH),
conv_std_logic_vector(12971,AMPL_WIDTH),
conv_std_logic_vector(12973,AMPL_WIDTH),
conv_std_logic_vector(12976,AMPL_WIDTH),
conv_std_logic_vector(12979,AMPL_WIDTH),
conv_std_logic_vector(12982,AMPL_WIDTH),
conv_std_logic_vector(12985,AMPL_WIDTH),
conv_std_logic_vector(12988,AMPL_WIDTH),
conv_std_logic_vector(12991,AMPL_WIDTH),
conv_std_logic_vector(12994,AMPL_WIDTH),
conv_std_logic_vector(12997,AMPL_WIDTH),
conv_std_logic_vector(12999,AMPL_WIDTH),
conv_std_logic_vector(13002,AMPL_WIDTH),
conv_std_logic_vector(13005,AMPL_WIDTH),
conv_std_logic_vector(13008,AMPL_WIDTH),
conv_std_logic_vector(13011,AMPL_WIDTH),
conv_std_logic_vector(13014,AMPL_WIDTH),
conv_std_logic_vector(13017,AMPL_WIDTH),
conv_std_logic_vector(13020,AMPL_WIDTH),
conv_std_logic_vector(13022,AMPL_WIDTH),
conv_std_logic_vector(13025,AMPL_WIDTH),
conv_std_logic_vector(13028,AMPL_WIDTH),
conv_std_logic_vector(13031,AMPL_WIDTH),
conv_std_logic_vector(13034,AMPL_WIDTH),
conv_std_logic_vector(13037,AMPL_WIDTH),
conv_std_logic_vector(13040,AMPL_WIDTH),
conv_std_logic_vector(13043,AMPL_WIDTH),
conv_std_logic_vector(13046,AMPL_WIDTH),
conv_std_logic_vector(13048,AMPL_WIDTH),
conv_std_logic_vector(13051,AMPL_WIDTH),
conv_std_logic_vector(13054,AMPL_WIDTH),
conv_std_logic_vector(13057,AMPL_WIDTH),
conv_std_logic_vector(13060,AMPL_WIDTH),
conv_std_logic_vector(13063,AMPL_WIDTH),
conv_std_logic_vector(13066,AMPL_WIDTH),
conv_std_logic_vector(13069,AMPL_WIDTH),
conv_std_logic_vector(13071,AMPL_WIDTH),
conv_std_logic_vector(13074,AMPL_WIDTH),
conv_std_logic_vector(13077,AMPL_WIDTH),
conv_std_logic_vector(13080,AMPL_WIDTH),
conv_std_logic_vector(13083,AMPL_WIDTH),
conv_std_logic_vector(13086,AMPL_WIDTH),
conv_std_logic_vector(13089,AMPL_WIDTH),
conv_std_logic_vector(13092,AMPL_WIDTH),
conv_std_logic_vector(13094,AMPL_WIDTH),
conv_std_logic_vector(13097,AMPL_WIDTH),
conv_std_logic_vector(13100,AMPL_WIDTH),
conv_std_logic_vector(13103,AMPL_WIDTH),
conv_std_logic_vector(13106,AMPL_WIDTH),
conv_std_logic_vector(13109,AMPL_WIDTH),
conv_std_logic_vector(13112,AMPL_WIDTH),
conv_std_logic_vector(13115,AMPL_WIDTH),
conv_std_logic_vector(13118,AMPL_WIDTH),
conv_std_logic_vector(13120,AMPL_WIDTH),
conv_std_logic_vector(13123,AMPL_WIDTH),
conv_std_logic_vector(13126,AMPL_WIDTH),
conv_std_logic_vector(13129,AMPL_WIDTH),
conv_std_logic_vector(13132,AMPL_WIDTH),
conv_std_logic_vector(13135,AMPL_WIDTH),
conv_std_logic_vector(13138,AMPL_WIDTH),
conv_std_logic_vector(13141,AMPL_WIDTH),
conv_std_logic_vector(13143,AMPL_WIDTH),
conv_std_logic_vector(13146,AMPL_WIDTH),
conv_std_logic_vector(13149,AMPL_WIDTH),
conv_std_logic_vector(13152,AMPL_WIDTH),
conv_std_logic_vector(13155,AMPL_WIDTH),
conv_std_logic_vector(13158,AMPL_WIDTH),
conv_std_logic_vector(13161,AMPL_WIDTH),
conv_std_logic_vector(13164,AMPL_WIDTH),
conv_std_logic_vector(13166,AMPL_WIDTH),
conv_std_logic_vector(13169,AMPL_WIDTH),
conv_std_logic_vector(13172,AMPL_WIDTH),
conv_std_logic_vector(13175,AMPL_WIDTH),
conv_std_logic_vector(13178,AMPL_WIDTH),
conv_std_logic_vector(13181,AMPL_WIDTH),
conv_std_logic_vector(13184,AMPL_WIDTH),
conv_std_logic_vector(13187,AMPL_WIDTH),
conv_std_logic_vector(13189,AMPL_WIDTH),
conv_std_logic_vector(13192,AMPL_WIDTH),
conv_std_logic_vector(13195,AMPL_WIDTH),
conv_std_logic_vector(13198,AMPL_WIDTH),
conv_std_logic_vector(13201,AMPL_WIDTH),
conv_std_logic_vector(13204,AMPL_WIDTH),
conv_std_logic_vector(13207,AMPL_WIDTH),
conv_std_logic_vector(13210,AMPL_WIDTH),
conv_std_logic_vector(13212,AMPL_WIDTH),
conv_std_logic_vector(13215,AMPL_WIDTH),
conv_std_logic_vector(13218,AMPL_WIDTH),
conv_std_logic_vector(13221,AMPL_WIDTH),
conv_std_logic_vector(13224,AMPL_WIDTH),
conv_std_logic_vector(13227,AMPL_WIDTH),
conv_std_logic_vector(13230,AMPL_WIDTH),
conv_std_logic_vector(13233,AMPL_WIDTH),
conv_std_logic_vector(13235,AMPL_WIDTH),
conv_std_logic_vector(13238,AMPL_WIDTH),
conv_std_logic_vector(13241,AMPL_WIDTH),
conv_std_logic_vector(13244,AMPL_WIDTH),
conv_std_logic_vector(13247,AMPL_WIDTH),
conv_std_logic_vector(13250,AMPL_WIDTH),
conv_std_logic_vector(13253,AMPL_WIDTH),
conv_std_logic_vector(13256,AMPL_WIDTH),
conv_std_logic_vector(13258,AMPL_WIDTH),
conv_std_logic_vector(13261,AMPL_WIDTH),
conv_std_logic_vector(13264,AMPL_WIDTH),
conv_std_logic_vector(13267,AMPL_WIDTH),
conv_std_logic_vector(13270,AMPL_WIDTH),
conv_std_logic_vector(13273,AMPL_WIDTH),
conv_std_logic_vector(13276,AMPL_WIDTH),
conv_std_logic_vector(13279,AMPL_WIDTH),
conv_std_logic_vector(13281,AMPL_WIDTH),
conv_std_logic_vector(13284,AMPL_WIDTH),
conv_std_logic_vector(13287,AMPL_WIDTH),
conv_std_logic_vector(13290,AMPL_WIDTH),
conv_std_logic_vector(13293,AMPL_WIDTH),
conv_std_logic_vector(13296,AMPL_WIDTH),
conv_std_logic_vector(13299,AMPL_WIDTH),
conv_std_logic_vector(13302,AMPL_WIDTH),
conv_std_logic_vector(13304,AMPL_WIDTH),
conv_std_logic_vector(13307,AMPL_WIDTH),
conv_std_logic_vector(13310,AMPL_WIDTH),
conv_std_logic_vector(13313,AMPL_WIDTH),
conv_std_logic_vector(13316,AMPL_WIDTH),
conv_std_logic_vector(13319,AMPL_WIDTH),
conv_std_logic_vector(13322,AMPL_WIDTH),
conv_std_logic_vector(13324,AMPL_WIDTH),
conv_std_logic_vector(13327,AMPL_WIDTH),
conv_std_logic_vector(13330,AMPL_WIDTH),
conv_std_logic_vector(13333,AMPL_WIDTH),
conv_std_logic_vector(13336,AMPL_WIDTH),
conv_std_logic_vector(13339,AMPL_WIDTH),
conv_std_logic_vector(13342,AMPL_WIDTH),
conv_std_logic_vector(13345,AMPL_WIDTH),
conv_std_logic_vector(13347,AMPL_WIDTH),
conv_std_logic_vector(13350,AMPL_WIDTH),
conv_std_logic_vector(13353,AMPL_WIDTH),
conv_std_logic_vector(13356,AMPL_WIDTH),
conv_std_logic_vector(13359,AMPL_WIDTH),
conv_std_logic_vector(13362,AMPL_WIDTH),
conv_std_logic_vector(13365,AMPL_WIDTH),
conv_std_logic_vector(13368,AMPL_WIDTH),
conv_std_logic_vector(13370,AMPL_WIDTH),
conv_std_logic_vector(13373,AMPL_WIDTH),
conv_std_logic_vector(13376,AMPL_WIDTH),
conv_std_logic_vector(13379,AMPL_WIDTH),
conv_std_logic_vector(13382,AMPL_WIDTH),
conv_std_logic_vector(13385,AMPL_WIDTH),
conv_std_logic_vector(13388,AMPL_WIDTH),
conv_std_logic_vector(13390,AMPL_WIDTH),
conv_std_logic_vector(13393,AMPL_WIDTH),
conv_std_logic_vector(13396,AMPL_WIDTH),
conv_std_logic_vector(13399,AMPL_WIDTH),
conv_std_logic_vector(13402,AMPL_WIDTH),
conv_std_logic_vector(13405,AMPL_WIDTH),
conv_std_logic_vector(13408,AMPL_WIDTH),
conv_std_logic_vector(13411,AMPL_WIDTH),
conv_std_logic_vector(13413,AMPL_WIDTH),
conv_std_logic_vector(13416,AMPL_WIDTH),
conv_std_logic_vector(13419,AMPL_WIDTH),
conv_std_logic_vector(13422,AMPL_WIDTH),
conv_std_logic_vector(13425,AMPL_WIDTH),
conv_std_logic_vector(13428,AMPL_WIDTH),
conv_std_logic_vector(13431,AMPL_WIDTH),
conv_std_logic_vector(13433,AMPL_WIDTH),
conv_std_logic_vector(13436,AMPL_WIDTH),
conv_std_logic_vector(13439,AMPL_WIDTH),
conv_std_logic_vector(13442,AMPL_WIDTH),
conv_std_logic_vector(13445,AMPL_WIDTH),
conv_std_logic_vector(13448,AMPL_WIDTH),
conv_std_logic_vector(13451,AMPL_WIDTH),
conv_std_logic_vector(13454,AMPL_WIDTH),
conv_std_logic_vector(13456,AMPL_WIDTH),
conv_std_logic_vector(13459,AMPL_WIDTH),
conv_std_logic_vector(13462,AMPL_WIDTH),
conv_std_logic_vector(13465,AMPL_WIDTH),
conv_std_logic_vector(13468,AMPL_WIDTH),
conv_std_logic_vector(13471,AMPL_WIDTH),
conv_std_logic_vector(13474,AMPL_WIDTH),
conv_std_logic_vector(13476,AMPL_WIDTH),
conv_std_logic_vector(13479,AMPL_WIDTH),
conv_std_logic_vector(13482,AMPL_WIDTH),
conv_std_logic_vector(13485,AMPL_WIDTH),
conv_std_logic_vector(13488,AMPL_WIDTH),
conv_std_logic_vector(13491,AMPL_WIDTH),
conv_std_logic_vector(13494,AMPL_WIDTH),
conv_std_logic_vector(13496,AMPL_WIDTH),
conv_std_logic_vector(13499,AMPL_WIDTH),
conv_std_logic_vector(13502,AMPL_WIDTH),
conv_std_logic_vector(13505,AMPL_WIDTH),
conv_std_logic_vector(13508,AMPL_WIDTH),
conv_std_logic_vector(13511,AMPL_WIDTH),
conv_std_logic_vector(13514,AMPL_WIDTH),
conv_std_logic_vector(13516,AMPL_WIDTH),
conv_std_logic_vector(13519,AMPL_WIDTH),
conv_std_logic_vector(13522,AMPL_WIDTH),
conv_std_logic_vector(13525,AMPL_WIDTH),
conv_std_logic_vector(13528,AMPL_WIDTH),
conv_std_logic_vector(13531,AMPL_WIDTH),
conv_std_logic_vector(13534,AMPL_WIDTH),
conv_std_logic_vector(13537,AMPL_WIDTH),
conv_std_logic_vector(13539,AMPL_WIDTH),
conv_std_logic_vector(13542,AMPL_WIDTH),
conv_std_logic_vector(13545,AMPL_WIDTH),
conv_std_logic_vector(13548,AMPL_WIDTH),
conv_std_logic_vector(13551,AMPL_WIDTH),
conv_std_logic_vector(13554,AMPL_WIDTH),
conv_std_logic_vector(13557,AMPL_WIDTH),
conv_std_logic_vector(13559,AMPL_WIDTH),
conv_std_logic_vector(13562,AMPL_WIDTH),
conv_std_logic_vector(13565,AMPL_WIDTH),
conv_std_logic_vector(13568,AMPL_WIDTH),
conv_std_logic_vector(13571,AMPL_WIDTH),
conv_std_logic_vector(13574,AMPL_WIDTH),
conv_std_logic_vector(13577,AMPL_WIDTH),
conv_std_logic_vector(13579,AMPL_WIDTH),
conv_std_logic_vector(13582,AMPL_WIDTH),
conv_std_logic_vector(13585,AMPL_WIDTH),
conv_std_logic_vector(13588,AMPL_WIDTH),
conv_std_logic_vector(13591,AMPL_WIDTH),
conv_std_logic_vector(13594,AMPL_WIDTH),
conv_std_logic_vector(13597,AMPL_WIDTH),
conv_std_logic_vector(13599,AMPL_WIDTH),
conv_std_logic_vector(13602,AMPL_WIDTH),
conv_std_logic_vector(13605,AMPL_WIDTH),
conv_std_logic_vector(13608,AMPL_WIDTH),
conv_std_logic_vector(13611,AMPL_WIDTH),
conv_std_logic_vector(13614,AMPL_WIDTH),
conv_std_logic_vector(13617,AMPL_WIDTH),
conv_std_logic_vector(13619,AMPL_WIDTH),
conv_std_logic_vector(13622,AMPL_WIDTH),
conv_std_logic_vector(13625,AMPL_WIDTH),
conv_std_logic_vector(13628,AMPL_WIDTH),
conv_std_logic_vector(13631,AMPL_WIDTH),
conv_std_logic_vector(13634,AMPL_WIDTH),
conv_std_logic_vector(13637,AMPL_WIDTH),
conv_std_logic_vector(13639,AMPL_WIDTH),
conv_std_logic_vector(13642,AMPL_WIDTH),
conv_std_logic_vector(13645,AMPL_WIDTH),
conv_std_logic_vector(13648,AMPL_WIDTH),
conv_std_logic_vector(13651,AMPL_WIDTH),
conv_std_logic_vector(13654,AMPL_WIDTH),
conv_std_logic_vector(13657,AMPL_WIDTH),
conv_std_logic_vector(13659,AMPL_WIDTH),
conv_std_logic_vector(13662,AMPL_WIDTH),
conv_std_logic_vector(13665,AMPL_WIDTH),
conv_std_logic_vector(13668,AMPL_WIDTH),
conv_std_logic_vector(13671,AMPL_WIDTH),
conv_std_logic_vector(13674,AMPL_WIDTH),
conv_std_logic_vector(13677,AMPL_WIDTH),
conv_std_logic_vector(13679,AMPL_WIDTH),
conv_std_logic_vector(13682,AMPL_WIDTH),
conv_std_logic_vector(13685,AMPL_WIDTH),
conv_std_logic_vector(13688,AMPL_WIDTH),
conv_std_logic_vector(13691,AMPL_WIDTH),
conv_std_logic_vector(13694,AMPL_WIDTH),
conv_std_logic_vector(13697,AMPL_WIDTH),
conv_std_logic_vector(13699,AMPL_WIDTH),
conv_std_logic_vector(13702,AMPL_WIDTH),
conv_std_logic_vector(13705,AMPL_WIDTH),
conv_std_logic_vector(13708,AMPL_WIDTH),
conv_std_logic_vector(13711,AMPL_WIDTH),
conv_std_logic_vector(13714,AMPL_WIDTH),
conv_std_logic_vector(13717,AMPL_WIDTH),
conv_std_logic_vector(13719,AMPL_WIDTH),
conv_std_logic_vector(13722,AMPL_WIDTH),
conv_std_logic_vector(13725,AMPL_WIDTH),
conv_std_logic_vector(13728,AMPL_WIDTH),
conv_std_logic_vector(13731,AMPL_WIDTH),
conv_std_logic_vector(13734,AMPL_WIDTH),
conv_std_logic_vector(13736,AMPL_WIDTH),
conv_std_logic_vector(13739,AMPL_WIDTH),
conv_std_logic_vector(13742,AMPL_WIDTH),
conv_std_logic_vector(13745,AMPL_WIDTH),
conv_std_logic_vector(13748,AMPL_WIDTH),
conv_std_logic_vector(13751,AMPL_WIDTH),
conv_std_logic_vector(13754,AMPL_WIDTH),
conv_std_logic_vector(13756,AMPL_WIDTH),
conv_std_logic_vector(13759,AMPL_WIDTH),
conv_std_logic_vector(13762,AMPL_WIDTH),
conv_std_logic_vector(13765,AMPL_WIDTH),
conv_std_logic_vector(13768,AMPL_WIDTH),
conv_std_logic_vector(13771,AMPL_WIDTH),
conv_std_logic_vector(13774,AMPL_WIDTH),
conv_std_logic_vector(13776,AMPL_WIDTH),
conv_std_logic_vector(13779,AMPL_WIDTH),
conv_std_logic_vector(13782,AMPL_WIDTH),
conv_std_logic_vector(13785,AMPL_WIDTH),
conv_std_logic_vector(13788,AMPL_WIDTH),
conv_std_logic_vector(13791,AMPL_WIDTH),
conv_std_logic_vector(13793,AMPL_WIDTH),
conv_std_logic_vector(13796,AMPL_WIDTH),
conv_std_logic_vector(13799,AMPL_WIDTH),
conv_std_logic_vector(13802,AMPL_WIDTH),
conv_std_logic_vector(13805,AMPL_WIDTH),
conv_std_logic_vector(13808,AMPL_WIDTH),
conv_std_logic_vector(13811,AMPL_WIDTH),
conv_std_logic_vector(13813,AMPL_WIDTH),
conv_std_logic_vector(13816,AMPL_WIDTH),
conv_std_logic_vector(13819,AMPL_WIDTH),
conv_std_logic_vector(13822,AMPL_WIDTH),
conv_std_logic_vector(13825,AMPL_WIDTH),
conv_std_logic_vector(13828,AMPL_WIDTH),
conv_std_logic_vector(13831,AMPL_WIDTH),
conv_std_logic_vector(13833,AMPL_WIDTH),
conv_std_logic_vector(13836,AMPL_WIDTH),
conv_std_logic_vector(13839,AMPL_WIDTH),
conv_std_logic_vector(13842,AMPL_WIDTH),
conv_std_logic_vector(13845,AMPL_WIDTH),
conv_std_logic_vector(13848,AMPL_WIDTH),
conv_std_logic_vector(13850,AMPL_WIDTH),
conv_std_logic_vector(13853,AMPL_WIDTH),
conv_std_logic_vector(13856,AMPL_WIDTH),
conv_std_logic_vector(13859,AMPL_WIDTH),
conv_std_logic_vector(13862,AMPL_WIDTH),
conv_std_logic_vector(13865,AMPL_WIDTH),
conv_std_logic_vector(13868,AMPL_WIDTH),
conv_std_logic_vector(13870,AMPL_WIDTH),
conv_std_logic_vector(13873,AMPL_WIDTH),
conv_std_logic_vector(13876,AMPL_WIDTH),
conv_std_logic_vector(13879,AMPL_WIDTH),
conv_std_logic_vector(13882,AMPL_WIDTH),
conv_std_logic_vector(13885,AMPL_WIDTH),
conv_std_logic_vector(13887,AMPL_WIDTH),
conv_std_logic_vector(13890,AMPL_WIDTH),
conv_std_logic_vector(13893,AMPL_WIDTH),
conv_std_logic_vector(13896,AMPL_WIDTH),
conv_std_logic_vector(13899,AMPL_WIDTH),
conv_std_logic_vector(13902,AMPL_WIDTH),
conv_std_logic_vector(13905,AMPL_WIDTH),
conv_std_logic_vector(13907,AMPL_WIDTH),
conv_std_logic_vector(13910,AMPL_WIDTH),
conv_std_logic_vector(13913,AMPL_WIDTH),
conv_std_logic_vector(13916,AMPL_WIDTH),
conv_std_logic_vector(13919,AMPL_WIDTH),
conv_std_logic_vector(13922,AMPL_WIDTH),
conv_std_logic_vector(13924,AMPL_WIDTH),
conv_std_logic_vector(13927,AMPL_WIDTH),
conv_std_logic_vector(13930,AMPL_WIDTH),
conv_std_logic_vector(13933,AMPL_WIDTH),
conv_std_logic_vector(13936,AMPL_WIDTH),
conv_std_logic_vector(13939,AMPL_WIDTH),
conv_std_logic_vector(13942,AMPL_WIDTH),
conv_std_logic_vector(13944,AMPL_WIDTH),
conv_std_logic_vector(13947,AMPL_WIDTH),
conv_std_logic_vector(13950,AMPL_WIDTH),
conv_std_logic_vector(13953,AMPL_WIDTH),
conv_std_logic_vector(13956,AMPL_WIDTH),
conv_std_logic_vector(13959,AMPL_WIDTH),
conv_std_logic_vector(13961,AMPL_WIDTH),
conv_std_logic_vector(13964,AMPL_WIDTH),
conv_std_logic_vector(13967,AMPL_WIDTH),
conv_std_logic_vector(13970,AMPL_WIDTH),
conv_std_logic_vector(13973,AMPL_WIDTH),
conv_std_logic_vector(13976,AMPL_WIDTH),
conv_std_logic_vector(13978,AMPL_WIDTH),
conv_std_logic_vector(13981,AMPL_WIDTH),
conv_std_logic_vector(13984,AMPL_WIDTH),
conv_std_logic_vector(13987,AMPL_WIDTH),
conv_std_logic_vector(13990,AMPL_WIDTH),
conv_std_logic_vector(13993,AMPL_WIDTH),
conv_std_logic_vector(13995,AMPL_WIDTH),
conv_std_logic_vector(13998,AMPL_WIDTH),
conv_std_logic_vector(14001,AMPL_WIDTH),
conv_std_logic_vector(14004,AMPL_WIDTH),
conv_std_logic_vector(14007,AMPL_WIDTH),
conv_std_logic_vector(14010,AMPL_WIDTH),
conv_std_logic_vector(14013,AMPL_WIDTH),
conv_std_logic_vector(14015,AMPL_WIDTH),
conv_std_logic_vector(14018,AMPL_WIDTH),
conv_std_logic_vector(14021,AMPL_WIDTH),
conv_std_logic_vector(14024,AMPL_WIDTH),
conv_std_logic_vector(14027,AMPL_WIDTH),
conv_std_logic_vector(14030,AMPL_WIDTH),
conv_std_logic_vector(14032,AMPL_WIDTH),
conv_std_logic_vector(14035,AMPL_WIDTH),
conv_std_logic_vector(14038,AMPL_WIDTH),
conv_std_logic_vector(14041,AMPL_WIDTH),
conv_std_logic_vector(14044,AMPL_WIDTH),
conv_std_logic_vector(14047,AMPL_WIDTH),
conv_std_logic_vector(14049,AMPL_WIDTH),
conv_std_logic_vector(14052,AMPL_WIDTH),
conv_std_logic_vector(14055,AMPL_WIDTH),
conv_std_logic_vector(14058,AMPL_WIDTH),
conv_std_logic_vector(14061,AMPL_WIDTH),
conv_std_logic_vector(14064,AMPL_WIDTH),
conv_std_logic_vector(14066,AMPL_WIDTH),
conv_std_logic_vector(14069,AMPL_WIDTH),
conv_std_logic_vector(14072,AMPL_WIDTH),
conv_std_logic_vector(14075,AMPL_WIDTH),
conv_std_logic_vector(14078,AMPL_WIDTH),
conv_std_logic_vector(14081,AMPL_WIDTH),
conv_std_logic_vector(14083,AMPL_WIDTH),
conv_std_logic_vector(14086,AMPL_WIDTH),
conv_std_logic_vector(14089,AMPL_WIDTH),
conv_std_logic_vector(14092,AMPL_WIDTH),
conv_std_logic_vector(14095,AMPL_WIDTH),
conv_std_logic_vector(14098,AMPL_WIDTH),
conv_std_logic_vector(14101,AMPL_WIDTH),
conv_std_logic_vector(14103,AMPL_WIDTH),
conv_std_logic_vector(14106,AMPL_WIDTH),
conv_std_logic_vector(14109,AMPL_WIDTH),
conv_std_logic_vector(14112,AMPL_WIDTH),
conv_std_logic_vector(14115,AMPL_WIDTH),
conv_std_logic_vector(14118,AMPL_WIDTH),
conv_std_logic_vector(14120,AMPL_WIDTH),
conv_std_logic_vector(14123,AMPL_WIDTH),
conv_std_logic_vector(14126,AMPL_WIDTH),
conv_std_logic_vector(14129,AMPL_WIDTH),
conv_std_logic_vector(14132,AMPL_WIDTH),
conv_std_logic_vector(14135,AMPL_WIDTH),
conv_std_logic_vector(14137,AMPL_WIDTH),
conv_std_logic_vector(14140,AMPL_WIDTH),
conv_std_logic_vector(14143,AMPL_WIDTH),
conv_std_logic_vector(14146,AMPL_WIDTH),
conv_std_logic_vector(14149,AMPL_WIDTH),
conv_std_logic_vector(14152,AMPL_WIDTH),
conv_std_logic_vector(14154,AMPL_WIDTH),
conv_std_logic_vector(14157,AMPL_WIDTH),
conv_std_logic_vector(14160,AMPL_WIDTH),
conv_std_logic_vector(14163,AMPL_WIDTH),
conv_std_logic_vector(14166,AMPL_WIDTH),
conv_std_logic_vector(14169,AMPL_WIDTH),
conv_std_logic_vector(14171,AMPL_WIDTH),
conv_std_logic_vector(14174,AMPL_WIDTH),
conv_std_logic_vector(14177,AMPL_WIDTH),
conv_std_logic_vector(14180,AMPL_WIDTH),
conv_std_logic_vector(14183,AMPL_WIDTH),
conv_std_logic_vector(14186,AMPL_WIDTH),
conv_std_logic_vector(14188,AMPL_WIDTH),
conv_std_logic_vector(14191,AMPL_WIDTH),
conv_std_logic_vector(14194,AMPL_WIDTH),
conv_std_logic_vector(14197,AMPL_WIDTH),
conv_std_logic_vector(14200,AMPL_WIDTH),
conv_std_logic_vector(14203,AMPL_WIDTH),
conv_std_logic_vector(14205,AMPL_WIDTH),
conv_std_logic_vector(14208,AMPL_WIDTH),
conv_std_logic_vector(14211,AMPL_WIDTH),
conv_std_logic_vector(14214,AMPL_WIDTH),
conv_std_logic_vector(14217,AMPL_WIDTH),
conv_std_logic_vector(14219,AMPL_WIDTH),
conv_std_logic_vector(14222,AMPL_WIDTH),
conv_std_logic_vector(14225,AMPL_WIDTH),
conv_std_logic_vector(14228,AMPL_WIDTH),
conv_std_logic_vector(14231,AMPL_WIDTH),
conv_std_logic_vector(14234,AMPL_WIDTH),
conv_std_logic_vector(14236,AMPL_WIDTH),
conv_std_logic_vector(14239,AMPL_WIDTH),
conv_std_logic_vector(14242,AMPL_WIDTH),
conv_std_logic_vector(14245,AMPL_WIDTH),
conv_std_logic_vector(14248,AMPL_WIDTH),
conv_std_logic_vector(14251,AMPL_WIDTH),
conv_std_logic_vector(14253,AMPL_WIDTH),
conv_std_logic_vector(14256,AMPL_WIDTH),
conv_std_logic_vector(14259,AMPL_WIDTH),
conv_std_logic_vector(14262,AMPL_WIDTH),
conv_std_logic_vector(14265,AMPL_WIDTH),
conv_std_logic_vector(14268,AMPL_WIDTH),
conv_std_logic_vector(14270,AMPL_WIDTH),
conv_std_logic_vector(14273,AMPL_WIDTH),
conv_std_logic_vector(14276,AMPL_WIDTH),
conv_std_logic_vector(14279,AMPL_WIDTH),
conv_std_logic_vector(14282,AMPL_WIDTH),
conv_std_logic_vector(14285,AMPL_WIDTH),
conv_std_logic_vector(14287,AMPL_WIDTH),
conv_std_logic_vector(14290,AMPL_WIDTH),
conv_std_logic_vector(14293,AMPL_WIDTH),
conv_std_logic_vector(14296,AMPL_WIDTH),
conv_std_logic_vector(14299,AMPL_WIDTH),
conv_std_logic_vector(14302,AMPL_WIDTH),
conv_std_logic_vector(14304,AMPL_WIDTH),
conv_std_logic_vector(14307,AMPL_WIDTH),
conv_std_logic_vector(14310,AMPL_WIDTH),
conv_std_logic_vector(14313,AMPL_WIDTH),
conv_std_logic_vector(14316,AMPL_WIDTH),
conv_std_logic_vector(14318,AMPL_WIDTH),
conv_std_logic_vector(14321,AMPL_WIDTH),
conv_std_logic_vector(14324,AMPL_WIDTH),
conv_std_logic_vector(14327,AMPL_WIDTH),
conv_std_logic_vector(14330,AMPL_WIDTH),
conv_std_logic_vector(14333,AMPL_WIDTH),
conv_std_logic_vector(14335,AMPL_WIDTH),
conv_std_logic_vector(14338,AMPL_WIDTH),
conv_std_logic_vector(14341,AMPL_WIDTH),
conv_std_logic_vector(14344,AMPL_WIDTH),
conv_std_logic_vector(14347,AMPL_WIDTH),
conv_std_logic_vector(14350,AMPL_WIDTH),
conv_std_logic_vector(14352,AMPL_WIDTH),
conv_std_logic_vector(14355,AMPL_WIDTH),
conv_std_logic_vector(14358,AMPL_WIDTH),
conv_std_logic_vector(14361,AMPL_WIDTH),
conv_std_logic_vector(14364,AMPL_WIDTH),
conv_std_logic_vector(14366,AMPL_WIDTH),
conv_std_logic_vector(14369,AMPL_WIDTH),
conv_std_logic_vector(14372,AMPL_WIDTH),
conv_std_logic_vector(14375,AMPL_WIDTH),
conv_std_logic_vector(14378,AMPL_WIDTH),
conv_std_logic_vector(14381,AMPL_WIDTH),
conv_std_logic_vector(14383,AMPL_WIDTH),
conv_std_logic_vector(14386,AMPL_WIDTH),
conv_std_logic_vector(14389,AMPL_WIDTH),
conv_std_logic_vector(14392,AMPL_WIDTH),
conv_std_logic_vector(14395,AMPL_WIDTH),
conv_std_logic_vector(14398,AMPL_WIDTH),
conv_std_logic_vector(14400,AMPL_WIDTH),
conv_std_logic_vector(14403,AMPL_WIDTH),
conv_std_logic_vector(14406,AMPL_WIDTH),
conv_std_logic_vector(14409,AMPL_WIDTH),
conv_std_logic_vector(14412,AMPL_WIDTH),
conv_std_logic_vector(14414,AMPL_WIDTH),
conv_std_logic_vector(14417,AMPL_WIDTH),
conv_std_logic_vector(14420,AMPL_WIDTH),
conv_std_logic_vector(14423,AMPL_WIDTH),
conv_std_logic_vector(14426,AMPL_WIDTH),
conv_std_logic_vector(14429,AMPL_WIDTH),
conv_std_logic_vector(14431,AMPL_WIDTH),
conv_std_logic_vector(14434,AMPL_WIDTH),
conv_std_logic_vector(14437,AMPL_WIDTH),
conv_std_logic_vector(14440,AMPL_WIDTH),
conv_std_logic_vector(14443,AMPL_WIDTH),
conv_std_logic_vector(14445,AMPL_WIDTH),
conv_std_logic_vector(14448,AMPL_WIDTH),
conv_std_logic_vector(14451,AMPL_WIDTH),
conv_std_logic_vector(14454,AMPL_WIDTH),
conv_std_logic_vector(14457,AMPL_WIDTH),
conv_std_logic_vector(14460,AMPL_WIDTH),
conv_std_logic_vector(14462,AMPL_WIDTH),
conv_std_logic_vector(14465,AMPL_WIDTH),
conv_std_logic_vector(14468,AMPL_WIDTH),
conv_std_logic_vector(14471,AMPL_WIDTH),
conv_std_logic_vector(14474,AMPL_WIDTH),
conv_std_logic_vector(14477,AMPL_WIDTH),
conv_std_logic_vector(14479,AMPL_WIDTH),
conv_std_logic_vector(14482,AMPL_WIDTH),
conv_std_logic_vector(14485,AMPL_WIDTH),
conv_std_logic_vector(14488,AMPL_WIDTH),
conv_std_logic_vector(14491,AMPL_WIDTH),
conv_std_logic_vector(14493,AMPL_WIDTH),
conv_std_logic_vector(14496,AMPL_WIDTH),
conv_std_logic_vector(14499,AMPL_WIDTH),
conv_std_logic_vector(14502,AMPL_WIDTH),
conv_std_logic_vector(14505,AMPL_WIDTH),
conv_std_logic_vector(14507,AMPL_WIDTH),
conv_std_logic_vector(14510,AMPL_WIDTH),
conv_std_logic_vector(14513,AMPL_WIDTH),
conv_std_logic_vector(14516,AMPL_WIDTH),
conv_std_logic_vector(14519,AMPL_WIDTH),
conv_std_logic_vector(14522,AMPL_WIDTH),
conv_std_logic_vector(14524,AMPL_WIDTH),
conv_std_logic_vector(14527,AMPL_WIDTH),
conv_std_logic_vector(14530,AMPL_WIDTH),
conv_std_logic_vector(14533,AMPL_WIDTH),
conv_std_logic_vector(14536,AMPL_WIDTH),
conv_std_logic_vector(14538,AMPL_WIDTH),
conv_std_logic_vector(14541,AMPL_WIDTH),
conv_std_logic_vector(14544,AMPL_WIDTH),
conv_std_logic_vector(14547,AMPL_WIDTH),
conv_std_logic_vector(14550,AMPL_WIDTH),
conv_std_logic_vector(14553,AMPL_WIDTH),
conv_std_logic_vector(14555,AMPL_WIDTH),
conv_std_logic_vector(14558,AMPL_WIDTH),
conv_std_logic_vector(14561,AMPL_WIDTH),
conv_std_logic_vector(14564,AMPL_WIDTH),
conv_std_logic_vector(14567,AMPL_WIDTH),
conv_std_logic_vector(14569,AMPL_WIDTH),
conv_std_logic_vector(14572,AMPL_WIDTH),
conv_std_logic_vector(14575,AMPL_WIDTH),
conv_std_logic_vector(14578,AMPL_WIDTH),
conv_std_logic_vector(14581,AMPL_WIDTH),
conv_std_logic_vector(14584,AMPL_WIDTH),
conv_std_logic_vector(14586,AMPL_WIDTH),
conv_std_logic_vector(14589,AMPL_WIDTH),
conv_std_logic_vector(14592,AMPL_WIDTH),
conv_std_logic_vector(14595,AMPL_WIDTH),
conv_std_logic_vector(14598,AMPL_WIDTH),
conv_std_logic_vector(14600,AMPL_WIDTH),
conv_std_logic_vector(14603,AMPL_WIDTH),
conv_std_logic_vector(14606,AMPL_WIDTH),
conv_std_logic_vector(14609,AMPL_WIDTH),
conv_std_logic_vector(14612,AMPL_WIDTH),
conv_std_logic_vector(14614,AMPL_WIDTH),
conv_std_logic_vector(14617,AMPL_WIDTH),
conv_std_logic_vector(14620,AMPL_WIDTH),
conv_std_logic_vector(14623,AMPL_WIDTH),
conv_std_logic_vector(14626,AMPL_WIDTH),
conv_std_logic_vector(14628,AMPL_WIDTH),
conv_std_logic_vector(14631,AMPL_WIDTH),
conv_std_logic_vector(14634,AMPL_WIDTH),
conv_std_logic_vector(14637,AMPL_WIDTH),
conv_std_logic_vector(14640,AMPL_WIDTH),
conv_std_logic_vector(14643,AMPL_WIDTH),
conv_std_logic_vector(14645,AMPL_WIDTH),
conv_std_logic_vector(14648,AMPL_WIDTH),
conv_std_logic_vector(14651,AMPL_WIDTH),
conv_std_logic_vector(14654,AMPL_WIDTH),
conv_std_logic_vector(14657,AMPL_WIDTH),
conv_std_logic_vector(14659,AMPL_WIDTH),
conv_std_logic_vector(14662,AMPL_WIDTH),
conv_std_logic_vector(14665,AMPL_WIDTH),
conv_std_logic_vector(14668,AMPL_WIDTH),
conv_std_logic_vector(14671,AMPL_WIDTH),
conv_std_logic_vector(14673,AMPL_WIDTH),
conv_std_logic_vector(14676,AMPL_WIDTH),
conv_std_logic_vector(14679,AMPL_WIDTH),
conv_std_logic_vector(14682,AMPL_WIDTH),
conv_std_logic_vector(14685,AMPL_WIDTH),
conv_std_logic_vector(14688,AMPL_WIDTH),
conv_std_logic_vector(14690,AMPL_WIDTH),
conv_std_logic_vector(14693,AMPL_WIDTH),
conv_std_logic_vector(14696,AMPL_WIDTH),
conv_std_logic_vector(14699,AMPL_WIDTH),
conv_std_logic_vector(14702,AMPL_WIDTH),
conv_std_logic_vector(14704,AMPL_WIDTH),
conv_std_logic_vector(14707,AMPL_WIDTH),
conv_std_logic_vector(14710,AMPL_WIDTH),
conv_std_logic_vector(14713,AMPL_WIDTH),
conv_std_logic_vector(14716,AMPL_WIDTH),
conv_std_logic_vector(14718,AMPL_WIDTH),
conv_std_logic_vector(14721,AMPL_WIDTH),
conv_std_logic_vector(14724,AMPL_WIDTH),
conv_std_logic_vector(14727,AMPL_WIDTH),
conv_std_logic_vector(14730,AMPL_WIDTH),
conv_std_logic_vector(14732,AMPL_WIDTH),
conv_std_logic_vector(14735,AMPL_WIDTH),
conv_std_logic_vector(14738,AMPL_WIDTH),
conv_std_logic_vector(14741,AMPL_WIDTH),
conv_std_logic_vector(14744,AMPL_WIDTH),
conv_std_logic_vector(14746,AMPL_WIDTH),
conv_std_logic_vector(14749,AMPL_WIDTH),
conv_std_logic_vector(14752,AMPL_WIDTH),
conv_std_logic_vector(14755,AMPL_WIDTH),
conv_std_logic_vector(14758,AMPL_WIDTH),
conv_std_logic_vector(14760,AMPL_WIDTH),
conv_std_logic_vector(14763,AMPL_WIDTH),
conv_std_logic_vector(14766,AMPL_WIDTH),
conv_std_logic_vector(14769,AMPL_WIDTH),
conv_std_logic_vector(14772,AMPL_WIDTH),
conv_std_logic_vector(14774,AMPL_WIDTH),
conv_std_logic_vector(14777,AMPL_WIDTH),
conv_std_logic_vector(14780,AMPL_WIDTH),
conv_std_logic_vector(14783,AMPL_WIDTH),
conv_std_logic_vector(14786,AMPL_WIDTH),
conv_std_logic_vector(14789,AMPL_WIDTH),
conv_std_logic_vector(14791,AMPL_WIDTH),
conv_std_logic_vector(14794,AMPL_WIDTH),
conv_std_logic_vector(14797,AMPL_WIDTH),
conv_std_logic_vector(14800,AMPL_WIDTH),
conv_std_logic_vector(14803,AMPL_WIDTH),
conv_std_logic_vector(14805,AMPL_WIDTH),
conv_std_logic_vector(14808,AMPL_WIDTH),
conv_std_logic_vector(14811,AMPL_WIDTH),
conv_std_logic_vector(14814,AMPL_WIDTH),
conv_std_logic_vector(14817,AMPL_WIDTH),
conv_std_logic_vector(14819,AMPL_WIDTH),
conv_std_logic_vector(14822,AMPL_WIDTH),
conv_std_logic_vector(14825,AMPL_WIDTH),
conv_std_logic_vector(14828,AMPL_WIDTH),
conv_std_logic_vector(14831,AMPL_WIDTH),
conv_std_logic_vector(14833,AMPL_WIDTH),
conv_std_logic_vector(14836,AMPL_WIDTH),
conv_std_logic_vector(14839,AMPL_WIDTH),
conv_std_logic_vector(14842,AMPL_WIDTH),
conv_std_logic_vector(14845,AMPL_WIDTH),
conv_std_logic_vector(14847,AMPL_WIDTH),
conv_std_logic_vector(14850,AMPL_WIDTH),
conv_std_logic_vector(14853,AMPL_WIDTH),
conv_std_logic_vector(14856,AMPL_WIDTH),
conv_std_logic_vector(14859,AMPL_WIDTH),
conv_std_logic_vector(14861,AMPL_WIDTH),
conv_std_logic_vector(14864,AMPL_WIDTH),
conv_std_logic_vector(14867,AMPL_WIDTH),
conv_std_logic_vector(14870,AMPL_WIDTH),
conv_std_logic_vector(14873,AMPL_WIDTH),
conv_std_logic_vector(14875,AMPL_WIDTH),
conv_std_logic_vector(14878,AMPL_WIDTH),
conv_std_logic_vector(14881,AMPL_WIDTH),
conv_std_logic_vector(14884,AMPL_WIDTH),
conv_std_logic_vector(14887,AMPL_WIDTH),
conv_std_logic_vector(14889,AMPL_WIDTH),
conv_std_logic_vector(14892,AMPL_WIDTH),
conv_std_logic_vector(14895,AMPL_WIDTH),
conv_std_logic_vector(14898,AMPL_WIDTH),
conv_std_logic_vector(14901,AMPL_WIDTH),
conv_std_logic_vector(14903,AMPL_WIDTH),
conv_std_logic_vector(14906,AMPL_WIDTH),
conv_std_logic_vector(14909,AMPL_WIDTH),
conv_std_logic_vector(14912,AMPL_WIDTH),
conv_std_logic_vector(14915,AMPL_WIDTH),
conv_std_logic_vector(14917,AMPL_WIDTH),
conv_std_logic_vector(14920,AMPL_WIDTH),
conv_std_logic_vector(14923,AMPL_WIDTH),
conv_std_logic_vector(14926,AMPL_WIDTH),
conv_std_logic_vector(14929,AMPL_WIDTH),
conv_std_logic_vector(14931,AMPL_WIDTH),
conv_std_logic_vector(14934,AMPL_WIDTH),
conv_std_logic_vector(14937,AMPL_WIDTH),
conv_std_logic_vector(14940,AMPL_WIDTH),
conv_std_logic_vector(14942,AMPL_WIDTH),
conv_std_logic_vector(14945,AMPL_WIDTH),
conv_std_logic_vector(14948,AMPL_WIDTH),
conv_std_logic_vector(14951,AMPL_WIDTH),
conv_std_logic_vector(14954,AMPL_WIDTH),
conv_std_logic_vector(14956,AMPL_WIDTH),
conv_std_logic_vector(14959,AMPL_WIDTH),
conv_std_logic_vector(14962,AMPL_WIDTH),
conv_std_logic_vector(14965,AMPL_WIDTH),
conv_std_logic_vector(14968,AMPL_WIDTH),
conv_std_logic_vector(14970,AMPL_WIDTH),
conv_std_logic_vector(14973,AMPL_WIDTH),
conv_std_logic_vector(14976,AMPL_WIDTH),
conv_std_logic_vector(14979,AMPL_WIDTH),
conv_std_logic_vector(14982,AMPL_WIDTH),
conv_std_logic_vector(14984,AMPL_WIDTH),
conv_std_logic_vector(14987,AMPL_WIDTH),
conv_std_logic_vector(14990,AMPL_WIDTH),
conv_std_logic_vector(14993,AMPL_WIDTH),
conv_std_logic_vector(14996,AMPL_WIDTH),
conv_std_logic_vector(14998,AMPL_WIDTH),
conv_std_logic_vector(15001,AMPL_WIDTH),
conv_std_logic_vector(15004,AMPL_WIDTH),
conv_std_logic_vector(15007,AMPL_WIDTH),
conv_std_logic_vector(15010,AMPL_WIDTH),
conv_std_logic_vector(15012,AMPL_WIDTH),
conv_std_logic_vector(15015,AMPL_WIDTH),
conv_std_logic_vector(15018,AMPL_WIDTH),
conv_std_logic_vector(15021,AMPL_WIDTH),
conv_std_logic_vector(15024,AMPL_WIDTH),
conv_std_logic_vector(15026,AMPL_WIDTH),
conv_std_logic_vector(15029,AMPL_WIDTH),
conv_std_logic_vector(15032,AMPL_WIDTH),
conv_std_logic_vector(15035,AMPL_WIDTH),
conv_std_logic_vector(15037,AMPL_WIDTH),
conv_std_logic_vector(15040,AMPL_WIDTH),
conv_std_logic_vector(15043,AMPL_WIDTH),
conv_std_logic_vector(15046,AMPL_WIDTH),
conv_std_logic_vector(15049,AMPL_WIDTH),
conv_std_logic_vector(15051,AMPL_WIDTH),
conv_std_logic_vector(15054,AMPL_WIDTH),
conv_std_logic_vector(15057,AMPL_WIDTH),
conv_std_logic_vector(15060,AMPL_WIDTH),
conv_std_logic_vector(15063,AMPL_WIDTH),
conv_std_logic_vector(15065,AMPL_WIDTH),
conv_std_logic_vector(15068,AMPL_WIDTH),
conv_std_logic_vector(15071,AMPL_WIDTH),
conv_std_logic_vector(15074,AMPL_WIDTH),
conv_std_logic_vector(15077,AMPL_WIDTH),
conv_std_logic_vector(15079,AMPL_WIDTH),
conv_std_logic_vector(15082,AMPL_WIDTH),
conv_std_logic_vector(15085,AMPL_WIDTH),
conv_std_logic_vector(15088,AMPL_WIDTH),
conv_std_logic_vector(15090,AMPL_WIDTH),
conv_std_logic_vector(15093,AMPL_WIDTH),
conv_std_logic_vector(15096,AMPL_WIDTH),
conv_std_logic_vector(15099,AMPL_WIDTH),
conv_std_logic_vector(15102,AMPL_WIDTH),
conv_std_logic_vector(15104,AMPL_WIDTH),
conv_std_logic_vector(15107,AMPL_WIDTH),
conv_std_logic_vector(15110,AMPL_WIDTH),
conv_std_logic_vector(15113,AMPL_WIDTH),
conv_std_logic_vector(15116,AMPL_WIDTH),
conv_std_logic_vector(15118,AMPL_WIDTH),
conv_std_logic_vector(15121,AMPL_WIDTH),
conv_std_logic_vector(15124,AMPL_WIDTH),
conv_std_logic_vector(15127,AMPL_WIDTH),
conv_std_logic_vector(15129,AMPL_WIDTH),
conv_std_logic_vector(15132,AMPL_WIDTH),
conv_std_logic_vector(15135,AMPL_WIDTH),
conv_std_logic_vector(15138,AMPL_WIDTH),
conv_std_logic_vector(15141,AMPL_WIDTH),
conv_std_logic_vector(15143,AMPL_WIDTH),
conv_std_logic_vector(15146,AMPL_WIDTH),
conv_std_logic_vector(15149,AMPL_WIDTH),
conv_std_logic_vector(15152,AMPL_WIDTH),
conv_std_logic_vector(15155,AMPL_WIDTH),
conv_std_logic_vector(15157,AMPL_WIDTH),
conv_std_logic_vector(15160,AMPL_WIDTH),
conv_std_logic_vector(15163,AMPL_WIDTH),
conv_std_logic_vector(15166,AMPL_WIDTH),
conv_std_logic_vector(15168,AMPL_WIDTH),
conv_std_logic_vector(15171,AMPL_WIDTH),
conv_std_logic_vector(15174,AMPL_WIDTH),
conv_std_logic_vector(15177,AMPL_WIDTH),
conv_std_logic_vector(15180,AMPL_WIDTH),
conv_std_logic_vector(15182,AMPL_WIDTH),
conv_std_logic_vector(15185,AMPL_WIDTH),
conv_std_logic_vector(15188,AMPL_WIDTH),
conv_std_logic_vector(15191,AMPL_WIDTH),
conv_std_logic_vector(15194,AMPL_WIDTH),
conv_std_logic_vector(15196,AMPL_WIDTH),
conv_std_logic_vector(15199,AMPL_WIDTH),
conv_std_logic_vector(15202,AMPL_WIDTH),
conv_std_logic_vector(15205,AMPL_WIDTH),
conv_std_logic_vector(15207,AMPL_WIDTH),
conv_std_logic_vector(15210,AMPL_WIDTH),
conv_std_logic_vector(15213,AMPL_WIDTH),
conv_std_logic_vector(15216,AMPL_WIDTH),
conv_std_logic_vector(15219,AMPL_WIDTH),
conv_std_logic_vector(15221,AMPL_WIDTH),
conv_std_logic_vector(15224,AMPL_WIDTH),
conv_std_logic_vector(15227,AMPL_WIDTH),
conv_std_logic_vector(15230,AMPL_WIDTH),
conv_std_logic_vector(15233,AMPL_WIDTH),
conv_std_logic_vector(15235,AMPL_WIDTH),
conv_std_logic_vector(15238,AMPL_WIDTH),
conv_std_logic_vector(15241,AMPL_WIDTH),
conv_std_logic_vector(15244,AMPL_WIDTH),
conv_std_logic_vector(15246,AMPL_WIDTH),
conv_std_logic_vector(15249,AMPL_WIDTH),
conv_std_logic_vector(15252,AMPL_WIDTH),
conv_std_logic_vector(15255,AMPL_WIDTH),
conv_std_logic_vector(15258,AMPL_WIDTH),
conv_std_logic_vector(15260,AMPL_WIDTH),
conv_std_logic_vector(15263,AMPL_WIDTH),
conv_std_logic_vector(15266,AMPL_WIDTH),
conv_std_logic_vector(15269,AMPL_WIDTH),
conv_std_logic_vector(15271,AMPL_WIDTH),
conv_std_logic_vector(15274,AMPL_WIDTH),
conv_std_logic_vector(15277,AMPL_WIDTH),
conv_std_logic_vector(15280,AMPL_WIDTH),
conv_std_logic_vector(15283,AMPL_WIDTH),
conv_std_logic_vector(15285,AMPL_WIDTH),
conv_std_logic_vector(15288,AMPL_WIDTH),
conv_std_logic_vector(15291,AMPL_WIDTH),
conv_std_logic_vector(15294,AMPL_WIDTH),
conv_std_logic_vector(15296,AMPL_WIDTH),
conv_std_logic_vector(15299,AMPL_WIDTH),
conv_std_logic_vector(15302,AMPL_WIDTH),
conv_std_logic_vector(15305,AMPL_WIDTH),
conv_std_logic_vector(15308,AMPL_WIDTH),
conv_std_logic_vector(15310,AMPL_WIDTH),
conv_std_logic_vector(15313,AMPL_WIDTH),
conv_std_logic_vector(15316,AMPL_WIDTH),
conv_std_logic_vector(15319,AMPL_WIDTH),
conv_std_logic_vector(15321,AMPL_WIDTH),
conv_std_logic_vector(15324,AMPL_WIDTH),
conv_std_logic_vector(15327,AMPL_WIDTH),
conv_std_logic_vector(15330,AMPL_WIDTH),
conv_std_logic_vector(15333,AMPL_WIDTH),
conv_std_logic_vector(15335,AMPL_WIDTH),
conv_std_logic_vector(15338,AMPL_WIDTH),
conv_std_logic_vector(15341,AMPL_WIDTH),
conv_std_logic_vector(15344,AMPL_WIDTH),
conv_std_logic_vector(15346,AMPL_WIDTH),
conv_std_logic_vector(15349,AMPL_WIDTH),
conv_std_logic_vector(15352,AMPL_WIDTH),
conv_std_logic_vector(15355,AMPL_WIDTH),
conv_std_logic_vector(15358,AMPL_WIDTH),
conv_std_logic_vector(15360,AMPL_WIDTH),
conv_std_logic_vector(15363,AMPL_WIDTH),
conv_std_logic_vector(15366,AMPL_WIDTH),
conv_std_logic_vector(15369,AMPL_WIDTH),
conv_std_logic_vector(15371,AMPL_WIDTH),
conv_std_logic_vector(15374,AMPL_WIDTH),
conv_std_logic_vector(15377,AMPL_WIDTH),
conv_std_logic_vector(15380,AMPL_WIDTH),
conv_std_logic_vector(15382,AMPL_WIDTH),
conv_std_logic_vector(15385,AMPL_WIDTH),
conv_std_logic_vector(15388,AMPL_WIDTH),
conv_std_logic_vector(15391,AMPL_WIDTH),
conv_std_logic_vector(15394,AMPL_WIDTH),
conv_std_logic_vector(15396,AMPL_WIDTH),
conv_std_logic_vector(15399,AMPL_WIDTH),
conv_std_logic_vector(15402,AMPL_WIDTH),
conv_std_logic_vector(15405,AMPL_WIDTH),
conv_std_logic_vector(15407,AMPL_WIDTH),
conv_std_logic_vector(15410,AMPL_WIDTH),
conv_std_logic_vector(15413,AMPL_WIDTH),
conv_std_logic_vector(15416,AMPL_WIDTH),
conv_std_logic_vector(15419,AMPL_WIDTH),
conv_std_logic_vector(15421,AMPL_WIDTH),
conv_std_logic_vector(15424,AMPL_WIDTH),
conv_std_logic_vector(15427,AMPL_WIDTH),
conv_std_logic_vector(15430,AMPL_WIDTH),
conv_std_logic_vector(15432,AMPL_WIDTH),
conv_std_logic_vector(15435,AMPL_WIDTH),
conv_std_logic_vector(15438,AMPL_WIDTH),
conv_std_logic_vector(15441,AMPL_WIDTH),
conv_std_logic_vector(15443,AMPL_WIDTH),
conv_std_logic_vector(15446,AMPL_WIDTH),
conv_std_logic_vector(15449,AMPL_WIDTH),
conv_std_logic_vector(15452,AMPL_WIDTH),
conv_std_logic_vector(15455,AMPL_WIDTH),
conv_std_logic_vector(15457,AMPL_WIDTH),
conv_std_logic_vector(15460,AMPL_WIDTH),
conv_std_logic_vector(15463,AMPL_WIDTH),
conv_std_logic_vector(15466,AMPL_WIDTH),
conv_std_logic_vector(15468,AMPL_WIDTH),
conv_std_logic_vector(15471,AMPL_WIDTH),
conv_std_logic_vector(15474,AMPL_WIDTH),
conv_std_logic_vector(15477,AMPL_WIDTH),
conv_std_logic_vector(15479,AMPL_WIDTH),
conv_std_logic_vector(15482,AMPL_WIDTH),
conv_std_logic_vector(15485,AMPL_WIDTH),
conv_std_logic_vector(15488,AMPL_WIDTH),
conv_std_logic_vector(15491,AMPL_WIDTH),
conv_std_logic_vector(15493,AMPL_WIDTH),
conv_std_logic_vector(15496,AMPL_WIDTH),
conv_std_logic_vector(15499,AMPL_WIDTH),
conv_std_logic_vector(15502,AMPL_WIDTH),
conv_std_logic_vector(15504,AMPL_WIDTH),
conv_std_logic_vector(15507,AMPL_WIDTH),
conv_std_logic_vector(15510,AMPL_WIDTH),
conv_std_logic_vector(15513,AMPL_WIDTH),
conv_std_logic_vector(15515,AMPL_WIDTH),
conv_std_logic_vector(15518,AMPL_WIDTH),
conv_std_logic_vector(15521,AMPL_WIDTH),
conv_std_logic_vector(15524,AMPL_WIDTH),
conv_std_logic_vector(15527,AMPL_WIDTH),
conv_std_logic_vector(15529,AMPL_WIDTH),
conv_std_logic_vector(15532,AMPL_WIDTH),
conv_std_logic_vector(15535,AMPL_WIDTH),
conv_std_logic_vector(15538,AMPL_WIDTH),
conv_std_logic_vector(15540,AMPL_WIDTH),
conv_std_logic_vector(15543,AMPL_WIDTH),
conv_std_logic_vector(15546,AMPL_WIDTH),
conv_std_logic_vector(15549,AMPL_WIDTH),
conv_std_logic_vector(15551,AMPL_WIDTH),
conv_std_logic_vector(15554,AMPL_WIDTH),
conv_std_logic_vector(15557,AMPL_WIDTH),
conv_std_logic_vector(15560,AMPL_WIDTH),
conv_std_logic_vector(15562,AMPL_WIDTH),
conv_std_logic_vector(15565,AMPL_WIDTH),
conv_std_logic_vector(15568,AMPL_WIDTH),
conv_std_logic_vector(15571,AMPL_WIDTH),
conv_std_logic_vector(15574,AMPL_WIDTH),
conv_std_logic_vector(15576,AMPL_WIDTH),
conv_std_logic_vector(15579,AMPL_WIDTH),
conv_std_logic_vector(15582,AMPL_WIDTH),
conv_std_logic_vector(15585,AMPL_WIDTH),
conv_std_logic_vector(15587,AMPL_WIDTH),
conv_std_logic_vector(15590,AMPL_WIDTH),
conv_std_logic_vector(15593,AMPL_WIDTH),
conv_std_logic_vector(15596,AMPL_WIDTH),
conv_std_logic_vector(15598,AMPL_WIDTH),
conv_std_logic_vector(15601,AMPL_WIDTH),
conv_std_logic_vector(15604,AMPL_WIDTH),
conv_std_logic_vector(15607,AMPL_WIDTH),
conv_std_logic_vector(15609,AMPL_WIDTH),
conv_std_logic_vector(15612,AMPL_WIDTH),
conv_std_logic_vector(15615,AMPL_WIDTH),
conv_std_logic_vector(15618,AMPL_WIDTH),
conv_std_logic_vector(15621,AMPL_WIDTH),
conv_std_logic_vector(15623,AMPL_WIDTH),
conv_std_logic_vector(15626,AMPL_WIDTH),
conv_std_logic_vector(15629,AMPL_WIDTH),
conv_std_logic_vector(15632,AMPL_WIDTH),
conv_std_logic_vector(15634,AMPL_WIDTH),
conv_std_logic_vector(15637,AMPL_WIDTH),
conv_std_logic_vector(15640,AMPL_WIDTH),
conv_std_logic_vector(15643,AMPL_WIDTH),
conv_std_logic_vector(15645,AMPL_WIDTH),
conv_std_logic_vector(15648,AMPL_WIDTH),
conv_std_logic_vector(15651,AMPL_WIDTH),
conv_std_logic_vector(15654,AMPL_WIDTH),
conv_std_logic_vector(15656,AMPL_WIDTH),
conv_std_logic_vector(15659,AMPL_WIDTH),
conv_std_logic_vector(15662,AMPL_WIDTH),
conv_std_logic_vector(15665,AMPL_WIDTH),
conv_std_logic_vector(15667,AMPL_WIDTH),
conv_std_logic_vector(15670,AMPL_WIDTH),
conv_std_logic_vector(15673,AMPL_WIDTH),
conv_std_logic_vector(15676,AMPL_WIDTH),
conv_std_logic_vector(15678,AMPL_WIDTH),
conv_std_logic_vector(15681,AMPL_WIDTH),
conv_std_logic_vector(15684,AMPL_WIDTH),
conv_std_logic_vector(15687,AMPL_WIDTH),
conv_std_logic_vector(15690,AMPL_WIDTH),
conv_std_logic_vector(15692,AMPL_WIDTH),
conv_std_logic_vector(15695,AMPL_WIDTH),
conv_std_logic_vector(15698,AMPL_WIDTH),
conv_std_logic_vector(15701,AMPL_WIDTH),
conv_std_logic_vector(15703,AMPL_WIDTH),
conv_std_logic_vector(15706,AMPL_WIDTH),
conv_std_logic_vector(15709,AMPL_WIDTH),
conv_std_logic_vector(15712,AMPL_WIDTH),
conv_std_logic_vector(15714,AMPL_WIDTH),
conv_std_logic_vector(15717,AMPL_WIDTH),
conv_std_logic_vector(15720,AMPL_WIDTH),
conv_std_logic_vector(15723,AMPL_WIDTH),
conv_std_logic_vector(15725,AMPL_WIDTH),
conv_std_logic_vector(15728,AMPL_WIDTH),
conv_std_logic_vector(15731,AMPL_WIDTH),
conv_std_logic_vector(15734,AMPL_WIDTH),
conv_std_logic_vector(15736,AMPL_WIDTH),
conv_std_logic_vector(15739,AMPL_WIDTH),
conv_std_logic_vector(15742,AMPL_WIDTH),
conv_std_logic_vector(15745,AMPL_WIDTH),
conv_std_logic_vector(15747,AMPL_WIDTH),
conv_std_logic_vector(15750,AMPL_WIDTH),
conv_std_logic_vector(15753,AMPL_WIDTH),
conv_std_logic_vector(15756,AMPL_WIDTH),
conv_std_logic_vector(15758,AMPL_WIDTH),
conv_std_logic_vector(15761,AMPL_WIDTH),
conv_std_logic_vector(15764,AMPL_WIDTH),
conv_std_logic_vector(15767,AMPL_WIDTH),
conv_std_logic_vector(15769,AMPL_WIDTH),
conv_std_logic_vector(15772,AMPL_WIDTH),
conv_std_logic_vector(15775,AMPL_WIDTH),
conv_std_logic_vector(15778,AMPL_WIDTH),
conv_std_logic_vector(15780,AMPL_WIDTH),
conv_std_logic_vector(15783,AMPL_WIDTH),
conv_std_logic_vector(15786,AMPL_WIDTH),
conv_std_logic_vector(15789,AMPL_WIDTH),
conv_std_logic_vector(15791,AMPL_WIDTH),
conv_std_logic_vector(15794,AMPL_WIDTH),
conv_std_logic_vector(15797,AMPL_WIDTH),
conv_std_logic_vector(15800,AMPL_WIDTH),
conv_std_logic_vector(15802,AMPL_WIDTH),
conv_std_logic_vector(15805,AMPL_WIDTH),
conv_std_logic_vector(15808,AMPL_WIDTH),
conv_std_logic_vector(15811,AMPL_WIDTH),
conv_std_logic_vector(15813,AMPL_WIDTH),
conv_std_logic_vector(15816,AMPL_WIDTH),
conv_std_logic_vector(15819,AMPL_WIDTH),
conv_std_logic_vector(15822,AMPL_WIDTH),
conv_std_logic_vector(15824,AMPL_WIDTH),
conv_std_logic_vector(15827,AMPL_WIDTH),
conv_std_logic_vector(15830,AMPL_WIDTH),
conv_std_logic_vector(15833,AMPL_WIDTH),
conv_std_logic_vector(15835,AMPL_WIDTH),
conv_std_logic_vector(15838,AMPL_WIDTH),
conv_std_logic_vector(15841,AMPL_WIDTH),
conv_std_logic_vector(15844,AMPL_WIDTH),
conv_std_logic_vector(15846,AMPL_WIDTH),
conv_std_logic_vector(15849,AMPL_WIDTH),
conv_std_logic_vector(15852,AMPL_WIDTH),
conv_std_logic_vector(15855,AMPL_WIDTH),
conv_std_logic_vector(15857,AMPL_WIDTH),
conv_std_logic_vector(15860,AMPL_WIDTH),
conv_std_logic_vector(15863,AMPL_WIDTH),
conv_std_logic_vector(15866,AMPL_WIDTH),
conv_std_logic_vector(15868,AMPL_WIDTH),
conv_std_logic_vector(15871,AMPL_WIDTH),
conv_std_logic_vector(15874,AMPL_WIDTH),
conv_std_logic_vector(15877,AMPL_WIDTH),
conv_std_logic_vector(15879,AMPL_WIDTH),
conv_std_logic_vector(15882,AMPL_WIDTH),
conv_std_logic_vector(15885,AMPL_WIDTH),
conv_std_logic_vector(15888,AMPL_WIDTH),
conv_std_logic_vector(15890,AMPL_WIDTH),
conv_std_logic_vector(15893,AMPL_WIDTH),
conv_std_logic_vector(15896,AMPL_WIDTH),
conv_std_logic_vector(15899,AMPL_WIDTH),
conv_std_logic_vector(15901,AMPL_WIDTH),
conv_std_logic_vector(15904,AMPL_WIDTH),
conv_std_logic_vector(15907,AMPL_WIDTH),
conv_std_logic_vector(15910,AMPL_WIDTH),
conv_std_logic_vector(15912,AMPL_WIDTH),
conv_std_logic_vector(15915,AMPL_WIDTH),
conv_std_logic_vector(15918,AMPL_WIDTH),
conv_std_logic_vector(15921,AMPL_WIDTH),
conv_std_logic_vector(15923,AMPL_WIDTH),
conv_std_logic_vector(15926,AMPL_WIDTH),
conv_std_logic_vector(15929,AMPL_WIDTH),
conv_std_logic_vector(15932,AMPL_WIDTH),
conv_std_logic_vector(15934,AMPL_WIDTH),
conv_std_logic_vector(15937,AMPL_WIDTH),
conv_std_logic_vector(15940,AMPL_WIDTH),
conv_std_logic_vector(15943,AMPL_WIDTH),
conv_std_logic_vector(15945,AMPL_WIDTH),
conv_std_logic_vector(15948,AMPL_WIDTH),
conv_std_logic_vector(15951,AMPL_WIDTH),
conv_std_logic_vector(15954,AMPL_WIDTH),
conv_std_logic_vector(15956,AMPL_WIDTH),
conv_std_logic_vector(15959,AMPL_WIDTH),
conv_std_logic_vector(15962,AMPL_WIDTH),
conv_std_logic_vector(15965,AMPL_WIDTH),
conv_std_logic_vector(15967,AMPL_WIDTH),
conv_std_logic_vector(15970,AMPL_WIDTH),
conv_std_logic_vector(15973,AMPL_WIDTH),
conv_std_logic_vector(15976,AMPL_WIDTH),
conv_std_logic_vector(15978,AMPL_WIDTH),
conv_std_logic_vector(15981,AMPL_WIDTH),
conv_std_logic_vector(15984,AMPL_WIDTH),
conv_std_logic_vector(15987,AMPL_WIDTH),
conv_std_logic_vector(15989,AMPL_WIDTH),
conv_std_logic_vector(15992,AMPL_WIDTH),
conv_std_logic_vector(15995,AMPL_WIDTH),
conv_std_logic_vector(15997,AMPL_WIDTH),
conv_std_logic_vector(16000,AMPL_WIDTH),
conv_std_logic_vector(16003,AMPL_WIDTH),
conv_std_logic_vector(16006,AMPL_WIDTH),
conv_std_logic_vector(16008,AMPL_WIDTH),
conv_std_logic_vector(16011,AMPL_WIDTH),
conv_std_logic_vector(16014,AMPL_WIDTH),
conv_std_logic_vector(16017,AMPL_WIDTH),
conv_std_logic_vector(16019,AMPL_WIDTH),
conv_std_logic_vector(16022,AMPL_WIDTH),
conv_std_logic_vector(16025,AMPL_WIDTH),
conv_std_logic_vector(16028,AMPL_WIDTH),
conv_std_logic_vector(16030,AMPL_WIDTH),
conv_std_logic_vector(16033,AMPL_WIDTH),
conv_std_logic_vector(16036,AMPL_WIDTH),
conv_std_logic_vector(16039,AMPL_WIDTH),
conv_std_logic_vector(16041,AMPL_WIDTH),
conv_std_logic_vector(16044,AMPL_WIDTH),
conv_std_logic_vector(16047,AMPL_WIDTH),
conv_std_logic_vector(16050,AMPL_WIDTH),
conv_std_logic_vector(16052,AMPL_WIDTH),
conv_std_logic_vector(16055,AMPL_WIDTH),
conv_std_logic_vector(16058,AMPL_WIDTH),
conv_std_logic_vector(16061,AMPL_WIDTH),
conv_std_logic_vector(16063,AMPL_WIDTH),
conv_std_logic_vector(16066,AMPL_WIDTH),
conv_std_logic_vector(16069,AMPL_WIDTH),
conv_std_logic_vector(16071,AMPL_WIDTH),
conv_std_logic_vector(16074,AMPL_WIDTH),
conv_std_logic_vector(16077,AMPL_WIDTH),
conv_std_logic_vector(16080,AMPL_WIDTH),
conv_std_logic_vector(16082,AMPL_WIDTH),
conv_std_logic_vector(16085,AMPL_WIDTH),
conv_std_logic_vector(16088,AMPL_WIDTH),
conv_std_logic_vector(16091,AMPL_WIDTH),
conv_std_logic_vector(16093,AMPL_WIDTH),
conv_std_logic_vector(16096,AMPL_WIDTH),
conv_std_logic_vector(16099,AMPL_WIDTH),
conv_std_logic_vector(16102,AMPL_WIDTH),
conv_std_logic_vector(16104,AMPL_WIDTH),
conv_std_logic_vector(16107,AMPL_WIDTH),
conv_std_logic_vector(16110,AMPL_WIDTH),
conv_std_logic_vector(16113,AMPL_WIDTH),
conv_std_logic_vector(16115,AMPL_WIDTH),
conv_std_logic_vector(16118,AMPL_WIDTH),
conv_std_logic_vector(16121,AMPL_WIDTH),
conv_std_logic_vector(16123,AMPL_WIDTH),
conv_std_logic_vector(16126,AMPL_WIDTH),
conv_std_logic_vector(16129,AMPL_WIDTH),
conv_std_logic_vector(16132,AMPL_WIDTH),
conv_std_logic_vector(16134,AMPL_WIDTH),
conv_std_logic_vector(16137,AMPL_WIDTH),
conv_std_logic_vector(16140,AMPL_WIDTH),
conv_std_logic_vector(16143,AMPL_WIDTH),
conv_std_logic_vector(16145,AMPL_WIDTH),
conv_std_logic_vector(16148,AMPL_WIDTH),
conv_std_logic_vector(16151,AMPL_WIDTH),
conv_std_logic_vector(16154,AMPL_WIDTH),
conv_std_logic_vector(16156,AMPL_WIDTH),
conv_std_logic_vector(16159,AMPL_WIDTH),
conv_std_logic_vector(16162,AMPL_WIDTH),
conv_std_logic_vector(16164,AMPL_WIDTH),
conv_std_logic_vector(16167,AMPL_WIDTH),
conv_std_logic_vector(16170,AMPL_WIDTH),
conv_std_logic_vector(16173,AMPL_WIDTH),
conv_std_logic_vector(16175,AMPL_WIDTH),
conv_std_logic_vector(16178,AMPL_WIDTH),
conv_std_logic_vector(16181,AMPL_WIDTH),
conv_std_logic_vector(16184,AMPL_WIDTH),
conv_std_logic_vector(16186,AMPL_WIDTH),
conv_std_logic_vector(16189,AMPL_WIDTH),
conv_std_logic_vector(16192,AMPL_WIDTH),
conv_std_logic_vector(16195,AMPL_WIDTH),
conv_std_logic_vector(16197,AMPL_WIDTH),
conv_std_logic_vector(16200,AMPL_WIDTH),
conv_std_logic_vector(16203,AMPL_WIDTH),
conv_std_logic_vector(16205,AMPL_WIDTH),
conv_std_logic_vector(16208,AMPL_WIDTH),
conv_std_logic_vector(16211,AMPL_WIDTH),
conv_std_logic_vector(16214,AMPL_WIDTH),
conv_std_logic_vector(16216,AMPL_WIDTH),
conv_std_logic_vector(16219,AMPL_WIDTH),
conv_std_logic_vector(16222,AMPL_WIDTH),
conv_std_logic_vector(16225,AMPL_WIDTH),
conv_std_logic_vector(16227,AMPL_WIDTH),
conv_std_logic_vector(16230,AMPL_WIDTH),
conv_std_logic_vector(16233,AMPL_WIDTH),
conv_std_logic_vector(16235,AMPL_WIDTH),
conv_std_logic_vector(16238,AMPL_WIDTH),
conv_std_logic_vector(16241,AMPL_WIDTH),
conv_std_logic_vector(16244,AMPL_WIDTH),
conv_std_logic_vector(16246,AMPL_WIDTH),
conv_std_logic_vector(16249,AMPL_WIDTH),
conv_std_logic_vector(16252,AMPL_WIDTH),
conv_std_logic_vector(16255,AMPL_WIDTH),
conv_std_logic_vector(16257,AMPL_WIDTH),
conv_std_logic_vector(16260,AMPL_WIDTH),
conv_std_logic_vector(16263,AMPL_WIDTH),
conv_std_logic_vector(16265,AMPL_WIDTH),
conv_std_logic_vector(16268,AMPL_WIDTH),
conv_std_logic_vector(16271,AMPL_WIDTH),
conv_std_logic_vector(16274,AMPL_WIDTH),
conv_std_logic_vector(16276,AMPL_WIDTH),
conv_std_logic_vector(16279,AMPL_WIDTH),
conv_std_logic_vector(16282,AMPL_WIDTH),
conv_std_logic_vector(16285,AMPL_WIDTH),
conv_std_logic_vector(16287,AMPL_WIDTH),
conv_std_logic_vector(16290,AMPL_WIDTH),
conv_std_logic_vector(16293,AMPL_WIDTH),
conv_std_logic_vector(16295,AMPL_WIDTH),
conv_std_logic_vector(16298,AMPL_WIDTH),
conv_std_logic_vector(16301,AMPL_WIDTH),
conv_std_logic_vector(16304,AMPL_WIDTH),
conv_std_logic_vector(16306,AMPL_WIDTH),
conv_std_logic_vector(16309,AMPL_WIDTH),
conv_std_logic_vector(16312,AMPL_WIDTH),
conv_std_logic_vector(16315,AMPL_WIDTH),
conv_std_logic_vector(16317,AMPL_WIDTH),
conv_std_logic_vector(16320,AMPL_WIDTH),
conv_std_logic_vector(16323,AMPL_WIDTH),
conv_std_logic_vector(16325,AMPL_WIDTH),
conv_std_logic_vector(16328,AMPL_WIDTH),
conv_std_logic_vector(16331,AMPL_WIDTH),
conv_std_logic_vector(16334,AMPL_WIDTH),
conv_std_logic_vector(16336,AMPL_WIDTH),
conv_std_logic_vector(16339,AMPL_WIDTH),
conv_std_logic_vector(16342,AMPL_WIDTH),
conv_std_logic_vector(16344,AMPL_WIDTH),
conv_std_logic_vector(16347,AMPL_WIDTH),
conv_std_logic_vector(16350,AMPL_WIDTH),
conv_std_logic_vector(16353,AMPL_WIDTH),
conv_std_logic_vector(16355,AMPL_WIDTH),
conv_std_logic_vector(16358,AMPL_WIDTH),
conv_std_logic_vector(16361,AMPL_WIDTH),
conv_std_logic_vector(16364,AMPL_WIDTH),
conv_std_logic_vector(16366,AMPL_WIDTH),
conv_std_logic_vector(16369,AMPL_WIDTH),
conv_std_logic_vector(16372,AMPL_WIDTH),
conv_std_logic_vector(16374,AMPL_WIDTH),
conv_std_logic_vector(16377,AMPL_WIDTH),
conv_std_logic_vector(16380,AMPL_WIDTH),
conv_std_logic_vector(16383,AMPL_WIDTH),
conv_std_logic_vector(16385,AMPL_WIDTH),
conv_std_logic_vector(16388,AMPL_WIDTH),
conv_std_logic_vector(16391,AMPL_WIDTH),
conv_std_logic_vector(16393,AMPL_WIDTH),
conv_std_logic_vector(16396,AMPL_WIDTH),
conv_std_logic_vector(16399,AMPL_WIDTH),
conv_std_logic_vector(16402,AMPL_WIDTH),
conv_std_logic_vector(16404,AMPL_WIDTH),
conv_std_logic_vector(16407,AMPL_WIDTH),
conv_std_logic_vector(16410,AMPL_WIDTH),
conv_std_logic_vector(16413,AMPL_WIDTH),
conv_std_logic_vector(16415,AMPL_WIDTH),
conv_std_logic_vector(16418,AMPL_WIDTH),
conv_std_logic_vector(16421,AMPL_WIDTH),
conv_std_logic_vector(16423,AMPL_WIDTH),
conv_std_logic_vector(16426,AMPL_WIDTH),
conv_std_logic_vector(16429,AMPL_WIDTH),
conv_std_logic_vector(16432,AMPL_WIDTH),
conv_std_logic_vector(16434,AMPL_WIDTH),
conv_std_logic_vector(16437,AMPL_WIDTH),
conv_std_logic_vector(16440,AMPL_WIDTH),
conv_std_logic_vector(16442,AMPL_WIDTH),
conv_std_logic_vector(16445,AMPL_WIDTH),
conv_std_logic_vector(16448,AMPL_WIDTH),
conv_std_logic_vector(16451,AMPL_WIDTH),
conv_std_logic_vector(16453,AMPL_WIDTH),
conv_std_logic_vector(16456,AMPL_WIDTH),
conv_std_logic_vector(16459,AMPL_WIDTH),
conv_std_logic_vector(16461,AMPL_WIDTH),
conv_std_logic_vector(16464,AMPL_WIDTH),
conv_std_logic_vector(16467,AMPL_WIDTH),
conv_std_logic_vector(16470,AMPL_WIDTH),
conv_std_logic_vector(16472,AMPL_WIDTH),
conv_std_logic_vector(16475,AMPL_WIDTH),
conv_std_logic_vector(16478,AMPL_WIDTH),
conv_std_logic_vector(16480,AMPL_WIDTH),
conv_std_logic_vector(16483,AMPL_WIDTH),
conv_std_logic_vector(16486,AMPL_WIDTH),
conv_std_logic_vector(16489,AMPL_WIDTH),
conv_std_logic_vector(16491,AMPL_WIDTH),
conv_std_logic_vector(16494,AMPL_WIDTH),
conv_std_logic_vector(16497,AMPL_WIDTH),
conv_std_logic_vector(16499,AMPL_WIDTH),
conv_std_logic_vector(16502,AMPL_WIDTH),
conv_std_logic_vector(16505,AMPL_WIDTH),
conv_std_logic_vector(16508,AMPL_WIDTH),
conv_std_logic_vector(16510,AMPL_WIDTH),
conv_std_logic_vector(16513,AMPL_WIDTH),
conv_std_logic_vector(16516,AMPL_WIDTH),
conv_std_logic_vector(16518,AMPL_WIDTH),
conv_std_logic_vector(16521,AMPL_WIDTH),
conv_std_logic_vector(16524,AMPL_WIDTH),
conv_std_logic_vector(16527,AMPL_WIDTH),
conv_std_logic_vector(16529,AMPL_WIDTH),
conv_std_logic_vector(16532,AMPL_WIDTH),
conv_std_logic_vector(16535,AMPL_WIDTH),
conv_std_logic_vector(16537,AMPL_WIDTH),
conv_std_logic_vector(16540,AMPL_WIDTH),
conv_std_logic_vector(16543,AMPL_WIDTH),
conv_std_logic_vector(16546,AMPL_WIDTH),
conv_std_logic_vector(16548,AMPL_WIDTH),
conv_std_logic_vector(16551,AMPL_WIDTH),
conv_std_logic_vector(16554,AMPL_WIDTH),
conv_std_logic_vector(16556,AMPL_WIDTH),
conv_std_logic_vector(16559,AMPL_WIDTH),
conv_std_logic_vector(16562,AMPL_WIDTH),
conv_std_logic_vector(16565,AMPL_WIDTH),
conv_std_logic_vector(16567,AMPL_WIDTH),
conv_std_logic_vector(16570,AMPL_WIDTH),
conv_std_logic_vector(16573,AMPL_WIDTH),
conv_std_logic_vector(16575,AMPL_WIDTH),
conv_std_logic_vector(16578,AMPL_WIDTH),
conv_std_logic_vector(16581,AMPL_WIDTH),
conv_std_logic_vector(16584,AMPL_WIDTH),
conv_std_logic_vector(16586,AMPL_WIDTH),
conv_std_logic_vector(16589,AMPL_WIDTH),
conv_std_logic_vector(16592,AMPL_WIDTH),
conv_std_logic_vector(16594,AMPL_WIDTH),
conv_std_logic_vector(16597,AMPL_WIDTH),
conv_std_logic_vector(16600,AMPL_WIDTH),
conv_std_logic_vector(16602,AMPL_WIDTH),
conv_std_logic_vector(16605,AMPL_WIDTH),
conv_std_logic_vector(16608,AMPL_WIDTH),
conv_std_logic_vector(16611,AMPL_WIDTH),
conv_std_logic_vector(16613,AMPL_WIDTH),
conv_std_logic_vector(16616,AMPL_WIDTH),
conv_std_logic_vector(16619,AMPL_WIDTH),
conv_std_logic_vector(16621,AMPL_WIDTH),
conv_std_logic_vector(16624,AMPL_WIDTH),
conv_std_logic_vector(16627,AMPL_WIDTH),
conv_std_logic_vector(16630,AMPL_WIDTH),
conv_std_logic_vector(16632,AMPL_WIDTH),
conv_std_logic_vector(16635,AMPL_WIDTH),
conv_std_logic_vector(16638,AMPL_WIDTH),
conv_std_logic_vector(16640,AMPL_WIDTH),
conv_std_logic_vector(16643,AMPL_WIDTH),
conv_std_logic_vector(16646,AMPL_WIDTH),
conv_std_logic_vector(16648,AMPL_WIDTH),
conv_std_logic_vector(16651,AMPL_WIDTH),
conv_std_logic_vector(16654,AMPL_WIDTH),
conv_std_logic_vector(16657,AMPL_WIDTH),
conv_std_logic_vector(16659,AMPL_WIDTH),
conv_std_logic_vector(16662,AMPL_WIDTH),
conv_std_logic_vector(16665,AMPL_WIDTH),
conv_std_logic_vector(16667,AMPL_WIDTH),
conv_std_logic_vector(16670,AMPL_WIDTH),
conv_std_logic_vector(16673,AMPL_WIDTH),
conv_std_logic_vector(16676,AMPL_WIDTH),
conv_std_logic_vector(16678,AMPL_WIDTH),
conv_std_logic_vector(16681,AMPL_WIDTH),
conv_std_logic_vector(16684,AMPL_WIDTH),
conv_std_logic_vector(16686,AMPL_WIDTH),
conv_std_logic_vector(16689,AMPL_WIDTH),
conv_std_logic_vector(16692,AMPL_WIDTH),
conv_std_logic_vector(16694,AMPL_WIDTH),
conv_std_logic_vector(16697,AMPL_WIDTH),
conv_std_logic_vector(16700,AMPL_WIDTH),
conv_std_logic_vector(16703,AMPL_WIDTH),
conv_std_logic_vector(16705,AMPL_WIDTH),
conv_std_logic_vector(16708,AMPL_WIDTH),
conv_std_logic_vector(16711,AMPL_WIDTH),
conv_std_logic_vector(16713,AMPL_WIDTH),
conv_std_logic_vector(16716,AMPL_WIDTH),
conv_std_logic_vector(16719,AMPL_WIDTH),
conv_std_logic_vector(16721,AMPL_WIDTH),
conv_std_logic_vector(16724,AMPL_WIDTH),
conv_std_logic_vector(16727,AMPL_WIDTH),
conv_std_logic_vector(16730,AMPL_WIDTH),
conv_std_logic_vector(16732,AMPL_WIDTH),
conv_std_logic_vector(16735,AMPL_WIDTH),
conv_std_logic_vector(16738,AMPL_WIDTH),
conv_std_logic_vector(16740,AMPL_WIDTH),
conv_std_logic_vector(16743,AMPL_WIDTH),
conv_std_logic_vector(16746,AMPL_WIDTH),
conv_std_logic_vector(16749,AMPL_WIDTH),
conv_std_logic_vector(16751,AMPL_WIDTH),
conv_std_logic_vector(16754,AMPL_WIDTH),
conv_std_logic_vector(16757,AMPL_WIDTH),
conv_std_logic_vector(16759,AMPL_WIDTH),
conv_std_logic_vector(16762,AMPL_WIDTH),
conv_std_logic_vector(16765,AMPL_WIDTH),
conv_std_logic_vector(16767,AMPL_WIDTH),
conv_std_logic_vector(16770,AMPL_WIDTH),
conv_std_logic_vector(16773,AMPL_WIDTH),
conv_std_logic_vector(16775,AMPL_WIDTH),
conv_std_logic_vector(16778,AMPL_WIDTH),
conv_std_logic_vector(16781,AMPL_WIDTH),
conv_std_logic_vector(16784,AMPL_WIDTH),
conv_std_logic_vector(16786,AMPL_WIDTH),
conv_std_logic_vector(16789,AMPL_WIDTH),
conv_std_logic_vector(16792,AMPL_WIDTH),
conv_std_logic_vector(16794,AMPL_WIDTH),
conv_std_logic_vector(16797,AMPL_WIDTH),
conv_std_logic_vector(16800,AMPL_WIDTH),
conv_std_logic_vector(16802,AMPL_WIDTH),
conv_std_logic_vector(16805,AMPL_WIDTH),
conv_std_logic_vector(16808,AMPL_WIDTH),
conv_std_logic_vector(16811,AMPL_WIDTH),
conv_std_logic_vector(16813,AMPL_WIDTH),
conv_std_logic_vector(16816,AMPL_WIDTH),
conv_std_logic_vector(16819,AMPL_WIDTH),
conv_std_logic_vector(16821,AMPL_WIDTH),
conv_std_logic_vector(16824,AMPL_WIDTH),
conv_std_logic_vector(16827,AMPL_WIDTH),
conv_std_logic_vector(16829,AMPL_WIDTH),
conv_std_logic_vector(16832,AMPL_WIDTH),
conv_std_logic_vector(16835,AMPL_WIDTH),
conv_std_logic_vector(16838,AMPL_WIDTH),
conv_std_logic_vector(16840,AMPL_WIDTH),
conv_std_logic_vector(16843,AMPL_WIDTH),
conv_std_logic_vector(16846,AMPL_WIDTH),
conv_std_logic_vector(16848,AMPL_WIDTH),
conv_std_logic_vector(16851,AMPL_WIDTH),
conv_std_logic_vector(16854,AMPL_WIDTH),
conv_std_logic_vector(16856,AMPL_WIDTH),
conv_std_logic_vector(16859,AMPL_WIDTH),
conv_std_logic_vector(16862,AMPL_WIDTH),
conv_std_logic_vector(16864,AMPL_WIDTH),
conv_std_logic_vector(16867,AMPL_WIDTH),
conv_std_logic_vector(16870,AMPL_WIDTH),
conv_std_logic_vector(16873,AMPL_WIDTH),
conv_std_logic_vector(16875,AMPL_WIDTH),
conv_std_logic_vector(16878,AMPL_WIDTH),
conv_std_logic_vector(16881,AMPL_WIDTH),
conv_std_logic_vector(16883,AMPL_WIDTH),
conv_std_logic_vector(16886,AMPL_WIDTH),
conv_std_logic_vector(16889,AMPL_WIDTH),
conv_std_logic_vector(16891,AMPL_WIDTH),
conv_std_logic_vector(16894,AMPL_WIDTH),
conv_std_logic_vector(16897,AMPL_WIDTH),
conv_std_logic_vector(16899,AMPL_WIDTH),
conv_std_logic_vector(16902,AMPL_WIDTH),
conv_std_logic_vector(16905,AMPL_WIDTH),
conv_std_logic_vector(16908,AMPL_WIDTH),
conv_std_logic_vector(16910,AMPL_WIDTH),
conv_std_logic_vector(16913,AMPL_WIDTH),
conv_std_logic_vector(16916,AMPL_WIDTH),
conv_std_logic_vector(16918,AMPL_WIDTH),
conv_std_logic_vector(16921,AMPL_WIDTH),
conv_std_logic_vector(16924,AMPL_WIDTH),
conv_std_logic_vector(16926,AMPL_WIDTH),
conv_std_logic_vector(16929,AMPL_WIDTH),
conv_std_logic_vector(16932,AMPL_WIDTH),
conv_std_logic_vector(16934,AMPL_WIDTH),
conv_std_logic_vector(16937,AMPL_WIDTH),
conv_std_logic_vector(16940,AMPL_WIDTH),
conv_std_logic_vector(16943,AMPL_WIDTH),
conv_std_logic_vector(16945,AMPL_WIDTH),
conv_std_logic_vector(16948,AMPL_WIDTH),
conv_std_logic_vector(16951,AMPL_WIDTH),
conv_std_logic_vector(16953,AMPL_WIDTH),
conv_std_logic_vector(16956,AMPL_WIDTH),
conv_std_logic_vector(16959,AMPL_WIDTH),
conv_std_logic_vector(16961,AMPL_WIDTH),
conv_std_logic_vector(16964,AMPL_WIDTH),
conv_std_logic_vector(16967,AMPL_WIDTH),
conv_std_logic_vector(16969,AMPL_WIDTH),
conv_std_logic_vector(16972,AMPL_WIDTH),
conv_std_logic_vector(16975,AMPL_WIDTH),
conv_std_logic_vector(16977,AMPL_WIDTH),
conv_std_logic_vector(16980,AMPL_WIDTH),
conv_std_logic_vector(16983,AMPL_WIDTH),
conv_std_logic_vector(16986,AMPL_WIDTH),
conv_std_logic_vector(16988,AMPL_WIDTH),
conv_std_logic_vector(16991,AMPL_WIDTH),
conv_std_logic_vector(16994,AMPL_WIDTH),
conv_std_logic_vector(16996,AMPL_WIDTH),
conv_std_logic_vector(16999,AMPL_WIDTH),
conv_std_logic_vector(17002,AMPL_WIDTH),
conv_std_logic_vector(17004,AMPL_WIDTH),
conv_std_logic_vector(17007,AMPL_WIDTH),
conv_std_logic_vector(17010,AMPL_WIDTH),
conv_std_logic_vector(17012,AMPL_WIDTH),
conv_std_logic_vector(17015,AMPL_WIDTH),
conv_std_logic_vector(17018,AMPL_WIDTH),
conv_std_logic_vector(17020,AMPL_WIDTH),
conv_std_logic_vector(17023,AMPL_WIDTH),
conv_std_logic_vector(17026,AMPL_WIDTH),
conv_std_logic_vector(17028,AMPL_WIDTH),
conv_std_logic_vector(17031,AMPL_WIDTH),
conv_std_logic_vector(17034,AMPL_WIDTH),
conv_std_logic_vector(17037,AMPL_WIDTH),
conv_std_logic_vector(17039,AMPL_WIDTH),
conv_std_logic_vector(17042,AMPL_WIDTH),
conv_std_logic_vector(17045,AMPL_WIDTH),
conv_std_logic_vector(17047,AMPL_WIDTH),
conv_std_logic_vector(17050,AMPL_WIDTH),
conv_std_logic_vector(17053,AMPL_WIDTH),
conv_std_logic_vector(17055,AMPL_WIDTH),
conv_std_logic_vector(17058,AMPL_WIDTH),
conv_std_logic_vector(17061,AMPL_WIDTH),
conv_std_logic_vector(17063,AMPL_WIDTH),
conv_std_logic_vector(17066,AMPL_WIDTH),
conv_std_logic_vector(17069,AMPL_WIDTH),
conv_std_logic_vector(17071,AMPL_WIDTH),
conv_std_logic_vector(17074,AMPL_WIDTH),
conv_std_logic_vector(17077,AMPL_WIDTH),
conv_std_logic_vector(17079,AMPL_WIDTH),
conv_std_logic_vector(17082,AMPL_WIDTH),
conv_std_logic_vector(17085,AMPL_WIDTH),
conv_std_logic_vector(17087,AMPL_WIDTH),
conv_std_logic_vector(17090,AMPL_WIDTH),
conv_std_logic_vector(17093,AMPL_WIDTH),
conv_std_logic_vector(17096,AMPL_WIDTH),
conv_std_logic_vector(17098,AMPL_WIDTH),
conv_std_logic_vector(17101,AMPL_WIDTH),
conv_std_logic_vector(17104,AMPL_WIDTH),
conv_std_logic_vector(17106,AMPL_WIDTH),
conv_std_logic_vector(17109,AMPL_WIDTH),
conv_std_logic_vector(17112,AMPL_WIDTH),
conv_std_logic_vector(17114,AMPL_WIDTH),
conv_std_logic_vector(17117,AMPL_WIDTH),
conv_std_logic_vector(17120,AMPL_WIDTH),
conv_std_logic_vector(17122,AMPL_WIDTH),
conv_std_logic_vector(17125,AMPL_WIDTH),
conv_std_logic_vector(17128,AMPL_WIDTH),
conv_std_logic_vector(17130,AMPL_WIDTH),
conv_std_logic_vector(17133,AMPL_WIDTH),
conv_std_logic_vector(17136,AMPL_WIDTH),
conv_std_logic_vector(17138,AMPL_WIDTH),
conv_std_logic_vector(17141,AMPL_WIDTH),
conv_std_logic_vector(17144,AMPL_WIDTH),
conv_std_logic_vector(17146,AMPL_WIDTH),
conv_std_logic_vector(17149,AMPL_WIDTH),
conv_std_logic_vector(17152,AMPL_WIDTH),
conv_std_logic_vector(17154,AMPL_WIDTH),
conv_std_logic_vector(17157,AMPL_WIDTH),
conv_std_logic_vector(17160,AMPL_WIDTH),
conv_std_logic_vector(17162,AMPL_WIDTH),
conv_std_logic_vector(17165,AMPL_WIDTH),
conv_std_logic_vector(17168,AMPL_WIDTH),
conv_std_logic_vector(17171,AMPL_WIDTH),
conv_std_logic_vector(17173,AMPL_WIDTH),
conv_std_logic_vector(17176,AMPL_WIDTH),
conv_std_logic_vector(17179,AMPL_WIDTH),
conv_std_logic_vector(17181,AMPL_WIDTH),
conv_std_logic_vector(17184,AMPL_WIDTH),
conv_std_logic_vector(17187,AMPL_WIDTH),
conv_std_logic_vector(17189,AMPL_WIDTH),
conv_std_logic_vector(17192,AMPL_WIDTH),
conv_std_logic_vector(17195,AMPL_WIDTH),
conv_std_logic_vector(17197,AMPL_WIDTH),
conv_std_logic_vector(17200,AMPL_WIDTH),
conv_std_logic_vector(17203,AMPL_WIDTH),
conv_std_logic_vector(17205,AMPL_WIDTH),
conv_std_logic_vector(17208,AMPL_WIDTH),
conv_std_logic_vector(17211,AMPL_WIDTH),
conv_std_logic_vector(17213,AMPL_WIDTH),
conv_std_logic_vector(17216,AMPL_WIDTH),
conv_std_logic_vector(17219,AMPL_WIDTH),
conv_std_logic_vector(17221,AMPL_WIDTH),
conv_std_logic_vector(17224,AMPL_WIDTH),
conv_std_logic_vector(17227,AMPL_WIDTH),
conv_std_logic_vector(17229,AMPL_WIDTH),
conv_std_logic_vector(17232,AMPL_WIDTH),
conv_std_logic_vector(17235,AMPL_WIDTH),
conv_std_logic_vector(17237,AMPL_WIDTH),
conv_std_logic_vector(17240,AMPL_WIDTH),
conv_std_logic_vector(17243,AMPL_WIDTH),
conv_std_logic_vector(17245,AMPL_WIDTH),
conv_std_logic_vector(17248,AMPL_WIDTH),
conv_std_logic_vector(17251,AMPL_WIDTH),
conv_std_logic_vector(17253,AMPL_WIDTH),
conv_std_logic_vector(17256,AMPL_WIDTH),
conv_std_logic_vector(17259,AMPL_WIDTH),
conv_std_logic_vector(17261,AMPL_WIDTH),
conv_std_logic_vector(17264,AMPL_WIDTH),
conv_std_logic_vector(17267,AMPL_WIDTH),
conv_std_logic_vector(17269,AMPL_WIDTH),
conv_std_logic_vector(17272,AMPL_WIDTH),
conv_std_logic_vector(17275,AMPL_WIDTH),
conv_std_logic_vector(17277,AMPL_WIDTH),
conv_std_logic_vector(17280,AMPL_WIDTH),
conv_std_logic_vector(17283,AMPL_WIDTH),
conv_std_logic_vector(17285,AMPL_WIDTH),
conv_std_logic_vector(17288,AMPL_WIDTH),
conv_std_logic_vector(17291,AMPL_WIDTH),
conv_std_logic_vector(17293,AMPL_WIDTH),
conv_std_logic_vector(17296,AMPL_WIDTH),
conv_std_logic_vector(17299,AMPL_WIDTH),
conv_std_logic_vector(17301,AMPL_WIDTH),
conv_std_logic_vector(17304,AMPL_WIDTH),
conv_std_logic_vector(17307,AMPL_WIDTH),
conv_std_logic_vector(17309,AMPL_WIDTH),
conv_std_logic_vector(17312,AMPL_WIDTH),
conv_std_logic_vector(17315,AMPL_WIDTH),
conv_std_logic_vector(17317,AMPL_WIDTH),
conv_std_logic_vector(17320,AMPL_WIDTH),
conv_std_logic_vector(17323,AMPL_WIDTH),
conv_std_logic_vector(17325,AMPL_WIDTH),
conv_std_logic_vector(17328,AMPL_WIDTH),
conv_std_logic_vector(17331,AMPL_WIDTH),
conv_std_logic_vector(17333,AMPL_WIDTH),
conv_std_logic_vector(17336,AMPL_WIDTH),
conv_std_logic_vector(17339,AMPL_WIDTH),
conv_std_logic_vector(17341,AMPL_WIDTH),
conv_std_logic_vector(17344,AMPL_WIDTH),
conv_std_logic_vector(17347,AMPL_WIDTH),
conv_std_logic_vector(17349,AMPL_WIDTH),
conv_std_logic_vector(17352,AMPL_WIDTH),
conv_std_logic_vector(17355,AMPL_WIDTH),
conv_std_logic_vector(17357,AMPL_WIDTH),
conv_std_logic_vector(17360,AMPL_WIDTH),
conv_std_logic_vector(17363,AMPL_WIDTH),
conv_std_logic_vector(17365,AMPL_WIDTH),
conv_std_logic_vector(17368,AMPL_WIDTH),
conv_std_logic_vector(17371,AMPL_WIDTH),
conv_std_logic_vector(17373,AMPL_WIDTH),
conv_std_logic_vector(17376,AMPL_WIDTH),
conv_std_logic_vector(17379,AMPL_WIDTH),
conv_std_logic_vector(17381,AMPL_WIDTH),
conv_std_logic_vector(17384,AMPL_WIDTH),
conv_std_logic_vector(17387,AMPL_WIDTH),
conv_std_logic_vector(17389,AMPL_WIDTH),
conv_std_logic_vector(17392,AMPL_WIDTH),
conv_std_logic_vector(17395,AMPL_WIDTH),
conv_std_logic_vector(17397,AMPL_WIDTH),
conv_std_logic_vector(17400,AMPL_WIDTH),
conv_std_logic_vector(17403,AMPL_WIDTH),
conv_std_logic_vector(17405,AMPL_WIDTH),
conv_std_logic_vector(17408,AMPL_WIDTH),
conv_std_logic_vector(17411,AMPL_WIDTH),
conv_std_logic_vector(17413,AMPL_WIDTH),
conv_std_logic_vector(17416,AMPL_WIDTH),
conv_std_logic_vector(17419,AMPL_WIDTH),
conv_std_logic_vector(17421,AMPL_WIDTH),
conv_std_logic_vector(17424,AMPL_WIDTH),
conv_std_logic_vector(17427,AMPL_WIDTH),
conv_std_logic_vector(17429,AMPL_WIDTH),
conv_std_logic_vector(17432,AMPL_WIDTH),
conv_std_logic_vector(17435,AMPL_WIDTH),
conv_std_logic_vector(17437,AMPL_WIDTH),
conv_std_logic_vector(17440,AMPL_WIDTH),
conv_std_logic_vector(17443,AMPL_WIDTH),
conv_std_logic_vector(17445,AMPL_WIDTH),
conv_std_logic_vector(17448,AMPL_WIDTH),
conv_std_logic_vector(17451,AMPL_WIDTH),
conv_std_logic_vector(17453,AMPL_WIDTH),
conv_std_logic_vector(17456,AMPL_WIDTH),
conv_std_logic_vector(17459,AMPL_WIDTH),
conv_std_logic_vector(17461,AMPL_WIDTH),
conv_std_logic_vector(17464,AMPL_WIDTH),
conv_std_logic_vector(17467,AMPL_WIDTH),
conv_std_logic_vector(17469,AMPL_WIDTH),
conv_std_logic_vector(17472,AMPL_WIDTH),
conv_std_logic_vector(17474,AMPL_WIDTH),
conv_std_logic_vector(17477,AMPL_WIDTH),
conv_std_logic_vector(17480,AMPL_WIDTH),
conv_std_logic_vector(17482,AMPL_WIDTH),
conv_std_logic_vector(17485,AMPL_WIDTH),
conv_std_logic_vector(17488,AMPL_WIDTH),
conv_std_logic_vector(17490,AMPL_WIDTH),
conv_std_logic_vector(17493,AMPL_WIDTH),
conv_std_logic_vector(17496,AMPL_WIDTH),
conv_std_logic_vector(17498,AMPL_WIDTH),
conv_std_logic_vector(17501,AMPL_WIDTH),
conv_std_logic_vector(17504,AMPL_WIDTH),
conv_std_logic_vector(17506,AMPL_WIDTH),
conv_std_logic_vector(17509,AMPL_WIDTH),
conv_std_logic_vector(17512,AMPL_WIDTH),
conv_std_logic_vector(17514,AMPL_WIDTH),
conv_std_logic_vector(17517,AMPL_WIDTH),
conv_std_logic_vector(17520,AMPL_WIDTH),
conv_std_logic_vector(17522,AMPL_WIDTH),
conv_std_logic_vector(17525,AMPL_WIDTH),
conv_std_logic_vector(17528,AMPL_WIDTH),
conv_std_logic_vector(17530,AMPL_WIDTH),
conv_std_logic_vector(17533,AMPL_WIDTH),
conv_std_logic_vector(17536,AMPL_WIDTH),
conv_std_logic_vector(17538,AMPL_WIDTH),
conv_std_logic_vector(17541,AMPL_WIDTH),
conv_std_logic_vector(17544,AMPL_WIDTH),
conv_std_logic_vector(17546,AMPL_WIDTH),
conv_std_logic_vector(17549,AMPL_WIDTH),
conv_std_logic_vector(17551,AMPL_WIDTH),
conv_std_logic_vector(17554,AMPL_WIDTH),
conv_std_logic_vector(17557,AMPL_WIDTH),
conv_std_logic_vector(17559,AMPL_WIDTH),
conv_std_logic_vector(17562,AMPL_WIDTH),
conv_std_logic_vector(17565,AMPL_WIDTH),
conv_std_logic_vector(17567,AMPL_WIDTH),
conv_std_logic_vector(17570,AMPL_WIDTH),
conv_std_logic_vector(17573,AMPL_WIDTH),
conv_std_logic_vector(17575,AMPL_WIDTH),
conv_std_logic_vector(17578,AMPL_WIDTH),
conv_std_logic_vector(17581,AMPL_WIDTH),
conv_std_logic_vector(17583,AMPL_WIDTH),
conv_std_logic_vector(17586,AMPL_WIDTH),
conv_std_logic_vector(17589,AMPL_WIDTH),
conv_std_logic_vector(17591,AMPL_WIDTH),
conv_std_logic_vector(17594,AMPL_WIDTH),
conv_std_logic_vector(17597,AMPL_WIDTH),
conv_std_logic_vector(17599,AMPL_WIDTH),
conv_std_logic_vector(17602,AMPL_WIDTH),
conv_std_logic_vector(17605,AMPL_WIDTH),
conv_std_logic_vector(17607,AMPL_WIDTH),
conv_std_logic_vector(17610,AMPL_WIDTH),
conv_std_logic_vector(17612,AMPL_WIDTH),
conv_std_logic_vector(17615,AMPL_WIDTH),
conv_std_logic_vector(17618,AMPL_WIDTH),
conv_std_logic_vector(17620,AMPL_WIDTH),
conv_std_logic_vector(17623,AMPL_WIDTH),
conv_std_logic_vector(17626,AMPL_WIDTH),
conv_std_logic_vector(17628,AMPL_WIDTH),
conv_std_logic_vector(17631,AMPL_WIDTH),
conv_std_logic_vector(17634,AMPL_WIDTH),
conv_std_logic_vector(17636,AMPL_WIDTH),
conv_std_logic_vector(17639,AMPL_WIDTH),
conv_std_logic_vector(17642,AMPL_WIDTH),
conv_std_logic_vector(17644,AMPL_WIDTH),
conv_std_logic_vector(17647,AMPL_WIDTH),
conv_std_logic_vector(17650,AMPL_WIDTH),
conv_std_logic_vector(17652,AMPL_WIDTH),
conv_std_logic_vector(17655,AMPL_WIDTH),
conv_std_logic_vector(17657,AMPL_WIDTH),
conv_std_logic_vector(17660,AMPL_WIDTH),
conv_std_logic_vector(17663,AMPL_WIDTH),
conv_std_logic_vector(17665,AMPL_WIDTH),
conv_std_logic_vector(17668,AMPL_WIDTH),
conv_std_logic_vector(17671,AMPL_WIDTH),
conv_std_logic_vector(17673,AMPL_WIDTH),
conv_std_logic_vector(17676,AMPL_WIDTH),
conv_std_logic_vector(17679,AMPL_WIDTH),
conv_std_logic_vector(17681,AMPL_WIDTH),
conv_std_logic_vector(17684,AMPL_WIDTH),
conv_std_logic_vector(17687,AMPL_WIDTH),
conv_std_logic_vector(17689,AMPL_WIDTH),
conv_std_logic_vector(17692,AMPL_WIDTH),
conv_std_logic_vector(17695,AMPL_WIDTH),
conv_std_logic_vector(17697,AMPL_WIDTH),
conv_std_logic_vector(17700,AMPL_WIDTH),
conv_std_logic_vector(17702,AMPL_WIDTH),
conv_std_logic_vector(17705,AMPL_WIDTH),
conv_std_logic_vector(17708,AMPL_WIDTH),
conv_std_logic_vector(17710,AMPL_WIDTH),
conv_std_logic_vector(17713,AMPL_WIDTH),
conv_std_logic_vector(17716,AMPL_WIDTH),
conv_std_logic_vector(17718,AMPL_WIDTH),
conv_std_logic_vector(17721,AMPL_WIDTH),
conv_std_logic_vector(17724,AMPL_WIDTH),
conv_std_logic_vector(17726,AMPL_WIDTH),
conv_std_logic_vector(17729,AMPL_WIDTH),
conv_std_logic_vector(17732,AMPL_WIDTH),
conv_std_logic_vector(17734,AMPL_WIDTH),
conv_std_logic_vector(17737,AMPL_WIDTH),
conv_std_logic_vector(17739,AMPL_WIDTH),
conv_std_logic_vector(17742,AMPL_WIDTH),
conv_std_logic_vector(17745,AMPL_WIDTH),
conv_std_logic_vector(17747,AMPL_WIDTH),
conv_std_logic_vector(17750,AMPL_WIDTH),
conv_std_logic_vector(17753,AMPL_WIDTH),
conv_std_logic_vector(17755,AMPL_WIDTH),
conv_std_logic_vector(17758,AMPL_WIDTH),
conv_std_logic_vector(17761,AMPL_WIDTH),
conv_std_logic_vector(17763,AMPL_WIDTH),
conv_std_logic_vector(17766,AMPL_WIDTH),
conv_std_logic_vector(17768,AMPL_WIDTH),
conv_std_logic_vector(17771,AMPL_WIDTH),
conv_std_logic_vector(17774,AMPL_WIDTH),
conv_std_logic_vector(17776,AMPL_WIDTH),
conv_std_logic_vector(17779,AMPL_WIDTH),
conv_std_logic_vector(17782,AMPL_WIDTH),
conv_std_logic_vector(17784,AMPL_WIDTH),
conv_std_logic_vector(17787,AMPL_WIDTH),
conv_std_logic_vector(17790,AMPL_WIDTH),
conv_std_logic_vector(17792,AMPL_WIDTH),
conv_std_logic_vector(17795,AMPL_WIDTH),
conv_std_logic_vector(17798,AMPL_WIDTH),
conv_std_logic_vector(17800,AMPL_WIDTH),
conv_std_logic_vector(17803,AMPL_WIDTH),
conv_std_logic_vector(17805,AMPL_WIDTH),
conv_std_logic_vector(17808,AMPL_WIDTH),
conv_std_logic_vector(17811,AMPL_WIDTH),
conv_std_logic_vector(17813,AMPL_WIDTH),
conv_std_logic_vector(17816,AMPL_WIDTH),
conv_std_logic_vector(17819,AMPL_WIDTH),
conv_std_logic_vector(17821,AMPL_WIDTH),
conv_std_logic_vector(17824,AMPL_WIDTH),
conv_std_logic_vector(17827,AMPL_WIDTH),
conv_std_logic_vector(17829,AMPL_WIDTH),
conv_std_logic_vector(17832,AMPL_WIDTH),
conv_std_logic_vector(17834,AMPL_WIDTH),
conv_std_logic_vector(17837,AMPL_WIDTH),
conv_std_logic_vector(17840,AMPL_WIDTH),
conv_std_logic_vector(17842,AMPL_WIDTH),
conv_std_logic_vector(17845,AMPL_WIDTH),
conv_std_logic_vector(17848,AMPL_WIDTH),
conv_std_logic_vector(17850,AMPL_WIDTH),
conv_std_logic_vector(17853,AMPL_WIDTH),
conv_std_logic_vector(17855,AMPL_WIDTH),
conv_std_logic_vector(17858,AMPL_WIDTH),
conv_std_logic_vector(17861,AMPL_WIDTH),
conv_std_logic_vector(17863,AMPL_WIDTH),
conv_std_logic_vector(17866,AMPL_WIDTH),
conv_std_logic_vector(17869,AMPL_WIDTH),
conv_std_logic_vector(17871,AMPL_WIDTH),
conv_std_logic_vector(17874,AMPL_WIDTH),
conv_std_logic_vector(17877,AMPL_WIDTH),
conv_std_logic_vector(17879,AMPL_WIDTH),
conv_std_logic_vector(17882,AMPL_WIDTH),
conv_std_logic_vector(17884,AMPL_WIDTH),
conv_std_logic_vector(17887,AMPL_WIDTH),
conv_std_logic_vector(17890,AMPL_WIDTH),
conv_std_logic_vector(17892,AMPL_WIDTH),
conv_std_logic_vector(17895,AMPL_WIDTH),
conv_std_logic_vector(17898,AMPL_WIDTH),
conv_std_logic_vector(17900,AMPL_WIDTH),
conv_std_logic_vector(17903,AMPL_WIDTH),
conv_std_logic_vector(17906,AMPL_WIDTH),
conv_std_logic_vector(17908,AMPL_WIDTH),
conv_std_logic_vector(17911,AMPL_WIDTH),
conv_std_logic_vector(17913,AMPL_WIDTH),
conv_std_logic_vector(17916,AMPL_WIDTH),
conv_std_logic_vector(17919,AMPL_WIDTH),
conv_std_logic_vector(17921,AMPL_WIDTH),
conv_std_logic_vector(17924,AMPL_WIDTH),
conv_std_logic_vector(17927,AMPL_WIDTH),
conv_std_logic_vector(17929,AMPL_WIDTH),
conv_std_logic_vector(17932,AMPL_WIDTH),
conv_std_logic_vector(17934,AMPL_WIDTH),
conv_std_logic_vector(17937,AMPL_WIDTH),
conv_std_logic_vector(17940,AMPL_WIDTH),
conv_std_logic_vector(17942,AMPL_WIDTH),
conv_std_logic_vector(17945,AMPL_WIDTH),
conv_std_logic_vector(17948,AMPL_WIDTH),
conv_std_logic_vector(17950,AMPL_WIDTH),
conv_std_logic_vector(17953,AMPL_WIDTH),
conv_std_logic_vector(17955,AMPL_WIDTH),
conv_std_logic_vector(17958,AMPL_WIDTH),
conv_std_logic_vector(17961,AMPL_WIDTH),
conv_std_logic_vector(17963,AMPL_WIDTH),
conv_std_logic_vector(17966,AMPL_WIDTH),
conv_std_logic_vector(17969,AMPL_WIDTH),
conv_std_logic_vector(17971,AMPL_WIDTH),
conv_std_logic_vector(17974,AMPL_WIDTH),
conv_std_logic_vector(17976,AMPL_WIDTH),
conv_std_logic_vector(17979,AMPL_WIDTH),
conv_std_logic_vector(17982,AMPL_WIDTH),
conv_std_logic_vector(17984,AMPL_WIDTH),
conv_std_logic_vector(17987,AMPL_WIDTH),
conv_std_logic_vector(17990,AMPL_WIDTH),
conv_std_logic_vector(17992,AMPL_WIDTH),
conv_std_logic_vector(17995,AMPL_WIDTH),
conv_std_logic_vector(17997,AMPL_WIDTH),
conv_std_logic_vector(18000,AMPL_WIDTH),
conv_std_logic_vector(18003,AMPL_WIDTH),
conv_std_logic_vector(18005,AMPL_WIDTH),
conv_std_logic_vector(18008,AMPL_WIDTH),
conv_std_logic_vector(18011,AMPL_WIDTH),
conv_std_logic_vector(18013,AMPL_WIDTH),
conv_std_logic_vector(18016,AMPL_WIDTH),
conv_std_logic_vector(18018,AMPL_WIDTH),
conv_std_logic_vector(18021,AMPL_WIDTH),
conv_std_logic_vector(18024,AMPL_WIDTH),
conv_std_logic_vector(18026,AMPL_WIDTH),
conv_std_logic_vector(18029,AMPL_WIDTH),
conv_std_logic_vector(18032,AMPL_WIDTH),
conv_std_logic_vector(18034,AMPL_WIDTH),
conv_std_logic_vector(18037,AMPL_WIDTH),
conv_std_logic_vector(18039,AMPL_WIDTH),
conv_std_logic_vector(18042,AMPL_WIDTH),
conv_std_logic_vector(18045,AMPL_WIDTH),
conv_std_logic_vector(18047,AMPL_WIDTH),
conv_std_logic_vector(18050,AMPL_WIDTH),
conv_std_logic_vector(18053,AMPL_WIDTH),
conv_std_logic_vector(18055,AMPL_WIDTH),
conv_std_logic_vector(18058,AMPL_WIDTH),
conv_std_logic_vector(18060,AMPL_WIDTH),
conv_std_logic_vector(18063,AMPL_WIDTH),
conv_std_logic_vector(18066,AMPL_WIDTH),
conv_std_logic_vector(18068,AMPL_WIDTH),
conv_std_logic_vector(18071,AMPL_WIDTH),
conv_std_logic_vector(18074,AMPL_WIDTH),
conv_std_logic_vector(18076,AMPL_WIDTH),
conv_std_logic_vector(18079,AMPL_WIDTH),
conv_std_logic_vector(18081,AMPL_WIDTH),
conv_std_logic_vector(18084,AMPL_WIDTH),
conv_std_logic_vector(18087,AMPL_WIDTH),
conv_std_logic_vector(18089,AMPL_WIDTH),
conv_std_logic_vector(18092,AMPL_WIDTH),
conv_std_logic_vector(18095,AMPL_WIDTH),
conv_std_logic_vector(18097,AMPL_WIDTH),
conv_std_logic_vector(18100,AMPL_WIDTH),
conv_std_logic_vector(18102,AMPL_WIDTH),
conv_std_logic_vector(18105,AMPL_WIDTH),
conv_std_logic_vector(18108,AMPL_WIDTH),
conv_std_logic_vector(18110,AMPL_WIDTH),
conv_std_logic_vector(18113,AMPL_WIDTH),
conv_std_logic_vector(18115,AMPL_WIDTH),
conv_std_logic_vector(18118,AMPL_WIDTH),
conv_std_logic_vector(18121,AMPL_WIDTH),
conv_std_logic_vector(18123,AMPL_WIDTH),
conv_std_logic_vector(18126,AMPL_WIDTH),
conv_std_logic_vector(18129,AMPL_WIDTH),
conv_std_logic_vector(18131,AMPL_WIDTH),
conv_std_logic_vector(18134,AMPL_WIDTH),
conv_std_logic_vector(18136,AMPL_WIDTH),
conv_std_logic_vector(18139,AMPL_WIDTH),
conv_std_logic_vector(18142,AMPL_WIDTH),
conv_std_logic_vector(18144,AMPL_WIDTH),
conv_std_logic_vector(18147,AMPL_WIDTH),
conv_std_logic_vector(18149,AMPL_WIDTH),
conv_std_logic_vector(18152,AMPL_WIDTH),
conv_std_logic_vector(18155,AMPL_WIDTH),
conv_std_logic_vector(18157,AMPL_WIDTH),
conv_std_logic_vector(18160,AMPL_WIDTH),
conv_std_logic_vector(18163,AMPL_WIDTH),
conv_std_logic_vector(18165,AMPL_WIDTH),
conv_std_logic_vector(18168,AMPL_WIDTH),
conv_std_logic_vector(18170,AMPL_WIDTH),
conv_std_logic_vector(18173,AMPL_WIDTH),
conv_std_logic_vector(18176,AMPL_WIDTH),
conv_std_logic_vector(18178,AMPL_WIDTH),
conv_std_logic_vector(18181,AMPL_WIDTH),
conv_std_logic_vector(18183,AMPL_WIDTH),
conv_std_logic_vector(18186,AMPL_WIDTH),
conv_std_logic_vector(18189,AMPL_WIDTH),
conv_std_logic_vector(18191,AMPL_WIDTH),
conv_std_logic_vector(18194,AMPL_WIDTH),
conv_std_logic_vector(18197,AMPL_WIDTH),
conv_std_logic_vector(18199,AMPL_WIDTH),
conv_std_logic_vector(18202,AMPL_WIDTH),
conv_std_logic_vector(18204,AMPL_WIDTH),
conv_std_logic_vector(18207,AMPL_WIDTH),
conv_std_logic_vector(18210,AMPL_WIDTH),
conv_std_logic_vector(18212,AMPL_WIDTH),
conv_std_logic_vector(18215,AMPL_WIDTH),
conv_std_logic_vector(18217,AMPL_WIDTH),
conv_std_logic_vector(18220,AMPL_WIDTH),
conv_std_logic_vector(18223,AMPL_WIDTH),
conv_std_logic_vector(18225,AMPL_WIDTH),
conv_std_logic_vector(18228,AMPL_WIDTH),
conv_std_logic_vector(18230,AMPL_WIDTH),
conv_std_logic_vector(18233,AMPL_WIDTH),
conv_std_logic_vector(18236,AMPL_WIDTH),
conv_std_logic_vector(18238,AMPL_WIDTH),
conv_std_logic_vector(18241,AMPL_WIDTH),
conv_std_logic_vector(18244,AMPL_WIDTH),
conv_std_logic_vector(18246,AMPL_WIDTH),
conv_std_logic_vector(18249,AMPL_WIDTH),
conv_std_logic_vector(18251,AMPL_WIDTH),
conv_std_logic_vector(18254,AMPL_WIDTH),
conv_std_logic_vector(18257,AMPL_WIDTH),
conv_std_logic_vector(18259,AMPL_WIDTH),
conv_std_logic_vector(18262,AMPL_WIDTH),
conv_std_logic_vector(18264,AMPL_WIDTH),
conv_std_logic_vector(18267,AMPL_WIDTH),
conv_std_logic_vector(18270,AMPL_WIDTH),
conv_std_logic_vector(18272,AMPL_WIDTH),
conv_std_logic_vector(18275,AMPL_WIDTH),
conv_std_logic_vector(18277,AMPL_WIDTH),
conv_std_logic_vector(18280,AMPL_WIDTH),
conv_std_logic_vector(18283,AMPL_WIDTH),
conv_std_logic_vector(18285,AMPL_WIDTH),
conv_std_logic_vector(18288,AMPL_WIDTH),
conv_std_logic_vector(18290,AMPL_WIDTH),
conv_std_logic_vector(18293,AMPL_WIDTH),
conv_std_logic_vector(18296,AMPL_WIDTH),
conv_std_logic_vector(18298,AMPL_WIDTH),
conv_std_logic_vector(18301,AMPL_WIDTH),
conv_std_logic_vector(18304,AMPL_WIDTH),
conv_std_logic_vector(18306,AMPL_WIDTH),
conv_std_logic_vector(18309,AMPL_WIDTH),
conv_std_logic_vector(18311,AMPL_WIDTH),
conv_std_logic_vector(18314,AMPL_WIDTH),
conv_std_logic_vector(18317,AMPL_WIDTH),
conv_std_logic_vector(18319,AMPL_WIDTH),
conv_std_logic_vector(18322,AMPL_WIDTH),
conv_std_logic_vector(18324,AMPL_WIDTH),
conv_std_logic_vector(18327,AMPL_WIDTH),
conv_std_logic_vector(18330,AMPL_WIDTH),
conv_std_logic_vector(18332,AMPL_WIDTH),
conv_std_logic_vector(18335,AMPL_WIDTH),
conv_std_logic_vector(18337,AMPL_WIDTH),
conv_std_logic_vector(18340,AMPL_WIDTH),
conv_std_logic_vector(18343,AMPL_WIDTH),
conv_std_logic_vector(18345,AMPL_WIDTH),
conv_std_logic_vector(18348,AMPL_WIDTH),
conv_std_logic_vector(18350,AMPL_WIDTH),
conv_std_logic_vector(18353,AMPL_WIDTH),
conv_std_logic_vector(18356,AMPL_WIDTH),
conv_std_logic_vector(18358,AMPL_WIDTH),
conv_std_logic_vector(18361,AMPL_WIDTH),
conv_std_logic_vector(18363,AMPL_WIDTH),
conv_std_logic_vector(18366,AMPL_WIDTH),
conv_std_logic_vector(18369,AMPL_WIDTH),
conv_std_logic_vector(18371,AMPL_WIDTH),
conv_std_logic_vector(18374,AMPL_WIDTH),
conv_std_logic_vector(18376,AMPL_WIDTH),
conv_std_logic_vector(18379,AMPL_WIDTH),
conv_std_logic_vector(18382,AMPL_WIDTH),
conv_std_logic_vector(18384,AMPL_WIDTH),
conv_std_logic_vector(18387,AMPL_WIDTH),
conv_std_logic_vector(18389,AMPL_WIDTH),
conv_std_logic_vector(18392,AMPL_WIDTH),
conv_std_logic_vector(18395,AMPL_WIDTH),
conv_std_logic_vector(18397,AMPL_WIDTH),
conv_std_logic_vector(18400,AMPL_WIDTH),
conv_std_logic_vector(18402,AMPL_WIDTH),
conv_std_logic_vector(18405,AMPL_WIDTH),
conv_std_logic_vector(18408,AMPL_WIDTH),
conv_std_logic_vector(18410,AMPL_WIDTH),
conv_std_logic_vector(18413,AMPL_WIDTH),
conv_std_logic_vector(18415,AMPL_WIDTH),
conv_std_logic_vector(18418,AMPL_WIDTH),
conv_std_logic_vector(18421,AMPL_WIDTH),
conv_std_logic_vector(18423,AMPL_WIDTH),
conv_std_logic_vector(18426,AMPL_WIDTH),
conv_std_logic_vector(18428,AMPL_WIDTH),
conv_std_logic_vector(18431,AMPL_WIDTH),
conv_std_logic_vector(18434,AMPL_WIDTH),
conv_std_logic_vector(18436,AMPL_WIDTH),
conv_std_logic_vector(18439,AMPL_WIDTH),
conv_std_logic_vector(18441,AMPL_WIDTH),
conv_std_logic_vector(18444,AMPL_WIDTH),
conv_std_logic_vector(18447,AMPL_WIDTH),
conv_std_logic_vector(18449,AMPL_WIDTH),
conv_std_logic_vector(18452,AMPL_WIDTH),
conv_std_logic_vector(18454,AMPL_WIDTH),
conv_std_logic_vector(18457,AMPL_WIDTH),
conv_std_logic_vector(18460,AMPL_WIDTH),
conv_std_logic_vector(18462,AMPL_WIDTH),
conv_std_logic_vector(18465,AMPL_WIDTH),
conv_std_logic_vector(18467,AMPL_WIDTH),
conv_std_logic_vector(18470,AMPL_WIDTH),
conv_std_logic_vector(18473,AMPL_WIDTH),
conv_std_logic_vector(18475,AMPL_WIDTH),
conv_std_logic_vector(18478,AMPL_WIDTH),
conv_std_logic_vector(18480,AMPL_WIDTH),
conv_std_logic_vector(18483,AMPL_WIDTH),
conv_std_logic_vector(18485,AMPL_WIDTH),
conv_std_logic_vector(18488,AMPL_WIDTH),
conv_std_logic_vector(18491,AMPL_WIDTH),
conv_std_logic_vector(18493,AMPL_WIDTH),
conv_std_logic_vector(18496,AMPL_WIDTH),
conv_std_logic_vector(18498,AMPL_WIDTH),
conv_std_logic_vector(18501,AMPL_WIDTH),
conv_std_logic_vector(18504,AMPL_WIDTH),
conv_std_logic_vector(18506,AMPL_WIDTH),
conv_std_logic_vector(18509,AMPL_WIDTH),
conv_std_logic_vector(18511,AMPL_WIDTH),
conv_std_logic_vector(18514,AMPL_WIDTH),
conv_std_logic_vector(18517,AMPL_WIDTH),
conv_std_logic_vector(18519,AMPL_WIDTH),
conv_std_logic_vector(18522,AMPL_WIDTH),
conv_std_logic_vector(18524,AMPL_WIDTH),
conv_std_logic_vector(18527,AMPL_WIDTH),
conv_std_logic_vector(18530,AMPL_WIDTH),
conv_std_logic_vector(18532,AMPL_WIDTH),
conv_std_logic_vector(18535,AMPL_WIDTH),
conv_std_logic_vector(18537,AMPL_WIDTH),
conv_std_logic_vector(18540,AMPL_WIDTH),
conv_std_logic_vector(18543,AMPL_WIDTH),
conv_std_logic_vector(18545,AMPL_WIDTH),
conv_std_logic_vector(18548,AMPL_WIDTH),
conv_std_logic_vector(18550,AMPL_WIDTH),
conv_std_logic_vector(18553,AMPL_WIDTH),
conv_std_logic_vector(18555,AMPL_WIDTH),
conv_std_logic_vector(18558,AMPL_WIDTH),
conv_std_logic_vector(18561,AMPL_WIDTH),
conv_std_logic_vector(18563,AMPL_WIDTH),
conv_std_logic_vector(18566,AMPL_WIDTH),
conv_std_logic_vector(18568,AMPL_WIDTH),
conv_std_logic_vector(18571,AMPL_WIDTH),
conv_std_logic_vector(18574,AMPL_WIDTH),
conv_std_logic_vector(18576,AMPL_WIDTH),
conv_std_logic_vector(18579,AMPL_WIDTH),
conv_std_logic_vector(18581,AMPL_WIDTH),
conv_std_logic_vector(18584,AMPL_WIDTH),
conv_std_logic_vector(18587,AMPL_WIDTH),
conv_std_logic_vector(18589,AMPL_WIDTH),
conv_std_logic_vector(18592,AMPL_WIDTH),
conv_std_logic_vector(18594,AMPL_WIDTH),
conv_std_logic_vector(18597,AMPL_WIDTH),
conv_std_logic_vector(18599,AMPL_WIDTH),
conv_std_logic_vector(18602,AMPL_WIDTH),
conv_std_logic_vector(18605,AMPL_WIDTH),
conv_std_logic_vector(18607,AMPL_WIDTH),
conv_std_logic_vector(18610,AMPL_WIDTH),
conv_std_logic_vector(18612,AMPL_WIDTH),
conv_std_logic_vector(18615,AMPL_WIDTH),
conv_std_logic_vector(18618,AMPL_WIDTH),
conv_std_logic_vector(18620,AMPL_WIDTH),
conv_std_logic_vector(18623,AMPL_WIDTH),
conv_std_logic_vector(18625,AMPL_WIDTH),
conv_std_logic_vector(18628,AMPL_WIDTH),
conv_std_logic_vector(18630,AMPL_WIDTH),
conv_std_logic_vector(18633,AMPL_WIDTH),
conv_std_logic_vector(18636,AMPL_WIDTH),
conv_std_logic_vector(18638,AMPL_WIDTH),
conv_std_logic_vector(18641,AMPL_WIDTH),
conv_std_logic_vector(18643,AMPL_WIDTH),
conv_std_logic_vector(18646,AMPL_WIDTH),
conv_std_logic_vector(18649,AMPL_WIDTH),
conv_std_logic_vector(18651,AMPL_WIDTH),
conv_std_logic_vector(18654,AMPL_WIDTH),
conv_std_logic_vector(18656,AMPL_WIDTH),
conv_std_logic_vector(18659,AMPL_WIDTH),
conv_std_logic_vector(18661,AMPL_WIDTH),
conv_std_logic_vector(18664,AMPL_WIDTH),
conv_std_logic_vector(18667,AMPL_WIDTH),
conv_std_logic_vector(18669,AMPL_WIDTH),
conv_std_logic_vector(18672,AMPL_WIDTH),
conv_std_logic_vector(18674,AMPL_WIDTH),
conv_std_logic_vector(18677,AMPL_WIDTH),
conv_std_logic_vector(18680,AMPL_WIDTH),
conv_std_logic_vector(18682,AMPL_WIDTH),
conv_std_logic_vector(18685,AMPL_WIDTH),
conv_std_logic_vector(18687,AMPL_WIDTH),
conv_std_logic_vector(18690,AMPL_WIDTH),
conv_std_logic_vector(18692,AMPL_WIDTH),
conv_std_logic_vector(18695,AMPL_WIDTH),
conv_std_logic_vector(18698,AMPL_WIDTH),
conv_std_logic_vector(18700,AMPL_WIDTH),
conv_std_logic_vector(18703,AMPL_WIDTH),
conv_std_logic_vector(18705,AMPL_WIDTH),
conv_std_logic_vector(18708,AMPL_WIDTH),
conv_std_logic_vector(18711,AMPL_WIDTH),
conv_std_logic_vector(18713,AMPL_WIDTH),
conv_std_logic_vector(18716,AMPL_WIDTH),
conv_std_logic_vector(18718,AMPL_WIDTH),
conv_std_logic_vector(18721,AMPL_WIDTH),
conv_std_logic_vector(18723,AMPL_WIDTH),
conv_std_logic_vector(18726,AMPL_WIDTH),
conv_std_logic_vector(18729,AMPL_WIDTH),
conv_std_logic_vector(18731,AMPL_WIDTH),
conv_std_logic_vector(18734,AMPL_WIDTH),
conv_std_logic_vector(18736,AMPL_WIDTH),
conv_std_logic_vector(18739,AMPL_WIDTH),
conv_std_logic_vector(18741,AMPL_WIDTH),
conv_std_logic_vector(18744,AMPL_WIDTH),
conv_std_logic_vector(18747,AMPL_WIDTH),
conv_std_logic_vector(18749,AMPL_WIDTH),
conv_std_logic_vector(18752,AMPL_WIDTH),
conv_std_logic_vector(18754,AMPL_WIDTH),
conv_std_logic_vector(18757,AMPL_WIDTH),
conv_std_logic_vector(18759,AMPL_WIDTH),
conv_std_logic_vector(18762,AMPL_WIDTH),
conv_std_logic_vector(18765,AMPL_WIDTH),
conv_std_logic_vector(18767,AMPL_WIDTH),
conv_std_logic_vector(18770,AMPL_WIDTH),
conv_std_logic_vector(18772,AMPL_WIDTH),
conv_std_logic_vector(18775,AMPL_WIDTH),
conv_std_logic_vector(18778,AMPL_WIDTH),
conv_std_logic_vector(18780,AMPL_WIDTH),
conv_std_logic_vector(18783,AMPL_WIDTH),
conv_std_logic_vector(18785,AMPL_WIDTH),
conv_std_logic_vector(18788,AMPL_WIDTH),
conv_std_logic_vector(18790,AMPL_WIDTH),
conv_std_logic_vector(18793,AMPL_WIDTH),
conv_std_logic_vector(18796,AMPL_WIDTH),
conv_std_logic_vector(18798,AMPL_WIDTH),
conv_std_logic_vector(18801,AMPL_WIDTH),
conv_std_logic_vector(18803,AMPL_WIDTH),
conv_std_logic_vector(18806,AMPL_WIDTH),
conv_std_logic_vector(18808,AMPL_WIDTH),
conv_std_logic_vector(18811,AMPL_WIDTH),
conv_std_logic_vector(18814,AMPL_WIDTH),
conv_std_logic_vector(18816,AMPL_WIDTH),
conv_std_logic_vector(18819,AMPL_WIDTH),
conv_std_logic_vector(18821,AMPL_WIDTH),
conv_std_logic_vector(18824,AMPL_WIDTH),
conv_std_logic_vector(18826,AMPL_WIDTH),
conv_std_logic_vector(18829,AMPL_WIDTH),
conv_std_logic_vector(18832,AMPL_WIDTH),
conv_std_logic_vector(18834,AMPL_WIDTH),
conv_std_logic_vector(18837,AMPL_WIDTH),
conv_std_logic_vector(18839,AMPL_WIDTH),
conv_std_logic_vector(18842,AMPL_WIDTH),
conv_std_logic_vector(18844,AMPL_WIDTH),
conv_std_logic_vector(18847,AMPL_WIDTH),
conv_std_logic_vector(18850,AMPL_WIDTH),
conv_std_logic_vector(18852,AMPL_WIDTH),
conv_std_logic_vector(18855,AMPL_WIDTH),
conv_std_logic_vector(18857,AMPL_WIDTH),
conv_std_logic_vector(18860,AMPL_WIDTH),
conv_std_logic_vector(18862,AMPL_WIDTH),
conv_std_logic_vector(18865,AMPL_WIDTH),
conv_std_logic_vector(18868,AMPL_WIDTH),
conv_std_logic_vector(18870,AMPL_WIDTH),
conv_std_logic_vector(18873,AMPL_WIDTH),
conv_std_logic_vector(18875,AMPL_WIDTH),
conv_std_logic_vector(18878,AMPL_WIDTH),
conv_std_logic_vector(18880,AMPL_WIDTH),
conv_std_logic_vector(18883,AMPL_WIDTH),
conv_std_logic_vector(18885,AMPL_WIDTH),
conv_std_logic_vector(18888,AMPL_WIDTH),
conv_std_logic_vector(18891,AMPL_WIDTH),
conv_std_logic_vector(18893,AMPL_WIDTH),
conv_std_logic_vector(18896,AMPL_WIDTH),
conv_std_logic_vector(18898,AMPL_WIDTH),
conv_std_logic_vector(18901,AMPL_WIDTH),
conv_std_logic_vector(18903,AMPL_WIDTH),
conv_std_logic_vector(18906,AMPL_WIDTH),
conv_std_logic_vector(18909,AMPL_WIDTH),
conv_std_logic_vector(18911,AMPL_WIDTH),
conv_std_logic_vector(18914,AMPL_WIDTH),
conv_std_logic_vector(18916,AMPL_WIDTH),
conv_std_logic_vector(18919,AMPL_WIDTH),
conv_std_logic_vector(18921,AMPL_WIDTH),
conv_std_logic_vector(18924,AMPL_WIDTH),
conv_std_logic_vector(18927,AMPL_WIDTH),
conv_std_logic_vector(18929,AMPL_WIDTH),
conv_std_logic_vector(18932,AMPL_WIDTH),
conv_std_logic_vector(18934,AMPL_WIDTH),
conv_std_logic_vector(18937,AMPL_WIDTH),
conv_std_logic_vector(18939,AMPL_WIDTH),
conv_std_logic_vector(18942,AMPL_WIDTH),
conv_std_logic_vector(18944,AMPL_WIDTH),
conv_std_logic_vector(18947,AMPL_WIDTH),
conv_std_logic_vector(18950,AMPL_WIDTH),
conv_std_logic_vector(18952,AMPL_WIDTH),
conv_std_logic_vector(18955,AMPL_WIDTH),
conv_std_logic_vector(18957,AMPL_WIDTH),
conv_std_logic_vector(18960,AMPL_WIDTH),
conv_std_logic_vector(18962,AMPL_WIDTH),
conv_std_logic_vector(18965,AMPL_WIDTH),
conv_std_logic_vector(18968,AMPL_WIDTH),
conv_std_logic_vector(18970,AMPL_WIDTH),
conv_std_logic_vector(18973,AMPL_WIDTH),
conv_std_logic_vector(18975,AMPL_WIDTH),
conv_std_logic_vector(18978,AMPL_WIDTH),
conv_std_logic_vector(18980,AMPL_WIDTH),
conv_std_logic_vector(18983,AMPL_WIDTH),
conv_std_logic_vector(18985,AMPL_WIDTH),
conv_std_logic_vector(18988,AMPL_WIDTH),
conv_std_logic_vector(18991,AMPL_WIDTH),
conv_std_logic_vector(18993,AMPL_WIDTH),
conv_std_logic_vector(18996,AMPL_WIDTH),
conv_std_logic_vector(18998,AMPL_WIDTH),
conv_std_logic_vector(19001,AMPL_WIDTH),
conv_std_logic_vector(19003,AMPL_WIDTH),
conv_std_logic_vector(19006,AMPL_WIDTH),
conv_std_logic_vector(19009,AMPL_WIDTH),
conv_std_logic_vector(19011,AMPL_WIDTH),
conv_std_logic_vector(19014,AMPL_WIDTH),
conv_std_logic_vector(19016,AMPL_WIDTH),
conv_std_logic_vector(19019,AMPL_WIDTH),
conv_std_logic_vector(19021,AMPL_WIDTH),
conv_std_logic_vector(19024,AMPL_WIDTH),
conv_std_logic_vector(19026,AMPL_WIDTH),
conv_std_logic_vector(19029,AMPL_WIDTH),
conv_std_logic_vector(19032,AMPL_WIDTH),
conv_std_logic_vector(19034,AMPL_WIDTH),
conv_std_logic_vector(19037,AMPL_WIDTH),
conv_std_logic_vector(19039,AMPL_WIDTH),
conv_std_logic_vector(19042,AMPL_WIDTH),
conv_std_logic_vector(19044,AMPL_WIDTH),
conv_std_logic_vector(19047,AMPL_WIDTH),
conv_std_logic_vector(19049,AMPL_WIDTH),
conv_std_logic_vector(19052,AMPL_WIDTH),
conv_std_logic_vector(19055,AMPL_WIDTH),
conv_std_logic_vector(19057,AMPL_WIDTH),
conv_std_logic_vector(19060,AMPL_WIDTH),
conv_std_logic_vector(19062,AMPL_WIDTH),
conv_std_logic_vector(19065,AMPL_WIDTH),
conv_std_logic_vector(19067,AMPL_WIDTH),
conv_std_logic_vector(19070,AMPL_WIDTH),
conv_std_logic_vector(19072,AMPL_WIDTH),
conv_std_logic_vector(19075,AMPL_WIDTH),
conv_std_logic_vector(19078,AMPL_WIDTH),
conv_std_logic_vector(19080,AMPL_WIDTH),
conv_std_logic_vector(19083,AMPL_WIDTH),
conv_std_logic_vector(19085,AMPL_WIDTH),
conv_std_logic_vector(19088,AMPL_WIDTH),
conv_std_logic_vector(19090,AMPL_WIDTH),
conv_std_logic_vector(19093,AMPL_WIDTH),
conv_std_logic_vector(19095,AMPL_WIDTH),
conv_std_logic_vector(19098,AMPL_WIDTH),
conv_std_logic_vector(19101,AMPL_WIDTH),
conv_std_logic_vector(19103,AMPL_WIDTH),
conv_std_logic_vector(19106,AMPL_WIDTH),
conv_std_logic_vector(19108,AMPL_WIDTH),
conv_std_logic_vector(19111,AMPL_WIDTH),
conv_std_logic_vector(19113,AMPL_WIDTH),
conv_std_logic_vector(19116,AMPL_WIDTH),
conv_std_logic_vector(19118,AMPL_WIDTH),
conv_std_logic_vector(19121,AMPL_WIDTH),
conv_std_logic_vector(19123,AMPL_WIDTH),
conv_std_logic_vector(19126,AMPL_WIDTH),
conv_std_logic_vector(19129,AMPL_WIDTH),
conv_std_logic_vector(19131,AMPL_WIDTH),
conv_std_logic_vector(19134,AMPL_WIDTH),
conv_std_logic_vector(19136,AMPL_WIDTH),
conv_std_logic_vector(19139,AMPL_WIDTH),
conv_std_logic_vector(19141,AMPL_WIDTH),
conv_std_logic_vector(19144,AMPL_WIDTH),
conv_std_logic_vector(19146,AMPL_WIDTH),
conv_std_logic_vector(19149,AMPL_WIDTH),
conv_std_logic_vector(19152,AMPL_WIDTH),
conv_std_logic_vector(19154,AMPL_WIDTH),
conv_std_logic_vector(19157,AMPL_WIDTH),
conv_std_logic_vector(19159,AMPL_WIDTH),
conv_std_logic_vector(19162,AMPL_WIDTH),
conv_std_logic_vector(19164,AMPL_WIDTH),
conv_std_logic_vector(19167,AMPL_WIDTH),
conv_std_logic_vector(19169,AMPL_WIDTH),
conv_std_logic_vector(19172,AMPL_WIDTH),
conv_std_logic_vector(19174,AMPL_WIDTH),
conv_std_logic_vector(19177,AMPL_WIDTH),
conv_std_logic_vector(19180,AMPL_WIDTH),
conv_std_logic_vector(19182,AMPL_WIDTH),
conv_std_logic_vector(19185,AMPL_WIDTH),
conv_std_logic_vector(19187,AMPL_WIDTH),
conv_std_logic_vector(19190,AMPL_WIDTH),
conv_std_logic_vector(19192,AMPL_WIDTH),
conv_std_logic_vector(19195,AMPL_WIDTH),
conv_std_logic_vector(19197,AMPL_WIDTH),
conv_std_logic_vector(19200,AMPL_WIDTH),
conv_std_logic_vector(19202,AMPL_WIDTH),
conv_std_logic_vector(19205,AMPL_WIDTH),
conv_std_logic_vector(19208,AMPL_WIDTH),
conv_std_logic_vector(19210,AMPL_WIDTH),
conv_std_logic_vector(19213,AMPL_WIDTH),
conv_std_logic_vector(19215,AMPL_WIDTH),
conv_std_logic_vector(19218,AMPL_WIDTH),
conv_std_logic_vector(19220,AMPL_WIDTH),
conv_std_logic_vector(19223,AMPL_WIDTH),
conv_std_logic_vector(19225,AMPL_WIDTH),
conv_std_logic_vector(19228,AMPL_WIDTH),
conv_std_logic_vector(19230,AMPL_WIDTH),
conv_std_logic_vector(19233,AMPL_WIDTH),
conv_std_logic_vector(19236,AMPL_WIDTH),
conv_std_logic_vector(19238,AMPL_WIDTH),
conv_std_logic_vector(19241,AMPL_WIDTH),
conv_std_logic_vector(19243,AMPL_WIDTH),
conv_std_logic_vector(19246,AMPL_WIDTH),
conv_std_logic_vector(19248,AMPL_WIDTH),
conv_std_logic_vector(19251,AMPL_WIDTH),
conv_std_logic_vector(19253,AMPL_WIDTH),
conv_std_logic_vector(19256,AMPL_WIDTH),
conv_std_logic_vector(19258,AMPL_WIDTH),
conv_std_logic_vector(19261,AMPL_WIDTH),
conv_std_logic_vector(19264,AMPL_WIDTH),
conv_std_logic_vector(19266,AMPL_WIDTH),
conv_std_logic_vector(19269,AMPL_WIDTH),
conv_std_logic_vector(19271,AMPL_WIDTH),
conv_std_logic_vector(19274,AMPL_WIDTH),
conv_std_logic_vector(19276,AMPL_WIDTH),
conv_std_logic_vector(19279,AMPL_WIDTH),
conv_std_logic_vector(19281,AMPL_WIDTH),
conv_std_logic_vector(19284,AMPL_WIDTH),
conv_std_logic_vector(19286,AMPL_WIDTH),
conv_std_logic_vector(19289,AMPL_WIDTH),
conv_std_logic_vector(19291,AMPL_WIDTH),
conv_std_logic_vector(19294,AMPL_WIDTH),
conv_std_logic_vector(19297,AMPL_WIDTH),
conv_std_logic_vector(19299,AMPL_WIDTH),
conv_std_logic_vector(19302,AMPL_WIDTH),
conv_std_logic_vector(19304,AMPL_WIDTH),
conv_std_logic_vector(19307,AMPL_WIDTH),
conv_std_logic_vector(19309,AMPL_WIDTH),
conv_std_logic_vector(19312,AMPL_WIDTH),
conv_std_logic_vector(19314,AMPL_WIDTH),
conv_std_logic_vector(19317,AMPL_WIDTH),
conv_std_logic_vector(19319,AMPL_WIDTH),
conv_std_logic_vector(19322,AMPL_WIDTH),
conv_std_logic_vector(19324,AMPL_WIDTH),
conv_std_logic_vector(19327,AMPL_WIDTH),
conv_std_logic_vector(19330,AMPL_WIDTH),
conv_std_logic_vector(19332,AMPL_WIDTH),
conv_std_logic_vector(19335,AMPL_WIDTH),
conv_std_logic_vector(19337,AMPL_WIDTH),
conv_std_logic_vector(19340,AMPL_WIDTH),
conv_std_logic_vector(19342,AMPL_WIDTH),
conv_std_logic_vector(19345,AMPL_WIDTH),
conv_std_logic_vector(19347,AMPL_WIDTH),
conv_std_logic_vector(19350,AMPL_WIDTH),
conv_std_logic_vector(19352,AMPL_WIDTH),
conv_std_logic_vector(19355,AMPL_WIDTH),
conv_std_logic_vector(19357,AMPL_WIDTH),
conv_std_logic_vector(19360,AMPL_WIDTH),
conv_std_logic_vector(19362,AMPL_WIDTH),
conv_std_logic_vector(19365,AMPL_WIDTH),
conv_std_logic_vector(19368,AMPL_WIDTH),
conv_std_logic_vector(19370,AMPL_WIDTH),
conv_std_logic_vector(19373,AMPL_WIDTH),
conv_std_logic_vector(19375,AMPL_WIDTH),
conv_std_logic_vector(19378,AMPL_WIDTH),
conv_std_logic_vector(19380,AMPL_WIDTH),
conv_std_logic_vector(19383,AMPL_WIDTH),
conv_std_logic_vector(19385,AMPL_WIDTH),
conv_std_logic_vector(19388,AMPL_WIDTH),
conv_std_logic_vector(19390,AMPL_WIDTH),
conv_std_logic_vector(19393,AMPL_WIDTH),
conv_std_logic_vector(19395,AMPL_WIDTH),
conv_std_logic_vector(19398,AMPL_WIDTH),
conv_std_logic_vector(19400,AMPL_WIDTH),
conv_std_logic_vector(19403,AMPL_WIDTH),
conv_std_logic_vector(19406,AMPL_WIDTH),
conv_std_logic_vector(19408,AMPL_WIDTH),
conv_std_logic_vector(19411,AMPL_WIDTH),
conv_std_logic_vector(19413,AMPL_WIDTH),
conv_std_logic_vector(19416,AMPL_WIDTH),
conv_std_logic_vector(19418,AMPL_WIDTH),
conv_std_logic_vector(19421,AMPL_WIDTH),
conv_std_logic_vector(19423,AMPL_WIDTH),
conv_std_logic_vector(19426,AMPL_WIDTH),
conv_std_logic_vector(19428,AMPL_WIDTH),
conv_std_logic_vector(19431,AMPL_WIDTH),
conv_std_logic_vector(19433,AMPL_WIDTH),
conv_std_logic_vector(19436,AMPL_WIDTH),
conv_std_logic_vector(19438,AMPL_WIDTH),
conv_std_logic_vector(19441,AMPL_WIDTH),
conv_std_logic_vector(19444,AMPL_WIDTH),
conv_std_logic_vector(19446,AMPL_WIDTH),
conv_std_logic_vector(19449,AMPL_WIDTH),
conv_std_logic_vector(19451,AMPL_WIDTH),
conv_std_logic_vector(19454,AMPL_WIDTH),
conv_std_logic_vector(19456,AMPL_WIDTH),
conv_std_logic_vector(19459,AMPL_WIDTH),
conv_std_logic_vector(19461,AMPL_WIDTH),
conv_std_logic_vector(19464,AMPL_WIDTH),
conv_std_logic_vector(19466,AMPL_WIDTH),
conv_std_logic_vector(19469,AMPL_WIDTH),
conv_std_logic_vector(19471,AMPL_WIDTH),
conv_std_logic_vector(19474,AMPL_WIDTH),
conv_std_logic_vector(19476,AMPL_WIDTH),
conv_std_logic_vector(19479,AMPL_WIDTH),
conv_std_logic_vector(19481,AMPL_WIDTH),
conv_std_logic_vector(19484,AMPL_WIDTH),
conv_std_logic_vector(19486,AMPL_WIDTH),
conv_std_logic_vector(19489,AMPL_WIDTH),
conv_std_logic_vector(19492,AMPL_WIDTH),
conv_std_logic_vector(19494,AMPL_WIDTH),
conv_std_logic_vector(19497,AMPL_WIDTH),
conv_std_logic_vector(19499,AMPL_WIDTH),
conv_std_logic_vector(19502,AMPL_WIDTH),
conv_std_logic_vector(19504,AMPL_WIDTH),
conv_std_logic_vector(19507,AMPL_WIDTH),
conv_std_logic_vector(19509,AMPL_WIDTH),
conv_std_logic_vector(19512,AMPL_WIDTH),
conv_std_logic_vector(19514,AMPL_WIDTH),
conv_std_logic_vector(19517,AMPL_WIDTH),
conv_std_logic_vector(19519,AMPL_WIDTH),
conv_std_logic_vector(19522,AMPL_WIDTH),
conv_std_logic_vector(19524,AMPL_WIDTH),
conv_std_logic_vector(19527,AMPL_WIDTH),
conv_std_logic_vector(19529,AMPL_WIDTH),
conv_std_logic_vector(19532,AMPL_WIDTH),
conv_std_logic_vector(19534,AMPL_WIDTH),
conv_std_logic_vector(19537,AMPL_WIDTH),
conv_std_logic_vector(19539,AMPL_WIDTH),
conv_std_logic_vector(19542,AMPL_WIDTH),
conv_std_logic_vector(19545,AMPL_WIDTH),
conv_std_logic_vector(19547,AMPL_WIDTH),
conv_std_logic_vector(19550,AMPL_WIDTH),
conv_std_logic_vector(19552,AMPL_WIDTH),
conv_std_logic_vector(19555,AMPL_WIDTH),
conv_std_logic_vector(19557,AMPL_WIDTH),
conv_std_logic_vector(19560,AMPL_WIDTH),
conv_std_logic_vector(19562,AMPL_WIDTH),
conv_std_logic_vector(19565,AMPL_WIDTH),
conv_std_logic_vector(19567,AMPL_WIDTH),
conv_std_logic_vector(19570,AMPL_WIDTH),
conv_std_logic_vector(19572,AMPL_WIDTH),
conv_std_logic_vector(19575,AMPL_WIDTH),
conv_std_logic_vector(19577,AMPL_WIDTH),
conv_std_logic_vector(19580,AMPL_WIDTH),
conv_std_logic_vector(19582,AMPL_WIDTH),
conv_std_logic_vector(19585,AMPL_WIDTH),
conv_std_logic_vector(19587,AMPL_WIDTH),
conv_std_logic_vector(19590,AMPL_WIDTH),
conv_std_logic_vector(19592,AMPL_WIDTH),
conv_std_logic_vector(19595,AMPL_WIDTH),
conv_std_logic_vector(19597,AMPL_WIDTH),
conv_std_logic_vector(19600,AMPL_WIDTH),
conv_std_logic_vector(19602,AMPL_WIDTH),
conv_std_logic_vector(19605,AMPL_WIDTH),
conv_std_logic_vector(19607,AMPL_WIDTH),
conv_std_logic_vector(19610,AMPL_WIDTH),
conv_std_logic_vector(19613,AMPL_WIDTH),
conv_std_logic_vector(19615,AMPL_WIDTH),
conv_std_logic_vector(19618,AMPL_WIDTH),
conv_std_logic_vector(19620,AMPL_WIDTH),
conv_std_logic_vector(19623,AMPL_WIDTH),
conv_std_logic_vector(19625,AMPL_WIDTH),
conv_std_logic_vector(19628,AMPL_WIDTH),
conv_std_logic_vector(19630,AMPL_WIDTH),
conv_std_logic_vector(19633,AMPL_WIDTH),
conv_std_logic_vector(19635,AMPL_WIDTH),
conv_std_logic_vector(19638,AMPL_WIDTH),
conv_std_logic_vector(19640,AMPL_WIDTH),
conv_std_logic_vector(19643,AMPL_WIDTH),
conv_std_logic_vector(19645,AMPL_WIDTH),
conv_std_logic_vector(19648,AMPL_WIDTH),
conv_std_logic_vector(19650,AMPL_WIDTH),
conv_std_logic_vector(19653,AMPL_WIDTH),
conv_std_logic_vector(19655,AMPL_WIDTH),
conv_std_logic_vector(19658,AMPL_WIDTH),
conv_std_logic_vector(19660,AMPL_WIDTH),
conv_std_logic_vector(19663,AMPL_WIDTH),
conv_std_logic_vector(19665,AMPL_WIDTH),
conv_std_logic_vector(19668,AMPL_WIDTH),
conv_std_logic_vector(19670,AMPL_WIDTH),
conv_std_logic_vector(19673,AMPL_WIDTH),
conv_std_logic_vector(19675,AMPL_WIDTH),
conv_std_logic_vector(19678,AMPL_WIDTH),
conv_std_logic_vector(19680,AMPL_WIDTH),
conv_std_logic_vector(19683,AMPL_WIDTH),
conv_std_logic_vector(19685,AMPL_WIDTH),
conv_std_logic_vector(19688,AMPL_WIDTH),
conv_std_logic_vector(19690,AMPL_WIDTH),
conv_std_logic_vector(19693,AMPL_WIDTH),
conv_std_logic_vector(19695,AMPL_WIDTH),
conv_std_logic_vector(19698,AMPL_WIDTH),
conv_std_logic_vector(19700,AMPL_WIDTH),
conv_std_logic_vector(19703,AMPL_WIDTH),
conv_std_logic_vector(19706,AMPL_WIDTH),
conv_std_logic_vector(19708,AMPL_WIDTH),
conv_std_logic_vector(19711,AMPL_WIDTH),
conv_std_logic_vector(19713,AMPL_WIDTH),
conv_std_logic_vector(19716,AMPL_WIDTH),
conv_std_logic_vector(19718,AMPL_WIDTH),
conv_std_logic_vector(19721,AMPL_WIDTH),
conv_std_logic_vector(19723,AMPL_WIDTH),
conv_std_logic_vector(19726,AMPL_WIDTH),
conv_std_logic_vector(19728,AMPL_WIDTH),
conv_std_logic_vector(19731,AMPL_WIDTH),
conv_std_logic_vector(19733,AMPL_WIDTH),
conv_std_logic_vector(19736,AMPL_WIDTH),
conv_std_logic_vector(19738,AMPL_WIDTH),
conv_std_logic_vector(19741,AMPL_WIDTH),
conv_std_logic_vector(19743,AMPL_WIDTH),
conv_std_logic_vector(19746,AMPL_WIDTH),
conv_std_logic_vector(19748,AMPL_WIDTH),
conv_std_logic_vector(19751,AMPL_WIDTH),
conv_std_logic_vector(19753,AMPL_WIDTH),
conv_std_logic_vector(19756,AMPL_WIDTH),
conv_std_logic_vector(19758,AMPL_WIDTH),
conv_std_logic_vector(19761,AMPL_WIDTH),
conv_std_logic_vector(19763,AMPL_WIDTH),
conv_std_logic_vector(19766,AMPL_WIDTH),
conv_std_logic_vector(19768,AMPL_WIDTH),
conv_std_logic_vector(19771,AMPL_WIDTH),
conv_std_logic_vector(19773,AMPL_WIDTH),
conv_std_logic_vector(19776,AMPL_WIDTH),
conv_std_logic_vector(19778,AMPL_WIDTH),
conv_std_logic_vector(19781,AMPL_WIDTH),
conv_std_logic_vector(19783,AMPL_WIDTH),
conv_std_logic_vector(19786,AMPL_WIDTH),
conv_std_logic_vector(19788,AMPL_WIDTH),
conv_std_logic_vector(19791,AMPL_WIDTH),
conv_std_logic_vector(19793,AMPL_WIDTH),
conv_std_logic_vector(19796,AMPL_WIDTH),
conv_std_logic_vector(19798,AMPL_WIDTH),
conv_std_logic_vector(19801,AMPL_WIDTH),
conv_std_logic_vector(19803,AMPL_WIDTH),
conv_std_logic_vector(19806,AMPL_WIDTH),
conv_std_logic_vector(19808,AMPL_WIDTH),
conv_std_logic_vector(19811,AMPL_WIDTH),
conv_std_logic_vector(19813,AMPL_WIDTH),
conv_std_logic_vector(19816,AMPL_WIDTH),
conv_std_logic_vector(19818,AMPL_WIDTH),
conv_std_logic_vector(19821,AMPL_WIDTH),
conv_std_logic_vector(19823,AMPL_WIDTH),
conv_std_logic_vector(19826,AMPL_WIDTH),
conv_std_logic_vector(19828,AMPL_WIDTH),
conv_std_logic_vector(19831,AMPL_WIDTH),
conv_std_logic_vector(19833,AMPL_WIDTH),
conv_std_logic_vector(19836,AMPL_WIDTH),
conv_std_logic_vector(19838,AMPL_WIDTH),
conv_std_logic_vector(19841,AMPL_WIDTH),
conv_std_logic_vector(19843,AMPL_WIDTH),
conv_std_logic_vector(19846,AMPL_WIDTH),
conv_std_logic_vector(19848,AMPL_WIDTH),
conv_std_logic_vector(19851,AMPL_WIDTH),
conv_std_logic_vector(19853,AMPL_WIDTH),
conv_std_logic_vector(19856,AMPL_WIDTH),
conv_std_logic_vector(19858,AMPL_WIDTH),
conv_std_logic_vector(19861,AMPL_WIDTH),
conv_std_logic_vector(19863,AMPL_WIDTH),
conv_std_logic_vector(19866,AMPL_WIDTH),
conv_std_logic_vector(19868,AMPL_WIDTH),
conv_std_logic_vector(19871,AMPL_WIDTH),
conv_std_logic_vector(19873,AMPL_WIDTH),
conv_std_logic_vector(19876,AMPL_WIDTH),
conv_std_logic_vector(19878,AMPL_WIDTH),
conv_std_logic_vector(19881,AMPL_WIDTH),
conv_std_logic_vector(19883,AMPL_WIDTH),
conv_std_logic_vector(19886,AMPL_WIDTH),
conv_std_logic_vector(19888,AMPL_WIDTH),
conv_std_logic_vector(19891,AMPL_WIDTH),
conv_std_logic_vector(19893,AMPL_WIDTH),
conv_std_logic_vector(19896,AMPL_WIDTH),
conv_std_logic_vector(19898,AMPL_WIDTH),
conv_std_logic_vector(19901,AMPL_WIDTH),
conv_std_logic_vector(19903,AMPL_WIDTH),
conv_std_logic_vector(19906,AMPL_WIDTH),
conv_std_logic_vector(19908,AMPL_WIDTH),
conv_std_logic_vector(19911,AMPL_WIDTH),
conv_std_logic_vector(19913,AMPL_WIDTH),
conv_std_logic_vector(19916,AMPL_WIDTH),
conv_std_logic_vector(19918,AMPL_WIDTH),
conv_std_logic_vector(19921,AMPL_WIDTH),
conv_std_logic_vector(19923,AMPL_WIDTH),
conv_std_logic_vector(19926,AMPL_WIDTH),
conv_std_logic_vector(19928,AMPL_WIDTH),
conv_std_logic_vector(19931,AMPL_WIDTH),
conv_std_logic_vector(19933,AMPL_WIDTH),
conv_std_logic_vector(19936,AMPL_WIDTH),
conv_std_logic_vector(19938,AMPL_WIDTH),
conv_std_logic_vector(19941,AMPL_WIDTH),
conv_std_logic_vector(19943,AMPL_WIDTH),
conv_std_logic_vector(19946,AMPL_WIDTH),
conv_std_logic_vector(19948,AMPL_WIDTH),
conv_std_logic_vector(19951,AMPL_WIDTH),
conv_std_logic_vector(19953,AMPL_WIDTH),
conv_std_logic_vector(19956,AMPL_WIDTH),
conv_std_logic_vector(19958,AMPL_WIDTH),
conv_std_logic_vector(19961,AMPL_WIDTH),
conv_std_logic_vector(19963,AMPL_WIDTH),
conv_std_logic_vector(19966,AMPL_WIDTH),
conv_std_logic_vector(19968,AMPL_WIDTH),
conv_std_logic_vector(19971,AMPL_WIDTH),
conv_std_logic_vector(19973,AMPL_WIDTH),
conv_std_logic_vector(19976,AMPL_WIDTH),
conv_std_logic_vector(19978,AMPL_WIDTH),
conv_std_logic_vector(19981,AMPL_WIDTH),
conv_std_logic_vector(19983,AMPL_WIDTH),
conv_std_logic_vector(19985,AMPL_WIDTH),
conv_std_logic_vector(19988,AMPL_WIDTH),
conv_std_logic_vector(19990,AMPL_WIDTH),
conv_std_logic_vector(19993,AMPL_WIDTH),
conv_std_logic_vector(19995,AMPL_WIDTH),
conv_std_logic_vector(19998,AMPL_WIDTH),
conv_std_logic_vector(20000,AMPL_WIDTH),
conv_std_logic_vector(20003,AMPL_WIDTH),
conv_std_logic_vector(20005,AMPL_WIDTH),
conv_std_logic_vector(20008,AMPL_WIDTH),
conv_std_logic_vector(20010,AMPL_WIDTH),
conv_std_logic_vector(20013,AMPL_WIDTH),
conv_std_logic_vector(20015,AMPL_WIDTH),
conv_std_logic_vector(20018,AMPL_WIDTH),
conv_std_logic_vector(20020,AMPL_WIDTH),
conv_std_logic_vector(20023,AMPL_WIDTH),
conv_std_logic_vector(20025,AMPL_WIDTH),
conv_std_logic_vector(20028,AMPL_WIDTH),
conv_std_logic_vector(20030,AMPL_WIDTH),
conv_std_logic_vector(20033,AMPL_WIDTH),
conv_std_logic_vector(20035,AMPL_WIDTH),
conv_std_logic_vector(20038,AMPL_WIDTH),
conv_std_logic_vector(20040,AMPL_WIDTH),
conv_std_logic_vector(20043,AMPL_WIDTH),
conv_std_logic_vector(20045,AMPL_WIDTH),
conv_std_logic_vector(20048,AMPL_WIDTH),
conv_std_logic_vector(20050,AMPL_WIDTH),
conv_std_logic_vector(20053,AMPL_WIDTH),
conv_std_logic_vector(20055,AMPL_WIDTH),
conv_std_logic_vector(20058,AMPL_WIDTH),
conv_std_logic_vector(20060,AMPL_WIDTH),
conv_std_logic_vector(20063,AMPL_WIDTH),
conv_std_logic_vector(20065,AMPL_WIDTH),
conv_std_logic_vector(20068,AMPL_WIDTH),
conv_std_logic_vector(20070,AMPL_WIDTH),
conv_std_logic_vector(20072,AMPL_WIDTH),
conv_std_logic_vector(20075,AMPL_WIDTH),
conv_std_logic_vector(20077,AMPL_WIDTH),
conv_std_logic_vector(20080,AMPL_WIDTH),
conv_std_logic_vector(20082,AMPL_WIDTH),
conv_std_logic_vector(20085,AMPL_WIDTH),
conv_std_logic_vector(20087,AMPL_WIDTH),
conv_std_logic_vector(20090,AMPL_WIDTH),
conv_std_logic_vector(20092,AMPL_WIDTH),
conv_std_logic_vector(20095,AMPL_WIDTH),
conv_std_logic_vector(20097,AMPL_WIDTH),
conv_std_logic_vector(20100,AMPL_WIDTH),
conv_std_logic_vector(20102,AMPL_WIDTH),
conv_std_logic_vector(20105,AMPL_WIDTH),
conv_std_logic_vector(20107,AMPL_WIDTH),
conv_std_logic_vector(20110,AMPL_WIDTH),
conv_std_logic_vector(20112,AMPL_WIDTH),
conv_std_logic_vector(20115,AMPL_WIDTH),
conv_std_logic_vector(20117,AMPL_WIDTH),
conv_std_logic_vector(20120,AMPL_WIDTH),
conv_std_logic_vector(20122,AMPL_WIDTH),
conv_std_logic_vector(20125,AMPL_WIDTH),
conv_std_logic_vector(20127,AMPL_WIDTH),
conv_std_logic_vector(20130,AMPL_WIDTH),
conv_std_logic_vector(20132,AMPL_WIDTH),
conv_std_logic_vector(20135,AMPL_WIDTH),
conv_std_logic_vector(20137,AMPL_WIDTH),
conv_std_logic_vector(20139,AMPL_WIDTH),
conv_std_logic_vector(20142,AMPL_WIDTH),
conv_std_logic_vector(20144,AMPL_WIDTH),
conv_std_logic_vector(20147,AMPL_WIDTH),
conv_std_logic_vector(20149,AMPL_WIDTH),
conv_std_logic_vector(20152,AMPL_WIDTH),
conv_std_logic_vector(20154,AMPL_WIDTH),
conv_std_logic_vector(20157,AMPL_WIDTH),
conv_std_logic_vector(20159,AMPL_WIDTH),
conv_std_logic_vector(20162,AMPL_WIDTH),
conv_std_logic_vector(20164,AMPL_WIDTH),
conv_std_logic_vector(20167,AMPL_WIDTH),
conv_std_logic_vector(20169,AMPL_WIDTH),
conv_std_logic_vector(20172,AMPL_WIDTH),
conv_std_logic_vector(20174,AMPL_WIDTH),
conv_std_logic_vector(20177,AMPL_WIDTH),
conv_std_logic_vector(20179,AMPL_WIDTH),
conv_std_logic_vector(20182,AMPL_WIDTH),
conv_std_logic_vector(20184,AMPL_WIDTH),
conv_std_logic_vector(20187,AMPL_WIDTH),
conv_std_logic_vector(20189,AMPL_WIDTH),
conv_std_logic_vector(20191,AMPL_WIDTH),
conv_std_logic_vector(20194,AMPL_WIDTH),
conv_std_logic_vector(20196,AMPL_WIDTH),
conv_std_logic_vector(20199,AMPL_WIDTH),
conv_std_logic_vector(20201,AMPL_WIDTH),
conv_std_logic_vector(20204,AMPL_WIDTH),
conv_std_logic_vector(20206,AMPL_WIDTH),
conv_std_logic_vector(20209,AMPL_WIDTH),
conv_std_logic_vector(20211,AMPL_WIDTH),
conv_std_logic_vector(20214,AMPL_WIDTH),
conv_std_logic_vector(20216,AMPL_WIDTH),
conv_std_logic_vector(20219,AMPL_WIDTH),
conv_std_logic_vector(20221,AMPL_WIDTH),
conv_std_logic_vector(20224,AMPL_WIDTH),
conv_std_logic_vector(20226,AMPL_WIDTH),
conv_std_logic_vector(20229,AMPL_WIDTH),
conv_std_logic_vector(20231,AMPL_WIDTH),
conv_std_logic_vector(20234,AMPL_WIDTH),
conv_std_logic_vector(20236,AMPL_WIDTH),
conv_std_logic_vector(20238,AMPL_WIDTH),
conv_std_logic_vector(20241,AMPL_WIDTH),
conv_std_logic_vector(20243,AMPL_WIDTH),
conv_std_logic_vector(20246,AMPL_WIDTH),
conv_std_logic_vector(20248,AMPL_WIDTH),
conv_std_logic_vector(20251,AMPL_WIDTH),
conv_std_logic_vector(20253,AMPL_WIDTH),
conv_std_logic_vector(20256,AMPL_WIDTH),
conv_std_logic_vector(20258,AMPL_WIDTH),
conv_std_logic_vector(20261,AMPL_WIDTH),
conv_std_logic_vector(20263,AMPL_WIDTH),
conv_std_logic_vector(20266,AMPL_WIDTH),
conv_std_logic_vector(20268,AMPL_WIDTH),
conv_std_logic_vector(20271,AMPL_WIDTH),
conv_std_logic_vector(20273,AMPL_WIDTH),
conv_std_logic_vector(20275,AMPL_WIDTH),
conv_std_logic_vector(20278,AMPL_WIDTH),
conv_std_logic_vector(20280,AMPL_WIDTH),
conv_std_logic_vector(20283,AMPL_WIDTH),
conv_std_logic_vector(20285,AMPL_WIDTH),
conv_std_logic_vector(20288,AMPL_WIDTH),
conv_std_logic_vector(20290,AMPL_WIDTH),
conv_std_logic_vector(20293,AMPL_WIDTH),
conv_std_logic_vector(20295,AMPL_WIDTH),
conv_std_logic_vector(20298,AMPL_WIDTH),
conv_std_logic_vector(20300,AMPL_WIDTH),
conv_std_logic_vector(20303,AMPL_WIDTH),
conv_std_logic_vector(20305,AMPL_WIDTH),
conv_std_logic_vector(20308,AMPL_WIDTH),
conv_std_logic_vector(20310,AMPL_WIDTH),
conv_std_logic_vector(20312,AMPL_WIDTH),
conv_std_logic_vector(20315,AMPL_WIDTH),
conv_std_logic_vector(20317,AMPL_WIDTH),
conv_std_logic_vector(20320,AMPL_WIDTH),
conv_std_logic_vector(20322,AMPL_WIDTH),
conv_std_logic_vector(20325,AMPL_WIDTH),
conv_std_logic_vector(20327,AMPL_WIDTH),
conv_std_logic_vector(20330,AMPL_WIDTH),
conv_std_logic_vector(20332,AMPL_WIDTH),
conv_std_logic_vector(20335,AMPL_WIDTH),
conv_std_logic_vector(20337,AMPL_WIDTH),
conv_std_logic_vector(20340,AMPL_WIDTH),
conv_std_logic_vector(20342,AMPL_WIDTH),
conv_std_logic_vector(20345,AMPL_WIDTH),
conv_std_logic_vector(20347,AMPL_WIDTH),
conv_std_logic_vector(20349,AMPL_WIDTH),
conv_std_logic_vector(20352,AMPL_WIDTH),
conv_std_logic_vector(20354,AMPL_WIDTH),
conv_std_logic_vector(20357,AMPL_WIDTH),
conv_std_logic_vector(20359,AMPL_WIDTH),
conv_std_logic_vector(20362,AMPL_WIDTH),
conv_std_logic_vector(20364,AMPL_WIDTH),
conv_std_logic_vector(20367,AMPL_WIDTH),
conv_std_logic_vector(20369,AMPL_WIDTH),
conv_std_logic_vector(20372,AMPL_WIDTH),
conv_std_logic_vector(20374,AMPL_WIDTH),
conv_std_logic_vector(20377,AMPL_WIDTH),
conv_std_logic_vector(20379,AMPL_WIDTH),
conv_std_logic_vector(20381,AMPL_WIDTH),
conv_std_logic_vector(20384,AMPL_WIDTH),
conv_std_logic_vector(20386,AMPL_WIDTH),
conv_std_logic_vector(20389,AMPL_WIDTH),
conv_std_logic_vector(20391,AMPL_WIDTH),
conv_std_logic_vector(20394,AMPL_WIDTH),
conv_std_logic_vector(20396,AMPL_WIDTH),
conv_std_logic_vector(20399,AMPL_WIDTH),
conv_std_logic_vector(20401,AMPL_WIDTH),
conv_std_logic_vector(20404,AMPL_WIDTH),
conv_std_logic_vector(20406,AMPL_WIDTH),
conv_std_logic_vector(20408,AMPL_WIDTH),
conv_std_logic_vector(20411,AMPL_WIDTH),
conv_std_logic_vector(20413,AMPL_WIDTH),
conv_std_logic_vector(20416,AMPL_WIDTH),
conv_std_logic_vector(20418,AMPL_WIDTH),
conv_std_logic_vector(20421,AMPL_WIDTH),
conv_std_logic_vector(20423,AMPL_WIDTH),
conv_std_logic_vector(20426,AMPL_WIDTH),
conv_std_logic_vector(20428,AMPL_WIDTH),
conv_std_logic_vector(20431,AMPL_WIDTH),
conv_std_logic_vector(20433,AMPL_WIDTH),
conv_std_logic_vector(20436,AMPL_WIDTH),
conv_std_logic_vector(20438,AMPL_WIDTH),
conv_std_logic_vector(20440,AMPL_WIDTH),
conv_std_logic_vector(20443,AMPL_WIDTH),
conv_std_logic_vector(20445,AMPL_WIDTH),
conv_std_logic_vector(20448,AMPL_WIDTH),
conv_std_logic_vector(20450,AMPL_WIDTH),
conv_std_logic_vector(20453,AMPL_WIDTH),
conv_std_logic_vector(20455,AMPL_WIDTH),
conv_std_logic_vector(20458,AMPL_WIDTH),
conv_std_logic_vector(20460,AMPL_WIDTH),
conv_std_logic_vector(20463,AMPL_WIDTH),
conv_std_logic_vector(20465,AMPL_WIDTH),
conv_std_logic_vector(20467,AMPL_WIDTH),
conv_std_logic_vector(20470,AMPL_WIDTH),
conv_std_logic_vector(20472,AMPL_WIDTH),
conv_std_logic_vector(20475,AMPL_WIDTH),
conv_std_logic_vector(20477,AMPL_WIDTH),
conv_std_logic_vector(20480,AMPL_WIDTH),
conv_std_logic_vector(20482,AMPL_WIDTH),
conv_std_logic_vector(20485,AMPL_WIDTH),
conv_std_logic_vector(20487,AMPL_WIDTH),
conv_std_logic_vector(20489,AMPL_WIDTH),
conv_std_logic_vector(20492,AMPL_WIDTH),
conv_std_logic_vector(20494,AMPL_WIDTH),
conv_std_logic_vector(20497,AMPL_WIDTH),
conv_std_logic_vector(20499,AMPL_WIDTH),
conv_std_logic_vector(20502,AMPL_WIDTH),
conv_std_logic_vector(20504,AMPL_WIDTH),
conv_std_logic_vector(20507,AMPL_WIDTH),
conv_std_logic_vector(20509,AMPL_WIDTH),
conv_std_logic_vector(20512,AMPL_WIDTH),
conv_std_logic_vector(20514,AMPL_WIDTH),
conv_std_logic_vector(20516,AMPL_WIDTH),
conv_std_logic_vector(20519,AMPL_WIDTH),
conv_std_logic_vector(20521,AMPL_WIDTH),
conv_std_logic_vector(20524,AMPL_WIDTH),
conv_std_logic_vector(20526,AMPL_WIDTH),
conv_std_logic_vector(20529,AMPL_WIDTH),
conv_std_logic_vector(20531,AMPL_WIDTH),
conv_std_logic_vector(20534,AMPL_WIDTH),
conv_std_logic_vector(20536,AMPL_WIDTH),
conv_std_logic_vector(20538,AMPL_WIDTH),
conv_std_logic_vector(20541,AMPL_WIDTH),
conv_std_logic_vector(20543,AMPL_WIDTH),
conv_std_logic_vector(20546,AMPL_WIDTH),
conv_std_logic_vector(20548,AMPL_WIDTH),
conv_std_logic_vector(20551,AMPL_WIDTH),
conv_std_logic_vector(20553,AMPL_WIDTH),
conv_std_logic_vector(20556,AMPL_WIDTH),
conv_std_logic_vector(20558,AMPL_WIDTH),
conv_std_logic_vector(20560,AMPL_WIDTH),
conv_std_logic_vector(20563,AMPL_WIDTH),
conv_std_logic_vector(20565,AMPL_WIDTH),
conv_std_logic_vector(20568,AMPL_WIDTH),
conv_std_logic_vector(20570,AMPL_WIDTH),
conv_std_logic_vector(20573,AMPL_WIDTH),
conv_std_logic_vector(20575,AMPL_WIDTH),
conv_std_logic_vector(20578,AMPL_WIDTH),
conv_std_logic_vector(20580,AMPL_WIDTH),
conv_std_logic_vector(20583,AMPL_WIDTH),
conv_std_logic_vector(20585,AMPL_WIDTH),
conv_std_logic_vector(20587,AMPL_WIDTH),
conv_std_logic_vector(20590,AMPL_WIDTH),
conv_std_logic_vector(20592,AMPL_WIDTH),
conv_std_logic_vector(20595,AMPL_WIDTH),
conv_std_logic_vector(20597,AMPL_WIDTH),
conv_std_logic_vector(20600,AMPL_WIDTH),
conv_std_logic_vector(20602,AMPL_WIDTH),
conv_std_logic_vector(20604,AMPL_WIDTH),
conv_std_logic_vector(20607,AMPL_WIDTH),
conv_std_logic_vector(20609,AMPL_WIDTH),
conv_std_logic_vector(20612,AMPL_WIDTH),
conv_std_logic_vector(20614,AMPL_WIDTH),
conv_std_logic_vector(20617,AMPL_WIDTH),
conv_std_logic_vector(20619,AMPL_WIDTH),
conv_std_logic_vector(20622,AMPL_WIDTH),
conv_std_logic_vector(20624,AMPL_WIDTH),
conv_std_logic_vector(20626,AMPL_WIDTH),
conv_std_logic_vector(20629,AMPL_WIDTH),
conv_std_logic_vector(20631,AMPL_WIDTH),
conv_std_logic_vector(20634,AMPL_WIDTH),
conv_std_logic_vector(20636,AMPL_WIDTH),
conv_std_logic_vector(20639,AMPL_WIDTH),
conv_std_logic_vector(20641,AMPL_WIDTH),
conv_std_logic_vector(20644,AMPL_WIDTH),
conv_std_logic_vector(20646,AMPL_WIDTH),
conv_std_logic_vector(20648,AMPL_WIDTH),
conv_std_logic_vector(20651,AMPL_WIDTH),
conv_std_logic_vector(20653,AMPL_WIDTH),
conv_std_logic_vector(20656,AMPL_WIDTH),
conv_std_logic_vector(20658,AMPL_WIDTH),
conv_std_logic_vector(20661,AMPL_WIDTH),
conv_std_logic_vector(20663,AMPL_WIDTH),
conv_std_logic_vector(20666,AMPL_WIDTH),
conv_std_logic_vector(20668,AMPL_WIDTH),
conv_std_logic_vector(20670,AMPL_WIDTH),
conv_std_logic_vector(20673,AMPL_WIDTH),
conv_std_logic_vector(20675,AMPL_WIDTH),
conv_std_logic_vector(20678,AMPL_WIDTH),
conv_std_logic_vector(20680,AMPL_WIDTH),
conv_std_logic_vector(20683,AMPL_WIDTH),
conv_std_logic_vector(20685,AMPL_WIDTH),
conv_std_logic_vector(20687,AMPL_WIDTH),
conv_std_logic_vector(20690,AMPL_WIDTH),
conv_std_logic_vector(20692,AMPL_WIDTH),
conv_std_logic_vector(20695,AMPL_WIDTH),
conv_std_logic_vector(20697,AMPL_WIDTH),
conv_std_logic_vector(20700,AMPL_WIDTH),
conv_std_logic_vector(20702,AMPL_WIDTH),
conv_std_logic_vector(20704,AMPL_WIDTH),
conv_std_logic_vector(20707,AMPL_WIDTH),
conv_std_logic_vector(20709,AMPL_WIDTH),
conv_std_logic_vector(20712,AMPL_WIDTH),
conv_std_logic_vector(20714,AMPL_WIDTH),
conv_std_logic_vector(20717,AMPL_WIDTH),
conv_std_logic_vector(20719,AMPL_WIDTH),
conv_std_logic_vector(20722,AMPL_WIDTH),
conv_std_logic_vector(20724,AMPL_WIDTH),
conv_std_logic_vector(20726,AMPL_WIDTH),
conv_std_logic_vector(20729,AMPL_WIDTH),
conv_std_logic_vector(20731,AMPL_WIDTH),
conv_std_logic_vector(20734,AMPL_WIDTH),
conv_std_logic_vector(20736,AMPL_WIDTH),
conv_std_logic_vector(20739,AMPL_WIDTH),
conv_std_logic_vector(20741,AMPL_WIDTH),
conv_std_logic_vector(20743,AMPL_WIDTH),
conv_std_logic_vector(20746,AMPL_WIDTH),
conv_std_logic_vector(20748,AMPL_WIDTH),
conv_std_logic_vector(20751,AMPL_WIDTH),
conv_std_logic_vector(20753,AMPL_WIDTH),
conv_std_logic_vector(20756,AMPL_WIDTH),
conv_std_logic_vector(20758,AMPL_WIDTH),
conv_std_logic_vector(20760,AMPL_WIDTH),
conv_std_logic_vector(20763,AMPL_WIDTH),
conv_std_logic_vector(20765,AMPL_WIDTH),
conv_std_logic_vector(20768,AMPL_WIDTH),
conv_std_logic_vector(20770,AMPL_WIDTH),
conv_std_logic_vector(20773,AMPL_WIDTH),
conv_std_logic_vector(20775,AMPL_WIDTH),
conv_std_logic_vector(20777,AMPL_WIDTH),
conv_std_logic_vector(20780,AMPL_WIDTH),
conv_std_logic_vector(20782,AMPL_WIDTH),
conv_std_logic_vector(20785,AMPL_WIDTH),
conv_std_logic_vector(20787,AMPL_WIDTH),
conv_std_logic_vector(20790,AMPL_WIDTH),
conv_std_logic_vector(20792,AMPL_WIDTH),
conv_std_logic_vector(20794,AMPL_WIDTH),
conv_std_logic_vector(20797,AMPL_WIDTH),
conv_std_logic_vector(20799,AMPL_WIDTH),
conv_std_logic_vector(20802,AMPL_WIDTH),
conv_std_logic_vector(20804,AMPL_WIDTH),
conv_std_logic_vector(20807,AMPL_WIDTH),
conv_std_logic_vector(20809,AMPL_WIDTH),
conv_std_logic_vector(20811,AMPL_WIDTH),
conv_std_logic_vector(20814,AMPL_WIDTH),
conv_std_logic_vector(20816,AMPL_WIDTH),
conv_std_logic_vector(20819,AMPL_WIDTH),
conv_std_logic_vector(20821,AMPL_WIDTH),
conv_std_logic_vector(20824,AMPL_WIDTH),
conv_std_logic_vector(20826,AMPL_WIDTH),
conv_std_logic_vector(20828,AMPL_WIDTH),
conv_std_logic_vector(20831,AMPL_WIDTH),
conv_std_logic_vector(20833,AMPL_WIDTH),
conv_std_logic_vector(20836,AMPL_WIDTH),
conv_std_logic_vector(20838,AMPL_WIDTH),
conv_std_logic_vector(20841,AMPL_WIDTH),
conv_std_logic_vector(20843,AMPL_WIDTH),
conv_std_logic_vector(20845,AMPL_WIDTH),
conv_std_logic_vector(20848,AMPL_WIDTH),
conv_std_logic_vector(20850,AMPL_WIDTH),
conv_std_logic_vector(20853,AMPL_WIDTH),
conv_std_logic_vector(20855,AMPL_WIDTH),
conv_std_logic_vector(20858,AMPL_WIDTH),
conv_std_logic_vector(20860,AMPL_WIDTH),
conv_std_logic_vector(20862,AMPL_WIDTH),
conv_std_logic_vector(20865,AMPL_WIDTH),
conv_std_logic_vector(20867,AMPL_WIDTH),
conv_std_logic_vector(20870,AMPL_WIDTH),
conv_std_logic_vector(20872,AMPL_WIDTH),
conv_std_logic_vector(20874,AMPL_WIDTH),
conv_std_logic_vector(20877,AMPL_WIDTH),
conv_std_logic_vector(20879,AMPL_WIDTH),
conv_std_logic_vector(20882,AMPL_WIDTH),
conv_std_logic_vector(20884,AMPL_WIDTH),
conv_std_logic_vector(20887,AMPL_WIDTH),
conv_std_logic_vector(20889,AMPL_WIDTH),
conv_std_logic_vector(20891,AMPL_WIDTH),
conv_std_logic_vector(20894,AMPL_WIDTH),
conv_std_logic_vector(20896,AMPL_WIDTH),
conv_std_logic_vector(20899,AMPL_WIDTH),
conv_std_logic_vector(20901,AMPL_WIDTH),
conv_std_logic_vector(20904,AMPL_WIDTH),
conv_std_logic_vector(20906,AMPL_WIDTH),
conv_std_logic_vector(20908,AMPL_WIDTH),
conv_std_logic_vector(20911,AMPL_WIDTH),
conv_std_logic_vector(20913,AMPL_WIDTH),
conv_std_logic_vector(20916,AMPL_WIDTH),
conv_std_logic_vector(20918,AMPL_WIDTH),
conv_std_logic_vector(20920,AMPL_WIDTH),
conv_std_logic_vector(20923,AMPL_WIDTH),
conv_std_logic_vector(20925,AMPL_WIDTH),
conv_std_logic_vector(20928,AMPL_WIDTH),
conv_std_logic_vector(20930,AMPL_WIDTH),
conv_std_logic_vector(20933,AMPL_WIDTH),
conv_std_logic_vector(20935,AMPL_WIDTH),
conv_std_logic_vector(20937,AMPL_WIDTH),
conv_std_logic_vector(20940,AMPL_WIDTH),
conv_std_logic_vector(20942,AMPL_WIDTH),
conv_std_logic_vector(20945,AMPL_WIDTH),
conv_std_logic_vector(20947,AMPL_WIDTH),
conv_std_logic_vector(20949,AMPL_WIDTH),
conv_std_logic_vector(20952,AMPL_WIDTH),
conv_std_logic_vector(20954,AMPL_WIDTH),
conv_std_logic_vector(20957,AMPL_WIDTH),
conv_std_logic_vector(20959,AMPL_WIDTH),
conv_std_logic_vector(20962,AMPL_WIDTH),
conv_std_logic_vector(20964,AMPL_WIDTH),
conv_std_logic_vector(20966,AMPL_WIDTH),
conv_std_logic_vector(20969,AMPL_WIDTH),
conv_std_logic_vector(20971,AMPL_WIDTH),
conv_std_logic_vector(20974,AMPL_WIDTH),
conv_std_logic_vector(20976,AMPL_WIDTH),
conv_std_logic_vector(20978,AMPL_WIDTH),
conv_std_logic_vector(20981,AMPL_WIDTH),
conv_std_logic_vector(20983,AMPL_WIDTH),
conv_std_logic_vector(20986,AMPL_WIDTH),
conv_std_logic_vector(20988,AMPL_WIDTH),
conv_std_logic_vector(20990,AMPL_WIDTH),
conv_std_logic_vector(20993,AMPL_WIDTH),
conv_std_logic_vector(20995,AMPL_WIDTH),
conv_std_logic_vector(20998,AMPL_WIDTH),
conv_std_logic_vector(21000,AMPL_WIDTH),
conv_std_logic_vector(21003,AMPL_WIDTH),
conv_std_logic_vector(21005,AMPL_WIDTH),
conv_std_logic_vector(21007,AMPL_WIDTH),
conv_std_logic_vector(21010,AMPL_WIDTH),
conv_std_logic_vector(21012,AMPL_WIDTH),
conv_std_logic_vector(21015,AMPL_WIDTH),
conv_std_logic_vector(21017,AMPL_WIDTH),
conv_std_logic_vector(21019,AMPL_WIDTH),
conv_std_logic_vector(21022,AMPL_WIDTH),
conv_std_logic_vector(21024,AMPL_WIDTH),
conv_std_logic_vector(21027,AMPL_WIDTH),
conv_std_logic_vector(21029,AMPL_WIDTH),
conv_std_logic_vector(21031,AMPL_WIDTH),
conv_std_logic_vector(21034,AMPL_WIDTH),
conv_std_logic_vector(21036,AMPL_WIDTH),
conv_std_logic_vector(21039,AMPL_WIDTH),
conv_std_logic_vector(21041,AMPL_WIDTH),
conv_std_logic_vector(21043,AMPL_WIDTH),
conv_std_logic_vector(21046,AMPL_WIDTH),
conv_std_logic_vector(21048,AMPL_WIDTH),
conv_std_logic_vector(21051,AMPL_WIDTH),
conv_std_logic_vector(21053,AMPL_WIDTH),
conv_std_logic_vector(21056,AMPL_WIDTH),
conv_std_logic_vector(21058,AMPL_WIDTH),
conv_std_logic_vector(21060,AMPL_WIDTH),
conv_std_logic_vector(21063,AMPL_WIDTH),
conv_std_logic_vector(21065,AMPL_WIDTH),
conv_std_logic_vector(21068,AMPL_WIDTH),
conv_std_logic_vector(21070,AMPL_WIDTH),
conv_std_logic_vector(21072,AMPL_WIDTH),
conv_std_logic_vector(21075,AMPL_WIDTH),
conv_std_logic_vector(21077,AMPL_WIDTH),
conv_std_logic_vector(21080,AMPL_WIDTH),
conv_std_logic_vector(21082,AMPL_WIDTH),
conv_std_logic_vector(21084,AMPL_WIDTH),
conv_std_logic_vector(21087,AMPL_WIDTH),
conv_std_logic_vector(21089,AMPL_WIDTH),
conv_std_logic_vector(21092,AMPL_WIDTH),
conv_std_logic_vector(21094,AMPL_WIDTH),
conv_std_logic_vector(21096,AMPL_WIDTH),
conv_std_logic_vector(21099,AMPL_WIDTH),
conv_std_logic_vector(21101,AMPL_WIDTH),
conv_std_logic_vector(21104,AMPL_WIDTH),
conv_std_logic_vector(21106,AMPL_WIDTH),
conv_std_logic_vector(21108,AMPL_WIDTH),
conv_std_logic_vector(21111,AMPL_WIDTH),
conv_std_logic_vector(21113,AMPL_WIDTH),
conv_std_logic_vector(21116,AMPL_WIDTH),
conv_std_logic_vector(21118,AMPL_WIDTH),
conv_std_logic_vector(21120,AMPL_WIDTH),
conv_std_logic_vector(21123,AMPL_WIDTH),
conv_std_logic_vector(21125,AMPL_WIDTH),
conv_std_logic_vector(21128,AMPL_WIDTH),
conv_std_logic_vector(21130,AMPL_WIDTH),
conv_std_logic_vector(21132,AMPL_WIDTH),
conv_std_logic_vector(21135,AMPL_WIDTH),
conv_std_logic_vector(21137,AMPL_WIDTH),
conv_std_logic_vector(21140,AMPL_WIDTH),
conv_std_logic_vector(21142,AMPL_WIDTH),
conv_std_logic_vector(21144,AMPL_WIDTH),
conv_std_logic_vector(21147,AMPL_WIDTH),
conv_std_logic_vector(21149,AMPL_WIDTH),
conv_std_logic_vector(21152,AMPL_WIDTH),
conv_std_logic_vector(21154,AMPL_WIDTH),
conv_std_logic_vector(21156,AMPL_WIDTH),
conv_std_logic_vector(21159,AMPL_WIDTH),
conv_std_logic_vector(21161,AMPL_WIDTH),
conv_std_logic_vector(21164,AMPL_WIDTH),
conv_std_logic_vector(21166,AMPL_WIDTH),
conv_std_logic_vector(21168,AMPL_WIDTH),
conv_std_logic_vector(21171,AMPL_WIDTH),
conv_std_logic_vector(21173,AMPL_WIDTH),
conv_std_logic_vector(21176,AMPL_WIDTH),
conv_std_logic_vector(21178,AMPL_WIDTH),
conv_std_logic_vector(21180,AMPL_WIDTH),
conv_std_logic_vector(21183,AMPL_WIDTH),
conv_std_logic_vector(21185,AMPL_WIDTH),
conv_std_logic_vector(21188,AMPL_WIDTH),
conv_std_logic_vector(21190,AMPL_WIDTH),
conv_std_logic_vector(21192,AMPL_WIDTH),
conv_std_logic_vector(21195,AMPL_WIDTH),
conv_std_logic_vector(21197,AMPL_WIDTH),
conv_std_logic_vector(21200,AMPL_WIDTH),
conv_std_logic_vector(21202,AMPL_WIDTH),
conv_std_logic_vector(21204,AMPL_WIDTH),
conv_std_logic_vector(21207,AMPL_WIDTH),
conv_std_logic_vector(21209,AMPL_WIDTH),
conv_std_logic_vector(21212,AMPL_WIDTH),
conv_std_logic_vector(21214,AMPL_WIDTH),
conv_std_logic_vector(21216,AMPL_WIDTH),
conv_std_logic_vector(21219,AMPL_WIDTH),
conv_std_logic_vector(21221,AMPL_WIDTH),
conv_std_logic_vector(21224,AMPL_WIDTH),
conv_std_logic_vector(21226,AMPL_WIDTH),
conv_std_logic_vector(21228,AMPL_WIDTH),
conv_std_logic_vector(21231,AMPL_WIDTH),
conv_std_logic_vector(21233,AMPL_WIDTH),
conv_std_logic_vector(21236,AMPL_WIDTH),
conv_std_logic_vector(21238,AMPL_WIDTH),
conv_std_logic_vector(21240,AMPL_WIDTH),
conv_std_logic_vector(21243,AMPL_WIDTH),
conv_std_logic_vector(21245,AMPL_WIDTH),
conv_std_logic_vector(21247,AMPL_WIDTH),
conv_std_logic_vector(21250,AMPL_WIDTH),
conv_std_logic_vector(21252,AMPL_WIDTH),
conv_std_logic_vector(21255,AMPL_WIDTH),
conv_std_logic_vector(21257,AMPL_WIDTH),
conv_std_logic_vector(21259,AMPL_WIDTH),
conv_std_logic_vector(21262,AMPL_WIDTH),
conv_std_logic_vector(21264,AMPL_WIDTH),
conv_std_logic_vector(21267,AMPL_WIDTH),
conv_std_logic_vector(21269,AMPL_WIDTH),
conv_std_logic_vector(21271,AMPL_WIDTH),
conv_std_logic_vector(21274,AMPL_WIDTH),
conv_std_logic_vector(21276,AMPL_WIDTH),
conv_std_logic_vector(21279,AMPL_WIDTH),
conv_std_logic_vector(21281,AMPL_WIDTH),
conv_std_logic_vector(21283,AMPL_WIDTH),
conv_std_logic_vector(21286,AMPL_WIDTH),
conv_std_logic_vector(21288,AMPL_WIDTH),
conv_std_logic_vector(21290,AMPL_WIDTH),
conv_std_logic_vector(21293,AMPL_WIDTH),
conv_std_logic_vector(21295,AMPL_WIDTH),
conv_std_logic_vector(21298,AMPL_WIDTH),
conv_std_logic_vector(21300,AMPL_WIDTH),
conv_std_logic_vector(21302,AMPL_WIDTH),
conv_std_logic_vector(21305,AMPL_WIDTH),
conv_std_logic_vector(21307,AMPL_WIDTH),
conv_std_logic_vector(21310,AMPL_WIDTH),
conv_std_logic_vector(21312,AMPL_WIDTH),
conv_std_logic_vector(21314,AMPL_WIDTH),
conv_std_logic_vector(21317,AMPL_WIDTH),
conv_std_logic_vector(21319,AMPL_WIDTH),
conv_std_logic_vector(21322,AMPL_WIDTH),
conv_std_logic_vector(21324,AMPL_WIDTH),
conv_std_logic_vector(21326,AMPL_WIDTH),
conv_std_logic_vector(21329,AMPL_WIDTH),
conv_std_logic_vector(21331,AMPL_WIDTH),
conv_std_logic_vector(21333,AMPL_WIDTH),
conv_std_logic_vector(21336,AMPL_WIDTH),
conv_std_logic_vector(21338,AMPL_WIDTH),
conv_std_logic_vector(21341,AMPL_WIDTH),
conv_std_logic_vector(21343,AMPL_WIDTH),
conv_std_logic_vector(21345,AMPL_WIDTH),
conv_std_logic_vector(21348,AMPL_WIDTH),
conv_std_logic_vector(21350,AMPL_WIDTH),
conv_std_logic_vector(21353,AMPL_WIDTH),
conv_std_logic_vector(21355,AMPL_WIDTH),
conv_std_logic_vector(21357,AMPL_WIDTH),
conv_std_logic_vector(21360,AMPL_WIDTH),
conv_std_logic_vector(21362,AMPL_WIDTH),
conv_std_logic_vector(21364,AMPL_WIDTH),
conv_std_logic_vector(21367,AMPL_WIDTH),
conv_std_logic_vector(21369,AMPL_WIDTH),
conv_std_logic_vector(21372,AMPL_WIDTH),
conv_std_logic_vector(21374,AMPL_WIDTH),
conv_std_logic_vector(21376,AMPL_WIDTH),
conv_std_logic_vector(21379,AMPL_WIDTH),
conv_std_logic_vector(21381,AMPL_WIDTH),
conv_std_logic_vector(21383,AMPL_WIDTH),
conv_std_logic_vector(21386,AMPL_WIDTH),
conv_std_logic_vector(21388,AMPL_WIDTH),
conv_std_logic_vector(21391,AMPL_WIDTH),
conv_std_logic_vector(21393,AMPL_WIDTH),
conv_std_logic_vector(21395,AMPL_WIDTH),
conv_std_logic_vector(21398,AMPL_WIDTH),
conv_std_logic_vector(21400,AMPL_WIDTH),
conv_std_logic_vector(21403,AMPL_WIDTH),
conv_std_logic_vector(21405,AMPL_WIDTH),
conv_std_logic_vector(21407,AMPL_WIDTH),
conv_std_logic_vector(21410,AMPL_WIDTH),
conv_std_logic_vector(21412,AMPL_WIDTH),
conv_std_logic_vector(21414,AMPL_WIDTH),
conv_std_logic_vector(21417,AMPL_WIDTH),
conv_std_logic_vector(21419,AMPL_WIDTH),
conv_std_logic_vector(21422,AMPL_WIDTH),
conv_std_logic_vector(21424,AMPL_WIDTH),
conv_std_logic_vector(21426,AMPL_WIDTH),
conv_std_logic_vector(21429,AMPL_WIDTH),
conv_std_logic_vector(21431,AMPL_WIDTH),
conv_std_logic_vector(21433,AMPL_WIDTH),
conv_std_logic_vector(21436,AMPL_WIDTH),
conv_std_logic_vector(21438,AMPL_WIDTH),
conv_std_logic_vector(21441,AMPL_WIDTH),
conv_std_logic_vector(21443,AMPL_WIDTH),
conv_std_logic_vector(21445,AMPL_WIDTH),
conv_std_logic_vector(21448,AMPL_WIDTH),
conv_std_logic_vector(21450,AMPL_WIDTH),
conv_std_logic_vector(21452,AMPL_WIDTH),
conv_std_logic_vector(21455,AMPL_WIDTH),
conv_std_logic_vector(21457,AMPL_WIDTH),
conv_std_logic_vector(21460,AMPL_WIDTH),
conv_std_logic_vector(21462,AMPL_WIDTH),
conv_std_logic_vector(21464,AMPL_WIDTH),
conv_std_logic_vector(21467,AMPL_WIDTH),
conv_std_logic_vector(21469,AMPL_WIDTH),
conv_std_logic_vector(21471,AMPL_WIDTH),
conv_std_logic_vector(21474,AMPL_WIDTH),
conv_std_logic_vector(21476,AMPL_WIDTH),
conv_std_logic_vector(21479,AMPL_WIDTH),
conv_std_logic_vector(21481,AMPL_WIDTH),
conv_std_logic_vector(21483,AMPL_WIDTH),
conv_std_logic_vector(21486,AMPL_WIDTH),
conv_std_logic_vector(21488,AMPL_WIDTH),
conv_std_logic_vector(21490,AMPL_WIDTH),
conv_std_logic_vector(21493,AMPL_WIDTH),
conv_std_logic_vector(21495,AMPL_WIDTH),
conv_std_logic_vector(21498,AMPL_WIDTH),
conv_std_logic_vector(21500,AMPL_WIDTH),
conv_std_logic_vector(21502,AMPL_WIDTH),
conv_std_logic_vector(21505,AMPL_WIDTH),
conv_std_logic_vector(21507,AMPL_WIDTH),
conv_std_logic_vector(21509,AMPL_WIDTH),
conv_std_logic_vector(21512,AMPL_WIDTH),
conv_std_logic_vector(21514,AMPL_WIDTH),
conv_std_logic_vector(21516,AMPL_WIDTH),
conv_std_logic_vector(21519,AMPL_WIDTH),
conv_std_logic_vector(21521,AMPL_WIDTH),
conv_std_logic_vector(21524,AMPL_WIDTH),
conv_std_logic_vector(21526,AMPL_WIDTH),
conv_std_logic_vector(21528,AMPL_WIDTH),
conv_std_logic_vector(21531,AMPL_WIDTH),
conv_std_logic_vector(21533,AMPL_WIDTH),
conv_std_logic_vector(21535,AMPL_WIDTH),
conv_std_logic_vector(21538,AMPL_WIDTH),
conv_std_logic_vector(21540,AMPL_WIDTH),
conv_std_logic_vector(21543,AMPL_WIDTH),
conv_std_logic_vector(21545,AMPL_WIDTH),
conv_std_logic_vector(21547,AMPL_WIDTH),
conv_std_logic_vector(21550,AMPL_WIDTH),
conv_std_logic_vector(21552,AMPL_WIDTH),
conv_std_logic_vector(21554,AMPL_WIDTH),
conv_std_logic_vector(21557,AMPL_WIDTH),
conv_std_logic_vector(21559,AMPL_WIDTH),
conv_std_logic_vector(21561,AMPL_WIDTH),
conv_std_logic_vector(21564,AMPL_WIDTH),
conv_std_logic_vector(21566,AMPL_WIDTH),
conv_std_logic_vector(21569,AMPL_WIDTH),
conv_std_logic_vector(21571,AMPL_WIDTH),
conv_std_logic_vector(21573,AMPL_WIDTH),
conv_std_logic_vector(21576,AMPL_WIDTH),
conv_std_logic_vector(21578,AMPL_WIDTH),
conv_std_logic_vector(21580,AMPL_WIDTH),
conv_std_logic_vector(21583,AMPL_WIDTH),
conv_std_logic_vector(21585,AMPL_WIDTH),
conv_std_logic_vector(21587,AMPL_WIDTH),
conv_std_logic_vector(21590,AMPL_WIDTH),
conv_std_logic_vector(21592,AMPL_WIDTH),
conv_std_logic_vector(21595,AMPL_WIDTH),
conv_std_logic_vector(21597,AMPL_WIDTH),
conv_std_logic_vector(21599,AMPL_WIDTH),
conv_std_logic_vector(21602,AMPL_WIDTH),
conv_std_logic_vector(21604,AMPL_WIDTH),
conv_std_logic_vector(21606,AMPL_WIDTH),
conv_std_logic_vector(21609,AMPL_WIDTH),
conv_std_logic_vector(21611,AMPL_WIDTH),
conv_std_logic_vector(21613,AMPL_WIDTH),
conv_std_logic_vector(21616,AMPL_WIDTH),
conv_std_logic_vector(21618,AMPL_WIDTH),
conv_std_logic_vector(21621,AMPL_WIDTH),
conv_std_logic_vector(21623,AMPL_WIDTH),
conv_std_logic_vector(21625,AMPL_WIDTH),
conv_std_logic_vector(21628,AMPL_WIDTH),
conv_std_logic_vector(21630,AMPL_WIDTH),
conv_std_logic_vector(21632,AMPL_WIDTH),
conv_std_logic_vector(21635,AMPL_WIDTH),
conv_std_logic_vector(21637,AMPL_WIDTH),
conv_std_logic_vector(21639,AMPL_WIDTH),
conv_std_logic_vector(21642,AMPL_WIDTH),
conv_std_logic_vector(21644,AMPL_WIDTH),
conv_std_logic_vector(21646,AMPL_WIDTH),
conv_std_logic_vector(21649,AMPL_WIDTH),
conv_std_logic_vector(21651,AMPL_WIDTH),
conv_std_logic_vector(21654,AMPL_WIDTH),
conv_std_logic_vector(21656,AMPL_WIDTH),
conv_std_logic_vector(21658,AMPL_WIDTH),
conv_std_logic_vector(21661,AMPL_WIDTH),
conv_std_logic_vector(21663,AMPL_WIDTH),
conv_std_logic_vector(21665,AMPL_WIDTH),
conv_std_logic_vector(21668,AMPL_WIDTH),
conv_std_logic_vector(21670,AMPL_WIDTH),
conv_std_logic_vector(21672,AMPL_WIDTH),
conv_std_logic_vector(21675,AMPL_WIDTH),
conv_std_logic_vector(21677,AMPL_WIDTH),
conv_std_logic_vector(21679,AMPL_WIDTH),
conv_std_logic_vector(21682,AMPL_WIDTH),
conv_std_logic_vector(21684,AMPL_WIDTH),
conv_std_logic_vector(21687,AMPL_WIDTH),
conv_std_logic_vector(21689,AMPL_WIDTH),
conv_std_logic_vector(21691,AMPL_WIDTH),
conv_std_logic_vector(21694,AMPL_WIDTH),
conv_std_logic_vector(21696,AMPL_WIDTH),
conv_std_logic_vector(21698,AMPL_WIDTH),
conv_std_logic_vector(21701,AMPL_WIDTH),
conv_std_logic_vector(21703,AMPL_WIDTH),
conv_std_logic_vector(21705,AMPL_WIDTH),
conv_std_logic_vector(21708,AMPL_WIDTH),
conv_std_logic_vector(21710,AMPL_WIDTH),
conv_std_logic_vector(21712,AMPL_WIDTH),
conv_std_logic_vector(21715,AMPL_WIDTH),
conv_std_logic_vector(21717,AMPL_WIDTH),
conv_std_logic_vector(21719,AMPL_WIDTH),
conv_std_logic_vector(21722,AMPL_WIDTH),
conv_std_logic_vector(21724,AMPL_WIDTH),
conv_std_logic_vector(21727,AMPL_WIDTH),
conv_std_logic_vector(21729,AMPL_WIDTH),
conv_std_logic_vector(21731,AMPL_WIDTH),
conv_std_logic_vector(21734,AMPL_WIDTH),
conv_std_logic_vector(21736,AMPL_WIDTH),
conv_std_logic_vector(21738,AMPL_WIDTH),
conv_std_logic_vector(21741,AMPL_WIDTH),
conv_std_logic_vector(21743,AMPL_WIDTH),
conv_std_logic_vector(21745,AMPL_WIDTH),
conv_std_logic_vector(21748,AMPL_WIDTH),
conv_std_logic_vector(21750,AMPL_WIDTH),
conv_std_logic_vector(21752,AMPL_WIDTH),
conv_std_logic_vector(21755,AMPL_WIDTH),
conv_std_logic_vector(21757,AMPL_WIDTH),
conv_std_logic_vector(21759,AMPL_WIDTH),
conv_std_logic_vector(21762,AMPL_WIDTH),
conv_std_logic_vector(21764,AMPL_WIDTH),
conv_std_logic_vector(21766,AMPL_WIDTH),
conv_std_logic_vector(21769,AMPL_WIDTH),
conv_std_logic_vector(21771,AMPL_WIDTH),
conv_std_logic_vector(21774,AMPL_WIDTH),
conv_std_logic_vector(21776,AMPL_WIDTH),
conv_std_logic_vector(21778,AMPL_WIDTH),
conv_std_logic_vector(21781,AMPL_WIDTH),
conv_std_logic_vector(21783,AMPL_WIDTH),
conv_std_logic_vector(21785,AMPL_WIDTH),
conv_std_logic_vector(21788,AMPL_WIDTH),
conv_std_logic_vector(21790,AMPL_WIDTH),
conv_std_logic_vector(21792,AMPL_WIDTH),
conv_std_logic_vector(21795,AMPL_WIDTH),
conv_std_logic_vector(21797,AMPL_WIDTH),
conv_std_logic_vector(21799,AMPL_WIDTH),
conv_std_logic_vector(21802,AMPL_WIDTH),
conv_std_logic_vector(21804,AMPL_WIDTH),
conv_std_logic_vector(21806,AMPL_WIDTH),
conv_std_logic_vector(21809,AMPL_WIDTH),
conv_std_logic_vector(21811,AMPL_WIDTH),
conv_std_logic_vector(21813,AMPL_WIDTH),
conv_std_logic_vector(21816,AMPL_WIDTH),
conv_std_logic_vector(21818,AMPL_WIDTH),
conv_std_logic_vector(21820,AMPL_WIDTH),
conv_std_logic_vector(21823,AMPL_WIDTH),
conv_std_logic_vector(21825,AMPL_WIDTH),
conv_std_logic_vector(21827,AMPL_WIDTH),
conv_std_logic_vector(21830,AMPL_WIDTH),
conv_std_logic_vector(21832,AMPL_WIDTH),
conv_std_logic_vector(21835,AMPL_WIDTH),
conv_std_logic_vector(21837,AMPL_WIDTH),
conv_std_logic_vector(21839,AMPL_WIDTH),
conv_std_logic_vector(21842,AMPL_WIDTH),
conv_std_logic_vector(21844,AMPL_WIDTH),
conv_std_logic_vector(21846,AMPL_WIDTH),
conv_std_logic_vector(21849,AMPL_WIDTH),
conv_std_logic_vector(21851,AMPL_WIDTH),
conv_std_logic_vector(21853,AMPL_WIDTH),
conv_std_logic_vector(21856,AMPL_WIDTH),
conv_std_logic_vector(21858,AMPL_WIDTH),
conv_std_logic_vector(21860,AMPL_WIDTH),
conv_std_logic_vector(21863,AMPL_WIDTH),
conv_std_logic_vector(21865,AMPL_WIDTH),
conv_std_logic_vector(21867,AMPL_WIDTH),
conv_std_logic_vector(21870,AMPL_WIDTH),
conv_std_logic_vector(21872,AMPL_WIDTH),
conv_std_logic_vector(21874,AMPL_WIDTH),
conv_std_logic_vector(21877,AMPL_WIDTH),
conv_std_logic_vector(21879,AMPL_WIDTH),
conv_std_logic_vector(21881,AMPL_WIDTH),
conv_std_logic_vector(21884,AMPL_WIDTH),
conv_std_logic_vector(21886,AMPL_WIDTH),
conv_std_logic_vector(21888,AMPL_WIDTH),
conv_std_logic_vector(21891,AMPL_WIDTH),
conv_std_logic_vector(21893,AMPL_WIDTH),
conv_std_logic_vector(21895,AMPL_WIDTH),
conv_std_logic_vector(21898,AMPL_WIDTH),
conv_std_logic_vector(21900,AMPL_WIDTH),
conv_std_logic_vector(21902,AMPL_WIDTH),
conv_std_logic_vector(21905,AMPL_WIDTH),
conv_std_logic_vector(21907,AMPL_WIDTH),
conv_std_logic_vector(21909,AMPL_WIDTH),
conv_std_logic_vector(21912,AMPL_WIDTH),
conv_std_logic_vector(21914,AMPL_WIDTH),
conv_std_logic_vector(21916,AMPL_WIDTH),
conv_std_logic_vector(21919,AMPL_WIDTH),
conv_std_logic_vector(21921,AMPL_WIDTH),
conv_std_logic_vector(21923,AMPL_WIDTH),
conv_std_logic_vector(21926,AMPL_WIDTH),
conv_std_logic_vector(21928,AMPL_WIDTH),
conv_std_logic_vector(21930,AMPL_WIDTH),
conv_std_logic_vector(21933,AMPL_WIDTH),
conv_std_logic_vector(21935,AMPL_WIDTH),
conv_std_logic_vector(21937,AMPL_WIDTH),
conv_std_logic_vector(21940,AMPL_WIDTH),
conv_std_logic_vector(21942,AMPL_WIDTH),
conv_std_logic_vector(21944,AMPL_WIDTH),
conv_std_logic_vector(21947,AMPL_WIDTH),
conv_std_logic_vector(21949,AMPL_WIDTH),
conv_std_logic_vector(21951,AMPL_WIDTH),
conv_std_logic_vector(21954,AMPL_WIDTH),
conv_std_logic_vector(21956,AMPL_WIDTH),
conv_std_logic_vector(21958,AMPL_WIDTH),
conv_std_logic_vector(21961,AMPL_WIDTH),
conv_std_logic_vector(21963,AMPL_WIDTH),
conv_std_logic_vector(21965,AMPL_WIDTH),
conv_std_logic_vector(21968,AMPL_WIDTH),
conv_std_logic_vector(21970,AMPL_WIDTH),
conv_std_logic_vector(21972,AMPL_WIDTH),
conv_std_logic_vector(21975,AMPL_WIDTH),
conv_std_logic_vector(21977,AMPL_WIDTH),
conv_std_logic_vector(21979,AMPL_WIDTH),
conv_std_logic_vector(21982,AMPL_WIDTH),
conv_std_logic_vector(21984,AMPL_WIDTH),
conv_std_logic_vector(21986,AMPL_WIDTH),
conv_std_logic_vector(21989,AMPL_WIDTH),
conv_std_logic_vector(21991,AMPL_WIDTH),
conv_std_logic_vector(21993,AMPL_WIDTH),
conv_std_logic_vector(21996,AMPL_WIDTH),
conv_std_logic_vector(21998,AMPL_WIDTH),
conv_std_logic_vector(22000,AMPL_WIDTH),
conv_std_logic_vector(22003,AMPL_WIDTH),
conv_std_logic_vector(22005,AMPL_WIDTH),
conv_std_logic_vector(22007,AMPL_WIDTH),
conv_std_logic_vector(22010,AMPL_WIDTH),
conv_std_logic_vector(22012,AMPL_WIDTH),
conv_std_logic_vector(22014,AMPL_WIDTH),
conv_std_logic_vector(22017,AMPL_WIDTH),
conv_std_logic_vector(22019,AMPL_WIDTH),
conv_std_logic_vector(22021,AMPL_WIDTH),
conv_std_logic_vector(22024,AMPL_WIDTH),
conv_std_logic_vector(22026,AMPL_WIDTH),
conv_std_logic_vector(22028,AMPL_WIDTH),
conv_std_logic_vector(22031,AMPL_WIDTH),
conv_std_logic_vector(22033,AMPL_WIDTH),
conv_std_logic_vector(22035,AMPL_WIDTH),
conv_std_logic_vector(22038,AMPL_WIDTH),
conv_std_logic_vector(22040,AMPL_WIDTH),
conv_std_logic_vector(22042,AMPL_WIDTH),
conv_std_logic_vector(22045,AMPL_WIDTH),
conv_std_logic_vector(22047,AMPL_WIDTH),
conv_std_logic_vector(22049,AMPL_WIDTH),
conv_std_logic_vector(22051,AMPL_WIDTH),
conv_std_logic_vector(22054,AMPL_WIDTH),
conv_std_logic_vector(22056,AMPL_WIDTH),
conv_std_logic_vector(22058,AMPL_WIDTH),
conv_std_logic_vector(22061,AMPL_WIDTH),
conv_std_logic_vector(22063,AMPL_WIDTH),
conv_std_logic_vector(22065,AMPL_WIDTH),
conv_std_logic_vector(22068,AMPL_WIDTH),
conv_std_logic_vector(22070,AMPL_WIDTH),
conv_std_logic_vector(22072,AMPL_WIDTH),
conv_std_logic_vector(22075,AMPL_WIDTH),
conv_std_logic_vector(22077,AMPL_WIDTH),
conv_std_logic_vector(22079,AMPL_WIDTH),
conv_std_logic_vector(22082,AMPL_WIDTH),
conv_std_logic_vector(22084,AMPL_WIDTH),
conv_std_logic_vector(22086,AMPL_WIDTH),
conv_std_logic_vector(22089,AMPL_WIDTH),
conv_std_logic_vector(22091,AMPL_WIDTH),
conv_std_logic_vector(22093,AMPL_WIDTH),
conv_std_logic_vector(22096,AMPL_WIDTH),
conv_std_logic_vector(22098,AMPL_WIDTH),
conv_std_logic_vector(22100,AMPL_WIDTH),
conv_std_logic_vector(22103,AMPL_WIDTH),
conv_std_logic_vector(22105,AMPL_WIDTH),
conv_std_logic_vector(22107,AMPL_WIDTH),
conv_std_logic_vector(22110,AMPL_WIDTH),
conv_std_logic_vector(22112,AMPL_WIDTH),
conv_std_logic_vector(22114,AMPL_WIDTH),
conv_std_logic_vector(22116,AMPL_WIDTH),
conv_std_logic_vector(22119,AMPL_WIDTH),
conv_std_logic_vector(22121,AMPL_WIDTH),
conv_std_logic_vector(22123,AMPL_WIDTH),
conv_std_logic_vector(22126,AMPL_WIDTH),
conv_std_logic_vector(22128,AMPL_WIDTH),
conv_std_logic_vector(22130,AMPL_WIDTH),
conv_std_logic_vector(22133,AMPL_WIDTH),
conv_std_logic_vector(22135,AMPL_WIDTH),
conv_std_logic_vector(22137,AMPL_WIDTH),
conv_std_logic_vector(22140,AMPL_WIDTH),
conv_std_logic_vector(22142,AMPL_WIDTH),
conv_std_logic_vector(22144,AMPL_WIDTH),
conv_std_logic_vector(22147,AMPL_WIDTH),
conv_std_logic_vector(22149,AMPL_WIDTH),
conv_std_logic_vector(22151,AMPL_WIDTH),
conv_std_logic_vector(22154,AMPL_WIDTH),
conv_std_logic_vector(22156,AMPL_WIDTH),
conv_std_logic_vector(22158,AMPL_WIDTH),
conv_std_logic_vector(22160,AMPL_WIDTH),
conv_std_logic_vector(22163,AMPL_WIDTH),
conv_std_logic_vector(22165,AMPL_WIDTH),
conv_std_logic_vector(22167,AMPL_WIDTH),
conv_std_logic_vector(22170,AMPL_WIDTH),
conv_std_logic_vector(22172,AMPL_WIDTH),
conv_std_logic_vector(22174,AMPL_WIDTH),
conv_std_logic_vector(22177,AMPL_WIDTH),
conv_std_logic_vector(22179,AMPL_WIDTH),
conv_std_logic_vector(22181,AMPL_WIDTH),
conv_std_logic_vector(22184,AMPL_WIDTH),
conv_std_logic_vector(22186,AMPL_WIDTH),
conv_std_logic_vector(22188,AMPL_WIDTH),
conv_std_logic_vector(22191,AMPL_WIDTH),
conv_std_logic_vector(22193,AMPL_WIDTH),
conv_std_logic_vector(22195,AMPL_WIDTH),
conv_std_logic_vector(22197,AMPL_WIDTH),
conv_std_logic_vector(22200,AMPL_WIDTH),
conv_std_logic_vector(22202,AMPL_WIDTH),
conv_std_logic_vector(22204,AMPL_WIDTH),
conv_std_logic_vector(22207,AMPL_WIDTH),
conv_std_logic_vector(22209,AMPL_WIDTH),
conv_std_logic_vector(22211,AMPL_WIDTH),
conv_std_logic_vector(22214,AMPL_WIDTH),
conv_std_logic_vector(22216,AMPL_WIDTH),
conv_std_logic_vector(22218,AMPL_WIDTH),
conv_std_logic_vector(22221,AMPL_WIDTH),
conv_std_logic_vector(22223,AMPL_WIDTH),
conv_std_logic_vector(22225,AMPL_WIDTH),
conv_std_logic_vector(22227,AMPL_WIDTH),
conv_std_logic_vector(22230,AMPL_WIDTH),
conv_std_logic_vector(22232,AMPL_WIDTH),
conv_std_logic_vector(22234,AMPL_WIDTH),
conv_std_logic_vector(22237,AMPL_WIDTH),
conv_std_logic_vector(22239,AMPL_WIDTH),
conv_std_logic_vector(22241,AMPL_WIDTH),
conv_std_logic_vector(22244,AMPL_WIDTH),
conv_std_logic_vector(22246,AMPL_WIDTH),
conv_std_logic_vector(22248,AMPL_WIDTH),
conv_std_logic_vector(22251,AMPL_WIDTH),
conv_std_logic_vector(22253,AMPL_WIDTH),
conv_std_logic_vector(22255,AMPL_WIDTH),
conv_std_logic_vector(22257,AMPL_WIDTH),
conv_std_logic_vector(22260,AMPL_WIDTH),
conv_std_logic_vector(22262,AMPL_WIDTH),
conv_std_logic_vector(22264,AMPL_WIDTH),
conv_std_logic_vector(22267,AMPL_WIDTH),
conv_std_logic_vector(22269,AMPL_WIDTH),
conv_std_logic_vector(22271,AMPL_WIDTH),
conv_std_logic_vector(22274,AMPL_WIDTH),
conv_std_logic_vector(22276,AMPL_WIDTH),
conv_std_logic_vector(22278,AMPL_WIDTH),
conv_std_logic_vector(22281,AMPL_WIDTH),
conv_std_logic_vector(22283,AMPL_WIDTH),
conv_std_logic_vector(22285,AMPL_WIDTH),
conv_std_logic_vector(22287,AMPL_WIDTH),
conv_std_logic_vector(22290,AMPL_WIDTH),
conv_std_logic_vector(22292,AMPL_WIDTH),
conv_std_logic_vector(22294,AMPL_WIDTH),
conv_std_logic_vector(22297,AMPL_WIDTH),
conv_std_logic_vector(22299,AMPL_WIDTH),
conv_std_logic_vector(22301,AMPL_WIDTH),
conv_std_logic_vector(22304,AMPL_WIDTH),
conv_std_logic_vector(22306,AMPL_WIDTH),
conv_std_logic_vector(22308,AMPL_WIDTH),
conv_std_logic_vector(22310,AMPL_WIDTH),
conv_std_logic_vector(22313,AMPL_WIDTH),
conv_std_logic_vector(22315,AMPL_WIDTH),
conv_std_logic_vector(22317,AMPL_WIDTH),
conv_std_logic_vector(22320,AMPL_WIDTH),
conv_std_logic_vector(22322,AMPL_WIDTH),
conv_std_logic_vector(22324,AMPL_WIDTH),
conv_std_logic_vector(22327,AMPL_WIDTH),
conv_std_logic_vector(22329,AMPL_WIDTH),
conv_std_logic_vector(22331,AMPL_WIDTH),
conv_std_logic_vector(22333,AMPL_WIDTH),
conv_std_logic_vector(22336,AMPL_WIDTH),
conv_std_logic_vector(22338,AMPL_WIDTH),
conv_std_logic_vector(22340,AMPL_WIDTH),
conv_std_logic_vector(22343,AMPL_WIDTH),
conv_std_logic_vector(22345,AMPL_WIDTH),
conv_std_logic_vector(22347,AMPL_WIDTH),
conv_std_logic_vector(22350,AMPL_WIDTH),
conv_std_logic_vector(22352,AMPL_WIDTH),
conv_std_logic_vector(22354,AMPL_WIDTH),
conv_std_logic_vector(22356,AMPL_WIDTH),
conv_std_logic_vector(22359,AMPL_WIDTH),
conv_std_logic_vector(22361,AMPL_WIDTH),
conv_std_logic_vector(22363,AMPL_WIDTH),
conv_std_logic_vector(22366,AMPL_WIDTH),
conv_std_logic_vector(22368,AMPL_WIDTH),
conv_std_logic_vector(22370,AMPL_WIDTH),
conv_std_logic_vector(22373,AMPL_WIDTH),
conv_std_logic_vector(22375,AMPL_WIDTH),
conv_std_logic_vector(22377,AMPL_WIDTH),
conv_std_logic_vector(22379,AMPL_WIDTH),
conv_std_logic_vector(22382,AMPL_WIDTH),
conv_std_logic_vector(22384,AMPL_WIDTH),
conv_std_logic_vector(22386,AMPL_WIDTH),
conv_std_logic_vector(22389,AMPL_WIDTH),
conv_std_logic_vector(22391,AMPL_WIDTH),
conv_std_logic_vector(22393,AMPL_WIDTH),
conv_std_logic_vector(22395,AMPL_WIDTH),
conv_std_logic_vector(22398,AMPL_WIDTH),
conv_std_logic_vector(22400,AMPL_WIDTH),
conv_std_logic_vector(22402,AMPL_WIDTH),
conv_std_logic_vector(22405,AMPL_WIDTH),
conv_std_logic_vector(22407,AMPL_WIDTH),
conv_std_logic_vector(22409,AMPL_WIDTH),
conv_std_logic_vector(22411,AMPL_WIDTH),
conv_std_logic_vector(22414,AMPL_WIDTH),
conv_std_logic_vector(22416,AMPL_WIDTH),
conv_std_logic_vector(22418,AMPL_WIDTH),
conv_std_logic_vector(22421,AMPL_WIDTH),
conv_std_logic_vector(22423,AMPL_WIDTH),
conv_std_logic_vector(22425,AMPL_WIDTH),
conv_std_logic_vector(22428,AMPL_WIDTH),
conv_std_logic_vector(22430,AMPL_WIDTH),
conv_std_logic_vector(22432,AMPL_WIDTH),
conv_std_logic_vector(22434,AMPL_WIDTH),
conv_std_logic_vector(22437,AMPL_WIDTH),
conv_std_logic_vector(22439,AMPL_WIDTH),
conv_std_logic_vector(22441,AMPL_WIDTH),
conv_std_logic_vector(22444,AMPL_WIDTH),
conv_std_logic_vector(22446,AMPL_WIDTH),
conv_std_logic_vector(22448,AMPL_WIDTH),
conv_std_logic_vector(22450,AMPL_WIDTH),
conv_std_logic_vector(22453,AMPL_WIDTH),
conv_std_logic_vector(22455,AMPL_WIDTH),
conv_std_logic_vector(22457,AMPL_WIDTH),
conv_std_logic_vector(22460,AMPL_WIDTH),
conv_std_logic_vector(22462,AMPL_WIDTH),
conv_std_logic_vector(22464,AMPL_WIDTH),
conv_std_logic_vector(22466,AMPL_WIDTH),
conv_std_logic_vector(22469,AMPL_WIDTH),
conv_std_logic_vector(22471,AMPL_WIDTH),
conv_std_logic_vector(22473,AMPL_WIDTH),
conv_std_logic_vector(22476,AMPL_WIDTH),
conv_std_logic_vector(22478,AMPL_WIDTH),
conv_std_logic_vector(22480,AMPL_WIDTH),
conv_std_logic_vector(22482,AMPL_WIDTH),
conv_std_logic_vector(22485,AMPL_WIDTH),
conv_std_logic_vector(22487,AMPL_WIDTH),
conv_std_logic_vector(22489,AMPL_WIDTH),
conv_std_logic_vector(22492,AMPL_WIDTH),
conv_std_logic_vector(22494,AMPL_WIDTH),
conv_std_logic_vector(22496,AMPL_WIDTH),
conv_std_logic_vector(22498,AMPL_WIDTH),
conv_std_logic_vector(22501,AMPL_WIDTH),
conv_std_logic_vector(22503,AMPL_WIDTH),
conv_std_logic_vector(22505,AMPL_WIDTH),
conv_std_logic_vector(22508,AMPL_WIDTH),
conv_std_logic_vector(22510,AMPL_WIDTH),
conv_std_logic_vector(22512,AMPL_WIDTH),
conv_std_logic_vector(22514,AMPL_WIDTH),
conv_std_logic_vector(22517,AMPL_WIDTH),
conv_std_logic_vector(22519,AMPL_WIDTH),
conv_std_logic_vector(22521,AMPL_WIDTH),
conv_std_logic_vector(22524,AMPL_WIDTH),
conv_std_logic_vector(22526,AMPL_WIDTH),
conv_std_logic_vector(22528,AMPL_WIDTH),
conv_std_logic_vector(22530,AMPL_WIDTH),
conv_std_logic_vector(22533,AMPL_WIDTH),
conv_std_logic_vector(22535,AMPL_WIDTH),
conv_std_logic_vector(22537,AMPL_WIDTH),
conv_std_logic_vector(22540,AMPL_WIDTH),
conv_std_logic_vector(22542,AMPL_WIDTH),
conv_std_logic_vector(22544,AMPL_WIDTH),
conv_std_logic_vector(22546,AMPL_WIDTH),
conv_std_logic_vector(22549,AMPL_WIDTH),
conv_std_logic_vector(22551,AMPL_WIDTH),
conv_std_logic_vector(22553,AMPL_WIDTH),
conv_std_logic_vector(22555,AMPL_WIDTH),
conv_std_logic_vector(22558,AMPL_WIDTH),
conv_std_logic_vector(22560,AMPL_WIDTH),
conv_std_logic_vector(22562,AMPL_WIDTH),
conv_std_logic_vector(22565,AMPL_WIDTH),
conv_std_logic_vector(22567,AMPL_WIDTH),
conv_std_logic_vector(22569,AMPL_WIDTH),
conv_std_logic_vector(22571,AMPL_WIDTH),
conv_std_logic_vector(22574,AMPL_WIDTH),
conv_std_logic_vector(22576,AMPL_WIDTH),
conv_std_logic_vector(22578,AMPL_WIDTH),
conv_std_logic_vector(22581,AMPL_WIDTH),
conv_std_logic_vector(22583,AMPL_WIDTH),
conv_std_logic_vector(22585,AMPL_WIDTH),
conv_std_logic_vector(22587,AMPL_WIDTH),
conv_std_logic_vector(22590,AMPL_WIDTH),
conv_std_logic_vector(22592,AMPL_WIDTH),
conv_std_logic_vector(22594,AMPL_WIDTH),
conv_std_logic_vector(22596,AMPL_WIDTH),
conv_std_logic_vector(22599,AMPL_WIDTH),
conv_std_logic_vector(22601,AMPL_WIDTH),
conv_std_logic_vector(22603,AMPL_WIDTH),
conv_std_logic_vector(22606,AMPL_WIDTH),
conv_std_logic_vector(22608,AMPL_WIDTH),
conv_std_logic_vector(22610,AMPL_WIDTH),
conv_std_logic_vector(22612,AMPL_WIDTH),
conv_std_logic_vector(22615,AMPL_WIDTH),
conv_std_logic_vector(22617,AMPL_WIDTH),
conv_std_logic_vector(22619,AMPL_WIDTH),
conv_std_logic_vector(22621,AMPL_WIDTH),
conv_std_logic_vector(22624,AMPL_WIDTH),
conv_std_logic_vector(22626,AMPL_WIDTH),
conv_std_logic_vector(22628,AMPL_WIDTH),
conv_std_logic_vector(22631,AMPL_WIDTH),
conv_std_logic_vector(22633,AMPL_WIDTH),
conv_std_logic_vector(22635,AMPL_WIDTH),
conv_std_logic_vector(22637,AMPL_WIDTH),
conv_std_logic_vector(22640,AMPL_WIDTH),
conv_std_logic_vector(22642,AMPL_WIDTH),
conv_std_logic_vector(22644,AMPL_WIDTH),
conv_std_logic_vector(22646,AMPL_WIDTH),
conv_std_logic_vector(22649,AMPL_WIDTH),
conv_std_logic_vector(22651,AMPL_WIDTH),
conv_std_logic_vector(22653,AMPL_WIDTH),
conv_std_logic_vector(22656,AMPL_WIDTH),
conv_std_logic_vector(22658,AMPL_WIDTH),
conv_std_logic_vector(22660,AMPL_WIDTH),
conv_std_logic_vector(22662,AMPL_WIDTH),
conv_std_logic_vector(22665,AMPL_WIDTH),
conv_std_logic_vector(22667,AMPL_WIDTH),
conv_std_logic_vector(22669,AMPL_WIDTH),
conv_std_logic_vector(22671,AMPL_WIDTH),
conv_std_logic_vector(22674,AMPL_WIDTH),
conv_std_logic_vector(22676,AMPL_WIDTH),
conv_std_logic_vector(22678,AMPL_WIDTH),
conv_std_logic_vector(22680,AMPL_WIDTH),
conv_std_logic_vector(22683,AMPL_WIDTH),
conv_std_logic_vector(22685,AMPL_WIDTH),
conv_std_logic_vector(22687,AMPL_WIDTH),
conv_std_logic_vector(22690,AMPL_WIDTH),
conv_std_logic_vector(22692,AMPL_WIDTH),
conv_std_logic_vector(22694,AMPL_WIDTH),
conv_std_logic_vector(22696,AMPL_WIDTH),
conv_std_logic_vector(22699,AMPL_WIDTH),
conv_std_logic_vector(22701,AMPL_WIDTH),
conv_std_logic_vector(22703,AMPL_WIDTH),
conv_std_logic_vector(22705,AMPL_WIDTH),
conv_std_logic_vector(22708,AMPL_WIDTH),
conv_std_logic_vector(22710,AMPL_WIDTH),
conv_std_logic_vector(22712,AMPL_WIDTH),
conv_std_logic_vector(22714,AMPL_WIDTH),
conv_std_logic_vector(22717,AMPL_WIDTH),
conv_std_logic_vector(22719,AMPL_WIDTH),
conv_std_logic_vector(22721,AMPL_WIDTH),
conv_std_logic_vector(22724,AMPL_WIDTH),
conv_std_logic_vector(22726,AMPL_WIDTH),
conv_std_logic_vector(22728,AMPL_WIDTH),
conv_std_logic_vector(22730,AMPL_WIDTH),
conv_std_logic_vector(22733,AMPL_WIDTH),
conv_std_logic_vector(22735,AMPL_WIDTH),
conv_std_logic_vector(22737,AMPL_WIDTH),
conv_std_logic_vector(22739,AMPL_WIDTH),
conv_std_logic_vector(22742,AMPL_WIDTH),
conv_std_logic_vector(22744,AMPL_WIDTH),
conv_std_logic_vector(22746,AMPL_WIDTH),
conv_std_logic_vector(22748,AMPL_WIDTH),
conv_std_logic_vector(22751,AMPL_WIDTH),
conv_std_logic_vector(22753,AMPL_WIDTH),
conv_std_logic_vector(22755,AMPL_WIDTH),
conv_std_logic_vector(22757,AMPL_WIDTH),
conv_std_logic_vector(22760,AMPL_WIDTH),
conv_std_logic_vector(22762,AMPL_WIDTH),
conv_std_logic_vector(22764,AMPL_WIDTH),
conv_std_logic_vector(22766,AMPL_WIDTH),
conv_std_logic_vector(22769,AMPL_WIDTH),
conv_std_logic_vector(22771,AMPL_WIDTH),
conv_std_logic_vector(22773,AMPL_WIDTH),
conv_std_logic_vector(22776,AMPL_WIDTH),
conv_std_logic_vector(22778,AMPL_WIDTH),
conv_std_logic_vector(22780,AMPL_WIDTH),
conv_std_logic_vector(22782,AMPL_WIDTH),
conv_std_logic_vector(22785,AMPL_WIDTH),
conv_std_logic_vector(22787,AMPL_WIDTH),
conv_std_logic_vector(22789,AMPL_WIDTH),
conv_std_logic_vector(22791,AMPL_WIDTH),
conv_std_logic_vector(22794,AMPL_WIDTH),
conv_std_logic_vector(22796,AMPL_WIDTH),
conv_std_logic_vector(22798,AMPL_WIDTH),
conv_std_logic_vector(22800,AMPL_WIDTH),
conv_std_logic_vector(22803,AMPL_WIDTH),
conv_std_logic_vector(22805,AMPL_WIDTH),
conv_std_logic_vector(22807,AMPL_WIDTH),
conv_std_logic_vector(22809,AMPL_WIDTH),
conv_std_logic_vector(22812,AMPL_WIDTH),
conv_std_logic_vector(22814,AMPL_WIDTH),
conv_std_logic_vector(22816,AMPL_WIDTH),
conv_std_logic_vector(22818,AMPL_WIDTH),
conv_std_logic_vector(22821,AMPL_WIDTH),
conv_std_logic_vector(22823,AMPL_WIDTH),
conv_std_logic_vector(22825,AMPL_WIDTH),
conv_std_logic_vector(22827,AMPL_WIDTH),
conv_std_logic_vector(22830,AMPL_WIDTH),
conv_std_logic_vector(22832,AMPL_WIDTH),
conv_std_logic_vector(22834,AMPL_WIDTH),
conv_std_logic_vector(22836,AMPL_WIDTH),
conv_std_logic_vector(22839,AMPL_WIDTH),
conv_std_logic_vector(22841,AMPL_WIDTH),
conv_std_logic_vector(22843,AMPL_WIDTH),
conv_std_logic_vector(22845,AMPL_WIDTH),
conv_std_logic_vector(22848,AMPL_WIDTH),
conv_std_logic_vector(22850,AMPL_WIDTH),
conv_std_logic_vector(22852,AMPL_WIDTH),
conv_std_logic_vector(22854,AMPL_WIDTH),
conv_std_logic_vector(22857,AMPL_WIDTH),
conv_std_logic_vector(22859,AMPL_WIDTH),
conv_std_logic_vector(22861,AMPL_WIDTH),
conv_std_logic_vector(22863,AMPL_WIDTH),
conv_std_logic_vector(22866,AMPL_WIDTH),
conv_std_logic_vector(22868,AMPL_WIDTH),
conv_std_logic_vector(22870,AMPL_WIDTH),
conv_std_logic_vector(22872,AMPL_WIDTH),
conv_std_logic_vector(22875,AMPL_WIDTH),
conv_std_logic_vector(22877,AMPL_WIDTH),
conv_std_logic_vector(22879,AMPL_WIDTH),
conv_std_logic_vector(22881,AMPL_WIDTH),
conv_std_logic_vector(22884,AMPL_WIDTH),
conv_std_logic_vector(22886,AMPL_WIDTH),
conv_std_logic_vector(22888,AMPL_WIDTH),
conv_std_logic_vector(22890,AMPL_WIDTH),
conv_std_logic_vector(22893,AMPL_WIDTH),
conv_std_logic_vector(22895,AMPL_WIDTH),
conv_std_logic_vector(22897,AMPL_WIDTH),
conv_std_logic_vector(22899,AMPL_WIDTH),
conv_std_logic_vector(22902,AMPL_WIDTH),
conv_std_logic_vector(22904,AMPL_WIDTH),
conv_std_logic_vector(22906,AMPL_WIDTH),
conv_std_logic_vector(22908,AMPL_WIDTH),
conv_std_logic_vector(22911,AMPL_WIDTH),
conv_std_logic_vector(22913,AMPL_WIDTH),
conv_std_logic_vector(22915,AMPL_WIDTH),
conv_std_logic_vector(22917,AMPL_WIDTH),
conv_std_logic_vector(22920,AMPL_WIDTH),
conv_std_logic_vector(22922,AMPL_WIDTH),
conv_std_logic_vector(22924,AMPL_WIDTH),
conv_std_logic_vector(22926,AMPL_WIDTH),
conv_std_logic_vector(22929,AMPL_WIDTH),
conv_std_logic_vector(22931,AMPL_WIDTH),
conv_std_logic_vector(22933,AMPL_WIDTH),
conv_std_logic_vector(22935,AMPL_WIDTH),
conv_std_logic_vector(22938,AMPL_WIDTH),
conv_std_logic_vector(22940,AMPL_WIDTH),
conv_std_logic_vector(22942,AMPL_WIDTH),
conv_std_logic_vector(22944,AMPL_WIDTH),
conv_std_logic_vector(22947,AMPL_WIDTH),
conv_std_logic_vector(22949,AMPL_WIDTH),
conv_std_logic_vector(22951,AMPL_WIDTH),
conv_std_logic_vector(22953,AMPL_WIDTH),
conv_std_logic_vector(22956,AMPL_WIDTH),
conv_std_logic_vector(22958,AMPL_WIDTH),
conv_std_logic_vector(22960,AMPL_WIDTH),
conv_std_logic_vector(22962,AMPL_WIDTH),
conv_std_logic_vector(22965,AMPL_WIDTH),
conv_std_logic_vector(22967,AMPL_WIDTH),
conv_std_logic_vector(22969,AMPL_WIDTH),
conv_std_logic_vector(22971,AMPL_WIDTH),
conv_std_logic_vector(22973,AMPL_WIDTH),
conv_std_logic_vector(22976,AMPL_WIDTH),
conv_std_logic_vector(22978,AMPL_WIDTH),
conv_std_logic_vector(22980,AMPL_WIDTH),
conv_std_logic_vector(22982,AMPL_WIDTH),
conv_std_logic_vector(22985,AMPL_WIDTH),
conv_std_logic_vector(22987,AMPL_WIDTH),
conv_std_logic_vector(22989,AMPL_WIDTH),
conv_std_logic_vector(22991,AMPL_WIDTH),
conv_std_logic_vector(22994,AMPL_WIDTH),
conv_std_logic_vector(22996,AMPL_WIDTH),
conv_std_logic_vector(22998,AMPL_WIDTH),
conv_std_logic_vector(23000,AMPL_WIDTH),
conv_std_logic_vector(23003,AMPL_WIDTH),
conv_std_logic_vector(23005,AMPL_WIDTH),
conv_std_logic_vector(23007,AMPL_WIDTH),
conv_std_logic_vector(23009,AMPL_WIDTH),
conv_std_logic_vector(23012,AMPL_WIDTH),
conv_std_logic_vector(23014,AMPL_WIDTH),
conv_std_logic_vector(23016,AMPL_WIDTH),
conv_std_logic_vector(23018,AMPL_WIDTH),
conv_std_logic_vector(23020,AMPL_WIDTH),
conv_std_logic_vector(23023,AMPL_WIDTH),
conv_std_logic_vector(23025,AMPL_WIDTH),
conv_std_logic_vector(23027,AMPL_WIDTH),
conv_std_logic_vector(23029,AMPL_WIDTH),
conv_std_logic_vector(23032,AMPL_WIDTH),
conv_std_logic_vector(23034,AMPL_WIDTH),
conv_std_logic_vector(23036,AMPL_WIDTH),
conv_std_logic_vector(23038,AMPL_WIDTH),
conv_std_logic_vector(23041,AMPL_WIDTH),
conv_std_logic_vector(23043,AMPL_WIDTH),
conv_std_logic_vector(23045,AMPL_WIDTH),
conv_std_logic_vector(23047,AMPL_WIDTH),
conv_std_logic_vector(23050,AMPL_WIDTH),
conv_std_logic_vector(23052,AMPL_WIDTH),
conv_std_logic_vector(23054,AMPL_WIDTH),
conv_std_logic_vector(23056,AMPL_WIDTH),
conv_std_logic_vector(23058,AMPL_WIDTH),
conv_std_logic_vector(23061,AMPL_WIDTH),
conv_std_logic_vector(23063,AMPL_WIDTH),
conv_std_logic_vector(23065,AMPL_WIDTH),
conv_std_logic_vector(23067,AMPL_WIDTH),
conv_std_logic_vector(23070,AMPL_WIDTH),
conv_std_logic_vector(23072,AMPL_WIDTH),
conv_std_logic_vector(23074,AMPL_WIDTH),
conv_std_logic_vector(23076,AMPL_WIDTH),
conv_std_logic_vector(23079,AMPL_WIDTH),
conv_std_logic_vector(23081,AMPL_WIDTH),
conv_std_logic_vector(23083,AMPL_WIDTH),
conv_std_logic_vector(23085,AMPL_WIDTH),
conv_std_logic_vector(23087,AMPL_WIDTH),
conv_std_logic_vector(23090,AMPL_WIDTH),
conv_std_logic_vector(23092,AMPL_WIDTH),
conv_std_logic_vector(23094,AMPL_WIDTH),
conv_std_logic_vector(23096,AMPL_WIDTH),
conv_std_logic_vector(23099,AMPL_WIDTH),
conv_std_logic_vector(23101,AMPL_WIDTH),
conv_std_logic_vector(23103,AMPL_WIDTH),
conv_std_logic_vector(23105,AMPL_WIDTH),
conv_std_logic_vector(23107,AMPL_WIDTH),
conv_std_logic_vector(23110,AMPL_WIDTH),
conv_std_logic_vector(23112,AMPL_WIDTH),
conv_std_logic_vector(23114,AMPL_WIDTH),
conv_std_logic_vector(23116,AMPL_WIDTH),
conv_std_logic_vector(23119,AMPL_WIDTH),
conv_std_logic_vector(23121,AMPL_WIDTH),
conv_std_logic_vector(23123,AMPL_WIDTH),
conv_std_logic_vector(23125,AMPL_WIDTH),
conv_std_logic_vector(23128,AMPL_WIDTH),
conv_std_logic_vector(23130,AMPL_WIDTH),
conv_std_logic_vector(23132,AMPL_WIDTH),
conv_std_logic_vector(23134,AMPL_WIDTH),
conv_std_logic_vector(23136,AMPL_WIDTH),
conv_std_logic_vector(23139,AMPL_WIDTH),
conv_std_logic_vector(23141,AMPL_WIDTH),
conv_std_logic_vector(23143,AMPL_WIDTH),
conv_std_logic_vector(23145,AMPL_WIDTH),
conv_std_logic_vector(23148,AMPL_WIDTH),
conv_std_logic_vector(23150,AMPL_WIDTH),
conv_std_logic_vector(23152,AMPL_WIDTH),
conv_std_logic_vector(23154,AMPL_WIDTH),
conv_std_logic_vector(23156,AMPL_WIDTH),
conv_std_logic_vector(23159,AMPL_WIDTH),
conv_std_logic_vector(23161,AMPL_WIDTH),
conv_std_logic_vector(23163,AMPL_WIDTH),
conv_std_logic_vector(23165,AMPL_WIDTH),
conv_std_logic_vector(23168,AMPL_WIDTH),
conv_std_logic_vector(23170,AMPL_WIDTH),
conv_std_logic_vector(23172,AMPL_WIDTH),
conv_std_logic_vector(23174,AMPL_WIDTH),
conv_std_logic_vector(23176,AMPL_WIDTH),
conv_std_logic_vector(23179,AMPL_WIDTH),
conv_std_logic_vector(23181,AMPL_WIDTH),
conv_std_logic_vector(23183,AMPL_WIDTH),
conv_std_logic_vector(23185,AMPL_WIDTH),
conv_std_logic_vector(23188,AMPL_WIDTH),
conv_std_logic_vector(23190,AMPL_WIDTH),
conv_std_logic_vector(23192,AMPL_WIDTH),
conv_std_logic_vector(23194,AMPL_WIDTH),
conv_std_logic_vector(23196,AMPL_WIDTH),
conv_std_logic_vector(23199,AMPL_WIDTH),
conv_std_logic_vector(23201,AMPL_WIDTH),
conv_std_logic_vector(23203,AMPL_WIDTH),
conv_std_logic_vector(23205,AMPL_WIDTH),
conv_std_logic_vector(23208,AMPL_WIDTH),
conv_std_logic_vector(23210,AMPL_WIDTH),
conv_std_logic_vector(23212,AMPL_WIDTH),
conv_std_logic_vector(23214,AMPL_WIDTH),
conv_std_logic_vector(23216,AMPL_WIDTH),
conv_std_logic_vector(23219,AMPL_WIDTH),
conv_std_logic_vector(23221,AMPL_WIDTH),
conv_std_logic_vector(23223,AMPL_WIDTH),
conv_std_logic_vector(23225,AMPL_WIDTH),
conv_std_logic_vector(23227,AMPL_WIDTH),
conv_std_logic_vector(23230,AMPL_WIDTH),
conv_std_logic_vector(23232,AMPL_WIDTH),
conv_std_logic_vector(23234,AMPL_WIDTH),
conv_std_logic_vector(23236,AMPL_WIDTH),
conv_std_logic_vector(23239,AMPL_WIDTH),
conv_std_logic_vector(23241,AMPL_WIDTH),
conv_std_logic_vector(23243,AMPL_WIDTH),
conv_std_logic_vector(23245,AMPL_WIDTH),
conv_std_logic_vector(23247,AMPL_WIDTH),
conv_std_logic_vector(23250,AMPL_WIDTH),
conv_std_logic_vector(23252,AMPL_WIDTH),
conv_std_logic_vector(23254,AMPL_WIDTH),
conv_std_logic_vector(23256,AMPL_WIDTH),
conv_std_logic_vector(23258,AMPL_WIDTH),
conv_std_logic_vector(23261,AMPL_WIDTH),
conv_std_logic_vector(23263,AMPL_WIDTH),
conv_std_logic_vector(23265,AMPL_WIDTH),
conv_std_logic_vector(23267,AMPL_WIDTH),
conv_std_logic_vector(23270,AMPL_WIDTH),
conv_std_logic_vector(23272,AMPL_WIDTH),
conv_std_logic_vector(23274,AMPL_WIDTH),
conv_std_logic_vector(23276,AMPL_WIDTH),
conv_std_logic_vector(23278,AMPL_WIDTH),
conv_std_logic_vector(23281,AMPL_WIDTH),
conv_std_logic_vector(23283,AMPL_WIDTH),
conv_std_logic_vector(23285,AMPL_WIDTH),
conv_std_logic_vector(23287,AMPL_WIDTH),
conv_std_logic_vector(23289,AMPL_WIDTH),
conv_std_logic_vector(23292,AMPL_WIDTH),
conv_std_logic_vector(23294,AMPL_WIDTH),
conv_std_logic_vector(23296,AMPL_WIDTH),
conv_std_logic_vector(23298,AMPL_WIDTH),
conv_std_logic_vector(23300,AMPL_WIDTH),
conv_std_logic_vector(23303,AMPL_WIDTH),
conv_std_logic_vector(23305,AMPL_WIDTH),
conv_std_logic_vector(23307,AMPL_WIDTH),
conv_std_logic_vector(23309,AMPL_WIDTH),
conv_std_logic_vector(23311,AMPL_WIDTH),
conv_std_logic_vector(23314,AMPL_WIDTH),
conv_std_logic_vector(23316,AMPL_WIDTH),
conv_std_logic_vector(23318,AMPL_WIDTH),
conv_std_logic_vector(23320,AMPL_WIDTH),
conv_std_logic_vector(23323,AMPL_WIDTH),
conv_std_logic_vector(23325,AMPL_WIDTH),
conv_std_logic_vector(23327,AMPL_WIDTH),
conv_std_logic_vector(23329,AMPL_WIDTH),
conv_std_logic_vector(23331,AMPL_WIDTH),
conv_std_logic_vector(23334,AMPL_WIDTH),
conv_std_logic_vector(23336,AMPL_WIDTH),
conv_std_logic_vector(23338,AMPL_WIDTH),
conv_std_logic_vector(23340,AMPL_WIDTH),
conv_std_logic_vector(23342,AMPL_WIDTH),
conv_std_logic_vector(23345,AMPL_WIDTH),
conv_std_logic_vector(23347,AMPL_WIDTH),
conv_std_logic_vector(23349,AMPL_WIDTH),
conv_std_logic_vector(23351,AMPL_WIDTH),
conv_std_logic_vector(23353,AMPL_WIDTH),
conv_std_logic_vector(23356,AMPL_WIDTH),
conv_std_logic_vector(23358,AMPL_WIDTH),
conv_std_logic_vector(23360,AMPL_WIDTH),
conv_std_logic_vector(23362,AMPL_WIDTH),
conv_std_logic_vector(23364,AMPL_WIDTH),
conv_std_logic_vector(23367,AMPL_WIDTH),
conv_std_logic_vector(23369,AMPL_WIDTH),
conv_std_logic_vector(23371,AMPL_WIDTH),
conv_std_logic_vector(23373,AMPL_WIDTH),
conv_std_logic_vector(23375,AMPL_WIDTH),
conv_std_logic_vector(23378,AMPL_WIDTH),
conv_std_logic_vector(23380,AMPL_WIDTH),
conv_std_logic_vector(23382,AMPL_WIDTH),
conv_std_logic_vector(23384,AMPL_WIDTH),
conv_std_logic_vector(23386,AMPL_WIDTH),
conv_std_logic_vector(23389,AMPL_WIDTH),
conv_std_logic_vector(23391,AMPL_WIDTH),
conv_std_logic_vector(23393,AMPL_WIDTH),
conv_std_logic_vector(23395,AMPL_WIDTH),
conv_std_logic_vector(23397,AMPL_WIDTH),
conv_std_logic_vector(23400,AMPL_WIDTH),
conv_std_logic_vector(23402,AMPL_WIDTH),
conv_std_logic_vector(23404,AMPL_WIDTH),
conv_std_logic_vector(23406,AMPL_WIDTH),
conv_std_logic_vector(23408,AMPL_WIDTH),
conv_std_logic_vector(23411,AMPL_WIDTH),
conv_std_logic_vector(23413,AMPL_WIDTH),
conv_std_logic_vector(23415,AMPL_WIDTH),
conv_std_logic_vector(23417,AMPL_WIDTH),
conv_std_logic_vector(23419,AMPL_WIDTH),
conv_std_logic_vector(23422,AMPL_WIDTH),
conv_std_logic_vector(23424,AMPL_WIDTH),
conv_std_logic_vector(23426,AMPL_WIDTH),
conv_std_logic_vector(23428,AMPL_WIDTH),
conv_std_logic_vector(23430,AMPL_WIDTH),
conv_std_logic_vector(23433,AMPL_WIDTH),
conv_std_logic_vector(23435,AMPL_WIDTH),
conv_std_logic_vector(23437,AMPL_WIDTH),
conv_std_logic_vector(23439,AMPL_WIDTH),
conv_std_logic_vector(23441,AMPL_WIDTH),
conv_std_logic_vector(23444,AMPL_WIDTH),
conv_std_logic_vector(23446,AMPL_WIDTH),
conv_std_logic_vector(23448,AMPL_WIDTH),
conv_std_logic_vector(23450,AMPL_WIDTH),
conv_std_logic_vector(23452,AMPL_WIDTH),
conv_std_logic_vector(23455,AMPL_WIDTH),
conv_std_logic_vector(23457,AMPL_WIDTH),
conv_std_logic_vector(23459,AMPL_WIDTH),
conv_std_logic_vector(23461,AMPL_WIDTH),
conv_std_logic_vector(23463,AMPL_WIDTH),
conv_std_logic_vector(23466,AMPL_WIDTH),
conv_std_logic_vector(23468,AMPL_WIDTH),
conv_std_logic_vector(23470,AMPL_WIDTH),
conv_std_logic_vector(23472,AMPL_WIDTH),
conv_std_logic_vector(23474,AMPL_WIDTH),
conv_std_logic_vector(23476,AMPL_WIDTH),
conv_std_logic_vector(23479,AMPL_WIDTH),
conv_std_logic_vector(23481,AMPL_WIDTH),
conv_std_logic_vector(23483,AMPL_WIDTH),
conv_std_logic_vector(23485,AMPL_WIDTH),
conv_std_logic_vector(23487,AMPL_WIDTH),
conv_std_logic_vector(23490,AMPL_WIDTH),
conv_std_logic_vector(23492,AMPL_WIDTH),
conv_std_logic_vector(23494,AMPL_WIDTH),
conv_std_logic_vector(23496,AMPL_WIDTH),
conv_std_logic_vector(23498,AMPL_WIDTH),
conv_std_logic_vector(23501,AMPL_WIDTH),
conv_std_logic_vector(23503,AMPL_WIDTH),
conv_std_logic_vector(23505,AMPL_WIDTH),
conv_std_logic_vector(23507,AMPL_WIDTH),
conv_std_logic_vector(23509,AMPL_WIDTH),
conv_std_logic_vector(23512,AMPL_WIDTH),
conv_std_logic_vector(23514,AMPL_WIDTH),
conv_std_logic_vector(23516,AMPL_WIDTH),
conv_std_logic_vector(23518,AMPL_WIDTH),
conv_std_logic_vector(23520,AMPL_WIDTH),
conv_std_logic_vector(23522,AMPL_WIDTH),
conv_std_logic_vector(23525,AMPL_WIDTH),
conv_std_logic_vector(23527,AMPL_WIDTH),
conv_std_logic_vector(23529,AMPL_WIDTH),
conv_std_logic_vector(23531,AMPL_WIDTH),
conv_std_logic_vector(23533,AMPL_WIDTH),
conv_std_logic_vector(23536,AMPL_WIDTH),
conv_std_logic_vector(23538,AMPL_WIDTH),
conv_std_logic_vector(23540,AMPL_WIDTH),
conv_std_logic_vector(23542,AMPL_WIDTH),
conv_std_logic_vector(23544,AMPL_WIDTH),
conv_std_logic_vector(23546,AMPL_WIDTH),
conv_std_logic_vector(23549,AMPL_WIDTH),
conv_std_logic_vector(23551,AMPL_WIDTH),
conv_std_logic_vector(23553,AMPL_WIDTH),
conv_std_logic_vector(23555,AMPL_WIDTH),
conv_std_logic_vector(23557,AMPL_WIDTH),
conv_std_logic_vector(23560,AMPL_WIDTH),
conv_std_logic_vector(23562,AMPL_WIDTH),
conv_std_logic_vector(23564,AMPL_WIDTH),
conv_std_logic_vector(23566,AMPL_WIDTH),
conv_std_logic_vector(23568,AMPL_WIDTH),
conv_std_logic_vector(23571,AMPL_WIDTH),
conv_std_logic_vector(23573,AMPL_WIDTH),
conv_std_logic_vector(23575,AMPL_WIDTH),
conv_std_logic_vector(23577,AMPL_WIDTH),
conv_std_logic_vector(23579,AMPL_WIDTH),
conv_std_logic_vector(23581,AMPL_WIDTH),
conv_std_logic_vector(23584,AMPL_WIDTH),
conv_std_logic_vector(23586,AMPL_WIDTH),
conv_std_logic_vector(23588,AMPL_WIDTH),
conv_std_logic_vector(23590,AMPL_WIDTH),
conv_std_logic_vector(23592,AMPL_WIDTH),
conv_std_logic_vector(23595,AMPL_WIDTH),
conv_std_logic_vector(23597,AMPL_WIDTH),
conv_std_logic_vector(23599,AMPL_WIDTH),
conv_std_logic_vector(23601,AMPL_WIDTH),
conv_std_logic_vector(23603,AMPL_WIDTH),
conv_std_logic_vector(23605,AMPL_WIDTH),
conv_std_logic_vector(23608,AMPL_WIDTH),
conv_std_logic_vector(23610,AMPL_WIDTH),
conv_std_logic_vector(23612,AMPL_WIDTH),
conv_std_logic_vector(23614,AMPL_WIDTH),
conv_std_logic_vector(23616,AMPL_WIDTH),
conv_std_logic_vector(23618,AMPL_WIDTH),
conv_std_logic_vector(23621,AMPL_WIDTH),
conv_std_logic_vector(23623,AMPL_WIDTH),
conv_std_logic_vector(23625,AMPL_WIDTH),
conv_std_logic_vector(23627,AMPL_WIDTH),
conv_std_logic_vector(23629,AMPL_WIDTH),
conv_std_logic_vector(23632,AMPL_WIDTH),
conv_std_logic_vector(23634,AMPL_WIDTH),
conv_std_logic_vector(23636,AMPL_WIDTH),
conv_std_logic_vector(23638,AMPL_WIDTH),
conv_std_logic_vector(23640,AMPL_WIDTH),
conv_std_logic_vector(23642,AMPL_WIDTH),
conv_std_logic_vector(23645,AMPL_WIDTH),
conv_std_logic_vector(23647,AMPL_WIDTH),
conv_std_logic_vector(23649,AMPL_WIDTH),
conv_std_logic_vector(23651,AMPL_WIDTH),
conv_std_logic_vector(23653,AMPL_WIDTH),
conv_std_logic_vector(23655,AMPL_WIDTH),
conv_std_logic_vector(23658,AMPL_WIDTH),
conv_std_logic_vector(23660,AMPL_WIDTH),
conv_std_logic_vector(23662,AMPL_WIDTH),
conv_std_logic_vector(23664,AMPL_WIDTH),
conv_std_logic_vector(23666,AMPL_WIDTH),
conv_std_logic_vector(23668,AMPL_WIDTH),
conv_std_logic_vector(23671,AMPL_WIDTH),
conv_std_logic_vector(23673,AMPL_WIDTH),
conv_std_logic_vector(23675,AMPL_WIDTH),
conv_std_logic_vector(23677,AMPL_WIDTH),
conv_std_logic_vector(23679,AMPL_WIDTH),
conv_std_logic_vector(23682,AMPL_WIDTH),
conv_std_logic_vector(23684,AMPL_WIDTH),
conv_std_logic_vector(23686,AMPL_WIDTH),
conv_std_logic_vector(23688,AMPL_WIDTH),
conv_std_logic_vector(23690,AMPL_WIDTH),
conv_std_logic_vector(23692,AMPL_WIDTH),
conv_std_logic_vector(23695,AMPL_WIDTH),
conv_std_logic_vector(23697,AMPL_WIDTH),
conv_std_logic_vector(23699,AMPL_WIDTH),
conv_std_logic_vector(23701,AMPL_WIDTH),
conv_std_logic_vector(23703,AMPL_WIDTH),
conv_std_logic_vector(23705,AMPL_WIDTH),
conv_std_logic_vector(23708,AMPL_WIDTH),
conv_std_logic_vector(23710,AMPL_WIDTH),
conv_std_logic_vector(23712,AMPL_WIDTH),
conv_std_logic_vector(23714,AMPL_WIDTH),
conv_std_logic_vector(23716,AMPL_WIDTH),
conv_std_logic_vector(23718,AMPL_WIDTH),
conv_std_logic_vector(23721,AMPL_WIDTH),
conv_std_logic_vector(23723,AMPL_WIDTH),
conv_std_logic_vector(23725,AMPL_WIDTH),
conv_std_logic_vector(23727,AMPL_WIDTH),
conv_std_logic_vector(23729,AMPL_WIDTH),
conv_std_logic_vector(23731,AMPL_WIDTH),
conv_std_logic_vector(23734,AMPL_WIDTH),
conv_std_logic_vector(23736,AMPL_WIDTH),
conv_std_logic_vector(23738,AMPL_WIDTH),
conv_std_logic_vector(23740,AMPL_WIDTH),
conv_std_logic_vector(23742,AMPL_WIDTH),
conv_std_logic_vector(23744,AMPL_WIDTH),
conv_std_logic_vector(23747,AMPL_WIDTH),
conv_std_logic_vector(23749,AMPL_WIDTH),
conv_std_logic_vector(23751,AMPL_WIDTH),
conv_std_logic_vector(23753,AMPL_WIDTH),
conv_std_logic_vector(23755,AMPL_WIDTH),
conv_std_logic_vector(23757,AMPL_WIDTH),
conv_std_logic_vector(23760,AMPL_WIDTH),
conv_std_logic_vector(23762,AMPL_WIDTH),
conv_std_logic_vector(23764,AMPL_WIDTH),
conv_std_logic_vector(23766,AMPL_WIDTH),
conv_std_logic_vector(23768,AMPL_WIDTH),
conv_std_logic_vector(23770,AMPL_WIDTH),
conv_std_logic_vector(23773,AMPL_WIDTH),
conv_std_logic_vector(23775,AMPL_WIDTH),
conv_std_logic_vector(23777,AMPL_WIDTH),
conv_std_logic_vector(23779,AMPL_WIDTH),
conv_std_logic_vector(23781,AMPL_WIDTH),
conv_std_logic_vector(23783,AMPL_WIDTH),
conv_std_logic_vector(23785,AMPL_WIDTH),
conv_std_logic_vector(23788,AMPL_WIDTH),
conv_std_logic_vector(23790,AMPL_WIDTH),
conv_std_logic_vector(23792,AMPL_WIDTH),
conv_std_logic_vector(23794,AMPL_WIDTH),
conv_std_logic_vector(23796,AMPL_WIDTH),
conv_std_logic_vector(23798,AMPL_WIDTH),
conv_std_logic_vector(23801,AMPL_WIDTH),
conv_std_logic_vector(23803,AMPL_WIDTH),
conv_std_logic_vector(23805,AMPL_WIDTH),
conv_std_logic_vector(23807,AMPL_WIDTH),
conv_std_logic_vector(23809,AMPL_WIDTH),
conv_std_logic_vector(23811,AMPL_WIDTH),
conv_std_logic_vector(23814,AMPL_WIDTH),
conv_std_logic_vector(23816,AMPL_WIDTH),
conv_std_logic_vector(23818,AMPL_WIDTH),
conv_std_logic_vector(23820,AMPL_WIDTH),
conv_std_logic_vector(23822,AMPL_WIDTH),
conv_std_logic_vector(23824,AMPL_WIDTH),
conv_std_logic_vector(23827,AMPL_WIDTH),
conv_std_logic_vector(23829,AMPL_WIDTH),
conv_std_logic_vector(23831,AMPL_WIDTH),
conv_std_logic_vector(23833,AMPL_WIDTH),
conv_std_logic_vector(23835,AMPL_WIDTH),
conv_std_logic_vector(23837,AMPL_WIDTH),
conv_std_logic_vector(23839,AMPL_WIDTH),
conv_std_logic_vector(23842,AMPL_WIDTH),
conv_std_logic_vector(23844,AMPL_WIDTH),
conv_std_logic_vector(23846,AMPL_WIDTH),
conv_std_logic_vector(23848,AMPL_WIDTH),
conv_std_logic_vector(23850,AMPL_WIDTH),
conv_std_logic_vector(23852,AMPL_WIDTH),
conv_std_logic_vector(23855,AMPL_WIDTH),
conv_std_logic_vector(23857,AMPL_WIDTH),
conv_std_logic_vector(23859,AMPL_WIDTH),
conv_std_logic_vector(23861,AMPL_WIDTH),
conv_std_logic_vector(23863,AMPL_WIDTH),
conv_std_logic_vector(23865,AMPL_WIDTH),
conv_std_logic_vector(23867,AMPL_WIDTH),
conv_std_logic_vector(23870,AMPL_WIDTH),
conv_std_logic_vector(23872,AMPL_WIDTH),
conv_std_logic_vector(23874,AMPL_WIDTH),
conv_std_logic_vector(23876,AMPL_WIDTH),
conv_std_logic_vector(23878,AMPL_WIDTH),
conv_std_logic_vector(23880,AMPL_WIDTH),
conv_std_logic_vector(23883,AMPL_WIDTH),
conv_std_logic_vector(23885,AMPL_WIDTH),
conv_std_logic_vector(23887,AMPL_WIDTH),
conv_std_logic_vector(23889,AMPL_WIDTH),
conv_std_logic_vector(23891,AMPL_WIDTH),
conv_std_logic_vector(23893,AMPL_WIDTH),
conv_std_logic_vector(23895,AMPL_WIDTH),
conv_std_logic_vector(23898,AMPL_WIDTH),
conv_std_logic_vector(23900,AMPL_WIDTH),
conv_std_logic_vector(23902,AMPL_WIDTH),
conv_std_logic_vector(23904,AMPL_WIDTH),
conv_std_logic_vector(23906,AMPL_WIDTH),
conv_std_logic_vector(23908,AMPL_WIDTH),
conv_std_logic_vector(23910,AMPL_WIDTH),
conv_std_logic_vector(23913,AMPL_WIDTH),
conv_std_logic_vector(23915,AMPL_WIDTH),
conv_std_logic_vector(23917,AMPL_WIDTH),
conv_std_logic_vector(23919,AMPL_WIDTH),
conv_std_logic_vector(23921,AMPL_WIDTH),
conv_std_logic_vector(23923,AMPL_WIDTH),
conv_std_logic_vector(23925,AMPL_WIDTH),
conv_std_logic_vector(23928,AMPL_WIDTH),
conv_std_logic_vector(23930,AMPL_WIDTH),
conv_std_logic_vector(23932,AMPL_WIDTH),
conv_std_logic_vector(23934,AMPL_WIDTH),
conv_std_logic_vector(23936,AMPL_WIDTH),
conv_std_logic_vector(23938,AMPL_WIDTH),
conv_std_logic_vector(23940,AMPL_WIDTH),
conv_std_logic_vector(23943,AMPL_WIDTH),
conv_std_logic_vector(23945,AMPL_WIDTH),
conv_std_logic_vector(23947,AMPL_WIDTH),
conv_std_logic_vector(23949,AMPL_WIDTH),
conv_std_logic_vector(23951,AMPL_WIDTH),
conv_std_logic_vector(23953,AMPL_WIDTH),
conv_std_logic_vector(23956,AMPL_WIDTH),
conv_std_logic_vector(23958,AMPL_WIDTH),
conv_std_logic_vector(23960,AMPL_WIDTH),
conv_std_logic_vector(23962,AMPL_WIDTH),
conv_std_logic_vector(23964,AMPL_WIDTH),
conv_std_logic_vector(23966,AMPL_WIDTH),
conv_std_logic_vector(23968,AMPL_WIDTH),
conv_std_logic_vector(23971,AMPL_WIDTH),
conv_std_logic_vector(23973,AMPL_WIDTH),
conv_std_logic_vector(23975,AMPL_WIDTH),
conv_std_logic_vector(23977,AMPL_WIDTH),
conv_std_logic_vector(23979,AMPL_WIDTH),
conv_std_logic_vector(23981,AMPL_WIDTH),
conv_std_logic_vector(23983,AMPL_WIDTH),
conv_std_logic_vector(23985,AMPL_WIDTH),
conv_std_logic_vector(23988,AMPL_WIDTH),
conv_std_logic_vector(23990,AMPL_WIDTH),
conv_std_logic_vector(23992,AMPL_WIDTH),
conv_std_logic_vector(23994,AMPL_WIDTH),
conv_std_logic_vector(23996,AMPL_WIDTH),
conv_std_logic_vector(23998,AMPL_WIDTH),
conv_std_logic_vector(24000,AMPL_WIDTH),
conv_std_logic_vector(24003,AMPL_WIDTH),
conv_std_logic_vector(24005,AMPL_WIDTH),
conv_std_logic_vector(24007,AMPL_WIDTH),
conv_std_logic_vector(24009,AMPL_WIDTH),
conv_std_logic_vector(24011,AMPL_WIDTH),
conv_std_logic_vector(24013,AMPL_WIDTH),
conv_std_logic_vector(24015,AMPL_WIDTH),
conv_std_logic_vector(24018,AMPL_WIDTH),
conv_std_logic_vector(24020,AMPL_WIDTH),
conv_std_logic_vector(24022,AMPL_WIDTH),
conv_std_logic_vector(24024,AMPL_WIDTH),
conv_std_logic_vector(24026,AMPL_WIDTH),
conv_std_logic_vector(24028,AMPL_WIDTH),
conv_std_logic_vector(24030,AMPL_WIDTH),
conv_std_logic_vector(24033,AMPL_WIDTH),
conv_std_logic_vector(24035,AMPL_WIDTH),
conv_std_logic_vector(24037,AMPL_WIDTH),
conv_std_logic_vector(24039,AMPL_WIDTH),
conv_std_logic_vector(24041,AMPL_WIDTH),
conv_std_logic_vector(24043,AMPL_WIDTH),
conv_std_logic_vector(24045,AMPL_WIDTH),
conv_std_logic_vector(24047,AMPL_WIDTH),
conv_std_logic_vector(24050,AMPL_WIDTH),
conv_std_logic_vector(24052,AMPL_WIDTH),
conv_std_logic_vector(24054,AMPL_WIDTH),
conv_std_logic_vector(24056,AMPL_WIDTH),
conv_std_logic_vector(24058,AMPL_WIDTH),
conv_std_logic_vector(24060,AMPL_WIDTH),
conv_std_logic_vector(24062,AMPL_WIDTH),
conv_std_logic_vector(24065,AMPL_WIDTH),
conv_std_logic_vector(24067,AMPL_WIDTH),
conv_std_logic_vector(24069,AMPL_WIDTH),
conv_std_logic_vector(24071,AMPL_WIDTH),
conv_std_logic_vector(24073,AMPL_WIDTH),
conv_std_logic_vector(24075,AMPL_WIDTH),
conv_std_logic_vector(24077,AMPL_WIDTH),
conv_std_logic_vector(24079,AMPL_WIDTH),
conv_std_logic_vector(24082,AMPL_WIDTH),
conv_std_logic_vector(24084,AMPL_WIDTH),
conv_std_logic_vector(24086,AMPL_WIDTH),
conv_std_logic_vector(24088,AMPL_WIDTH),
conv_std_logic_vector(24090,AMPL_WIDTH),
conv_std_logic_vector(24092,AMPL_WIDTH),
conv_std_logic_vector(24094,AMPL_WIDTH),
conv_std_logic_vector(24096,AMPL_WIDTH),
conv_std_logic_vector(24099,AMPL_WIDTH),
conv_std_logic_vector(24101,AMPL_WIDTH),
conv_std_logic_vector(24103,AMPL_WIDTH),
conv_std_logic_vector(24105,AMPL_WIDTH),
conv_std_logic_vector(24107,AMPL_WIDTH),
conv_std_logic_vector(24109,AMPL_WIDTH),
conv_std_logic_vector(24111,AMPL_WIDTH),
conv_std_logic_vector(24114,AMPL_WIDTH),
conv_std_logic_vector(24116,AMPL_WIDTH),
conv_std_logic_vector(24118,AMPL_WIDTH),
conv_std_logic_vector(24120,AMPL_WIDTH),
conv_std_logic_vector(24122,AMPL_WIDTH),
conv_std_logic_vector(24124,AMPL_WIDTH),
conv_std_logic_vector(24126,AMPL_WIDTH),
conv_std_logic_vector(24128,AMPL_WIDTH),
conv_std_logic_vector(24131,AMPL_WIDTH),
conv_std_logic_vector(24133,AMPL_WIDTH),
conv_std_logic_vector(24135,AMPL_WIDTH),
conv_std_logic_vector(24137,AMPL_WIDTH),
conv_std_logic_vector(24139,AMPL_WIDTH),
conv_std_logic_vector(24141,AMPL_WIDTH),
conv_std_logic_vector(24143,AMPL_WIDTH),
conv_std_logic_vector(24145,AMPL_WIDTH),
conv_std_logic_vector(24148,AMPL_WIDTH),
conv_std_logic_vector(24150,AMPL_WIDTH),
conv_std_logic_vector(24152,AMPL_WIDTH),
conv_std_logic_vector(24154,AMPL_WIDTH),
conv_std_logic_vector(24156,AMPL_WIDTH),
conv_std_logic_vector(24158,AMPL_WIDTH),
conv_std_logic_vector(24160,AMPL_WIDTH),
conv_std_logic_vector(24162,AMPL_WIDTH),
conv_std_logic_vector(24164,AMPL_WIDTH),
conv_std_logic_vector(24167,AMPL_WIDTH),
conv_std_logic_vector(24169,AMPL_WIDTH),
conv_std_logic_vector(24171,AMPL_WIDTH),
conv_std_logic_vector(24173,AMPL_WIDTH),
conv_std_logic_vector(24175,AMPL_WIDTH),
conv_std_logic_vector(24177,AMPL_WIDTH),
conv_std_logic_vector(24179,AMPL_WIDTH),
conv_std_logic_vector(24181,AMPL_WIDTH),
conv_std_logic_vector(24184,AMPL_WIDTH),
conv_std_logic_vector(24186,AMPL_WIDTH),
conv_std_logic_vector(24188,AMPL_WIDTH),
conv_std_logic_vector(24190,AMPL_WIDTH),
conv_std_logic_vector(24192,AMPL_WIDTH),
conv_std_logic_vector(24194,AMPL_WIDTH),
conv_std_logic_vector(24196,AMPL_WIDTH),
conv_std_logic_vector(24198,AMPL_WIDTH),
conv_std_logic_vector(24201,AMPL_WIDTH),
conv_std_logic_vector(24203,AMPL_WIDTH),
conv_std_logic_vector(24205,AMPL_WIDTH),
conv_std_logic_vector(24207,AMPL_WIDTH),
conv_std_logic_vector(24209,AMPL_WIDTH),
conv_std_logic_vector(24211,AMPL_WIDTH),
conv_std_logic_vector(24213,AMPL_WIDTH),
conv_std_logic_vector(24215,AMPL_WIDTH),
conv_std_logic_vector(24217,AMPL_WIDTH),
conv_std_logic_vector(24220,AMPL_WIDTH),
conv_std_logic_vector(24222,AMPL_WIDTH),
conv_std_logic_vector(24224,AMPL_WIDTH),
conv_std_logic_vector(24226,AMPL_WIDTH),
conv_std_logic_vector(24228,AMPL_WIDTH),
conv_std_logic_vector(24230,AMPL_WIDTH),
conv_std_logic_vector(24232,AMPL_WIDTH),
conv_std_logic_vector(24234,AMPL_WIDTH),
conv_std_logic_vector(24237,AMPL_WIDTH),
conv_std_logic_vector(24239,AMPL_WIDTH),
conv_std_logic_vector(24241,AMPL_WIDTH),
conv_std_logic_vector(24243,AMPL_WIDTH),
conv_std_logic_vector(24245,AMPL_WIDTH),
conv_std_logic_vector(24247,AMPL_WIDTH),
conv_std_logic_vector(24249,AMPL_WIDTH),
conv_std_logic_vector(24251,AMPL_WIDTH),
conv_std_logic_vector(24253,AMPL_WIDTH),
conv_std_logic_vector(24256,AMPL_WIDTH),
conv_std_logic_vector(24258,AMPL_WIDTH),
conv_std_logic_vector(24260,AMPL_WIDTH),
conv_std_logic_vector(24262,AMPL_WIDTH),
conv_std_logic_vector(24264,AMPL_WIDTH),
conv_std_logic_vector(24266,AMPL_WIDTH),
conv_std_logic_vector(24268,AMPL_WIDTH),
conv_std_logic_vector(24270,AMPL_WIDTH),
conv_std_logic_vector(24272,AMPL_WIDTH),
conv_std_logic_vector(24275,AMPL_WIDTH),
conv_std_logic_vector(24277,AMPL_WIDTH),
conv_std_logic_vector(24279,AMPL_WIDTH),
conv_std_logic_vector(24281,AMPL_WIDTH),
conv_std_logic_vector(24283,AMPL_WIDTH),
conv_std_logic_vector(24285,AMPL_WIDTH),
conv_std_logic_vector(24287,AMPL_WIDTH),
conv_std_logic_vector(24289,AMPL_WIDTH),
conv_std_logic_vector(24291,AMPL_WIDTH),
conv_std_logic_vector(24294,AMPL_WIDTH),
conv_std_logic_vector(24296,AMPL_WIDTH),
conv_std_logic_vector(24298,AMPL_WIDTH),
conv_std_logic_vector(24300,AMPL_WIDTH),
conv_std_logic_vector(24302,AMPL_WIDTH),
conv_std_logic_vector(24304,AMPL_WIDTH),
conv_std_logic_vector(24306,AMPL_WIDTH),
conv_std_logic_vector(24308,AMPL_WIDTH),
conv_std_logic_vector(24310,AMPL_WIDTH),
conv_std_logic_vector(24312,AMPL_WIDTH),
conv_std_logic_vector(24315,AMPL_WIDTH),
conv_std_logic_vector(24317,AMPL_WIDTH),
conv_std_logic_vector(24319,AMPL_WIDTH),
conv_std_logic_vector(24321,AMPL_WIDTH),
conv_std_logic_vector(24323,AMPL_WIDTH),
conv_std_logic_vector(24325,AMPL_WIDTH),
conv_std_logic_vector(24327,AMPL_WIDTH),
conv_std_logic_vector(24329,AMPL_WIDTH),
conv_std_logic_vector(24331,AMPL_WIDTH),
conv_std_logic_vector(24334,AMPL_WIDTH),
conv_std_logic_vector(24336,AMPL_WIDTH),
conv_std_logic_vector(24338,AMPL_WIDTH),
conv_std_logic_vector(24340,AMPL_WIDTH),
conv_std_logic_vector(24342,AMPL_WIDTH),
conv_std_logic_vector(24344,AMPL_WIDTH),
conv_std_logic_vector(24346,AMPL_WIDTH),
conv_std_logic_vector(24348,AMPL_WIDTH),
conv_std_logic_vector(24350,AMPL_WIDTH),
conv_std_logic_vector(24352,AMPL_WIDTH),
conv_std_logic_vector(24355,AMPL_WIDTH),
conv_std_logic_vector(24357,AMPL_WIDTH),
conv_std_logic_vector(24359,AMPL_WIDTH),
conv_std_logic_vector(24361,AMPL_WIDTH),
conv_std_logic_vector(24363,AMPL_WIDTH),
conv_std_logic_vector(24365,AMPL_WIDTH),
conv_std_logic_vector(24367,AMPL_WIDTH),
conv_std_logic_vector(24369,AMPL_WIDTH),
conv_std_logic_vector(24371,AMPL_WIDTH),
conv_std_logic_vector(24373,AMPL_WIDTH),
conv_std_logic_vector(24376,AMPL_WIDTH),
conv_std_logic_vector(24378,AMPL_WIDTH),
conv_std_logic_vector(24380,AMPL_WIDTH),
conv_std_logic_vector(24382,AMPL_WIDTH),
conv_std_logic_vector(24384,AMPL_WIDTH),
conv_std_logic_vector(24386,AMPL_WIDTH),
conv_std_logic_vector(24388,AMPL_WIDTH),
conv_std_logic_vector(24390,AMPL_WIDTH),
conv_std_logic_vector(24392,AMPL_WIDTH),
conv_std_logic_vector(24394,AMPL_WIDTH),
conv_std_logic_vector(24397,AMPL_WIDTH),
conv_std_logic_vector(24399,AMPL_WIDTH),
conv_std_logic_vector(24401,AMPL_WIDTH),
conv_std_logic_vector(24403,AMPL_WIDTH),
conv_std_logic_vector(24405,AMPL_WIDTH),
conv_std_logic_vector(24407,AMPL_WIDTH),
conv_std_logic_vector(24409,AMPL_WIDTH),
conv_std_logic_vector(24411,AMPL_WIDTH),
conv_std_logic_vector(24413,AMPL_WIDTH),
conv_std_logic_vector(24415,AMPL_WIDTH),
conv_std_logic_vector(24417,AMPL_WIDTH),
conv_std_logic_vector(24420,AMPL_WIDTH),
conv_std_logic_vector(24422,AMPL_WIDTH),
conv_std_logic_vector(24424,AMPL_WIDTH),
conv_std_logic_vector(24426,AMPL_WIDTH),
conv_std_logic_vector(24428,AMPL_WIDTH),
conv_std_logic_vector(24430,AMPL_WIDTH),
conv_std_logic_vector(24432,AMPL_WIDTH),
conv_std_logic_vector(24434,AMPL_WIDTH),
conv_std_logic_vector(24436,AMPL_WIDTH),
conv_std_logic_vector(24438,AMPL_WIDTH),
conv_std_logic_vector(24441,AMPL_WIDTH),
conv_std_logic_vector(24443,AMPL_WIDTH),
conv_std_logic_vector(24445,AMPL_WIDTH),
conv_std_logic_vector(24447,AMPL_WIDTH),
conv_std_logic_vector(24449,AMPL_WIDTH),
conv_std_logic_vector(24451,AMPL_WIDTH),
conv_std_logic_vector(24453,AMPL_WIDTH),
conv_std_logic_vector(24455,AMPL_WIDTH),
conv_std_logic_vector(24457,AMPL_WIDTH),
conv_std_logic_vector(24459,AMPL_WIDTH),
conv_std_logic_vector(24461,AMPL_WIDTH),
conv_std_logic_vector(24464,AMPL_WIDTH),
conv_std_logic_vector(24466,AMPL_WIDTH),
conv_std_logic_vector(24468,AMPL_WIDTH),
conv_std_logic_vector(24470,AMPL_WIDTH),
conv_std_logic_vector(24472,AMPL_WIDTH),
conv_std_logic_vector(24474,AMPL_WIDTH),
conv_std_logic_vector(24476,AMPL_WIDTH),
conv_std_logic_vector(24478,AMPL_WIDTH),
conv_std_logic_vector(24480,AMPL_WIDTH),
conv_std_logic_vector(24482,AMPL_WIDTH),
conv_std_logic_vector(24484,AMPL_WIDTH),
conv_std_logic_vector(24487,AMPL_WIDTH),
conv_std_logic_vector(24489,AMPL_WIDTH),
conv_std_logic_vector(24491,AMPL_WIDTH),
conv_std_logic_vector(24493,AMPL_WIDTH),
conv_std_logic_vector(24495,AMPL_WIDTH),
conv_std_logic_vector(24497,AMPL_WIDTH),
conv_std_logic_vector(24499,AMPL_WIDTH),
conv_std_logic_vector(24501,AMPL_WIDTH),
conv_std_logic_vector(24503,AMPL_WIDTH),
conv_std_logic_vector(24505,AMPL_WIDTH),
conv_std_logic_vector(24507,AMPL_WIDTH),
conv_std_logic_vector(24509,AMPL_WIDTH),
conv_std_logic_vector(24512,AMPL_WIDTH),
conv_std_logic_vector(24514,AMPL_WIDTH),
conv_std_logic_vector(24516,AMPL_WIDTH),
conv_std_logic_vector(24518,AMPL_WIDTH),
conv_std_logic_vector(24520,AMPL_WIDTH),
conv_std_logic_vector(24522,AMPL_WIDTH),
conv_std_logic_vector(24524,AMPL_WIDTH),
conv_std_logic_vector(24526,AMPL_WIDTH),
conv_std_logic_vector(24528,AMPL_WIDTH),
conv_std_logic_vector(24530,AMPL_WIDTH),
conv_std_logic_vector(24532,AMPL_WIDTH),
conv_std_logic_vector(24534,AMPL_WIDTH),
conv_std_logic_vector(24537,AMPL_WIDTH),
conv_std_logic_vector(24539,AMPL_WIDTH),
conv_std_logic_vector(24541,AMPL_WIDTH),
conv_std_logic_vector(24543,AMPL_WIDTH),
conv_std_logic_vector(24545,AMPL_WIDTH),
conv_std_logic_vector(24547,AMPL_WIDTH),
conv_std_logic_vector(24549,AMPL_WIDTH),
conv_std_logic_vector(24551,AMPL_WIDTH),
conv_std_logic_vector(24553,AMPL_WIDTH),
conv_std_logic_vector(24555,AMPL_WIDTH),
conv_std_logic_vector(24557,AMPL_WIDTH),
conv_std_logic_vector(24559,AMPL_WIDTH),
conv_std_logic_vector(24562,AMPL_WIDTH),
conv_std_logic_vector(24564,AMPL_WIDTH),
conv_std_logic_vector(24566,AMPL_WIDTH),
conv_std_logic_vector(24568,AMPL_WIDTH),
conv_std_logic_vector(24570,AMPL_WIDTH),
conv_std_logic_vector(24572,AMPL_WIDTH),
conv_std_logic_vector(24574,AMPL_WIDTH),
conv_std_logic_vector(24576,AMPL_WIDTH),
conv_std_logic_vector(24578,AMPL_WIDTH),
conv_std_logic_vector(24580,AMPL_WIDTH),
conv_std_logic_vector(24582,AMPL_WIDTH),
conv_std_logic_vector(24584,AMPL_WIDTH),
conv_std_logic_vector(24586,AMPL_WIDTH),
conv_std_logic_vector(24589,AMPL_WIDTH),
conv_std_logic_vector(24591,AMPL_WIDTH),
conv_std_logic_vector(24593,AMPL_WIDTH),
conv_std_logic_vector(24595,AMPL_WIDTH),
conv_std_logic_vector(24597,AMPL_WIDTH),
conv_std_logic_vector(24599,AMPL_WIDTH),
conv_std_logic_vector(24601,AMPL_WIDTH),
conv_std_logic_vector(24603,AMPL_WIDTH),
conv_std_logic_vector(24605,AMPL_WIDTH),
conv_std_logic_vector(24607,AMPL_WIDTH),
conv_std_logic_vector(24609,AMPL_WIDTH),
conv_std_logic_vector(24611,AMPL_WIDTH),
conv_std_logic_vector(24613,AMPL_WIDTH),
conv_std_logic_vector(24616,AMPL_WIDTH),
conv_std_logic_vector(24618,AMPL_WIDTH),
conv_std_logic_vector(24620,AMPL_WIDTH),
conv_std_logic_vector(24622,AMPL_WIDTH),
conv_std_logic_vector(24624,AMPL_WIDTH),
conv_std_logic_vector(24626,AMPL_WIDTH),
conv_std_logic_vector(24628,AMPL_WIDTH),
conv_std_logic_vector(24630,AMPL_WIDTH),
conv_std_logic_vector(24632,AMPL_WIDTH),
conv_std_logic_vector(24634,AMPL_WIDTH),
conv_std_logic_vector(24636,AMPL_WIDTH),
conv_std_logic_vector(24638,AMPL_WIDTH),
conv_std_logic_vector(24640,AMPL_WIDTH),
conv_std_logic_vector(24642,AMPL_WIDTH),
conv_std_logic_vector(24645,AMPL_WIDTH),
conv_std_logic_vector(24647,AMPL_WIDTH),
conv_std_logic_vector(24649,AMPL_WIDTH),
conv_std_logic_vector(24651,AMPL_WIDTH),
conv_std_logic_vector(24653,AMPL_WIDTH),
conv_std_logic_vector(24655,AMPL_WIDTH),
conv_std_logic_vector(24657,AMPL_WIDTH),
conv_std_logic_vector(24659,AMPL_WIDTH),
conv_std_logic_vector(24661,AMPL_WIDTH),
conv_std_logic_vector(24663,AMPL_WIDTH),
conv_std_logic_vector(24665,AMPL_WIDTH),
conv_std_logic_vector(24667,AMPL_WIDTH),
conv_std_logic_vector(24669,AMPL_WIDTH),
conv_std_logic_vector(24671,AMPL_WIDTH),
conv_std_logic_vector(24673,AMPL_WIDTH),
conv_std_logic_vector(24676,AMPL_WIDTH),
conv_std_logic_vector(24678,AMPL_WIDTH),
conv_std_logic_vector(24680,AMPL_WIDTH),
conv_std_logic_vector(24682,AMPL_WIDTH),
conv_std_logic_vector(24684,AMPL_WIDTH),
conv_std_logic_vector(24686,AMPL_WIDTH),
conv_std_logic_vector(24688,AMPL_WIDTH),
conv_std_logic_vector(24690,AMPL_WIDTH),
conv_std_logic_vector(24692,AMPL_WIDTH),
conv_std_logic_vector(24694,AMPL_WIDTH),
conv_std_logic_vector(24696,AMPL_WIDTH),
conv_std_logic_vector(24698,AMPL_WIDTH),
conv_std_logic_vector(24700,AMPL_WIDTH),
conv_std_logic_vector(24702,AMPL_WIDTH),
conv_std_logic_vector(24704,AMPL_WIDTH),
conv_std_logic_vector(24707,AMPL_WIDTH),
conv_std_logic_vector(24709,AMPL_WIDTH),
conv_std_logic_vector(24711,AMPL_WIDTH),
conv_std_logic_vector(24713,AMPL_WIDTH),
conv_std_logic_vector(24715,AMPL_WIDTH),
conv_std_logic_vector(24717,AMPL_WIDTH),
conv_std_logic_vector(24719,AMPL_WIDTH),
conv_std_logic_vector(24721,AMPL_WIDTH),
conv_std_logic_vector(24723,AMPL_WIDTH),
conv_std_logic_vector(24725,AMPL_WIDTH),
conv_std_logic_vector(24727,AMPL_WIDTH),
conv_std_logic_vector(24729,AMPL_WIDTH),
conv_std_logic_vector(24731,AMPL_WIDTH),
conv_std_logic_vector(24733,AMPL_WIDTH),
conv_std_logic_vector(24735,AMPL_WIDTH),
conv_std_logic_vector(24737,AMPL_WIDTH),
conv_std_logic_vector(24740,AMPL_WIDTH),
conv_std_logic_vector(24742,AMPL_WIDTH),
conv_std_logic_vector(24744,AMPL_WIDTH),
conv_std_logic_vector(24746,AMPL_WIDTH),
conv_std_logic_vector(24748,AMPL_WIDTH),
conv_std_logic_vector(24750,AMPL_WIDTH),
conv_std_logic_vector(24752,AMPL_WIDTH),
conv_std_logic_vector(24754,AMPL_WIDTH),
conv_std_logic_vector(24756,AMPL_WIDTH),
conv_std_logic_vector(24758,AMPL_WIDTH),
conv_std_logic_vector(24760,AMPL_WIDTH),
conv_std_logic_vector(24762,AMPL_WIDTH),
conv_std_logic_vector(24764,AMPL_WIDTH),
conv_std_logic_vector(24766,AMPL_WIDTH),
conv_std_logic_vector(24768,AMPL_WIDTH),
conv_std_logic_vector(24770,AMPL_WIDTH),
conv_std_logic_vector(24772,AMPL_WIDTH),
conv_std_logic_vector(24774,AMPL_WIDTH),
conv_std_logic_vector(24777,AMPL_WIDTH),
conv_std_logic_vector(24779,AMPL_WIDTH),
conv_std_logic_vector(24781,AMPL_WIDTH),
conv_std_logic_vector(24783,AMPL_WIDTH),
conv_std_logic_vector(24785,AMPL_WIDTH),
conv_std_logic_vector(24787,AMPL_WIDTH),
conv_std_logic_vector(24789,AMPL_WIDTH),
conv_std_logic_vector(24791,AMPL_WIDTH),
conv_std_logic_vector(24793,AMPL_WIDTH),
conv_std_logic_vector(24795,AMPL_WIDTH),
conv_std_logic_vector(24797,AMPL_WIDTH),
conv_std_logic_vector(24799,AMPL_WIDTH),
conv_std_logic_vector(24801,AMPL_WIDTH),
conv_std_logic_vector(24803,AMPL_WIDTH),
conv_std_logic_vector(24805,AMPL_WIDTH),
conv_std_logic_vector(24807,AMPL_WIDTH),
conv_std_logic_vector(24809,AMPL_WIDTH),
conv_std_logic_vector(24811,AMPL_WIDTH),
conv_std_logic_vector(24814,AMPL_WIDTH),
conv_std_logic_vector(24816,AMPL_WIDTH),
conv_std_logic_vector(24818,AMPL_WIDTH),
conv_std_logic_vector(24820,AMPL_WIDTH),
conv_std_logic_vector(24822,AMPL_WIDTH),
conv_std_logic_vector(24824,AMPL_WIDTH),
conv_std_logic_vector(24826,AMPL_WIDTH),
conv_std_logic_vector(24828,AMPL_WIDTH),
conv_std_logic_vector(24830,AMPL_WIDTH),
conv_std_logic_vector(24832,AMPL_WIDTH),
conv_std_logic_vector(24834,AMPL_WIDTH),
conv_std_logic_vector(24836,AMPL_WIDTH),
conv_std_logic_vector(24838,AMPL_WIDTH),
conv_std_logic_vector(24840,AMPL_WIDTH),
conv_std_logic_vector(24842,AMPL_WIDTH),
conv_std_logic_vector(24844,AMPL_WIDTH),
conv_std_logic_vector(24846,AMPL_WIDTH),
conv_std_logic_vector(24848,AMPL_WIDTH),
conv_std_logic_vector(24850,AMPL_WIDTH),
conv_std_logic_vector(24852,AMPL_WIDTH),
conv_std_logic_vector(24855,AMPL_WIDTH),
conv_std_logic_vector(24857,AMPL_WIDTH),
conv_std_logic_vector(24859,AMPL_WIDTH),
conv_std_logic_vector(24861,AMPL_WIDTH),
conv_std_logic_vector(24863,AMPL_WIDTH),
conv_std_logic_vector(24865,AMPL_WIDTH),
conv_std_logic_vector(24867,AMPL_WIDTH),
conv_std_logic_vector(24869,AMPL_WIDTH),
conv_std_logic_vector(24871,AMPL_WIDTH),
conv_std_logic_vector(24873,AMPL_WIDTH),
conv_std_logic_vector(24875,AMPL_WIDTH),
conv_std_logic_vector(24877,AMPL_WIDTH),
conv_std_logic_vector(24879,AMPL_WIDTH),
conv_std_logic_vector(24881,AMPL_WIDTH),
conv_std_logic_vector(24883,AMPL_WIDTH),
conv_std_logic_vector(24885,AMPL_WIDTH),
conv_std_logic_vector(24887,AMPL_WIDTH),
conv_std_logic_vector(24889,AMPL_WIDTH),
conv_std_logic_vector(24891,AMPL_WIDTH),
conv_std_logic_vector(24893,AMPL_WIDTH),
conv_std_logic_vector(24895,AMPL_WIDTH),
conv_std_logic_vector(24897,AMPL_WIDTH),
conv_std_logic_vector(24899,AMPL_WIDTH),
conv_std_logic_vector(24902,AMPL_WIDTH),
conv_std_logic_vector(24904,AMPL_WIDTH),
conv_std_logic_vector(24906,AMPL_WIDTH),
conv_std_logic_vector(24908,AMPL_WIDTH),
conv_std_logic_vector(24910,AMPL_WIDTH),
conv_std_logic_vector(24912,AMPL_WIDTH),
conv_std_logic_vector(24914,AMPL_WIDTH),
conv_std_logic_vector(24916,AMPL_WIDTH),
conv_std_logic_vector(24918,AMPL_WIDTH),
conv_std_logic_vector(24920,AMPL_WIDTH),
conv_std_logic_vector(24922,AMPL_WIDTH),
conv_std_logic_vector(24924,AMPL_WIDTH),
conv_std_logic_vector(24926,AMPL_WIDTH),
conv_std_logic_vector(24928,AMPL_WIDTH),
conv_std_logic_vector(24930,AMPL_WIDTH),
conv_std_logic_vector(24932,AMPL_WIDTH),
conv_std_logic_vector(24934,AMPL_WIDTH),
conv_std_logic_vector(24936,AMPL_WIDTH),
conv_std_logic_vector(24938,AMPL_WIDTH),
conv_std_logic_vector(24940,AMPL_WIDTH),
conv_std_logic_vector(24942,AMPL_WIDTH),
conv_std_logic_vector(24944,AMPL_WIDTH),
conv_std_logic_vector(24946,AMPL_WIDTH),
conv_std_logic_vector(24948,AMPL_WIDTH),
conv_std_logic_vector(24950,AMPL_WIDTH),
conv_std_logic_vector(24953,AMPL_WIDTH),
conv_std_logic_vector(24955,AMPL_WIDTH),
conv_std_logic_vector(24957,AMPL_WIDTH),
conv_std_logic_vector(24959,AMPL_WIDTH),
conv_std_logic_vector(24961,AMPL_WIDTH),
conv_std_logic_vector(24963,AMPL_WIDTH),
conv_std_logic_vector(24965,AMPL_WIDTH),
conv_std_logic_vector(24967,AMPL_WIDTH),
conv_std_logic_vector(24969,AMPL_WIDTH),
conv_std_logic_vector(24971,AMPL_WIDTH),
conv_std_logic_vector(24973,AMPL_WIDTH),
conv_std_logic_vector(24975,AMPL_WIDTH),
conv_std_logic_vector(24977,AMPL_WIDTH),
conv_std_logic_vector(24979,AMPL_WIDTH),
conv_std_logic_vector(24981,AMPL_WIDTH),
conv_std_logic_vector(24983,AMPL_WIDTH),
conv_std_logic_vector(24985,AMPL_WIDTH),
conv_std_logic_vector(24987,AMPL_WIDTH),
conv_std_logic_vector(24989,AMPL_WIDTH),
conv_std_logic_vector(24991,AMPL_WIDTH),
conv_std_logic_vector(24993,AMPL_WIDTH),
conv_std_logic_vector(24995,AMPL_WIDTH),
conv_std_logic_vector(24997,AMPL_WIDTH),
conv_std_logic_vector(24999,AMPL_WIDTH),
conv_std_logic_vector(25001,AMPL_WIDTH),
conv_std_logic_vector(25003,AMPL_WIDTH),
conv_std_logic_vector(25005,AMPL_WIDTH),
conv_std_logic_vector(25007,AMPL_WIDTH),
conv_std_logic_vector(25009,AMPL_WIDTH),
conv_std_logic_vector(25011,AMPL_WIDTH),
conv_std_logic_vector(25013,AMPL_WIDTH),
conv_std_logic_vector(25016,AMPL_WIDTH),
conv_std_logic_vector(25018,AMPL_WIDTH),
conv_std_logic_vector(25020,AMPL_WIDTH),
conv_std_logic_vector(25022,AMPL_WIDTH),
conv_std_logic_vector(25024,AMPL_WIDTH),
conv_std_logic_vector(25026,AMPL_WIDTH),
conv_std_logic_vector(25028,AMPL_WIDTH),
conv_std_logic_vector(25030,AMPL_WIDTH),
conv_std_logic_vector(25032,AMPL_WIDTH),
conv_std_logic_vector(25034,AMPL_WIDTH),
conv_std_logic_vector(25036,AMPL_WIDTH),
conv_std_logic_vector(25038,AMPL_WIDTH),
conv_std_logic_vector(25040,AMPL_WIDTH),
conv_std_logic_vector(25042,AMPL_WIDTH),
conv_std_logic_vector(25044,AMPL_WIDTH),
conv_std_logic_vector(25046,AMPL_WIDTH),
conv_std_logic_vector(25048,AMPL_WIDTH),
conv_std_logic_vector(25050,AMPL_WIDTH),
conv_std_logic_vector(25052,AMPL_WIDTH),
conv_std_logic_vector(25054,AMPL_WIDTH),
conv_std_logic_vector(25056,AMPL_WIDTH),
conv_std_logic_vector(25058,AMPL_WIDTH),
conv_std_logic_vector(25060,AMPL_WIDTH),
conv_std_logic_vector(25062,AMPL_WIDTH),
conv_std_logic_vector(25064,AMPL_WIDTH),
conv_std_logic_vector(25066,AMPL_WIDTH),
conv_std_logic_vector(25068,AMPL_WIDTH),
conv_std_logic_vector(25070,AMPL_WIDTH),
conv_std_logic_vector(25072,AMPL_WIDTH),
conv_std_logic_vector(25074,AMPL_WIDTH),
conv_std_logic_vector(25076,AMPL_WIDTH),
conv_std_logic_vector(25078,AMPL_WIDTH),
conv_std_logic_vector(25080,AMPL_WIDTH),
conv_std_logic_vector(25082,AMPL_WIDTH),
conv_std_logic_vector(25084,AMPL_WIDTH),
conv_std_logic_vector(25086,AMPL_WIDTH),
conv_std_logic_vector(25088,AMPL_WIDTH),
conv_std_logic_vector(25090,AMPL_WIDTH),
conv_std_logic_vector(25092,AMPL_WIDTH),
conv_std_logic_vector(25094,AMPL_WIDTH),
conv_std_logic_vector(25096,AMPL_WIDTH),
conv_std_logic_vector(25099,AMPL_WIDTH),
conv_std_logic_vector(25101,AMPL_WIDTH),
conv_std_logic_vector(25103,AMPL_WIDTH),
conv_std_logic_vector(25105,AMPL_WIDTH),
conv_std_logic_vector(25107,AMPL_WIDTH),
conv_std_logic_vector(25109,AMPL_WIDTH),
conv_std_logic_vector(25111,AMPL_WIDTH),
conv_std_logic_vector(25113,AMPL_WIDTH),
conv_std_logic_vector(25115,AMPL_WIDTH),
conv_std_logic_vector(25117,AMPL_WIDTH),
conv_std_logic_vector(25119,AMPL_WIDTH),
conv_std_logic_vector(25121,AMPL_WIDTH),
conv_std_logic_vector(25123,AMPL_WIDTH),
conv_std_logic_vector(25125,AMPL_WIDTH),
conv_std_logic_vector(25127,AMPL_WIDTH),
conv_std_logic_vector(25129,AMPL_WIDTH),
conv_std_logic_vector(25131,AMPL_WIDTH),
conv_std_logic_vector(25133,AMPL_WIDTH),
conv_std_logic_vector(25135,AMPL_WIDTH),
conv_std_logic_vector(25137,AMPL_WIDTH),
conv_std_logic_vector(25139,AMPL_WIDTH),
conv_std_logic_vector(25141,AMPL_WIDTH),
conv_std_logic_vector(25143,AMPL_WIDTH),
conv_std_logic_vector(25145,AMPL_WIDTH),
conv_std_logic_vector(25147,AMPL_WIDTH),
conv_std_logic_vector(25149,AMPL_WIDTH),
conv_std_logic_vector(25151,AMPL_WIDTH),
conv_std_logic_vector(25153,AMPL_WIDTH),
conv_std_logic_vector(25155,AMPL_WIDTH),
conv_std_logic_vector(25157,AMPL_WIDTH),
conv_std_logic_vector(25159,AMPL_WIDTH),
conv_std_logic_vector(25161,AMPL_WIDTH),
conv_std_logic_vector(25163,AMPL_WIDTH),
conv_std_logic_vector(25165,AMPL_WIDTH),
conv_std_logic_vector(25167,AMPL_WIDTH),
conv_std_logic_vector(25169,AMPL_WIDTH),
conv_std_logic_vector(25171,AMPL_WIDTH),
conv_std_logic_vector(25173,AMPL_WIDTH),
conv_std_logic_vector(25175,AMPL_WIDTH),
conv_std_logic_vector(25177,AMPL_WIDTH),
conv_std_logic_vector(25179,AMPL_WIDTH),
conv_std_logic_vector(25181,AMPL_WIDTH),
conv_std_logic_vector(25183,AMPL_WIDTH),
conv_std_logic_vector(25185,AMPL_WIDTH),
conv_std_logic_vector(25187,AMPL_WIDTH),
conv_std_logic_vector(25189,AMPL_WIDTH),
conv_std_logic_vector(25191,AMPL_WIDTH),
conv_std_logic_vector(25193,AMPL_WIDTH),
conv_std_logic_vector(25195,AMPL_WIDTH),
conv_std_logic_vector(25197,AMPL_WIDTH),
conv_std_logic_vector(25199,AMPL_WIDTH),
conv_std_logic_vector(25201,AMPL_WIDTH),
conv_std_logic_vector(25203,AMPL_WIDTH),
conv_std_logic_vector(25205,AMPL_WIDTH),
conv_std_logic_vector(25207,AMPL_WIDTH),
conv_std_logic_vector(25209,AMPL_WIDTH),
conv_std_logic_vector(25211,AMPL_WIDTH),
conv_std_logic_vector(25213,AMPL_WIDTH),
conv_std_logic_vector(25215,AMPL_WIDTH),
conv_std_logic_vector(25217,AMPL_WIDTH),
conv_std_logic_vector(25219,AMPL_WIDTH),
conv_std_logic_vector(25221,AMPL_WIDTH),
conv_std_logic_vector(25223,AMPL_WIDTH),
conv_std_logic_vector(25225,AMPL_WIDTH),
conv_std_logic_vector(25227,AMPL_WIDTH),
conv_std_logic_vector(25229,AMPL_WIDTH),
conv_std_logic_vector(25231,AMPL_WIDTH),
conv_std_logic_vector(25233,AMPL_WIDTH),
conv_std_logic_vector(25235,AMPL_WIDTH),
conv_std_logic_vector(25237,AMPL_WIDTH),
conv_std_logic_vector(25239,AMPL_WIDTH),
conv_std_logic_vector(25241,AMPL_WIDTH),
conv_std_logic_vector(25243,AMPL_WIDTH),
conv_std_logic_vector(25245,AMPL_WIDTH),
conv_std_logic_vector(25247,AMPL_WIDTH),
conv_std_logic_vector(25249,AMPL_WIDTH),
conv_std_logic_vector(25251,AMPL_WIDTH),
conv_std_logic_vector(25253,AMPL_WIDTH),
conv_std_logic_vector(25255,AMPL_WIDTH),
conv_std_logic_vector(25257,AMPL_WIDTH),
conv_std_logic_vector(25259,AMPL_WIDTH),
conv_std_logic_vector(25261,AMPL_WIDTH),
conv_std_logic_vector(25263,AMPL_WIDTH),
conv_std_logic_vector(25265,AMPL_WIDTH),
conv_std_logic_vector(25267,AMPL_WIDTH),
conv_std_logic_vector(25269,AMPL_WIDTH),
conv_std_logic_vector(25271,AMPL_WIDTH),
conv_std_logic_vector(25273,AMPL_WIDTH),
conv_std_logic_vector(25275,AMPL_WIDTH),
conv_std_logic_vector(25277,AMPL_WIDTH),
conv_std_logic_vector(25279,AMPL_WIDTH),
conv_std_logic_vector(25281,AMPL_WIDTH),
conv_std_logic_vector(25283,AMPL_WIDTH),
conv_std_logic_vector(25285,AMPL_WIDTH),
conv_std_logic_vector(25287,AMPL_WIDTH),
conv_std_logic_vector(25289,AMPL_WIDTH),
conv_std_logic_vector(25291,AMPL_WIDTH),
conv_std_logic_vector(25293,AMPL_WIDTH),
conv_std_logic_vector(25295,AMPL_WIDTH),
conv_std_logic_vector(25297,AMPL_WIDTH),
conv_std_logic_vector(25299,AMPL_WIDTH),
conv_std_logic_vector(25301,AMPL_WIDTH),
conv_std_logic_vector(25303,AMPL_WIDTH),
conv_std_logic_vector(25305,AMPL_WIDTH),
conv_std_logic_vector(25307,AMPL_WIDTH),
conv_std_logic_vector(25309,AMPL_WIDTH),
conv_std_logic_vector(25311,AMPL_WIDTH),
conv_std_logic_vector(25313,AMPL_WIDTH),
conv_std_logic_vector(25315,AMPL_WIDTH),
conv_std_logic_vector(25317,AMPL_WIDTH),
conv_std_logic_vector(25319,AMPL_WIDTH),
conv_std_logic_vector(25321,AMPL_WIDTH),
conv_std_logic_vector(25323,AMPL_WIDTH),
conv_std_logic_vector(25325,AMPL_WIDTH),
conv_std_logic_vector(25327,AMPL_WIDTH),
conv_std_logic_vector(25329,AMPL_WIDTH),
conv_std_logic_vector(25331,AMPL_WIDTH),
conv_std_logic_vector(25333,AMPL_WIDTH),
conv_std_logic_vector(25335,AMPL_WIDTH),
conv_std_logic_vector(25337,AMPL_WIDTH),
conv_std_logic_vector(25339,AMPL_WIDTH),
conv_std_logic_vector(25341,AMPL_WIDTH),
conv_std_logic_vector(25343,AMPL_WIDTH),
conv_std_logic_vector(25345,AMPL_WIDTH),
conv_std_logic_vector(25347,AMPL_WIDTH),
conv_std_logic_vector(25349,AMPL_WIDTH),
conv_std_logic_vector(25351,AMPL_WIDTH),
conv_std_logic_vector(25353,AMPL_WIDTH),
conv_std_logic_vector(25355,AMPL_WIDTH),
conv_std_logic_vector(25357,AMPL_WIDTH),
conv_std_logic_vector(25359,AMPL_WIDTH),
conv_std_logic_vector(25361,AMPL_WIDTH),
conv_std_logic_vector(25363,AMPL_WIDTH),
conv_std_logic_vector(25365,AMPL_WIDTH),
conv_std_logic_vector(25367,AMPL_WIDTH),
conv_std_logic_vector(25369,AMPL_WIDTH),
conv_std_logic_vector(25371,AMPL_WIDTH),
conv_std_logic_vector(25373,AMPL_WIDTH),
conv_std_logic_vector(25375,AMPL_WIDTH),
conv_std_logic_vector(25377,AMPL_WIDTH),
conv_std_logic_vector(25379,AMPL_WIDTH),
conv_std_logic_vector(25381,AMPL_WIDTH),
conv_std_logic_vector(25383,AMPL_WIDTH),
conv_std_logic_vector(25385,AMPL_WIDTH),
conv_std_logic_vector(25387,AMPL_WIDTH),
conv_std_logic_vector(25389,AMPL_WIDTH),
conv_std_logic_vector(25391,AMPL_WIDTH),
conv_std_logic_vector(25393,AMPL_WIDTH),
conv_std_logic_vector(25395,AMPL_WIDTH),
conv_std_logic_vector(25397,AMPL_WIDTH),
conv_std_logic_vector(25399,AMPL_WIDTH),
conv_std_logic_vector(25401,AMPL_WIDTH),
conv_std_logic_vector(25403,AMPL_WIDTH),
conv_std_logic_vector(25405,AMPL_WIDTH),
conv_std_logic_vector(25407,AMPL_WIDTH),
conv_std_logic_vector(25409,AMPL_WIDTH),
conv_std_logic_vector(25411,AMPL_WIDTH),
conv_std_logic_vector(25413,AMPL_WIDTH),
conv_std_logic_vector(25415,AMPL_WIDTH),
conv_std_logic_vector(25417,AMPL_WIDTH),
conv_std_logic_vector(25419,AMPL_WIDTH),
conv_std_logic_vector(25421,AMPL_WIDTH),
conv_std_logic_vector(25423,AMPL_WIDTH),
conv_std_logic_vector(25425,AMPL_WIDTH),
conv_std_logic_vector(25427,AMPL_WIDTH),
conv_std_logic_vector(25429,AMPL_WIDTH),
conv_std_logic_vector(25431,AMPL_WIDTH),
conv_std_logic_vector(25433,AMPL_WIDTH),
conv_std_logic_vector(25435,AMPL_WIDTH),
conv_std_logic_vector(25437,AMPL_WIDTH),
conv_std_logic_vector(25438,AMPL_WIDTH),
conv_std_logic_vector(25440,AMPL_WIDTH),
conv_std_logic_vector(25442,AMPL_WIDTH),
conv_std_logic_vector(25444,AMPL_WIDTH),
conv_std_logic_vector(25446,AMPL_WIDTH),
conv_std_logic_vector(25448,AMPL_WIDTH),
conv_std_logic_vector(25450,AMPL_WIDTH),
conv_std_logic_vector(25452,AMPL_WIDTH),
conv_std_logic_vector(25454,AMPL_WIDTH),
conv_std_logic_vector(25456,AMPL_WIDTH),
conv_std_logic_vector(25458,AMPL_WIDTH),
conv_std_logic_vector(25460,AMPL_WIDTH),
conv_std_logic_vector(25462,AMPL_WIDTH),
conv_std_logic_vector(25464,AMPL_WIDTH),
conv_std_logic_vector(25466,AMPL_WIDTH),
conv_std_logic_vector(25468,AMPL_WIDTH),
conv_std_logic_vector(25470,AMPL_WIDTH),
conv_std_logic_vector(25472,AMPL_WIDTH),
conv_std_logic_vector(25474,AMPL_WIDTH),
conv_std_logic_vector(25476,AMPL_WIDTH),
conv_std_logic_vector(25478,AMPL_WIDTH),
conv_std_logic_vector(25480,AMPL_WIDTH),
conv_std_logic_vector(25482,AMPL_WIDTH),
conv_std_logic_vector(25484,AMPL_WIDTH),
conv_std_logic_vector(25486,AMPL_WIDTH),
conv_std_logic_vector(25488,AMPL_WIDTH),
conv_std_logic_vector(25490,AMPL_WIDTH),
conv_std_logic_vector(25492,AMPL_WIDTH),
conv_std_logic_vector(25494,AMPL_WIDTH),
conv_std_logic_vector(25496,AMPL_WIDTH),
conv_std_logic_vector(25498,AMPL_WIDTH),
conv_std_logic_vector(25500,AMPL_WIDTH),
conv_std_logic_vector(25502,AMPL_WIDTH),
conv_std_logic_vector(25504,AMPL_WIDTH),
conv_std_logic_vector(25506,AMPL_WIDTH),
conv_std_logic_vector(25508,AMPL_WIDTH),
conv_std_logic_vector(25510,AMPL_WIDTH),
conv_std_logic_vector(25512,AMPL_WIDTH),
conv_std_logic_vector(25514,AMPL_WIDTH),
conv_std_logic_vector(25516,AMPL_WIDTH),
conv_std_logic_vector(25518,AMPL_WIDTH),
conv_std_logic_vector(25519,AMPL_WIDTH),
conv_std_logic_vector(25521,AMPL_WIDTH),
conv_std_logic_vector(25523,AMPL_WIDTH),
conv_std_logic_vector(25525,AMPL_WIDTH),
conv_std_logic_vector(25527,AMPL_WIDTH),
conv_std_logic_vector(25529,AMPL_WIDTH),
conv_std_logic_vector(25531,AMPL_WIDTH),
conv_std_logic_vector(25533,AMPL_WIDTH),
conv_std_logic_vector(25535,AMPL_WIDTH),
conv_std_logic_vector(25537,AMPL_WIDTH),
conv_std_logic_vector(25539,AMPL_WIDTH),
conv_std_logic_vector(25541,AMPL_WIDTH),
conv_std_logic_vector(25543,AMPL_WIDTH),
conv_std_logic_vector(25545,AMPL_WIDTH),
conv_std_logic_vector(25547,AMPL_WIDTH),
conv_std_logic_vector(25549,AMPL_WIDTH),
conv_std_logic_vector(25551,AMPL_WIDTH),
conv_std_logic_vector(25553,AMPL_WIDTH),
conv_std_logic_vector(25555,AMPL_WIDTH),
conv_std_logic_vector(25557,AMPL_WIDTH),
conv_std_logic_vector(25559,AMPL_WIDTH),
conv_std_logic_vector(25561,AMPL_WIDTH),
conv_std_logic_vector(25563,AMPL_WIDTH),
conv_std_logic_vector(25565,AMPL_WIDTH),
conv_std_logic_vector(25567,AMPL_WIDTH),
conv_std_logic_vector(25569,AMPL_WIDTH),
conv_std_logic_vector(25571,AMPL_WIDTH),
conv_std_logic_vector(25573,AMPL_WIDTH),
conv_std_logic_vector(25575,AMPL_WIDTH),
conv_std_logic_vector(25577,AMPL_WIDTH),
conv_std_logic_vector(25578,AMPL_WIDTH),
conv_std_logic_vector(25580,AMPL_WIDTH),
conv_std_logic_vector(25582,AMPL_WIDTH),
conv_std_logic_vector(25584,AMPL_WIDTH),
conv_std_logic_vector(25586,AMPL_WIDTH),
conv_std_logic_vector(25588,AMPL_WIDTH),
conv_std_logic_vector(25590,AMPL_WIDTH),
conv_std_logic_vector(25592,AMPL_WIDTH),
conv_std_logic_vector(25594,AMPL_WIDTH),
conv_std_logic_vector(25596,AMPL_WIDTH),
conv_std_logic_vector(25598,AMPL_WIDTH),
conv_std_logic_vector(25600,AMPL_WIDTH),
conv_std_logic_vector(25602,AMPL_WIDTH),
conv_std_logic_vector(25604,AMPL_WIDTH),
conv_std_logic_vector(25606,AMPL_WIDTH),
conv_std_logic_vector(25608,AMPL_WIDTH),
conv_std_logic_vector(25610,AMPL_WIDTH),
conv_std_logic_vector(25612,AMPL_WIDTH),
conv_std_logic_vector(25614,AMPL_WIDTH),
conv_std_logic_vector(25616,AMPL_WIDTH),
conv_std_logic_vector(25618,AMPL_WIDTH),
conv_std_logic_vector(25620,AMPL_WIDTH),
conv_std_logic_vector(25622,AMPL_WIDTH),
conv_std_logic_vector(25624,AMPL_WIDTH),
conv_std_logic_vector(25626,AMPL_WIDTH),
conv_std_logic_vector(25628,AMPL_WIDTH),
conv_std_logic_vector(25629,AMPL_WIDTH),
conv_std_logic_vector(25631,AMPL_WIDTH),
conv_std_logic_vector(25633,AMPL_WIDTH),
conv_std_logic_vector(25635,AMPL_WIDTH),
conv_std_logic_vector(25637,AMPL_WIDTH),
conv_std_logic_vector(25639,AMPL_WIDTH),
conv_std_logic_vector(25641,AMPL_WIDTH),
conv_std_logic_vector(25643,AMPL_WIDTH),
conv_std_logic_vector(25645,AMPL_WIDTH),
conv_std_logic_vector(25647,AMPL_WIDTH),
conv_std_logic_vector(25649,AMPL_WIDTH),
conv_std_logic_vector(25651,AMPL_WIDTH),
conv_std_logic_vector(25653,AMPL_WIDTH),
conv_std_logic_vector(25655,AMPL_WIDTH),
conv_std_logic_vector(25657,AMPL_WIDTH),
conv_std_logic_vector(25659,AMPL_WIDTH),
conv_std_logic_vector(25661,AMPL_WIDTH),
conv_std_logic_vector(25663,AMPL_WIDTH),
conv_std_logic_vector(25665,AMPL_WIDTH),
conv_std_logic_vector(25667,AMPL_WIDTH),
conv_std_logic_vector(25669,AMPL_WIDTH),
conv_std_logic_vector(25671,AMPL_WIDTH),
conv_std_logic_vector(25672,AMPL_WIDTH),
conv_std_logic_vector(25674,AMPL_WIDTH),
conv_std_logic_vector(25676,AMPL_WIDTH),
conv_std_logic_vector(25678,AMPL_WIDTH),
conv_std_logic_vector(25680,AMPL_WIDTH),
conv_std_logic_vector(25682,AMPL_WIDTH),
conv_std_logic_vector(25684,AMPL_WIDTH),
conv_std_logic_vector(25686,AMPL_WIDTH),
conv_std_logic_vector(25688,AMPL_WIDTH),
conv_std_logic_vector(25690,AMPL_WIDTH),
conv_std_logic_vector(25692,AMPL_WIDTH),
conv_std_logic_vector(25694,AMPL_WIDTH),
conv_std_logic_vector(25696,AMPL_WIDTH),
conv_std_logic_vector(25698,AMPL_WIDTH),
conv_std_logic_vector(25700,AMPL_WIDTH),
conv_std_logic_vector(25702,AMPL_WIDTH),
conv_std_logic_vector(25704,AMPL_WIDTH),
conv_std_logic_vector(25706,AMPL_WIDTH),
conv_std_logic_vector(25708,AMPL_WIDTH),
conv_std_logic_vector(25710,AMPL_WIDTH),
conv_std_logic_vector(25711,AMPL_WIDTH),
conv_std_logic_vector(25713,AMPL_WIDTH),
conv_std_logic_vector(25715,AMPL_WIDTH),
conv_std_logic_vector(25717,AMPL_WIDTH),
conv_std_logic_vector(25719,AMPL_WIDTH),
conv_std_logic_vector(25721,AMPL_WIDTH),
conv_std_logic_vector(25723,AMPL_WIDTH),
conv_std_logic_vector(25725,AMPL_WIDTH),
conv_std_logic_vector(25727,AMPL_WIDTH),
conv_std_logic_vector(25729,AMPL_WIDTH),
conv_std_logic_vector(25731,AMPL_WIDTH),
conv_std_logic_vector(25733,AMPL_WIDTH),
conv_std_logic_vector(25735,AMPL_WIDTH),
conv_std_logic_vector(25737,AMPL_WIDTH),
conv_std_logic_vector(25739,AMPL_WIDTH),
conv_std_logic_vector(25741,AMPL_WIDTH),
conv_std_logic_vector(25743,AMPL_WIDTH),
conv_std_logic_vector(25745,AMPL_WIDTH),
conv_std_logic_vector(25746,AMPL_WIDTH),
conv_std_logic_vector(25748,AMPL_WIDTH),
conv_std_logic_vector(25750,AMPL_WIDTH),
conv_std_logic_vector(25752,AMPL_WIDTH),
conv_std_logic_vector(25754,AMPL_WIDTH),
conv_std_logic_vector(25756,AMPL_WIDTH),
conv_std_logic_vector(25758,AMPL_WIDTH),
conv_std_logic_vector(25760,AMPL_WIDTH),
conv_std_logic_vector(25762,AMPL_WIDTH),
conv_std_logic_vector(25764,AMPL_WIDTH),
conv_std_logic_vector(25766,AMPL_WIDTH),
conv_std_logic_vector(25768,AMPL_WIDTH),
conv_std_logic_vector(25770,AMPL_WIDTH),
conv_std_logic_vector(25772,AMPL_WIDTH),
conv_std_logic_vector(25774,AMPL_WIDTH),
conv_std_logic_vector(25776,AMPL_WIDTH),
conv_std_logic_vector(25778,AMPL_WIDTH),
conv_std_logic_vector(25779,AMPL_WIDTH),
conv_std_logic_vector(25781,AMPL_WIDTH),
conv_std_logic_vector(25783,AMPL_WIDTH),
conv_std_logic_vector(25785,AMPL_WIDTH),
conv_std_logic_vector(25787,AMPL_WIDTH),
conv_std_logic_vector(25789,AMPL_WIDTH),
conv_std_logic_vector(25791,AMPL_WIDTH),
conv_std_logic_vector(25793,AMPL_WIDTH),
conv_std_logic_vector(25795,AMPL_WIDTH),
conv_std_logic_vector(25797,AMPL_WIDTH),
conv_std_logic_vector(25799,AMPL_WIDTH),
conv_std_logic_vector(25801,AMPL_WIDTH),
conv_std_logic_vector(25803,AMPL_WIDTH),
conv_std_logic_vector(25805,AMPL_WIDTH),
conv_std_logic_vector(25807,AMPL_WIDTH),
conv_std_logic_vector(25809,AMPL_WIDTH),
conv_std_logic_vector(25810,AMPL_WIDTH),
conv_std_logic_vector(25812,AMPL_WIDTH),
conv_std_logic_vector(25814,AMPL_WIDTH),
conv_std_logic_vector(25816,AMPL_WIDTH),
conv_std_logic_vector(25818,AMPL_WIDTH),
conv_std_logic_vector(25820,AMPL_WIDTH),
conv_std_logic_vector(25822,AMPL_WIDTH),
conv_std_logic_vector(25824,AMPL_WIDTH),
conv_std_logic_vector(25826,AMPL_WIDTH),
conv_std_logic_vector(25828,AMPL_WIDTH),
conv_std_logic_vector(25830,AMPL_WIDTH),
conv_std_logic_vector(25832,AMPL_WIDTH),
conv_std_logic_vector(25834,AMPL_WIDTH),
conv_std_logic_vector(25836,AMPL_WIDTH),
conv_std_logic_vector(25838,AMPL_WIDTH),
conv_std_logic_vector(25839,AMPL_WIDTH),
conv_std_logic_vector(25841,AMPL_WIDTH),
conv_std_logic_vector(25843,AMPL_WIDTH),
conv_std_logic_vector(25845,AMPL_WIDTH),
conv_std_logic_vector(25847,AMPL_WIDTH),
conv_std_logic_vector(25849,AMPL_WIDTH),
conv_std_logic_vector(25851,AMPL_WIDTH),
conv_std_logic_vector(25853,AMPL_WIDTH),
conv_std_logic_vector(25855,AMPL_WIDTH),
conv_std_logic_vector(25857,AMPL_WIDTH),
conv_std_logic_vector(25859,AMPL_WIDTH),
conv_std_logic_vector(25861,AMPL_WIDTH),
conv_std_logic_vector(25863,AMPL_WIDTH),
conv_std_logic_vector(25865,AMPL_WIDTH),
conv_std_logic_vector(25866,AMPL_WIDTH),
conv_std_logic_vector(25868,AMPL_WIDTH),
conv_std_logic_vector(25870,AMPL_WIDTH),
conv_std_logic_vector(25872,AMPL_WIDTH),
conv_std_logic_vector(25874,AMPL_WIDTH),
conv_std_logic_vector(25876,AMPL_WIDTH),
conv_std_logic_vector(25878,AMPL_WIDTH),
conv_std_logic_vector(25880,AMPL_WIDTH),
conv_std_logic_vector(25882,AMPL_WIDTH),
conv_std_logic_vector(25884,AMPL_WIDTH),
conv_std_logic_vector(25886,AMPL_WIDTH),
conv_std_logic_vector(25888,AMPL_WIDTH),
conv_std_logic_vector(25890,AMPL_WIDTH),
conv_std_logic_vector(25892,AMPL_WIDTH),
conv_std_logic_vector(25893,AMPL_WIDTH),
conv_std_logic_vector(25895,AMPL_WIDTH),
conv_std_logic_vector(25897,AMPL_WIDTH),
conv_std_logic_vector(25899,AMPL_WIDTH),
conv_std_logic_vector(25901,AMPL_WIDTH),
conv_std_logic_vector(25903,AMPL_WIDTH),
conv_std_logic_vector(25905,AMPL_WIDTH),
conv_std_logic_vector(25907,AMPL_WIDTH),
conv_std_logic_vector(25909,AMPL_WIDTH),
conv_std_logic_vector(25911,AMPL_WIDTH),
conv_std_logic_vector(25913,AMPL_WIDTH),
conv_std_logic_vector(25915,AMPL_WIDTH),
conv_std_logic_vector(25917,AMPL_WIDTH),
conv_std_logic_vector(25918,AMPL_WIDTH),
conv_std_logic_vector(25920,AMPL_WIDTH),
conv_std_logic_vector(25922,AMPL_WIDTH),
conv_std_logic_vector(25924,AMPL_WIDTH),
conv_std_logic_vector(25926,AMPL_WIDTH),
conv_std_logic_vector(25928,AMPL_WIDTH),
conv_std_logic_vector(25930,AMPL_WIDTH),
conv_std_logic_vector(25932,AMPL_WIDTH),
conv_std_logic_vector(25934,AMPL_WIDTH),
conv_std_logic_vector(25936,AMPL_WIDTH),
conv_std_logic_vector(25938,AMPL_WIDTH),
conv_std_logic_vector(25940,AMPL_WIDTH),
conv_std_logic_vector(25942,AMPL_WIDTH),
conv_std_logic_vector(25943,AMPL_WIDTH),
conv_std_logic_vector(25945,AMPL_WIDTH),
conv_std_logic_vector(25947,AMPL_WIDTH),
conv_std_logic_vector(25949,AMPL_WIDTH),
conv_std_logic_vector(25951,AMPL_WIDTH),
conv_std_logic_vector(25953,AMPL_WIDTH),
conv_std_logic_vector(25955,AMPL_WIDTH),
conv_std_logic_vector(25957,AMPL_WIDTH),
conv_std_logic_vector(25959,AMPL_WIDTH),
conv_std_logic_vector(25961,AMPL_WIDTH),
conv_std_logic_vector(25963,AMPL_WIDTH),
conv_std_logic_vector(25965,AMPL_WIDTH),
conv_std_logic_vector(25966,AMPL_WIDTH),
conv_std_logic_vector(25968,AMPL_WIDTH),
conv_std_logic_vector(25970,AMPL_WIDTH),
conv_std_logic_vector(25972,AMPL_WIDTH),
conv_std_logic_vector(25974,AMPL_WIDTH),
conv_std_logic_vector(25976,AMPL_WIDTH),
conv_std_logic_vector(25978,AMPL_WIDTH),
conv_std_logic_vector(25980,AMPL_WIDTH),
conv_std_logic_vector(25982,AMPL_WIDTH),
conv_std_logic_vector(25984,AMPL_WIDTH),
conv_std_logic_vector(25986,AMPL_WIDTH),
conv_std_logic_vector(25988,AMPL_WIDTH),
conv_std_logic_vector(25989,AMPL_WIDTH),
conv_std_logic_vector(25991,AMPL_WIDTH),
conv_std_logic_vector(25993,AMPL_WIDTH),
conv_std_logic_vector(25995,AMPL_WIDTH),
conv_std_logic_vector(25997,AMPL_WIDTH),
conv_std_logic_vector(25999,AMPL_WIDTH),
conv_std_logic_vector(26001,AMPL_WIDTH),
conv_std_logic_vector(26003,AMPL_WIDTH),
conv_std_logic_vector(26005,AMPL_WIDTH),
conv_std_logic_vector(26007,AMPL_WIDTH),
conv_std_logic_vector(26009,AMPL_WIDTH),
conv_std_logic_vector(26010,AMPL_WIDTH),
conv_std_logic_vector(26012,AMPL_WIDTH),
conv_std_logic_vector(26014,AMPL_WIDTH),
conv_std_logic_vector(26016,AMPL_WIDTH),
conv_std_logic_vector(26018,AMPL_WIDTH),
conv_std_logic_vector(26020,AMPL_WIDTH),
conv_std_logic_vector(26022,AMPL_WIDTH),
conv_std_logic_vector(26024,AMPL_WIDTH),
conv_std_logic_vector(26026,AMPL_WIDTH),
conv_std_logic_vector(26028,AMPL_WIDTH),
conv_std_logic_vector(26030,AMPL_WIDTH),
conv_std_logic_vector(26031,AMPL_WIDTH),
conv_std_logic_vector(26033,AMPL_WIDTH),
conv_std_logic_vector(26035,AMPL_WIDTH),
conv_std_logic_vector(26037,AMPL_WIDTH),
conv_std_logic_vector(26039,AMPL_WIDTH),
conv_std_logic_vector(26041,AMPL_WIDTH),
conv_std_logic_vector(26043,AMPL_WIDTH),
conv_std_logic_vector(26045,AMPL_WIDTH),
conv_std_logic_vector(26047,AMPL_WIDTH),
conv_std_logic_vector(26049,AMPL_WIDTH),
conv_std_logic_vector(26051,AMPL_WIDTH),
conv_std_logic_vector(26052,AMPL_WIDTH),
conv_std_logic_vector(26054,AMPL_WIDTH),
conv_std_logic_vector(26056,AMPL_WIDTH),
conv_std_logic_vector(26058,AMPL_WIDTH),
conv_std_logic_vector(26060,AMPL_WIDTH),
conv_std_logic_vector(26062,AMPL_WIDTH),
conv_std_logic_vector(26064,AMPL_WIDTH),
conv_std_logic_vector(26066,AMPL_WIDTH),
conv_std_logic_vector(26068,AMPL_WIDTH),
conv_std_logic_vector(26070,AMPL_WIDTH),
conv_std_logic_vector(26071,AMPL_WIDTH),
conv_std_logic_vector(26073,AMPL_WIDTH),
conv_std_logic_vector(26075,AMPL_WIDTH),
conv_std_logic_vector(26077,AMPL_WIDTH),
conv_std_logic_vector(26079,AMPL_WIDTH),
conv_std_logic_vector(26081,AMPL_WIDTH),
conv_std_logic_vector(26083,AMPL_WIDTH),
conv_std_logic_vector(26085,AMPL_WIDTH),
conv_std_logic_vector(26087,AMPL_WIDTH),
conv_std_logic_vector(26089,AMPL_WIDTH),
conv_std_logic_vector(26090,AMPL_WIDTH),
conv_std_logic_vector(26092,AMPL_WIDTH),
conv_std_logic_vector(26094,AMPL_WIDTH),
conv_std_logic_vector(26096,AMPL_WIDTH),
conv_std_logic_vector(26098,AMPL_WIDTH),
conv_std_logic_vector(26100,AMPL_WIDTH),
conv_std_logic_vector(26102,AMPL_WIDTH),
conv_std_logic_vector(26104,AMPL_WIDTH),
conv_std_logic_vector(26106,AMPL_WIDTH),
conv_std_logic_vector(26108,AMPL_WIDTH),
conv_std_logic_vector(26109,AMPL_WIDTH),
conv_std_logic_vector(26111,AMPL_WIDTH),
conv_std_logic_vector(26113,AMPL_WIDTH),
conv_std_logic_vector(26115,AMPL_WIDTH),
conv_std_logic_vector(26117,AMPL_WIDTH),
conv_std_logic_vector(26119,AMPL_WIDTH),
conv_std_logic_vector(26121,AMPL_WIDTH),
conv_std_logic_vector(26123,AMPL_WIDTH),
conv_std_logic_vector(26125,AMPL_WIDTH),
conv_std_logic_vector(26127,AMPL_WIDTH),
conv_std_logic_vector(26128,AMPL_WIDTH),
conv_std_logic_vector(26130,AMPL_WIDTH),
conv_std_logic_vector(26132,AMPL_WIDTH),
conv_std_logic_vector(26134,AMPL_WIDTH),
conv_std_logic_vector(26136,AMPL_WIDTH),
conv_std_logic_vector(26138,AMPL_WIDTH),
conv_std_logic_vector(26140,AMPL_WIDTH),
conv_std_logic_vector(26142,AMPL_WIDTH),
conv_std_logic_vector(26144,AMPL_WIDTH),
conv_std_logic_vector(26146,AMPL_WIDTH),
conv_std_logic_vector(26147,AMPL_WIDTH),
conv_std_logic_vector(26149,AMPL_WIDTH),
conv_std_logic_vector(26151,AMPL_WIDTH),
conv_std_logic_vector(26153,AMPL_WIDTH),
conv_std_logic_vector(26155,AMPL_WIDTH),
conv_std_logic_vector(26157,AMPL_WIDTH),
conv_std_logic_vector(26159,AMPL_WIDTH),
conv_std_logic_vector(26161,AMPL_WIDTH),
conv_std_logic_vector(26163,AMPL_WIDTH),
conv_std_logic_vector(26164,AMPL_WIDTH),
conv_std_logic_vector(26166,AMPL_WIDTH),
conv_std_logic_vector(26168,AMPL_WIDTH),
conv_std_logic_vector(26170,AMPL_WIDTH),
conv_std_logic_vector(26172,AMPL_WIDTH),
conv_std_logic_vector(26174,AMPL_WIDTH),
conv_std_logic_vector(26176,AMPL_WIDTH),
conv_std_logic_vector(26178,AMPL_WIDTH),
conv_std_logic_vector(26180,AMPL_WIDTH),
conv_std_logic_vector(26181,AMPL_WIDTH),
conv_std_logic_vector(26183,AMPL_WIDTH),
conv_std_logic_vector(26185,AMPL_WIDTH),
conv_std_logic_vector(26187,AMPL_WIDTH),
conv_std_logic_vector(26189,AMPL_WIDTH),
conv_std_logic_vector(26191,AMPL_WIDTH),
conv_std_logic_vector(26193,AMPL_WIDTH),
conv_std_logic_vector(26195,AMPL_WIDTH),
conv_std_logic_vector(26197,AMPL_WIDTH),
conv_std_logic_vector(26198,AMPL_WIDTH),
conv_std_logic_vector(26200,AMPL_WIDTH),
conv_std_logic_vector(26202,AMPL_WIDTH),
conv_std_logic_vector(26204,AMPL_WIDTH),
conv_std_logic_vector(26206,AMPL_WIDTH),
conv_std_logic_vector(26208,AMPL_WIDTH),
conv_std_logic_vector(26210,AMPL_WIDTH),
conv_std_logic_vector(26212,AMPL_WIDTH),
conv_std_logic_vector(26214,AMPL_WIDTH),
conv_std_logic_vector(26215,AMPL_WIDTH),
conv_std_logic_vector(26217,AMPL_WIDTH),
conv_std_logic_vector(26219,AMPL_WIDTH),
conv_std_logic_vector(26221,AMPL_WIDTH),
conv_std_logic_vector(26223,AMPL_WIDTH),
conv_std_logic_vector(26225,AMPL_WIDTH),
conv_std_logic_vector(26227,AMPL_WIDTH),
conv_std_logic_vector(26229,AMPL_WIDTH),
conv_std_logic_vector(26230,AMPL_WIDTH),
conv_std_logic_vector(26232,AMPL_WIDTH),
conv_std_logic_vector(26234,AMPL_WIDTH),
conv_std_logic_vector(26236,AMPL_WIDTH),
conv_std_logic_vector(26238,AMPL_WIDTH),
conv_std_logic_vector(26240,AMPL_WIDTH),
conv_std_logic_vector(26242,AMPL_WIDTH),
conv_std_logic_vector(26244,AMPL_WIDTH),
conv_std_logic_vector(26246,AMPL_WIDTH),
conv_std_logic_vector(26247,AMPL_WIDTH),
conv_std_logic_vector(26249,AMPL_WIDTH),
conv_std_logic_vector(26251,AMPL_WIDTH),
conv_std_logic_vector(26253,AMPL_WIDTH),
conv_std_logic_vector(26255,AMPL_WIDTH),
conv_std_logic_vector(26257,AMPL_WIDTH),
conv_std_logic_vector(26259,AMPL_WIDTH),
conv_std_logic_vector(26261,AMPL_WIDTH),
conv_std_logic_vector(26262,AMPL_WIDTH),
conv_std_logic_vector(26264,AMPL_WIDTH),
conv_std_logic_vector(26266,AMPL_WIDTH),
conv_std_logic_vector(26268,AMPL_WIDTH),
conv_std_logic_vector(26270,AMPL_WIDTH),
conv_std_logic_vector(26272,AMPL_WIDTH),
conv_std_logic_vector(26274,AMPL_WIDTH),
conv_std_logic_vector(26276,AMPL_WIDTH),
conv_std_logic_vector(26277,AMPL_WIDTH),
conv_std_logic_vector(26279,AMPL_WIDTH),
conv_std_logic_vector(26281,AMPL_WIDTH),
conv_std_logic_vector(26283,AMPL_WIDTH),
conv_std_logic_vector(26285,AMPL_WIDTH),
conv_std_logic_vector(26287,AMPL_WIDTH),
conv_std_logic_vector(26289,AMPL_WIDTH),
conv_std_logic_vector(26291,AMPL_WIDTH),
conv_std_logic_vector(26292,AMPL_WIDTH),
conv_std_logic_vector(26294,AMPL_WIDTH),
conv_std_logic_vector(26296,AMPL_WIDTH),
conv_std_logic_vector(26298,AMPL_WIDTH),
conv_std_logic_vector(26300,AMPL_WIDTH),
conv_std_logic_vector(26302,AMPL_WIDTH),
conv_std_logic_vector(26304,AMPL_WIDTH),
conv_std_logic_vector(26306,AMPL_WIDTH),
conv_std_logic_vector(26307,AMPL_WIDTH),
conv_std_logic_vector(26309,AMPL_WIDTH),
conv_std_logic_vector(26311,AMPL_WIDTH),
conv_std_logic_vector(26313,AMPL_WIDTH),
conv_std_logic_vector(26315,AMPL_WIDTH),
conv_std_logic_vector(26317,AMPL_WIDTH),
conv_std_logic_vector(26319,AMPL_WIDTH),
conv_std_logic_vector(26321,AMPL_WIDTH),
conv_std_logic_vector(26322,AMPL_WIDTH),
conv_std_logic_vector(26324,AMPL_WIDTH),
conv_std_logic_vector(26326,AMPL_WIDTH),
conv_std_logic_vector(26328,AMPL_WIDTH),
conv_std_logic_vector(26330,AMPL_WIDTH),
conv_std_logic_vector(26332,AMPL_WIDTH),
conv_std_logic_vector(26334,AMPL_WIDTH),
conv_std_logic_vector(26336,AMPL_WIDTH),
conv_std_logic_vector(26337,AMPL_WIDTH),
conv_std_logic_vector(26339,AMPL_WIDTH),
conv_std_logic_vector(26341,AMPL_WIDTH),
conv_std_logic_vector(26343,AMPL_WIDTH),
conv_std_logic_vector(26345,AMPL_WIDTH),
conv_std_logic_vector(26347,AMPL_WIDTH),
conv_std_logic_vector(26349,AMPL_WIDTH),
conv_std_logic_vector(26350,AMPL_WIDTH),
conv_std_logic_vector(26352,AMPL_WIDTH),
conv_std_logic_vector(26354,AMPL_WIDTH),
conv_std_logic_vector(26356,AMPL_WIDTH),
conv_std_logic_vector(26358,AMPL_WIDTH),
conv_std_logic_vector(26360,AMPL_WIDTH),
conv_std_logic_vector(26362,AMPL_WIDTH),
conv_std_logic_vector(26364,AMPL_WIDTH),
conv_std_logic_vector(26365,AMPL_WIDTH),
conv_std_logic_vector(26367,AMPL_WIDTH),
conv_std_logic_vector(26369,AMPL_WIDTH),
conv_std_logic_vector(26371,AMPL_WIDTH),
conv_std_logic_vector(26373,AMPL_WIDTH),
conv_std_logic_vector(26375,AMPL_WIDTH),
conv_std_logic_vector(26377,AMPL_WIDTH),
conv_std_logic_vector(26378,AMPL_WIDTH),
conv_std_logic_vector(26380,AMPL_WIDTH),
conv_std_logic_vector(26382,AMPL_WIDTH),
conv_std_logic_vector(26384,AMPL_WIDTH),
conv_std_logic_vector(26386,AMPL_WIDTH),
conv_std_logic_vector(26388,AMPL_WIDTH),
conv_std_logic_vector(26390,AMPL_WIDTH),
conv_std_logic_vector(26392,AMPL_WIDTH),
conv_std_logic_vector(26393,AMPL_WIDTH),
conv_std_logic_vector(26395,AMPL_WIDTH),
conv_std_logic_vector(26397,AMPL_WIDTH),
conv_std_logic_vector(26399,AMPL_WIDTH),
conv_std_logic_vector(26401,AMPL_WIDTH),
conv_std_logic_vector(26403,AMPL_WIDTH),
conv_std_logic_vector(26405,AMPL_WIDTH),
conv_std_logic_vector(26406,AMPL_WIDTH),
conv_std_logic_vector(26408,AMPL_WIDTH),
conv_std_logic_vector(26410,AMPL_WIDTH),
conv_std_logic_vector(26412,AMPL_WIDTH),
conv_std_logic_vector(26414,AMPL_WIDTH),
conv_std_logic_vector(26416,AMPL_WIDTH),
conv_std_logic_vector(26418,AMPL_WIDTH),
conv_std_logic_vector(26419,AMPL_WIDTH),
conv_std_logic_vector(26421,AMPL_WIDTH),
conv_std_logic_vector(26423,AMPL_WIDTH),
conv_std_logic_vector(26425,AMPL_WIDTH),
conv_std_logic_vector(26427,AMPL_WIDTH),
conv_std_logic_vector(26429,AMPL_WIDTH),
conv_std_logic_vector(26431,AMPL_WIDTH),
conv_std_logic_vector(26432,AMPL_WIDTH),
conv_std_logic_vector(26434,AMPL_WIDTH),
conv_std_logic_vector(26436,AMPL_WIDTH),
conv_std_logic_vector(26438,AMPL_WIDTH),
conv_std_logic_vector(26440,AMPL_WIDTH),
conv_std_logic_vector(26442,AMPL_WIDTH),
conv_std_logic_vector(26444,AMPL_WIDTH),
conv_std_logic_vector(26445,AMPL_WIDTH),
conv_std_logic_vector(26447,AMPL_WIDTH),
conv_std_logic_vector(26449,AMPL_WIDTH),
conv_std_logic_vector(26451,AMPL_WIDTH),
conv_std_logic_vector(26453,AMPL_WIDTH),
conv_std_logic_vector(26455,AMPL_WIDTH),
conv_std_logic_vector(26457,AMPL_WIDTH),
conv_std_logic_vector(26458,AMPL_WIDTH),
conv_std_logic_vector(26460,AMPL_WIDTH),
conv_std_logic_vector(26462,AMPL_WIDTH),
conv_std_logic_vector(26464,AMPL_WIDTH),
conv_std_logic_vector(26466,AMPL_WIDTH),
conv_std_logic_vector(26468,AMPL_WIDTH),
conv_std_logic_vector(26469,AMPL_WIDTH),
conv_std_logic_vector(26471,AMPL_WIDTH),
conv_std_logic_vector(26473,AMPL_WIDTH),
conv_std_logic_vector(26475,AMPL_WIDTH),
conv_std_logic_vector(26477,AMPL_WIDTH),
conv_std_logic_vector(26479,AMPL_WIDTH),
conv_std_logic_vector(26481,AMPL_WIDTH),
conv_std_logic_vector(26482,AMPL_WIDTH),
conv_std_logic_vector(26484,AMPL_WIDTH),
conv_std_logic_vector(26486,AMPL_WIDTH),
conv_std_logic_vector(26488,AMPL_WIDTH),
conv_std_logic_vector(26490,AMPL_WIDTH),
conv_std_logic_vector(26492,AMPL_WIDTH),
conv_std_logic_vector(26494,AMPL_WIDTH),
conv_std_logic_vector(26495,AMPL_WIDTH),
conv_std_logic_vector(26497,AMPL_WIDTH),
conv_std_logic_vector(26499,AMPL_WIDTH),
conv_std_logic_vector(26501,AMPL_WIDTH),
conv_std_logic_vector(26503,AMPL_WIDTH),
conv_std_logic_vector(26505,AMPL_WIDTH),
conv_std_logic_vector(26506,AMPL_WIDTH),
conv_std_logic_vector(26508,AMPL_WIDTH),
conv_std_logic_vector(26510,AMPL_WIDTH),
conv_std_logic_vector(26512,AMPL_WIDTH),
conv_std_logic_vector(26514,AMPL_WIDTH),
conv_std_logic_vector(26516,AMPL_WIDTH),
conv_std_logic_vector(26518,AMPL_WIDTH),
conv_std_logic_vector(26519,AMPL_WIDTH),
conv_std_logic_vector(26521,AMPL_WIDTH),
conv_std_logic_vector(26523,AMPL_WIDTH),
conv_std_logic_vector(26525,AMPL_WIDTH),
conv_std_logic_vector(26527,AMPL_WIDTH),
conv_std_logic_vector(26529,AMPL_WIDTH),
conv_std_logic_vector(26530,AMPL_WIDTH),
conv_std_logic_vector(26532,AMPL_WIDTH),
conv_std_logic_vector(26534,AMPL_WIDTH),
conv_std_logic_vector(26536,AMPL_WIDTH),
conv_std_logic_vector(26538,AMPL_WIDTH),
conv_std_logic_vector(26540,AMPL_WIDTH),
conv_std_logic_vector(26542,AMPL_WIDTH),
conv_std_logic_vector(26543,AMPL_WIDTH),
conv_std_logic_vector(26545,AMPL_WIDTH),
conv_std_logic_vector(26547,AMPL_WIDTH),
conv_std_logic_vector(26549,AMPL_WIDTH),
conv_std_logic_vector(26551,AMPL_WIDTH),
conv_std_logic_vector(26553,AMPL_WIDTH),
conv_std_logic_vector(26554,AMPL_WIDTH),
conv_std_logic_vector(26556,AMPL_WIDTH),
conv_std_logic_vector(26558,AMPL_WIDTH),
conv_std_logic_vector(26560,AMPL_WIDTH),
conv_std_logic_vector(26562,AMPL_WIDTH),
conv_std_logic_vector(26564,AMPL_WIDTH),
conv_std_logic_vector(26565,AMPL_WIDTH),
conv_std_logic_vector(26567,AMPL_WIDTH),
conv_std_logic_vector(26569,AMPL_WIDTH),
conv_std_logic_vector(26571,AMPL_WIDTH),
conv_std_logic_vector(26573,AMPL_WIDTH),
conv_std_logic_vector(26575,AMPL_WIDTH),
conv_std_logic_vector(26576,AMPL_WIDTH),
conv_std_logic_vector(26578,AMPL_WIDTH),
conv_std_logic_vector(26580,AMPL_WIDTH),
conv_std_logic_vector(26582,AMPL_WIDTH),
conv_std_logic_vector(26584,AMPL_WIDTH),
conv_std_logic_vector(26586,AMPL_WIDTH),
conv_std_logic_vector(26588,AMPL_WIDTH),
conv_std_logic_vector(26589,AMPL_WIDTH),
conv_std_logic_vector(26591,AMPL_WIDTH),
conv_std_logic_vector(26593,AMPL_WIDTH),
conv_std_logic_vector(26595,AMPL_WIDTH),
conv_std_logic_vector(26597,AMPL_WIDTH),
conv_std_logic_vector(26599,AMPL_WIDTH),
conv_std_logic_vector(26600,AMPL_WIDTH),
conv_std_logic_vector(26602,AMPL_WIDTH),
conv_std_logic_vector(26604,AMPL_WIDTH),
conv_std_logic_vector(26606,AMPL_WIDTH),
conv_std_logic_vector(26608,AMPL_WIDTH),
conv_std_logic_vector(26610,AMPL_WIDTH),
conv_std_logic_vector(26611,AMPL_WIDTH),
conv_std_logic_vector(26613,AMPL_WIDTH),
conv_std_logic_vector(26615,AMPL_WIDTH),
conv_std_logic_vector(26617,AMPL_WIDTH),
conv_std_logic_vector(26619,AMPL_WIDTH),
conv_std_logic_vector(26621,AMPL_WIDTH),
conv_std_logic_vector(26622,AMPL_WIDTH),
conv_std_logic_vector(26624,AMPL_WIDTH),
conv_std_logic_vector(26626,AMPL_WIDTH),
conv_std_logic_vector(26628,AMPL_WIDTH),
conv_std_logic_vector(26630,AMPL_WIDTH),
conv_std_logic_vector(26631,AMPL_WIDTH),
conv_std_logic_vector(26633,AMPL_WIDTH),
conv_std_logic_vector(26635,AMPL_WIDTH),
conv_std_logic_vector(26637,AMPL_WIDTH),
conv_std_logic_vector(26639,AMPL_WIDTH),
conv_std_logic_vector(26641,AMPL_WIDTH),
conv_std_logic_vector(26642,AMPL_WIDTH),
conv_std_logic_vector(26644,AMPL_WIDTH),
conv_std_logic_vector(26646,AMPL_WIDTH),
conv_std_logic_vector(26648,AMPL_WIDTH),
conv_std_logic_vector(26650,AMPL_WIDTH),
conv_std_logic_vector(26652,AMPL_WIDTH),
conv_std_logic_vector(26653,AMPL_WIDTH),
conv_std_logic_vector(26655,AMPL_WIDTH),
conv_std_logic_vector(26657,AMPL_WIDTH),
conv_std_logic_vector(26659,AMPL_WIDTH),
conv_std_logic_vector(26661,AMPL_WIDTH),
conv_std_logic_vector(26663,AMPL_WIDTH),
conv_std_logic_vector(26664,AMPL_WIDTH),
conv_std_logic_vector(26666,AMPL_WIDTH),
conv_std_logic_vector(26668,AMPL_WIDTH),
conv_std_logic_vector(26670,AMPL_WIDTH),
conv_std_logic_vector(26672,AMPL_WIDTH),
conv_std_logic_vector(26674,AMPL_WIDTH),
conv_std_logic_vector(26675,AMPL_WIDTH),
conv_std_logic_vector(26677,AMPL_WIDTH),
conv_std_logic_vector(26679,AMPL_WIDTH),
conv_std_logic_vector(26681,AMPL_WIDTH),
conv_std_logic_vector(26683,AMPL_WIDTH),
conv_std_logic_vector(26684,AMPL_WIDTH),
conv_std_logic_vector(26686,AMPL_WIDTH),
conv_std_logic_vector(26688,AMPL_WIDTH),
conv_std_logic_vector(26690,AMPL_WIDTH),
conv_std_logic_vector(26692,AMPL_WIDTH),
conv_std_logic_vector(26694,AMPL_WIDTH),
conv_std_logic_vector(26695,AMPL_WIDTH),
conv_std_logic_vector(26697,AMPL_WIDTH),
conv_std_logic_vector(26699,AMPL_WIDTH),
conv_std_logic_vector(26701,AMPL_WIDTH),
conv_std_logic_vector(26703,AMPL_WIDTH),
conv_std_logic_vector(26705,AMPL_WIDTH),
conv_std_logic_vector(26706,AMPL_WIDTH),
conv_std_logic_vector(26708,AMPL_WIDTH),
conv_std_logic_vector(26710,AMPL_WIDTH),
conv_std_logic_vector(26712,AMPL_WIDTH),
conv_std_logic_vector(26714,AMPL_WIDTH),
conv_std_logic_vector(26715,AMPL_WIDTH),
conv_std_logic_vector(26717,AMPL_WIDTH),
conv_std_logic_vector(26719,AMPL_WIDTH),
conv_std_logic_vector(26721,AMPL_WIDTH),
conv_std_logic_vector(26723,AMPL_WIDTH),
conv_std_logic_vector(26725,AMPL_WIDTH),
conv_std_logic_vector(26726,AMPL_WIDTH),
conv_std_logic_vector(26728,AMPL_WIDTH),
conv_std_logic_vector(26730,AMPL_WIDTH),
conv_std_logic_vector(26732,AMPL_WIDTH),
conv_std_logic_vector(26734,AMPL_WIDTH),
conv_std_logic_vector(26735,AMPL_WIDTH),
conv_std_logic_vector(26737,AMPL_WIDTH),
conv_std_logic_vector(26739,AMPL_WIDTH),
conv_std_logic_vector(26741,AMPL_WIDTH),
conv_std_logic_vector(26743,AMPL_WIDTH),
conv_std_logic_vector(26745,AMPL_WIDTH),
conv_std_logic_vector(26746,AMPL_WIDTH),
conv_std_logic_vector(26748,AMPL_WIDTH),
conv_std_logic_vector(26750,AMPL_WIDTH),
conv_std_logic_vector(26752,AMPL_WIDTH),
conv_std_logic_vector(26754,AMPL_WIDTH),
conv_std_logic_vector(26755,AMPL_WIDTH),
conv_std_logic_vector(26757,AMPL_WIDTH),
conv_std_logic_vector(26759,AMPL_WIDTH),
conv_std_logic_vector(26761,AMPL_WIDTH),
conv_std_logic_vector(26763,AMPL_WIDTH),
conv_std_logic_vector(26764,AMPL_WIDTH),
conv_std_logic_vector(26766,AMPL_WIDTH),
conv_std_logic_vector(26768,AMPL_WIDTH),
conv_std_logic_vector(26770,AMPL_WIDTH),
conv_std_logic_vector(26772,AMPL_WIDTH),
conv_std_logic_vector(26774,AMPL_WIDTH),
conv_std_logic_vector(26775,AMPL_WIDTH),
conv_std_logic_vector(26777,AMPL_WIDTH),
conv_std_logic_vector(26779,AMPL_WIDTH),
conv_std_logic_vector(26781,AMPL_WIDTH),
conv_std_logic_vector(26783,AMPL_WIDTH),
conv_std_logic_vector(26784,AMPL_WIDTH),
conv_std_logic_vector(26786,AMPL_WIDTH),
conv_std_logic_vector(26788,AMPL_WIDTH),
conv_std_logic_vector(26790,AMPL_WIDTH),
conv_std_logic_vector(26792,AMPL_WIDTH),
conv_std_logic_vector(26793,AMPL_WIDTH),
conv_std_logic_vector(26795,AMPL_WIDTH),
conv_std_logic_vector(26797,AMPL_WIDTH),
conv_std_logic_vector(26799,AMPL_WIDTH),
conv_std_logic_vector(26801,AMPL_WIDTH),
conv_std_logic_vector(26802,AMPL_WIDTH),
conv_std_logic_vector(26804,AMPL_WIDTH),
conv_std_logic_vector(26806,AMPL_WIDTH),
conv_std_logic_vector(26808,AMPL_WIDTH),
conv_std_logic_vector(26810,AMPL_WIDTH),
conv_std_logic_vector(26811,AMPL_WIDTH),
conv_std_logic_vector(26813,AMPL_WIDTH),
conv_std_logic_vector(26815,AMPL_WIDTH),
conv_std_logic_vector(26817,AMPL_WIDTH),
conv_std_logic_vector(26819,AMPL_WIDTH),
conv_std_logic_vector(26821,AMPL_WIDTH),
conv_std_logic_vector(26822,AMPL_WIDTH),
conv_std_logic_vector(26824,AMPL_WIDTH),
conv_std_logic_vector(26826,AMPL_WIDTH),
conv_std_logic_vector(26828,AMPL_WIDTH),
conv_std_logic_vector(26830,AMPL_WIDTH),
conv_std_logic_vector(26831,AMPL_WIDTH),
conv_std_logic_vector(26833,AMPL_WIDTH),
conv_std_logic_vector(26835,AMPL_WIDTH),
conv_std_logic_vector(26837,AMPL_WIDTH),
conv_std_logic_vector(26839,AMPL_WIDTH),
conv_std_logic_vector(26840,AMPL_WIDTH),
conv_std_logic_vector(26842,AMPL_WIDTH),
conv_std_logic_vector(26844,AMPL_WIDTH),
conv_std_logic_vector(26846,AMPL_WIDTH),
conv_std_logic_vector(26848,AMPL_WIDTH),
conv_std_logic_vector(26849,AMPL_WIDTH),
conv_std_logic_vector(26851,AMPL_WIDTH),
conv_std_logic_vector(26853,AMPL_WIDTH),
conv_std_logic_vector(26855,AMPL_WIDTH),
conv_std_logic_vector(26857,AMPL_WIDTH),
conv_std_logic_vector(26858,AMPL_WIDTH),
conv_std_logic_vector(26860,AMPL_WIDTH),
conv_std_logic_vector(26862,AMPL_WIDTH),
conv_std_logic_vector(26864,AMPL_WIDTH),
conv_std_logic_vector(26866,AMPL_WIDTH),
conv_std_logic_vector(26867,AMPL_WIDTH),
conv_std_logic_vector(26869,AMPL_WIDTH),
conv_std_logic_vector(26871,AMPL_WIDTH),
conv_std_logic_vector(26873,AMPL_WIDTH),
conv_std_logic_vector(26875,AMPL_WIDTH),
conv_std_logic_vector(26876,AMPL_WIDTH),
conv_std_logic_vector(26878,AMPL_WIDTH),
conv_std_logic_vector(26880,AMPL_WIDTH),
conv_std_logic_vector(26882,AMPL_WIDTH),
conv_std_logic_vector(26884,AMPL_WIDTH),
conv_std_logic_vector(26885,AMPL_WIDTH),
conv_std_logic_vector(26887,AMPL_WIDTH),
conv_std_logic_vector(26889,AMPL_WIDTH),
conv_std_logic_vector(26891,AMPL_WIDTH),
conv_std_logic_vector(26893,AMPL_WIDTH),
conv_std_logic_vector(26894,AMPL_WIDTH),
conv_std_logic_vector(26896,AMPL_WIDTH),
conv_std_logic_vector(26898,AMPL_WIDTH),
conv_std_logic_vector(26900,AMPL_WIDTH),
conv_std_logic_vector(26901,AMPL_WIDTH),
conv_std_logic_vector(26903,AMPL_WIDTH),
conv_std_logic_vector(26905,AMPL_WIDTH),
conv_std_logic_vector(26907,AMPL_WIDTH),
conv_std_logic_vector(26909,AMPL_WIDTH),
conv_std_logic_vector(26910,AMPL_WIDTH),
conv_std_logic_vector(26912,AMPL_WIDTH),
conv_std_logic_vector(26914,AMPL_WIDTH),
conv_std_logic_vector(26916,AMPL_WIDTH),
conv_std_logic_vector(26918,AMPL_WIDTH),
conv_std_logic_vector(26919,AMPL_WIDTH),
conv_std_logic_vector(26921,AMPL_WIDTH),
conv_std_logic_vector(26923,AMPL_WIDTH),
conv_std_logic_vector(26925,AMPL_WIDTH),
conv_std_logic_vector(26927,AMPL_WIDTH),
conv_std_logic_vector(26928,AMPL_WIDTH),
conv_std_logic_vector(26930,AMPL_WIDTH),
conv_std_logic_vector(26932,AMPL_WIDTH),
conv_std_logic_vector(26934,AMPL_WIDTH),
conv_std_logic_vector(26936,AMPL_WIDTH),
conv_std_logic_vector(26937,AMPL_WIDTH),
conv_std_logic_vector(26939,AMPL_WIDTH),
conv_std_logic_vector(26941,AMPL_WIDTH),
conv_std_logic_vector(26943,AMPL_WIDTH),
conv_std_logic_vector(26944,AMPL_WIDTH),
conv_std_logic_vector(26946,AMPL_WIDTH),
conv_std_logic_vector(26948,AMPL_WIDTH),
conv_std_logic_vector(26950,AMPL_WIDTH),
conv_std_logic_vector(26952,AMPL_WIDTH),
conv_std_logic_vector(26953,AMPL_WIDTH),
conv_std_logic_vector(26955,AMPL_WIDTH),
conv_std_logic_vector(26957,AMPL_WIDTH),
conv_std_logic_vector(26959,AMPL_WIDTH),
conv_std_logic_vector(26961,AMPL_WIDTH),
conv_std_logic_vector(26962,AMPL_WIDTH),
conv_std_logic_vector(26964,AMPL_WIDTH),
conv_std_logic_vector(26966,AMPL_WIDTH),
conv_std_logic_vector(26968,AMPL_WIDTH),
conv_std_logic_vector(26969,AMPL_WIDTH),
conv_std_logic_vector(26971,AMPL_WIDTH),
conv_std_logic_vector(26973,AMPL_WIDTH),
conv_std_logic_vector(26975,AMPL_WIDTH),
conv_std_logic_vector(26977,AMPL_WIDTH),
conv_std_logic_vector(26978,AMPL_WIDTH),
conv_std_logic_vector(26980,AMPL_WIDTH),
conv_std_logic_vector(26982,AMPL_WIDTH),
conv_std_logic_vector(26984,AMPL_WIDTH),
conv_std_logic_vector(26986,AMPL_WIDTH),
conv_std_logic_vector(26987,AMPL_WIDTH),
conv_std_logic_vector(26989,AMPL_WIDTH),
conv_std_logic_vector(26991,AMPL_WIDTH),
conv_std_logic_vector(26993,AMPL_WIDTH),
conv_std_logic_vector(26994,AMPL_WIDTH),
conv_std_logic_vector(26996,AMPL_WIDTH),
conv_std_logic_vector(26998,AMPL_WIDTH),
conv_std_logic_vector(27000,AMPL_WIDTH),
conv_std_logic_vector(27002,AMPL_WIDTH),
conv_std_logic_vector(27003,AMPL_WIDTH),
conv_std_logic_vector(27005,AMPL_WIDTH),
conv_std_logic_vector(27007,AMPL_WIDTH),
conv_std_logic_vector(27009,AMPL_WIDTH),
conv_std_logic_vector(27010,AMPL_WIDTH),
conv_std_logic_vector(27012,AMPL_WIDTH),
conv_std_logic_vector(27014,AMPL_WIDTH),
conv_std_logic_vector(27016,AMPL_WIDTH),
conv_std_logic_vector(27018,AMPL_WIDTH),
conv_std_logic_vector(27019,AMPL_WIDTH),
conv_std_logic_vector(27021,AMPL_WIDTH),
conv_std_logic_vector(27023,AMPL_WIDTH),
conv_std_logic_vector(27025,AMPL_WIDTH),
conv_std_logic_vector(27026,AMPL_WIDTH),
conv_std_logic_vector(27028,AMPL_WIDTH),
conv_std_logic_vector(27030,AMPL_WIDTH),
conv_std_logic_vector(27032,AMPL_WIDTH),
conv_std_logic_vector(27034,AMPL_WIDTH),
conv_std_logic_vector(27035,AMPL_WIDTH),
conv_std_logic_vector(27037,AMPL_WIDTH),
conv_std_logic_vector(27039,AMPL_WIDTH),
conv_std_logic_vector(27041,AMPL_WIDTH),
conv_std_logic_vector(27042,AMPL_WIDTH),
conv_std_logic_vector(27044,AMPL_WIDTH),
conv_std_logic_vector(27046,AMPL_WIDTH),
conv_std_logic_vector(27048,AMPL_WIDTH),
conv_std_logic_vector(27049,AMPL_WIDTH),
conv_std_logic_vector(27051,AMPL_WIDTH),
conv_std_logic_vector(27053,AMPL_WIDTH),
conv_std_logic_vector(27055,AMPL_WIDTH),
conv_std_logic_vector(27057,AMPL_WIDTH),
conv_std_logic_vector(27058,AMPL_WIDTH),
conv_std_logic_vector(27060,AMPL_WIDTH),
conv_std_logic_vector(27062,AMPL_WIDTH),
conv_std_logic_vector(27064,AMPL_WIDTH),
conv_std_logic_vector(27065,AMPL_WIDTH),
conv_std_logic_vector(27067,AMPL_WIDTH),
conv_std_logic_vector(27069,AMPL_WIDTH),
conv_std_logic_vector(27071,AMPL_WIDTH),
conv_std_logic_vector(27073,AMPL_WIDTH),
conv_std_logic_vector(27074,AMPL_WIDTH),
conv_std_logic_vector(27076,AMPL_WIDTH),
conv_std_logic_vector(27078,AMPL_WIDTH),
conv_std_logic_vector(27080,AMPL_WIDTH),
conv_std_logic_vector(27081,AMPL_WIDTH),
conv_std_logic_vector(27083,AMPL_WIDTH),
conv_std_logic_vector(27085,AMPL_WIDTH),
conv_std_logic_vector(27087,AMPL_WIDTH),
conv_std_logic_vector(27088,AMPL_WIDTH),
conv_std_logic_vector(27090,AMPL_WIDTH),
conv_std_logic_vector(27092,AMPL_WIDTH),
conv_std_logic_vector(27094,AMPL_WIDTH),
conv_std_logic_vector(27096,AMPL_WIDTH),
conv_std_logic_vector(27097,AMPL_WIDTH),
conv_std_logic_vector(27099,AMPL_WIDTH),
conv_std_logic_vector(27101,AMPL_WIDTH),
conv_std_logic_vector(27103,AMPL_WIDTH),
conv_std_logic_vector(27104,AMPL_WIDTH),
conv_std_logic_vector(27106,AMPL_WIDTH),
conv_std_logic_vector(27108,AMPL_WIDTH),
conv_std_logic_vector(27110,AMPL_WIDTH),
conv_std_logic_vector(27111,AMPL_WIDTH),
conv_std_logic_vector(27113,AMPL_WIDTH),
conv_std_logic_vector(27115,AMPL_WIDTH),
conv_std_logic_vector(27117,AMPL_WIDTH),
conv_std_logic_vector(27118,AMPL_WIDTH),
conv_std_logic_vector(27120,AMPL_WIDTH),
conv_std_logic_vector(27122,AMPL_WIDTH),
conv_std_logic_vector(27124,AMPL_WIDTH),
conv_std_logic_vector(27126,AMPL_WIDTH),
conv_std_logic_vector(27127,AMPL_WIDTH),
conv_std_logic_vector(27129,AMPL_WIDTH),
conv_std_logic_vector(27131,AMPL_WIDTH),
conv_std_logic_vector(27133,AMPL_WIDTH),
conv_std_logic_vector(27134,AMPL_WIDTH),
conv_std_logic_vector(27136,AMPL_WIDTH),
conv_std_logic_vector(27138,AMPL_WIDTH),
conv_std_logic_vector(27140,AMPL_WIDTH),
conv_std_logic_vector(27141,AMPL_WIDTH),
conv_std_logic_vector(27143,AMPL_WIDTH),
conv_std_logic_vector(27145,AMPL_WIDTH),
conv_std_logic_vector(27147,AMPL_WIDTH),
conv_std_logic_vector(27148,AMPL_WIDTH),
conv_std_logic_vector(27150,AMPL_WIDTH),
conv_std_logic_vector(27152,AMPL_WIDTH),
conv_std_logic_vector(27154,AMPL_WIDTH),
conv_std_logic_vector(27155,AMPL_WIDTH),
conv_std_logic_vector(27157,AMPL_WIDTH),
conv_std_logic_vector(27159,AMPL_WIDTH),
conv_std_logic_vector(27161,AMPL_WIDTH),
conv_std_logic_vector(27162,AMPL_WIDTH),
conv_std_logic_vector(27164,AMPL_WIDTH),
conv_std_logic_vector(27166,AMPL_WIDTH),
conv_std_logic_vector(27168,AMPL_WIDTH),
conv_std_logic_vector(27169,AMPL_WIDTH),
conv_std_logic_vector(27171,AMPL_WIDTH),
conv_std_logic_vector(27173,AMPL_WIDTH),
conv_std_logic_vector(27175,AMPL_WIDTH),
conv_std_logic_vector(27177,AMPL_WIDTH),
conv_std_logic_vector(27178,AMPL_WIDTH),
conv_std_logic_vector(27180,AMPL_WIDTH),
conv_std_logic_vector(27182,AMPL_WIDTH),
conv_std_logic_vector(27184,AMPL_WIDTH),
conv_std_logic_vector(27185,AMPL_WIDTH),
conv_std_logic_vector(27187,AMPL_WIDTH),
conv_std_logic_vector(27189,AMPL_WIDTH),
conv_std_logic_vector(27191,AMPL_WIDTH),
conv_std_logic_vector(27192,AMPL_WIDTH),
conv_std_logic_vector(27194,AMPL_WIDTH),
conv_std_logic_vector(27196,AMPL_WIDTH),
conv_std_logic_vector(27198,AMPL_WIDTH),
conv_std_logic_vector(27199,AMPL_WIDTH),
conv_std_logic_vector(27201,AMPL_WIDTH),
conv_std_logic_vector(27203,AMPL_WIDTH),
conv_std_logic_vector(27205,AMPL_WIDTH),
conv_std_logic_vector(27206,AMPL_WIDTH),
conv_std_logic_vector(27208,AMPL_WIDTH),
conv_std_logic_vector(27210,AMPL_WIDTH),
conv_std_logic_vector(27212,AMPL_WIDTH),
conv_std_logic_vector(27213,AMPL_WIDTH),
conv_std_logic_vector(27215,AMPL_WIDTH),
conv_std_logic_vector(27217,AMPL_WIDTH),
conv_std_logic_vector(27219,AMPL_WIDTH),
conv_std_logic_vector(27220,AMPL_WIDTH),
conv_std_logic_vector(27222,AMPL_WIDTH),
conv_std_logic_vector(27224,AMPL_WIDTH),
conv_std_logic_vector(27226,AMPL_WIDTH),
conv_std_logic_vector(27227,AMPL_WIDTH),
conv_std_logic_vector(27229,AMPL_WIDTH),
conv_std_logic_vector(27231,AMPL_WIDTH),
conv_std_logic_vector(27233,AMPL_WIDTH),
conv_std_logic_vector(27234,AMPL_WIDTH),
conv_std_logic_vector(27236,AMPL_WIDTH),
conv_std_logic_vector(27238,AMPL_WIDTH),
conv_std_logic_vector(27240,AMPL_WIDTH),
conv_std_logic_vector(27241,AMPL_WIDTH),
conv_std_logic_vector(27243,AMPL_WIDTH),
conv_std_logic_vector(27245,AMPL_WIDTH),
conv_std_logic_vector(27247,AMPL_WIDTH),
conv_std_logic_vector(27248,AMPL_WIDTH),
conv_std_logic_vector(27250,AMPL_WIDTH),
conv_std_logic_vector(27252,AMPL_WIDTH),
conv_std_logic_vector(27253,AMPL_WIDTH),
conv_std_logic_vector(27255,AMPL_WIDTH),
conv_std_logic_vector(27257,AMPL_WIDTH),
conv_std_logic_vector(27259,AMPL_WIDTH),
conv_std_logic_vector(27260,AMPL_WIDTH),
conv_std_logic_vector(27262,AMPL_WIDTH),
conv_std_logic_vector(27264,AMPL_WIDTH),
conv_std_logic_vector(27266,AMPL_WIDTH),
conv_std_logic_vector(27267,AMPL_WIDTH),
conv_std_logic_vector(27269,AMPL_WIDTH),
conv_std_logic_vector(27271,AMPL_WIDTH),
conv_std_logic_vector(27273,AMPL_WIDTH),
conv_std_logic_vector(27274,AMPL_WIDTH),
conv_std_logic_vector(27276,AMPL_WIDTH),
conv_std_logic_vector(27278,AMPL_WIDTH),
conv_std_logic_vector(27280,AMPL_WIDTH),
conv_std_logic_vector(27281,AMPL_WIDTH),
conv_std_logic_vector(27283,AMPL_WIDTH),
conv_std_logic_vector(27285,AMPL_WIDTH),
conv_std_logic_vector(27287,AMPL_WIDTH),
conv_std_logic_vector(27288,AMPL_WIDTH),
conv_std_logic_vector(27290,AMPL_WIDTH),
conv_std_logic_vector(27292,AMPL_WIDTH),
conv_std_logic_vector(27294,AMPL_WIDTH),
conv_std_logic_vector(27295,AMPL_WIDTH),
conv_std_logic_vector(27297,AMPL_WIDTH),
conv_std_logic_vector(27299,AMPL_WIDTH),
conv_std_logic_vector(27300,AMPL_WIDTH),
conv_std_logic_vector(27302,AMPL_WIDTH),
conv_std_logic_vector(27304,AMPL_WIDTH),
conv_std_logic_vector(27306,AMPL_WIDTH),
conv_std_logic_vector(27307,AMPL_WIDTH),
conv_std_logic_vector(27309,AMPL_WIDTH),
conv_std_logic_vector(27311,AMPL_WIDTH),
conv_std_logic_vector(27313,AMPL_WIDTH),
conv_std_logic_vector(27314,AMPL_WIDTH),
conv_std_logic_vector(27316,AMPL_WIDTH),
conv_std_logic_vector(27318,AMPL_WIDTH),
conv_std_logic_vector(27320,AMPL_WIDTH),
conv_std_logic_vector(27321,AMPL_WIDTH),
conv_std_logic_vector(27323,AMPL_WIDTH),
conv_std_logic_vector(27325,AMPL_WIDTH),
conv_std_logic_vector(27327,AMPL_WIDTH),
conv_std_logic_vector(27328,AMPL_WIDTH),
conv_std_logic_vector(27330,AMPL_WIDTH),
conv_std_logic_vector(27332,AMPL_WIDTH),
conv_std_logic_vector(27333,AMPL_WIDTH),
conv_std_logic_vector(27335,AMPL_WIDTH),
conv_std_logic_vector(27337,AMPL_WIDTH),
conv_std_logic_vector(27339,AMPL_WIDTH),
conv_std_logic_vector(27340,AMPL_WIDTH),
conv_std_logic_vector(27342,AMPL_WIDTH),
conv_std_logic_vector(27344,AMPL_WIDTH),
conv_std_logic_vector(27346,AMPL_WIDTH),
conv_std_logic_vector(27347,AMPL_WIDTH),
conv_std_logic_vector(27349,AMPL_WIDTH),
conv_std_logic_vector(27351,AMPL_WIDTH),
conv_std_logic_vector(27352,AMPL_WIDTH),
conv_std_logic_vector(27354,AMPL_WIDTH),
conv_std_logic_vector(27356,AMPL_WIDTH),
conv_std_logic_vector(27358,AMPL_WIDTH),
conv_std_logic_vector(27359,AMPL_WIDTH),
conv_std_logic_vector(27361,AMPL_WIDTH),
conv_std_logic_vector(27363,AMPL_WIDTH),
conv_std_logic_vector(27365,AMPL_WIDTH),
conv_std_logic_vector(27366,AMPL_WIDTH),
conv_std_logic_vector(27368,AMPL_WIDTH),
conv_std_logic_vector(27370,AMPL_WIDTH),
conv_std_logic_vector(27372,AMPL_WIDTH),
conv_std_logic_vector(27373,AMPL_WIDTH),
conv_std_logic_vector(27375,AMPL_WIDTH),
conv_std_logic_vector(27377,AMPL_WIDTH),
conv_std_logic_vector(27378,AMPL_WIDTH),
conv_std_logic_vector(27380,AMPL_WIDTH),
conv_std_logic_vector(27382,AMPL_WIDTH),
conv_std_logic_vector(27384,AMPL_WIDTH),
conv_std_logic_vector(27385,AMPL_WIDTH),
conv_std_logic_vector(27387,AMPL_WIDTH),
conv_std_logic_vector(27389,AMPL_WIDTH),
conv_std_logic_vector(27390,AMPL_WIDTH),
conv_std_logic_vector(27392,AMPL_WIDTH),
conv_std_logic_vector(27394,AMPL_WIDTH),
conv_std_logic_vector(27396,AMPL_WIDTH),
conv_std_logic_vector(27397,AMPL_WIDTH),
conv_std_logic_vector(27399,AMPL_WIDTH),
conv_std_logic_vector(27401,AMPL_WIDTH),
conv_std_logic_vector(27403,AMPL_WIDTH),
conv_std_logic_vector(27404,AMPL_WIDTH),
conv_std_logic_vector(27406,AMPL_WIDTH),
conv_std_logic_vector(27408,AMPL_WIDTH),
conv_std_logic_vector(27409,AMPL_WIDTH),
conv_std_logic_vector(27411,AMPL_WIDTH),
conv_std_logic_vector(27413,AMPL_WIDTH),
conv_std_logic_vector(27415,AMPL_WIDTH),
conv_std_logic_vector(27416,AMPL_WIDTH),
conv_std_logic_vector(27418,AMPL_WIDTH),
conv_std_logic_vector(27420,AMPL_WIDTH),
conv_std_logic_vector(27421,AMPL_WIDTH),
conv_std_logic_vector(27423,AMPL_WIDTH),
conv_std_logic_vector(27425,AMPL_WIDTH),
conv_std_logic_vector(27427,AMPL_WIDTH),
conv_std_logic_vector(27428,AMPL_WIDTH),
conv_std_logic_vector(27430,AMPL_WIDTH),
conv_std_logic_vector(27432,AMPL_WIDTH),
conv_std_logic_vector(27434,AMPL_WIDTH),
conv_std_logic_vector(27435,AMPL_WIDTH),
conv_std_logic_vector(27437,AMPL_WIDTH),
conv_std_logic_vector(27439,AMPL_WIDTH),
conv_std_logic_vector(27440,AMPL_WIDTH),
conv_std_logic_vector(27442,AMPL_WIDTH),
conv_std_logic_vector(27444,AMPL_WIDTH),
conv_std_logic_vector(27446,AMPL_WIDTH),
conv_std_logic_vector(27447,AMPL_WIDTH),
conv_std_logic_vector(27449,AMPL_WIDTH),
conv_std_logic_vector(27451,AMPL_WIDTH),
conv_std_logic_vector(27452,AMPL_WIDTH),
conv_std_logic_vector(27454,AMPL_WIDTH),
conv_std_logic_vector(27456,AMPL_WIDTH),
conv_std_logic_vector(27458,AMPL_WIDTH),
conv_std_logic_vector(27459,AMPL_WIDTH),
conv_std_logic_vector(27461,AMPL_WIDTH),
conv_std_logic_vector(27463,AMPL_WIDTH),
conv_std_logic_vector(27464,AMPL_WIDTH),
conv_std_logic_vector(27466,AMPL_WIDTH),
conv_std_logic_vector(27468,AMPL_WIDTH),
conv_std_logic_vector(27470,AMPL_WIDTH),
conv_std_logic_vector(27471,AMPL_WIDTH),
conv_std_logic_vector(27473,AMPL_WIDTH),
conv_std_logic_vector(27475,AMPL_WIDTH),
conv_std_logic_vector(27476,AMPL_WIDTH),
conv_std_logic_vector(27478,AMPL_WIDTH),
conv_std_logic_vector(27480,AMPL_WIDTH),
conv_std_logic_vector(27482,AMPL_WIDTH),
conv_std_logic_vector(27483,AMPL_WIDTH),
conv_std_logic_vector(27485,AMPL_WIDTH),
conv_std_logic_vector(27487,AMPL_WIDTH),
conv_std_logic_vector(27488,AMPL_WIDTH),
conv_std_logic_vector(27490,AMPL_WIDTH),
conv_std_logic_vector(27492,AMPL_WIDTH),
conv_std_logic_vector(27493,AMPL_WIDTH),
conv_std_logic_vector(27495,AMPL_WIDTH),
conv_std_logic_vector(27497,AMPL_WIDTH),
conv_std_logic_vector(27499,AMPL_WIDTH),
conv_std_logic_vector(27500,AMPL_WIDTH),
conv_std_logic_vector(27502,AMPL_WIDTH),
conv_std_logic_vector(27504,AMPL_WIDTH),
conv_std_logic_vector(27505,AMPL_WIDTH),
conv_std_logic_vector(27507,AMPL_WIDTH),
conv_std_logic_vector(27509,AMPL_WIDTH),
conv_std_logic_vector(27511,AMPL_WIDTH),
conv_std_logic_vector(27512,AMPL_WIDTH),
conv_std_logic_vector(27514,AMPL_WIDTH),
conv_std_logic_vector(27516,AMPL_WIDTH),
conv_std_logic_vector(27517,AMPL_WIDTH),
conv_std_logic_vector(27519,AMPL_WIDTH),
conv_std_logic_vector(27521,AMPL_WIDTH),
conv_std_logic_vector(27523,AMPL_WIDTH),
conv_std_logic_vector(27524,AMPL_WIDTH),
conv_std_logic_vector(27526,AMPL_WIDTH),
conv_std_logic_vector(27528,AMPL_WIDTH),
conv_std_logic_vector(27529,AMPL_WIDTH),
conv_std_logic_vector(27531,AMPL_WIDTH),
conv_std_logic_vector(27533,AMPL_WIDTH),
conv_std_logic_vector(27534,AMPL_WIDTH),
conv_std_logic_vector(27536,AMPL_WIDTH),
conv_std_logic_vector(27538,AMPL_WIDTH),
conv_std_logic_vector(27540,AMPL_WIDTH),
conv_std_logic_vector(27541,AMPL_WIDTH),
conv_std_logic_vector(27543,AMPL_WIDTH),
conv_std_logic_vector(27545,AMPL_WIDTH),
conv_std_logic_vector(27546,AMPL_WIDTH),
conv_std_logic_vector(27548,AMPL_WIDTH),
conv_std_logic_vector(27550,AMPL_WIDTH),
conv_std_logic_vector(27551,AMPL_WIDTH),
conv_std_logic_vector(27553,AMPL_WIDTH),
conv_std_logic_vector(27555,AMPL_WIDTH),
conv_std_logic_vector(27557,AMPL_WIDTH),
conv_std_logic_vector(27558,AMPL_WIDTH),
conv_std_logic_vector(27560,AMPL_WIDTH),
conv_std_logic_vector(27562,AMPL_WIDTH),
conv_std_logic_vector(27563,AMPL_WIDTH),
conv_std_logic_vector(27565,AMPL_WIDTH),
conv_std_logic_vector(27567,AMPL_WIDTH),
conv_std_logic_vector(27568,AMPL_WIDTH),
conv_std_logic_vector(27570,AMPL_WIDTH),
conv_std_logic_vector(27572,AMPL_WIDTH),
conv_std_logic_vector(27574,AMPL_WIDTH),
conv_std_logic_vector(27575,AMPL_WIDTH),
conv_std_logic_vector(27577,AMPL_WIDTH),
conv_std_logic_vector(27579,AMPL_WIDTH),
conv_std_logic_vector(27580,AMPL_WIDTH),
conv_std_logic_vector(27582,AMPL_WIDTH),
conv_std_logic_vector(27584,AMPL_WIDTH),
conv_std_logic_vector(27585,AMPL_WIDTH),
conv_std_logic_vector(27587,AMPL_WIDTH),
conv_std_logic_vector(27589,AMPL_WIDTH),
conv_std_logic_vector(27590,AMPL_WIDTH),
conv_std_logic_vector(27592,AMPL_WIDTH),
conv_std_logic_vector(27594,AMPL_WIDTH),
conv_std_logic_vector(27596,AMPL_WIDTH),
conv_std_logic_vector(27597,AMPL_WIDTH),
conv_std_logic_vector(27599,AMPL_WIDTH),
conv_std_logic_vector(27601,AMPL_WIDTH),
conv_std_logic_vector(27602,AMPL_WIDTH),
conv_std_logic_vector(27604,AMPL_WIDTH),
conv_std_logic_vector(27606,AMPL_WIDTH),
conv_std_logic_vector(27607,AMPL_WIDTH),
conv_std_logic_vector(27609,AMPL_WIDTH),
conv_std_logic_vector(27611,AMPL_WIDTH),
conv_std_logic_vector(27613,AMPL_WIDTH),
conv_std_logic_vector(27614,AMPL_WIDTH),
conv_std_logic_vector(27616,AMPL_WIDTH),
conv_std_logic_vector(27618,AMPL_WIDTH),
conv_std_logic_vector(27619,AMPL_WIDTH),
conv_std_logic_vector(27621,AMPL_WIDTH),
conv_std_logic_vector(27623,AMPL_WIDTH),
conv_std_logic_vector(27624,AMPL_WIDTH),
conv_std_logic_vector(27626,AMPL_WIDTH),
conv_std_logic_vector(27628,AMPL_WIDTH),
conv_std_logic_vector(27629,AMPL_WIDTH),
conv_std_logic_vector(27631,AMPL_WIDTH),
conv_std_logic_vector(27633,AMPL_WIDTH),
conv_std_logic_vector(27634,AMPL_WIDTH),
conv_std_logic_vector(27636,AMPL_WIDTH),
conv_std_logic_vector(27638,AMPL_WIDTH),
conv_std_logic_vector(27640,AMPL_WIDTH),
conv_std_logic_vector(27641,AMPL_WIDTH),
conv_std_logic_vector(27643,AMPL_WIDTH),
conv_std_logic_vector(27645,AMPL_WIDTH),
conv_std_logic_vector(27646,AMPL_WIDTH),
conv_std_logic_vector(27648,AMPL_WIDTH),
conv_std_logic_vector(27650,AMPL_WIDTH),
conv_std_logic_vector(27651,AMPL_WIDTH),
conv_std_logic_vector(27653,AMPL_WIDTH),
conv_std_logic_vector(27655,AMPL_WIDTH),
conv_std_logic_vector(27656,AMPL_WIDTH),
conv_std_logic_vector(27658,AMPL_WIDTH),
conv_std_logic_vector(27660,AMPL_WIDTH),
conv_std_logic_vector(27661,AMPL_WIDTH),
conv_std_logic_vector(27663,AMPL_WIDTH),
conv_std_logic_vector(27665,AMPL_WIDTH),
conv_std_logic_vector(27666,AMPL_WIDTH),
conv_std_logic_vector(27668,AMPL_WIDTH),
conv_std_logic_vector(27670,AMPL_WIDTH),
conv_std_logic_vector(27672,AMPL_WIDTH),
conv_std_logic_vector(27673,AMPL_WIDTH),
conv_std_logic_vector(27675,AMPL_WIDTH),
conv_std_logic_vector(27677,AMPL_WIDTH),
conv_std_logic_vector(27678,AMPL_WIDTH),
conv_std_logic_vector(27680,AMPL_WIDTH),
conv_std_logic_vector(27682,AMPL_WIDTH),
conv_std_logic_vector(27683,AMPL_WIDTH),
conv_std_logic_vector(27685,AMPL_WIDTH),
conv_std_logic_vector(27687,AMPL_WIDTH),
conv_std_logic_vector(27688,AMPL_WIDTH),
conv_std_logic_vector(27690,AMPL_WIDTH),
conv_std_logic_vector(27692,AMPL_WIDTH),
conv_std_logic_vector(27693,AMPL_WIDTH),
conv_std_logic_vector(27695,AMPL_WIDTH),
conv_std_logic_vector(27697,AMPL_WIDTH),
conv_std_logic_vector(27698,AMPL_WIDTH),
conv_std_logic_vector(27700,AMPL_WIDTH),
conv_std_logic_vector(27702,AMPL_WIDTH),
conv_std_logic_vector(27703,AMPL_WIDTH),
conv_std_logic_vector(27705,AMPL_WIDTH),
conv_std_logic_vector(27707,AMPL_WIDTH),
conv_std_logic_vector(27708,AMPL_WIDTH),
conv_std_logic_vector(27710,AMPL_WIDTH),
conv_std_logic_vector(27712,AMPL_WIDTH),
conv_std_logic_vector(27714,AMPL_WIDTH),
conv_std_logic_vector(27715,AMPL_WIDTH),
conv_std_logic_vector(27717,AMPL_WIDTH),
conv_std_logic_vector(27719,AMPL_WIDTH),
conv_std_logic_vector(27720,AMPL_WIDTH),
conv_std_logic_vector(27722,AMPL_WIDTH),
conv_std_logic_vector(27724,AMPL_WIDTH),
conv_std_logic_vector(27725,AMPL_WIDTH),
conv_std_logic_vector(27727,AMPL_WIDTH),
conv_std_logic_vector(27729,AMPL_WIDTH),
conv_std_logic_vector(27730,AMPL_WIDTH),
conv_std_logic_vector(27732,AMPL_WIDTH),
conv_std_logic_vector(27734,AMPL_WIDTH),
conv_std_logic_vector(27735,AMPL_WIDTH),
conv_std_logic_vector(27737,AMPL_WIDTH),
conv_std_logic_vector(27739,AMPL_WIDTH),
conv_std_logic_vector(27740,AMPL_WIDTH),
conv_std_logic_vector(27742,AMPL_WIDTH),
conv_std_logic_vector(27744,AMPL_WIDTH),
conv_std_logic_vector(27745,AMPL_WIDTH),
conv_std_logic_vector(27747,AMPL_WIDTH),
conv_std_logic_vector(27749,AMPL_WIDTH),
conv_std_logic_vector(27750,AMPL_WIDTH),
conv_std_logic_vector(27752,AMPL_WIDTH),
conv_std_logic_vector(27754,AMPL_WIDTH),
conv_std_logic_vector(27755,AMPL_WIDTH),
conv_std_logic_vector(27757,AMPL_WIDTH),
conv_std_logic_vector(27759,AMPL_WIDTH),
conv_std_logic_vector(27760,AMPL_WIDTH),
conv_std_logic_vector(27762,AMPL_WIDTH),
conv_std_logic_vector(27764,AMPL_WIDTH),
conv_std_logic_vector(27765,AMPL_WIDTH),
conv_std_logic_vector(27767,AMPL_WIDTH),
conv_std_logic_vector(27769,AMPL_WIDTH),
conv_std_logic_vector(27770,AMPL_WIDTH),
conv_std_logic_vector(27772,AMPL_WIDTH),
conv_std_logic_vector(27774,AMPL_WIDTH),
conv_std_logic_vector(27775,AMPL_WIDTH),
conv_std_logic_vector(27777,AMPL_WIDTH),
conv_std_logic_vector(27779,AMPL_WIDTH),
conv_std_logic_vector(27780,AMPL_WIDTH),
conv_std_logic_vector(27782,AMPL_WIDTH),
conv_std_logic_vector(27784,AMPL_WIDTH),
conv_std_logic_vector(27785,AMPL_WIDTH),
conv_std_logic_vector(27787,AMPL_WIDTH),
conv_std_logic_vector(27789,AMPL_WIDTH),
conv_std_logic_vector(27790,AMPL_WIDTH),
conv_std_logic_vector(27792,AMPL_WIDTH),
conv_std_logic_vector(27794,AMPL_WIDTH),
conv_std_logic_vector(27795,AMPL_WIDTH),
conv_std_logic_vector(27797,AMPL_WIDTH),
conv_std_logic_vector(27799,AMPL_WIDTH),
conv_std_logic_vector(27800,AMPL_WIDTH),
conv_std_logic_vector(27802,AMPL_WIDTH),
conv_std_logic_vector(27804,AMPL_WIDTH),
conv_std_logic_vector(27805,AMPL_WIDTH),
conv_std_logic_vector(27807,AMPL_WIDTH),
conv_std_logic_vector(27809,AMPL_WIDTH),
conv_std_logic_vector(27810,AMPL_WIDTH),
conv_std_logic_vector(27812,AMPL_WIDTH),
conv_std_logic_vector(27814,AMPL_WIDTH),
conv_std_logic_vector(27815,AMPL_WIDTH),
conv_std_logic_vector(27817,AMPL_WIDTH),
conv_std_logic_vector(27819,AMPL_WIDTH),
conv_std_logic_vector(27820,AMPL_WIDTH),
conv_std_logic_vector(27822,AMPL_WIDTH),
conv_std_logic_vector(27824,AMPL_WIDTH),
conv_std_logic_vector(27825,AMPL_WIDTH),
conv_std_logic_vector(27827,AMPL_WIDTH),
conv_std_logic_vector(27829,AMPL_WIDTH),
conv_std_logic_vector(27830,AMPL_WIDTH),
conv_std_logic_vector(27832,AMPL_WIDTH),
conv_std_logic_vector(27834,AMPL_WIDTH),
conv_std_logic_vector(27835,AMPL_WIDTH),
conv_std_logic_vector(27837,AMPL_WIDTH),
conv_std_logic_vector(27839,AMPL_WIDTH),
conv_std_logic_vector(27840,AMPL_WIDTH),
conv_std_logic_vector(27842,AMPL_WIDTH),
conv_std_logic_vector(27843,AMPL_WIDTH),
conv_std_logic_vector(27845,AMPL_WIDTH),
conv_std_logic_vector(27847,AMPL_WIDTH),
conv_std_logic_vector(27848,AMPL_WIDTH),
conv_std_logic_vector(27850,AMPL_WIDTH),
conv_std_logic_vector(27852,AMPL_WIDTH),
conv_std_logic_vector(27853,AMPL_WIDTH),
conv_std_logic_vector(27855,AMPL_WIDTH),
conv_std_logic_vector(27857,AMPL_WIDTH),
conv_std_logic_vector(27858,AMPL_WIDTH),
conv_std_logic_vector(27860,AMPL_WIDTH),
conv_std_logic_vector(27862,AMPL_WIDTH),
conv_std_logic_vector(27863,AMPL_WIDTH),
conv_std_logic_vector(27865,AMPL_WIDTH),
conv_std_logic_vector(27867,AMPL_WIDTH),
conv_std_logic_vector(27868,AMPL_WIDTH),
conv_std_logic_vector(27870,AMPL_WIDTH),
conv_std_logic_vector(27872,AMPL_WIDTH),
conv_std_logic_vector(27873,AMPL_WIDTH),
conv_std_logic_vector(27875,AMPL_WIDTH),
conv_std_logic_vector(27877,AMPL_WIDTH),
conv_std_logic_vector(27878,AMPL_WIDTH),
conv_std_logic_vector(27880,AMPL_WIDTH),
conv_std_logic_vector(27882,AMPL_WIDTH),
conv_std_logic_vector(27883,AMPL_WIDTH),
conv_std_logic_vector(27885,AMPL_WIDTH),
conv_std_logic_vector(27886,AMPL_WIDTH),
conv_std_logic_vector(27888,AMPL_WIDTH),
conv_std_logic_vector(27890,AMPL_WIDTH),
conv_std_logic_vector(27891,AMPL_WIDTH),
conv_std_logic_vector(27893,AMPL_WIDTH),
conv_std_logic_vector(27895,AMPL_WIDTH),
conv_std_logic_vector(27896,AMPL_WIDTH),
conv_std_logic_vector(27898,AMPL_WIDTH),
conv_std_logic_vector(27900,AMPL_WIDTH),
conv_std_logic_vector(27901,AMPL_WIDTH),
conv_std_logic_vector(27903,AMPL_WIDTH),
conv_std_logic_vector(27905,AMPL_WIDTH),
conv_std_logic_vector(27906,AMPL_WIDTH),
conv_std_logic_vector(27908,AMPL_WIDTH),
conv_std_logic_vector(27910,AMPL_WIDTH),
conv_std_logic_vector(27911,AMPL_WIDTH),
conv_std_logic_vector(27913,AMPL_WIDTH),
conv_std_logic_vector(27914,AMPL_WIDTH),
conv_std_logic_vector(27916,AMPL_WIDTH),
conv_std_logic_vector(27918,AMPL_WIDTH),
conv_std_logic_vector(27919,AMPL_WIDTH),
conv_std_logic_vector(27921,AMPL_WIDTH),
conv_std_logic_vector(27923,AMPL_WIDTH),
conv_std_logic_vector(27924,AMPL_WIDTH),
conv_std_logic_vector(27926,AMPL_WIDTH),
conv_std_logic_vector(27928,AMPL_WIDTH),
conv_std_logic_vector(27929,AMPL_WIDTH),
conv_std_logic_vector(27931,AMPL_WIDTH),
conv_std_logic_vector(27933,AMPL_WIDTH),
conv_std_logic_vector(27934,AMPL_WIDTH),
conv_std_logic_vector(27936,AMPL_WIDTH),
conv_std_logic_vector(27937,AMPL_WIDTH),
conv_std_logic_vector(27939,AMPL_WIDTH),
conv_std_logic_vector(27941,AMPL_WIDTH),
conv_std_logic_vector(27942,AMPL_WIDTH),
conv_std_logic_vector(27944,AMPL_WIDTH),
conv_std_logic_vector(27946,AMPL_WIDTH),
conv_std_logic_vector(27947,AMPL_WIDTH),
conv_std_logic_vector(27949,AMPL_WIDTH),
conv_std_logic_vector(27951,AMPL_WIDTH),
conv_std_logic_vector(27952,AMPL_WIDTH),
conv_std_logic_vector(27954,AMPL_WIDTH),
conv_std_logic_vector(27956,AMPL_WIDTH),
conv_std_logic_vector(27957,AMPL_WIDTH),
conv_std_logic_vector(27959,AMPL_WIDTH),
conv_std_logic_vector(27960,AMPL_WIDTH),
conv_std_logic_vector(27962,AMPL_WIDTH),
conv_std_logic_vector(27964,AMPL_WIDTH),
conv_std_logic_vector(27965,AMPL_WIDTH),
conv_std_logic_vector(27967,AMPL_WIDTH),
conv_std_logic_vector(27969,AMPL_WIDTH),
conv_std_logic_vector(27970,AMPL_WIDTH),
conv_std_logic_vector(27972,AMPL_WIDTH),
conv_std_logic_vector(27974,AMPL_WIDTH),
conv_std_logic_vector(27975,AMPL_WIDTH),
conv_std_logic_vector(27977,AMPL_WIDTH),
conv_std_logic_vector(27978,AMPL_WIDTH),
conv_std_logic_vector(27980,AMPL_WIDTH),
conv_std_logic_vector(27982,AMPL_WIDTH),
conv_std_logic_vector(27983,AMPL_WIDTH),
conv_std_logic_vector(27985,AMPL_WIDTH),
conv_std_logic_vector(27987,AMPL_WIDTH),
conv_std_logic_vector(27988,AMPL_WIDTH),
conv_std_logic_vector(27990,AMPL_WIDTH),
conv_std_logic_vector(27992,AMPL_WIDTH),
conv_std_logic_vector(27993,AMPL_WIDTH),
conv_std_logic_vector(27995,AMPL_WIDTH),
conv_std_logic_vector(27996,AMPL_WIDTH),
conv_std_logic_vector(27998,AMPL_WIDTH),
conv_std_logic_vector(28000,AMPL_WIDTH),
conv_std_logic_vector(28001,AMPL_WIDTH),
conv_std_logic_vector(28003,AMPL_WIDTH),
conv_std_logic_vector(28005,AMPL_WIDTH),
conv_std_logic_vector(28006,AMPL_WIDTH),
conv_std_logic_vector(28008,AMPL_WIDTH),
conv_std_logic_vector(28009,AMPL_WIDTH),
conv_std_logic_vector(28011,AMPL_WIDTH),
conv_std_logic_vector(28013,AMPL_WIDTH),
conv_std_logic_vector(28014,AMPL_WIDTH),
conv_std_logic_vector(28016,AMPL_WIDTH),
conv_std_logic_vector(28018,AMPL_WIDTH),
conv_std_logic_vector(28019,AMPL_WIDTH),
conv_std_logic_vector(28021,AMPL_WIDTH),
conv_std_logic_vector(28022,AMPL_WIDTH),
conv_std_logic_vector(28024,AMPL_WIDTH),
conv_std_logic_vector(28026,AMPL_WIDTH),
conv_std_logic_vector(28027,AMPL_WIDTH),
conv_std_logic_vector(28029,AMPL_WIDTH),
conv_std_logic_vector(28031,AMPL_WIDTH),
conv_std_logic_vector(28032,AMPL_WIDTH),
conv_std_logic_vector(28034,AMPL_WIDTH),
conv_std_logic_vector(28036,AMPL_WIDTH),
conv_std_logic_vector(28037,AMPL_WIDTH),
conv_std_logic_vector(28039,AMPL_WIDTH),
conv_std_logic_vector(28040,AMPL_WIDTH),
conv_std_logic_vector(28042,AMPL_WIDTH),
conv_std_logic_vector(28044,AMPL_WIDTH),
conv_std_logic_vector(28045,AMPL_WIDTH),
conv_std_logic_vector(28047,AMPL_WIDTH),
conv_std_logic_vector(28049,AMPL_WIDTH),
conv_std_logic_vector(28050,AMPL_WIDTH),
conv_std_logic_vector(28052,AMPL_WIDTH),
conv_std_logic_vector(28053,AMPL_WIDTH),
conv_std_logic_vector(28055,AMPL_WIDTH),
conv_std_logic_vector(28057,AMPL_WIDTH),
conv_std_logic_vector(28058,AMPL_WIDTH),
conv_std_logic_vector(28060,AMPL_WIDTH),
conv_std_logic_vector(28061,AMPL_WIDTH),
conv_std_logic_vector(28063,AMPL_WIDTH),
conv_std_logic_vector(28065,AMPL_WIDTH),
conv_std_logic_vector(28066,AMPL_WIDTH),
conv_std_logic_vector(28068,AMPL_WIDTH),
conv_std_logic_vector(28070,AMPL_WIDTH),
conv_std_logic_vector(28071,AMPL_WIDTH),
conv_std_logic_vector(28073,AMPL_WIDTH),
conv_std_logic_vector(28074,AMPL_WIDTH),
conv_std_logic_vector(28076,AMPL_WIDTH),
conv_std_logic_vector(28078,AMPL_WIDTH),
conv_std_logic_vector(28079,AMPL_WIDTH),
conv_std_logic_vector(28081,AMPL_WIDTH),
conv_std_logic_vector(28083,AMPL_WIDTH),
conv_std_logic_vector(28084,AMPL_WIDTH),
conv_std_logic_vector(28086,AMPL_WIDTH),
conv_std_logic_vector(28087,AMPL_WIDTH),
conv_std_logic_vector(28089,AMPL_WIDTH),
conv_std_logic_vector(28091,AMPL_WIDTH),
conv_std_logic_vector(28092,AMPL_WIDTH),
conv_std_logic_vector(28094,AMPL_WIDTH),
conv_std_logic_vector(28095,AMPL_WIDTH),
conv_std_logic_vector(28097,AMPL_WIDTH),
conv_std_logic_vector(28099,AMPL_WIDTH),
conv_std_logic_vector(28100,AMPL_WIDTH),
conv_std_logic_vector(28102,AMPL_WIDTH),
conv_std_logic_vector(28104,AMPL_WIDTH),
conv_std_logic_vector(28105,AMPL_WIDTH),
conv_std_logic_vector(28107,AMPL_WIDTH),
conv_std_logic_vector(28108,AMPL_WIDTH),
conv_std_logic_vector(28110,AMPL_WIDTH),
conv_std_logic_vector(28112,AMPL_WIDTH),
conv_std_logic_vector(28113,AMPL_WIDTH),
conv_std_logic_vector(28115,AMPL_WIDTH),
conv_std_logic_vector(28116,AMPL_WIDTH),
conv_std_logic_vector(28118,AMPL_WIDTH),
conv_std_logic_vector(28120,AMPL_WIDTH),
conv_std_logic_vector(28121,AMPL_WIDTH),
conv_std_logic_vector(28123,AMPL_WIDTH),
conv_std_logic_vector(28125,AMPL_WIDTH),
conv_std_logic_vector(28126,AMPL_WIDTH),
conv_std_logic_vector(28128,AMPL_WIDTH),
conv_std_logic_vector(28129,AMPL_WIDTH),
conv_std_logic_vector(28131,AMPL_WIDTH),
conv_std_logic_vector(28133,AMPL_WIDTH),
conv_std_logic_vector(28134,AMPL_WIDTH),
conv_std_logic_vector(28136,AMPL_WIDTH),
conv_std_logic_vector(28137,AMPL_WIDTH),
conv_std_logic_vector(28139,AMPL_WIDTH),
conv_std_logic_vector(28141,AMPL_WIDTH),
conv_std_logic_vector(28142,AMPL_WIDTH),
conv_std_logic_vector(28144,AMPL_WIDTH),
conv_std_logic_vector(28145,AMPL_WIDTH),
conv_std_logic_vector(28147,AMPL_WIDTH),
conv_std_logic_vector(28149,AMPL_WIDTH),
conv_std_logic_vector(28150,AMPL_WIDTH),
conv_std_logic_vector(28152,AMPL_WIDTH),
conv_std_logic_vector(28154,AMPL_WIDTH),
conv_std_logic_vector(28155,AMPL_WIDTH),
conv_std_logic_vector(28157,AMPL_WIDTH),
conv_std_logic_vector(28158,AMPL_WIDTH),
conv_std_logic_vector(28160,AMPL_WIDTH),
conv_std_logic_vector(28162,AMPL_WIDTH),
conv_std_logic_vector(28163,AMPL_WIDTH),
conv_std_logic_vector(28165,AMPL_WIDTH),
conv_std_logic_vector(28166,AMPL_WIDTH),
conv_std_logic_vector(28168,AMPL_WIDTH),
conv_std_logic_vector(28170,AMPL_WIDTH),
conv_std_logic_vector(28171,AMPL_WIDTH),
conv_std_logic_vector(28173,AMPL_WIDTH),
conv_std_logic_vector(28174,AMPL_WIDTH),
conv_std_logic_vector(28176,AMPL_WIDTH),
conv_std_logic_vector(28178,AMPL_WIDTH),
conv_std_logic_vector(28179,AMPL_WIDTH),
conv_std_logic_vector(28181,AMPL_WIDTH),
conv_std_logic_vector(28182,AMPL_WIDTH),
conv_std_logic_vector(28184,AMPL_WIDTH),
conv_std_logic_vector(28186,AMPL_WIDTH),
conv_std_logic_vector(28187,AMPL_WIDTH),
conv_std_logic_vector(28189,AMPL_WIDTH),
conv_std_logic_vector(28190,AMPL_WIDTH),
conv_std_logic_vector(28192,AMPL_WIDTH),
conv_std_logic_vector(28194,AMPL_WIDTH),
conv_std_logic_vector(28195,AMPL_WIDTH),
conv_std_logic_vector(28197,AMPL_WIDTH),
conv_std_logic_vector(28198,AMPL_WIDTH),
conv_std_logic_vector(28200,AMPL_WIDTH),
conv_std_logic_vector(28202,AMPL_WIDTH),
conv_std_logic_vector(28203,AMPL_WIDTH),
conv_std_logic_vector(28205,AMPL_WIDTH),
conv_std_logic_vector(28206,AMPL_WIDTH),
conv_std_logic_vector(28208,AMPL_WIDTH),
conv_std_logic_vector(28210,AMPL_WIDTH),
conv_std_logic_vector(28211,AMPL_WIDTH),
conv_std_logic_vector(28213,AMPL_WIDTH),
conv_std_logic_vector(28214,AMPL_WIDTH),
conv_std_logic_vector(28216,AMPL_WIDTH),
conv_std_logic_vector(28218,AMPL_WIDTH),
conv_std_logic_vector(28219,AMPL_WIDTH),
conv_std_logic_vector(28221,AMPL_WIDTH),
conv_std_logic_vector(28222,AMPL_WIDTH),
conv_std_logic_vector(28224,AMPL_WIDTH),
conv_std_logic_vector(28226,AMPL_WIDTH),
conv_std_logic_vector(28227,AMPL_WIDTH),
conv_std_logic_vector(28229,AMPL_WIDTH),
conv_std_logic_vector(28230,AMPL_WIDTH),
conv_std_logic_vector(28232,AMPL_WIDTH),
conv_std_logic_vector(28234,AMPL_WIDTH),
conv_std_logic_vector(28235,AMPL_WIDTH),
conv_std_logic_vector(28237,AMPL_WIDTH),
conv_std_logic_vector(28238,AMPL_WIDTH),
conv_std_logic_vector(28240,AMPL_WIDTH),
conv_std_logic_vector(28242,AMPL_WIDTH),
conv_std_logic_vector(28243,AMPL_WIDTH),
conv_std_logic_vector(28245,AMPL_WIDTH),
conv_std_logic_vector(28246,AMPL_WIDTH),
conv_std_logic_vector(28248,AMPL_WIDTH),
conv_std_logic_vector(28249,AMPL_WIDTH),
conv_std_logic_vector(28251,AMPL_WIDTH),
conv_std_logic_vector(28253,AMPL_WIDTH),
conv_std_logic_vector(28254,AMPL_WIDTH),
conv_std_logic_vector(28256,AMPL_WIDTH),
conv_std_logic_vector(28257,AMPL_WIDTH),
conv_std_logic_vector(28259,AMPL_WIDTH),
conv_std_logic_vector(28261,AMPL_WIDTH),
conv_std_logic_vector(28262,AMPL_WIDTH),
conv_std_logic_vector(28264,AMPL_WIDTH),
conv_std_logic_vector(28265,AMPL_WIDTH),
conv_std_logic_vector(28267,AMPL_WIDTH),
conv_std_logic_vector(28269,AMPL_WIDTH),
conv_std_logic_vector(28270,AMPL_WIDTH),
conv_std_logic_vector(28272,AMPL_WIDTH),
conv_std_logic_vector(28273,AMPL_WIDTH),
conv_std_logic_vector(28275,AMPL_WIDTH),
conv_std_logic_vector(28277,AMPL_WIDTH),
conv_std_logic_vector(28278,AMPL_WIDTH),
conv_std_logic_vector(28280,AMPL_WIDTH),
conv_std_logic_vector(28281,AMPL_WIDTH),
conv_std_logic_vector(28283,AMPL_WIDTH),
conv_std_logic_vector(28284,AMPL_WIDTH),
conv_std_logic_vector(28286,AMPL_WIDTH),
conv_std_logic_vector(28288,AMPL_WIDTH),
conv_std_logic_vector(28289,AMPL_WIDTH),
conv_std_logic_vector(28291,AMPL_WIDTH),
conv_std_logic_vector(28292,AMPL_WIDTH),
conv_std_logic_vector(28294,AMPL_WIDTH),
conv_std_logic_vector(28296,AMPL_WIDTH),
conv_std_logic_vector(28297,AMPL_WIDTH),
conv_std_logic_vector(28299,AMPL_WIDTH),
conv_std_logic_vector(28300,AMPL_WIDTH),
conv_std_logic_vector(28302,AMPL_WIDTH),
conv_std_logic_vector(28303,AMPL_WIDTH),
conv_std_logic_vector(28305,AMPL_WIDTH),
conv_std_logic_vector(28307,AMPL_WIDTH),
conv_std_logic_vector(28308,AMPL_WIDTH),
conv_std_logic_vector(28310,AMPL_WIDTH),
conv_std_logic_vector(28311,AMPL_WIDTH),
conv_std_logic_vector(28313,AMPL_WIDTH),
conv_std_logic_vector(28315,AMPL_WIDTH),
conv_std_logic_vector(28316,AMPL_WIDTH),
conv_std_logic_vector(28318,AMPL_WIDTH),
conv_std_logic_vector(28319,AMPL_WIDTH),
conv_std_logic_vector(28321,AMPL_WIDTH),
conv_std_logic_vector(28322,AMPL_WIDTH),
conv_std_logic_vector(28324,AMPL_WIDTH),
conv_std_logic_vector(28326,AMPL_WIDTH),
conv_std_logic_vector(28327,AMPL_WIDTH),
conv_std_logic_vector(28329,AMPL_WIDTH),
conv_std_logic_vector(28330,AMPL_WIDTH),
conv_std_logic_vector(28332,AMPL_WIDTH),
conv_std_logic_vector(28333,AMPL_WIDTH),
conv_std_logic_vector(28335,AMPL_WIDTH),
conv_std_logic_vector(28337,AMPL_WIDTH),
conv_std_logic_vector(28338,AMPL_WIDTH),
conv_std_logic_vector(28340,AMPL_WIDTH),
conv_std_logic_vector(28341,AMPL_WIDTH),
conv_std_logic_vector(28343,AMPL_WIDTH),
conv_std_logic_vector(28345,AMPL_WIDTH),
conv_std_logic_vector(28346,AMPL_WIDTH),
conv_std_logic_vector(28348,AMPL_WIDTH),
conv_std_logic_vector(28349,AMPL_WIDTH),
conv_std_logic_vector(28351,AMPL_WIDTH),
conv_std_logic_vector(28352,AMPL_WIDTH),
conv_std_logic_vector(28354,AMPL_WIDTH),
conv_std_logic_vector(28356,AMPL_WIDTH),
conv_std_logic_vector(28357,AMPL_WIDTH),
conv_std_logic_vector(28359,AMPL_WIDTH),
conv_std_logic_vector(28360,AMPL_WIDTH),
conv_std_logic_vector(28362,AMPL_WIDTH),
conv_std_logic_vector(28363,AMPL_WIDTH),
conv_std_logic_vector(28365,AMPL_WIDTH),
conv_std_logic_vector(28367,AMPL_WIDTH),
conv_std_logic_vector(28368,AMPL_WIDTH),
conv_std_logic_vector(28370,AMPL_WIDTH),
conv_std_logic_vector(28371,AMPL_WIDTH),
conv_std_logic_vector(28373,AMPL_WIDTH),
conv_std_logic_vector(28374,AMPL_WIDTH),
conv_std_logic_vector(28376,AMPL_WIDTH),
conv_std_logic_vector(28378,AMPL_WIDTH),
conv_std_logic_vector(28379,AMPL_WIDTH),
conv_std_logic_vector(28381,AMPL_WIDTH),
conv_std_logic_vector(28382,AMPL_WIDTH),
conv_std_logic_vector(28384,AMPL_WIDTH),
conv_std_logic_vector(28385,AMPL_WIDTH),
conv_std_logic_vector(28387,AMPL_WIDTH),
conv_std_logic_vector(28389,AMPL_WIDTH),
conv_std_logic_vector(28390,AMPL_WIDTH),
conv_std_logic_vector(28392,AMPL_WIDTH),
conv_std_logic_vector(28393,AMPL_WIDTH),
conv_std_logic_vector(28395,AMPL_WIDTH),
conv_std_logic_vector(28396,AMPL_WIDTH),
conv_std_logic_vector(28398,AMPL_WIDTH),
conv_std_logic_vector(28400,AMPL_WIDTH),
conv_std_logic_vector(28401,AMPL_WIDTH),
conv_std_logic_vector(28403,AMPL_WIDTH),
conv_std_logic_vector(28404,AMPL_WIDTH),
conv_std_logic_vector(28406,AMPL_WIDTH),
conv_std_logic_vector(28407,AMPL_WIDTH),
conv_std_logic_vector(28409,AMPL_WIDTH),
conv_std_logic_vector(28411,AMPL_WIDTH),
conv_std_logic_vector(28412,AMPL_WIDTH),
conv_std_logic_vector(28414,AMPL_WIDTH),
conv_std_logic_vector(28415,AMPL_WIDTH),
conv_std_logic_vector(28417,AMPL_WIDTH),
conv_std_logic_vector(28418,AMPL_WIDTH),
conv_std_logic_vector(28420,AMPL_WIDTH),
conv_std_logic_vector(28421,AMPL_WIDTH),
conv_std_logic_vector(28423,AMPL_WIDTH),
conv_std_logic_vector(28425,AMPL_WIDTH),
conv_std_logic_vector(28426,AMPL_WIDTH),
conv_std_logic_vector(28428,AMPL_WIDTH),
conv_std_logic_vector(28429,AMPL_WIDTH),
conv_std_logic_vector(28431,AMPL_WIDTH),
conv_std_logic_vector(28432,AMPL_WIDTH),
conv_std_logic_vector(28434,AMPL_WIDTH),
conv_std_logic_vector(28436,AMPL_WIDTH),
conv_std_logic_vector(28437,AMPL_WIDTH),
conv_std_logic_vector(28439,AMPL_WIDTH),
conv_std_logic_vector(28440,AMPL_WIDTH),
conv_std_logic_vector(28442,AMPL_WIDTH),
conv_std_logic_vector(28443,AMPL_WIDTH),
conv_std_logic_vector(28445,AMPL_WIDTH),
conv_std_logic_vector(28446,AMPL_WIDTH),
conv_std_logic_vector(28448,AMPL_WIDTH),
conv_std_logic_vector(28450,AMPL_WIDTH),
conv_std_logic_vector(28451,AMPL_WIDTH),
conv_std_logic_vector(28453,AMPL_WIDTH),
conv_std_logic_vector(28454,AMPL_WIDTH),
conv_std_logic_vector(28456,AMPL_WIDTH),
conv_std_logic_vector(28457,AMPL_WIDTH),
conv_std_logic_vector(28459,AMPL_WIDTH),
conv_std_logic_vector(28460,AMPL_WIDTH),
conv_std_logic_vector(28462,AMPL_WIDTH),
conv_std_logic_vector(28464,AMPL_WIDTH),
conv_std_logic_vector(28465,AMPL_WIDTH),
conv_std_logic_vector(28467,AMPL_WIDTH),
conv_std_logic_vector(28468,AMPL_WIDTH),
conv_std_logic_vector(28470,AMPL_WIDTH),
conv_std_logic_vector(28471,AMPL_WIDTH),
conv_std_logic_vector(28473,AMPL_WIDTH),
conv_std_logic_vector(28474,AMPL_WIDTH),
conv_std_logic_vector(28476,AMPL_WIDTH),
conv_std_logic_vector(28478,AMPL_WIDTH),
conv_std_logic_vector(28479,AMPL_WIDTH),
conv_std_logic_vector(28481,AMPL_WIDTH),
conv_std_logic_vector(28482,AMPL_WIDTH),
conv_std_logic_vector(28484,AMPL_WIDTH),
conv_std_logic_vector(28485,AMPL_WIDTH),
conv_std_logic_vector(28487,AMPL_WIDTH),
conv_std_logic_vector(28488,AMPL_WIDTH),
conv_std_logic_vector(28490,AMPL_WIDTH),
conv_std_logic_vector(28492,AMPL_WIDTH),
conv_std_logic_vector(28493,AMPL_WIDTH),
conv_std_logic_vector(28495,AMPL_WIDTH),
conv_std_logic_vector(28496,AMPL_WIDTH),
conv_std_logic_vector(28498,AMPL_WIDTH),
conv_std_logic_vector(28499,AMPL_WIDTH),
conv_std_logic_vector(28501,AMPL_WIDTH),
conv_std_logic_vector(28502,AMPL_WIDTH),
conv_std_logic_vector(28504,AMPL_WIDTH),
conv_std_logic_vector(28505,AMPL_WIDTH),
conv_std_logic_vector(28507,AMPL_WIDTH),
conv_std_logic_vector(28509,AMPL_WIDTH),
conv_std_logic_vector(28510,AMPL_WIDTH),
conv_std_logic_vector(28512,AMPL_WIDTH),
conv_std_logic_vector(28513,AMPL_WIDTH),
conv_std_logic_vector(28515,AMPL_WIDTH),
conv_std_logic_vector(28516,AMPL_WIDTH),
conv_std_logic_vector(28518,AMPL_WIDTH),
conv_std_logic_vector(28519,AMPL_WIDTH),
conv_std_logic_vector(28521,AMPL_WIDTH),
conv_std_logic_vector(28523,AMPL_WIDTH),
conv_std_logic_vector(28524,AMPL_WIDTH),
conv_std_logic_vector(28526,AMPL_WIDTH),
conv_std_logic_vector(28527,AMPL_WIDTH),
conv_std_logic_vector(28529,AMPL_WIDTH),
conv_std_logic_vector(28530,AMPL_WIDTH),
conv_std_logic_vector(28532,AMPL_WIDTH),
conv_std_logic_vector(28533,AMPL_WIDTH),
conv_std_logic_vector(28535,AMPL_WIDTH),
conv_std_logic_vector(28536,AMPL_WIDTH),
conv_std_logic_vector(28538,AMPL_WIDTH),
conv_std_logic_vector(28540,AMPL_WIDTH),
conv_std_logic_vector(28541,AMPL_WIDTH),
conv_std_logic_vector(28543,AMPL_WIDTH),
conv_std_logic_vector(28544,AMPL_WIDTH),
conv_std_logic_vector(28546,AMPL_WIDTH),
conv_std_logic_vector(28547,AMPL_WIDTH),
conv_std_logic_vector(28549,AMPL_WIDTH),
conv_std_logic_vector(28550,AMPL_WIDTH),
conv_std_logic_vector(28552,AMPL_WIDTH),
conv_std_logic_vector(28553,AMPL_WIDTH),
conv_std_logic_vector(28555,AMPL_WIDTH),
conv_std_logic_vector(28556,AMPL_WIDTH),
conv_std_logic_vector(28558,AMPL_WIDTH),
conv_std_logic_vector(28560,AMPL_WIDTH),
conv_std_logic_vector(28561,AMPL_WIDTH),
conv_std_logic_vector(28563,AMPL_WIDTH),
conv_std_logic_vector(28564,AMPL_WIDTH),
conv_std_logic_vector(28566,AMPL_WIDTH),
conv_std_logic_vector(28567,AMPL_WIDTH),
conv_std_logic_vector(28569,AMPL_WIDTH),
conv_std_logic_vector(28570,AMPL_WIDTH),
conv_std_logic_vector(28572,AMPL_WIDTH),
conv_std_logic_vector(28573,AMPL_WIDTH),
conv_std_logic_vector(28575,AMPL_WIDTH),
conv_std_logic_vector(28576,AMPL_WIDTH),
conv_std_logic_vector(28578,AMPL_WIDTH),
conv_std_logic_vector(28580,AMPL_WIDTH),
conv_std_logic_vector(28581,AMPL_WIDTH),
conv_std_logic_vector(28583,AMPL_WIDTH),
conv_std_logic_vector(28584,AMPL_WIDTH),
conv_std_logic_vector(28586,AMPL_WIDTH),
conv_std_logic_vector(28587,AMPL_WIDTH),
conv_std_logic_vector(28589,AMPL_WIDTH),
conv_std_logic_vector(28590,AMPL_WIDTH),
conv_std_logic_vector(28592,AMPL_WIDTH),
conv_std_logic_vector(28593,AMPL_WIDTH),
conv_std_logic_vector(28595,AMPL_WIDTH),
conv_std_logic_vector(28596,AMPL_WIDTH),
conv_std_logic_vector(28598,AMPL_WIDTH),
conv_std_logic_vector(28600,AMPL_WIDTH),
conv_std_logic_vector(28601,AMPL_WIDTH),
conv_std_logic_vector(28603,AMPL_WIDTH),
conv_std_logic_vector(28604,AMPL_WIDTH),
conv_std_logic_vector(28606,AMPL_WIDTH),
conv_std_logic_vector(28607,AMPL_WIDTH),
conv_std_logic_vector(28609,AMPL_WIDTH),
conv_std_logic_vector(28610,AMPL_WIDTH),
conv_std_logic_vector(28612,AMPL_WIDTH),
conv_std_logic_vector(28613,AMPL_WIDTH),
conv_std_logic_vector(28615,AMPL_WIDTH),
conv_std_logic_vector(28616,AMPL_WIDTH),
conv_std_logic_vector(28618,AMPL_WIDTH),
conv_std_logic_vector(28619,AMPL_WIDTH),
conv_std_logic_vector(28621,AMPL_WIDTH),
conv_std_logic_vector(28622,AMPL_WIDTH),
conv_std_logic_vector(28624,AMPL_WIDTH),
conv_std_logic_vector(28626,AMPL_WIDTH),
conv_std_logic_vector(28627,AMPL_WIDTH),
conv_std_logic_vector(28629,AMPL_WIDTH),
conv_std_logic_vector(28630,AMPL_WIDTH),
conv_std_logic_vector(28632,AMPL_WIDTH),
conv_std_logic_vector(28633,AMPL_WIDTH),
conv_std_logic_vector(28635,AMPL_WIDTH),
conv_std_logic_vector(28636,AMPL_WIDTH),
conv_std_logic_vector(28638,AMPL_WIDTH),
conv_std_logic_vector(28639,AMPL_WIDTH),
conv_std_logic_vector(28641,AMPL_WIDTH),
conv_std_logic_vector(28642,AMPL_WIDTH),
conv_std_logic_vector(28644,AMPL_WIDTH),
conv_std_logic_vector(28645,AMPL_WIDTH),
conv_std_logic_vector(28647,AMPL_WIDTH),
conv_std_logic_vector(28648,AMPL_WIDTH),
conv_std_logic_vector(28650,AMPL_WIDTH),
conv_std_logic_vector(28651,AMPL_WIDTH),
conv_std_logic_vector(28653,AMPL_WIDTH),
conv_std_logic_vector(28655,AMPL_WIDTH),
conv_std_logic_vector(28656,AMPL_WIDTH),
conv_std_logic_vector(28658,AMPL_WIDTH),
conv_std_logic_vector(28659,AMPL_WIDTH),
conv_std_logic_vector(28661,AMPL_WIDTH),
conv_std_logic_vector(28662,AMPL_WIDTH),
conv_std_logic_vector(28664,AMPL_WIDTH),
conv_std_logic_vector(28665,AMPL_WIDTH),
conv_std_logic_vector(28667,AMPL_WIDTH),
conv_std_logic_vector(28668,AMPL_WIDTH),
conv_std_logic_vector(28670,AMPL_WIDTH),
conv_std_logic_vector(28671,AMPL_WIDTH),
conv_std_logic_vector(28673,AMPL_WIDTH),
conv_std_logic_vector(28674,AMPL_WIDTH),
conv_std_logic_vector(28676,AMPL_WIDTH),
conv_std_logic_vector(28677,AMPL_WIDTH),
conv_std_logic_vector(28679,AMPL_WIDTH),
conv_std_logic_vector(28680,AMPL_WIDTH),
conv_std_logic_vector(28682,AMPL_WIDTH),
conv_std_logic_vector(28683,AMPL_WIDTH),
conv_std_logic_vector(28685,AMPL_WIDTH),
conv_std_logic_vector(28686,AMPL_WIDTH),
conv_std_logic_vector(28688,AMPL_WIDTH),
conv_std_logic_vector(28690,AMPL_WIDTH),
conv_std_logic_vector(28691,AMPL_WIDTH),
conv_std_logic_vector(28693,AMPL_WIDTH),
conv_std_logic_vector(28694,AMPL_WIDTH),
conv_std_logic_vector(28696,AMPL_WIDTH),
conv_std_logic_vector(28697,AMPL_WIDTH),
conv_std_logic_vector(28699,AMPL_WIDTH),
conv_std_logic_vector(28700,AMPL_WIDTH),
conv_std_logic_vector(28702,AMPL_WIDTH),
conv_std_logic_vector(28703,AMPL_WIDTH),
conv_std_logic_vector(28705,AMPL_WIDTH),
conv_std_logic_vector(28706,AMPL_WIDTH),
conv_std_logic_vector(28708,AMPL_WIDTH),
conv_std_logic_vector(28709,AMPL_WIDTH),
conv_std_logic_vector(28711,AMPL_WIDTH),
conv_std_logic_vector(28712,AMPL_WIDTH),
conv_std_logic_vector(28714,AMPL_WIDTH),
conv_std_logic_vector(28715,AMPL_WIDTH),
conv_std_logic_vector(28717,AMPL_WIDTH),
conv_std_logic_vector(28718,AMPL_WIDTH),
conv_std_logic_vector(28720,AMPL_WIDTH),
conv_std_logic_vector(28721,AMPL_WIDTH),
conv_std_logic_vector(28723,AMPL_WIDTH),
conv_std_logic_vector(28724,AMPL_WIDTH),
conv_std_logic_vector(28726,AMPL_WIDTH),
conv_std_logic_vector(28727,AMPL_WIDTH),
conv_std_logic_vector(28729,AMPL_WIDTH),
conv_std_logic_vector(28730,AMPL_WIDTH),
conv_std_logic_vector(28732,AMPL_WIDTH),
conv_std_logic_vector(28733,AMPL_WIDTH),
conv_std_logic_vector(28735,AMPL_WIDTH),
conv_std_logic_vector(28736,AMPL_WIDTH),
conv_std_logic_vector(28738,AMPL_WIDTH),
conv_std_logic_vector(28739,AMPL_WIDTH),
conv_std_logic_vector(28741,AMPL_WIDTH),
conv_std_logic_vector(28742,AMPL_WIDTH),
conv_std_logic_vector(28744,AMPL_WIDTH),
conv_std_logic_vector(28745,AMPL_WIDTH),
conv_std_logic_vector(28747,AMPL_WIDTH),
conv_std_logic_vector(28748,AMPL_WIDTH),
conv_std_logic_vector(28750,AMPL_WIDTH),
conv_std_logic_vector(28752,AMPL_WIDTH),
conv_std_logic_vector(28753,AMPL_WIDTH),
conv_std_logic_vector(28755,AMPL_WIDTH),
conv_std_logic_vector(28756,AMPL_WIDTH),
conv_std_logic_vector(28758,AMPL_WIDTH),
conv_std_logic_vector(28759,AMPL_WIDTH),
conv_std_logic_vector(28761,AMPL_WIDTH),
conv_std_logic_vector(28762,AMPL_WIDTH),
conv_std_logic_vector(28764,AMPL_WIDTH),
conv_std_logic_vector(28765,AMPL_WIDTH),
conv_std_logic_vector(28767,AMPL_WIDTH),
conv_std_logic_vector(28768,AMPL_WIDTH),
conv_std_logic_vector(28770,AMPL_WIDTH),
conv_std_logic_vector(28771,AMPL_WIDTH),
conv_std_logic_vector(28773,AMPL_WIDTH),
conv_std_logic_vector(28774,AMPL_WIDTH),
conv_std_logic_vector(28776,AMPL_WIDTH),
conv_std_logic_vector(28777,AMPL_WIDTH),
conv_std_logic_vector(28779,AMPL_WIDTH),
conv_std_logic_vector(28780,AMPL_WIDTH),
conv_std_logic_vector(28782,AMPL_WIDTH),
conv_std_logic_vector(28783,AMPL_WIDTH),
conv_std_logic_vector(28785,AMPL_WIDTH),
conv_std_logic_vector(28786,AMPL_WIDTH),
conv_std_logic_vector(28788,AMPL_WIDTH),
conv_std_logic_vector(28789,AMPL_WIDTH),
conv_std_logic_vector(28791,AMPL_WIDTH),
conv_std_logic_vector(28792,AMPL_WIDTH),
conv_std_logic_vector(28794,AMPL_WIDTH),
conv_std_logic_vector(28795,AMPL_WIDTH),
conv_std_logic_vector(28797,AMPL_WIDTH),
conv_std_logic_vector(28798,AMPL_WIDTH),
conv_std_logic_vector(28800,AMPL_WIDTH),
conv_std_logic_vector(28801,AMPL_WIDTH),
conv_std_logic_vector(28803,AMPL_WIDTH),
conv_std_logic_vector(28804,AMPL_WIDTH),
conv_std_logic_vector(28806,AMPL_WIDTH),
conv_std_logic_vector(28807,AMPL_WIDTH),
conv_std_logic_vector(28809,AMPL_WIDTH),
conv_std_logic_vector(28810,AMPL_WIDTH),
conv_std_logic_vector(28812,AMPL_WIDTH),
conv_std_logic_vector(28813,AMPL_WIDTH),
conv_std_logic_vector(28815,AMPL_WIDTH),
conv_std_logic_vector(28816,AMPL_WIDTH),
conv_std_logic_vector(28818,AMPL_WIDTH),
conv_std_logic_vector(28819,AMPL_WIDTH),
conv_std_logic_vector(28821,AMPL_WIDTH),
conv_std_logic_vector(28822,AMPL_WIDTH),
conv_std_logic_vector(28824,AMPL_WIDTH),
conv_std_logic_vector(28825,AMPL_WIDTH),
conv_std_logic_vector(28827,AMPL_WIDTH),
conv_std_logic_vector(28828,AMPL_WIDTH),
conv_std_logic_vector(28830,AMPL_WIDTH),
conv_std_logic_vector(28831,AMPL_WIDTH),
conv_std_logic_vector(28832,AMPL_WIDTH),
conv_std_logic_vector(28834,AMPL_WIDTH),
conv_std_logic_vector(28835,AMPL_WIDTH),
conv_std_logic_vector(28837,AMPL_WIDTH),
conv_std_logic_vector(28838,AMPL_WIDTH),
conv_std_logic_vector(28840,AMPL_WIDTH),
conv_std_logic_vector(28841,AMPL_WIDTH),
conv_std_logic_vector(28843,AMPL_WIDTH),
conv_std_logic_vector(28844,AMPL_WIDTH),
conv_std_logic_vector(28846,AMPL_WIDTH),
conv_std_logic_vector(28847,AMPL_WIDTH),
conv_std_logic_vector(28849,AMPL_WIDTH),
conv_std_logic_vector(28850,AMPL_WIDTH),
conv_std_logic_vector(28852,AMPL_WIDTH),
conv_std_logic_vector(28853,AMPL_WIDTH),
conv_std_logic_vector(28855,AMPL_WIDTH),
conv_std_logic_vector(28856,AMPL_WIDTH),
conv_std_logic_vector(28858,AMPL_WIDTH),
conv_std_logic_vector(28859,AMPL_WIDTH),
conv_std_logic_vector(28861,AMPL_WIDTH),
conv_std_logic_vector(28862,AMPL_WIDTH),
conv_std_logic_vector(28864,AMPL_WIDTH),
conv_std_logic_vector(28865,AMPL_WIDTH),
conv_std_logic_vector(28867,AMPL_WIDTH),
conv_std_logic_vector(28868,AMPL_WIDTH),
conv_std_logic_vector(28870,AMPL_WIDTH),
conv_std_logic_vector(28871,AMPL_WIDTH),
conv_std_logic_vector(28873,AMPL_WIDTH),
conv_std_logic_vector(28874,AMPL_WIDTH),
conv_std_logic_vector(28876,AMPL_WIDTH),
conv_std_logic_vector(28877,AMPL_WIDTH),
conv_std_logic_vector(28879,AMPL_WIDTH),
conv_std_logic_vector(28880,AMPL_WIDTH),
conv_std_logic_vector(28882,AMPL_WIDTH),
conv_std_logic_vector(28883,AMPL_WIDTH),
conv_std_logic_vector(28885,AMPL_WIDTH),
conv_std_logic_vector(28886,AMPL_WIDTH),
conv_std_logic_vector(28888,AMPL_WIDTH),
conv_std_logic_vector(28889,AMPL_WIDTH),
conv_std_logic_vector(28891,AMPL_WIDTH),
conv_std_logic_vector(28892,AMPL_WIDTH),
conv_std_logic_vector(28893,AMPL_WIDTH),
conv_std_logic_vector(28895,AMPL_WIDTH),
conv_std_logic_vector(28896,AMPL_WIDTH),
conv_std_logic_vector(28898,AMPL_WIDTH),
conv_std_logic_vector(28899,AMPL_WIDTH),
conv_std_logic_vector(28901,AMPL_WIDTH),
conv_std_logic_vector(28902,AMPL_WIDTH),
conv_std_logic_vector(28904,AMPL_WIDTH),
conv_std_logic_vector(28905,AMPL_WIDTH),
conv_std_logic_vector(28907,AMPL_WIDTH),
conv_std_logic_vector(28908,AMPL_WIDTH),
conv_std_logic_vector(28910,AMPL_WIDTH),
conv_std_logic_vector(28911,AMPL_WIDTH),
conv_std_logic_vector(28913,AMPL_WIDTH),
conv_std_logic_vector(28914,AMPL_WIDTH),
conv_std_logic_vector(28916,AMPL_WIDTH),
conv_std_logic_vector(28917,AMPL_WIDTH),
conv_std_logic_vector(28919,AMPL_WIDTH),
conv_std_logic_vector(28920,AMPL_WIDTH),
conv_std_logic_vector(28922,AMPL_WIDTH),
conv_std_logic_vector(28923,AMPL_WIDTH),
conv_std_logic_vector(28925,AMPL_WIDTH),
conv_std_logic_vector(28926,AMPL_WIDTH),
conv_std_logic_vector(28927,AMPL_WIDTH),
conv_std_logic_vector(28929,AMPL_WIDTH),
conv_std_logic_vector(28930,AMPL_WIDTH),
conv_std_logic_vector(28932,AMPL_WIDTH),
conv_std_logic_vector(28933,AMPL_WIDTH),
conv_std_logic_vector(28935,AMPL_WIDTH),
conv_std_logic_vector(28936,AMPL_WIDTH),
conv_std_logic_vector(28938,AMPL_WIDTH),
conv_std_logic_vector(28939,AMPL_WIDTH),
conv_std_logic_vector(28941,AMPL_WIDTH),
conv_std_logic_vector(28942,AMPL_WIDTH),
conv_std_logic_vector(28944,AMPL_WIDTH),
conv_std_logic_vector(28945,AMPL_WIDTH),
conv_std_logic_vector(28947,AMPL_WIDTH),
conv_std_logic_vector(28948,AMPL_WIDTH),
conv_std_logic_vector(28950,AMPL_WIDTH),
conv_std_logic_vector(28951,AMPL_WIDTH),
conv_std_logic_vector(28953,AMPL_WIDTH),
conv_std_logic_vector(28954,AMPL_WIDTH),
conv_std_logic_vector(28955,AMPL_WIDTH),
conv_std_logic_vector(28957,AMPL_WIDTH),
conv_std_logic_vector(28958,AMPL_WIDTH),
conv_std_logic_vector(28960,AMPL_WIDTH),
conv_std_logic_vector(28961,AMPL_WIDTH),
conv_std_logic_vector(28963,AMPL_WIDTH),
conv_std_logic_vector(28964,AMPL_WIDTH),
conv_std_logic_vector(28966,AMPL_WIDTH),
conv_std_logic_vector(28967,AMPL_WIDTH),
conv_std_logic_vector(28969,AMPL_WIDTH),
conv_std_logic_vector(28970,AMPL_WIDTH),
conv_std_logic_vector(28972,AMPL_WIDTH),
conv_std_logic_vector(28973,AMPL_WIDTH),
conv_std_logic_vector(28975,AMPL_WIDTH),
conv_std_logic_vector(28976,AMPL_WIDTH),
conv_std_logic_vector(28977,AMPL_WIDTH),
conv_std_logic_vector(28979,AMPL_WIDTH),
conv_std_logic_vector(28980,AMPL_WIDTH),
conv_std_logic_vector(28982,AMPL_WIDTH),
conv_std_logic_vector(28983,AMPL_WIDTH),
conv_std_logic_vector(28985,AMPL_WIDTH),
conv_std_logic_vector(28986,AMPL_WIDTH),
conv_std_logic_vector(28988,AMPL_WIDTH),
conv_std_logic_vector(28989,AMPL_WIDTH),
conv_std_logic_vector(28991,AMPL_WIDTH),
conv_std_logic_vector(28992,AMPL_WIDTH),
conv_std_logic_vector(28994,AMPL_WIDTH),
conv_std_logic_vector(28995,AMPL_WIDTH),
conv_std_logic_vector(28997,AMPL_WIDTH),
conv_std_logic_vector(28998,AMPL_WIDTH),
conv_std_logic_vector(28999,AMPL_WIDTH),
conv_std_logic_vector(29001,AMPL_WIDTH),
conv_std_logic_vector(29002,AMPL_WIDTH),
conv_std_logic_vector(29004,AMPL_WIDTH),
conv_std_logic_vector(29005,AMPL_WIDTH),
conv_std_logic_vector(29007,AMPL_WIDTH),
conv_std_logic_vector(29008,AMPL_WIDTH),
conv_std_logic_vector(29010,AMPL_WIDTH),
conv_std_logic_vector(29011,AMPL_WIDTH),
conv_std_logic_vector(29013,AMPL_WIDTH),
conv_std_logic_vector(29014,AMPL_WIDTH),
conv_std_logic_vector(29016,AMPL_WIDTH),
conv_std_logic_vector(29017,AMPL_WIDTH),
conv_std_logic_vector(29018,AMPL_WIDTH),
conv_std_logic_vector(29020,AMPL_WIDTH),
conv_std_logic_vector(29021,AMPL_WIDTH),
conv_std_logic_vector(29023,AMPL_WIDTH),
conv_std_logic_vector(29024,AMPL_WIDTH),
conv_std_logic_vector(29026,AMPL_WIDTH),
conv_std_logic_vector(29027,AMPL_WIDTH),
conv_std_logic_vector(29029,AMPL_WIDTH),
conv_std_logic_vector(29030,AMPL_WIDTH),
conv_std_logic_vector(29032,AMPL_WIDTH),
conv_std_logic_vector(29033,AMPL_WIDTH),
conv_std_logic_vector(29034,AMPL_WIDTH),
conv_std_logic_vector(29036,AMPL_WIDTH),
conv_std_logic_vector(29037,AMPL_WIDTH),
conv_std_logic_vector(29039,AMPL_WIDTH),
conv_std_logic_vector(29040,AMPL_WIDTH),
conv_std_logic_vector(29042,AMPL_WIDTH),
conv_std_logic_vector(29043,AMPL_WIDTH),
conv_std_logic_vector(29045,AMPL_WIDTH),
conv_std_logic_vector(29046,AMPL_WIDTH),
conv_std_logic_vector(29048,AMPL_WIDTH),
conv_std_logic_vector(29049,AMPL_WIDTH),
conv_std_logic_vector(29050,AMPL_WIDTH),
conv_std_logic_vector(29052,AMPL_WIDTH),
conv_std_logic_vector(29053,AMPL_WIDTH),
conv_std_logic_vector(29055,AMPL_WIDTH),
conv_std_logic_vector(29056,AMPL_WIDTH),
conv_std_logic_vector(29058,AMPL_WIDTH),
conv_std_logic_vector(29059,AMPL_WIDTH),
conv_std_logic_vector(29061,AMPL_WIDTH),
conv_std_logic_vector(29062,AMPL_WIDTH),
conv_std_logic_vector(29064,AMPL_WIDTH),
conv_std_logic_vector(29065,AMPL_WIDTH),
conv_std_logic_vector(29066,AMPL_WIDTH),
conv_std_logic_vector(29068,AMPL_WIDTH),
conv_std_logic_vector(29069,AMPL_WIDTH),
conv_std_logic_vector(29071,AMPL_WIDTH),
conv_std_logic_vector(29072,AMPL_WIDTH),
conv_std_logic_vector(29074,AMPL_WIDTH),
conv_std_logic_vector(29075,AMPL_WIDTH),
conv_std_logic_vector(29077,AMPL_WIDTH),
conv_std_logic_vector(29078,AMPL_WIDTH),
conv_std_logic_vector(29079,AMPL_WIDTH),
conv_std_logic_vector(29081,AMPL_WIDTH),
conv_std_logic_vector(29082,AMPL_WIDTH),
conv_std_logic_vector(29084,AMPL_WIDTH),
conv_std_logic_vector(29085,AMPL_WIDTH),
conv_std_logic_vector(29087,AMPL_WIDTH),
conv_std_logic_vector(29088,AMPL_WIDTH),
conv_std_logic_vector(29090,AMPL_WIDTH),
conv_std_logic_vector(29091,AMPL_WIDTH),
conv_std_logic_vector(29093,AMPL_WIDTH),
conv_std_logic_vector(29094,AMPL_WIDTH),
conv_std_logic_vector(29095,AMPL_WIDTH),
conv_std_logic_vector(29097,AMPL_WIDTH),
conv_std_logic_vector(29098,AMPL_WIDTH),
conv_std_logic_vector(29100,AMPL_WIDTH),
conv_std_logic_vector(29101,AMPL_WIDTH),
conv_std_logic_vector(29103,AMPL_WIDTH),
conv_std_logic_vector(29104,AMPL_WIDTH),
conv_std_logic_vector(29106,AMPL_WIDTH),
conv_std_logic_vector(29107,AMPL_WIDTH),
conv_std_logic_vector(29108,AMPL_WIDTH),
conv_std_logic_vector(29110,AMPL_WIDTH),
conv_std_logic_vector(29111,AMPL_WIDTH),
conv_std_logic_vector(29113,AMPL_WIDTH),
conv_std_logic_vector(29114,AMPL_WIDTH),
conv_std_logic_vector(29116,AMPL_WIDTH),
conv_std_logic_vector(29117,AMPL_WIDTH),
conv_std_logic_vector(29118,AMPL_WIDTH),
conv_std_logic_vector(29120,AMPL_WIDTH),
conv_std_logic_vector(29121,AMPL_WIDTH),
conv_std_logic_vector(29123,AMPL_WIDTH),
conv_std_logic_vector(29124,AMPL_WIDTH),
conv_std_logic_vector(29126,AMPL_WIDTH),
conv_std_logic_vector(29127,AMPL_WIDTH),
conv_std_logic_vector(29129,AMPL_WIDTH),
conv_std_logic_vector(29130,AMPL_WIDTH),
conv_std_logic_vector(29131,AMPL_WIDTH),
conv_std_logic_vector(29133,AMPL_WIDTH),
conv_std_logic_vector(29134,AMPL_WIDTH),
conv_std_logic_vector(29136,AMPL_WIDTH),
conv_std_logic_vector(29137,AMPL_WIDTH),
conv_std_logic_vector(29139,AMPL_WIDTH),
conv_std_logic_vector(29140,AMPL_WIDTH),
conv_std_logic_vector(29142,AMPL_WIDTH),
conv_std_logic_vector(29143,AMPL_WIDTH),
conv_std_logic_vector(29144,AMPL_WIDTH),
conv_std_logic_vector(29146,AMPL_WIDTH),
conv_std_logic_vector(29147,AMPL_WIDTH),
conv_std_logic_vector(29149,AMPL_WIDTH),
conv_std_logic_vector(29150,AMPL_WIDTH),
conv_std_logic_vector(29152,AMPL_WIDTH),
conv_std_logic_vector(29153,AMPL_WIDTH),
conv_std_logic_vector(29154,AMPL_WIDTH),
conv_std_logic_vector(29156,AMPL_WIDTH),
conv_std_logic_vector(29157,AMPL_WIDTH),
conv_std_logic_vector(29159,AMPL_WIDTH),
conv_std_logic_vector(29160,AMPL_WIDTH),
conv_std_logic_vector(29162,AMPL_WIDTH),
conv_std_logic_vector(29163,AMPL_WIDTH),
conv_std_logic_vector(29164,AMPL_WIDTH),
conv_std_logic_vector(29166,AMPL_WIDTH),
conv_std_logic_vector(29167,AMPL_WIDTH),
conv_std_logic_vector(29169,AMPL_WIDTH),
conv_std_logic_vector(29170,AMPL_WIDTH),
conv_std_logic_vector(29172,AMPL_WIDTH),
conv_std_logic_vector(29173,AMPL_WIDTH),
conv_std_logic_vector(29174,AMPL_WIDTH),
conv_std_logic_vector(29176,AMPL_WIDTH),
conv_std_logic_vector(29177,AMPL_WIDTH),
conv_std_logic_vector(29179,AMPL_WIDTH),
conv_std_logic_vector(29180,AMPL_WIDTH),
conv_std_logic_vector(29182,AMPL_WIDTH),
conv_std_logic_vector(29183,AMPL_WIDTH),
conv_std_logic_vector(29184,AMPL_WIDTH),
conv_std_logic_vector(29186,AMPL_WIDTH),
conv_std_logic_vector(29187,AMPL_WIDTH),
conv_std_logic_vector(29189,AMPL_WIDTH),
conv_std_logic_vector(29190,AMPL_WIDTH),
conv_std_logic_vector(29192,AMPL_WIDTH),
conv_std_logic_vector(29193,AMPL_WIDTH),
conv_std_logic_vector(29194,AMPL_WIDTH),
conv_std_logic_vector(29196,AMPL_WIDTH),
conv_std_logic_vector(29197,AMPL_WIDTH),
conv_std_logic_vector(29199,AMPL_WIDTH),
conv_std_logic_vector(29200,AMPL_WIDTH),
conv_std_logic_vector(29202,AMPL_WIDTH),
conv_std_logic_vector(29203,AMPL_WIDTH),
conv_std_logic_vector(29204,AMPL_WIDTH),
conv_std_logic_vector(29206,AMPL_WIDTH),
conv_std_logic_vector(29207,AMPL_WIDTH),
conv_std_logic_vector(29209,AMPL_WIDTH),
conv_std_logic_vector(29210,AMPL_WIDTH),
conv_std_logic_vector(29212,AMPL_WIDTH),
conv_std_logic_vector(29213,AMPL_WIDTH),
conv_std_logic_vector(29214,AMPL_WIDTH),
conv_std_logic_vector(29216,AMPL_WIDTH),
conv_std_logic_vector(29217,AMPL_WIDTH),
conv_std_logic_vector(29219,AMPL_WIDTH),
conv_std_logic_vector(29220,AMPL_WIDTH),
conv_std_logic_vector(29222,AMPL_WIDTH),
conv_std_logic_vector(29223,AMPL_WIDTH),
conv_std_logic_vector(29224,AMPL_WIDTH),
conv_std_logic_vector(29226,AMPL_WIDTH),
conv_std_logic_vector(29227,AMPL_WIDTH),
conv_std_logic_vector(29229,AMPL_WIDTH),
conv_std_logic_vector(29230,AMPL_WIDTH),
conv_std_logic_vector(29231,AMPL_WIDTH),
conv_std_logic_vector(29233,AMPL_WIDTH),
conv_std_logic_vector(29234,AMPL_WIDTH),
conv_std_logic_vector(29236,AMPL_WIDTH),
conv_std_logic_vector(29237,AMPL_WIDTH),
conv_std_logic_vector(29239,AMPL_WIDTH),
conv_std_logic_vector(29240,AMPL_WIDTH),
conv_std_logic_vector(29241,AMPL_WIDTH),
conv_std_logic_vector(29243,AMPL_WIDTH),
conv_std_logic_vector(29244,AMPL_WIDTH),
conv_std_logic_vector(29246,AMPL_WIDTH),
conv_std_logic_vector(29247,AMPL_WIDTH),
conv_std_logic_vector(29248,AMPL_WIDTH),
conv_std_logic_vector(29250,AMPL_WIDTH),
conv_std_logic_vector(29251,AMPL_WIDTH),
conv_std_logic_vector(29253,AMPL_WIDTH),
conv_std_logic_vector(29254,AMPL_WIDTH),
conv_std_logic_vector(29256,AMPL_WIDTH),
conv_std_logic_vector(29257,AMPL_WIDTH),
conv_std_logic_vector(29258,AMPL_WIDTH),
conv_std_logic_vector(29260,AMPL_WIDTH),
conv_std_logic_vector(29261,AMPL_WIDTH),
conv_std_logic_vector(29263,AMPL_WIDTH),
conv_std_logic_vector(29264,AMPL_WIDTH),
conv_std_logic_vector(29265,AMPL_WIDTH),
conv_std_logic_vector(29267,AMPL_WIDTH),
conv_std_logic_vector(29268,AMPL_WIDTH),
conv_std_logic_vector(29270,AMPL_WIDTH),
conv_std_logic_vector(29271,AMPL_WIDTH),
conv_std_logic_vector(29273,AMPL_WIDTH),
conv_std_logic_vector(29274,AMPL_WIDTH),
conv_std_logic_vector(29275,AMPL_WIDTH),
conv_std_logic_vector(29277,AMPL_WIDTH),
conv_std_logic_vector(29278,AMPL_WIDTH),
conv_std_logic_vector(29280,AMPL_WIDTH),
conv_std_logic_vector(29281,AMPL_WIDTH),
conv_std_logic_vector(29282,AMPL_WIDTH),
conv_std_logic_vector(29284,AMPL_WIDTH),
conv_std_logic_vector(29285,AMPL_WIDTH),
conv_std_logic_vector(29287,AMPL_WIDTH),
conv_std_logic_vector(29288,AMPL_WIDTH),
conv_std_logic_vector(29289,AMPL_WIDTH),
conv_std_logic_vector(29291,AMPL_WIDTH),
conv_std_logic_vector(29292,AMPL_WIDTH),
conv_std_logic_vector(29294,AMPL_WIDTH),
conv_std_logic_vector(29295,AMPL_WIDTH),
conv_std_logic_vector(29296,AMPL_WIDTH),
conv_std_logic_vector(29298,AMPL_WIDTH),
conv_std_logic_vector(29299,AMPL_WIDTH),
conv_std_logic_vector(29301,AMPL_WIDTH),
conv_std_logic_vector(29302,AMPL_WIDTH),
conv_std_logic_vector(29304,AMPL_WIDTH),
conv_std_logic_vector(29305,AMPL_WIDTH),
conv_std_logic_vector(29306,AMPL_WIDTH),
conv_std_logic_vector(29308,AMPL_WIDTH),
conv_std_logic_vector(29309,AMPL_WIDTH),
conv_std_logic_vector(29311,AMPL_WIDTH),
conv_std_logic_vector(29312,AMPL_WIDTH),
conv_std_logic_vector(29313,AMPL_WIDTH),
conv_std_logic_vector(29315,AMPL_WIDTH),
conv_std_logic_vector(29316,AMPL_WIDTH),
conv_std_logic_vector(29318,AMPL_WIDTH),
conv_std_logic_vector(29319,AMPL_WIDTH),
conv_std_logic_vector(29320,AMPL_WIDTH),
conv_std_logic_vector(29322,AMPL_WIDTH),
conv_std_logic_vector(29323,AMPL_WIDTH),
conv_std_logic_vector(29325,AMPL_WIDTH),
conv_std_logic_vector(29326,AMPL_WIDTH),
conv_std_logic_vector(29327,AMPL_WIDTH),
conv_std_logic_vector(29329,AMPL_WIDTH),
conv_std_logic_vector(29330,AMPL_WIDTH),
conv_std_logic_vector(29332,AMPL_WIDTH),
conv_std_logic_vector(29333,AMPL_WIDTH),
conv_std_logic_vector(29334,AMPL_WIDTH),
conv_std_logic_vector(29336,AMPL_WIDTH),
conv_std_logic_vector(29337,AMPL_WIDTH),
conv_std_logic_vector(29339,AMPL_WIDTH),
conv_std_logic_vector(29340,AMPL_WIDTH),
conv_std_logic_vector(29341,AMPL_WIDTH),
conv_std_logic_vector(29343,AMPL_WIDTH),
conv_std_logic_vector(29344,AMPL_WIDTH),
conv_std_logic_vector(29346,AMPL_WIDTH),
conv_std_logic_vector(29347,AMPL_WIDTH),
conv_std_logic_vector(29348,AMPL_WIDTH),
conv_std_logic_vector(29350,AMPL_WIDTH),
conv_std_logic_vector(29351,AMPL_WIDTH),
conv_std_logic_vector(29353,AMPL_WIDTH),
conv_std_logic_vector(29354,AMPL_WIDTH),
conv_std_logic_vector(29355,AMPL_WIDTH),
conv_std_logic_vector(29357,AMPL_WIDTH),
conv_std_logic_vector(29358,AMPL_WIDTH),
conv_std_logic_vector(29360,AMPL_WIDTH),
conv_std_logic_vector(29361,AMPL_WIDTH),
conv_std_logic_vector(29362,AMPL_WIDTH),
conv_std_logic_vector(29364,AMPL_WIDTH),
conv_std_logic_vector(29365,AMPL_WIDTH),
conv_std_logic_vector(29366,AMPL_WIDTH),
conv_std_logic_vector(29368,AMPL_WIDTH),
conv_std_logic_vector(29369,AMPL_WIDTH),
conv_std_logic_vector(29371,AMPL_WIDTH),
conv_std_logic_vector(29372,AMPL_WIDTH),
conv_std_logic_vector(29373,AMPL_WIDTH),
conv_std_logic_vector(29375,AMPL_WIDTH),
conv_std_logic_vector(29376,AMPL_WIDTH),
conv_std_logic_vector(29378,AMPL_WIDTH),
conv_std_logic_vector(29379,AMPL_WIDTH),
conv_std_logic_vector(29380,AMPL_WIDTH),
conv_std_logic_vector(29382,AMPL_WIDTH),
conv_std_logic_vector(29383,AMPL_WIDTH),
conv_std_logic_vector(29385,AMPL_WIDTH),
conv_std_logic_vector(29386,AMPL_WIDTH),
conv_std_logic_vector(29387,AMPL_WIDTH),
conv_std_logic_vector(29389,AMPL_WIDTH),
conv_std_logic_vector(29390,AMPL_WIDTH),
conv_std_logic_vector(29392,AMPL_WIDTH),
conv_std_logic_vector(29393,AMPL_WIDTH),
conv_std_logic_vector(29394,AMPL_WIDTH),
conv_std_logic_vector(29396,AMPL_WIDTH),
conv_std_logic_vector(29397,AMPL_WIDTH),
conv_std_logic_vector(29398,AMPL_WIDTH),
conv_std_logic_vector(29400,AMPL_WIDTH),
conv_std_logic_vector(29401,AMPL_WIDTH),
conv_std_logic_vector(29403,AMPL_WIDTH),
conv_std_logic_vector(29404,AMPL_WIDTH),
conv_std_logic_vector(29405,AMPL_WIDTH),
conv_std_logic_vector(29407,AMPL_WIDTH),
conv_std_logic_vector(29408,AMPL_WIDTH),
conv_std_logic_vector(29410,AMPL_WIDTH),
conv_std_logic_vector(29411,AMPL_WIDTH),
conv_std_logic_vector(29412,AMPL_WIDTH),
conv_std_logic_vector(29414,AMPL_WIDTH),
conv_std_logic_vector(29415,AMPL_WIDTH),
conv_std_logic_vector(29416,AMPL_WIDTH),
conv_std_logic_vector(29418,AMPL_WIDTH),
conv_std_logic_vector(29419,AMPL_WIDTH),
conv_std_logic_vector(29421,AMPL_WIDTH),
conv_std_logic_vector(29422,AMPL_WIDTH),
conv_std_logic_vector(29423,AMPL_WIDTH),
conv_std_logic_vector(29425,AMPL_WIDTH),
conv_std_logic_vector(29426,AMPL_WIDTH),
conv_std_logic_vector(29428,AMPL_WIDTH),
conv_std_logic_vector(29429,AMPL_WIDTH),
conv_std_logic_vector(29430,AMPL_WIDTH),
conv_std_logic_vector(29432,AMPL_WIDTH),
conv_std_logic_vector(29433,AMPL_WIDTH),
conv_std_logic_vector(29434,AMPL_WIDTH),
conv_std_logic_vector(29436,AMPL_WIDTH),
conv_std_logic_vector(29437,AMPL_WIDTH),
conv_std_logic_vector(29439,AMPL_WIDTH),
conv_std_logic_vector(29440,AMPL_WIDTH),
conv_std_logic_vector(29441,AMPL_WIDTH),
conv_std_logic_vector(29443,AMPL_WIDTH),
conv_std_logic_vector(29444,AMPL_WIDTH),
conv_std_logic_vector(29445,AMPL_WIDTH),
conv_std_logic_vector(29447,AMPL_WIDTH),
conv_std_logic_vector(29448,AMPL_WIDTH),
conv_std_logic_vector(29450,AMPL_WIDTH),
conv_std_logic_vector(29451,AMPL_WIDTH),
conv_std_logic_vector(29452,AMPL_WIDTH),
conv_std_logic_vector(29454,AMPL_WIDTH),
conv_std_logic_vector(29455,AMPL_WIDTH),
conv_std_logic_vector(29457,AMPL_WIDTH),
conv_std_logic_vector(29458,AMPL_WIDTH),
conv_std_logic_vector(29459,AMPL_WIDTH),
conv_std_logic_vector(29461,AMPL_WIDTH),
conv_std_logic_vector(29462,AMPL_WIDTH),
conv_std_logic_vector(29463,AMPL_WIDTH),
conv_std_logic_vector(29465,AMPL_WIDTH),
conv_std_logic_vector(29466,AMPL_WIDTH),
conv_std_logic_vector(29468,AMPL_WIDTH),
conv_std_logic_vector(29469,AMPL_WIDTH),
conv_std_logic_vector(29470,AMPL_WIDTH),
conv_std_logic_vector(29472,AMPL_WIDTH),
conv_std_logic_vector(29473,AMPL_WIDTH),
conv_std_logic_vector(29474,AMPL_WIDTH),
conv_std_logic_vector(29476,AMPL_WIDTH),
conv_std_logic_vector(29477,AMPL_WIDTH),
conv_std_logic_vector(29478,AMPL_WIDTH),
conv_std_logic_vector(29480,AMPL_WIDTH),
conv_std_logic_vector(29481,AMPL_WIDTH),
conv_std_logic_vector(29483,AMPL_WIDTH),
conv_std_logic_vector(29484,AMPL_WIDTH),
conv_std_logic_vector(29485,AMPL_WIDTH),
conv_std_logic_vector(29487,AMPL_WIDTH),
conv_std_logic_vector(29488,AMPL_WIDTH),
conv_std_logic_vector(29489,AMPL_WIDTH),
conv_std_logic_vector(29491,AMPL_WIDTH),
conv_std_logic_vector(29492,AMPL_WIDTH),
conv_std_logic_vector(29494,AMPL_WIDTH),
conv_std_logic_vector(29495,AMPL_WIDTH),
conv_std_logic_vector(29496,AMPL_WIDTH),
conv_std_logic_vector(29498,AMPL_WIDTH),
conv_std_logic_vector(29499,AMPL_WIDTH),
conv_std_logic_vector(29500,AMPL_WIDTH),
conv_std_logic_vector(29502,AMPL_WIDTH),
conv_std_logic_vector(29503,AMPL_WIDTH),
conv_std_logic_vector(29504,AMPL_WIDTH),
conv_std_logic_vector(29506,AMPL_WIDTH),
conv_std_logic_vector(29507,AMPL_WIDTH),
conv_std_logic_vector(29509,AMPL_WIDTH),
conv_std_logic_vector(29510,AMPL_WIDTH),
conv_std_logic_vector(29511,AMPL_WIDTH),
conv_std_logic_vector(29513,AMPL_WIDTH),
conv_std_logic_vector(29514,AMPL_WIDTH),
conv_std_logic_vector(29515,AMPL_WIDTH),
conv_std_logic_vector(29517,AMPL_WIDTH),
conv_std_logic_vector(29518,AMPL_WIDTH),
conv_std_logic_vector(29520,AMPL_WIDTH),
conv_std_logic_vector(29521,AMPL_WIDTH),
conv_std_logic_vector(29522,AMPL_WIDTH),
conv_std_logic_vector(29524,AMPL_WIDTH),
conv_std_logic_vector(29525,AMPL_WIDTH),
conv_std_logic_vector(29526,AMPL_WIDTH),
conv_std_logic_vector(29528,AMPL_WIDTH),
conv_std_logic_vector(29529,AMPL_WIDTH),
conv_std_logic_vector(29530,AMPL_WIDTH),
conv_std_logic_vector(29532,AMPL_WIDTH),
conv_std_logic_vector(29533,AMPL_WIDTH),
conv_std_logic_vector(29534,AMPL_WIDTH),
conv_std_logic_vector(29536,AMPL_WIDTH),
conv_std_logic_vector(29537,AMPL_WIDTH),
conv_std_logic_vector(29539,AMPL_WIDTH),
conv_std_logic_vector(29540,AMPL_WIDTH),
conv_std_logic_vector(29541,AMPL_WIDTH),
conv_std_logic_vector(29543,AMPL_WIDTH),
conv_std_logic_vector(29544,AMPL_WIDTH),
conv_std_logic_vector(29545,AMPL_WIDTH),
conv_std_logic_vector(29547,AMPL_WIDTH),
conv_std_logic_vector(29548,AMPL_WIDTH),
conv_std_logic_vector(29549,AMPL_WIDTH),
conv_std_logic_vector(29551,AMPL_WIDTH),
conv_std_logic_vector(29552,AMPL_WIDTH),
conv_std_logic_vector(29554,AMPL_WIDTH),
conv_std_logic_vector(29555,AMPL_WIDTH),
conv_std_logic_vector(29556,AMPL_WIDTH),
conv_std_logic_vector(29558,AMPL_WIDTH),
conv_std_logic_vector(29559,AMPL_WIDTH),
conv_std_logic_vector(29560,AMPL_WIDTH),
conv_std_logic_vector(29562,AMPL_WIDTH),
conv_std_logic_vector(29563,AMPL_WIDTH),
conv_std_logic_vector(29564,AMPL_WIDTH),
conv_std_logic_vector(29566,AMPL_WIDTH),
conv_std_logic_vector(29567,AMPL_WIDTH),
conv_std_logic_vector(29568,AMPL_WIDTH),
conv_std_logic_vector(29570,AMPL_WIDTH),
conv_std_logic_vector(29571,AMPL_WIDTH),
conv_std_logic_vector(29572,AMPL_WIDTH),
conv_std_logic_vector(29574,AMPL_WIDTH),
conv_std_logic_vector(29575,AMPL_WIDTH),
conv_std_logic_vector(29577,AMPL_WIDTH),
conv_std_logic_vector(29578,AMPL_WIDTH),
conv_std_logic_vector(29579,AMPL_WIDTH),
conv_std_logic_vector(29581,AMPL_WIDTH),
conv_std_logic_vector(29582,AMPL_WIDTH),
conv_std_logic_vector(29583,AMPL_WIDTH),
conv_std_logic_vector(29585,AMPL_WIDTH),
conv_std_logic_vector(29586,AMPL_WIDTH),
conv_std_logic_vector(29587,AMPL_WIDTH),
conv_std_logic_vector(29589,AMPL_WIDTH),
conv_std_logic_vector(29590,AMPL_WIDTH),
conv_std_logic_vector(29591,AMPL_WIDTH),
conv_std_logic_vector(29593,AMPL_WIDTH),
conv_std_logic_vector(29594,AMPL_WIDTH),
conv_std_logic_vector(29595,AMPL_WIDTH),
conv_std_logic_vector(29597,AMPL_WIDTH),
conv_std_logic_vector(29598,AMPL_WIDTH),
conv_std_logic_vector(29599,AMPL_WIDTH),
conv_std_logic_vector(29601,AMPL_WIDTH),
conv_std_logic_vector(29602,AMPL_WIDTH),
conv_std_logic_vector(29604,AMPL_WIDTH),
conv_std_logic_vector(29605,AMPL_WIDTH),
conv_std_logic_vector(29606,AMPL_WIDTH),
conv_std_logic_vector(29608,AMPL_WIDTH),
conv_std_logic_vector(29609,AMPL_WIDTH),
conv_std_logic_vector(29610,AMPL_WIDTH),
conv_std_logic_vector(29612,AMPL_WIDTH),
conv_std_logic_vector(29613,AMPL_WIDTH),
conv_std_logic_vector(29614,AMPL_WIDTH),
conv_std_logic_vector(29616,AMPL_WIDTH),
conv_std_logic_vector(29617,AMPL_WIDTH),
conv_std_logic_vector(29618,AMPL_WIDTH),
conv_std_logic_vector(29620,AMPL_WIDTH),
conv_std_logic_vector(29621,AMPL_WIDTH),
conv_std_logic_vector(29622,AMPL_WIDTH),
conv_std_logic_vector(29624,AMPL_WIDTH),
conv_std_logic_vector(29625,AMPL_WIDTH),
conv_std_logic_vector(29626,AMPL_WIDTH),
conv_std_logic_vector(29628,AMPL_WIDTH),
conv_std_logic_vector(29629,AMPL_WIDTH),
conv_std_logic_vector(29630,AMPL_WIDTH),
conv_std_logic_vector(29632,AMPL_WIDTH),
conv_std_logic_vector(29633,AMPL_WIDTH),
conv_std_logic_vector(29634,AMPL_WIDTH),
conv_std_logic_vector(29636,AMPL_WIDTH),
conv_std_logic_vector(29637,AMPL_WIDTH),
conv_std_logic_vector(29638,AMPL_WIDTH),
conv_std_logic_vector(29640,AMPL_WIDTH),
conv_std_logic_vector(29641,AMPL_WIDTH),
conv_std_logic_vector(29642,AMPL_WIDTH),
conv_std_logic_vector(29644,AMPL_WIDTH),
conv_std_logic_vector(29645,AMPL_WIDTH),
conv_std_logic_vector(29646,AMPL_WIDTH),
conv_std_logic_vector(29648,AMPL_WIDTH),
conv_std_logic_vector(29649,AMPL_WIDTH),
conv_std_logic_vector(29651,AMPL_WIDTH),
conv_std_logic_vector(29652,AMPL_WIDTH),
conv_std_logic_vector(29653,AMPL_WIDTH),
conv_std_logic_vector(29655,AMPL_WIDTH),
conv_std_logic_vector(29656,AMPL_WIDTH),
conv_std_logic_vector(29657,AMPL_WIDTH),
conv_std_logic_vector(29659,AMPL_WIDTH),
conv_std_logic_vector(29660,AMPL_WIDTH),
conv_std_logic_vector(29661,AMPL_WIDTH),
conv_std_logic_vector(29663,AMPL_WIDTH),
conv_std_logic_vector(29664,AMPL_WIDTH),
conv_std_logic_vector(29665,AMPL_WIDTH),
conv_std_logic_vector(29667,AMPL_WIDTH),
conv_std_logic_vector(29668,AMPL_WIDTH),
conv_std_logic_vector(29669,AMPL_WIDTH),
conv_std_logic_vector(29671,AMPL_WIDTH),
conv_std_logic_vector(29672,AMPL_WIDTH),
conv_std_logic_vector(29673,AMPL_WIDTH),
conv_std_logic_vector(29675,AMPL_WIDTH),
conv_std_logic_vector(29676,AMPL_WIDTH),
conv_std_logic_vector(29677,AMPL_WIDTH),
conv_std_logic_vector(29679,AMPL_WIDTH),
conv_std_logic_vector(29680,AMPL_WIDTH),
conv_std_logic_vector(29681,AMPL_WIDTH),
conv_std_logic_vector(29683,AMPL_WIDTH),
conv_std_logic_vector(29684,AMPL_WIDTH),
conv_std_logic_vector(29685,AMPL_WIDTH),
conv_std_logic_vector(29687,AMPL_WIDTH),
conv_std_logic_vector(29688,AMPL_WIDTH),
conv_std_logic_vector(29689,AMPL_WIDTH),
conv_std_logic_vector(29690,AMPL_WIDTH),
conv_std_logic_vector(29692,AMPL_WIDTH),
conv_std_logic_vector(29693,AMPL_WIDTH),
conv_std_logic_vector(29694,AMPL_WIDTH),
conv_std_logic_vector(29696,AMPL_WIDTH),
conv_std_logic_vector(29697,AMPL_WIDTH),
conv_std_logic_vector(29698,AMPL_WIDTH),
conv_std_logic_vector(29700,AMPL_WIDTH),
conv_std_logic_vector(29701,AMPL_WIDTH),
conv_std_logic_vector(29702,AMPL_WIDTH),
conv_std_logic_vector(29704,AMPL_WIDTH),
conv_std_logic_vector(29705,AMPL_WIDTH),
conv_std_logic_vector(29706,AMPL_WIDTH),
conv_std_logic_vector(29708,AMPL_WIDTH),
conv_std_logic_vector(29709,AMPL_WIDTH),
conv_std_logic_vector(29710,AMPL_WIDTH),
conv_std_logic_vector(29712,AMPL_WIDTH),
conv_std_logic_vector(29713,AMPL_WIDTH),
conv_std_logic_vector(29714,AMPL_WIDTH),
conv_std_logic_vector(29716,AMPL_WIDTH),
conv_std_logic_vector(29717,AMPL_WIDTH),
conv_std_logic_vector(29718,AMPL_WIDTH),
conv_std_logic_vector(29720,AMPL_WIDTH),
conv_std_logic_vector(29721,AMPL_WIDTH),
conv_std_logic_vector(29722,AMPL_WIDTH),
conv_std_logic_vector(29724,AMPL_WIDTH),
conv_std_logic_vector(29725,AMPL_WIDTH),
conv_std_logic_vector(29726,AMPL_WIDTH),
conv_std_logic_vector(29728,AMPL_WIDTH),
conv_std_logic_vector(29729,AMPL_WIDTH),
conv_std_logic_vector(29730,AMPL_WIDTH),
conv_std_logic_vector(29732,AMPL_WIDTH),
conv_std_logic_vector(29733,AMPL_WIDTH),
conv_std_logic_vector(29734,AMPL_WIDTH),
conv_std_logic_vector(29736,AMPL_WIDTH),
conv_std_logic_vector(29737,AMPL_WIDTH),
conv_std_logic_vector(29738,AMPL_WIDTH),
conv_std_logic_vector(29739,AMPL_WIDTH),
conv_std_logic_vector(29741,AMPL_WIDTH),
conv_std_logic_vector(29742,AMPL_WIDTH),
conv_std_logic_vector(29743,AMPL_WIDTH),
conv_std_logic_vector(29745,AMPL_WIDTH),
conv_std_logic_vector(29746,AMPL_WIDTH),
conv_std_logic_vector(29747,AMPL_WIDTH),
conv_std_logic_vector(29749,AMPL_WIDTH),
conv_std_logic_vector(29750,AMPL_WIDTH),
conv_std_logic_vector(29751,AMPL_WIDTH),
conv_std_logic_vector(29753,AMPL_WIDTH),
conv_std_logic_vector(29754,AMPL_WIDTH),
conv_std_logic_vector(29755,AMPL_WIDTH),
conv_std_logic_vector(29757,AMPL_WIDTH),
conv_std_logic_vector(29758,AMPL_WIDTH),
conv_std_logic_vector(29759,AMPL_WIDTH),
conv_std_logic_vector(29761,AMPL_WIDTH),
conv_std_logic_vector(29762,AMPL_WIDTH),
conv_std_logic_vector(29763,AMPL_WIDTH),
conv_std_logic_vector(29764,AMPL_WIDTH),
conv_std_logic_vector(29766,AMPL_WIDTH),
conv_std_logic_vector(29767,AMPL_WIDTH),
conv_std_logic_vector(29768,AMPL_WIDTH),
conv_std_logic_vector(29770,AMPL_WIDTH),
conv_std_logic_vector(29771,AMPL_WIDTH),
conv_std_logic_vector(29772,AMPL_WIDTH),
conv_std_logic_vector(29774,AMPL_WIDTH),
conv_std_logic_vector(29775,AMPL_WIDTH),
conv_std_logic_vector(29776,AMPL_WIDTH),
conv_std_logic_vector(29778,AMPL_WIDTH),
conv_std_logic_vector(29779,AMPL_WIDTH),
conv_std_logic_vector(29780,AMPL_WIDTH),
conv_std_logic_vector(29782,AMPL_WIDTH),
conv_std_logic_vector(29783,AMPL_WIDTH),
conv_std_logic_vector(29784,AMPL_WIDTH),
conv_std_logic_vector(29785,AMPL_WIDTH),
conv_std_logic_vector(29787,AMPL_WIDTH),
conv_std_logic_vector(29788,AMPL_WIDTH),
conv_std_logic_vector(29789,AMPL_WIDTH),
conv_std_logic_vector(29791,AMPL_WIDTH),
conv_std_logic_vector(29792,AMPL_WIDTH),
conv_std_logic_vector(29793,AMPL_WIDTH),
conv_std_logic_vector(29795,AMPL_WIDTH),
conv_std_logic_vector(29796,AMPL_WIDTH),
conv_std_logic_vector(29797,AMPL_WIDTH),
conv_std_logic_vector(29799,AMPL_WIDTH),
conv_std_logic_vector(29800,AMPL_WIDTH),
conv_std_logic_vector(29801,AMPL_WIDTH),
conv_std_logic_vector(29802,AMPL_WIDTH),
conv_std_logic_vector(29804,AMPL_WIDTH),
conv_std_logic_vector(29805,AMPL_WIDTH),
conv_std_logic_vector(29806,AMPL_WIDTH),
conv_std_logic_vector(29808,AMPL_WIDTH),
conv_std_logic_vector(29809,AMPL_WIDTH),
conv_std_logic_vector(29810,AMPL_WIDTH),
conv_std_logic_vector(29812,AMPL_WIDTH),
conv_std_logic_vector(29813,AMPL_WIDTH),
conv_std_logic_vector(29814,AMPL_WIDTH),
conv_std_logic_vector(29816,AMPL_WIDTH),
conv_std_logic_vector(29817,AMPL_WIDTH),
conv_std_logic_vector(29818,AMPL_WIDTH),
conv_std_logic_vector(29819,AMPL_WIDTH),
conv_std_logic_vector(29821,AMPL_WIDTH),
conv_std_logic_vector(29822,AMPL_WIDTH),
conv_std_logic_vector(29823,AMPL_WIDTH),
conv_std_logic_vector(29825,AMPL_WIDTH),
conv_std_logic_vector(29826,AMPL_WIDTH),
conv_std_logic_vector(29827,AMPL_WIDTH),
conv_std_logic_vector(29829,AMPL_WIDTH),
conv_std_logic_vector(29830,AMPL_WIDTH),
conv_std_logic_vector(29831,AMPL_WIDTH),
conv_std_logic_vector(29832,AMPL_WIDTH),
conv_std_logic_vector(29834,AMPL_WIDTH),
conv_std_logic_vector(29835,AMPL_WIDTH),
conv_std_logic_vector(29836,AMPL_WIDTH),
conv_std_logic_vector(29838,AMPL_WIDTH),
conv_std_logic_vector(29839,AMPL_WIDTH),
conv_std_logic_vector(29840,AMPL_WIDTH),
conv_std_logic_vector(29842,AMPL_WIDTH),
conv_std_logic_vector(29843,AMPL_WIDTH),
conv_std_logic_vector(29844,AMPL_WIDTH),
conv_std_logic_vector(29845,AMPL_WIDTH),
conv_std_logic_vector(29847,AMPL_WIDTH),
conv_std_logic_vector(29848,AMPL_WIDTH),
conv_std_logic_vector(29849,AMPL_WIDTH),
conv_std_logic_vector(29851,AMPL_WIDTH),
conv_std_logic_vector(29852,AMPL_WIDTH),
conv_std_logic_vector(29853,AMPL_WIDTH),
conv_std_logic_vector(29854,AMPL_WIDTH),
conv_std_logic_vector(29856,AMPL_WIDTH),
conv_std_logic_vector(29857,AMPL_WIDTH),
conv_std_logic_vector(29858,AMPL_WIDTH),
conv_std_logic_vector(29860,AMPL_WIDTH),
conv_std_logic_vector(29861,AMPL_WIDTH),
conv_std_logic_vector(29862,AMPL_WIDTH),
conv_std_logic_vector(29864,AMPL_WIDTH),
conv_std_logic_vector(29865,AMPL_WIDTH),
conv_std_logic_vector(29866,AMPL_WIDTH),
conv_std_logic_vector(29867,AMPL_WIDTH),
conv_std_logic_vector(29869,AMPL_WIDTH),
conv_std_logic_vector(29870,AMPL_WIDTH),
conv_std_logic_vector(29871,AMPL_WIDTH),
conv_std_logic_vector(29873,AMPL_WIDTH),
conv_std_logic_vector(29874,AMPL_WIDTH),
conv_std_logic_vector(29875,AMPL_WIDTH),
conv_std_logic_vector(29876,AMPL_WIDTH),
conv_std_logic_vector(29878,AMPL_WIDTH),
conv_std_logic_vector(29879,AMPL_WIDTH),
conv_std_logic_vector(29880,AMPL_WIDTH),
conv_std_logic_vector(29882,AMPL_WIDTH),
conv_std_logic_vector(29883,AMPL_WIDTH),
conv_std_logic_vector(29884,AMPL_WIDTH),
conv_std_logic_vector(29885,AMPL_WIDTH),
conv_std_logic_vector(29887,AMPL_WIDTH),
conv_std_logic_vector(29888,AMPL_WIDTH),
conv_std_logic_vector(29889,AMPL_WIDTH),
conv_std_logic_vector(29891,AMPL_WIDTH),
conv_std_logic_vector(29892,AMPL_WIDTH),
conv_std_logic_vector(29893,AMPL_WIDTH),
conv_std_logic_vector(29894,AMPL_WIDTH),
conv_std_logic_vector(29896,AMPL_WIDTH),
conv_std_logic_vector(29897,AMPL_WIDTH),
conv_std_logic_vector(29898,AMPL_WIDTH),
conv_std_logic_vector(29900,AMPL_WIDTH),
conv_std_logic_vector(29901,AMPL_WIDTH),
conv_std_logic_vector(29902,AMPL_WIDTH),
conv_std_logic_vector(29903,AMPL_WIDTH),
conv_std_logic_vector(29905,AMPL_WIDTH),
conv_std_logic_vector(29906,AMPL_WIDTH),
conv_std_logic_vector(29907,AMPL_WIDTH),
conv_std_logic_vector(29909,AMPL_WIDTH),
conv_std_logic_vector(29910,AMPL_WIDTH),
conv_std_logic_vector(29911,AMPL_WIDTH),
conv_std_logic_vector(29912,AMPL_WIDTH),
conv_std_logic_vector(29914,AMPL_WIDTH),
conv_std_logic_vector(29915,AMPL_WIDTH),
conv_std_logic_vector(29916,AMPL_WIDTH),
conv_std_logic_vector(29918,AMPL_WIDTH),
conv_std_logic_vector(29919,AMPL_WIDTH),
conv_std_logic_vector(29920,AMPL_WIDTH),
conv_std_logic_vector(29921,AMPL_WIDTH),
conv_std_logic_vector(29923,AMPL_WIDTH),
conv_std_logic_vector(29924,AMPL_WIDTH),
conv_std_logic_vector(29925,AMPL_WIDTH),
conv_std_logic_vector(29927,AMPL_WIDTH),
conv_std_logic_vector(29928,AMPL_WIDTH),
conv_std_logic_vector(29929,AMPL_WIDTH),
conv_std_logic_vector(29930,AMPL_WIDTH),
conv_std_logic_vector(29932,AMPL_WIDTH),
conv_std_logic_vector(29933,AMPL_WIDTH),
conv_std_logic_vector(29934,AMPL_WIDTH),
conv_std_logic_vector(29936,AMPL_WIDTH),
conv_std_logic_vector(29937,AMPL_WIDTH),
conv_std_logic_vector(29938,AMPL_WIDTH),
conv_std_logic_vector(29939,AMPL_WIDTH),
conv_std_logic_vector(29941,AMPL_WIDTH),
conv_std_logic_vector(29942,AMPL_WIDTH),
conv_std_logic_vector(29943,AMPL_WIDTH),
conv_std_logic_vector(29944,AMPL_WIDTH),
conv_std_logic_vector(29946,AMPL_WIDTH),
conv_std_logic_vector(29947,AMPL_WIDTH),
conv_std_logic_vector(29948,AMPL_WIDTH),
conv_std_logic_vector(29950,AMPL_WIDTH),
conv_std_logic_vector(29951,AMPL_WIDTH),
conv_std_logic_vector(29952,AMPL_WIDTH),
conv_std_logic_vector(29953,AMPL_WIDTH),
conv_std_logic_vector(29955,AMPL_WIDTH),
conv_std_logic_vector(29956,AMPL_WIDTH),
conv_std_logic_vector(29957,AMPL_WIDTH),
conv_std_logic_vector(29958,AMPL_WIDTH),
conv_std_logic_vector(29960,AMPL_WIDTH),
conv_std_logic_vector(29961,AMPL_WIDTH),
conv_std_logic_vector(29962,AMPL_WIDTH),
conv_std_logic_vector(29964,AMPL_WIDTH),
conv_std_logic_vector(29965,AMPL_WIDTH),
conv_std_logic_vector(29966,AMPL_WIDTH),
conv_std_logic_vector(29967,AMPL_WIDTH),
conv_std_logic_vector(29969,AMPL_WIDTH),
conv_std_logic_vector(29970,AMPL_WIDTH),
conv_std_logic_vector(29971,AMPL_WIDTH),
conv_std_logic_vector(29972,AMPL_WIDTH),
conv_std_logic_vector(29974,AMPL_WIDTH),
conv_std_logic_vector(29975,AMPL_WIDTH),
conv_std_logic_vector(29976,AMPL_WIDTH),
conv_std_logic_vector(29978,AMPL_WIDTH),
conv_std_logic_vector(29979,AMPL_WIDTH),
conv_std_logic_vector(29980,AMPL_WIDTH),
conv_std_logic_vector(29981,AMPL_WIDTH),
conv_std_logic_vector(29983,AMPL_WIDTH),
conv_std_logic_vector(29984,AMPL_WIDTH),
conv_std_logic_vector(29985,AMPL_WIDTH),
conv_std_logic_vector(29986,AMPL_WIDTH),
conv_std_logic_vector(29988,AMPL_WIDTH),
conv_std_logic_vector(29989,AMPL_WIDTH),
conv_std_logic_vector(29990,AMPL_WIDTH),
conv_std_logic_vector(29991,AMPL_WIDTH),
conv_std_logic_vector(29993,AMPL_WIDTH),
conv_std_logic_vector(29994,AMPL_WIDTH),
conv_std_logic_vector(29995,AMPL_WIDTH),
conv_std_logic_vector(29997,AMPL_WIDTH),
conv_std_logic_vector(29998,AMPL_WIDTH),
conv_std_logic_vector(29999,AMPL_WIDTH),
conv_std_logic_vector(30000,AMPL_WIDTH),
conv_std_logic_vector(30002,AMPL_WIDTH),
conv_std_logic_vector(30003,AMPL_WIDTH),
conv_std_logic_vector(30004,AMPL_WIDTH),
conv_std_logic_vector(30005,AMPL_WIDTH),
conv_std_logic_vector(30007,AMPL_WIDTH),
conv_std_logic_vector(30008,AMPL_WIDTH),
conv_std_logic_vector(30009,AMPL_WIDTH),
conv_std_logic_vector(30010,AMPL_WIDTH),
conv_std_logic_vector(30012,AMPL_WIDTH),
conv_std_logic_vector(30013,AMPL_WIDTH),
conv_std_logic_vector(30014,AMPL_WIDTH),
conv_std_logic_vector(30015,AMPL_WIDTH),
conv_std_logic_vector(30017,AMPL_WIDTH),
conv_std_logic_vector(30018,AMPL_WIDTH),
conv_std_logic_vector(30019,AMPL_WIDTH),
conv_std_logic_vector(30020,AMPL_WIDTH),
conv_std_logic_vector(30022,AMPL_WIDTH),
conv_std_logic_vector(30023,AMPL_WIDTH),
conv_std_logic_vector(30024,AMPL_WIDTH),
conv_std_logic_vector(30026,AMPL_WIDTH),
conv_std_logic_vector(30027,AMPL_WIDTH),
conv_std_logic_vector(30028,AMPL_WIDTH),
conv_std_logic_vector(30029,AMPL_WIDTH),
conv_std_logic_vector(30031,AMPL_WIDTH),
conv_std_logic_vector(30032,AMPL_WIDTH),
conv_std_logic_vector(30033,AMPL_WIDTH),
conv_std_logic_vector(30034,AMPL_WIDTH),
conv_std_logic_vector(30036,AMPL_WIDTH),
conv_std_logic_vector(30037,AMPL_WIDTH),
conv_std_logic_vector(30038,AMPL_WIDTH),
conv_std_logic_vector(30039,AMPL_WIDTH),
conv_std_logic_vector(30041,AMPL_WIDTH),
conv_std_logic_vector(30042,AMPL_WIDTH),
conv_std_logic_vector(30043,AMPL_WIDTH),
conv_std_logic_vector(30044,AMPL_WIDTH),
conv_std_logic_vector(30046,AMPL_WIDTH),
conv_std_logic_vector(30047,AMPL_WIDTH),
conv_std_logic_vector(30048,AMPL_WIDTH),
conv_std_logic_vector(30049,AMPL_WIDTH),
conv_std_logic_vector(30051,AMPL_WIDTH),
conv_std_logic_vector(30052,AMPL_WIDTH),
conv_std_logic_vector(30053,AMPL_WIDTH),
conv_std_logic_vector(30054,AMPL_WIDTH),
conv_std_logic_vector(30056,AMPL_WIDTH),
conv_std_logic_vector(30057,AMPL_WIDTH),
conv_std_logic_vector(30058,AMPL_WIDTH),
conv_std_logic_vector(30059,AMPL_WIDTH),
conv_std_logic_vector(30061,AMPL_WIDTH),
conv_std_logic_vector(30062,AMPL_WIDTH),
conv_std_logic_vector(30063,AMPL_WIDTH),
conv_std_logic_vector(30064,AMPL_WIDTH),
conv_std_logic_vector(30066,AMPL_WIDTH),
conv_std_logic_vector(30067,AMPL_WIDTH),
conv_std_logic_vector(30068,AMPL_WIDTH),
conv_std_logic_vector(30069,AMPL_WIDTH),
conv_std_logic_vector(30071,AMPL_WIDTH),
conv_std_logic_vector(30072,AMPL_WIDTH),
conv_std_logic_vector(30073,AMPL_WIDTH),
conv_std_logic_vector(30074,AMPL_WIDTH),
conv_std_logic_vector(30076,AMPL_WIDTH),
conv_std_logic_vector(30077,AMPL_WIDTH),
conv_std_logic_vector(30078,AMPL_WIDTH),
conv_std_logic_vector(30079,AMPL_WIDTH),
conv_std_logic_vector(30081,AMPL_WIDTH),
conv_std_logic_vector(30082,AMPL_WIDTH),
conv_std_logic_vector(30083,AMPL_WIDTH),
conv_std_logic_vector(30084,AMPL_WIDTH),
conv_std_logic_vector(30086,AMPL_WIDTH),
conv_std_logic_vector(30087,AMPL_WIDTH),
conv_std_logic_vector(30088,AMPL_WIDTH),
conv_std_logic_vector(30089,AMPL_WIDTH),
conv_std_logic_vector(30091,AMPL_WIDTH),
conv_std_logic_vector(30092,AMPL_WIDTH),
conv_std_logic_vector(30093,AMPL_WIDTH),
conv_std_logic_vector(30094,AMPL_WIDTH),
conv_std_logic_vector(30096,AMPL_WIDTH),
conv_std_logic_vector(30097,AMPL_WIDTH),
conv_std_logic_vector(30098,AMPL_WIDTH),
conv_std_logic_vector(30099,AMPL_WIDTH),
conv_std_logic_vector(30100,AMPL_WIDTH),
conv_std_logic_vector(30102,AMPL_WIDTH),
conv_std_logic_vector(30103,AMPL_WIDTH),
conv_std_logic_vector(30104,AMPL_WIDTH),
conv_std_logic_vector(30105,AMPL_WIDTH),
conv_std_logic_vector(30107,AMPL_WIDTH),
conv_std_logic_vector(30108,AMPL_WIDTH),
conv_std_logic_vector(30109,AMPL_WIDTH),
conv_std_logic_vector(30110,AMPL_WIDTH),
conv_std_logic_vector(30112,AMPL_WIDTH),
conv_std_logic_vector(30113,AMPL_WIDTH),
conv_std_logic_vector(30114,AMPL_WIDTH),
conv_std_logic_vector(30115,AMPL_WIDTH),
conv_std_logic_vector(30117,AMPL_WIDTH),
conv_std_logic_vector(30118,AMPL_WIDTH),
conv_std_logic_vector(30119,AMPL_WIDTH),
conv_std_logic_vector(30120,AMPL_WIDTH),
conv_std_logic_vector(30122,AMPL_WIDTH),
conv_std_logic_vector(30123,AMPL_WIDTH),
conv_std_logic_vector(30124,AMPL_WIDTH),
conv_std_logic_vector(30125,AMPL_WIDTH),
conv_std_logic_vector(30126,AMPL_WIDTH),
conv_std_logic_vector(30128,AMPL_WIDTH),
conv_std_logic_vector(30129,AMPL_WIDTH),
conv_std_logic_vector(30130,AMPL_WIDTH),
conv_std_logic_vector(30131,AMPL_WIDTH),
conv_std_logic_vector(30133,AMPL_WIDTH),
conv_std_logic_vector(30134,AMPL_WIDTH),
conv_std_logic_vector(30135,AMPL_WIDTH),
conv_std_logic_vector(30136,AMPL_WIDTH),
conv_std_logic_vector(30138,AMPL_WIDTH),
conv_std_logic_vector(30139,AMPL_WIDTH),
conv_std_logic_vector(30140,AMPL_WIDTH),
conv_std_logic_vector(30141,AMPL_WIDTH),
conv_std_logic_vector(30143,AMPL_WIDTH),
conv_std_logic_vector(30144,AMPL_WIDTH),
conv_std_logic_vector(30145,AMPL_WIDTH),
conv_std_logic_vector(30146,AMPL_WIDTH),
conv_std_logic_vector(30147,AMPL_WIDTH),
conv_std_logic_vector(30149,AMPL_WIDTH),
conv_std_logic_vector(30150,AMPL_WIDTH),
conv_std_logic_vector(30151,AMPL_WIDTH),
conv_std_logic_vector(30152,AMPL_WIDTH),
conv_std_logic_vector(30154,AMPL_WIDTH),
conv_std_logic_vector(30155,AMPL_WIDTH),
conv_std_logic_vector(30156,AMPL_WIDTH),
conv_std_logic_vector(30157,AMPL_WIDTH),
conv_std_logic_vector(30159,AMPL_WIDTH),
conv_std_logic_vector(30160,AMPL_WIDTH),
conv_std_logic_vector(30161,AMPL_WIDTH),
conv_std_logic_vector(30162,AMPL_WIDTH),
conv_std_logic_vector(30163,AMPL_WIDTH),
conv_std_logic_vector(30165,AMPL_WIDTH),
conv_std_logic_vector(30166,AMPL_WIDTH),
conv_std_logic_vector(30167,AMPL_WIDTH),
conv_std_logic_vector(30168,AMPL_WIDTH),
conv_std_logic_vector(30170,AMPL_WIDTH),
conv_std_logic_vector(30171,AMPL_WIDTH),
conv_std_logic_vector(30172,AMPL_WIDTH),
conv_std_logic_vector(30173,AMPL_WIDTH),
conv_std_logic_vector(30174,AMPL_WIDTH),
conv_std_logic_vector(30176,AMPL_WIDTH),
conv_std_logic_vector(30177,AMPL_WIDTH),
conv_std_logic_vector(30178,AMPL_WIDTH),
conv_std_logic_vector(30179,AMPL_WIDTH),
conv_std_logic_vector(30181,AMPL_WIDTH),
conv_std_logic_vector(30182,AMPL_WIDTH),
conv_std_logic_vector(30183,AMPL_WIDTH),
conv_std_logic_vector(30184,AMPL_WIDTH),
conv_std_logic_vector(30185,AMPL_WIDTH),
conv_std_logic_vector(30187,AMPL_WIDTH),
conv_std_logic_vector(30188,AMPL_WIDTH),
conv_std_logic_vector(30189,AMPL_WIDTH),
conv_std_logic_vector(30190,AMPL_WIDTH),
conv_std_logic_vector(30192,AMPL_WIDTH),
conv_std_logic_vector(30193,AMPL_WIDTH),
conv_std_logic_vector(30194,AMPL_WIDTH),
conv_std_logic_vector(30195,AMPL_WIDTH),
conv_std_logic_vector(30196,AMPL_WIDTH),
conv_std_logic_vector(30198,AMPL_WIDTH),
conv_std_logic_vector(30199,AMPL_WIDTH),
conv_std_logic_vector(30200,AMPL_WIDTH),
conv_std_logic_vector(30201,AMPL_WIDTH),
conv_std_logic_vector(30203,AMPL_WIDTH),
conv_std_logic_vector(30204,AMPL_WIDTH),
conv_std_logic_vector(30205,AMPL_WIDTH),
conv_std_logic_vector(30206,AMPL_WIDTH),
conv_std_logic_vector(30207,AMPL_WIDTH),
conv_std_logic_vector(30209,AMPL_WIDTH),
conv_std_logic_vector(30210,AMPL_WIDTH),
conv_std_logic_vector(30211,AMPL_WIDTH),
conv_std_logic_vector(30212,AMPL_WIDTH),
conv_std_logic_vector(30214,AMPL_WIDTH),
conv_std_logic_vector(30215,AMPL_WIDTH),
conv_std_logic_vector(30216,AMPL_WIDTH),
conv_std_logic_vector(30217,AMPL_WIDTH),
conv_std_logic_vector(30218,AMPL_WIDTH),
conv_std_logic_vector(30220,AMPL_WIDTH),
conv_std_logic_vector(30221,AMPL_WIDTH),
conv_std_logic_vector(30222,AMPL_WIDTH),
conv_std_logic_vector(30223,AMPL_WIDTH),
conv_std_logic_vector(30224,AMPL_WIDTH),
conv_std_logic_vector(30226,AMPL_WIDTH),
conv_std_logic_vector(30227,AMPL_WIDTH),
conv_std_logic_vector(30228,AMPL_WIDTH),
conv_std_logic_vector(30229,AMPL_WIDTH),
conv_std_logic_vector(30231,AMPL_WIDTH),
conv_std_logic_vector(30232,AMPL_WIDTH),
conv_std_logic_vector(30233,AMPL_WIDTH),
conv_std_logic_vector(30234,AMPL_WIDTH),
conv_std_logic_vector(30235,AMPL_WIDTH),
conv_std_logic_vector(30237,AMPL_WIDTH),
conv_std_logic_vector(30238,AMPL_WIDTH),
conv_std_logic_vector(30239,AMPL_WIDTH),
conv_std_logic_vector(30240,AMPL_WIDTH),
conv_std_logic_vector(30241,AMPL_WIDTH),
conv_std_logic_vector(30243,AMPL_WIDTH),
conv_std_logic_vector(30244,AMPL_WIDTH),
conv_std_logic_vector(30245,AMPL_WIDTH),
conv_std_logic_vector(30246,AMPL_WIDTH),
conv_std_logic_vector(30247,AMPL_WIDTH),
conv_std_logic_vector(30249,AMPL_WIDTH),
conv_std_logic_vector(30250,AMPL_WIDTH),
conv_std_logic_vector(30251,AMPL_WIDTH),
conv_std_logic_vector(30252,AMPL_WIDTH),
conv_std_logic_vector(30253,AMPL_WIDTH),
conv_std_logic_vector(30255,AMPL_WIDTH),
conv_std_logic_vector(30256,AMPL_WIDTH),
conv_std_logic_vector(30257,AMPL_WIDTH),
conv_std_logic_vector(30258,AMPL_WIDTH),
conv_std_logic_vector(30260,AMPL_WIDTH),
conv_std_logic_vector(30261,AMPL_WIDTH),
conv_std_logic_vector(30262,AMPL_WIDTH),
conv_std_logic_vector(30263,AMPL_WIDTH),
conv_std_logic_vector(30264,AMPL_WIDTH),
conv_std_logic_vector(30266,AMPL_WIDTH),
conv_std_logic_vector(30267,AMPL_WIDTH),
conv_std_logic_vector(30268,AMPL_WIDTH),
conv_std_logic_vector(30269,AMPL_WIDTH),
conv_std_logic_vector(30270,AMPL_WIDTH),
conv_std_logic_vector(30272,AMPL_WIDTH),
conv_std_logic_vector(30273,AMPL_WIDTH),
conv_std_logic_vector(30274,AMPL_WIDTH),
conv_std_logic_vector(30275,AMPL_WIDTH),
conv_std_logic_vector(30276,AMPL_WIDTH),
conv_std_logic_vector(30278,AMPL_WIDTH),
conv_std_logic_vector(30279,AMPL_WIDTH),
conv_std_logic_vector(30280,AMPL_WIDTH),
conv_std_logic_vector(30281,AMPL_WIDTH),
conv_std_logic_vector(30282,AMPL_WIDTH),
conv_std_logic_vector(30284,AMPL_WIDTH),
conv_std_logic_vector(30285,AMPL_WIDTH),
conv_std_logic_vector(30286,AMPL_WIDTH),
conv_std_logic_vector(30287,AMPL_WIDTH),
conv_std_logic_vector(30288,AMPL_WIDTH),
conv_std_logic_vector(30290,AMPL_WIDTH),
conv_std_logic_vector(30291,AMPL_WIDTH),
conv_std_logic_vector(30292,AMPL_WIDTH),
conv_std_logic_vector(30293,AMPL_WIDTH),
conv_std_logic_vector(30294,AMPL_WIDTH),
conv_std_logic_vector(30296,AMPL_WIDTH),
conv_std_logic_vector(30297,AMPL_WIDTH),
conv_std_logic_vector(30298,AMPL_WIDTH),
conv_std_logic_vector(30299,AMPL_WIDTH),
conv_std_logic_vector(30300,AMPL_WIDTH),
conv_std_logic_vector(30302,AMPL_WIDTH),
conv_std_logic_vector(30303,AMPL_WIDTH),
conv_std_logic_vector(30304,AMPL_WIDTH),
conv_std_logic_vector(30305,AMPL_WIDTH),
conv_std_logic_vector(30306,AMPL_WIDTH),
conv_std_logic_vector(30308,AMPL_WIDTH),
conv_std_logic_vector(30309,AMPL_WIDTH),
conv_std_logic_vector(30310,AMPL_WIDTH),
conv_std_logic_vector(30311,AMPL_WIDTH),
conv_std_logic_vector(30312,AMPL_WIDTH),
conv_std_logic_vector(30313,AMPL_WIDTH),
conv_std_logic_vector(30315,AMPL_WIDTH),
conv_std_logic_vector(30316,AMPL_WIDTH),
conv_std_logic_vector(30317,AMPL_WIDTH),
conv_std_logic_vector(30318,AMPL_WIDTH),
conv_std_logic_vector(30319,AMPL_WIDTH),
conv_std_logic_vector(30321,AMPL_WIDTH),
conv_std_logic_vector(30322,AMPL_WIDTH),
conv_std_logic_vector(30323,AMPL_WIDTH),
conv_std_logic_vector(30324,AMPL_WIDTH),
conv_std_logic_vector(30325,AMPL_WIDTH),
conv_std_logic_vector(30327,AMPL_WIDTH),
conv_std_logic_vector(30328,AMPL_WIDTH),
conv_std_logic_vector(30329,AMPL_WIDTH),
conv_std_logic_vector(30330,AMPL_WIDTH),
conv_std_logic_vector(30331,AMPL_WIDTH),
conv_std_logic_vector(30333,AMPL_WIDTH),
conv_std_logic_vector(30334,AMPL_WIDTH),
conv_std_logic_vector(30335,AMPL_WIDTH),
conv_std_logic_vector(30336,AMPL_WIDTH),
conv_std_logic_vector(30337,AMPL_WIDTH),
conv_std_logic_vector(30338,AMPL_WIDTH),
conv_std_logic_vector(30340,AMPL_WIDTH),
conv_std_logic_vector(30341,AMPL_WIDTH),
conv_std_logic_vector(30342,AMPL_WIDTH),
conv_std_logic_vector(30343,AMPL_WIDTH),
conv_std_logic_vector(30344,AMPL_WIDTH),
conv_std_logic_vector(30346,AMPL_WIDTH),
conv_std_logic_vector(30347,AMPL_WIDTH),
conv_std_logic_vector(30348,AMPL_WIDTH),
conv_std_logic_vector(30349,AMPL_WIDTH),
conv_std_logic_vector(30350,AMPL_WIDTH),
conv_std_logic_vector(30351,AMPL_WIDTH),
conv_std_logic_vector(30353,AMPL_WIDTH),
conv_std_logic_vector(30354,AMPL_WIDTH),
conv_std_logic_vector(30355,AMPL_WIDTH),
conv_std_logic_vector(30356,AMPL_WIDTH),
conv_std_logic_vector(30357,AMPL_WIDTH),
conv_std_logic_vector(30359,AMPL_WIDTH),
conv_std_logic_vector(30360,AMPL_WIDTH),
conv_std_logic_vector(30361,AMPL_WIDTH),
conv_std_logic_vector(30362,AMPL_WIDTH),
conv_std_logic_vector(30363,AMPL_WIDTH),
conv_std_logic_vector(30365,AMPL_WIDTH),
conv_std_logic_vector(30366,AMPL_WIDTH),
conv_std_logic_vector(30367,AMPL_WIDTH),
conv_std_logic_vector(30368,AMPL_WIDTH),
conv_std_logic_vector(30369,AMPL_WIDTH),
conv_std_logic_vector(30370,AMPL_WIDTH),
conv_std_logic_vector(30372,AMPL_WIDTH),
conv_std_logic_vector(30373,AMPL_WIDTH),
conv_std_logic_vector(30374,AMPL_WIDTH),
conv_std_logic_vector(30375,AMPL_WIDTH),
conv_std_logic_vector(30376,AMPL_WIDTH),
conv_std_logic_vector(30377,AMPL_WIDTH),
conv_std_logic_vector(30379,AMPL_WIDTH),
conv_std_logic_vector(30380,AMPL_WIDTH),
conv_std_logic_vector(30381,AMPL_WIDTH),
conv_std_logic_vector(30382,AMPL_WIDTH),
conv_std_logic_vector(30383,AMPL_WIDTH),
conv_std_logic_vector(30385,AMPL_WIDTH),
conv_std_logic_vector(30386,AMPL_WIDTH),
conv_std_logic_vector(30387,AMPL_WIDTH),
conv_std_logic_vector(30388,AMPL_WIDTH),
conv_std_logic_vector(30389,AMPL_WIDTH),
conv_std_logic_vector(30390,AMPL_WIDTH),
conv_std_logic_vector(30392,AMPL_WIDTH),
conv_std_logic_vector(30393,AMPL_WIDTH),
conv_std_logic_vector(30394,AMPL_WIDTH),
conv_std_logic_vector(30395,AMPL_WIDTH),
conv_std_logic_vector(30396,AMPL_WIDTH),
conv_std_logic_vector(30397,AMPL_WIDTH),
conv_std_logic_vector(30399,AMPL_WIDTH),
conv_std_logic_vector(30400,AMPL_WIDTH),
conv_std_logic_vector(30401,AMPL_WIDTH),
conv_std_logic_vector(30402,AMPL_WIDTH),
conv_std_logic_vector(30403,AMPL_WIDTH),
conv_std_logic_vector(30404,AMPL_WIDTH),
conv_std_logic_vector(30406,AMPL_WIDTH),
conv_std_logic_vector(30407,AMPL_WIDTH),
conv_std_logic_vector(30408,AMPL_WIDTH),
conv_std_logic_vector(30409,AMPL_WIDTH),
conv_std_logic_vector(30410,AMPL_WIDTH),
conv_std_logic_vector(30412,AMPL_WIDTH),
conv_std_logic_vector(30413,AMPL_WIDTH),
conv_std_logic_vector(30414,AMPL_WIDTH),
conv_std_logic_vector(30415,AMPL_WIDTH),
conv_std_logic_vector(30416,AMPL_WIDTH),
conv_std_logic_vector(30417,AMPL_WIDTH),
conv_std_logic_vector(30419,AMPL_WIDTH),
conv_std_logic_vector(30420,AMPL_WIDTH),
conv_std_logic_vector(30421,AMPL_WIDTH),
conv_std_logic_vector(30422,AMPL_WIDTH),
conv_std_logic_vector(30423,AMPL_WIDTH),
conv_std_logic_vector(30424,AMPL_WIDTH),
conv_std_logic_vector(30426,AMPL_WIDTH),
conv_std_logic_vector(30427,AMPL_WIDTH),
conv_std_logic_vector(30428,AMPL_WIDTH),
conv_std_logic_vector(30429,AMPL_WIDTH),
conv_std_logic_vector(30430,AMPL_WIDTH),
conv_std_logic_vector(30431,AMPL_WIDTH),
conv_std_logic_vector(30433,AMPL_WIDTH),
conv_std_logic_vector(30434,AMPL_WIDTH),
conv_std_logic_vector(30435,AMPL_WIDTH),
conv_std_logic_vector(30436,AMPL_WIDTH),
conv_std_logic_vector(30437,AMPL_WIDTH),
conv_std_logic_vector(30438,AMPL_WIDTH),
conv_std_logic_vector(30439,AMPL_WIDTH),
conv_std_logic_vector(30441,AMPL_WIDTH),
conv_std_logic_vector(30442,AMPL_WIDTH),
conv_std_logic_vector(30443,AMPL_WIDTH),
conv_std_logic_vector(30444,AMPL_WIDTH),
conv_std_logic_vector(30445,AMPL_WIDTH),
conv_std_logic_vector(30446,AMPL_WIDTH),
conv_std_logic_vector(30448,AMPL_WIDTH),
conv_std_logic_vector(30449,AMPL_WIDTH),
conv_std_logic_vector(30450,AMPL_WIDTH),
conv_std_logic_vector(30451,AMPL_WIDTH),
conv_std_logic_vector(30452,AMPL_WIDTH),
conv_std_logic_vector(30453,AMPL_WIDTH),
conv_std_logic_vector(30455,AMPL_WIDTH),
conv_std_logic_vector(30456,AMPL_WIDTH),
conv_std_logic_vector(30457,AMPL_WIDTH),
conv_std_logic_vector(30458,AMPL_WIDTH),
conv_std_logic_vector(30459,AMPL_WIDTH),
conv_std_logic_vector(30460,AMPL_WIDTH),
conv_std_logic_vector(30462,AMPL_WIDTH),
conv_std_logic_vector(30463,AMPL_WIDTH),
conv_std_logic_vector(30464,AMPL_WIDTH),
conv_std_logic_vector(30465,AMPL_WIDTH),
conv_std_logic_vector(30466,AMPL_WIDTH),
conv_std_logic_vector(30467,AMPL_WIDTH),
conv_std_logic_vector(30468,AMPL_WIDTH),
conv_std_logic_vector(30470,AMPL_WIDTH),
conv_std_logic_vector(30471,AMPL_WIDTH),
conv_std_logic_vector(30472,AMPL_WIDTH),
conv_std_logic_vector(30473,AMPL_WIDTH),
conv_std_logic_vector(30474,AMPL_WIDTH),
conv_std_logic_vector(30475,AMPL_WIDTH),
conv_std_logic_vector(30477,AMPL_WIDTH),
conv_std_logic_vector(30478,AMPL_WIDTH),
conv_std_logic_vector(30479,AMPL_WIDTH),
conv_std_logic_vector(30480,AMPL_WIDTH),
conv_std_logic_vector(30481,AMPL_WIDTH),
conv_std_logic_vector(30482,AMPL_WIDTH),
conv_std_logic_vector(30483,AMPL_WIDTH),
conv_std_logic_vector(30485,AMPL_WIDTH),
conv_std_logic_vector(30486,AMPL_WIDTH),
conv_std_logic_vector(30487,AMPL_WIDTH),
conv_std_logic_vector(30488,AMPL_WIDTH),
conv_std_logic_vector(30489,AMPL_WIDTH),
conv_std_logic_vector(30490,AMPL_WIDTH),
conv_std_logic_vector(30492,AMPL_WIDTH),
conv_std_logic_vector(30493,AMPL_WIDTH),
conv_std_logic_vector(30494,AMPL_WIDTH),
conv_std_logic_vector(30495,AMPL_WIDTH),
conv_std_logic_vector(30496,AMPL_WIDTH),
conv_std_logic_vector(30497,AMPL_WIDTH),
conv_std_logic_vector(30498,AMPL_WIDTH),
conv_std_logic_vector(30500,AMPL_WIDTH),
conv_std_logic_vector(30501,AMPL_WIDTH),
conv_std_logic_vector(30502,AMPL_WIDTH),
conv_std_logic_vector(30503,AMPL_WIDTH),
conv_std_logic_vector(30504,AMPL_WIDTH),
conv_std_logic_vector(30505,AMPL_WIDTH),
conv_std_logic_vector(30506,AMPL_WIDTH),
conv_std_logic_vector(30508,AMPL_WIDTH),
conv_std_logic_vector(30509,AMPL_WIDTH),
conv_std_logic_vector(30510,AMPL_WIDTH),
conv_std_logic_vector(30511,AMPL_WIDTH),
conv_std_logic_vector(30512,AMPL_WIDTH),
conv_std_logic_vector(30513,AMPL_WIDTH),
conv_std_logic_vector(30514,AMPL_WIDTH),
conv_std_logic_vector(30516,AMPL_WIDTH),
conv_std_logic_vector(30517,AMPL_WIDTH),
conv_std_logic_vector(30518,AMPL_WIDTH),
conv_std_logic_vector(30519,AMPL_WIDTH),
conv_std_logic_vector(30520,AMPL_WIDTH),
conv_std_logic_vector(30521,AMPL_WIDTH),
conv_std_logic_vector(30522,AMPL_WIDTH),
conv_std_logic_vector(30524,AMPL_WIDTH),
conv_std_logic_vector(30525,AMPL_WIDTH),
conv_std_logic_vector(30526,AMPL_WIDTH),
conv_std_logic_vector(30527,AMPL_WIDTH),
conv_std_logic_vector(30528,AMPL_WIDTH),
conv_std_logic_vector(30529,AMPL_WIDTH),
conv_std_logic_vector(30530,AMPL_WIDTH),
conv_std_logic_vector(30532,AMPL_WIDTH),
conv_std_logic_vector(30533,AMPL_WIDTH),
conv_std_logic_vector(30534,AMPL_WIDTH),
conv_std_logic_vector(30535,AMPL_WIDTH),
conv_std_logic_vector(30536,AMPL_WIDTH),
conv_std_logic_vector(30537,AMPL_WIDTH),
conv_std_logic_vector(30538,AMPL_WIDTH),
conv_std_logic_vector(30540,AMPL_WIDTH),
conv_std_logic_vector(30541,AMPL_WIDTH),
conv_std_logic_vector(30542,AMPL_WIDTH),
conv_std_logic_vector(30543,AMPL_WIDTH),
conv_std_logic_vector(30544,AMPL_WIDTH),
conv_std_logic_vector(30545,AMPL_WIDTH),
conv_std_logic_vector(30546,AMPL_WIDTH),
conv_std_logic_vector(30548,AMPL_WIDTH),
conv_std_logic_vector(30549,AMPL_WIDTH),
conv_std_logic_vector(30550,AMPL_WIDTH),
conv_std_logic_vector(30551,AMPL_WIDTH),
conv_std_logic_vector(30552,AMPL_WIDTH),
conv_std_logic_vector(30553,AMPL_WIDTH),
conv_std_logic_vector(30554,AMPL_WIDTH),
conv_std_logic_vector(30556,AMPL_WIDTH),
conv_std_logic_vector(30557,AMPL_WIDTH),
conv_std_logic_vector(30558,AMPL_WIDTH),
conv_std_logic_vector(30559,AMPL_WIDTH),
conv_std_logic_vector(30560,AMPL_WIDTH),
conv_std_logic_vector(30561,AMPL_WIDTH),
conv_std_logic_vector(30562,AMPL_WIDTH),
conv_std_logic_vector(30563,AMPL_WIDTH),
conv_std_logic_vector(30565,AMPL_WIDTH),
conv_std_logic_vector(30566,AMPL_WIDTH),
conv_std_logic_vector(30567,AMPL_WIDTH),
conv_std_logic_vector(30568,AMPL_WIDTH),
conv_std_logic_vector(30569,AMPL_WIDTH),
conv_std_logic_vector(30570,AMPL_WIDTH),
conv_std_logic_vector(30571,AMPL_WIDTH),
conv_std_logic_vector(30573,AMPL_WIDTH),
conv_std_logic_vector(30574,AMPL_WIDTH),
conv_std_logic_vector(30575,AMPL_WIDTH),
conv_std_logic_vector(30576,AMPL_WIDTH),
conv_std_logic_vector(30577,AMPL_WIDTH),
conv_std_logic_vector(30578,AMPL_WIDTH),
conv_std_logic_vector(30579,AMPL_WIDTH),
conv_std_logic_vector(30580,AMPL_WIDTH),
conv_std_logic_vector(30582,AMPL_WIDTH),
conv_std_logic_vector(30583,AMPL_WIDTH),
conv_std_logic_vector(30584,AMPL_WIDTH),
conv_std_logic_vector(30585,AMPL_WIDTH),
conv_std_logic_vector(30586,AMPL_WIDTH),
conv_std_logic_vector(30587,AMPL_WIDTH),
conv_std_logic_vector(30588,AMPL_WIDTH),
conv_std_logic_vector(30589,AMPL_WIDTH),
conv_std_logic_vector(30591,AMPL_WIDTH),
conv_std_logic_vector(30592,AMPL_WIDTH),
conv_std_logic_vector(30593,AMPL_WIDTH),
conv_std_logic_vector(30594,AMPL_WIDTH),
conv_std_logic_vector(30595,AMPL_WIDTH),
conv_std_logic_vector(30596,AMPL_WIDTH),
conv_std_logic_vector(30597,AMPL_WIDTH),
conv_std_logic_vector(30598,AMPL_WIDTH),
conv_std_logic_vector(30600,AMPL_WIDTH),
conv_std_logic_vector(30601,AMPL_WIDTH),
conv_std_logic_vector(30602,AMPL_WIDTH),
conv_std_logic_vector(30603,AMPL_WIDTH),
conv_std_logic_vector(30604,AMPL_WIDTH),
conv_std_logic_vector(30605,AMPL_WIDTH),
conv_std_logic_vector(30606,AMPL_WIDTH),
conv_std_logic_vector(30607,AMPL_WIDTH),
conv_std_logic_vector(30609,AMPL_WIDTH),
conv_std_logic_vector(30610,AMPL_WIDTH),
conv_std_logic_vector(30611,AMPL_WIDTH),
conv_std_logic_vector(30612,AMPL_WIDTH),
conv_std_logic_vector(30613,AMPL_WIDTH),
conv_std_logic_vector(30614,AMPL_WIDTH),
conv_std_logic_vector(30615,AMPL_WIDTH),
conv_std_logic_vector(30616,AMPL_WIDTH),
conv_std_logic_vector(30617,AMPL_WIDTH),
conv_std_logic_vector(30619,AMPL_WIDTH),
conv_std_logic_vector(30620,AMPL_WIDTH),
conv_std_logic_vector(30621,AMPL_WIDTH),
conv_std_logic_vector(30622,AMPL_WIDTH),
conv_std_logic_vector(30623,AMPL_WIDTH),
conv_std_logic_vector(30624,AMPL_WIDTH),
conv_std_logic_vector(30625,AMPL_WIDTH),
conv_std_logic_vector(30626,AMPL_WIDTH),
conv_std_logic_vector(30628,AMPL_WIDTH),
conv_std_logic_vector(30629,AMPL_WIDTH),
conv_std_logic_vector(30630,AMPL_WIDTH),
conv_std_logic_vector(30631,AMPL_WIDTH),
conv_std_logic_vector(30632,AMPL_WIDTH),
conv_std_logic_vector(30633,AMPL_WIDTH),
conv_std_logic_vector(30634,AMPL_WIDTH),
conv_std_logic_vector(30635,AMPL_WIDTH),
conv_std_logic_vector(30636,AMPL_WIDTH),
conv_std_logic_vector(30638,AMPL_WIDTH),
conv_std_logic_vector(30639,AMPL_WIDTH),
conv_std_logic_vector(30640,AMPL_WIDTH),
conv_std_logic_vector(30641,AMPL_WIDTH),
conv_std_logic_vector(30642,AMPL_WIDTH),
conv_std_logic_vector(30643,AMPL_WIDTH),
conv_std_logic_vector(30644,AMPL_WIDTH),
conv_std_logic_vector(30645,AMPL_WIDTH),
conv_std_logic_vector(30646,AMPL_WIDTH),
conv_std_logic_vector(30648,AMPL_WIDTH),
conv_std_logic_vector(30649,AMPL_WIDTH),
conv_std_logic_vector(30650,AMPL_WIDTH),
conv_std_logic_vector(30651,AMPL_WIDTH),
conv_std_logic_vector(30652,AMPL_WIDTH),
conv_std_logic_vector(30653,AMPL_WIDTH),
conv_std_logic_vector(30654,AMPL_WIDTH),
conv_std_logic_vector(30655,AMPL_WIDTH),
conv_std_logic_vector(30656,AMPL_WIDTH),
conv_std_logic_vector(30658,AMPL_WIDTH),
conv_std_logic_vector(30659,AMPL_WIDTH),
conv_std_logic_vector(30660,AMPL_WIDTH),
conv_std_logic_vector(30661,AMPL_WIDTH),
conv_std_logic_vector(30662,AMPL_WIDTH),
conv_std_logic_vector(30663,AMPL_WIDTH),
conv_std_logic_vector(30664,AMPL_WIDTH),
conv_std_logic_vector(30665,AMPL_WIDTH),
conv_std_logic_vector(30666,AMPL_WIDTH),
conv_std_logic_vector(30668,AMPL_WIDTH),
conv_std_logic_vector(30669,AMPL_WIDTH),
conv_std_logic_vector(30670,AMPL_WIDTH),
conv_std_logic_vector(30671,AMPL_WIDTH),
conv_std_logic_vector(30672,AMPL_WIDTH),
conv_std_logic_vector(30673,AMPL_WIDTH),
conv_std_logic_vector(30674,AMPL_WIDTH),
conv_std_logic_vector(30675,AMPL_WIDTH),
conv_std_logic_vector(30676,AMPL_WIDTH),
conv_std_logic_vector(30678,AMPL_WIDTH),
conv_std_logic_vector(30679,AMPL_WIDTH),
conv_std_logic_vector(30680,AMPL_WIDTH),
conv_std_logic_vector(30681,AMPL_WIDTH),
conv_std_logic_vector(30682,AMPL_WIDTH),
conv_std_logic_vector(30683,AMPL_WIDTH),
conv_std_logic_vector(30684,AMPL_WIDTH),
conv_std_logic_vector(30685,AMPL_WIDTH),
conv_std_logic_vector(30686,AMPL_WIDTH),
conv_std_logic_vector(30687,AMPL_WIDTH),
conv_std_logic_vector(30689,AMPL_WIDTH),
conv_std_logic_vector(30690,AMPL_WIDTH),
conv_std_logic_vector(30691,AMPL_WIDTH),
conv_std_logic_vector(30692,AMPL_WIDTH),
conv_std_logic_vector(30693,AMPL_WIDTH),
conv_std_logic_vector(30694,AMPL_WIDTH),
conv_std_logic_vector(30695,AMPL_WIDTH),
conv_std_logic_vector(30696,AMPL_WIDTH),
conv_std_logic_vector(30697,AMPL_WIDTH),
conv_std_logic_vector(30698,AMPL_WIDTH),
conv_std_logic_vector(30700,AMPL_WIDTH),
conv_std_logic_vector(30701,AMPL_WIDTH),
conv_std_logic_vector(30702,AMPL_WIDTH),
conv_std_logic_vector(30703,AMPL_WIDTH),
conv_std_logic_vector(30704,AMPL_WIDTH),
conv_std_logic_vector(30705,AMPL_WIDTH),
conv_std_logic_vector(30706,AMPL_WIDTH),
conv_std_logic_vector(30707,AMPL_WIDTH),
conv_std_logic_vector(30708,AMPL_WIDTH),
conv_std_logic_vector(30709,AMPL_WIDTH),
conv_std_logic_vector(30711,AMPL_WIDTH),
conv_std_logic_vector(30712,AMPL_WIDTH),
conv_std_logic_vector(30713,AMPL_WIDTH),
conv_std_logic_vector(30714,AMPL_WIDTH),
conv_std_logic_vector(30715,AMPL_WIDTH),
conv_std_logic_vector(30716,AMPL_WIDTH),
conv_std_logic_vector(30717,AMPL_WIDTH),
conv_std_logic_vector(30718,AMPL_WIDTH),
conv_std_logic_vector(30719,AMPL_WIDTH),
conv_std_logic_vector(30720,AMPL_WIDTH),
conv_std_logic_vector(30721,AMPL_WIDTH),
conv_std_logic_vector(30723,AMPL_WIDTH),
conv_std_logic_vector(30724,AMPL_WIDTH),
conv_std_logic_vector(30725,AMPL_WIDTH),
conv_std_logic_vector(30726,AMPL_WIDTH),
conv_std_logic_vector(30727,AMPL_WIDTH),
conv_std_logic_vector(30728,AMPL_WIDTH),
conv_std_logic_vector(30729,AMPL_WIDTH),
conv_std_logic_vector(30730,AMPL_WIDTH),
conv_std_logic_vector(30731,AMPL_WIDTH),
conv_std_logic_vector(30732,AMPL_WIDTH),
conv_std_logic_vector(30733,AMPL_WIDTH),
conv_std_logic_vector(30735,AMPL_WIDTH),
conv_std_logic_vector(30736,AMPL_WIDTH),
conv_std_logic_vector(30737,AMPL_WIDTH),
conv_std_logic_vector(30738,AMPL_WIDTH),
conv_std_logic_vector(30739,AMPL_WIDTH),
conv_std_logic_vector(30740,AMPL_WIDTH),
conv_std_logic_vector(30741,AMPL_WIDTH),
conv_std_logic_vector(30742,AMPL_WIDTH),
conv_std_logic_vector(30743,AMPL_WIDTH),
conv_std_logic_vector(30744,AMPL_WIDTH),
conv_std_logic_vector(30745,AMPL_WIDTH),
conv_std_logic_vector(30746,AMPL_WIDTH),
conv_std_logic_vector(30748,AMPL_WIDTH),
conv_std_logic_vector(30749,AMPL_WIDTH),
conv_std_logic_vector(30750,AMPL_WIDTH),
conv_std_logic_vector(30751,AMPL_WIDTH),
conv_std_logic_vector(30752,AMPL_WIDTH),
conv_std_logic_vector(30753,AMPL_WIDTH),
conv_std_logic_vector(30754,AMPL_WIDTH),
conv_std_logic_vector(30755,AMPL_WIDTH),
conv_std_logic_vector(30756,AMPL_WIDTH),
conv_std_logic_vector(30757,AMPL_WIDTH),
conv_std_logic_vector(30758,AMPL_WIDTH),
conv_std_logic_vector(30760,AMPL_WIDTH),
conv_std_logic_vector(30761,AMPL_WIDTH),
conv_std_logic_vector(30762,AMPL_WIDTH),
conv_std_logic_vector(30763,AMPL_WIDTH),
conv_std_logic_vector(30764,AMPL_WIDTH),
conv_std_logic_vector(30765,AMPL_WIDTH),
conv_std_logic_vector(30766,AMPL_WIDTH),
conv_std_logic_vector(30767,AMPL_WIDTH),
conv_std_logic_vector(30768,AMPL_WIDTH),
conv_std_logic_vector(30769,AMPL_WIDTH),
conv_std_logic_vector(30770,AMPL_WIDTH),
conv_std_logic_vector(30771,AMPL_WIDTH),
conv_std_logic_vector(30772,AMPL_WIDTH),
conv_std_logic_vector(30774,AMPL_WIDTH),
conv_std_logic_vector(30775,AMPL_WIDTH),
conv_std_logic_vector(30776,AMPL_WIDTH),
conv_std_logic_vector(30777,AMPL_WIDTH),
conv_std_logic_vector(30778,AMPL_WIDTH),
conv_std_logic_vector(30779,AMPL_WIDTH),
conv_std_logic_vector(30780,AMPL_WIDTH),
conv_std_logic_vector(30781,AMPL_WIDTH),
conv_std_logic_vector(30782,AMPL_WIDTH),
conv_std_logic_vector(30783,AMPL_WIDTH),
conv_std_logic_vector(30784,AMPL_WIDTH),
conv_std_logic_vector(30785,AMPL_WIDTH),
conv_std_logic_vector(30786,AMPL_WIDTH),
conv_std_logic_vector(30788,AMPL_WIDTH),
conv_std_logic_vector(30789,AMPL_WIDTH),
conv_std_logic_vector(30790,AMPL_WIDTH),
conv_std_logic_vector(30791,AMPL_WIDTH),
conv_std_logic_vector(30792,AMPL_WIDTH),
conv_std_logic_vector(30793,AMPL_WIDTH),
conv_std_logic_vector(30794,AMPL_WIDTH),
conv_std_logic_vector(30795,AMPL_WIDTH),
conv_std_logic_vector(30796,AMPL_WIDTH),
conv_std_logic_vector(30797,AMPL_WIDTH),
conv_std_logic_vector(30798,AMPL_WIDTH),
conv_std_logic_vector(30799,AMPL_WIDTH),
conv_std_logic_vector(30800,AMPL_WIDTH),
conv_std_logic_vector(30802,AMPL_WIDTH),
conv_std_logic_vector(30803,AMPL_WIDTH),
conv_std_logic_vector(30804,AMPL_WIDTH),
conv_std_logic_vector(30805,AMPL_WIDTH),
conv_std_logic_vector(30806,AMPL_WIDTH),
conv_std_logic_vector(30807,AMPL_WIDTH),
conv_std_logic_vector(30808,AMPL_WIDTH),
conv_std_logic_vector(30809,AMPL_WIDTH),
conv_std_logic_vector(30810,AMPL_WIDTH),
conv_std_logic_vector(30811,AMPL_WIDTH),
conv_std_logic_vector(30812,AMPL_WIDTH),
conv_std_logic_vector(30813,AMPL_WIDTH),
conv_std_logic_vector(30814,AMPL_WIDTH),
conv_std_logic_vector(30815,AMPL_WIDTH),
conv_std_logic_vector(30816,AMPL_WIDTH),
conv_std_logic_vector(30818,AMPL_WIDTH),
conv_std_logic_vector(30819,AMPL_WIDTH),
conv_std_logic_vector(30820,AMPL_WIDTH),
conv_std_logic_vector(30821,AMPL_WIDTH),
conv_std_logic_vector(30822,AMPL_WIDTH),
conv_std_logic_vector(30823,AMPL_WIDTH),
conv_std_logic_vector(30824,AMPL_WIDTH),
conv_std_logic_vector(30825,AMPL_WIDTH),
conv_std_logic_vector(30826,AMPL_WIDTH),
conv_std_logic_vector(30827,AMPL_WIDTH),
conv_std_logic_vector(30828,AMPL_WIDTH),
conv_std_logic_vector(30829,AMPL_WIDTH),
conv_std_logic_vector(30830,AMPL_WIDTH),
conv_std_logic_vector(30831,AMPL_WIDTH),
conv_std_logic_vector(30832,AMPL_WIDTH),
conv_std_logic_vector(30834,AMPL_WIDTH),
conv_std_logic_vector(30835,AMPL_WIDTH),
conv_std_logic_vector(30836,AMPL_WIDTH),
conv_std_logic_vector(30837,AMPL_WIDTH),
conv_std_logic_vector(30838,AMPL_WIDTH),
conv_std_logic_vector(30839,AMPL_WIDTH),
conv_std_logic_vector(30840,AMPL_WIDTH),
conv_std_logic_vector(30841,AMPL_WIDTH),
conv_std_logic_vector(30842,AMPL_WIDTH),
conv_std_logic_vector(30843,AMPL_WIDTH),
conv_std_logic_vector(30844,AMPL_WIDTH),
conv_std_logic_vector(30845,AMPL_WIDTH),
conv_std_logic_vector(30846,AMPL_WIDTH),
conv_std_logic_vector(30847,AMPL_WIDTH),
conv_std_logic_vector(30848,AMPL_WIDTH),
conv_std_logic_vector(30849,AMPL_WIDTH),
conv_std_logic_vector(30851,AMPL_WIDTH),
conv_std_logic_vector(30852,AMPL_WIDTH),
conv_std_logic_vector(30853,AMPL_WIDTH),
conv_std_logic_vector(30854,AMPL_WIDTH),
conv_std_logic_vector(30855,AMPL_WIDTH),
conv_std_logic_vector(30856,AMPL_WIDTH),
conv_std_logic_vector(30857,AMPL_WIDTH),
conv_std_logic_vector(30858,AMPL_WIDTH),
conv_std_logic_vector(30859,AMPL_WIDTH),
conv_std_logic_vector(30860,AMPL_WIDTH),
conv_std_logic_vector(30861,AMPL_WIDTH),
conv_std_logic_vector(30862,AMPL_WIDTH),
conv_std_logic_vector(30863,AMPL_WIDTH),
conv_std_logic_vector(30864,AMPL_WIDTH),
conv_std_logic_vector(30865,AMPL_WIDTH),
conv_std_logic_vector(30866,AMPL_WIDTH),
conv_std_logic_vector(30867,AMPL_WIDTH),
conv_std_logic_vector(30868,AMPL_WIDTH),
conv_std_logic_vector(30870,AMPL_WIDTH),
conv_std_logic_vector(30871,AMPL_WIDTH),
conv_std_logic_vector(30872,AMPL_WIDTH),
conv_std_logic_vector(30873,AMPL_WIDTH),
conv_std_logic_vector(30874,AMPL_WIDTH),
conv_std_logic_vector(30875,AMPL_WIDTH),
conv_std_logic_vector(30876,AMPL_WIDTH),
conv_std_logic_vector(30877,AMPL_WIDTH),
conv_std_logic_vector(30878,AMPL_WIDTH),
conv_std_logic_vector(30879,AMPL_WIDTH),
conv_std_logic_vector(30880,AMPL_WIDTH),
conv_std_logic_vector(30881,AMPL_WIDTH),
conv_std_logic_vector(30882,AMPL_WIDTH),
conv_std_logic_vector(30883,AMPL_WIDTH),
conv_std_logic_vector(30884,AMPL_WIDTH),
conv_std_logic_vector(30885,AMPL_WIDTH),
conv_std_logic_vector(30886,AMPL_WIDTH),
conv_std_logic_vector(30887,AMPL_WIDTH),
conv_std_logic_vector(30888,AMPL_WIDTH),
conv_std_logic_vector(30889,AMPL_WIDTH),
conv_std_logic_vector(30891,AMPL_WIDTH),
conv_std_logic_vector(30892,AMPL_WIDTH),
conv_std_logic_vector(30893,AMPL_WIDTH),
conv_std_logic_vector(30894,AMPL_WIDTH),
conv_std_logic_vector(30895,AMPL_WIDTH),
conv_std_logic_vector(30896,AMPL_WIDTH),
conv_std_logic_vector(30897,AMPL_WIDTH),
conv_std_logic_vector(30898,AMPL_WIDTH),
conv_std_logic_vector(30899,AMPL_WIDTH),
conv_std_logic_vector(30900,AMPL_WIDTH),
conv_std_logic_vector(30901,AMPL_WIDTH),
conv_std_logic_vector(30902,AMPL_WIDTH),
conv_std_logic_vector(30903,AMPL_WIDTH),
conv_std_logic_vector(30904,AMPL_WIDTH),
conv_std_logic_vector(30905,AMPL_WIDTH),
conv_std_logic_vector(30906,AMPL_WIDTH),
conv_std_logic_vector(30907,AMPL_WIDTH),
conv_std_logic_vector(30908,AMPL_WIDTH),
conv_std_logic_vector(30909,AMPL_WIDTH),
conv_std_logic_vector(30910,AMPL_WIDTH),
conv_std_logic_vector(30911,AMPL_WIDTH),
conv_std_logic_vector(30912,AMPL_WIDTH),
conv_std_logic_vector(30914,AMPL_WIDTH),
conv_std_logic_vector(30915,AMPL_WIDTH),
conv_std_logic_vector(30916,AMPL_WIDTH),
conv_std_logic_vector(30917,AMPL_WIDTH),
conv_std_logic_vector(30918,AMPL_WIDTH),
conv_std_logic_vector(30919,AMPL_WIDTH),
conv_std_logic_vector(30920,AMPL_WIDTH),
conv_std_logic_vector(30921,AMPL_WIDTH),
conv_std_logic_vector(30922,AMPL_WIDTH),
conv_std_logic_vector(30923,AMPL_WIDTH),
conv_std_logic_vector(30924,AMPL_WIDTH),
conv_std_logic_vector(30925,AMPL_WIDTH),
conv_std_logic_vector(30926,AMPL_WIDTH),
conv_std_logic_vector(30927,AMPL_WIDTH),
conv_std_logic_vector(30928,AMPL_WIDTH),
conv_std_logic_vector(30929,AMPL_WIDTH),
conv_std_logic_vector(30930,AMPL_WIDTH),
conv_std_logic_vector(30931,AMPL_WIDTH),
conv_std_logic_vector(30932,AMPL_WIDTH),
conv_std_logic_vector(30933,AMPL_WIDTH),
conv_std_logic_vector(30934,AMPL_WIDTH),
conv_std_logic_vector(30935,AMPL_WIDTH),
conv_std_logic_vector(30936,AMPL_WIDTH),
conv_std_logic_vector(30937,AMPL_WIDTH),
conv_std_logic_vector(30938,AMPL_WIDTH),
conv_std_logic_vector(30939,AMPL_WIDTH),
conv_std_logic_vector(30941,AMPL_WIDTH),
conv_std_logic_vector(30942,AMPL_WIDTH),
conv_std_logic_vector(30943,AMPL_WIDTH),
conv_std_logic_vector(30944,AMPL_WIDTH),
conv_std_logic_vector(30945,AMPL_WIDTH),
conv_std_logic_vector(30946,AMPL_WIDTH),
conv_std_logic_vector(30947,AMPL_WIDTH),
conv_std_logic_vector(30948,AMPL_WIDTH),
conv_std_logic_vector(30949,AMPL_WIDTH),
conv_std_logic_vector(30950,AMPL_WIDTH),
conv_std_logic_vector(30951,AMPL_WIDTH),
conv_std_logic_vector(30952,AMPL_WIDTH),
conv_std_logic_vector(30953,AMPL_WIDTH),
conv_std_logic_vector(30954,AMPL_WIDTH),
conv_std_logic_vector(30955,AMPL_WIDTH),
conv_std_logic_vector(30956,AMPL_WIDTH),
conv_std_logic_vector(30957,AMPL_WIDTH),
conv_std_logic_vector(30958,AMPL_WIDTH),
conv_std_logic_vector(30959,AMPL_WIDTH),
conv_std_logic_vector(30960,AMPL_WIDTH),
conv_std_logic_vector(30961,AMPL_WIDTH),
conv_std_logic_vector(30962,AMPL_WIDTH),
conv_std_logic_vector(30963,AMPL_WIDTH),
conv_std_logic_vector(30964,AMPL_WIDTH),
conv_std_logic_vector(30965,AMPL_WIDTH),
conv_std_logic_vector(30966,AMPL_WIDTH),
conv_std_logic_vector(30967,AMPL_WIDTH),
conv_std_logic_vector(30968,AMPL_WIDTH),
conv_std_logic_vector(30969,AMPL_WIDTH),
conv_std_logic_vector(30970,AMPL_WIDTH),
conv_std_logic_vector(30971,AMPL_WIDTH),
conv_std_logic_vector(30972,AMPL_WIDTH),
conv_std_logic_vector(30973,AMPL_WIDTH),
conv_std_logic_vector(30974,AMPL_WIDTH),
conv_std_logic_vector(30976,AMPL_WIDTH),
conv_std_logic_vector(30977,AMPL_WIDTH),
conv_std_logic_vector(30978,AMPL_WIDTH),
conv_std_logic_vector(30979,AMPL_WIDTH),
conv_std_logic_vector(30980,AMPL_WIDTH),
conv_std_logic_vector(30981,AMPL_WIDTH),
conv_std_logic_vector(30982,AMPL_WIDTH),
conv_std_logic_vector(30983,AMPL_WIDTH),
conv_std_logic_vector(30984,AMPL_WIDTH),
conv_std_logic_vector(30985,AMPL_WIDTH),
conv_std_logic_vector(30986,AMPL_WIDTH),
conv_std_logic_vector(30987,AMPL_WIDTH),
conv_std_logic_vector(30988,AMPL_WIDTH),
conv_std_logic_vector(30989,AMPL_WIDTH),
conv_std_logic_vector(30990,AMPL_WIDTH),
conv_std_logic_vector(30991,AMPL_WIDTH),
conv_std_logic_vector(30992,AMPL_WIDTH),
conv_std_logic_vector(30993,AMPL_WIDTH),
conv_std_logic_vector(30994,AMPL_WIDTH),
conv_std_logic_vector(30995,AMPL_WIDTH),
conv_std_logic_vector(30996,AMPL_WIDTH),
conv_std_logic_vector(30997,AMPL_WIDTH),
conv_std_logic_vector(30998,AMPL_WIDTH),
conv_std_logic_vector(30999,AMPL_WIDTH),
conv_std_logic_vector(31000,AMPL_WIDTH),
conv_std_logic_vector(31001,AMPL_WIDTH),
conv_std_logic_vector(31002,AMPL_WIDTH),
conv_std_logic_vector(31003,AMPL_WIDTH),
conv_std_logic_vector(31004,AMPL_WIDTH),
conv_std_logic_vector(31005,AMPL_WIDTH),
conv_std_logic_vector(31006,AMPL_WIDTH),
conv_std_logic_vector(31007,AMPL_WIDTH),
conv_std_logic_vector(31008,AMPL_WIDTH),
conv_std_logic_vector(31009,AMPL_WIDTH),
conv_std_logic_vector(31010,AMPL_WIDTH),
conv_std_logic_vector(31011,AMPL_WIDTH),
conv_std_logic_vector(31012,AMPL_WIDTH),
conv_std_logic_vector(31013,AMPL_WIDTH),
conv_std_logic_vector(31014,AMPL_WIDTH),
conv_std_logic_vector(31015,AMPL_WIDTH),
conv_std_logic_vector(31016,AMPL_WIDTH),
conv_std_logic_vector(31017,AMPL_WIDTH),
conv_std_logic_vector(31018,AMPL_WIDTH),
conv_std_logic_vector(31019,AMPL_WIDTH),
conv_std_logic_vector(31020,AMPL_WIDTH),
conv_std_logic_vector(31021,AMPL_WIDTH),
conv_std_logic_vector(31022,AMPL_WIDTH),
conv_std_logic_vector(31023,AMPL_WIDTH),
conv_std_logic_vector(31024,AMPL_WIDTH),
conv_std_logic_vector(31025,AMPL_WIDTH),
conv_std_logic_vector(31026,AMPL_WIDTH),
conv_std_logic_vector(31027,AMPL_WIDTH),
conv_std_logic_vector(31028,AMPL_WIDTH),
conv_std_logic_vector(31029,AMPL_WIDTH),
conv_std_logic_vector(31030,AMPL_WIDTH),
conv_std_logic_vector(31031,AMPL_WIDTH),
conv_std_logic_vector(31032,AMPL_WIDTH),
conv_std_logic_vector(31033,AMPL_WIDTH),
conv_std_logic_vector(31034,AMPL_WIDTH),
conv_std_logic_vector(31035,AMPL_WIDTH),
conv_std_logic_vector(31036,AMPL_WIDTH),
conv_std_logic_vector(31037,AMPL_WIDTH),
conv_std_logic_vector(31038,AMPL_WIDTH),
conv_std_logic_vector(31039,AMPL_WIDTH),
conv_std_logic_vector(31040,AMPL_WIDTH),
conv_std_logic_vector(31041,AMPL_WIDTH),
conv_std_logic_vector(31043,AMPL_WIDTH),
conv_std_logic_vector(31044,AMPL_WIDTH),
conv_std_logic_vector(31045,AMPL_WIDTH),
conv_std_logic_vector(31046,AMPL_WIDTH),
conv_std_logic_vector(31047,AMPL_WIDTH),
conv_std_logic_vector(31048,AMPL_WIDTH),
conv_std_logic_vector(31049,AMPL_WIDTH),
conv_std_logic_vector(31050,AMPL_WIDTH),
conv_std_logic_vector(31051,AMPL_WIDTH),
conv_std_logic_vector(31052,AMPL_WIDTH),
conv_std_logic_vector(31053,AMPL_WIDTH),
conv_std_logic_vector(31054,AMPL_WIDTH),
conv_std_logic_vector(31055,AMPL_WIDTH),
conv_std_logic_vector(31056,AMPL_WIDTH),
conv_std_logic_vector(31057,AMPL_WIDTH),
conv_std_logic_vector(31058,AMPL_WIDTH),
conv_std_logic_vector(31059,AMPL_WIDTH),
conv_std_logic_vector(31060,AMPL_WIDTH),
conv_std_logic_vector(31061,AMPL_WIDTH),
conv_std_logic_vector(31062,AMPL_WIDTH),
conv_std_logic_vector(31063,AMPL_WIDTH),
conv_std_logic_vector(31064,AMPL_WIDTH),
conv_std_logic_vector(31065,AMPL_WIDTH),
conv_std_logic_vector(31066,AMPL_WIDTH),
conv_std_logic_vector(31067,AMPL_WIDTH),
conv_std_logic_vector(31068,AMPL_WIDTH),
conv_std_logic_vector(31069,AMPL_WIDTH),
conv_std_logic_vector(31070,AMPL_WIDTH),
conv_std_logic_vector(31071,AMPL_WIDTH),
conv_std_logic_vector(31072,AMPL_WIDTH),
conv_std_logic_vector(31073,AMPL_WIDTH),
conv_std_logic_vector(31074,AMPL_WIDTH),
conv_std_logic_vector(31075,AMPL_WIDTH),
conv_std_logic_vector(31076,AMPL_WIDTH),
conv_std_logic_vector(31077,AMPL_WIDTH),
conv_std_logic_vector(31078,AMPL_WIDTH),
conv_std_logic_vector(31079,AMPL_WIDTH),
conv_std_logic_vector(31080,AMPL_WIDTH),
conv_std_logic_vector(31081,AMPL_WIDTH),
conv_std_logic_vector(31082,AMPL_WIDTH),
conv_std_logic_vector(31083,AMPL_WIDTH),
conv_std_logic_vector(31083,AMPL_WIDTH),
conv_std_logic_vector(31084,AMPL_WIDTH),
conv_std_logic_vector(31085,AMPL_WIDTH),
conv_std_logic_vector(31086,AMPL_WIDTH),
conv_std_logic_vector(31087,AMPL_WIDTH),
conv_std_logic_vector(31088,AMPL_WIDTH),
conv_std_logic_vector(31089,AMPL_WIDTH),
conv_std_logic_vector(31090,AMPL_WIDTH),
conv_std_logic_vector(31091,AMPL_WIDTH),
conv_std_logic_vector(31092,AMPL_WIDTH),
conv_std_logic_vector(31093,AMPL_WIDTH),
conv_std_logic_vector(31094,AMPL_WIDTH),
conv_std_logic_vector(31095,AMPL_WIDTH),
conv_std_logic_vector(31096,AMPL_WIDTH),
conv_std_logic_vector(31097,AMPL_WIDTH),
conv_std_logic_vector(31098,AMPL_WIDTH),
conv_std_logic_vector(31099,AMPL_WIDTH),
conv_std_logic_vector(31100,AMPL_WIDTH),
conv_std_logic_vector(31101,AMPL_WIDTH),
conv_std_logic_vector(31102,AMPL_WIDTH),
conv_std_logic_vector(31103,AMPL_WIDTH),
conv_std_logic_vector(31104,AMPL_WIDTH),
conv_std_logic_vector(31105,AMPL_WIDTH),
conv_std_logic_vector(31106,AMPL_WIDTH),
conv_std_logic_vector(31107,AMPL_WIDTH),
conv_std_logic_vector(31108,AMPL_WIDTH),
conv_std_logic_vector(31109,AMPL_WIDTH),
conv_std_logic_vector(31110,AMPL_WIDTH),
conv_std_logic_vector(31111,AMPL_WIDTH),
conv_std_logic_vector(31112,AMPL_WIDTH),
conv_std_logic_vector(31113,AMPL_WIDTH),
conv_std_logic_vector(31114,AMPL_WIDTH),
conv_std_logic_vector(31115,AMPL_WIDTH),
conv_std_logic_vector(31116,AMPL_WIDTH),
conv_std_logic_vector(31117,AMPL_WIDTH),
conv_std_logic_vector(31118,AMPL_WIDTH),
conv_std_logic_vector(31119,AMPL_WIDTH),
conv_std_logic_vector(31120,AMPL_WIDTH),
conv_std_logic_vector(31121,AMPL_WIDTH),
conv_std_logic_vector(31122,AMPL_WIDTH),
conv_std_logic_vector(31123,AMPL_WIDTH),
conv_std_logic_vector(31124,AMPL_WIDTH),
conv_std_logic_vector(31125,AMPL_WIDTH),
conv_std_logic_vector(31126,AMPL_WIDTH),
conv_std_logic_vector(31127,AMPL_WIDTH),
conv_std_logic_vector(31128,AMPL_WIDTH),
conv_std_logic_vector(31129,AMPL_WIDTH),
conv_std_logic_vector(31130,AMPL_WIDTH),
conv_std_logic_vector(31131,AMPL_WIDTH),
conv_std_logic_vector(31132,AMPL_WIDTH),
conv_std_logic_vector(31133,AMPL_WIDTH),
conv_std_logic_vector(31134,AMPL_WIDTH),
conv_std_logic_vector(31135,AMPL_WIDTH),
conv_std_logic_vector(31136,AMPL_WIDTH),
conv_std_logic_vector(31137,AMPL_WIDTH),
conv_std_logic_vector(31138,AMPL_WIDTH),
conv_std_logic_vector(31139,AMPL_WIDTH),
conv_std_logic_vector(31140,AMPL_WIDTH),
conv_std_logic_vector(31141,AMPL_WIDTH),
conv_std_logic_vector(31142,AMPL_WIDTH),
conv_std_logic_vector(31143,AMPL_WIDTH),
conv_std_logic_vector(31144,AMPL_WIDTH),
conv_std_logic_vector(31145,AMPL_WIDTH),
conv_std_logic_vector(31146,AMPL_WIDTH),
conv_std_logic_vector(31147,AMPL_WIDTH),
conv_std_logic_vector(31148,AMPL_WIDTH),
conv_std_logic_vector(31148,AMPL_WIDTH),
conv_std_logic_vector(31149,AMPL_WIDTH),
conv_std_logic_vector(31150,AMPL_WIDTH),
conv_std_logic_vector(31151,AMPL_WIDTH),
conv_std_logic_vector(31152,AMPL_WIDTH),
conv_std_logic_vector(31153,AMPL_WIDTH),
conv_std_logic_vector(31154,AMPL_WIDTH),
conv_std_logic_vector(31155,AMPL_WIDTH),
conv_std_logic_vector(31156,AMPL_WIDTH),
conv_std_logic_vector(31157,AMPL_WIDTH),
conv_std_logic_vector(31158,AMPL_WIDTH),
conv_std_logic_vector(31159,AMPL_WIDTH),
conv_std_logic_vector(31160,AMPL_WIDTH),
conv_std_logic_vector(31161,AMPL_WIDTH),
conv_std_logic_vector(31162,AMPL_WIDTH),
conv_std_logic_vector(31163,AMPL_WIDTH),
conv_std_logic_vector(31164,AMPL_WIDTH),
conv_std_logic_vector(31165,AMPL_WIDTH),
conv_std_logic_vector(31166,AMPL_WIDTH),
conv_std_logic_vector(31167,AMPL_WIDTH),
conv_std_logic_vector(31168,AMPL_WIDTH),
conv_std_logic_vector(31169,AMPL_WIDTH),
conv_std_logic_vector(31170,AMPL_WIDTH),
conv_std_logic_vector(31171,AMPL_WIDTH),
conv_std_logic_vector(31172,AMPL_WIDTH),
conv_std_logic_vector(31173,AMPL_WIDTH),
conv_std_logic_vector(31174,AMPL_WIDTH),
conv_std_logic_vector(31175,AMPL_WIDTH),
conv_std_logic_vector(31176,AMPL_WIDTH),
conv_std_logic_vector(31177,AMPL_WIDTH),
conv_std_logic_vector(31178,AMPL_WIDTH),
conv_std_logic_vector(31179,AMPL_WIDTH),
conv_std_logic_vector(31180,AMPL_WIDTH),
conv_std_logic_vector(31181,AMPL_WIDTH),
conv_std_logic_vector(31181,AMPL_WIDTH),
conv_std_logic_vector(31182,AMPL_WIDTH),
conv_std_logic_vector(31183,AMPL_WIDTH),
conv_std_logic_vector(31184,AMPL_WIDTH),
conv_std_logic_vector(31185,AMPL_WIDTH),
conv_std_logic_vector(31186,AMPL_WIDTH),
conv_std_logic_vector(31187,AMPL_WIDTH),
conv_std_logic_vector(31188,AMPL_WIDTH),
conv_std_logic_vector(31189,AMPL_WIDTH),
conv_std_logic_vector(31190,AMPL_WIDTH),
conv_std_logic_vector(31191,AMPL_WIDTH),
conv_std_logic_vector(31192,AMPL_WIDTH),
conv_std_logic_vector(31193,AMPL_WIDTH),
conv_std_logic_vector(31194,AMPL_WIDTH),
conv_std_logic_vector(31195,AMPL_WIDTH),
conv_std_logic_vector(31196,AMPL_WIDTH),
conv_std_logic_vector(31197,AMPL_WIDTH),
conv_std_logic_vector(31198,AMPL_WIDTH),
conv_std_logic_vector(31199,AMPL_WIDTH),
conv_std_logic_vector(31200,AMPL_WIDTH),
conv_std_logic_vector(31201,AMPL_WIDTH),
conv_std_logic_vector(31202,AMPL_WIDTH),
conv_std_logic_vector(31203,AMPL_WIDTH),
conv_std_logic_vector(31204,AMPL_WIDTH),
conv_std_logic_vector(31205,AMPL_WIDTH),
conv_std_logic_vector(31206,AMPL_WIDTH),
conv_std_logic_vector(31206,AMPL_WIDTH),
conv_std_logic_vector(31207,AMPL_WIDTH),
conv_std_logic_vector(31208,AMPL_WIDTH),
conv_std_logic_vector(31209,AMPL_WIDTH),
conv_std_logic_vector(31210,AMPL_WIDTH),
conv_std_logic_vector(31211,AMPL_WIDTH),
conv_std_logic_vector(31212,AMPL_WIDTH),
conv_std_logic_vector(31213,AMPL_WIDTH),
conv_std_logic_vector(31214,AMPL_WIDTH),
conv_std_logic_vector(31215,AMPL_WIDTH),
conv_std_logic_vector(31216,AMPL_WIDTH),
conv_std_logic_vector(31217,AMPL_WIDTH),
conv_std_logic_vector(31218,AMPL_WIDTH),
conv_std_logic_vector(31219,AMPL_WIDTH),
conv_std_logic_vector(31220,AMPL_WIDTH),
conv_std_logic_vector(31221,AMPL_WIDTH),
conv_std_logic_vector(31222,AMPL_WIDTH),
conv_std_logic_vector(31223,AMPL_WIDTH),
conv_std_logic_vector(31224,AMPL_WIDTH),
conv_std_logic_vector(31225,AMPL_WIDTH),
conv_std_logic_vector(31226,AMPL_WIDTH),
conv_std_logic_vector(31227,AMPL_WIDTH),
conv_std_logic_vector(31227,AMPL_WIDTH),
conv_std_logic_vector(31228,AMPL_WIDTH),
conv_std_logic_vector(31229,AMPL_WIDTH),
conv_std_logic_vector(31230,AMPL_WIDTH),
conv_std_logic_vector(31231,AMPL_WIDTH),
conv_std_logic_vector(31232,AMPL_WIDTH),
conv_std_logic_vector(31233,AMPL_WIDTH),
conv_std_logic_vector(31234,AMPL_WIDTH),
conv_std_logic_vector(31235,AMPL_WIDTH),
conv_std_logic_vector(31236,AMPL_WIDTH),
conv_std_logic_vector(31237,AMPL_WIDTH),
conv_std_logic_vector(31238,AMPL_WIDTH),
conv_std_logic_vector(31239,AMPL_WIDTH),
conv_std_logic_vector(31240,AMPL_WIDTH),
conv_std_logic_vector(31241,AMPL_WIDTH),
conv_std_logic_vector(31242,AMPL_WIDTH),
conv_std_logic_vector(31243,AMPL_WIDTH),
conv_std_logic_vector(31244,AMPL_WIDTH),
conv_std_logic_vector(31245,AMPL_WIDTH),
conv_std_logic_vector(31246,AMPL_WIDTH),
conv_std_logic_vector(31246,AMPL_WIDTH),
conv_std_logic_vector(31247,AMPL_WIDTH),
conv_std_logic_vector(31248,AMPL_WIDTH),
conv_std_logic_vector(31249,AMPL_WIDTH),
conv_std_logic_vector(31250,AMPL_WIDTH),
conv_std_logic_vector(31251,AMPL_WIDTH),
conv_std_logic_vector(31252,AMPL_WIDTH),
conv_std_logic_vector(31253,AMPL_WIDTH),
conv_std_logic_vector(31254,AMPL_WIDTH),
conv_std_logic_vector(31255,AMPL_WIDTH),
conv_std_logic_vector(31256,AMPL_WIDTH),
conv_std_logic_vector(31257,AMPL_WIDTH),
conv_std_logic_vector(31258,AMPL_WIDTH),
conv_std_logic_vector(31259,AMPL_WIDTH),
conv_std_logic_vector(31260,AMPL_WIDTH),
conv_std_logic_vector(31261,AMPL_WIDTH),
conv_std_logic_vector(31262,AMPL_WIDTH),
conv_std_logic_vector(31262,AMPL_WIDTH),
conv_std_logic_vector(31263,AMPL_WIDTH),
conv_std_logic_vector(31264,AMPL_WIDTH),
conv_std_logic_vector(31265,AMPL_WIDTH),
conv_std_logic_vector(31266,AMPL_WIDTH),
conv_std_logic_vector(31267,AMPL_WIDTH),
conv_std_logic_vector(31268,AMPL_WIDTH),
conv_std_logic_vector(31269,AMPL_WIDTH),
conv_std_logic_vector(31270,AMPL_WIDTH),
conv_std_logic_vector(31271,AMPL_WIDTH),
conv_std_logic_vector(31272,AMPL_WIDTH),
conv_std_logic_vector(31273,AMPL_WIDTH),
conv_std_logic_vector(31274,AMPL_WIDTH),
conv_std_logic_vector(31275,AMPL_WIDTH),
conv_std_logic_vector(31276,AMPL_WIDTH),
conv_std_logic_vector(31277,AMPL_WIDTH),
conv_std_logic_vector(31278,AMPL_WIDTH),
conv_std_logic_vector(31278,AMPL_WIDTH),
conv_std_logic_vector(31279,AMPL_WIDTH),
conv_std_logic_vector(31280,AMPL_WIDTH),
conv_std_logic_vector(31281,AMPL_WIDTH),
conv_std_logic_vector(31282,AMPL_WIDTH),
conv_std_logic_vector(31283,AMPL_WIDTH),
conv_std_logic_vector(31284,AMPL_WIDTH),
conv_std_logic_vector(31285,AMPL_WIDTH),
conv_std_logic_vector(31286,AMPL_WIDTH),
conv_std_logic_vector(31287,AMPL_WIDTH),
conv_std_logic_vector(31288,AMPL_WIDTH),
conv_std_logic_vector(31289,AMPL_WIDTH),
conv_std_logic_vector(31290,AMPL_WIDTH),
conv_std_logic_vector(31291,AMPL_WIDTH),
conv_std_logic_vector(31292,AMPL_WIDTH),
conv_std_logic_vector(31292,AMPL_WIDTH),
conv_std_logic_vector(31293,AMPL_WIDTH),
conv_std_logic_vector(31294,AMPL_WIDTH),
conv_std_logic_vector(31295,AMPL_WIDTH),
conv_std_logic_vector(31296,AMPL_WIDTH),
conv_std_logic_vector(31297,AMPL_WIDTH),
conv_std_logic_vector(31298,AMPL_WIDTH),
conv_std_logic_vector(31299,AMPL_WIDTH),
conv_std_logic_vector(31300,AMPL_WIDTH),
conv_std_logic_vector(31301,AMPL_WIDTH),
conv_std_logic_vector(31302,AMPL_WIDTH),
conv_std_logic_vector(31303,AMPL_WIDTH),
conv_std_logic_vector(31304,AMPL_WIDTH),
conv_std_logic_vector(31305,AMPL_WIDTH),
conv_std_logic_vector(31305,AMPL_WIDTH),
conv_std_logic_vector(31306,AMPL_WIDTH),
conv_std_logic_vector(31307,AMPL_WIDTH),
conv_std_logic_vector(31308,AMPL_WIDTH),
conv_std_logic_vector(31309,AMPL_WIDTH),
conv_std_logic_vector(31310,AMPL_WIDTH),
conv_std_logic_vector(31311,AMPL_WIDTH),
conv_std_logic_vector(31312,AMPL_WIDTH),
conv_std_logic_vector(31313,AMPL_WIDTH),
conv_std_logic_vector(31314,AMPL_WIDTH),
conv_std_logic_vector(31315,AMPL_WIDTH),
conv_std_logic_vector(31316,AMPL_WIDTH),
conv_std_logic_vector(31317,AMPL_WIDTH),
conv_std_logic_vector(31318,AMPL_WIDTH),
conv_std_logic_vector(31318,AMPL_WIDTH),
conv_std_logic_vector(31319,AMPL_WIDTH),
conv_std_logic_vector(31320,AMPL_WIDTH),
conv_std_logic_vector(31321,AMPL_WIDTH),
conv_std_logic_vector(31322,AMPL_WIDTH),
conv_std_logic_vector(31323,AMPL_WIDTH),
conv_std_logic_vector(31324,AMPL_WIDTH),
conv_std_logic_vector(31325,AMPL_WIDTH),
conv_std_logic_vector(31326,AMPL_WIDTH),
conv_std_logic_vector(31327,AMPL_WIDTH),
conv_std_logic_vector(31328,AMPL_WIDTH),
conv_std_logic_vector(31329,AMPL_WIDTH),
conv_std_logic_vector(31329,AMPL_WIDTH),
conv_std_logic_vector(31330,AMPL_WIDTH),
conv_std_logic_vector(31331,AMPL_WIDTH),
conv_std_logic_vector(31332,AMPL_WIDTH),
conv_std_logic_vector(31333,AMPL_WIDTH),
conv_std_logic_vector(31334,AMPL_WIDTH),
conv_std_logic_vector(31335,AMPL_WIDTH),
conv_std_logic_vector(31336,AMPL_WIDTH),
conv_std_logic_vector(31337,AMPL_WIDTH),
conv_std_logic_vector(31338,AMPL_WIDTH),
conv_std_logic_vector(31339,AMPL_WIDTH),
conv_std_logic_vector(31340,AMPL_WIDTH),
conv_std_logic_vector(31341,AMPL_WIDTH),
conv_std_logic_vector(31341,AMPL_WIDTH),
conv_std_logic_vector(31342,AMPL_WIDTH),
conv_std_logic_vector(31343,AMPL_WIDTH),
conv_std_logic_vector(31344,AMPL_WIDTH),
conv_std_logic_vector(31345,AMPL_WIDTH),
conv_std_logic_vector(31346,AMPL_WIDTH),
conv_std_logic_vector(31347,AMPL_WIDTH),
conv_std_logic_vector(31348,AMPL_WIDTH),
conv_std_logic_vector(31349,AMPL_WIDTH),
conv_std_logic_vector(31350,AMPL_WIDTH),
conv_std_logic_vector(31351,AMPL_WIDTH),
conv_std_logic_vector(31352,AMPL_WIDTH),
conv_std_logic_vector(31352,AMPL_WIDTH),
conv_std_logic_vector(31353,AMPL_WIDTH),
conv_std_logic_vector(31354,AMPL_WIDTH),
conv_std_logic_vector(31355,AMPL_WIDTH),
conv_std_logic_vector(31356,AMPL_WIDTH),
conv_std_logic_vector(31357,AMPL_WIDTH),
conv_std_logic_vector(31358,AMPL_WIDTH),
conv_std_logic_vector(31359,AMPL_WIDTH),
conv_std_logic_vector(31360,AMPL_WIDTH),
conv_std_logic_vector(31361,AMPL_WIDTH),
conv_std_logic_vector(31362,AMPL_WIDTH),
conv_std_logic_vector(31362,AMPL_WIDTH),
conv_std_logic_vector(31363,AMPL_WIDTH),
conv_std_logic_vector(31364,AMPL_WIDTH),
conv_std_logic_vector(31365,AMPL_WIDTH),
conv_std_logic_vector(31366,AMPL_WIDTH),
conv_std_logic_vector(31367,AMPL_WIDTH),
conv_std_logic_vector(31368,AMPL_WIDTH),
conv_std_logic_vector(31369,AMPL_WIDTH),
conv_std_logic_vector(31370,AMPL_WIDTH),
conv_std_logic_vector(31371,AMPL_WIDTH),
conv_std_logic_vector(31372,AMPL_WIDTH),
conv_std_logic_vector(31372,AMPL_WIDTH),
conv_std_logic_vector(31373,AMPL_WIDTH),
conv_std_logic_vector(31374,AMPL_WIDTH),
conv_std_logic_vector(31375,AMPL_WIDTH),
conv_std_logic_vector(31376,AMPL_WIDTH),
conv_std_logic_vector(31377,AMPL_WIDTH),
conv_std_logic_vector(31378,AMPL_WIDTH),
conv_std_logic_vector(31379,AMPL_WIDTH),
conv_std_logic_vector(31380,AMPL_WIDTH),
conv_std_logic_vector(31381,AMPL_WIDTH),
conv_std_logic_vector(31381,AMPL_WIDTH),
conv_std_logic_vector(31382,AMPL_WIDTH),
conv_std_logic_vector(31383,AMPL_WIDTH),
conv_std_logic_vector(31384,AMPL_WIDTH),
conv_std_logic_vector(31385,AMPL_WIDTH),
conv_std_logic_vector(31386,AMPL_WIDTH),
conv_std_logic_vector(31387,AMPL_WIDTH),
conv_std_logic_vector(31388,AMPL_WIDTH),
conv_std_logic_vector(31389,AMPL_WIDTH),
conv_std_logic_vector(31390,AMPL_WIDTH),
conv_std_logic_vector(31391,AMPL_WIDTH),
conv_std_logic_vector(31391,AMPL_WIDTH),
conv_std_logic_vector(31392,AMPL_WIDTH),
conv_std_logic_vector(31393,AMPL_WIDTH),
conv_std_logic_vector(31394,AMPL_WIDTH),
conv_std_logic_vector(31395,AMPL_WIDTH),
conv_std_logic_vector(31396,AMPL_WIDTH),
conv_std_logic_vector(31397,AMPL_WIDTH),
conv_std_logic_vector(31398,AMPL_WIDTH),
conv_std_logic_vector(31399,AMPL_WIDTH),
conv_std_logic_vector(31400,AMPL_WIDTH),
conv_std_logic_vector(31400,AMPL_WIDTH),
conv_std_logic_vector(31401,AMPL_WIDTH),
conv_std_logic_vector(31402,AMPL_WIDTH),
conv_std_logic_vector(31403,AMPL_WIDTH),
conv_std_logic_vector(31404,AMPL_WIDTH),
conv_std_logic_vector(31405,AMPL_WIDTH),
conv_std_logic_vector(31406,AMPL_WIDTH),
conv_std_logic_vector(31407,AMPL_WIDTH),
conv_std_logic_vector(31408,AMPL_WIDTH),
conv_std_logic_vector(31408,AMPL_WIDTH),
conv_std_logic_vector(31409,AMPL_WIDTH),
conv_std_logic_vector(31410,AMPL_WIDTH),
conv_std_logic_vector(31411,AMPL_WIDTH),
conv_std_logic_vector(31412,AMPL_WIDTH),
conv_std_logic_vector(31413,AMPL_WIDTH),
conv_std_logic_vector(31414,AMPL_WIDTH),
conv_std_logic_vector(31415,AMPL_WIDTH),
conv_std_logic_vector(31416,AMPL_WIDTH),
conv_std_logic_vector(31417,AMPL_WIDTH),
conv_std_logic_vector(31417,AMPL_WIDTH),
conv_std_logic_vector(31418,AMPL_WIDTH),
conv_std_logic_vector(31419,AMPL_WIDTH),
conv_std_logic_vector(31420,AMPL_WIDTH),
conv_std_logic_vector(31421,AMPL_WIDTH),
conv_std_logic_vector(31422,AMPL_WIDTH),
conv_std_logic_vector(31423,AMPL_WIDTH),
conv_std_logic_vector(31424,AMPL_WIDTH),
conv_std_logic_vector(31425,AMPL_WIDTH),
conv_std_logic_vector(31425,AMPL_WIDTH),
conv_std_logic_vector(31426,AMPL_WIDTH),
conv_std_logic_vector(31427,AMPL_WIDTH),
conv_std_logic_vector(31428,AMPL_WIDTH),
conv_std_logic_vector(31429,AMPL_WIDTH),
conv_std_logic_vector(31430,AMPL_WIDTH),
conv_std_logic_vector(31431,AMPL_WIDTH),
conv_std_logic_vector(31432,AMPL_WIDTH),
conv_std_logic_vector(31433,AMPL_WIDTH),
conv_std_logic_vector(31433,AMPL_WIDTH),
conv_std_logic_vector(31434,AMPL_WIDTH),
conv_std_logic_vector(31435,AMPL_WIDTH),
conv_std_logic_vector(31436,AMPL_WIDTH),
conv_std_logic_vector(31437,AMPL_WIDTH),
conv_std_logic_vector(31438,AMPL_WIDTH),
conv_std_logic_vector(31439,AMPL_WIDTH),
conv_std_logic_vector(31440,AMPL_WIDTH),
conv_std_logic_vector(31441,AMPL_WIDTH),
conv_std_logic_vector(31441,AMPL_WIDTH),
conv_std_logic_vector(31442,AMPL_WIDTH),
conv_std_logic_vector(31443,AMPL_WIDTH),
conv_std_logic_vector(31444,AMPL_WIDTH),
conv_std_logic_vector(31445,AMPL_WIDTH),
conv_std_logic_vector(31446,AMPL_WIDTH),
conv_std_logic_vector(31447,AMPL_WIDTH),
conv_std_logic_vector(31448,AMPL_WIDTH),
conv_std_logic_vector(31448,AMPL_WIDTH),
conv_std_logic_vector(31449,AMPL_WIDTH),
conv_std_logic_vector(31450,AMPL_WIDTH),
conv_std_logic_vector(31451,AMPL_WIDTH),
conv_std_logic_vector(31452,AMPL_WIDTH),
conv_std_logic_vector(31453,AMPL_WIDTH),
conv_std_logic_vector(31454,AMPL_WIDTH),
conv_std_logic_vector(31455,AMPL_WIDTH),
conv_std_logic_vector(31456,AMPL_WIDTH),
conv_std_logic_vector(31456,AMPL_WIDTH),
conv_std_logic_vector(31457,AMPL_WIDTH),
conv_std_logic_vector(31458,AMPL_WIDTH),
conv_std_logic_vector(31459,AMPL_WIDTH),
conv_std_logic_vector(31460,AMPL_WIDTH),
conv_std_logic_vector(31461,AMPL_WIDTH),
conv_std_logic_vector(31462,AMPL_WIDTH),
conv_std_logic_vector(31463,AMPL_WIDTH),
conv_std_logic_vector(31463,AMPL_WIDTH),
conv_std_logic_vector(31464,AMPL_WIDTH),
conv_std_logic_vector(31465,AMPL_WIDTH),
conv_std_logic_vector(31466,AMPL_WIDTH),
conv_std_logic_vector(31467,AMPL_WIDTH),
conv_std_logic_vector(31468,AMPL_WIDTH),
conv_std_logic_vector(31469,AMPL_WIDTH),
conv_std_logic_vector(31470,AMPL_WIDTH),
conv_std_logic_vector(31470,AMPL_WIDTH),
conv_std_logic_vector(31471,AMPL_WIDTH),
conv_std_logic_vector(31472,AMPL_WIDTH),
conv_std_logic_vector(31473,AMPL_WIDTH),
conv_std_logic_vector(31474,AMPL_WIDTH),
conv_std_logic_vector(31475,AMPL_WIDTH),
conv_std_logic_vector(31476,AMPL_WIDTH),
conv_std_logic_vector(31477,AMPL_WIDTH),
conv_std_logic_vector(31477,AMPL_WIDTH),
conv_std_logic_vector(31478,AMPL_WIDTH),
conv_std_logic_vector(31479,AMPL_WIDTH),
conv_std_logic_vector(31480,AMPL_WIDTH),
conv_std_logic_vector(31481,AMPL_WIDTH),
conv_std_logic_vector(31482,AMPL_WIDTH),
conv_std_logic_vector(31483,AMPL_WIDTH),
conv_std_logic_vector(31484,AMPL_WIDTH),
conv_std_logic_vector(31484,AMPL_WIDTH),
conv_std_logic_vector(31485,AMPL_WIDTH),
conv_std_logic_vector(31486,AMPL_WIDTH),
conv_std_logic_vector(31487,AMPL_WIDTH),
conv_std_logic_vector(31488,AMPL_WIDTH),
conv_std_logic_vector(31489,AMPL_WIDTH),
conv_std_logic_vector(31490,AMPL_WIDTH),
conv_std_logic_vector(31490,AMPL_WIDTH),
conv_std_logic_vector(31491,AMPL_WIDTH),
conv_std_logic_vector(31492,AMPL_WIDTH),
conv_std_logic_vector(31493,AMPL_WIDTH),
conv_std_logic_vector(31494,AMPL_WIDTH),
conv_std_logic_vector(31495,AMPL_WIDTH),
conv_std_logic_vector(31496,AMPL_WIDTH),
conv_std_logic_vector(31497,AMPL_WIDTH),
conv_std_logic_vector(31497,AMPL_WIDTH),
conv_std_logic_vector(31498,AMPL_WIDTH),
conv_std_logic_vector(31499,AMPL_WIDTH),
conv_std_logic_vector(31500,AMPL_WIDTH),
conv_std_logic_vector(31501,AMPL_WIDTH),
conv_std_logic_vector(31502,AMPL_WIDTH),
conv_std_logic_vector(31503,AMPL_WIDTH),
conv_std_logic_vector(31503,AMPL_WIDTH),
conv_std_logic_vector(31504,AMPL_WIDTH),
conv_std_logic_vector(31505,AMPL_WIDTH),
conv_std_logic_vector(31506,AMPL_WIDTH),
conv_std_logic_vector(31507,AMPL_WIDTH),
conv_std_logic_vector(31508,AMPL_WIDTH),
conv_std_logic_vector(31509,AMPL_WIDTH),
conv_std_logic_vector(31510,AMPL_WIDTH),
conv_std_logic_vector(31510,AMPL_WIDTH),
conv_std_logic_vector(31511,AMPL_WIDTH),
conv_std_logic_vector(31512,AMPL_WIDTH),
conv_std_logic_vector(31513,AMPL_WIDTH),
conv_std_logic_vector(31514,AMPL_WIDTH),
conv_std_logic_vector(31515,AMPL_WIDTH),
conv_std_logic_vector(31516,AMPL_WIDTH),
conv_std_logic_vector(31516,AMPL_WIDTH),
conv_std_logic_vector(31517,AMPL_WIDTH),
conv_std_logic_vector(31518,AMPL_WIDTH),
conv_std_logic_vector(31519,AMPL_WIDTH),
conv_std_logic_vector(31520,AMPL_WIDTH),
conv_std_logic_vector(31521,AMPL_WIDTH),
conv_std_logic_vector(31522,AMPL_WIDTH),
conv_std_logic_vector(31522,AMPL_WIDTH),
conv_std_logic_vector(31523,AMPL_WIDTH),
conv_std_logic_vector(31524,AMPL_WIDTH),
conv_std_logic_vector(31525,AMPL_WIDTH),
conv_std_logic_vector(31526,AMPL_WIDTH),
conv_std_logic_vector(31527,AMPL_WIDTH),
conv_std_logic_vector(31528,AMPL_WIDTH),
conv_std_logic_vector(31528,AMPL_WIDTH),
conv_std_logic_vector(31529,AMPL_WIDTH),
conv_std_logic_vector(31530,AMPL_WIDTH),
conv_std_logic_vector(31531,AMPL_WIDTH),
conv_std_logic_vector(31532,AMPL_WIDTH),
conv_std_logic_vector(31533,AMPL_WIDTH),
conv_std_logic_vector(31534,AMPL_WIDTH),
conv_std_logic_vector(31534,AMPL_WIDTH),
conv_std_logic_vector(31535,AMPL_WIDTH),
conv_std_logic_vector(31536,AMPL_WIDTH),
conv_std_logic_vector(31537,AMPL_WIDTH),
conv_std_logic_vector(31538,AMPL_WIDTH),
conv_std_logic_vector(31539,AMPL_WIDTH),
conv_std_logic_vector(31539,AMPL_WIDTH),
conv_std_logic_vector(31540,AMPL_WIDTH),
conv_std_logic_vector(31541,AMPL_WIDTH),
conv_std_logic_vector(31542,AMPL_WIDTH),
conv_std_logic_vector(31543,AMPL_WIDTH),
conv_std_logic_vector(31544,AMPL_WIDTH),
conv_std_logic_vector(31545,AMPL_WIDTH),
conv_std_logic_vector(31545,AMPL_WIDTH),
conv_std_logic_vector(31546,AMPL_WIDTH),
conv_std_logic_vector(31547,AMPL_WIDTH),
conv_std_logic_vector(31548,AMPL_WIDTH),
conv_std_logic_vector(31549,AMPL_WIDTH),
conv_std_logic_vector(31550,AMPL_WIDTH),
conv_std_logic_vector(31551,AMPL_WIDTH),
conv_std_logic_vector(31551,AMPL_WIDTH),
conv_std_logic_vector(31552,AMPL_WIDTH),
conv_std_logic_vector(31553,AMPL_WIDTH),
conv_std_logic_vector(31554,AMPL_WIDTH),
conv_std_logic_vector(31555,AMPL_WIDTH),
conv_std_logic_vector(31556,AMPL_WIDTH),
conv_std_logic_vector(31556,AMPL_WIDTH),
conv_std_logic_vector(31557,AMPL_WIDTH),
conv_std_logic_vector(31558,AMPL_WIDTH),
conv_std_logic_vector(31559,AMPL_WIDTH),
conv_std_logic_vector(31560,AMPL_WIDTH),
conv_std_logic_vector(31561,AMPL_WIDTH),
conv_std_logic_vector(31562,AMPL_WIDTH),
conv_std_logic_vector(31562,AMPL_WIDTH),
conv_std_logic_vector(31563,AMPL_WIDTH),
conv_std_logic_vector(31564,AMPL_WIDTH),
conv_std_logic_vector(31565,AMPL_WIDTH),
conv_std_logic_vector(31566,AMPL_WIDTH),
conv_std_logic_vector(31567,AMPL_WIDTH),
conv_std_logic_vector(31567,AMPL_WIDTH),
conv_std_logic_vector(31568,AMPL_WIDTH),
conv_std_logic_vector(31569,AMPL_WIDTH),
conv_std_logic_vector(31570,AMPL_WIDTH),
conv_std_logic_vector(31571,AMPL_WIDTH),
conv_std_logic_vector(31572,AMPL_WIDTH),
conv_std_logic_vector(31572,AMPL_WIDTH),
conv_std_logic_vector(31573,AMPL_WIDTH),
conv_std_logic_vector(31574,AMPL_WIDTH),
conv_std_logic_vector(31575,AMPL_WIDTH),
conv_std_logic_vector(31576,AMPL_WIDTH),
conv_std_logic_vector(31577,AMPL_WIDTH),
conv_std_logic_vector(31578,AMPL_WIDTH),
conv_std_logic_vector(31578,AMPL_WIDTH),
conv_std_logic_vector(31579,AMPL_WIDTH),
conv_std_logic_vector(31580,AMPL_WIDTH),
conv_std_logic_vector(31581,AMPL_WIDTH),
conv_std_logic_vector(31582,AMPL_WIDTH),
conv_std_logic_vector(31583,AMPL_WIDTH),
conv_std_logic_vector(31583,AMPL_WIDTH),
conv_std_logic_vector(31584,AMPL_WIDTH),
conv_std_logic_vector(31585,AMPL_WIDTH),
conv_std_logic_vector(31586,AMPL_WIDTH),
conv_std_logic_vector(31587,AMPL_WIDTH),
conv_std_logic_vector(31588,AMPL_WIDTH),
conv_std_logic_vector(31588,AMPL_WIDTH),
conv_std_logic_vector(31589,AMPL_WIDTH),
conv_std_logic_vector(31590,AMPL_WIDTH),
conv_std_logic_vector(31591,AMPL_WIDTH),
conv_std_logic_vector(31592,AMPL_WIDTH),
conv_std_logic_vector(31593,AMPL_WIDTH),
conv_std_logic_vector(31593,AMPL_WIDTH),
conv_std_logic_vector(31594,AMPL_WIDTH),
conv_std_logic_vector(31595,AMPL_WIDTH),
conv_std_logic_vector(31596,AMPL_WIDTH),
conv_std_logic_vector(31597,AMPL_WIDTH),
conv_std_logic_vector(31598,AMPL_WIDTH),
conv_std_logic_vector(31598,AMPL_WIDTH),
conv_std_logic_vector(31599,AMPL_WIDTH),
conv_std_logic_vector(31600,AMPL_WIDTH),
conv_std_logic_vector(31601,AMPL_WIDTH),
conv_std_logic_vector(31602,AMPL_WIDTH),
conv_std_logic_vector(31603,AMPL_WIDTH),
conv_std_logic_vector(31603,AMPL_WIDTH),
conv_std_logic_vector(31604,AMPL_WIDTH),
conv_std_logic_vector(31605,AMPL_WIDTH),
conv_std_logic_vector(31606,AMPL_WIDTH),
conv_std_logic_vector(31607,AMPL_WIDTH),
conv_std_logic_vector(31608,AMPL_WIDTH),
conv_std_logic_vector(31608,AMPL_WIDTH),
conv_std_logic_vector(31609,AMPL_WIDTH),
conv_std_logic_vector(31610,AMPL_WIDTH),
conv_std_logic_vector(31611,AMPL_WIDTH),
conv_std_logic_vector(31612,AMPL_WIDTH),
conv_std_logic_vector(31613,AMPL_WIDTH),
conv_std_logic_vector(31613,AMPL_WIDTH),
conv_std_logic_vector(31614,AMPL_WIDTH),
conv_std_logic_vector(31615,AMPL_WIDTH),
conv_std_logic_vector(31616,AMPL_WIDTH),
conv_std_logic_vector(31617,AMPL_WIDTH),
conv_std_logic_vector(31617,AMPL_WIDTH),
conv_std_logic_vector(31618,AMPL_WIDTH),
conv_std_logic_vector(31619,AMPL_WIDTH),
conv_std_logic_vector(31620,AMPL_WIDTH),
conv_std_logic_vector(31621,AMPL_WIDTH),
conv_std_logic_vector(31622,AMPL_WIDTH),
conv_std_logic_vector(31622,AMPL_WIDTH),
conv_std_logic_vector(31623,AMPL_WIDTH),
conv_std_logic_vector(31624,AMPL_WIDTH),
conv_std_logic_vector(31625,AMPL_WIDTH),
conv_std_logic_vector(31626,AMPL_WIDTH),
conv_std_logic_vector(31627,AMPL_WIDTH),
conv_std_logic_vector(31627,AMPL_WIDTH),
conv_std_logic_vector(31628,AMPL_WIDTH),
conv_std_logic_vector(31629,AMPL_WIDTH),
conv_std_logic_vector(31630,AMPL_WIDTH),
conv_std_logic_vector(31631,AMPL_WIDTH),
conv_std_logic_vector(31631,AMPL_WIDTH),
conv_std_logic_vector(31632,AMPL_WIDTH),
conv_std_logic_vector(31633,AMPL_WIDTH),
conv_std_logic_vector(31634,AMPL_WIDTH),
conv_std_logic_vector(31635,AMPL_WIDTH),
conv_std_logic_vector(31636,AMPL_WIDTH),
conv_std_logic_vector(31636,AMPL_WIDTH),
conv_std_logic_vector(31637,AMPL_WIDTH),
conv_std_logic_vector(31638,AMPL_WIDTH),
conv_std_logic_vector(31639,AMPL_WIDTH),
conv_std_logic_vector(31640,AMPL_WIDTH),
conv_std_logic_vector(31640,AMPL_WIDTH),
conv_std_logic_vector(31641,AMPL_WIDTH),
conv_std_logic_vector(31642,AMPL_WIDTH),
conv_std_logic_vector(31643,AMPL_WIDTH),
conv_std_logic_vector(31644,AMPL_WIDTH),
conv_std_logic_vector(31645,AMPL_WIDTH),
conv_std_logic_vector(31645,AMPL_WIDTH),
conv_std_logic_vector(31646,AMPL_WIDTH),
conv_std_logic_vector(31647,AMPL_WIDTH),
conv_std_logic_vector(31648,AMPL_WIDTH),
conv_std_logic_vector(31649,AMPL_WIDTH),
conv_std_logic_vector(31649,AMPL_WIDTH),
conv_std_logic_vector(31650,AMPL_WIDTH),
conv_std_logic_vector(31651,AMPL_WIDTH),
conv_std_logic_vector(31652,AMPL_WIDTH),
conv_std_logic_vector(31653,AMPL_WIDTH),
conv_std_logic_vector(31653,AMPL_WIDTH),
conv_std_logic_vector(31654,AMPL_WIDTH),
conv_std_logic_vector(31655,AMPL_WIDTH),
conv_std_logic_vector(31656,AMPL_WIDTH),
conv_std_logic_vector(31657,AMPL_WIDTH),
conv_std_logic_vector(31658,AMPL_WIDTH),
conv_std_logic_vector(31658,AMPL_WIDTH),
conv_std_logic_vector(31659,AMPL_WIDTH),
conv_std_logic_vector(31660,AMPL_WIDTH),
conv_std_logic_vector(31661,AMPL_WIDTH),
conv_std_logic_vector(31662,AMPL_WIDTH),
conv_std_logic_vector(31662,AMPL_WIDTH),
conv_std_logic_vector(31663,AMPL_WIDTH),
conv_std_logic_vector(31664,AMPL_WIDTH),
conv_std_logic_vector(31665,AMPL_WIDTH),
conv_std_logic_vector(31666,AMPL_WIDTH),
conv_std_logic_vector(31666,AMPL_WIDTH),
conv_std_logic_vector(31667,AMPL_WIDTH),
conv_std_logic_vector(31668,AMPL_WIDTH),
conv_std_logic_vector(31669,AMPL_WIDTH),
conv_std_logic_vector(31670,AMPL_WIDTH),
conv_std_logic_vector(31670,AMPL_WIDTH),
conv_std_logic_vector(31671,AMPL_WIDTH),
conv_std_logic_vector(31672,AMPL_WIDTH),
conv_std_logic_vector(31673,AMPL_WIDTH),
conv_std_logic_vector(31674,AMPL_WIDTH),
conv_std_logic_vector(31674,AMPL_WIDTH),
conv_std_logic_vector(31675,AMPL_WIDTH),
conv_std_logic_vector(31676,AMPL_WIDTH),
conv_std_logic_vector(31677,AMPL_WIDTH),
conv_std_logic_vector(31678,AMPL_WIDTH),
conv_std_logic_vector(31679,AMPL_WIDTH),
conv_std_logic_vector(31679,AMPL_WIDTH),
conv_std_logic_vector(31680,AMPL_WIDTH),
conv_std_logic_vector(31681,AMPL_WIDTH),
conv_std_logic_vector(31682,AMPL_WIDTH),
conv_std_logic_vector(31683,AMPL_WIDTH),
conv_std_logic_vector(31683,AMPL_WIDTH),
conv_std_logic_vector(31684,AMPL_WIDTH),
conv_std_logic_vector(31685,AMPL_WIDTH),
conv_std_logic_vector(31686,AMPL_WIDTH),
conv_std_logic_vector(31687,AMPL_WIDTH),
conv_std_logic_vector(31687,AMPL_WIDTH),
conv_std_logic_vector(31688,AMPL_WIDTH),
conv_std_logic_vector(31689,AMPL_WIDTH),
conv_std_logic_vector(31690,AMPL_WIDTH),
conv_std_logic_vector(31691,AMPL_WIDTH),
conv_std_logic_vector(31691,AMPL_WIDTH),
conv_std_logic_vector(31692,AMPL_WIDTH),
conv_std_logic_vector(31693,AMPL_WIDTH),
conv_std_logic_vector(31694,AMPL_WIDTH),
conv_std_logic_vector(31695,AMPL_WIDTH),
conv_std_logic_vector(31695,AMPL_WIDTH),
conv_std_logic_vector(31696,AMPL_WIDTH),
conv_std_logic_vector(31697,AMPL_WIDTH),
conv_std_logic_vector(31698,AMPL_WIDTH),
conv_std_logic_vector(31698,AMPL_WIDTH),
conv_std_logic_vector(31699,AMPL_WIDTH),
conv_std_logic_vector(31700,AMPL_WIDTH),
conv_std_logic_vector(31701,AMPL_WIDTH),
conv_std_logic_vector(31702,AMPL_WIDTH),
conv_std_logic_vector(31702,AMPL_WIDTH),
conv_std_logic_vector(31703,AMPL_WIDTH),
conv_std_logic_vector(31704,AMPL_WIDTH),
conv_std_logic_vector(31705,AMPL_WIDTH),
conv_std_logic_vector(31706,AMPL_WIDTH),
conv_std_logic_vector(31706,AMPL_WIDTH),
conv_std_logic_vector(31707,AMPL_WIDTH),
conv_std_logic_vector(31708,AMPL_WIDTH),
conv_std_logic_vector(31709,AMPL_WIDTH),
conv_std_logic_vector(31710,AMPL_WIDTH),
conv_std_logic_vector(31710,AMPL_WIDTH),
conv_std_logic_vector(31711,AMPL_WIDTH),
conv_std_logic_vector(31712,AMPL_WIDTH),
conv_std_logic_vector(31713,AMPL_WIDTH),
conv_std_logic_vector(31714,AMPL_WIDTH),
conv_std_logic_vector(31714,AMPL_WIDTH),
conv_std_logic_vector(31715,AMPL_WIDTH),
conv_std_logic_vector(31716,AMPL_WIDTH),
conv_std_logic_vector(31717,AMPL_WIDTH),
conv_std_logic_vector(31718,AMPL_WIDTH),
conv_std_logic_vector(31718,AMPL_WIDTH),
conv_std_logic_vector(31719,AMPL_WIDTH),
conv_std_logic_vector(31720,AMPL_WIDTH),
conv_std_logic_vector(31721,AMPL_WIDTH),
conv_std_logic_vector(31721,AMPL_WIDTH),
conv_std_logic_vector(31722,AMPL_WIDTH),
conv_std_logic_vector(31723,AMPL_WIDTH),
conv_std_logic_vector(31724,AMPL_WIDTH),
conv_std_logic_vector(31725,AMPL_WIDTH),
conv_std_logic_vector(31725,AMPL_WIDTH),
conv_std_logic_vector(31726,AMPL_WIDTH),
conv_std_logic_vector(31727,AMPL_WIDTH),
conv_std_logic_vector(31728,AMPL_WIDTH),
conv_std_logic_vector(31729,AMPL_WIDTH),
conv_std_logic_vector(31729,AMPL_WIDTH),
conv_std_logic_vector(31730,AMPL_WIDTH),
conv_std_logic_vector(31731,AMPL_WIDTH),
conv_std_logic_vector(31732,AMPL_WIDTH),
conv_std_logic_vector(31732,AMPL_WIDTH),
conv_std_logic_vector(31733,AMPL_WIDTH),
conv_std_logic_vector(31734,AMPL_WIDTH),
conv_std_logic_vector(31735,AMPL_WIDTH),
conv_std_logic_vector(31736,AMPL_WIDTH),
conv_std_logic_vector(31736,AMPL_WIDTH),
conv_std_logic_vector(31737,AMPL_WIDTH),
conv_std_logic_vector(31738,AMPL_WIDTH),
conv_std_logic_vector(31739,AMPL_WIDTH),
conv_std_logic_vector(31739,AMPL_WIDTH),
conv_std_logic_vector(31740,AMPL_WIDTH),
conv_std_logic_vector(31741,AMPL_WIDTH),
conv_std_logic_vector(31742,AMPL_WIDTH),
conv_std_logic_vector(31743,AMPL_WIDTH),
conv_std_logic_vector(31743,AMPL_WIDTH),
conv_std_logic_vector(31744,AMPL_WIDTH),
conv_std_logic_vector(31745,AMPL_WIDTH),
conv_std_logic_vector(31746,AMPL_WIDTH),
conv_std_logic_vector(31746,AMPL_WIDTH),
conv_std_logic_vector(31747,AMPL_WIDTH),
conv_std_logic_vector(31748,AMPL_WIDTH),
conv_std_logic_vector(31749,AMPL_WIDTH),
conv_std_logic_vector(31750,AMPL_WIDTH),
conv_std_logic_vector(31750,AMPL_WIDTH),
conv_std_logic_vector(31751,AMPL_WIDTH),
conv_std_logic_vector(31752,AMPL_WIDTH),
conv_std_logic_vector(31753,AMPL_WIDTH),
conv_std_logic_vector(31753,AMPL_WIDTH),
conv_std_logic_vector(31754,AMPL_WIDTH),
conv_std_logic_vector(31755,AMPL_WIDTH),
conv_std_logic_vector(31756,AMPL_WIDTH),
conv_std_logic_vector(31757,AMPL_WIDTH),
conv_std_logic_vector(31757,AMPL_WIDTH),
conv_std_logic_vector(31758,AMPL_WIDTH),
conv_std_logic_vector(31759,AMPL_WIDTH),
conv_std_logic_vector(31760,AMPL_WIDTH),
conv_std_logic_vector(31760,AMPL_WIDTH),
conv_std_logic_vector(31761,AMPL_WIDTH),
conv_std_logic_vector(31762,AMPL_WIDTH),
conv_std_logic_vector(31763,AMPL_WIDTH),
conv_std_logic_vector(31764,AMPL_WIDTH),
conv_std_logic_vector(31764,AMPL_WIDTH),
conv_std_logic_vector(31765,AMPL_WIDTH),
conv_std_logic_vector(31766,AMPL_WIDTH),
conv_std_logic_vector(31767,AMPL_WIDTH),
conv_std_logic_vector(31767,AMPL_WIDTH),
conv_std_logic_vector(31768,AMPL_WIDTH),
conv_std_logic_vector(31769,AMPL_WIDTH),
conv_std_logic_vector(31770,AMPL_WIDTH),
conv_std_logic_vector(31770,AMPL_WIDTH),
conv_std_logic_vector(31771,AMPL_WIDTH),
conv_std_logic_vector(31772,AMPL_WIDTH),
conv_std_logic_vector(31773,AMPL_WIDTH),
conv_std_logic_vector(31774,AMPL_WIDTH),
conv_std_logic_vector(31774,AMPL_WIDTH),
conv_std_logic_vector(31775,AMPL_WIDTH),
conv_std_logic_vector(31776,AMPL_WIDTH),
conv_std_logic_vector(31777,AMPL_WIDTH),
conv_std_logic_vector(31777,AMPL_WIDTH),
conv_std_logic_vector(31778,AMPL_WIDTH),
conv_std_logic_vector(31779,AMPL_WIDTH),
conv_std_logic_vector(31780,AMPL_WIDTH),
conv_std_logic_vector(31780,AMPL_WIDTH),
conv_std_logic_vector(31781,AMPL_WIDTH),
conv_std_logic_vector(31782,AMPL_WIDTH),
conv_std_logic_vector(31783,AMPL_WIDTH),
conv_std_logic_vector(31783,AMPL_WIDTH),
conv_std_logic_vector(31784,AMPL_WIDTH),
conv_std_logic_vector(31785,AMPL_WIDTH),
conv_std_logic_vector(31786,AMPL_WIDTH),
conv_std_logic_vector(31787,AMPL_WIDTH),
conv_std_logic_vector(31787,AMPL_WIDTH),
conv_std_logic_vector(31788,AMPL_WIDTH),
conv_std_logic_vector(31789,AMPL_WIDTH),
conv_std_logic_vector(31790,AMPL_WIDTH),
conv_std_logic_vector(31790,AMPL_WIDTH),
conv_std_logic_vector(31791,AMPL_WIDTH),
conv_std_logic_vector(31792,AMPL_WIDTH),
conv_std_logic_vector(31793,AMPL_WIDTH),
conv_std_logic_vector(31793,AMPL_WIDTH),
conv_std_logic_vector(31794,AMPL_WIDTH),
conv_std_logic_vector(31795,AMPL_WIDTH),
conv_std_logic_vector(31796,AMPL_WIDTH),
conv_std_logic_vector(31796,AMPL_WIDTH),
conv_std_logic_vector(31797,AMPL_WIDTH),
conv_std_logic_vector(31798,AMPL_WIDTH),
conv_std_logic_vector(31799,AMPL_WIDTH),
conv_std_logic_vector(31799,AMPL_WIDTH),
conv_std_logic_vector(31800,AMPL_WIDTH),
conv_std_logic_vector(31801,AMPL_WIDTH),
conv_std_logic_vector(31802,AMPL_WIDTH),
conv_std_logic_vector(31802,AMPL_WIDTH),
conv_std_logic_vector(31803,AMPL_WIDTH),
conv_std_logic_vector(31804,AMPL_WIDTH),
conv_std_logic_vector(31805,AMPL_WIDTH),
conv_std_logic_vector(31806,AMPL_WIDTH),
conv_std_logic_vector(31806,AMPL_WIDTH),
conv_std_logic_vector(31807,AMPL_WIDTH),
conv_std_logic_vector(31808,AMPL_WIDTH),
conv_std_logic_vector(31809,AMPL_WIDTH),
conv_std_logic_vector(31809,AMPL_WIDTH),
conv_std_logic_vector(31810,AMPL_WIDTH),
conv_std_logic_vector(31811,AMPL_WIDTH),
conv_std_logic_vector(31812,AMPL_WIDTH),
conv_std_logic_vector(31812,AMPL_WIDTH),
conv_std_logic_vector(31813,AMPL_WIDTH),
conv_std_logic_vector(31814,AMPL_WIDTH),
conv_std_logic_vector(31815,AMPL_WIDTH),
conv_std_logic_vector(31815,AMPL_WIDTH),
conv_std_logic_vector(31816,AMPL_WIDTH),
conv_std_logic_vector(31817,AMPL_WIDTH),
conv_std_logic_vector(31818,AMPL_WIDTH),
conv_std_logic_vector(31818,AMPL_WIDTH),
conv_std_logic_vector(31819,AMPL_WIDTH),
conv_std_logic_vector(31820,AMPL_WIDTH),
conv_std_logic_vector(31821,AMPL_WIDTH),
conv_std_logic_vector(31821,AMPL_WIDTH),
conv_std_logic_vector(31822,AMPL_WIDTH),
conv_std_logic_vector(31823,AMPL_WIDTH),
conv_std_logic_vector(31824,AMPL_WIDTH),
conv_std_logic_vector(31824,AMPL_WIDTH),
conv_std_logic_vector(31825,AMPL_WIDTH),
conv_std_logic_vector(31826,AMPL_WIDTH),
conv_std_logic_vector(31827,AMPL_WIDTH),
conv_std_logic_vector(31827,AMPL_WIDTH),
conv_std_logic_vector(31828,AMPL_WIDTH),
conv_std_logic_vector(31829,AMPL_WIDTH),
conv_std_logic_vector(31830,AMPL_WIDTH),
conv_std_logic_vector(31830,AMPL_WIDTH),
conv_std_logic_vector(31831,AMPL_WIDTH),
conv_std_logic_vector(31832,AMPL_WIDTH),
conv_std_logic_vector(31833,AMPL_WIDTH),
conv_std_logic_vector(31833,AMPL_WIDTH),
conv_std_logic_vector(31834,AMPL_WIDTH),
conv_std_logic_vector(31835,AMPL_WIDTH),
conv_std_logic_vector(31836,AMPL_WIDTH),
conv_std_logic_vector(31836,AMPL_WIDTH),
conv_std_logic_vector(31837,AMPL_WIDTH),
conv_std_logic_vector(31838,AMPL_WIDTH),
conv_std_logic_vector(31838,AMPL_WIDTH),
conv_std_logic_vector(31839,AMPL_WIDTH),
conv_std_logic_vector(31840,AMPL_WIDTH),
conv_std_logic_vector(31841,AMPL_WIDTH),
conv_std_logic_vector(31841,AMPL_WIDTH),
conv_std_logic_vector(31842,AMPL_WIDTH),
conv_std_logic_vector(31843,AMPL_WIDTH),
conv_std_logic_vector(31844,AMPL_WIDTH),
conv_std_logic_vector(31844,AMPL_WIDTH),
conv_std_logic_vector(31845,AMPL_WIDTH),
conv_std_logic_vector(31846,AMPL_WIDTH),
conv_std_logic_vector(31847,AMPL_WIDTH),
conv_std_logic_vector(31847,AMPL_WIDTH),
conv_std_logic_vector(31848,AMPL_WIDTH),
conv_std_logic_vector(31849,AMPL_WIDTH),
conv_std_logic_vector(31850,AMPL_WIDTH),
conv_std_logic_vector(31850,AMPL_WIDTH),
conv_std_logic_vector(31851,AMPL_WIDTH),
conv_std_logic_vector(31852,AMPL_WIDTH),
conv_std_logic_vector(31853,AMPL_WIDTH),
conv_std_logic_vector(31853,AMPL_WIDTH),
conv_std_logic_vector(31854,AMPL_WIDTH),
conv_std_logic_vector(31855,AMPL_WIDTH),
conv_std_logic_vector(31855,AMPL_WIDTH),
conv_std_logic_vector(31856,AMPL_WIDTH),
conv_std_logic_vector(31857,AMPL_WIDTH),
conv_std_logic_vector(31858,AMPL_WIDTH),
conv_std_logic_vector(31858,AMPL_WIDTH),
conv_std_logic_vector(31859,AMPL_WIDTH),
conv_std_logic_vector(31860,AMPL_WIDTH),
conv_std_logic_vector(31861,AMPL_WIDTH),
conv_std_logic_vector(31861,AMPL_WIDTH),
conv_std_logic_vector(31862,AMPL_WIDTH),
conv_std_logic_vector(31863,AMPL_WIDTH),
conv_std_logic_vector(31864,AMPL_WIDTH),
conv_std_logic_vector(31864,AMPL_WIDTH),
conv_std_logic_vector(31865,AMPL_WIDTH),
conv_std_logic_vector(31866,AMPL_WIDTH),
conv_std_logic_vector(31866,AMPL_WIDTH),
conv_std_logic_vector(31867,AMPL_WIDTH),
conv_std_logic_vector(31868,AMPL_WIDTH),
conv_std_logic_vector(31869,AMPL_WIDTH),
conv_std_logic_vector(31869,AMPL_WIDTH),
conv_std_logic_vector(31870,AMPL_WIDTH),
conv_std_logic_vector(31871,AMPL_WIDTH),
conv_std_logic_vector(31872,AMPL_WIDTH),
conv_std_logic_vector(31872,AMPL_WIDTH),
conv_std_logic_vector(31873,AMPL_WIDTH),
conv_std_logic_vector(31874,AMPL_WIDTH),
conv_std_logic_vector(31875,AMPL_WIDTH),
conv_std_logic_vector(31875,AMPL_WIDTH),
conv_std_logic_vector(31876,AMPL_WIDTH),
conv_std_logic_vector(31877,AMPL_WIDTH),
conv_std_logic_vector(31877,AMPL_WIDTH),
conv_std_logic_vector(31878,AMPL_WIDTH),
conv_std_logic_vector(31879,AMPL_WIDTH),
conv_std_logic_vector(31880,AMPL_WIDTH),
conv_std_logic_vector(31880,AMPL_WIDTH),
conv_std_logic_vector(31881,AMPL_WIDTH),
conv_std_logic_vector(31882,AMPL_WIDTH),
conv_std_logic_vector(31882,AMPL_WIDTH),
conv_std_logic_vector(31883,AMPL_WIDTH),
conv_std_logic_vector(31884,AMPL_WIDTH),
conv_std_logic_vector(31885,AMPL_WIDTH),
conv_std_logic_vector(31885,AMPL_WIDTH),
conv_std_logic_vector(31886,AMPL_WIDTH),
conv_std_logic_vector(31887,AMPL_WIDTH),
conv_std_logic_vector(31888,AMPL_WIDTH),
conv_std_logic_vector(31888,AMPL_WIDTH),
conv_std_logic_vector(31889,AMPL_WIDTH),
conv_std_logic_vector(31890,AMPL_WIDTH),
conv_std_logic_vector(31890,AMPL_WIDTH),
conv_std_logic_vector(31891,AMPL_WIDTH),
conv_std_logic_vector(31892,AMPL_WIDTH),
conv_std_logic_vector(31893,AMPL_WIDTH),
conv_std_logic_vector(31893,AMPL_WIDTH),
conv_std_logic_vector(31894,AMPL_WIDTH),
conv_std_logic_vector(31895,AMPL_WIDTH),
conv_std_logic_vector(31896,AMPL_WIDTH),
conv_std_logic_vector(31896,AMPL_WIDTH),
conv_std_logic_vector(31897,AMPL_WIDTH),
conv_std_logic_vector(31898,AMPL_WIDTH),
conv_std_logic_vector(31898,AMPL_WIDTH),
conv_std_logic_vector(31899,AMPL_WIDTH),
conv_std_logic_vector(31900,AMPL_WIDTH),
conv_std_logic_vector(31901,AMPL_WIDTH),
conv_std_logic_vector(31901,AMPL_WIDTH),
conv_std_logic_vector(31902,AMPL_WIDTH),
conv_std_logic_vector(31903,AMPL_WIDTH),
conv_std_logic_vector(31903,AMPL_WIDTH),
conv_std_logic_vector(31904,AMPL_WIDTH),
conv_std_logic_vector(31905,AMPL_WIDTH),
conv_std_logic_vector(31906,AMPL_WIDTH),
conv_std_logic_vector(31906,AMPL_WIDTH),
conv_std_logic_vector(31907,AMPL_WIDTH),
conv_std_logic_vector(31908,AMPL_WIDTH),
conv_std_logic_vector(31908,AMPL_WIDTH),
conv_std_logic_vector(31909,AMPL_WIDTH),
conv_std_logic_vector(31910,AMPL_WIDTH),
conv_std_logic_vector(31911,AMPL_WIDTH),
conv_std_logic_vector(31911,AMPL_WIDTH),
conv_std_logic_vector(31912,AMPL_WIDTH),
conv_std_logic_vector(31913,AMPL_WIDTH),
conv_std_logic_vector(31913,AMPL_WIDTH),
conv_std_logic_vector(31914,AMPL_WIDTH),
conv_std_logic_vector(31915,AMPL_WIDTH),
conv_std_logic_vector(31916,AMPL_WIDTH),
conv_std_logic_vector(31916,AMPL_WIDTH),
conv_std_logic_vector(31917,AMPL_WIDTH),
conv_std_logic_vector(31918,AMPL_WIDTH),
conv_std_logic_vector(31918,AMPL_WIDTH),
conv_std_logic_vector(31919,AMPL_WIDTH),
conv_std_logic_vector(31920,AMPL_WIDTH),
conv_std_logic_vector(31921,AMPL_WIDTH),
conv_std_logic_vector(31921,AMPL_WIDTH),
conv_std_logic_vector(31922,AMPL_WIDTH),
conv_std_logic_vector(31923,AMPL_WIDTH),
conv_std_logic_vector(31923,AMPL_WIDTH),
conv_std_logic_vector(31924,AMPL_WIDTH),
conv_std_logic_vector(31925,AMPL_WIDTH),
conv_std_logic_vector(31925,AMPL_WIDTH),
conv_std_logic_vector(31926,AMPL_WIDTH),
conv_std_logic_vector(31927,AMPL_WIDTH),
conv_std_logic_vector(31928,AMPL_WIDTH),
conv_std_logic_vector(31928,AMPL_WIDTH),
conv_std_logic_vector(31929,AMPL_WIDTH),
conv_std_logic_vector(31930,AMPL_WIDTH),
conv_std_logic_vector(31930,AMPL_WIDTH),
conv_std_logic_vector(31931,AMPL_WIDTH),
conv_std_logic_vector(31932,AMPL_WIDTH),
conv_std_logic_vector(31933,AMPL_WIDTH),
conv_std_logic_vector(31933,AMPL_WIDTH),
conv_std_logic_vector(31934,AMPL_WIDTH),
conv_std_logic_vector(31935,AMPL_WIDTH),
conv_std_logic_vector(31935,AMPL_WIDTH),
conv_std_logic_vector(31936,AMPL_WIDTH),
conv_std_logic_vector(31937,AMPL_WIDTH),
conv_std_logic_vector(31937,AMPL_WIDTH),
conv_std_logic_vector(31938,AMPL_WIDTH),
conv_std_logic_vector(31939,AMPL_WIDTH),
conv_std_logic_vector(31940,AMPL_WIDTH),
conv_std_logic_vector(31940,AMPL_WIDTH),
conv_std_logic_vector(31941,AMPL_WIDTH),
conv_std_logic_vector(31942,AMPL_WIDTH),
conv_std_logic_vector(31942,AMPL_WIDTH),
conv_std_logic_vector(31943,AMPL_WIDTH),
conv_std_logic_vector(31944,AMPL_WIDTH),
conv_std_logic_vector(31944,AMPL_WIDTH),
conv_std_logic_vector(31945,AMPL_WIDTH),
conv_std_logic_vector(31946,AMPL_WIDTH),
conv_std_logic_vector(31947,AMPL_WIDTH),
conv_std_logic_vector(31947,AMPL_WIDTH),
conv_std_logic_vector(31948,AMPL_WIDTH),
conv_std_logic_vector(31949,AMPL_WIDTH),
conv_std_logic_vector(31949,AMPL_WIDTH),
conv_std_logic_vector(31950,AMPL_WIDTH),
conv_std_logic_vector(31951,AMPL_WIDTH),
conv_std_logic_vector(31951,AMPL_WIDTH),
conv_std_logic_vector(31952,AMPL_WIDTH),
conv_std_logic_vector(31953,AMPL_WIDTH),
conv_std_logic_vector(31954,AMPL_WIDTH),
conv_std_logic_vector(31954,AMPL_WIDTH),
conv_std_logic_vector(31955,AMPL_WIDTH),
conv_std_logic_vector(31956,AMPL_WIDTH),
conv_std_logic_vector(31956,AMPL_WIDTH),
conv_std_logic_vector(31957,AMPL_WIDTH),
conv_std_logic_vector(31958,AMPL_WIDTH),
conv_std_logic_vector(31958,AMPL_WIDTH),
conv_std_logic_vector(31959,AMPL_WIDTH),
conv_std_logic_vector(31960,AMPL_WIDTH),
conv_std_logic_vector(31960,AMPL_WIDTH),
conv_std_logic_vector(31961,AMPL_WIDTH),
conv_std_logic_vector(31962,AMPL_WIDTH),
conv_std_logic_vector(31963,AMPL_WIDTH),
conv_std_logic_vector(31963,AMPL_WIDTH),
conv_std_logic_vector(31964,AMPL_WIDTH),
conv_std_logic_vector(31965,AMPL_WIDTH),
conv_std_logic_vector(31965,AMPL_WIDTH),
conv_std_logic_vector(31966,AMPL_WIDTH),
conv_std_logic_vector(31967,AMPL_WIDTH),
conv_std_logic_vector(31967,AMPL_WIDTH),
conv_std_logic_vector(31968,AMPL_WIDTH),
conv_std_logic_vector(31969,AMPL_WIDTH),
conv_std_logic_vector(31969,AMPL_WIDTH),
conv_std_logic_vector(31970,AMPL_WIDTH),
conv_std_logic_vector(31971,AMPL_WIDTH),
conv_std_logic_vector(31972,AMPL_WIDTH),
conv_std_logic_vector(31972,AMPL_WIDTH),
conv_std_logic_vector(31973,AMPL_WIDTH),
conv_std_logic_vector(31974,AMPL_WIDTH),
conv_std_logic_vector(31974,AMPL_WIDTH),
conv_std_logic_vector(31975,AMPL_WIDTH),
conv_std_logic_vector(31976,AMPL_WIDTH),
conv_std_logic_vector(31976,AMPL_WIDTH),
conv_std_logic_vector(31977,AMPL_WIDTH),
conv_std_logic_vector(31978,AMPL_WIDTH),
conv_std_logic_vector(31978,AMPL_WIDTH),
conv_std_logic_vector(31979,AMPL_WIDTH),
conv_std_logic_vector(31980,AMPL_WIDTH),
conv_std_logic_vector(31980,AMPL_WIDTH),
conv_std_logic_vector(31981,AMPL_WIDTH),
conv_std_logic_vector(31982,AMPL_WIDTH),
conv_std_logic_vector(31982,AMPL_WIDTH),
conv_std_logic_vector(31983,AMPL_WIDTH),
conv_std_logic_vector(31984,AMPL_WIDTH),
conv_std_logic_vector(31985,AMPL_WIDTH),
conv_std_logic_vector(31985,AMPL_WIDTH),
conv_std_logic_vector(31986,AMPL_WIDTH),
conv_std_logic_vector(31987,AMPL_WIDTH),
conv_std_logic_vector(31987,AMPL_WIDTH),
conv_std_logic_vector(31988,AMPL_WIDTH),
conv_std_logic_vector(31989,AMPL_WIDTH),
conv_std_logic_vector(31989,AMPL_WIDTH),
conv_std_logic_vector(31990,AMPL_WIDTH),
conv_std_logic_vector(31991,AMPL_WIDTH),
conv_std_logic_vector(31991,AMPL_WIDTH),
conv_std_logic_vector(31992,AMPL_WIDTH),
conv_std_logic_vector(31993,AMPL_WIDTH),
conv_std_logic_vector(31993,AMPL_WIDTH),
conv_std_logic_vector(31994,AMPL_WIDTH),
conv_std_logic_vector(31995,AMPL_WIDTH),
conv_std_logic_vector(31995,AMPL_WIDTH),
conv_std_logic_vector(31996,AMPL_WIDTH),
conv_std_logic_vector(31997,AMPL_WIDTH),
conv_std_logic_vector(31997,AMPL_WIDTH),
conv_std_logic_vector(31998,AMPL_WIDTH),
conv_std_logic_vector(31999,AMPL_WIDTH),
conv_std_logic_vector(31999,AMPL_WIDTH),
conv_std_logic_vector(32000,AMPL_WIDTH),
conv_std_logic_vector(32001,AMPL_WIDTH),
conv_std_logic_vector(32002,AMPL_WIDTH),
conv_std_logic_vector(32002,AMPL_WIDTH),
conv_std_logic_vector(32003,AMPL_WIDTH),
conv_std_logic_vector(32004,AMPL_WIDTH),
conv_std_logic_vector(32004,AMPL_WIDTH),
conv_std_logic_vector(32005,AMPL_WIDTH),
conv_std_logic_vector(32006,AMPL_WIDTH),
conv_std_logic_vector(32006,AMPL_WIDTH),
conv_std_logic_vector(32007,AMPL_WIDTH),
conv_std_logic_vector(32008,AMPL_WIDTH),
conv_std_logic_vector(32008,AMPL_WIDTH),
conv_std_logic_vector(32009,AMPL_WIDTH),
conv_std_logic_vector(32010,AMPL_WIDTH),
conv_std_logic_vector(32010,AMPL_WIDTH),
conv_std_logic_vector(32011,AMPL_WIDTH),
conv_std_logic_vector(32012,AMPL_WIDTH),
conv_std_logic_vector(32012,AMPL_WIDTH),
conv_std_logic_vector(32013,AMPL_WIDTH),
conv_std_logic_vector(32014,AMPL_WIDTH),
conv_std_logic_vector(32014,AMPL_WIDTH),
conv_std_logic_vector(32015,AMPL_WIDTH),
conv_std_logic_vector(32016,AMPL_WIDTH),
conv_std_logic_vector(32016,AMPL_WIDTH),
conv_std_logic_vector(32017,AMPL_WIDTH),
conv_std_logic_vector(32018,AMPL_WIDTH),
conv_std_logic_vector(32018,AMPL_WIDTH),
conv_std_logic_vector(32019,AMPL_WIDTH),
conv_std_logic_vector(32020,AMPL_WIDTH),
conv_std_logic_vector(32020,AMPL_WIDTH),
conv_std_logic_vector(32021,AMPL_WIDTH),
conv_std_logic_vector(32022,AMPL_WIDTH),
conv_std_logic_vector(32022,AMPL_WIDTH),
conv_std_logic_vector(32023,AMPL_WIDTH),
conv_std_logic_vector(32024,AMPL_WIDTH),
conv_std_logic_vector(32024,AMPL_WIDTH),
conv_std_logic_vector(32025,AMPL_WIDTH),
conv_std_logic_vector(32026,AMPL_WIDTH),
conv_std_logic_vector(32026,AMPL_WIDTH),
conv_std_logic_vector(32027,AMPL_WIDTH),
conv_std_logic_vector(32028,AMPL_WIDTH),
conv_std_logic_vector(32028,AMPL_WIDTH),
conv_std_logic_vector(32029,AMPL_WIDTH),
conv_std_logic_vector(32030,AMPL_WIDTH),
conv_std_logic_vector(32030,AMPL_WIDTH),
conv_std_logic_vector(32031,AMPL_WIDTH),
conv_std_logic_vector(32032,AMPL_WIDTH),
conv_std_logic_vector(32032,AMPL_WIDTH),
conv_std_logic_vector(32033,AMPL_WIDTH),
conv_std_logic_vector(32034,AMPL_WIDTH),
conv_std_logic_vector(32034,AMPL_WIDTH),
conv_std_logic_vector(32035,AMPL_WIDTH),
conv_std_logic_vector(32036,AMPL_WIDTH),
conv_std_logic_vector(32036,AMPL_WIDTH),
conv_std_logic_vector(32037,AMPL_WIDTH),
conv_std_logic_vector(32038,AMPL_WIDTH),
conv_std_logic_vector(32038,AMPL_WIDTH),
conv_std_logic_vector(32039,AMPL_WIDTH),
conv_std_logic_vector(32040,AMPL_WIDTH),
conv_std_logic_vector(32040,AMPL_WIDTH),
conv_std_logic_vector(32041,AMPL_WIDTH),
conv_std_logic_vector(32041,AMPL_WIDTH),
conv_std_logic_vector(32042,AMPL_WIDTH),
conv_std_logic_vector(32043,AMPL_WIDTH),
conv_std_logic_vector(32043,AMPL_WIDTH),
conv_std_logic_vector(32044,AMPL_WIDTH),
conv_std_logic_vector(32045,AMPL_WIDTH),
conv_std_logic_vector(32045,AMPL_WIDTH),
conv_std_logic_vector(32046,AMPL_WIDTH),
conv_std_logic_vector(32047,AMPL_WIDTH),
conv_std_logic_vector(32047,AMPL_WIDTH),
conv_std_logic_vector(32048,AMPL_WIDTH),
conv_std_logic_vector(32049,AMPL_WIDTH),
conv_std_logic_vector(32049,AMPL_WIDTH),
conv_std_logic_vector(32050,AMPL_WIDTH),
conv_std_logic_vector(32051,AMPL_WIDTH),
conv_std_logic_vector(32051,AMPL_WIDTH),
conv_std_logic_vector(32052,AMPL_WIDTH),
conv_std_logic_vector(32053,AMPL_WIDTH),
conv_std_logic_vector(32053,AMPL_WIDTH),
conv_std_logic_vector(32054,AMPL_WIDTH),
conv_std_logic_vector(32055,AMPL_WIDTH),
conv_std_logic_vector(32055,AMPL_WIDTH),
conv_std_logic_vector(32056,AMPL_WIDTH),
conv_std_logic_vector(32057,AMPL_WIDTH),
conv_std_logic_vector(32057,AMPL_WIDTH),
conv_std_logic_vector(32058,AMPL_WIDTH),
conv_std_logic_vector(32058,AMPL_WIDTH),
conv_std_logic_vector(32059,AMPL_WIDTH),
conv_std_logic_vector(32060,AMPL_WIDTH),
conv_std_logic_vector(32060,AMPL_WIDTH),
conv_std_logic_vector(32061,AMPL_WIDTH),
conv_std_logic_vector(32062,AMPL_WIDTH),
conv_std_logic_vector(32062,AMPL_WIDTH),
conv_std_logic_vector(32063,AMPL_WIDTH),
conv_std_logic_vector(32064,AMPL_WIDTH),
conv_std_logic_vector(32064,AMPL_WIDTH),
conv_std_logic_vector(32065,AMPL_WIDTH),
conv_std_logic_vector(32066,AMPL_WIDTH),
conv_std_logic_vector(32066,AMPL_WIDTH),
conv_std_logic_vector(32067,AMPL_WIDTH),
conv_std_logic_vector(32068,AMPL_WIDTH),
conv_std_logic_vector(32068,AMPL_WIDTH),
conv_std_logic_vector(32069,AMPL_WIDTH),
conv_std_logic_vector(32069,AMPL_WIDTH),
conv_std_logic_vector(32070,AMPL_WIDTH),
conv_std_logic_vector(32071,AMPL_WIDTH),
conv_std_logic_vector(32071,AMPL_WIDTH),
conv_std_logic_vector(32072,AMPL_WIDTH),
conv_std_logic_vector(32073,AMPL_WIDTH),
conv_std_logic_vector(32073,AMPL_WIDTH),
conv_std_logic_vector(32074,AMPL_WIDTH),
conv_std_logic_vector(32075,AMPL_WIDTH),
conv_std_logic_vector(32075,AMPL_WIDTH),
conv_std_logic_vector(32076,AMPL_WIDTH),
conv_std_logic_vector(32077,AMPL_WIDTH),
conv_std_logic_vector(32077,AMPL_WIDTH),
conv_std_logic_vector(32078,AMPL_WIDTH),
conv_std_logic_vector(32078,AMPL_WIDTH),
conv_std_logic_vector(32079,AMPL_WIDTH),
conv_std_logic_vector(32080,AMPL_WIDTH),
conv_std_logic_vector(32080,AMPL_WIDTH),
conv_std_logic_vector(32081,AMPL_WIDTH),
conv_std_logic_vector(32082,AMPL_WIDTH),
conv_std_logic_vector(32082,AMPL_WIDTH),
conv_std_logic_vector(32083,AMPL_WIDTH),
conv_std_logic_vector(32084,AMPL_WIDTH),
conv_std_logic_vector(32084,AMPL_WIDTH),
conv_std_logic_vector(32085,AMPL_WIDTH),
conv_std_logic_vector(32086,AMPL_WIDTH),
conv_std_logic_vector(32086,AMPL_WIDTH),
conv_std_logic_vector(32087,AMPL_WIDTH),
conv_std_logic_vector(32087,AMPL_WIDTH),
conv_std_logic_vector(32088,AMPL_WIDTH),
conv_std_logic_vector(32089,AMPL_WIDTH),
conv_std_logic_vector(32089,AMPL_WIDTH),
conv_std_logic_vector(32090,AMPL_WIDTH),
conv_std_logic_vector(32091,AMPL_WIDTH),
conv_std_logic_vector(32091,AMPL_WIDTH),
conv_std_logic_vector(32092,AMPL_WIDTH),
conv_std_logic_vector(32092,AMPL_WIDTH),
conv_std_logic_vector(32093,AMPL_WIDTH),
conv_std_logic_vector(32094,AMPL_WIDTH),
conv_std_logic_vector(32094,AMPL_WIDTH),
conv_std_logic_vector(32095,AMPL_WIDTH),
conv_std_logic_vector(32096,AMPL_WIDTH),
conv_std_logic_vector(32096,AMPL_WIDTH),
conv_std_logic_vector(32097,AMPL_WIDTH),
conv_std_logic_vector(32098,AMPL_WIDTH),
conv_std_logic_vector(32098,AMPL_WIDTH),
conv_std_logic_vector(32099,AMPL_WIDTH),
conv_std_logic_vector(32099,AMPL_WIDTH),
conv_std_logic_vector(32100,AMPL_WIDTH),
conv_std_logic_vector(32101,AMPL_WIDTH),
conv_std_logic_vector(32101,AMPL_WIDTH),
conv_std_logic_vector(32102,AMPL_WIDTH),
conv_std_logic_vector(32103,AMPL_WIDTH),
conv_std_logic_vector(32103,AMPL_WIDTH),
conv_std_logic_vector(32104,AMPL_WIDTH),
conv_std_logic_vector(32104,AMPL_WIDTH),
conv_std_logic_vector(32105,AMPL_WIDTH),
conv_std_logic_vector(32106,AMPL_WIDTH),
conv_std_logic_vector(32106,AMPL_WIDTH),
conv_std_logic_vector(32107,AMPL_WIDTH),
conv_std_logic_vector(32108,AMPL_WIDTH),
conv_std_logic_vector(32108,AMPL_WIDTH),
conv_std_logic_vector(32109,AMPL_WIDTH),
conv_std_logic_vector(32110,AMPL_WIDTH),
conv_std_logic_vector(32110,AMPL_WIDTH),
conv_std_logic_vector(32111,AMPL_WIDTH),
conv_std_logic_vector(32111,AMPL_WIDTH),
conv_std_logic_vector(32112,AMPL_WIDTH),
conv_std_logic_vector(32113,AMPL_WIDTH),
conv_std_logic_vector(32113,AMPL_WIDTH),
conv_std_logic_vector(32114,AMPL_WIDTH),
conv_std_logic_vector(32115,AMPL_WIDTH),
conv_std_logic_vector(32115,AMPL_WIDTH),
conv_std_logic_vector(32116,AMPL_WIDTH),
conv_std_logic_vector(32116,AMPL_WIDTH),
conv_std_logic_vector(32117,AMPL_WIDTH),
conv_std_logic_vector(32118,AMPL_WIDTH),
conv_std_logic_vector(32118,AMPL_WIDTH),
conv_std_logic_vector(32119,AMPL_WIDTH),
conv_std_logic_vector(32119,AMPL_WIDTH),
conv_std_logic_vector(32120,AMPL_WIDTH),
conv_std_logic_vector(32121,AMPL_WIDTH),
conv_std_logic_vector(32121,AMPL_WIDTH),
conv_std_logic_vector(32122,AMPL_WIDTH),
conv_std_logic_vector(32123,AMPL_WIDTH),
conv_std_logic_vector(32123,AMPL_WIDTH),
conv_std_logic_vector(32124,AMPL_WIDTH),
conv_std_logic_vector(32124,AMPL_WIDTH),
conv_std_logic_vector(32125,AMPL_WIDTH),
conv_std_logic_vector(32126,AMPL_WIDTH),
conv_std_logic_vector(32126,AMPL_WIDTH),
conv_std_logic_vector(32127,AMPL_WIDTH),
conv_std_logic_vector(32128,AMPL_WIDTH),
conv_std_logic_vector(32128,AMPL_WIDTH),
conv_std_logic_vector(32129,AMPL_WIDTH),
conv_std_logic_vector(32129,AMPL_WIDTH),
conv_std_logic_vector(32130,AMPL_WIDTH),
conv_std_logic_vector(32131,AMPL_WIDTH),
conv_std_logic_vector(32131,AMPL_WIDTH),
conv_std_logic_vector(32132,AMPL_WIDTH),
conv_std_logic_vector(32132,AMPL_WIDTH),
conv_std_logic_vector(32133,AMPL_WIDTH),
conv_std_logic_vector(32134,AMPL_WIDTH),
conv_std_logic_vector(32134,AMPL_WIDTH),
conv_std_logic_vector(32135,AMPL_WIDTH),
conv_std_logic_vector(32136,AMPL_WIDTH),
conv_std_logic_vector(32136,AMPL_WIDTH),
conv_std_logic_vector(32137,AMPL_WIDTH),
conv_std_logic_vector(32137,AMPL_WIDTH),
conv_std_logic_vector(32138,AMPL_WIDTH),
conv_std_logic_vector(32139,AMPL_WIDTH),
conv_std_logic_vector(32139,AMPL_WIDTH),
conv_std_logic_vector(32140,AMPL_WIDTH),
conv_std_logic_vector(32140,AMPL_WIDTH),
conv_std_logic_vector(32141,AMPL_WIDTH),
conv_std_logic_vector(32142,AMPL_WIDTH),
conv_std_logic_vector(32142,AMPL_WIDTH),
conv_std_logic_vector(32143,AMPL_WIDTH),
conv_std_logic_vector(32144,AMPL_WIDTH),
conv_std_logic_vector(32144,AMPL_WIDTH),
conv_std_logic_vector(32145,AMPL_WIDTH),
conv_std_logic_vector(32145,AMPL_WIDTH),
conv_std_logic_vector(32146,AMPL_WIDTH),
conv_std_logic_vector(32147,AMPL_WIDTH),
conv_std_logic_vector(32147,AMPL_WIDTH),
conv_std_logic_vector(32148,AMPL_WIDTH),
conv_std_logic_vector(32148,AMPL_WIDTH),
conv_std_logic_vector(32149,AMPL_WIDTH),
conv_std_logic_vector(32150,AMPL_WIDTH),
conv_std_logic_vector(32150,AMPL_WIDTH),
conv_std_logic_vector(32151,AMPL_WIDTH),
conv_std_logic_vector(32151,AMPL_WIDTH),
conv_std_logic_vector(32152,AMPL_WIDTH),
conv_std_logic_vector(32153,AMPL_WIDTH),
conv_std_logic_vector(32153,AMPL_WIDTH),
conv_std_logic_vector(32154,AMPL_WIDTH),
conv_std_logic_vector(32154,AMPL_WIDTH),
conv_std_logic_vector(32155,AMPL_WIDTH),
conv_std_logic_vector(32156,AMPL_WIDTH),
conv_std_logic_vector(32156,AMPL_WIDTH),
conv_std_logic_vector(32157,AMPL_WIDTH),
conv_std_logic_vector(32157,AMPL_WIDTH),
conv_std_logic_vector(32158,AMPL_WIDTH),
conv_std_logic_vector(32159,AMPL_WIDTH),
conv_std_logic_vector(32159,AMPL_WIDTH),
conv_std_logic_vector(32160,AMPL_WIDTH),
conv_std_logic_vector(32160,AMPL_WIDTH),
conv_std_logic_vector(32161,AMPL_WIDTH),
conv_std_logic_vector(32162,AMPL_WIDTH),
conv_std_logic_vector(32162,AMPL_WIDTH),
conv_std_logic_vector(32163,AMPL_WIDTH),
conv_std_logic_vector(32163,AMPL_WIDTH),
conv_std_logic_vector(32164,AMPL_WIDTH),
conv_std_logic_vector(32165,AMPL_WIDTH),
conv_std_logic_vector(32165,AMPL_WIDTH),
conv_std_logic_vector(32166,AMPL_WIDTH),
conv_std_logic_vector(32166,AMPL_WIDTH),
conv_std_logic_vector(32167,AMPL_WIDTH),
conv_std_logic_vector(32168,AMPL_WIDTH),
conv_std_logic_vector(32168,AMPL_WIDTH),
conv_std_logic_vector(32169,AMPL_WIDTH),
conv_std_logic_vector(32169,AMPL_WIDTH),
conv_std_logic_vector(32170,AMPL_WIDTH),
conv_std_logic_vector(32171,AMPL_WIDTH),
conv_std_logic_vector(32171,AMPL_WIDTH),
conv_std_logic_vector(32172,AMPL_WIDTH),
conv_std_logic_vector(32172,AMPL_WIDTH),
conv_std_logic_vector(32173,AMPL_WIDTH),
conv_std_logic_vector(32174,AMPL_WIDTH),
conv_std_logic_vector(32174,AMPL_WIDTH),
conv_std_logic_vector(32175,AMPL_WIDTH),
conv_std_logic_vector(32175,AMPL_WIDTH),
conv_std_logic_vector(32176,AMPL_WIDTH),
conv_std_logic_vector(32177,AMPL_WIDTH),
conv_std_logic_vector(32177,AMPL_WIDTH),
conv_std_logic_vector(32178,AMPL_WIDTH),
conv_std_logic_vector(32178,AMPL_WIDTH),
conv_std_logic_vector(32179,AMPL_WIDTH),
conv_std_logic_vector(32180,AMPL_WIDTH),
conv_std_logic_vector(32180,AMPL_WIDTH),
conv_std_logic_vector(32181,AMPL_WIDTH),
conv_std_logic_vector(32181,AMPL_WIDTH),
conv_std_logic_vector(32182,AMPL_WIDTH),
conv_std_logic_vector(32183,AMPL_WIDTH),
conv_std_logic_vector(32183,AMPL_WIDTH),
conv_std_logic_vector(32184,AMPL_WIDTH),
conv_std_logic_vector(32184,AMPL_WIDTH),
conv_std_logic_vector(32185,AMPL_WIDTH),
conv_std_logic_vector(32185,AMPL_WIDTH),
conv_std_logic_vector(32186,AMPL_WIDTH),
conv_std_logic_vector(32187,AMPL_WIDTH),
conv_std_logic_vector(32187,AMPL_WIDTH),
conv_std_logic_vector(32188,AMPL_WIDTH),
conv_std_logic_vector(32188,AMPL_WIDTH),
conv_std_logic_vector(32189,AMPL_WIDTH),
conv_std_logic_vector(32190,AMPL_WIDTH),
conv_std_logic_vector(32190,AMPL_WIDTH),
conv_std_logic_vector(32191,AMPL_WIDTH),
conv_std_logic_vector(32191,AMPL_WIDTH),
conv_std_logic_vector(32192,AMPL_WIDTH),
conv_std_logic_vector(32193,AMPL_WIDTH),
conv_std_logic_vector(32193,AMPL_WIDTH),
conv_std_logic_vector(32194,AMPL_WIDTH),
conv_std_logic_vector(32194,AMPL_WIDTH),
conv_std_logic_vector(32195,AMPL_WIDTH),
conv_std_logic_vector(32195,AMPL_WIDTH),
conv_std_logic_vector(32196,AMPL_WIDTH),
conv_std_logic_vector(32197,AMPL_WIDTH),
conv_std_logic_vector(32197,AMPL_WIDTH),
conv_std_logic_vector(32198,AMPL_WIDTH),
conv_std_logic_vector(32198,AMPL_WIDTH),
conv_std_logic_vector(32199,AMPL_WIDTH),
conv_std_logic_vector(32200,AMPL_WIDTH),
conv_std_logic_vector(32200,AMPL_WIDTH),
conv_std_logic_vector(32201,AMPL_WIDTH),
conv_std_logic_vector(32201,AMPL_WIDTH),
conv_std_logic_vector(32202,AMPL_WIDTH),
conv_std_logic_vector(32202,AMPL_WIDTH),
conv_std_logic_vector(32203,AMPL_WIDTH),
conv_std_logic_vector(32204,AMPL_WIDTH),
conv_std_logic_vector(32204,AMPL_WIDTH),
conv_std_logic_vector(32205,AMPL_WIDTH),
conv_std_logic_vector(32205,AMPL_WIDTH),
conv_std_logic_vector(32206,AMPL_WIDTH),
conv_std_logic_vector(32206,AMPL_WIDTH),
conv_std_logic_vector(32207,AMPL_WIDTH),
conv_std_logic_vector(32208,AMPL_WIDTH),
conv_std_logic_vector(32208,AMPL_WIDTH),
conv_std_logic_vector(32209,AMPL_WIDTH),
conv_std_logic_vector(32209,AMPL_WIDTH),
conv_std_logic_vector(32210,AMPL_WIDTH),
conv_std_logic_vector(32211,AMPL_WIDTH),
conv_std_logic_vector(32211,AMPL_WIDTH),
conv_std_logic_vector(32212,AMPL_WIDTH),
conv_std_logic_vector(32212,AMPL_WIDTH),
conv_std_logic_vector(32213,AMPL_WIDTH),
conv_std_logic_vector(32213,AMPL_WIDTH),
conv_std_logic_vector(32214,AMPL_WIDTH),
conv_std_logic_vector(32215,AMPL_WIDTH),
conv_std_logic_vector(32215,AMPL_WIDTH),
conv_std_logic_vector(32216,AMPL_WIDTH),
conv_std_logic_vector(32216,AMPL_WIDTH),
conv_std_logic_vector(32217,AMPL_WIDTH),
conv_std_logic_vector(32217,AMPL_WIDTH),
conv_std_logic_vector(32218,AMPL_WIDTH),
conv_std_logic_vector(32219,AMPL_WIDTH),
conv_std_logic_vector(32219,AMPL_WIDTH),
conv_std_logic_vector(32220,AMPL_WIDTH),
conv_std_logic_vector(32220,AMPL_WIDTH),
conv_std_logic_vector(32221,AMPL_WIDTH),
conv_std_logic_vector(32221,AMPL_WIDTH),
conv_std_logic_vector(32222,AMPL_WIDTH),
conv_std_logic_vector(32223,AMPL_WIDTH),
conv_std_logic_vector(32223,AMPL_WIDTH),
conv_std_logic_vector(32224,AMPL_WIDTH),
conv_std_logic_vector(32224,AMPL_WIDTH),
conv_std_logic_vector(32225,AMPL_WIDTH),
conv_std_logic_vector(32225,AMPL_WIDTH),
conv_std_logic_vector(32226,AMPL_WIDTH),
conv_std_logic_vector(32227,AMPL_WIDTH),
conv_std_logic_vector(32227,AMPL_WIDTH),
conv_std_logic_vector(32228,AMPL_WIDTH),
conv_std_logic_vector(32228,AMPL_WIDTH),
conv_std_logic_vector(32229,AMPL_WIDTH),
conv_std_logic_vector(32229,AMPL_WIDTH),
conv_std_logic_vector(32230,AMPL_WIDTH),
conv_std_logic_vector(32231,AMPL_WIDTH),
conv_std_logic_vector(32231,AMPL_WIDTH),
conv_std_logic_vector(32232,AMPL_WIDTH),
conv_std_logic_vector(32232,AMPL_WIDTH),
conv_std_logic_vector(32233,AMPL_WIDTH),
conv_std_logic_vector(32233,AMPL_WIDTH),
conv_std_logic_vector(32234,AMPL_WIDTH),
conv_std_logic_vector(32234,AMPL_WIDTH),
conv_std_logic_vector(32235,AMPL_WIDTH),
conv_std_logic_vector(32236,AMPL_WIDTH),
conv_std_logic_vector(32236,AMPL_WIDTH),
conv_std_logic_vector(32237,AMPL_WIDTH),
conv_std_logic_vector(32237,AMPL_WIDTH),
conv_std_logic_vector(32238,AMPL_WIDTH),
conv_std_logic_vector(32238,AMPL_WIDTH),
conv_std_logic_vector(32239,AMPL_WIDTH),
conv_std_logic_vector(32240,AMPL_WIDTH),
conv_std_logic_vector(32240,AMPL_WIDTH),
conv_std_logic_vector(32241,AMPL_WIDTH),
conv_std_logic_vector(32241,AMPL_WIDTH),
conv_std_logic_vector(32242,AMPL_WIDTH),
conv_std_logic_vector(32242,AMPL_WIDTH),
conv_std_logic_vector(32243,AMPL_WIDTH),
conv_std_logic_vector(32243,AMPL_WIDTH),
conv_std_logic_vector(32244,AMPL_WIDTH),
conv_std_logic_vector(32245,AMPL_WIDTH),
conv_std_logic_vector(32245,AMPL_WIDTH),
conv_std_logic_vector(32246,AMPL_WIDTH),
conv_std_logic_vector(32246,AMPL_WIDTH),
conv_std_logic_vector(32247,AMPL_WIDTH),
conv_std_logic_vector(32247,AMPL_WIDTH),
conv_std_logic_vector(32248,AMPL_WIDTH),
conv_std_logic_vector(32248,AMPL_WIDTH),
conv_std_logic_vector(32249,AMPL_WIDTH),
conv_std_logic_vector(32250,AMPL_WIDTH),
conv_std_logic_vector(32250,AMPL_WIDTH),
conv_std_logic_vector(32251,AMPL_WIDTH),
conv_std_logic_vector(32251,AMPL_WIDTH),
conv_std_logic_vector(32252,AMPL_WIDTH),
conv_std_logic_vector(32252,AMPL_WIDTH),
conv_std_logic_vector(32253,AMPL_WIDTH),
conv_std_logic_vector(32253,AMPL_WIDTH),
conv_std_logic_vector(32254,AMPL_WIDTH),
conv_std_logic_vector(32255,AMPL_WIDTH),
conv_std_logic_vector(32255,AMPL_WIDTH),
conv_std_logic_vector(32256,AMPL_WIDTH),
conv_std_logic_vector(32256,AMPL_WIDTH),
conv_std_logic_vector(32257,AMPL_WIDTH),
conv_std_logic_vector(32257,AMPL_WIDTH),
conv_std_logic_vector(32258,AMPL_WIDTH),
conv_std_logic_vector(32258,AMPL_WIDTH),
conv_std_logic_vector(32259,AMPL_WIDTH),
conv_std_logic_vector(32260,AMPL_WIDTH),
conv_std_logic_vector(32260,AMPL_WIDTH),
conv_std_logic_vector(32261,AMPL_WIDTH),
conv_std_logic_vector(32261,AMPL_WIDTH),
conv_std_logic_vector(32262,AMPL_WIDTH),
conv_std_logic_vector(32262,AMPL_WIDTH),
conv_std_logic_vector(32263,AMPL_WIDTH),
conv_std_logic_vector(32263,AMPL_WIDTH),
conv_std_logic_vector(32264,AMPL_WIDTH),
conv_std_logic_vector(32265,AMPL_WIDTH),
conv_std_logic_vector(32265,AMPL_WIDTH),
conv_std_logic_vector(32266,AMPL_WIDTH),
conv_std_logic_vector(32266,AMPL_WIDTH),
conv_std_logic_vector(32267,AMPL_WIDTH),
conv_std_logic_vector(32267,AMPL_WIDTH),
conv_std_logic_vector(32268,AMPL_WIDTH),
conv_std_logic_vector(32268,AMPL_WIDTH),
conv_std_logic_vector(32269,AMPL_WIDTH),
conv_std_logic_vector(32269,AMPL_WIDTH),
conv_std_logic_vector(32270,AMPL_WIDTH),
conv_std_logic_vector(32271,AMPL_WIDTH),
conv_std_logic_vector(32271,AMPL_WIDTH),
conv_std_logic_vector(32272,AMPL_WIDTH),
conv_std_logic_vector(32272,AMPL_WIDTH),
conv_std_logic_vector(32273,AMPL_WIDTH),
conv_std_logic_vector(32273,AMPL_WIDTH),
conv_std_logic_vector(32274,AMPL_WIDTH),
conv_std_logic_vector(32274,AMPL_WIDTH),
conv_std_logic_vector(32275,AMPL_WIDTH),
conv_std_logic_vector(32275,AMPL_WIDTH),
conv_std_logic_vector(32276,AMPL_WIDTH),
conv_std_logic_vector(32277,AMPL_WIDTH),
conv_std_logic_vector(32277,AMPL_WIDTH),
conv_std_logic_vector(32278,AMPL_WIDTH),
conv_std_logic_vector(32278,AMPL_WIDTH),
conv_std_logic_vector(32279,AMPL_WIDTH),
conv_std_logic_vector(32279,AMPL_WIDTH),
conv_std_logic_vector(32280,AMPL_WIDTH),
conv_std_logic_vector(32280,AMPL_WIDTH),
conv_std_logic_vector(32281,AMPL_WIDTH),
conv_std_logic_vector(32281,AMPL_WIDTH),
conv_std_logic_vector(32282,AMPL_WIDTH),
conv_std_logic_vector(32282,AMPL_WIDTH),
conv_std_logic_vector(32283,AMPL_WIDTH),
conv_std_logic_vector(32284,AMPL_WIDTH),
conv_std_logic_vector(32284,AMPL_WIDTH),
conv_std_logic_vector(32285,AMPL_WIDTH),
conv_std_logic_vector(32285,AMPL_WIDTH),
conv_std_logic_vector(32286,AMPL_WIDTH),
conv_std_logic_vector(32286,AMPL_WIDTH),
conv_std_logic_vector(32287,AMPL_WIDTH),
conv_std_logic_vector(32287,AMPL_WIDTH),
conv_std_logic_vector(32288,AMPL_WIDTH),
conv_std_logic_vector(32288,AMPL_WIDTH),
conv_std_logic_vector(32289,AMPL_WIDTH),
conv_std_logic_vector(32289,AMPL_WIDTH),
conv_std_logic_vector(32290,AMPL_WIDTH),
conv_std_logic_vector(32290,AMPL_WIDTH),
conv_std_logic_vector(32291,AMPL_WIDTH),
conv_std_logic_vector(32292,AMPL_WIDTH),
conv_std_logic_vector(32292,AMPL_WIDTH),
conv_std_logic_vector(32293,AMPL_WIDTH),
conv_std_logic_vector(32293,AMPL_WIDTH),
conv_std_logic_vector(32294,AMPL_WIDTH),
conv_std_logic_vector(32294,AMPL_WIDTH),
conv_std_logic_vector(32295,AMPL_WIDTH),
conv_std_logic_vector(32295,AMPL_WIDTH),
conv_std_logic_vector(32296,AMPL_WIDTH),
conv_std_logic_vector(32296,AMPL_WIDTH),
conv_std_logic_vector(32297,AMPL_WIDTH),
conv_std_logic_vector(32297,AMPL_WIDTH),
conv_std_logic_vector(32298,AMPL_WIDTH),
conv_std_logic_vector(32298,AMPL_WIDTH),
conv_std_logic_vector(32299,AMPL_WIDTH),
conv_std_logic_vector(32300,AMPL_WIDTH),
conv_std_logic_vector(32300,AMPL_WIDTH),
conv_std_logic_vector(32301,AMPL_WIDTH),
conv_std_logic_vector(32301,AMPL_WIDTH),
conv_std_logic_vector(32302,AMPL_WIDTH),
conv_std_logic_vector(32302,AMPL_WIDTH),
conv_std_logic_vector(32303,AMPL_WIDTH),
conv_std_logic_vector(32303,AMPL_WIDTH),
conv_std_logic_vector(32304,AMPL_WIDTH),
conv_std_logic_vector(32304,AMPL_WIDTH),
conv_std_logic_vector(32305,AMPL_WIDTH),
conv_std_logic_vector(32305,AMPL_WIDTH),
conv_std_logic_vector(32306,AMPL_WIDTH),
conv_std_logic_vector(32306,AMPL_WIDTH),
conv_std_logic_vector(32307,AMPL_WIDTH),
conv_std_logic_vector(32307,AMPL_WIDTH),
conv_std_logic_vector(32308,AMPL_WIDTH),
conv_std_logic_vector(32308,AMPL_WIDTH),
conv_std_logic_vector(32309,AMPL_WIDTH),
conv_std_logic_vector(32310,AMPL_WIDTH),
conv_std_logic_vector(32310,AMPL_WIDTH),
conv_std_logic_vector(32311,AMPL_WIDTH),
conv_std_logic_vector(32311,AMPL_WIDTH),
conv_std_logic_vector(32312,AMPL_WIDTH),
conv_std_logic_vector(32312,AMPL_WIDTH),
conv_std_logic_vector(32313,AMPL_WIDTH),
conv_std_logic_vector(32313,AMPL_WIDTH),
conv_std_logic_vector(32314,AMPL_WIDTH),
conv_std_logic_vector(32314,AMPL_WIDTH),
conv_std_logic_vector(32315,AMPL_WIDTH),
conv_std_logic_vector(32315,AMPL_WIDTH),
conv_std_logic_vector(32316,AMPL_WIDTH),
conv_std_logic_vector(32316,AMPL_WIDTH),
conv_std_logic_vector(32317,AMPL_WIDTH),
conv_std_logic_vector(32317,AMPL_WIDTH),
conv_std_logic_vector(32318,AMPL_WIDTH),
conv_std_logic_vector(32318,AMPL_WIDTH),
conv_std_logic_vector(32319,AMPL_WIDTH),
conv_std_logic_vector(32319,AMPL_WIDTH),
conv_std_logic_vector(32320,AMPL_WIDTH),
conv_std_logic_vector(32320,AMPL_WIDTH),
conv_std_logic_vector(32321,AMPL_WIDTH),
conv_std_logic_vector(32321,AMPL_WIDTH),
conv_std_logic_vector(32322,AMPL_WIDTH),
conv_std_logic_vector(32322,AMPL_WIDTH),
conv_std_logic_vector(32323,AMPL_WIDTH),
conv_std_logic_vector(32324,AMPL_WIDTH),
conv_std_logic_vector(32324,AMPL_WIDTH),
conv_std_logic_vector(32325,AMPL_WIDTH),
conv_std_logic_vector(32325,AMPL_WIDTH),
conv_std_logic_vector(32326,AMPL_WIDTH),
conv_std_logic_vector(32326,AMPL_WIDTH),
conv_std_logic_vector(32327,AMPL_WIDTH),
conv_std_logic_vector(32327,AMPL_WIDTH),
conv_std_logic_vector(32328,AMPL_WIDTH),
conv_std_logic_vector(32328,AMPL_WIDTH),
conv_std_logic_vector(32329,AMPL_WIDTH),
conv_std_logic_vector(32329,AMPL_WIDTH),
conv_std_logic_vector(32330,AMPL_WIDTH),
conv_std_logic_vector(32330,AMPL_WIDTH),
conv_std_logic_vector(32331,AMPL_WIDTH),
conv_std_logic_vector(32331,AMPL_WIDTH),
conv_std_logic_vector(32332,AMPL_WIDTH),
conv_std_logic_vector(32332,AMPL_WIDTH),
conv_std_logic_vector(32333,AMPL_WIDTH),
conv_std_logic_vector(32333,AMPL_WIDTH),
conv_std_logic_vector(32334,AMPL_WIDTH),
conv_std_logic_vector(32334,AMPL_WIDTH),
conv_std_logic_vector(32335,AMPL_WIDTH),
conv_std_logic_vector(32335,AMPL_WIDTH),
conv_std_logic_vector(32336,AMPL_WIDTH),
conv_std_logic_vector(32336,AMPL_WIDTH),
conv_std_logic_vector(32337,AMPL_WIDTH),
conv_std_logic_vector(32337,AMPL_WIDTH),
conv_std_logic_vector(32338,AMPL_WIDTH),
conv_std_logic_vector(32338,AMPL_WIDTH),
conv_std_logic_vector(32339,AMPL_WIDTH),
conv_std_logic_vector(32339,AMPL_WIDTH),
conv_std_logic_vector(32340,AMPL_WIDTH),
conv_std_logic_vector(32340,AMPL_WIDTH),
conv_std_logic_vector(32341,AMPL_WIDTH),
conv_std_logic_vector(32341,AMPL_WIDTH),
conv_std_logic_vector(32342,AMPL_WIDTH),
conv_std_logic_vector(32342,AMPL_WIDTH),
conv_std_logic_vector(32343,AMPL_WIDTH),
conv_std_logic_vector(32343,AMPL_WIDTH),
conv_std_logic_vector(32344,AMPL_WIDTH),
conv_std_logic_vector(32344,AMPL_WIDTH),
conv_std_logic_vector(32345,AMPL_WIDTH),
conv_std_logic_vector(32345,AMPL_WIDTH),
conv_std_logic_vector(32346,AMPL_WIDTH),
conv_std_logic_vector(32346,AMPL_WIDTH),
conv_std_logic_vector(32347,AMPL_WIDTH),
conv_std_logic_vector(32347,AMPL_WIDTH),
conv_std_logic_vector(32348,AMPL_WIDTH),
conv_std_logic_vector(32348,AMPL_WIDTH),
conv_std_logic_vector(32349,AMPL_WIDTH),
conv_std_logic_vector(32349,AMPL_WIDTH),
conv_std_logic_vector(32350,AMPL_WIDTH),
conv_std_logic_vector(32350,AMPL_WIDTH),
conv_std_logic_vector(32351,AMPL_WIDTH),
conv_std_logic_vector(32351,AMPL_WIDTH),
conv_std_logic_vector(32352,AMPL_WIDTH),
conv_std_logic_vector(32352,AMPL_WIDTH),
conv_std_logic_vector(32353,AMPL_WIDTH),
conv_std_logic_vector(32353,AMPL_WIDTH),
conv_std_logic_vector(32354,AMPL_WIDTH),
conv_std_logic_vector(32354,AMPL_WIDTH),
conv_std_logic_vector(32355,AMPL_WIDTH),
conv_std_logic_vector(32355,AMPL_WIDTH),
conv_std_logic_vector(32356,AMPL_WIDTH),
conv_std_logic_vector(32356,AMPL_WIDTH),
conv_std_logic_vector(32357,AMPL_WIDTH),
conv_std_logic_vector(32357,AMPL_WIDTH),
conv_std_logic_vector(32358,AMPL_WIDTH),
conv_std_logic_vector(32358,AMPL_WIDTH),
conv_std_logic_vector(32359,AMPL_WIDTH),
conv_std_logic_vector(32359,AMPL_WIDTH),
conv_std_logic_vector(32360,AMPL_WIDTH),
conv_std_logic_vector(32360,AMPL_WIDTH),
conv_std_logic_vector(32361,AMPL_WIDTH),
conv_std_logic_vector(32361,AMPL_WIDTH),
conv_std_logic_vector(32362,AMPL_WIDTH),
conv_std_logic_vector(32362,AMPL_WIDTH),
conv_std_logic_vector(32363,AMPL_WIDTH),
conv_std_logic_vector(32363,AMPL_WIDTH),
conv_std_logic_vector(32364,AMPL_WIDTH),
conv_std_logic_vector(32364,AMPL_WIDTH),
conv_std_logic_vector(32365,AMPL_WIDTH),
conv_std_logic_vector(32365,AMPL_WIDTH),
conv_std_logic_vector(32366,AMPL_WIDTH),
conv_std_logic_vector(32366,AMPL_WIDTH),
conv_std_logic_vector(32367,AMPL_WIDTH),
conv_std_logic_vector(32367,AMPL_WIDTH),
conv_std_logic_vector(32368,AMPL_WIDTH),
conv_std_logic_vector(32368,AMPL_WIDTH),
conv_std_logic_vector(32369,AMPL_WIDTH),
conv_std_logic_vector(32369,AMPL_WIDTH),
conv_std_logic_vector(32370,AMPL_WIDTH),
conv_std_logic_vector(32370,AMPL_WIDTH),
conv_std_logic_vector(32371,AMPL_WIDTH),
conv_std_logic_vector(32371,AMPL_WIDTH),
conv_std_logic_vector(32372,AMPL_WIDTH),
conv_std_logic_vector(32372,AMPL_WIDTH),
conv_std_logic_vector(32373,AMPL_WIDTH),
conv_std_logic_vector(32373,AMPL_WIDTH),
conv_std_logic_vector(32374,AMPL_WIDTH),
conv_std_logic_vector(32374,AMPL_WIDTH),
conv_std_logic_vector(32375,AMPL_WIDTH),
conv_std_logic_vector(32375,AMPL_WIDTH),
conv_std_logic_vector(32375,AMPL_WIDTH),
conv_std_logic_vector(32376,AMPL_WIDTH),
conv_std_logic_vector(32376,AMPL_WIDTH),
conv_std_logic_vector(32377,AMPL_WIDTH),
conv_std_logic_vector(32377,AMPL_WIDTH),
conv_std_logic_vector(32378,AMPL_WIDTH),
conv_std_logic_vector(32378,AMPL_WIDTH),
conv_std_logic_vector(32379,AMPL_WIDTH),
conv_std_logic_vector(32379,AMPL_WIDTH),
conv_std_logic_vector(32380,AMPL_WIDTH),
conv_std_logic_vector(32380,AMPL_WIDTH),
conv_std_logic_vector(32381,AMPL_WIDTH),
conv_std_logic_vector(32381,AMPL_WIDTH),
conv_std_logic_vector(32382,AMPL_WIDTH),
conv_std_logic_vector(32382,AMPL_WIDTH),
conv_std_logic_vector(32383,AMPL_WIDTH),
conv_std_logic_vector(32383,AMPL_WIDTH),
conv_std_logic_vector(32384,AMPL_WIDTH),
conv_std_logic_vector(32384,AMPL_WIDTH),
conv_std_logic_vector(32385,AMPL_WIDTH),
conv_std_logic_vector(32385,AMPL_WIDTH),
conv_std_logic_vector(32386,AMPL_WIDTH),
conv_std_logic_vector(32386,AMPL_WIDTH),
conv_std_logic_vector(32387,AMPL_WIDTH),
conv_std_logic_vector(32387,AMPL_WIDTH),
conv_std_logic_vector(32387,AMPL_WIDTH),
conv_std_logic_vector(32388,AMPL_WIDTH),
conv_std_logic_vector(32388,AMPL_WIDTH),
conv_std_logic_vector(32389,AMPL_WIDTH),
conv_std_logic_vector(32389,AMPL_WIDTH),
conv_std_logic_vector(32390,AMPL_WIDTH),
conv_std_logic_vector(32390,AMPL_WIDTH),
conv_std_logic_vector(32391,AMPL_WIDTH),
conv_std_logic_vector(32391,AMPL_WIDTH),
conv_std_logic_vector(32392,AMPL_WIDTH),
conv_std_logic_vector(32392,AMPL_WIDTH),
conv_std_logic_vector(32393,AMPL_WIDTH),
conv_std_logic_vector(32393,AMPL_WIDTH),
conv_std_logic_vector(32394,AMPL_WIDTH),
conv_std_logic_vector(32394,AMPL_WIDTH),
conv_std_logic_vector(32395,AMPL_WIDTH),
conv_std_logic_vector(32395,AMPL_WIDTH),
conv_std_logic_vector(32396,AMPL_WIDTH),
conv_std_logic_vector(32396,AMPL_WIDTH),
conv_std_logic_vector(32397,AMPL_WIDTH),
conv_std_logic_vector(32397,AMPL_WIDTH),
conv_std_logic_vector(32397,AMPL_WIDTH),
conv_std_logic_vector(32398,AMPL_WIDTH),
conv_std_logic_vector(32398,AMPL_WIDTH),
conv_std_logic_vector(32399,AMPL_WIDTH),
conv_std_logic_vector(32399,AMPL_WIDTH),
conv_std_logic_vector(32400,AMPL_WIDTH),
conv_std_logic_vector(32400,AMPL_WIDTH),
conv_std_logic_vector(32401,AMPL_WIDTH),
conv_std_logic_vector(32401,AMPL_WIDTH),
conv_std_logic_vector(32402,AMPL_WIDTH),
conv_std_logic_vector(32402,AMPL_WIDTH),
conv_std_logic_vector(32403,AMPL_WIDTH),
conv_std_logic_vector(32403,AMPL_WIDTH),
conv_std_logic_vector(32404,AMPL_WIDTH),
conv_std_logic_vector(32404,AMPL_WIDTH),
conv_std_logic_vector(32404,AMPL_WIDTH),
conv_std_logic_vector(32405,AMPL_WIDTH),
conv_std_logic_vector(32405,AMPL_WIDTH),
conv_std_logic_vector(32406,AMPL_WIDTH),
conv_std_logic_vector(32406,AMPL_WIDTH),
conv_std_logic_vector(32407,AMPL_WIDTH),
conv_std_logic_vector(32407,AMPL_WIDTH),
conv_std_logic_vector(32408,AMPL_WIDTH),
conv_std_logic_vector(32408,AMPL_WIDTH),
conv_std_logic_vector(32409,AMPL_WIDTH),
conv_std_logic_vector(32409,AMPL_WIDTH),
conv_std_logic_vector(32410,AMPL_WIDTH),
conv_std_logic_vector(32410,AMPL_WIDTH),
conv_std_logic_vector(32411,AMPL_WIDTH),
conv_std_logic_vector(32411,AMPL_WIDTH),
conv_std_logic_vector(32411,AMPL_WIDTH),
conv_std_logic_vector(32412,AMPL_WIDTH),
conv_std_logic_vector(32412,AMPL_WIDTH),
conv_std_logic_vector(32413,AMPL_WIDTH),
conv_std_logic_vector(32413,AMPL_WIDTH),
conv_std_logic_vector(32414,AMPL_WIDTH),
conv_std_logic_vector(32414,AMPL_WIDTH),
conv_std_logic_vector(32415,AMPL_WIDTH),
conv_std_logic_vector(32415,AMPL_WIDTH),
conv_std_logic_vector(32416,AMPL_WIDTH),
conv_std_logic_vector(32416,AMPL_WIDTH),
conv_std_logic_vector(32416,AMPL_WIDTH),
conv_std_logic_vector(32417,AMPL_WIDTH),
conv_std_logic_vector(32417,AMPL_WIDTH),
conv_std_logic_vector(32418,AMPL_WIDTH),
conv_std_logic_vector(32418,AMPL_WIDTH),
conv_std_logic_vector(32419,AMPL_WIDTH),
conv_std_logic_vector(32419,AMPL_WIDTH),
conv_std_logic_vector(32420,AMPL_WIDTH),
conv_std_logic_vector(32420,AMPL_WIDTH),
conv_std_logic_vector(32421,AMPL_WIDTH),
conv_std_logic_vector(32421,AMPL_WIDTH),
conv_std_logic_vector(32422,AMPL_WIDTH),
conv_std_logic_vector(32422,AMPL_WIDTH),
conv_std_logic_vector(32422,AMPL_WIDTH),
conv_std_logic_vector(32423,AMPL_WIDTH),
conv_std_logic_vector(32423,AMPL_WIDTH),
conv_std_logic_vector(32424,AMPL_WIDTH),
conv_std_logic_vector(32424,AMPL_WIDTH),
conv_std_logic_vector(32425,AMPL_WIDTH),
conv_std_logic_vector(32425,AMPL_WIDTH),
conv_std_logic_vector(32426,AMPL_WIDTH),
conv_std_logic_vector(32426,AMPL_WIDTH),
conv_std_logic_vector(32426,AMPL_WIDTH),
conv_std_logic_vector(32427,AMPL_WIDTH),
conv_std_logic_vector(32427,AMPL_WIDTH),
conv_std_logic_vector(32428,AMPL_WIDTH),
conv_std_logic_vector(32428,AMPL_WIDTH),
conv_std_logic_vector(32429,AMPL_WIDTH),
conv_std_logic_vector(32429,AMPL_WIDTH),
conv_std_logic_vector(32430,AMPL_WIDTH),
conv_std_logic_vector(32430,AMPL_WIDTH),
conv_std_logic_vector(32431,AMPL_WIDTH),
conv_std_logic_vector(32431,AMPL_WIDTH),
conv_std_logic_vector(32431,AMPL_WIDTH),
conv_std_logic_vector(32432,AMPL_WIDTH),
conv_std_logic_vector(32432,AMPL_WIDTH),
conv_std_logic_vector(32433,AMPL_WIDTH),
conv_std_logic_vector(32433,AMPL_WIDTH),
conv_std_logic_vector(32434,AMPL_WIDTH),
conv_std_logic_vector(32434,AMPL_WIDTH),
conv_std_logic_vector(32435,AMPL_WIDTH),
conv_std_logic_vector(32435,AMPL_WIDTH),
conv_std_logic_vector(32435,AMPL_WIDTH),
conv_std_logic_vector(32436,AMPL_WIDTH),
conv_std_logic_vector(32436,AMPL_WIDTH),
conv_std_logic_vector(32437,AMPL_WIDTH),
conv_std_logic_vector(32437,AMPL_WIDTH),
conv_std_logic_vector(32438,AMPL_WIDTH),
conv_std_logic_vector(32438,AMPL_WIDTH),
conv_std_logic_vector(32439,AMPL_WIDTH),
conv_std_logic_vector(32439,AMPL_WIDTH),
conv_std_logic_vector(32439,AMPL_WIDTH),
conv_std_logic_vector(32440,AMPL_WIDTH),
conv_std_logic_vector(32440,AMPL_WIDTH),
conv_std_logic_vector(32441,AMPL_WIDTH),
conv_std_logic_vector(32441,AMPL_WIDTH),
conv_std_logic_vector(32442,AMPL_WIDTH),
conv_std_logic_vector(32442,AMPL_WIDTH),
conv_std_logic_vector(32443,AMPL_WIDTH),
conv_std_logic_vector(32443,AMPL_WIDTH),
conv_std_logic_vector(32443,AMPL_WIDTH),
conv_std_logic_vector(32444,AMPL_WIDTH),
conv_std_logic_vector(32444,AMPL_WIDTH),
conv_std_logic_vector(32445,AMPL_WIDTH),
conv_std_logic_vector(32445,AMPL_WIDTH),
conv_std_logic_vector(32446,AMPL_WIDTH),
conv_std_logic_vector(32446,AMPL_WIDTH),
conv_std_logic_vector(32447,AMPL_WIDTH),
conv_std_logic_vector(32447,AMPL_WIDTH),
conv_std_logic_vector(32447,AMPL_WIDTH),
conv_std_logic_vector(32448,AMPL_WIDTH),
conv_std_logic_vector(32448,AMPL_WIDTH),
conv_std_logic_vector(32449,AMPL_WIDTH),
conv_std_logic_vector(32449,AMPL_WIDTH),
conv_std_logic_vector(32450,AMPL_WIDTH),
conv_std_logic_vector(32450,AMPL_WIDTH),
conv_std_logic_vector(32450,AMPL_WIDTH),
conv_std_logic_vector(32451,AMPL_WIDTH),
conv_std_logic_vector(32451,AMPL_WIDTH),
conv_std_logic_vector(32452,AMPL_WIDTH),
conv_std_logic_vector(32452,AMPL_WIDTH),
conv_std_logic_vector(32453,AMPL_WIDTH),
conv_std_logic_vector(32453,AMPL_WIDTH),
conv_std_logic_vector(32453,AMPL_WIDTH),
conv_std_logic_vector(32454,AMPL_WIDTH),
conv_std_logic_vector(32454,AMPL_WIDTH),
conv_std_logic_vector(32455,AMPL_WIDTH),
conv_std_logic_vector(32455,AMPL_WIDTH),
conv_std_logic_vector(32456,AMPL_WIDTH),
conv_std_logic_vector(32456,AMPL_WIDTH),
conv_std_logic_vector(32457,AMPL_WIDTH),
conv_std_logic_vector(32457,AMPL_WIDTH),
conv_std_logic_vector(32457,AMPL_WIDTH),
conv_std_logic_vector(32458,AMPL_WIDTH),
conv_std_logic_vector(32458,AMPL_WIDTH),
conv_std_logic_vector(32459,AMPL_WIDTH),
conv_std_logic_vector(32459,AMPL_WIDTH),
conv_std_logic_vector(32460,AMPL_WIDTH),
conv_std_logic_vector(32460,AMPL_WIDTH),
conv_std_logic_vector(32460,AMPL_WIDTH),
conv_std_logic_vector(32461,AMPL_WIDTH),
conv_std_logic_vector(32461,AMPL_WIDTH),
conv_std_logic_vector(32462,AMPL_WIDTH),
conv_std_logic_vector(32462,AMPL_WIDTH),
conv_std_logic_vector(32463,AMPL_WIDTH),
conv_std_logic_vector(32463,AMPL_WIDTH),
conv_std_logic_vector(32463,AMPL_WIDTH),
conv_std_logic_vector(32464,AMPL_WIDTH),
conv_std_logic_vector(32464,AMPL_WIDTH),
conv_std_logic_vector(32465,AMPL_WIDTH),
conv_std_logic_vector(32465,AMPL_WIDTH),
conv_std_logic_vector(32466,AMPL_WIDTH),
conv_std_logic_vector(32466,AMPL_WIDTH),
conv_std_logic_vector(32466,AMPL_WIDTH),
conv_std_logic_vector(32467,AMPL_WIDTH),
conv_std_logic_vector(32467,AMPL_WIDTH),
conv_std_logic_vector(32468,AMPL_WIDTH),
conv_std_logic_vector(32468,AMPL_WIDTH),
conv_std_logic_vector(32468,AMPL_WIDTH),
conv_std_logic_vector(32469,AMPL_WIDTH),
conv_std_logic_vector(32469,AMPL_WIDTH),
conv_std_logic_vector(32470,AMPL_WIDTH),
conv_std_logic_vector(32470,AMPL_WIDTH),
conv_std_logic_vector(32471,AMPL_WIDTH),
conv_std_logic_vector(32471,AMPL_WIDTH),
conv_std_logic_vector(32471,AMPL_WIDTH),
conv_std_logic_vector(32472,AMPL_WIDTH),
conv_std_logic_vector(32472,AMPL_WIDTH),
conv_std_logic_vector(32473,AMPL_WIDTH),
conv_std_logic_vector(32473,AMPL_WIDTH),
conv_std_logic_vector(32474,AMPL_WIDTH),
conv_std_logic_vector(32474,AMPL_WIDTH),
conv_std_logic_vector(32474,AMPL_WIDTH),
conv_std_logic_vector(32475,AMPL_WIDTH),
conv_std_logic_vector(32475,AMPL_WIDTH),
conv_std_logic_vector(32476,AMPL_WIDTH),
conv_std_logic_vector(32476,AMPL_WIDTH),
conv_std_logic_vector(32476,AMPL_WIDTH),
conv_std_logic_vector(32477,AMPL_WIDTH),
conv_std_logic_vector(32477,AMPL_WIDTH),
conv_std_logic_vector(32478,AMPL_WIDTH),
conv_std_logic_vector(32478,AMPL_WIDTH),
conv_std_logic_vector(32479,AMPL_WIDTH),
conv_std_logic_vector(32479,AMPL_WIDTH),
conv_std_logic_vector(32479,AMPL_WIDTH),
conv_std_logic_vector(32480,AMPL_WIDTH),
conv_std_logic_vector(32480,AMPL_WIDTH),
conv_std_logic_vector(32481,AMPL_WIDTH),
conv_std_logic_vector(32481,AMPL_WIDTH),
conv_std_logic_vector(32481,AMPL_WIDTH),
conv_std_logic_vector(32482,AMPL_WIDTH),
conv_std_logic_vector(32482,AMPL_WIDTH),
conv_std_logic_vector(32483,AMPL_WIDTH),
conv_std_logic_vector(32483,AMPL_WIDTH),
conv_std_logic_vector(32484,AMPL_WIDTH),
conv_std_logic_vector(32484,AMPL_WIDTH),
conv_std_logic_vector(32484,AMPL_WIDTH),
conv_std_logic_vector(32485,AMPL_WIDTH),
conv_std_logic_vector(32485,AMPL_WIDTH),
conv_std_logic_vector(32486,AMPL_WIDTH),
conv_std_logic_vector(32486,AMPL_WIDTH),
conv_std_logic_vector(32486,AMPL_WIDTH),
conv_std_logic_vector(32487,AMPL_WIDTH),
conv_std_logic_vector(32487,AMPL_WIDTH),
conv_std_logic_vector(32488,AMPL_WIDTH),
conv_std_logic_vector(32488,AMPL_WIDTH),
conv_std_logic_vector(32488,AMPL_WIDTH),
conv_std_logic_vector(32489,AMPL_WIDTH),
conv_std_logic_vector(32489,AMPL_WIDTH),
conv_std_logic_vector(32490,AMPL_WIDTH),
conv_std_logic_vector(32490,AMPL_WIDTH),
conv_std_logic_vector(32490,AMPL_WIDTH),
conv_std_logic_vector(32491,AMPL_WIDTH),
conv_std_logic_vector(32491,AMPL_WIDTH),
conv_std_logic_vector(32492,AMPL_WIDTH),
conv_std_logic_vector(32492,AMPL_WIDTH),
conv_std_logic_vector(32493,AMPL_WIDTH),
conv_std_logic_vector(32493,AMPL_WIDTH),
conv_std_logic_vector(32493,AMPL_WIDTH),
conv_std_logic_vector(32494,AMPL_WIDTH),
conv_std_logic_vector(32494,AMPL_WIDTH),
conv_std_logic_vector(32495,AMPL_WIDTH),
conv_std_logic_vector(32495,AMPL_WIDTH),
conv_std_logic_vector(32495,AMPL_WIDTH),
conv_std_logic_vector(32496,AMPL_WIDTH),
conv_std_logic_vector(32496,AMPL_WIDTH),
conv_std_logic_vector(32497,AMPL_WIDTH),
conv_std_logic_vector(32497,AMPL_WIDTH),
conv_std_logic_vector(32497,AMPL_WIDTH),
conv_std_logic_vector(32498,AMPL_WIDTH),
conv_std_logic_vector(32498,AMPL_WIDTH),
conv_std_logic_vector(32499,AMPL_WIDTH),
conv_std_logic_vector(32499,AMPL_WIDTH),
conv_std_logic_vector(32499,AMPL_WIDTH),
conv_std_logic_vector(32500,AMPL_WIDTH),
conv_std_logic_vector(32500,AMPL_WIDTH),
conv_std_logic_vector(32501,AMPL_WIDTH),
conv_std_logic_vector(32501,AMPL_WIDTH),
conv_std_logic_vector(32501,AMPL_WIDTH),
conv_std_logic_vector(32502,AMPL_WIDTH),
conv_std_logic_vector(32502,AMPL_WIDTH),
conv_std_logic_vector(32503,AMPL_WIDTH),
conv_std_logic_vector(32503,AMPL_WIDTH),
conv_std_logic_vector(32503,AMPL_WIDTH),
conv_std_logic_vector(32504,AMPL_WIDTH),
conv_std_logic_vector(32504,AMPL_WIDTH),
conv_std_logic_vector(32505,AMPL_WIDTH),
conv_std_logic_vector(32505,AMPL_WIDTH),
conv_std_logic_vector(32505,AMPL_WIDTH),
conv_std_logic_vector(32506,AMPL_WIDTH),
conv_std_logic_vector(32506,AMPL_WIDTH),
conv_std_logic_vector(32507,AMPL_WIDTH),
conv_std_logic_vector(32507,AMPL_WIDTH),
conv_std_logic_vector(32507,AMPL_WIDTH),
conv_std_logic_vector(32508,AMPL_WIDTH),
conv_std_logic_vector(32508,AMPL_WIDTH),
conv_std_logic_vector(32509,AMPL_WIDTH),
conv_std_logic_vector(32509,AMPL_WIDTH),
conv_std_logic_vector(32509,AMPL_WIDTH),
conv_std_logic_vector(32510,AMPL_WIDTH),
conv_std_logic_vector(32510,AMPL_WIDTH),
conv_std_logic_vector(32510,AMPL_WIDTH),
conv_std_logic_vector(32511,AMPL_WIDTH),
conv_std_logic_vector(32511,AMPL_WIDTH),
conv_std_logic_vector(32512,AMPL_WIDTH),
conv_std_logic_vector(32512,AMPL_WIDTH),
conv_std_logic_vector(32512,AMPL_WIDTH),
conv_std_logic_vector(32513,AMPL_WIDTH),
conv_std_logic_vector(32513,AMPL_WIDTH),
conv_std_logic_vector(32514,AMPL_WIDTH),
conv_std_logic_vector(32514,AMPL_WIDTH),
conv_std_logic_vector(32514,AMPL_WIDTH),
conv_std_logic_vector(32515,AMPL_WIDTH),
conv_std_logic_vector(32515,AMPL_WIDTH),
conv_std_logic_vector(32516,AMPL_WIDTH),
conv_std_logic_vector(32516,AMPL_WIDTH),
conv_std_logic_vector(32516,AMPL_WIDTH),
conv_std_logic_vector(32517,AMPL_WIDTH),
conv_std_logic_vector(32517,AMPL_WIDTH),
conv_std_logic_vector(32517,AMPL_WIDTH),
conv_std_logic_vector(32518,AMPL_WIDTH),
conv_std_logic_vector(32518,AMPL_WIDTH),
conv_std_logic_vector(32519,AMPL_WIDTH),
conv_std_logic_vector(32519,AMPL_WIDTH),
conv_std_logic_vector(32519,AMPL_WIDTH),
conv_std_logic_vector(32520,AMPL_WIDTH),
conv_std_logic_vector(32520,AMPL_WIDTH),
conv_std_logic_vector(32521,AMPL_WIDTH),
conv_std_logic_vector(32521,AMPL_WIDTH),
conv_std_logic_vector(32521,AMPL_WIDTH),
conv_std_logic_vector(32522,AMPL_WIDTH),
conv_std_logic_vector(32522,AMPL_WIDTH),
conv_std_logic_vector(32522,AMPL_WIDTH),
conv_std_logic_vector(32523,AMPL_WIDTH),
conv_std_logic_vector(32523,AMPL_WIDTH),
conv_std_logic_vector(32524,AMPL_WIDTH),
conv_std_logic_vector(32524,AMPL_WIDTH),
conv_std_logic_vector(32524,AMPL_WIDTH),
conv_std_logic_vector(32525,AMPL_WIDTH),
conv_std_logic_vector(32525,AMPL_WIDTH),
conv_std_logic_vector(32526,AMPL_WIDTH),
conv_std_logic_vector(32526,AMPL_WIDTH),
conv_std_logic_vector(32526,AMPL_WIDTH),
conv_std_logic_vector(32527,AMPL_WIDTH),
conv_std_logic_vector(32527,AMPL_WIDTH),
conv_std_logic_vector(32527,AMPL_WIDTH),
conv_std_logic_vector(32528,AMPL_WIDTH),
conv_std_logic_vector(32528,AMPL_WIDTH),
conv_std_logic_vector(32529,AMPL_WIDTH),
conv_std_logic_vector(32529,AMPL_WIDTH),
conv_std_logic_vector(32529,AMPL_WIDTH),
conv_std_logic_vector(32530,AMPL_WIDTH),
conv_std_logic_vector(32530,AMPL_WIDTH),
conv_std_logic_vector(32530,AMPL_WIDTH),
conv_std_logic_vector(32531,AMPL_WIDTH),
conv_std_logic_vector(32531,AMPL_WIDTH),
conv_std_logic_vector(32532,AMPL_WIDTH),
conv_std_logic_vector(32532,AMPL_WIDTH),
conv_std_logic_vector(32532,AMPL_WIDTH),
conv_std_logic_vector(32533,AMPL_WIDTH),
conv_std_logic_vector(32533,AMPL_WIDTH),
conv_std_logic_vector(32533,AMPL_WIDTH),
conv_std_logic_vector(32534,AMPL_WIDTH),
conv_std_logic_vector(32534,AMPL_WIDTH),
conv_std_logic_vector(32535,AMPL_WIDTH),
conv_std_logic_vector(32535,AMPL_WIDTH),
conv_std_logic_vector(32535,AMPL_WIDTH),
conv_std_logic_vector(32536,AMPL_WIDTH),
conv_std_logic_vector(32536,AMPL_WIDTH),
conv_std_logic_vector(32536,AMPL_WIDTH),
conv_std_logic_vector(32537,AMPL_WIDTH),
conv_std_logic_vector(32537,AMPL_WIDTH),
conv_std_logic_vector(32538,AMPL_WIDTH),
conv_std_logic_vector(32538,AMPL_WIDTH),
conv_std_logic_vector(32538,AMPL_WIDTH),
conv_std_logic_vector(32539,AMPL_WIDTH),
conv_std_logic_vector(32539,AMPL_WIDTH),
conv_std_logic_vector(32539,AMPL_WIDTH),
conv_std_logic_vector(32540,AMPL_WIDTH),
conv_std_logic_vector(32540,AMPL_WIDTH),
conv_std_logic_vector(32541,AMPL_WIDTH),
conv_std_logic_vector(32541,AMPL_WIDTH),
conv_std_logic_vector(32541,AMPL_WIDTH),
conv_std_logic_vector(32542,AMPL_WIDTH),
conv_std_logic_vector(32542,AMPL_WIDTH),
conv_std_logic_vector(32542,AMPL_WIDTH),
conv_std_logic_vector(32543,AMPL_WIDTH),
conv_std_logic_vector(32543,AMPL_WIDTH),
conv_std_logic_vector(32543,AMPL_WIDTH),
conv_std_logic_vector(32544,AMPL_WIDTH),
conv_std_logic_vector(32544,AMPL_WIDTH),
conv_std_logic_vector(32545,AMPL_WIDTH),
conv_std_logic_vector(32545,AMPL_WIDTH),
conv_std_logic_vector(32545,AMPL_WIDTH),
conv_std_logic_vector(32546,AMPL_WIDTH),
conv_std_logic_vector(32546,AMPL_WIDTH),
conv_std_logic_vector(32546,AMPL_WIDTH),
conv_std_logic_vector(32547,AMPL_WIDTH),
conv_std_logic_vector(32547,AMPL_WIDTH),
conv_std_logic_vector(32547,AMPL_WIDTH),
conv_std_logic_vector(32548,AMPL_WIDTH),
conv_std_logic_vector(32548,AMPL_WIDTH),
conv_std_logic_vector(32549,AMPL_WIDTH),
conv_std_logic_vector(32549,AMPL_WIDTH),
conv_std_logic_vector(32549,AMPL_WIDTH),
conv_std_logic_vector(32550,AMPL_WIDTH),
conv_std_logic_vector(32550,AMPL_WIDTH),
conv_std_logic_vector(32550,AMPL_WIDTH),
conv_std_logic_vector(32551,AMPL_WIDTH),
conv_std_logic_vector(32551,AMPL_WIDTH),
conv_std_logic_vector(32551,AMPL_WIDTH),
conv_std_logic_vector(32552,AMPL_WIDTH),
conv_std_logic_vector(32552,AMPL_WIDTH),
conv_std_logic_vector(32553,AMPL_WIDTH),
conv_std_logic_vector(32553,AMPL_WIDTH),
conv_std_logic_vector(32553,AMPL_WIDTH),
conv_std_logic_vector(32554,AMPL_WIDTH),
conv_std_logic_vector(32554,AMPL_WIDTH),
conv_std_logic_vector(32554,AMPL_WIDTH),
conv_std_logic_vector(32555,AMPL_WIDTH),
conv_std_logic_vector(32555,AMPL_WIDTH),
conv_std_logic_vector(32555,AMPL_WIDTH),
conv_std_logic_vector(32556,AMPL_WIDTH),
conv_std_logic_vector(32556,AMPL_WIDTH),
conv_std_logic_vector(32556,AMPL_WIDTH),
conv_std_logic_vector(32557,AMPL_WIDTH),
conv_std_logic_vector(32557,AMPL_WIDTH),
conv_std_logic_vector(32558,AMPL_WIDTH),
conv_std_logic_vector(32558,AMPL_WIDTH),
conv_std_logic_vector(32558,AMPL_WIDTH),
conv_std_logic_vector(32559,AMPL_WIDTH),
conv_std_logic_vector(32559,AMPL_WIDTH),
conv_std_logic_vector(32559,AMPL_WIDTH),
conv_std_logic_vector(32560,AMPL_WIDTH),
conv_std_logic_vector(32560,AMPL_WIDTH),
conv_std_logic_vector(32560,AMPL_WIDTH),
conv_std_logic_vector(32561,AMPL_WIDTH),
conv_std_logic_vector(32561,AMPL_WIDTH),
conv_std_logic_vector(32561,AMPL_WIDTH),
conv_std_logic_vector(32562,AMPL_WIDTH),
conv_std_logic_vector(32562,AMPL_WIDTH),
conv_std_logic_vector(32562,AMPL_WIDTH),
conv_std_logic_vector(32563,AMPL_WIDTH),
conv_std_logic_vector(32563,AMPL_WIDTH),
conv_std_logic_vector(32564,AMPL_WIDTH),
conv_std_logic_vector(32564,AMPL_WIDTH),
conv_std_logic_vector(32564,AMPL_WIDTH),
conv_std_logic_vector(32565,AMPL_WIDTH),
conv_std_logic_vector(32565,AMPL_WIDTH),
conv_std_logic_vector(32565,AMPL_WIDTH),
conv_std_logic_vector(32566,AMPL_WIDTH),
conv_std_logic_vector(32566,AMPL_WIDTH),
conv_std_logic_vector(32566,AMPL_WIDTH),
conv_std_logic_vector(32567,AMPL_WIDTH),
conv_std_logic_vector(32567,AMPL_WIDTH),
conv_std_logic_vector(32567,AMPL_WIDTH),
conv_std_logic_vector(32568,AMPL_WIDTH),
conv_std_logic_vector(32568,AMPL_WIDTH),
conv_std_logic_vector(32568,AMPL_WIDTH),
conv_std_logic_vector(32569,AMPL_WIDTH),
conv_std_logic_vector(32569,AMPL_WIDTH),
conv_std_logic_vector(32569,AMPL_WIDTH),
conv_std_logic_vector(32570,AMPL_WIDTH),
conv_std_logic_vector(32570,AMPL_WIDTH),
conv_std_logic_vector(32570,AMPL_WIDTH),
conv_std_logic_vector(32571,AMPL_WIDTH),
conv_std_logic_vector(32571,AMPL_WIDTH),
conv_std_logic_vector(32571,AMPL_WIDTH),
conv_std_logic_vector(32572,AMPL_WIDTH),
conv_std_logic_vector(32572,AMPL_WIDTH),
conv_std_logic_vector(32573,AMPL_WIDTH),
conv_std_logic_vector(32573,AMPL_WIDTH),
conv_std_logic_vector(32573,AMPL_WIDTH),
conv_std_logic_vector(32574,AMPL_WIDTH),
conv_std_logic_vector(32574,AMPL_WIDTH),
conv_std_logic_vector(32574,AMPL_WIDTH),
conv_std_logic_vector(32575,AMPL_WIDTH),
conv_std_logic_vector(32575,AMPL_WIDTH),
conv_std_logic_vector(32575,AMPL_WIDTH),
conv_std_logic_vector(32576,AMPL_WIDTH),
conv_std_logic_vector(32576,AMPL_WIDTH),
conv_std_logic_vector(32576,AMPL_WIDTH),
conv_std_logic_vector(32577,AMPL_WIDTH),
conv_std_logic_vector(32577,AMPL_WIDTH),
conv_std_logic_vector(32577,AMPL_WIDTH),
conv_std_logic_vector(32578,AMPL_WIDTH),
conv_std_logic_vector(32578,AMPL_WIDTH),
conv_std_logic_vector(32578,AMPL_WIDTH),
conv_std_logic_vector(32579,AMPL_WIDTH),
conv_std_logic_vector(32579,AMPL_WIDTH),
conv_std_logic_vector(32579,AMPL_WIDTH),
conv_std_logic_vector(32580,AMPL_WIDTH),
conv_std_logic_vector(32580,AMPL_WIDTH),
conv_std_logic_vector(32580,AMPL_WIDTH),
conv_std_logic_vector(32581,AMPL_WIDTH),
conv_std_logic_vector(32581,AMPL_WIDTH),
conv_std_logic_vector(32581,AMPL_WIDTH),
conv_std_logic_vector(32582,AMPL_WIDTH),
conv_std_logic_vector(32582,AMPL_WIDTH),
conv_std_logic_vector(32582,AMPL_WIDTH),
conv_std_logic_vector(32583,AMPL_WIDTH),
conv_std_logic_vector(32583,AMPL_WIDTH),
conv_std_logic_vector(32583,AMPL_WIDTH),
conv_std_logic_vector(32584,AMPL_WIDTH),
conv_std_logic_vector(32584,AMPL_WIDTH),
conv_std_logic_vector(32584,AMPL_WIDTH),
conv_std_logic_vector(32585,AMPL_WIDTH),
conv_std_logic_vector(32585,AMPL_WIDTH),
conv_std_logic_vector(32585,AMPL_WIDTH),
conv_std_logic_vector(32586,AMPL_WIDTH),
conv_std_logic_vector(32586,AMPL_WIDTH),
conv_std_logic_vector(32586,AMPL_WIDTH),
conv_std_logic_vector(32587,AMPL_WIDTH),
conv_std_logic_vector(32587,AMPL_WIDTH),
conv_std_logic_vector(32587,AMPL_WIDTH),
conv_std_logic_vector(32588,AMPL_WIDTH),
conv_std_logic_vector(32588,AMPL_WIDTH),
conv_std_logic_vector(32588,AMPL_WIDTH),
conv_std_logic_vector(32589,AMPL_WIDTH),
conv_std_logic_vector(32589,AMPL_WIDTH),
conv_std_logic_vector(32589,AMPL_WIDTH),
conv_std_logic_vector(32590,AMPL_WIDTH),
conv_std_logic_vector(32590,AMPL_WIDTH),
conv_std_logic_vector(32590,AMPL_WIDTH),
conv_std_logic_vector(32591,AMPL_WIDTH),
conv_std_logic_vector(32591,AMPL_WIDTH),
conv_std_logic_vector(32591,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32592,AMPL_WIDTH),
conv_std_logic_vector(32593,AMPL_WIDTH),
conv_std_logic_vector(32593,AMPL_WIDTH),
conv_std_logic_vector(32593,AMPL_WIDTH),
conv_std_logic_vector(32594,AMPL_WIDTH),
conv_std_logic_vector(32594,AMPL_WIDTH),
conv_std_logic_vector(32594,AMPL_WIDTH),
conv_std_logic_vector(32595,AMPL_WIDTH),
conv_std_logic_vector(32595,AMPL_WIDTH),
conv_std_logic_vector(32595,AMPL_WIDTH),
conv_std_logic_vector(32596,AMPL_WIDTH),
conv_std_logic_vector(32596,AMPL_WIDTH),
conv_std_logic_vector(32596,AMPL_WIDTH),
conv_std_logic_vector(32597,AMPL_WIDTH),
conv_std_logic_vector(32597,AMPL_WIDTH),
conv_std_logic_vector(32597,AMPL_WIDTH),
conv_std_logic_vector(32598,AMPL_WIDTH),
conv_std_logic_vector(32598,AMPL_WIDTH),
conv_std_logic_vector(32598,AMPL_WIDTH),
conv_std_logic_vector(32599,AMPL_WIDTH),
conv_std_logic_vector(32599,AMPL_WIDTH),
conv_std_logic_vector(32599,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32600,AMPL_WIDTH),
conv_std_logic_vector(32601,AMPL_WIDTH),
conv_std_logic_vector(32601,AMPL_WIDTH),
conv_std_logic_vector(32601,AMPL_WIDTH),
conv_std_logic_vector(32602,AMPL_WIDTH),
conv_std_logic_vector(32602,AMPL_WIDTH),
conv_std_logic_vector(32602,AMPL_WIDTH),
conv_std_logic_vector(32603,AMPL_WIDTH),
conv_std_logic_vector(32603,AMPL_WIDTH),
conv_std_logic_vector(32603,AMPL_WIDTH),
conv_std_logic_vector(32604,AMPL_WIDTH),
conv_std_logic_vector(32604,AMPL_WIDTH),
conv_std_logic_vector(32604,AMPL_WIDTH),
conv_std_logic_vector(32605,AMPL_WIDTH),
conv_std_logic_vector(32605,AMPL_WIDTH),
conv_std_logic_vector(32605,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32606,AMPL_WIDTH),
conv_std_logic_vector(32607,AMPL_WIDTH),
conv_std_logic_vector(32607,AMPL_WIDTH),
conv_std_logic_vector(32607,AMPL_WIDTH),
conv_std_logic_vector(32608,AMPL_WIDTH),
conv_std_logic_vector(32608,AMPL_WIDTH),
conv_std_logic_vector(32608,AMPL_WIDTH),
conv_std_logic_vector(32609,AMPL_WIDTH),
conv_std_logic_vector(32609,AMPL_WIDTH),
conv_std_logic_vector(32609,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32610,AMPL_WIDTH),
conv_std_logic_vector(32611,AMPL_WIDTH),
conv_std_logic_vector(32611,AMPL_WIDTH),
conv_std_logic_vector(32611,AMPL_WIDTH),
conv_std_logic_vector(32612,AMPL_WIDTH),
conv_std_logic_vector(32612,AMPL_WIDTH),
conv_std_logic_vector(32612,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32613,AMPL_WIDTH),
conv_std_logic_vector(32614,AMPL_WIDTH),
conv_std_logic_vector(32614,AMPL_WIDTH),
conv_std_logic_vector(32614,AMPL_WIDTH),
conv_std_logic_vector(32615,AMPL_WIDTH),
conv_std_logic_vector(32615,AMPL_WIDTH),
conv_std_logic_vector(32615,AMPL_WIDTH),
conv_std_logic_vector(32616,AMPL_WIDTH),
conv_std_logic_vector(32616,AMPL_WIDTH),
conv_std_logic_vector(32616,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32617,AMPL_WIDTH),
conv_std_logic_vector(32618,AMPL_WIDTH),
conv_std_logic_vector(32618,AMPL_WIDTH),
conv_std_logic_vector(32618,AMPL_WIDTH),
conv_std_logic_vector(32619,AMPL_WIDTH),
conv_std_logic_vector(32619,AMPL_WIDTH),
conv_std_logic_vector(32619,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32620,AMPL_WIDTH),
conv_std_logic_vector(32621,AMPL_WIDTH),
conv_std_logic_vector(32621,AMPL_WIDTH),
conv_std_logic_vector(32621,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32622,AMPL_WIDTH),
conv_std_logic_vector(32623,AMPL_WIDTH),
conv_std_logic_vector(32623,AMPL_WIDTH),
conv_std_logic_vector(32623,AMPL_WIDTH),
conv_std_logic_vector(32624,AMPL_WIDTH),
conv_std_logic_vector(32624,AMPL_WIDTH),
conv_std_logic_vector(32624,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32625,AMPL_WIDTH),
conv_std_logic_vector(32626,AMPL_WIDTH),
conv_std_logic_vector(32626,AMPL_WIDTH),
conv_std_logic_vector(32626,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32627,AMPL_WIDTH),
conv_std_logic_vector(32628,AMPL_WIDTH),
conv_std_logic_vector(32628,AMPL_WIDTH),
conv_std_logic_vector(32628,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32629,AMPL_WIDTH),
conv_std_logic_vector(32630,AMPL_WIDTH),
conv_std_logic_vector(32630,AMPL_WIDTH),
conv_std_logic_vector(32630,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32631,AMPL_WIDTH),
conv_std_logic_vector(32632,AMPL_WIDTH),
conv_std_logic_vector(32632,AMPL_WIDTH),
conv_std_logic_vector(32632,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32633,AMPL_WIDTH),
conv_std_logic_vector(32634,AMPL_WIDTH),
conv_std_logic_vector(32634,AMPL_WIDTH),
conv_std_logic_vector(32634,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32635,AMPL_WIDTH),
conv_std_logic_vector(32636,AMPL_WIDTH),
conv_std_logic_vector(32636,AMPL_WIDTH),
conv_std_logic_vector(32636,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32637,AMPL_WIDTH),
conv_std_logic_vector(32638,AMPL_WIDTH),
conv_std_logic_vector(32638,AMPL_WIDTH),
conv_std_logic_vector(32638,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32639,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32640,AMPL_WIDTH),
conv_std_logic_vector(32641,AMPL_WIDTH),
conv_std_logic_vector(32641,AMPL_WIDTH),
conv_std_logic_vector(32641,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32642,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32643,AMPL_WIDTH),
conv_std_logic_vector(32644,AMPL_WIDTH),
conv_std_logic_vector(32644,AMPL_WIDTH),
conv_std_logic_vector(32644,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32645,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32646,AMPL_WIDTH),
conv_std_logic_vector(32647,AMPL_WIDTH),
conv_std_logic_vector(32647,AMPL_WIDTH),
conv_std_logic_vector(32647,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32648,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32649,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32650,AMPL_WIDTH),
conv_std_logic_vector(32651,AMPL_WIDTH),
conv_std_logic_vector(32651,AMPL_WIDTH),
conv_std_logic_vector(32651,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32652,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32653,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32654,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32655,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32656,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32657,AMPL_WIDTH),
conv_std_logic_vector(32658,AMPL_WIDTH),
conv_std_logic_vector(32658,AMPL_WIDTH),
conv_std_logic_vector(32658,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32659,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32660,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32661,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32662,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32663,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32664,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32665,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32666,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32667,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32668,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32669,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32670,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32671,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32672,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32673,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32674,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32675,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32676,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32677,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32678,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32679,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32680,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32681,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32682,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32683,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32684,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32685,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32686,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32687,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32688,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32689,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32690,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32691,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32692,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32693,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32694,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32695,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32696,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32697,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32698,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32699,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32700,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32701,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32702,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32703,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32704,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32705,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32706,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32707,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32708,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32709,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32710,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32711,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32712,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32713,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32714,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32715,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32716,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32717,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32718,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32719,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32720,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32721,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32722,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32723,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32724,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32725,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32726,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32727,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32728,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32729,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32730,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32731,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32732,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32733,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32734,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32735,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32736,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32737,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32738,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32739,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32740,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32741,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32742,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32743,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32744,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32745,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32746,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32747,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32748,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32749,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32750,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32751,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32752,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32753,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32754,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32755,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32756,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32757,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32758,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32759,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32760,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32761,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32762,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32763,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32764,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32765,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32766,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH),
conv_std_logic_vector(32767,AMPL_WIDTH)
);
end sine_lut_pkg;
package body sine_lut_pkg is
end sine_lut_pkg; |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL18USUS.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 18 ***
--*** bit multiplier ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul18usus IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END hcc_mul18usus;
ARCHITECTURE SYN OF hcc_mul18usus IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(35 DOWNTO 0);
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => dataa_0,
datab => datab_0,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity korvet is
Port (
CLK50 : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
SOUND_L : out std_logic;
SOUND_R : out std_logic;
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_D : inout std_logic_vector(15 downto 0);
SRAM_WE : out std_logic;
SRAM_OE : out std_logic;
SRAM_CS : out std_logic;
SRAM_LB : out std_logic;
SRAM_UB : out std_logic;
COMM_CSA : in std_logic;
COMM_CSD : in std_logic;
COMM_SCK : in std_logic;
COMM_MOSI : in std_logic;
COMM_MISO : out std_logic;
COMM_REQ : out std_logic;
VGA_R : out std_logic_vector(3 downto 0);
VGA_G : out std_logic_vector(3 downto 0);
VGA_B : out std_logic_vector(3 downto 0);
VGA_HSYNC : out std_logic;
VGA_VSYNC : out std_logic );
end korvet;
architecture RTL of korvet is
-- Verilog Modules
----------------------------------------------------------
component k580wm80a is
port(
clk : in std_logic;
ce : in std_logic;
reset : in std_logic;
intr : in std_logic;
idata : in std_logic_vector(7 downto 0);
addr : out std_logic_vector(15 downto 0);
sync : out std_logic;
rd : out std_logic;
wr : out std_logic;
inta : out std_logic;
odata : out std_logic_vector(7 downto 0) );
end component;
-- component cpu8080 is
-- port(
-- addr : out std_logic_vector(15 downto 0);
-- data : in std_logic_vector(7 downto 0);
-- datao : out std_logic_vector(7 downto 0);
-- readmem : out std_logic;
-- writemem : out std_logic;
-- readio : out std_logic;
-- writeio : out std_logic;
-- intr : in std_logic;
-- inta : out std_logic;
-- waitr : in std_logic;
-- reset : in std_logic;
-- cke : in std_logic;
-- clock : in std_logic );
-- end component;
component k580wi53 is
port(
clk : in std_logic;
c0 : in std_logic;
c1 : in std_logic;
c2 : in std_logic;
g0 : in std_logic;
g1 : in std_logic;
g2 : in std_logic;
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
addr : in std_logic_vector(1 downto 0);
rd : in std_logic;
we_n : in std_logic;
idata : in std_logic_vector(7 downto 0);
odata : out std_logic_vector(7 downto 0) );
end component;
-- Memory Mapper Values -------------------------------------
constant M_RAM : std_logic_vector(2 downto 0) := "000";
constant M_ROM : std_logic_vector(2 downto 0) := "001";
constant M_KEYBOARD : std_logic_vector(2 downto 0) := "010";
constant M_PORTBASE : std_logic_vector(2 downto 0) := "011";
constant M_REGBASE : std_logic_vector(2 downto 0) := "100";
constant M_CGRAM : std_logic_vector(2 downto 0) := "101";
constant M_VRAM : std_logic_vector(2 downto 0) := "110";
-------------------------------------------------------------
signal CLK : std_logic;
signal RESET : std_logic := '1';
signal TICK : unsigned(3 downto 0);
signal TICK2_0 : unsigned(1 downto 0);
signal TICK2_1 : unsigned(4 downto 0);
signal CPU_PAUSE : std_logic;
signal CPU_RESET : std_logic;
signal CPU_CLK : std_logic;
signal CPU_INTA : std_logic;
signal CPU_INTR : std_logic;
signal CPU_RD : std_logic;
signal CPU_SYNC : std_logic;
signal CPU_WR : std_logic;
signal CPU_A : std_logic_vector(15 downto 0);
signal CPU_DI : std_logic_vector(7 downto 0);
signal CPU_DO : std_logic_vector(7 downto 0);
signal MAPPER_DO : std_logic_vector(2 downto 0);
signal KEYBOARD_DO : std_logic_vector(7 downto 0);
signal SYSREG : std_logic_vector(4 downto 0);
signal COLORREG : std_logic_vector(7 downto 0);
signal KB_SG_RESET : std_logic;
signal CHRAM_WR : std_logic;
signal CHRAM_DO : std_logic_vector(8 downto 0);
signal CHRAM_VA : std_logic_vector(9 downto 0);
signal CHRAM_VD : std_logic_vector(8 downto 0);
signal PPI1_WR : std_logic;
signal PPI1_DO : std_logic_vector(7 downto 0);
signal PPI1_PAI : std_logic_vector(7 downto 0);
signal PPI1_PAO : std_logic_vector(7 downto 0);
signal PPI1_PBI : std_logic_vector(7 downto 0);
signal PPI1_PBO : std_logic_vector(7 downto 0);
signal PPI1_PCI : std_logic_vector(7 downto 0);
signal PPI1_PCO : std_logic_vector(7 downto 0);
signal PPI2_WR : std_logic;
signal PPI2_DO : std_logic_vector(7 downto 0);
signal PPI2_PAI : std_logic_vector(7 downto 0);
signal PPI2_PAO : std_logic_vector(7 downto 0);
signal PPI2_PBI : std_logic_vector(7 downto 0);
signal PPI2_PBO : std_logic_vector(7 downto 0);
signal PPI2_PCI : std_logic_vector(7 downto 0);
signal PPI2_PCO : std_logic_vector(7 downto 0);
signal PPI3_WR : std_logic;
signal PPI3_DO : std_logic_vector(7 downto 0);
signal PPI3_PAI : std_logic_vector(7 downto 0);
signal PPI3_PAO : std_logic_vector(7 downto 0);
signal PPI3_PBI : std_logic_vector(7 downto 0);
signal PPI3_PBO : std_logic_vector(7 downto 0);
signal PPI3_PCI : std_logic_vector(7 downto 0);
signal PPI3_PCO : std_logic_vector(7 downto 0);
signal PIC_WR : std_logic;
signal PIC_DO : std_logic_vector(7 downto 0);
signal TIMER_RD : std_logic;
signal TIMER_WR : std_logic;
signal TIMER_DO : std_logic_vector(7 downto 0);
signal TIMER_C0 : std_logic;
signal TIMER_OUT0 : std_logic;
signal CDI : std_logic;
signal CDO : std_logic;
signal VBLANK : std_logic;
signal VBLANK_2 : std_logic;
signal VBLANK_TICK : unsigned(3 downto 0);
signal DRIVE : std_logic_vector(1 downto 0);
alias FLOPPY_SIDE : std_logic is PPI1_PBO(4);
alias DRV_SEL : std_logic_vector(3 downto 0) is PPI1_PBO(3 downto 0);
alias VRAM_PAGE : std_logic_vector(1 downto 0) is PPI1_PCO(7 downto 6);
alias INVON : std_logic is PPI1_PCO(5);
alias INVOFF : std_logic is PPI1_PCO(4);
alias WIDEFONT : std_logic is PPI1_PCO(3);
alias ALTFONT : std_logic is PPI1_PCO(2);
alias VIEW_PAGE : std_logic_vector(1 downto 0) is PPI1_PCO(1 downto 0);
alias TAPE_OUT0 : std_logic is PPI2_PCO(0);
alias TAPE_OUT1 : std_logic is PPI2_PCO(1);
alias SOUND_EN : std_logic is PPI2_PCO(3);
signal RAM_DO : std_logic_vector(7 downto 0);
signal ROM_DO : std_logic_vector(7 downto 0);
signal VRAM_DO : std_logic_vector(7 downto 0);
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal LUT_A : std_logic_vector(3 downto 0);
signal LUT_D : std_logic_vector(3 downto 0);
signal FONTROM_A : std_logic_vector(11 downto 0);
signal FONTROM_DO : std_logic_vector(7 downto 0);
signal CACHE_AI : std_logic_vector(5 downto 0);
signal CACHE_DI : std_logic_vector(31 downto 0);
signal CACHE_WE : std_logic;
signal CACHE_AO : std_logic_vector(5 downto 0);
signal CACHE_DO : std_logic_vector(31 downto 0);
signal CACHE_SWAP : std_logic;
signal CACHE_CNT : unsigned(5 downto 0);
signal CACHE_RD : std_logic;
signal PLANE0 : std_logic_vector(7 downto 0); -- PLANEs - temporary data from VRAM for write to cache and read/write VRAM
signal PLANE1 : std_logic_vector(7 downto 0);
signal PLANE2 : std_logic_vector(7 downto 0);
signal SCANLINE : std_logic_vector(7 downto 0);
signal SOUND : std_logic;
-- signal SOUND_L : std_logic_vector(15 downto 0);
-- signal SOUND_R : std_logic_vector(15 downto 0);
signal TAPE_IN : std_logic;
signal FLOPPY_DO : std_logic_vector(7 downto 0);
signal PAUSE_ONESHOT : std_logic;
signal COMM_ADDR_O : std_logic_vector(7 downto 0);
signal COMM_ADDR_I : std_logic_vector(7 downto 0);
signal COMM_ADDR_REQ : std_logic;
signal COMM_ADDR_ACK : std_logic;
signal COMM_DATA_O : std_logic_vector(7 downto 0);
signal COMM_DATA_I : std_logic_vector(7 downto 0);
signal COMM_DATA_REQ : std_logic;
signal COMM_DATA_ACK : std_logic;
type LUT_T is array (0 to 15) of std_logic_vector(3 downto 0);
signal LUT : LUT_T;
-- Memory Controller Statemachine
type STATE_TYPE is (ST_IDLE, ST_RAMREAD, ST_RAMWRITE1, ST_RAMWRITE2, ST_CACHEREAD1, ST_CACHEREAD2, ST_CACHEREAD3, ST_CACHEREAD4,
ST_VRAMREAD1, ST_VRAMREAD2, ST_VRAMREAD3, ST_VRAMREAD4, ST_VRAMREAD5,
ST_VRAMWRITE1, ST_VRAMWRITE2, ST_VRAMWRITE3, ST_VRAMWRITE4, ST_VRAMWRITE5, ST_VRAMWRITE6, ST_VRAMWRITE7, ST_VRAMWRITE8,
ST_FLOPPY1, ST_FLOPPY2, ST_FLOPPY3 );
signal STATE : STATE_TYPE := ST_IDLE;
signal NSTATE : STATE_TYPE := ST_IDLE;
begin
-- PLL Make 32.5MHz Design Clock from 50MHz Oscillator
----------------------------------------------------------
u_CLOCK : entity work.clock
port map(
CLK50 => CLK50,
CLK => CLK );
-- Memory Mapper
----------------------------------------------------------
u_MAPPER : entity work.mapper
port map(
CLKA => CLK,
ADDRA => SYSREG & CPU_A(15 downto 8),
DOUTA => MAPPER_DO );
-- Memory Mapper
----------------------------------------------------------
u_ROM : entity work.rom
port map(
CLKA => CLK,
ADDRA => CPU_A(14 downto 0),
DOUTA => ROM_DO );
-- i8080 CPU
----------------------------------------------------------
u_CPU : k580wm80a
port map(
clk => CLK,
ce => CPU_CLK,
reset => CPU_RESET,
intr => CPU_INTR,
idata => CPU_DI,
addr => CPU_A,
sync => CPU_SYNC,
rd => CPU_RD,
wr => CPU_WR,
inta => CPU_INTA,
odata => CPU_DO );
-- Character RAM
----------------------------------------------------------
u_CHRAM : entity work.chram
port map (
CLK => CLK,
CHRAM_A => CPU_A(9 downto 0),
CHRAM_WR => CHRAM_WR,
CHRAM_DI => CDI & CPU_DO,
CHRAM_DO => CHRAM_DO,
CHRAM_VA => CHRAM_VA,
CHRAM_VD => CHRAM_VD );
-- VGA Video Controller
----------------------------------------------------------
u_VIDEO : entity work.video
port map(
CLK => CLK,
RESET => RESET,
CACHE_SWAP => CACHE_SWAP,
CACHE_A => CACHE_AO,
CACHE_D => CACHE_DO,
CURRENT_LINE => SCANLINE,
LUT_A => LUT_A,
LUT_D => LUT_D,
VBLANK => VBLANK,
R => VGA_R,
G => VGA_G,
B => VGA_B,
HSYNC => VGA_HSYNC,
VSYNC => VGA_VSYNC );
-- Keyboard Controller
----------------------------------------------------------
u_KEYBOARD : entity work.keyboard
port map(
clk => CLK,
reset => RESET,
o_reset => KB_SG_RESET,
PS2_Clk => PS2_CLK,
PS2_Data => PS2_DATA,
Key_Addr => CPU_A(8 downto 0),
Key_Data => KEYBOARD_DO );
-- Font ROM
----------------------------------------------------------
u_FONTROM : ENTITY work.fontrom
PORT MAP(
ADDRA => FONTROM_A,
CLKA => CLK,
DOUTA => FONTROM_DO);
-- Video Scanline Cache
----------------------------------------------------------
u_CACHE : entity work.cache
port map (
CLK => CLK,
AI => CACHE_AI,
DI => CACHE_DI,
WE => CACHE_WE,
AO => CACHE_AO,
DO => CACHE_DO,
CACHE => CACHE_SWAP );
-- i8255 - PPI1 Controller
----------------------------------------------------------
u_PPI1 : entity work.i8255
port map(
CLK => CLK,
RESET => CPU_RESET,
A => CPU_A(1 downto 0),
DI => CPU_DO,
DO => PPI1_DO,
WR => PPI1_WR,
PAI => PPI1_PAI,
PAO => PPI1_PAO,
PBI => PPI1_PBI,
PBO => PPI1_PBO,
PCI => PPI1_PCI,
PCO => PPI1_PCO );
PPI1_PAI <= "1111" & CDI & '0' & VBLANK & not TAPE_IN;
PPI1_PBI <= "00000000";
PPI1_PCI <= "00000000";
-- i8255 - PPI2 Controller
----------------------------------------------------------
u_PPI2 : entity work.i8255
port map(
CLK => CLK,
RESET => CPU_RESET,
A => CPU_A(1 downto 0),
DI => CPU_DO,
DO => PPI2_DO,
WR => PPI2_WR,
PAI => PPI2_PAI,
PAO => PPI2_PAO,
PBI => PPI2_PBI,
PBO => PPI2_PBO,
PCI => PPI2_PCI,
PCO => PPI2_PCO );
PPI2_PAI <= "00000000";
PPI2_PBI <= "00000000";
PPI2_PCI <= "00000000";
-- i8255 - PPI3 Controller
----------------------------------------------------------
u_PPI3 : entity work.i8255
port map(
CLK => CLK,
RESET => CPU_RESET,
A => CPU_A(1 downto 0),
DI => CPU_DO,
DO => PPI3_DO,
WR => PPI3_WR,
PAI => PPI3_PAI,
PAO => PPI3_PAO,
PBI => PPI3_PBI,
PBO => PPI3_PBO,
PCI => PPI3_PCI,
PCO => PPI3_PCO );
PPI3_PAI <= "00000000";
PPI3_PBI <= "00000000";
PPI3_PCI <= "00000000";
-- i8259 - Programmable Interrupt Controller
----------------------------------------------------------
u_PIC : entity work.i8259
port map(
CLK => CLK,
RESET => CPU_RESET,
A0 => CPU_A(0),
WR => PIC_WR,
INTA => CPU_INTA,
INTR => CPU_INTR,
IRQ => "000" & (VBLANK and not PAUSE_ONESHOT) & "0000",
DI => CPU_DO,
DO => PIC_DO );
-- i8253 - Timer
----------------------------------------------------------
u_TIMER : k580wi53
port map (
clk => CLK,
c0 => TIMER_C0, -- 2MHz Clock for Sound Generation
c1 => '0', -- for RS232
c2 => '0', -- HBL 65.6 µS Period for Interrupt
g0 => '1',
g1 => '1',
g2 => '1',
out0 => TIMER_OUT0,
out1 => OPEN,
out2 => OPEN,
addr => CPU_A(1 downto 0),
rd => TIMER_RD,
we_n => not TIMER_WR,
idata => CPU_DO,
odata => TIMER_DO );
u_SPI : entity work.spi_comm
port map(
CLK => CLK,
RESET => RESET,
SPI_CS_A => COMM_CSA,
SPI_CS_D => COMM_CSD,
SPI_SCK => COMM_SCK,
SPI_DI => COMM_MOSI,
SPI_DO => COMM_MISO,
ADDR_O => COMM_ADDR_O,
ADDR_I => COMM_ADDR_I,
ADDR_REQ => COMM_ADDR_REQ,
ADDR_ACK => COMM_ADDR_ACK,
DATA_O => COMM_DATA_O,
DATA_I => COMM_DATA_I,
DATA_REQ => COMM_DATA_REQ,
DATA_ACK => COMM_DATA_ACK );
u_ONESHOT_RESET : entity work.oneshot
port map(
CLK => CLK,
RESET => RESET,
ONESHOT_IN => CPU_PAUSE,
ONESHOT_OUT => PAUSE_ONESHOT );
-- Select active Floppy Drive
----------------------------------------------------------
floppy_drive : process(DRV_SEL)
begin
case DRV_SEL is
when X"0" => DRIVE <= "00";
when X"1" => DRIVE <= "00";
when X"2" => DRIVE <= "01";
when X"3" => DRIVE <= "01";
when X"4" => DRIVE <= "10";
when X"5" => DRIVE <= "01";
when X"6" => DRIVE <= "10";
when X"7" => DRIVE <= "01";
when X"8" => DRIVE <= "11";
when X"9" => DRIVE <= "00";
when X"A" => DRIVE <= "01";
when X"B" => DRIVE <= "00";
when X"C" => DRIVE <= "00";
when X"D" => DRIVE <= "01";
when X"E" => DRIVE <= "00";
when X"F" => DRIVE <= "01";
when others => DRIVE <= "00";
end case;
end process;
-- Generate Global Reset and CPU Reset & Clock
----------------------------------------------------------
design_reset : process(CLK)
begin
if rising_edge(CLK) then
if KB_SG_RESET = '1' then
TICK <= "0000";
CPU_RESET <= '1';
CPU_CLK <= '0';
else
CPU_CLK <= '0';
if CPU_PAUSE = '0' then
TICK <= TICK + 1;
if TICK = 12 then
TICK <= "0000";
CPU_RESET <= '0';
RESET <= '0';
CPU_CLK <= '1';
end if;
end if;
end if;
end if;
end process;
-- Generate 2MHz Clock for Timer 0
----------------------------------------------------------
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
TICK2_0 <= "00";
TICK2_1 <= "00000";
else
if TICK2_1 < 8 then
TIMER_C0 <= '0';
else
TIMER_C0 <= '1';
end if;
TICK2_1 <= TICK2_1 + 1;
if (TICK2_0 = "00" and TICK2_1 = 17) or TICK2_1 = 16 then
TICK2_0 <= TICK2_0 + 1;
TICK2_1 <= "00000";
end if;
end if;
end if;
end process;
-- Character Inversion Logic
----------------------------------------------------------
inversion_logic : process(CLK)
begin
if rising_edge(CLK) then
if INVON = '0' and INVOFF = '1' then
CDI <= '1';
elsif INVON = '1' and INVOFF = '0' then
CDI <= '0';
elsif INVON = '1' and INVOFF = '1' then
CDI <= CDO;
end if;
if INVON = '1' and INVOFF = '1' then
CDO <= CHRAM_DO(8);
end if;
end if;
end process;
-- CPU Write
----------------------------------------------------------
CHRAM_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_CGRAM else '0';
PPI1_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "111" else '0';
PPI2_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "110" else '0';
PPI3_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "001" else '0';
PIC_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "101" else '0';
TIMER_WR <= '1' when CPU_WR = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000" else '0';
-- ########################################### TEST #####################################################
-- TIMER_RD <= '1' when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000" else '0';
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
TIMER_RD <= '0';
else
TIMER_RD <= '0';
if TICK = 3 and CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000" then
TIMER_RD <= '1';
end if;
end if;
end if;
end process;
-- ########################################### END TEST ################################################
-- CPU Read
----------------------------------------------------------
CPU_DI <= PIC_DO when CPU_INTA = '1' or (CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "101")
-- else FLASH_D when CPU_RD = '1' and MAPPER_DO = M_ROM
-- else RAM_DO when CPU_RD = '1' and (MAPPER_DO = M_RAM or MAPPER_DO = M_REGBASE)
else ROM_DO when CPU_RD = '1' and MAPPER_DO = M_ROM
else RAM_DO when CPU_RD = '1' and (MAPPER_DO = M_RAM or MAPPER_DO = M_REGBASE)
else PPI3_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "001"
else PPI2_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "110"
else PPI1_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "111"
else TIMER_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "000"
else FLOPPY_DO when CPU_RD = '1' and MAPPER_DO = M_PORTBASE and CPU_A(5 downto 3) = "011"
else CHRAM_DO(7 downto 0) when CPU_RD = '1' and MAPPER_DO = M_CGRAM
else VRAM_DO when CPU_RD = '1' and MAPPER_DO = M_VRAM
else KEYBOARD_DO when CPU_RD = '1' and MAPPER_DO = M_KEYBOARD
else "11111111";
-- SRAM Arbiter / Controller
----------------------------------------------------------
SRAM_DO <= SRAM_D;
SRAM_D <= SRAM_DI;
process(CLK)
begin
if rising_edge(CLK) then
if CPU_RESET = '1' then
STATE <= ST_IDLE;
SRAM_A <= (others => '0');
SRAM_DI <= (others => 'Z');
SRAM_CS <= '1';
SRAM_OE <= '1';
SRAM_WE <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
CACHE_WE <= '0';
CACHE_CNT <= "111111";
SYSREG <= "00000";
COLORREG <= "00000000";
CACHE_RD <= '0';
CPU_PAUSE <= '0';
COMM_REQ <= '0';
FLOPPY_DO <= "00000000";
COMM_ADDR_ACK <= '0';
COMM_DATA_ACK <= '0';
else
COMM_ADDR_ACK <= '0';
COMM_DATA_ACK <= '0';
CACHE_WE <= '0';
if CACHE_SWAP = '1' then
CACHE_RD <= '1';
CACHE_CNT <= "000000";
end if;
case STATE is
when ST_IDLE =>
if TICK = 3 then
if CPU_RD = '1' then
case MAPPER_DO is
when M_RAM | M_REGBASE =>
SRAM_A <= "00" & CPU_A;
SRAM_OE <= '0';
SRAM_WE <= '1';
SRAM_CS <= '0';
SRAM_LB <= '0';
SRAM_UB <= '1';
STATE <= ST_RAMREAD;
when M_VRAM =>
SRAM_A <= "00" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_VRAMREAD1;
when M_PORTBASE =>
if CPU_A(5 downto 3) = "011" then -- Read from Floppy
COMM_REQ <= '1';
COMM_ADDR_I <= '0' & FLOPPY_SIDE & DRIVE & "00" & CPU_A(1 downto 0);
COMM_DATA_I <= X"FF";
CPU_PAUSE <= '1';
STATE <= ST_FLOPPY1;
end if;
when others =>
STATE <= ST_IDLE;
end case;
elsif CPU_WR = '1' then
case MAPPER_DO is
when M_RAM | M_ROM | M_KEYBOARD =>
SRAM_A <= "00" & CPU_A;
SRAM_WE <= '0';
SRAM_OE <= '1';
SRAM_CS <= '0';
SRAM_LB <= '0';
SRAM_UB <= '1';
SRAM_DI <= "ZZZZZZZZ" & CPU_DO;
STATE <= ST_RAMWRITE1;
when M_VRAM =>
SRAM_A <= "00" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_VRAMWRITE1;
when M_REGBASE =>
if CPU_A(7) = '0' then
SYSREG <= CPU_DO(6 downto 2);
elsif CPU_A(6) = '0' then
COLORREG <= CPU_DO;
elsif CPU_A(2) = '0' then
LUT(to_integer(unsigned(CPU_DO(3 downto 0)))) <= CPU_DO(7 downto 4);
end if;
when M_PORTBASE =>
if CPU_A(5 downto 3) = "011" then -- Write to Floppy
COMM_REQ <= '1';
COMM_ADDR_I <= '1' & FLOPPY_SIDE & DRIVE & "00" & CPU_A(1 downto 0);
COMM_DATA_I <= CPU_DO;
CPU_PAUSE <= '1';
STATE <= ST_FLOPPY1;
end if;
when others =>
STATE <= ST_IDLE;
end case;
else
if CACHE_RD = '1' then
CHRAM_VA <= SCANLINE(7 downto 4) & std_logic_vector(CACHE_CNT);
SRAM_A <= "00" & VIEW_PAGE & SCANLINE & std_logic_vector(CACHE_CNT);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_CACHEREAD1;
NSTATE <= ST_IDLE;
end if;
end if;
end if;
when ST_FLOPPY1 =>
if COMM_ADDR_REQ = '1' then
COMM_REQ <= '0';
COMM_ADDR_ACK <= '1';
elsif COMM_DATA_REQ = '1' then
COMM_DATA_ACK <= '1';
FLOPPY_DO <= COMM_DATA_O;
CPU_PAUSE <= '0';
STATE <= ST_FLOPPY3;
elsif CACHE_RD = '1' then
CHRAM_VA <= SCANLINE(7 downto 4) & std_logic_vector(CACHE_CNT);
SRAM_A <= "00" & VIEW_PAGE & SCANLINE & std_logic_vector(CACHE_CNT);
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_OE <= '0';
SRAM_CS <= '0';
STATE <= ST_CACHEREAD1;
NSTATE <= ST_FLOPPY1;
end if;
when ST_FLOPPY3 =>
if CPU_RD = '0' and CPU_WR = '0' then
STATE <= ST_IDLE;
end if;
when ST_RAMREAD =>
RAM_DO <= SRAM_DO(7 downto 0);
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_LB <= '1';
STATE <= ST_IDLE;
when ST_RAMWRITE1 =>
SRAM_WE <= '1';
STATE <= ST_RAMWRITE2;
when ST_RAMWRITE2 =>
SRAM_DI <= (OTHERS => 'Z');
SRAM_CS <= '1';
SRAM_LB <= '1';
STATE <= ST_IDLE;
when ST_CACHEREAD1 =>
PLANE0 <= SRAM_DO(15 downto 8);
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VIEW_PAGE & SCANLINE & std_logic_vector(CACHE_CNT);
STATE <= ST_CACHEREAD2;
when ST_CACHEREAD2 =>
PLANE1 <= SRAM_DO(15 downto 8);
PLANE2 <= SRAM_DO(7 downto 0);
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
FONTROM_A <= CHRAM_VD(7 downto 0) & SCANLINE(3 downto 0);
-- FONTROM_A <= ALTFONT & CHRAM_VD(7 downto 0) & SCANLINE(3 downto 0);
STATE <= ST_CACHEREAD3;
when ST_CACHEREAD3 =>
STATE <= ST_CACHEREAD4;
when ST_CACHEREAD4 =>
CACHE_AI <= std_logic_vector(CACHE_CNT(5 downto 0));
if CHRAM_VD(8) = '0' then
CACHE_DI <= FONTROM_DO & PLANE2 & PLANE1 & PLANE0;
else
CACHE_DI <= (not FONTROM_DO) & PLANE2 & PLANE1 & PLANE0;
end if;
CACHE_WE <= '1';
if CACHE_CNT = "111111" then
CACHE_RD <= '0';
else
CACHE_CNT <= CACHE_CNT + 1;
end if;
STATE <= NSTATE;
when ST_VRAMREAD1 =>
PLANE0 <= SRAM_DO(15 downto 8);
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VRAM_PAGE & CPU_A(13 downto 0);
STATE <= ST_VRAMREAD2;
when ST_VRAMREAD2 =>
PLANE1 <= SRAM_DO(15 downto 8);
PLANE2 <= SRAM_DO(7 downto 0);
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_WE <= '1';
STATE <= ST_VRAMREAD3;
when ST_VRAMREAD3 =>
if COLORREG(7) = '1' then -- color mode
if COLORREG(4) = '0' then
PLANE0 <= PLANE0 xor "11111111";
end if;
if COLORREG(5) = '0' then
PLANE1 <= PLANE1 xor "11111111";
end if;
if COLORREG(6) = '0' then
PLANE2 <= PLANE2 xor "11111111";
end if;
else -- plane mode
if COLORREG(4) = '1' then
VRAM_DO <= PLANE0;
else
VRAM_DO <= "00000000";
end if;
end if;
STATE <= ST_VRAMREAD4;
when ST_VRAMREAD4 =>
if COLORREG(7) = '1' then
VRAM_DO <= (PLANE0 and PLANE1 and PLANE2) xor "11111111";
else
if COLORREG(5) = '1' then
VRAM_DO <= PLANE1;
end if;
end if;
STATE <= ST_VRAMREAD5;
when ST_VRAMREAD5 =>
if COLORREG(7) = '0' then
if COLORREG(6) = '1' then
VRAM_DO <= PLANE2;
end if;
end if;
STATE <= ST_IDLE;
when ST_VRAMWRITE1 =>
PLANE0 <= SRAM_DO(15 downto 8);
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VRAM_PAGE & CPU_A(13 downto 0);
STATE <= ST_VRAMWRITE2;
when ST_VRAMWRITE2 =>
PLANE1 <= SRAM_DO(15 downto 8);
PLANE2 <= SRAM_DO(7 downto 0);
SRAM_OE <= '1';
SRAM_CS <= '1';
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_WE <= '1';
STATE <= ST_VRAMWRITE3;
when ST_VRAMWRITE3 =>
if COLORREG(7) = '1' then -- color mode
if COLORREG(1) = '1' then
PLANE0 <= PLANE0 or CPU_DO;
else
PLANE0 <= PLANE0 and not CPU_DO;
end if;
if COLORREG(2) = '1' then
PLANE1 <= PLANE1 or CPU_DO;
else
PLANE1 <= PLANE1 and not CPU_DO;
end if;
if COLORREG(3) = '1' then
PLANE2 <= PLANE2 or CPU_DO;
else
PLANE2 <= PLANE2 and not CPU_DO;
end if;
else -- plane mode
if COLORREG(0) = '1' then -- write 1
if COLORREG(1) = '0' then
PLANE0 <= PLANE0 or CPU_DO;
end if;
if COLORREG(2) = '0' then
PLANE1 <= PLANE1 or CPU_DO;
end if;
if COLORREG(3) = '0' then
PLANE2 <= PLANE2 or CPU_DO;
end if;
else -- write 0
if COLORREG(1) = '0' then
PLANE0 <= PLANE0 and not CPU_DO;
end if;
if COLORREG(2) = '0' then
PLANE1 <= PLANE1 and not CPU_DO;
end if;
if COLORREG(3) = '0' then
PLANE2 <= PLANE2 and not CPU_DO;
end if;
end if;
end if;
STATE <= ST_VRAMWRITE4;
when ST_VRAMWRITE4 =>
SRAM_LB <= '1';
SRAM_UB <= '0';
SRAM_A <= "00" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_WE <= '0';
SRAM_CS <= '0';
SRAM_DI <= PLANE0 & "ZZZZZZZZ";
STATE <= ST_VRAMWRITE5;
when ST_VRAMWRITE5 =>
SRAM_WE <= '1';
STATE <= ST_VRAMWRITE6;
when ST_VRAMWRITE6 =>
SRAM_LB <= '0';
SRAM_UB <= '0';
SRAM_A <= "01" & VRAM_PAGE & CPU_A(13 downto 0);
SRAM_WE <= '0';
SRAM_DI <= PLANE1 & PLANE2;
STATE <= ST_VRAMWRITE7;
when ST_VRAMWRITE7 =>
SRAM_WE <= '1';
STATE <= ST_VRAMWRITE8;
when ST_VRAMWRITE8 =>
SRAM_LB <= '1';
SRAM_UB <= '1';
SRAM_CS <= '1';
SRAM_OE <= '1';
SRAM_DI <= "ZZZZZZZZZZZZZZZZ";
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
LUT_D <= LUT(to_integer(unsigned(LUT_A)));
SOUND <= TIMER_OUT0 and SOUND_EN;
SOUND_L <= SOUND;
SOUND_R <= SOUND;
-- SOUND_L <= "000" & SOUND & "00" & TAPE_OUT0 & TAPE_IN & "00000000" when SWITCH(8) = '1' else "00" & TAPE_OUT0 & "0000000000000";
-- SOUND_R <= "000" & SOUND & "00" & TAPE_OUT0 & TAPE_IN & "00000000" when SWITCH(8) = '1' else "00" & TAPE_OUT0 & "0000000000000";
end RTL;
|
-- niosii_system_rs232_0_avalon_rs232_slave_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:31
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_rs232_0_avalon_rs232_slave_translator is
generic (
AV_ADDRESS_W : integer := 1;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 1;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(0 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity niosii_system_rs232_0_avalon_rs232_slave_translator;
architecture rtl of niosii_system_rs232_0_avalon_rs232_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
rs232_0_avalon_rs232_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of niosii_system_rs232_0_avalon_rs232_slave_translator
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity Counter is
port(clk : in std_logic;
countup: in std_logic;
reset: in std_logic;
d0: out std_logic_vector(3 downto 0);
d10: out std_logic_vector(3 downto 0);
d100: out std_logic_vector(3 downto 0));
--d1000: out std_logic_vector(3 downto 0));
end Counter;
architecture Behavioral of Counter is
signal t0: integer := 0;
signal t10: integer := 0;
signal t100: integer := 0;
--signal t1000: integer := 0;
begin
process(clk)
variable prescalerCount: integer := 0;
variable prescaler: integer := 25000000;
begin
if (reset = '1') then
t0 <= 0;
t10 <= 0;
t100 <= 0;
--t1000 <= 0;
elsif(clk = '1' and clk'event) then
if prescalerCount >= prescaler then
if countup='1' then
if t100 >= 9 then
t0 <= 0;
t10 <= 0;
t100 <= 0;
--t1000 <= 0;
else
t0 <= t0 + 1;
if t0 >= 9 then
t10 <= t10 + 1;
t0 <= 0;
if t10 >= 9 then
t100 <= t100 + 1;
t10 <= 0;
--if t100 >= 9 then
-- t1000 <= t1000 + 1;
-- t100 <= 0;
--end if;
end if;
end if;
end if;
end if;
prescalerCount := 0;
end if;
prescalerCount := prescalerCount + 1;
end if;
end process;
d0 <= std_logic_vector(to_unsigned(t0, d0'length));
d10 <= std_logic_vector(to_unsigned(t10, d10'length));
d100 <= std_logic_vector(to_unsigned(t100, d100'length));
--d1000 <= std_logic_vector(to_unsigned(t1000, d1000'length));
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
entity cmp_202 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_202;
architecture augh of cmp_202 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_202 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_202;
architecture augh of cmp_202 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity altera_std_synchronizer_nocut is
generic(
depth : integer := 3
);
port(
clk : in vl_logic;
reset_n : in vl_logic;
din : in vl_logic;
dout : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of depth : constant is 1;
end altera_std_synchronizer_nocut;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Thu Sep 14 09:52:04 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_0_sim_netlist.vhdl
-- Design : fifo_generator_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => wr_clk,
CLKBWRCLK => rd_clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => E(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => \out\(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => E(0),
WEA(2) => E(0),
WEA(1) => E(0),
WEA(0) => E(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
\gic0.gc0.count_d1_reg[1]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC;
comp2 : in STD_LOGIC;
\out\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gic0.gc0.count_d1_reg[7]\,
S(2) => \gic0.gc0.count_d1_reg[5]\,
S(1) => \gic0.gc0.count_d1_reg[3]\,
S(0) => \gic0.gc0.count_d1_reg[1]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_d1_reg[9]\
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AEAA"
)
port map (
I0 => comp1,
I1 => comp2,
I2 => \out\,
I3 => wr_en,
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
port (
comp2 : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : in STD_LOGIC;
\gic0.gc0.count_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_reg[9]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gic0.gc0.count_reg[7]\,
S(2) => \gic0.gc0.count_reg[5]\,
S(1) => \gic0.gc0.count_reg[3]\,
S(0) => \gic0.gc0.count_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp2,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gic0.gc0.count_reg[9]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AEAA"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
O => ram_empty_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 : entity is "compare";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair8";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \plusOp__0\(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => \plusOp__0\(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => \plusOp__0\(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => \plusOp__0\(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => \plusOp__0\(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => \plusOp__0\(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7)
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8)
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(4),
Q => \^q\(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(5),
Q => \^q\(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(6),
Q => \^q\(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(7),
Q => \^q\(7)
);
\gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(8),
Q => \^q\(8)
);
\gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(9),
Q => \^q\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
port (
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as is
begin
\rd_dc_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0),
Q => rd_data_count(0)
);
\rd_dc_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1),
Q => rd_data_count(1)
);
\rd_dc_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2),
Q => rd_data_count(2)
);
\rd_dc_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3),
Q => rd_data_count(3)
);
\rd_dc_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4),
Q => rd_data_count(4)
);
\rd_dc_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5),
Q => rd_data_count(5)
);
\rd_dc_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6),
Q => rd_data_count(6)
);
\rd_dc_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7),
Q => rd_data_count(7)
);
\rd_dc_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8),
Q => rd_data_count(8)
);
\rd_dc_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9),
Q => rd_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
port (
prog_empty : out STD_LOGIC;
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as is
signal \gdiff.diff_pntr_pad_reg_n_0_[10]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[1]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[2]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[3]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[4]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[5]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[6]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[7]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[8]\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg_n_0_[9]\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gpe1.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
begin
prog_empty <= \^prog_empty\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => \gdiff.diff_pntr_pad_reg_n_0_[10]\
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => \gdiff.diff_pntr_pad_reg_n_0_[1]\
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => \gdiff.diff_pntr_pad_reg_n_0_[2]\
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => \gdiff.diff_pntr_pad_reg_n_0_[3]\
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => \gdiff.diff_pntr_pad_reg_n_0_[4]\
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => \gdiff.diff_pntr_pad_reg_n_0_[5]\
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => \gdiff.diff_pntr_pad_reg_n_0_[6]\
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => \gdiff.diff_pntr_pad_reg_n_0_[7]\
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => \gdiff.diff_pntr_pad_reg_n_0_[8]\
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => \gdiff.diff_pntr_pad_reg_n_0_[9]\
);
\gpe1.prog_empty_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \^prog_empty\,
I1 => \out\,
I2 => \gpe1.prog_empty_i_i_2_n_0\,
I3 => \gpe1.prog_empty_i_i_3_n_0\,
O => \gpe1.prog_empty_i_i_1_n_0\
);
\gpe1.prog_empty_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[9]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[10]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[8]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[7]\,
O => \gpe1.prog_empty_i_i_2_n_0\
);
\gpe1.prog_empty_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFEA"
)
port map (
I0 => \gdiff.diff_pntr_pad_reg_n_0_[4]\,
I1 => \gdiff.diff_pntr_pad_reg_n_0_[1]\,
I2 => \gdiff.diff_pntr_pad_reg_n_0_[2]\,
I3 => \gdiff.diff_pntr_pad_reg_n_0_[3]\,
I4 => \gdiff.diff_pntr_pad_reg_n_0_[6]\,
I5 => \gdiff.diff_pntr_pad_reg_n_0_[5]\,
O => \gpe1.prog_empty_i_i_3_n_0\
);
\gpe1.prog_empty_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gpe1.prog_empty_i_i_1_n_0\,
PRE => AR(0),
Q => \^prog_empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 : entity is "synchronizer_ff";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
D(9 downto 0) <= Q_reg(9 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => Q(9),
Q => Q_reg(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.wr_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.wr_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.wr_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.wr_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.wr_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
signal \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute msgon of \Q_reg_reg[5]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute msgon of \Q_reg_reg[6]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
attribute msgon of \Q_reg_reg[7]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[8]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[8]\ : label is "yes";
attribute msgon of \Q_reg_reg[8]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[9]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[9]\ : label is "yes";
attribute msgon of \Q_reg_reg[9]\ : label is "true";
begin
\out\(0) <= Q_reg(9);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(7),
Q => Q_reg(7)
);
\Q_reg_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(8),
Q => Q_reg(8)
);
\Q_reg_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => D(9),
Q => Q_reg(9)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(1),
I1 => Q_reg(0),
I2 => Q_reg(2),
I3 => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\,
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(0)
);
\gnxpm_cdc.rd_pntr_bin[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(3),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(9),
I2 => Q_reg(3),
I3 => Q_reg(4),
I4 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I5 => Q_reg(1),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(1)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\,
I1 => Q_reg(4),
I2 => Q_reg(3),
I3 => Q_reg(9),
I4 => Q_reg(2),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(2)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(6),
I3 => Q_reg(5),
O => \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(9),
I1 => Q_reg(3),
I2 => Q_reg(4),
I3 => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\,
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(3)
);
\gnxpm_cdc.rd_pntr_bin[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(5),
I1 => Q_reg(6),
O => \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0\
);
\gnxpm_cdc.rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(4),
I2 => Q_reg(5),
I3 => Q_reg(9),
I4 => Q_reg(7),
I5 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(4)
);
\gnxpm_cdc.rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(9),
I4 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(5)
);
\gnxpm_cdc.rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(6),
I2 => Q_reg(9),
I3 => Q_reg(8),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(6)
);
\gnxpm_cdc.rd_pntr_bin[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(7),
I2 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(7)
);
\gnxpm_cdc.rd_pntr_bin[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(8),
I1 => Q_reg(9),
O => \gnxpm_cdc.rd_pntr_bin_reg[8]\(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
port (
\gdiff.diff_pntr_pad_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
\gdiff.diff_pntr_pad_reg[8]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_0 : out STD_LOGIC;
ram_full_fb_i_reg_1 : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_2 : out STD_LOGIC;
ram_full_fb_i_reg_3 : out STD_LOGIC;
ram_full_fb_i_reg_4 : out STD_LOGIC;
ram_full_fb_i_reg_5 : out STD_LOGIC;
ram_full_fb_i_reg_6 : out STD_LOGIC;
ram_full_fb_i_reg_7 : out STD_LOGIC;
ram_full_fb_i_reg_8 : out STD_LOGIC;
\wr_data_count_i_reg[9]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wr_data_count_i_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.simple_prim36.ram\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gic0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[8]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gic0.gc0.count[9]_i_1\ : label is "soft_lutpair12";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) <= \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9 downto 0);
Q(8 downto 0) <= \^q\(8 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(2),
I4 => wr_pntr_plus2(4),
O => \plusOp__1\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => wr_pntr_plus2(2),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(1),
I4 => wr_pntr_plus2(3),
I5 => wr_pntr_plus2(5),
O => \plusOp__1\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
O => \plusOp__1\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(6),
I1 => \gic0.gc0.count[9]_i_2_n_0\,
I2 => wr_pntr_plus2(7),
O => \plusOp__1\(7)
);
\gic0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(6),
I2 => wr_pntr_plus2(7),
I3 => wr_pntr_plus2(8),
O => \plusOp__1\(8)
);
\gic0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \gic0.gc0.count[9]_i_2_n_0\,
I1 => wr_pntr_plus2(8),
I2 => wr_pntr_plus2(7),
I3 => wr_pntr_plus2(6),
I4 => wr_pntr_plus2(9),
O => \plusOp__1\(9)
);
\gic0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => wr_pntr_plus2(4),
I1 => wr_pntr_plus2(2),
I2 => wr_pntr_plus2(0),
I3 => wr_pntr_plus2(1),
I4 => wr_pntr_plus2(3),
I5 => wr_pntr_plus2(5),
O => \gic0.gc0.count[9]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => AR(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(4),
Q => \^q\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(5),
Q => \^q\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(6),
Q => \^q\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(7),
Q => \^q\(7)
);
\gic0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(8),
Q => \^q\(8)
);
\gic0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => wr_pntr_plus2(9),
Q => p_13_out(9)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(4),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(5),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(6),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(7),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7)
);
\gic0.gc0.count_d2_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(8),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8)
);
\gic0.gc0.count_d2_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => p_13_out(9),
Q => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(4),
Q => wr_pntr_plus2(4)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(5),
Q => wr_pntr_plus2(5)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(6),
Q => wr_pntr_plus2(6)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(7),
Q => wr_pntr_plus2(7)
);
\gic0.gc0.count_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(8),
Q => wr_pntr_plus2(8)
);
\gic0.gc0.count_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(9),
Q => wr_pntr_plus2(9)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
I2 => \^q\(0),
I3 => RD_PNTR_WR(0),
O => ram_full_fb_i_reg_3
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => RD_PNTR_WR(0),
I2 => wr_pntr_plus2(1),
I3 => RD_PNTR_WR(1),
O => ram_full_fb_i_reg_8
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
I2 => \^q\(2),
I3 => RD_PNTR_WR(2),
O => ram_full_fb_i_reg_2
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => RD_PNTR_WR(3),
I2 => wr_pntr_plus2(2),
I3 => RD_PNTR_WR(2),
O => ram_full_fb_i_reg_7
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
I2 => \^q\(4),
I3 => RD_PNTR_WR(4),
O => ram_full_fb_i_reg_1
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(5),
I1 => RD_PNTR_WR(5),
I2 => wr_pntr_plus2(4),
I3 => RD_PNTR_WR(4),
O => ram_full_fb_i_reg_6
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
I2 => \^q\(6),
I3 => RD_PNTR_WR(6),
O => ram_full_fb_i_reg_0
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(7),
I1 => RD_PNTR_WR(7),
I2 => wr_pntr_plus2(6),
I3 => RD_PNTR_WR(6),
O => ram_full_fb_i_reg_5
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
I2 => \^q\(8),
I3 => RD_PNTR_WR(8),
O => ram_full_fb_i_reg
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(9),
I1 => RD_PNTR_WR(9),
I2 => wr_pntr_plus2(8),
I3 => RD_PNTR_WR(8),
O => ram_full_fb_i_reg_4
);
\minusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[7]\(3)
);
\minusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[7]\(2)
);
\minusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[7]\(1)
);
\minusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[7]\(0)
);
\minusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(9),
I1 => RD_PNTR_WR(9),
O => \wr_data_count_i_reg[9]\(1)
);
\minusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(8),
I1 => RD_PNTR_WR(8),
O => \wr_data_count_i_reg[9]\(0)
);
minusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(3),
I1 => RD_PNTR_WR(3),
O => \wr_data_count_i_reg[3]\(3)
);
minusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(2),
I1 => RD_PNTR_WR(2),
O => \wr_data_count_i_reg[3]\(2)
);
minusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(1),
I1 => RD_PNTR_WR(1),
O => \wr_data_count_i_reg[3]\(1)
);
minusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.simple_prim36.ram\(0),
I1 => RD_PNTR_WR(0),
O => \wr_data_count_i_reg[3]\(0)
);
\plusOp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => RD_PNTR_WR(7),
O => \gdiff.diff_pntr_pad_reg[8]\(3)
);
\plusOp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => RD_PNTR_WR(6),
O => \gdiff.diff_pntr_pad_reg[8]\(2)
);
\plusOp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => RD_PNTR_WR(5),
O => \gdiff.diff_pntr_pad_reg[8]\(1)
);
\plusOp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => RD_PNTR_WR(4),
O => \gdiff.diff_pntr_pad_reg[8]\(0)
);
\plusOp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_13_out(9),
I1 => RD_PNTR_WR(9),
O => \gdiff.diff_pntr_pad_reg[10]\(1)
);
\plusOp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => RD_PNTR_WR(8),
O => \gdiff.diff_pntr_pad_reg[10]\(0)
);
plusOp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
plusOp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
plusOp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
plusOp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as is
signal \minusOp_carry__0_n_0\ : STD_LOGIC;
signal \minusOp_carry__0_n_1\ : STD_LOGIC;
signal \minusOp_carry__0_n_2\ : STD_LOGIC;
signal \minusOp_carry__0_n_3\ : STD_LOGIC;
signal \minusOp_carry__0_n_4\ : STD_LOGIC;
signal \minusOp_carry__0_n_5\ : STD_LOGIC;
signal \minusOp_carry__0_n_6\ : STD_LOGIC;
signal \minusOp_carry__0_n_7\ : STD_LOGIC;
signal \minusOp_carry__1_n_3\ : STD_LOGIC;
signal \minusOp_carry__1_n_6\ : STD_LOGIC;
signal \minusOp_carry__1_n_7\ : STD_LOGIC;
signal minusOp_carry_n_0 : STD_LOGIC;
signal minusOp_carry_n_1 : STD_LOGIC;
signal minusOp_carry_n_2 : STD_LOGIC;
signal minusOp_carry_n_3 : STD_LOGIC;
signal minusOp_carry_n_4 : STD_LOGIC;
signal minusOp_carry_n_5 : STD_LOGIC;
signal minusOp_carry_n_6 : STD_LOGIC;
signal minusOp_carry_n_7 : STD_LOGIC;
signal \NLW_minusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_minusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
minusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => minusOp_carry_n_0,
CO(2) => minusOp_carry_n_1,
CO(1) => minusOp_carry_n_2,
CO(0) => minusOp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3) => minusOp_carry_n_4,
O(2) => minusOp_carry_n_5,
O(1) => minusOp_carry_n_6,
O(0) => minusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\minusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => minusOp_carry_n_0,
CO(3) => \minusOp_carry__0_n_0\,
CO(2) => \minusOp_carry__0_n_1\,
CO(1) => \minusOp_carry__0_n_2\,
CO(0) => \minusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \minusOp_carry__0_n_4\,
O(2) => \minusOp_carry__0_n_5\,
O(1) => \minusOp_carry__0_n_6\,
O(0) => \minusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(3 downto 0)
);
\minusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \minusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_minusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \minusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_minusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \minusOp_carry__1_n_6\,
O(0) => \minusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d2_reg[9]\(1 downto 0)
);
\wr_data_count_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_7,
Q => wr_data_count(0)
);
\wr_data_count_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_6,
Q => wr_data_count(1)
);
\wr_data_count_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_5,
Q => wr_data_count(2)
);
\wr_data_count_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => minusOp_carry_n_4,
Q => wr_data_count(3)
);
\wr_data_count_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_7\,
Q => wr_data_count(4)
);
\wr_data_count_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_6\,
Q => wr_data_count(5)
);
\wr_data_count_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_5\,
Q => wr_data_count(6)
);
\wr_data_count_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__0_n_4\,
Q => wr_data_count(7)
);
\wr_data_count_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_7\,
Q => wr_data_count(8)
);
\wr_data_count_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \minusOp_carry__1_n_6\,
Q => wr_data_count(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gpf1.prog_full_i_i_1_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_2_n_0\ : STD_LOGIC;
signal \gpf1.prog_full_i_i_3_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_0\ : STD_LOGIC;
signal \plusOp_carry__0_n_1\ : STD_LOGIC;
signal \plusOp_carry__0_n_2\ : STD_LOGIC;
signal \plusOp_carry__0_n_3\ : STD_LOGIC;
signal \plusOp_carry__0_n_4\ : STD_LOGIC;
signal \plusOp_carry__0_n_5\ : STD_LOGIC;
signal \plusOp_carry__0_n_6\ : STD_LOGIC;
signal \plusOp_carry__0_n_7\ : STD_LOGIC;
signal \plusOp_carry__1_n_3\ : STD_LOGIC;
signal \plusOp_carry__1_n_6\ : STD_LOGIC;
signal \plusOp_carry__1_n_7\ : STD_LOGIC;
signal plusOp_carry_n_0 : STD_LOGIC;
signal plusOp_carry_n_1 : STD_LOGIC;
signal plusOp_carry_n_2 : STD_LOGIC;
signal plusOp_carry_n_3 : STD_LOGIC;
signal plusOp_carry_n_4 : STD_LOGIC;
signal plusOp_carry_n_5 : STD_LOGIC;
signal plusOp_carry_n_6 : STD_LOGIC;
signal plusOp_carry_n_7 : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal \NLW_plusOp_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_plusOp_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_6\,
Q => diff_pntr(9)
);
\gdiff.diff_pntr_pad_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_7,
Q => diff_pntr(0)
);
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_6,
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_5,
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => plusOp_carry_n_4,
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_7\,
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_6\,
Q => diff_pntr(5)
);
\gdiff.diff_pntr_pad_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_5\,
Q => diff_pntr(6)
);
\gdiff.diff_pntr_pad_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__0_n_4\,
Q => diff_pntr(7)
);
\gdiff.diff_pntr_pad_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \plusOp_carry__1_n_7\,
Q => diff_pntr(8)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8F888088"
)
port map (
I0 => \gpf1.prog_full_i_i_2_n_0\,
I1 => \gpf1.prog_full_i_i_3_n_0\,
I2 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I3 => ram_full_fb_i_reg,
I4 => \^prog_full\,
O => \gpf1.prog_full_i_i_1_n_0\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80808000"
)
port map (
I0 => diff_pntr(2),
I1 => diff_pntr(3),
I2 => diff_pntr(4),
I3 => diff_pntr(1),
I4 => diff_pntr(0),
O => \gpf1.prog_full_i_i_2_n_0\
);
\gpf1.prog_full_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => diff_pntr(7),
I1 => diff_pntr(8),
I2 => diff_pntr(5),
I3 => diff_pntr(6),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => diff_pntr(9),
O => \gpf1.prog_full_i_i_3_n_0\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gpf1.prog_full_i_i_1_n_0\,
PRE => \out\,
Q => \^prog_full\
);
plusOp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => plusOp_carry_n_0,
CO(2) => plusOp_carry_n_1,
CO(1) => plusOp_carry_n_2,
CO(0) => plusOp_carry_n_3,
CYINIT => E(0),
DI(3 downto 0) => Q(3 downto 0),
O(3) => plusOp_carry_n_4,
O(2) => plusOp_carry_n_5,
O(1) => plusOp_carry_n_6,
O(0) => plusOp_carry_n_7,
S(3 downto 0) => S(3 downto 0)
);
\plusOp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => plusOp_carry_n_0,
CO(3) => \plusOp_carry__0_n_0\,
CO(2) => \plusOp_carry__0_n_1\,
CO(1) => \plusOp_carry__0_n_2\,
CO(0) => \plusOp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3) => \plusOp_carry__0_n_4\,
O(2) => \plusOp_carry__0_n_5\,
O(1) => \plusOp_carry__0_n_6\,
O(0) => \plusOp_carry__0_n_7\,
S(3 downto 0) => \gic0.gc0.count_d1_reg[7]\(3 downto 0)
);
\plusOp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \plusOp_carry__0_n_0\,
CO(3 downto 1) => \NLW_plusOp_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \plusOp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => Q(8),
O(3 downto 2) => \NLW_plusOp_carry__1_O_UNCONNECTED\(3 downto 2),
O(1) => \plusOp_carry__1_n_6\,
O(0) => \plusOp_carry__1_n_7\,
S(3 downto 2) => B"00",
S(1 downto 0) => \gic0.gc0.count_d1_reg[9]\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0\
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
port (
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 9 downto 0 );
\rd_dc_i_reg[9]\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 9 downto 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : in STD_LOGIC;
\gic0.gc0.count_d2_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs is
signal bin2gray : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \gdiff.diff_pntr_pad[10]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[10]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[4]_i_6_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_2_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_3_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_4_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad[8]_i_5_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_0_out_0 : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal p_6_out : STD_LOGIC_VECTOR ( 9 to 9 );
signal \rd_dc_i[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_4_n_0\ : STD_LOGIC;
signal \rd_dc_i[7]_i_5_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_2_n_0\ : STD_LOGIC;
signal \rd_dc_i[9]_i_3_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rd_dc_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rd_dc_i_reg[9]_i_1_n_3\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[6]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[7]_i_1\ : label is "soft_lutpair3";
begin
\gdiff.diff_pntr_pad[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \gdiff.diff_pntr_pad[10]_i_2_n_0\
);
\gdiff.diff_pntr_pad[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \gdiff.diff_pntr_pad[4]_i_3_n_0\
);
\gdiff.diff_pntr_pad[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \gdiff.diff_pntr_pad[4]_i_4_n_0\
);
\gdiff.diff_pntr_pad[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \gdiff.diff_pntr_pad[4]_i_5_n_0\
);
\gdiff.diff_pntr_pad[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \gdiff.diff_pntr_pad[8]_i_2_n_0\
);
\gdiff.diff_pntr_pad[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \gdiff.diff_pntr_pad[8]_i_3_n_0\
);
\gdiff.diff_pntr_pad[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \gdiff.diff_pntr_pad[8]_i_4_n_0\
);
\gdiff.diff_pntr_pad[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gdiff.diff_pntr_pad_reg[10]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \gdiff.diff_pntr_pad_reg[10]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => D(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \gdiff.diff_pntr_pad[10]_i_2_n_0\,
S(0) => \gdiff.diff_pntr_pad[10]_i_3_n_0\
);
\gdiff.diff_pntr_pad_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[4]_i_1_n_3\,
CYINIT => p_0_out,
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => D(3 downto 0),
S(3) => \gdiff.diff_pntr_pad[4]_i_3_n_0\,
S(2) => \gdiff.diff_pntr_pad[4]_i_4_n_0\,
S(1) => \gdiff.diff_pntr_pad[4]_i_5_n_0\,
S(0) => \gdiff.diff_pntr_pad[4]_i_6_n_0\
);
\gdiff.diff_pntr_pad_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gdiff.diff_pntr_pad_reg[4]_i_1_n_0\,
CO(3) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_0\,
CO(2) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_1\,
CO(1) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_2\,
CO(0) => \gdiff.diff_pntr_pad_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => D(7 downto 4),
S(3) => \gdiff.diff_pntr_pad[8]_i_2_n_0\,
S(2) => \gdiff.diff_pntr_pad[8]_i_3_n_0\,
S(1) => \gdiff.diff_pntr_pad[8]_i_4_n_0\,
S(0) => \gdiff.diff_pntr_pad[8]_i_5_n_0\
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
I2 => p_22_out(1),
I3 => Q(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(0),
I1 => \gc0.count_reg[9]\(0),
I2 => p_22_out(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
I2 => p_22_out(3),
I3 => Q(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[9]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
I2 => p_22_out(5),
I3 => Q(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(4),
I1 => \gc0.count_reg[9]\(4),
I2 => p_22_out(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
I2 => p_22_out(7),
I3 => Q(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(6),
I1 => \gc0.count_reg[9]\(6),
I2 => p_22_out(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
I2 => p_22_out(9),
I3 => Q(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_22_out(8),
I1 => \gc0.count_reg[9]\(8),
I2 => p_22_out(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg_0(4)
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
Q(9 downto 0) => wr_pntr_gc(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
Q(9 downto 0) => rd_pntr_gc(9 downto 0),
wr_clk => wr_clk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2\
port map (
D(9 downto 0) => p_3_out(9 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(8) => p_0_out_0,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(7 downto 0) => gray2bin(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_5_out(9),
rd_clk => rd_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(9 downto 0) => p_4_out(9 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[8]\(8) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(7) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(6) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(5) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(4) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(3) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(2) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(1) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
\gnxpm_cdc.rd_pntr_bin_reg[8]\(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
\out\(0) => p_6_out(9),
wr_clk => wr_clk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9\,
Q => RD_PNTR_WR(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8\,
Q => RD_PNTR_WR(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7\,
Q => RD_PNTR_WR(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6\,
Q => RD_PNTR_WR(3)
);
\gnxpm_cdc.rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5\,
Q => RD_PNTR_WR(4)
);
\gnxpm_cdc.rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => RD_PNTR_WR(5)
);
\gnxpm_cdc.rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3\,
Q => RD_PNTR_WR(6)
);
\gnxpm_cdc.rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2\,
Q => RD_PNTR_WR(7)
);
\gnxpm_cdc.rd_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1\,
Q => RD_PNTR_WR(8)
);
\gnxpm_cdc.rd_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => p_6_out(9),
Q => RD_PNTR_WR(9)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(7),
I1 => Q(8),
O => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(8),
I1 => Q(9),
O => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\gnxpm_cdc.rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\gnxpm_cdc.rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\gnxpm_cdc.rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0\,
Q => rd_pntr_gc(7)
);
\gnxpm_cdc.rd_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0\,
Q => rd_pntr_gc(8)
);
\gnxpm_cdc.rd_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(9),
Q => rd_pntr_gc(9)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(4),
Q => p_22_out(4)
);
\gnxpm_cdc.wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(5),
Q => p_22_out(5)
);
\gnxpm_cdc.wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(6),
Q => p_22_out(6)
);
\gnxpm_cdc.wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(7),
Q => p_22_out(7)
);
\gnxpm_cdc.wr_pntr_bin_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out_0,
Q => p_22_out(8)
);
\gnxpm_cdc.wr_pntr_bin_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_5_out(9),
Q => p_22_out(9)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(0),
I1 => \gic0.gc0.count_d2_reg[9]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(1),
I1 => \gic0.gc0.count_d2_reg[9]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(2),
I1 => \gic0.gc0.count_d2_reg[9]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(3),
I1 => \gic0.gc0.count_d2_reg[9]\(4),
O => bin2gray(3)
);
\gnxpm_cdc.wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(4),
I1 => \gic0.gc0.count_d2_reg[9]\(5),
O => bin2gray(4)
);
\gnxpm_cdc.wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(5),
I1 => \gic0.gc0.count_d2_reg[9]\(6),
O => bin2gray(5)
);
\gnxpm_cdc.wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(6),
I1 => \gic0.gc0.count_d2_reg[9]\(7),
O => bin2gray(6)
);
\gnxpm_cdc.wr_pntr_gc[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(7),
I1 => \gic0.gc0.count_d2_reg[9]\(8),
O => bin2gray(7)
);
\gnxpm_cdc.wr_pntr_gc[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[9]\(8),
I1 => \gic0.gc0.count_d2_reg[9]\(9),
O => bin2gray(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(3),
Q => wr_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(4),
Q => wr_pntr_gc(4)
);
\gnxpm_cdc.wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(5),
Q => wr_pntr_gc(5)
);
\gnxpm_cdc.wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(6),
Q => wr_pntr_gc(6)
);
\gnxpm_cdc.wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(7),
Q => wr_pntr_gc(7)
);
\gnxpm_cdc.wr_pntr_gc_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => bin2gray(8),
Q => wr_pntr_gc(8)
);
\gnxpm_cdc.wr_pntr_gc_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[9]\(9),
Q => wr_pntr_gc(9)
);
\rd_dc_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
O => \rd_dc_i[3]_i_2_n_0\
);
\rd_dc_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(2),
I1 => Q(2),
O => \rd_dc_i[3]_i_3_n_0\
);
\rd_dc_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(1),
I1 => Q(1),
O => \rd_dc_i[3]_i_4_n_0\
);
\rd_dc_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(0),
I1 => Q(0),
O => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(7),
I1 => Q(7),
O => \rd_dc_i[7]_i_2_n_0\
);
\rd_dc_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(6),
I1 => Q(6),
O => \rd_dc_i[7]_i_3_n_0\
);
\rd_dc_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(5),
I1 => Q(5),
O => \rd_dc_i[7]_i_4_n_0\
);
\rd_dc_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(4),
I1 => Q(4),
O => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(9),
I1 => Q(9),
O => \rd_dc_i[9]_i_2_n_0\
);
\rd_dc_i[9]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_22_out(8),
I1 => Q(8),
O => \rd_dc_i[9]_i_3_n_0\
);
\rd_dc_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rd_dc_i_reg[3]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[3]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[3]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => p_22_out(3 downto 0),
O(3 downto 0) => \rd_dc_i_reg[9]\(3 downto 0),
S(3) => \rd_dc_i[3]_i_2_n_0\,
S(2) => \rd_dc_i[3]_i_3_n_0\,
S(1) => \rd_dc_i[3]_i_4_n_0\,
S(0) => \rd_dc_i[3]_i_5_n_0\
);
\rd_dc_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[3]_i_1_n_0\,
CO(3) => \rd_dc_i_reg[7]_i_1_n_0\,
CO(2) => \rd_dc_i_reg[7]_i_1_n_1\,
CO(1) => \rd_dc_i_reg[7]_i_1_n_2\,
CO(0) => \rd_dc_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_22_out(7 downto 4),
O(3 downto 0) => \rd_dc_i_reg[9]\(7 downto 4),
S(3) => \rd_dc_i[7]_i_2_n_0\,
S(2) => \rd_dc_i[7]_i_3_n_0\,
S(1) => \rd_dc_i[7]_i_4_n_0\,
S(0) => \rd_dc_i[7]_i_5_n_0\
);
\rd_dc_i_reg[9]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rd_dc_i_reg[7]_i_1_n_0\,
CO(3 downto 1) => \NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \rd_dc_i_reg[9]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_22_out(8),
O(3 downto 2) => \NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => \rd_dc_i_reg[9]\(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \rd_dc_i[9]_i_2_n_0\,
S(0) => \rd_dc_i[9]_i_3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_out : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
c0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
port map (
comp1 => comp1,
\out\ => ram_empty_fb_i,
ram_empty_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
\gdiff.diff_pntr_pad[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => ram_empty_fb_i,
I1 => rd_en,
O => p_0_out
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => c0_n_0,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
WR_RST_BUSY : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
WR_RST_BUSY <= rst_d3;
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst_reg(0),
I1 => ram_empty_fb_i_reg,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
rd_clk => rd_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
wr_clk => wr_clk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
port (
full : out STD_LOGIC;
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d1_reg[1]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_d1_reg[9]\ : in STD_LOGIC;
\gic0.gc0.count_reg[0]\ : in STD_LOGIC;
\gic0.gc0.count_reg[3]\ : in STD_LOGIC;
\gic0.gc0.count_reg[5]\ : in STD_LOGIC;
\gic0.gc0.count_reg[7]\ : in STD_LOGIC;
\gic0.gc0.count_reg[9]\ : in STD_LOGIC;
wr_clk : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d2_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as is
signal c1_n_0 : STD_LOGIC;
signal comp2 : STD_LOGIC;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
port map (
comp2 => comp2,
\gic0.gc0.count_d1_reg[1]\ => \gic0.gc0.count_d1_reg[1]\,
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gic0.gc0.count_d1_reg[5]\ => \gic0.gc0.count_d1_reg[5]\,
\gic0.gc0.count_d1_reg[7]\ => \gic0.gc0.count_d1_reg[7]\,
\gic0.gc0.count_d1_reg[9]\ => \gic0.gc0.count_d1_reg[9]\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => ram_full_fb_i,
ram_full_fb_i_reg => c1_n_0,
wr_en => wr_en
);
c2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
port map (
comp2 => comp2,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\gic0.gc0.count_reg[3]\ => \gic0.gc0.count_reg[3]\,
\gic0.gc0.count_reg[5]\ => \gic0.gc0.count_reg[5]\,
\gic0.gc0.count_reg[7]\ => \gic0.gc0.count_reg[7]\,
\gic0.gc0.count_reg[9]\ => \gic0.gc0.count_reg[9]\
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c1_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => c1_n_0,
PRE => \grstd1.grst_full.grst_f.rst_d2_reg\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
port (
empty : out STD_LOGIC;
\out\ : out STD_LOGIC;
prog_empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
p_0_out : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[8]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic is
signal \gras.rsts_n_2\ : STD_LOGIC;
signal \^out\ : STD_LOGIC;
begin
\out\ <= \^out\;
\gras.gpe.rdpe\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
port map (
AR(0) => AR(0),
D(9 downto 0) => D(9 downto 0),
\out\ => \^out\,
prog_empty => prog_empty,
rd_clk => rd_clk
);
\gras.grdc1.rdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
port map (
AR(0) => AR(0),
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0),
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0)
);
\gras.rsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \gras.rsts_n_2\,
empty => empty,
\out\ => \^out\,
p_0_out => p_0_out,
rd_clk => rd_clk,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
rpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \gras.rsts_n_2\,
Q(9 downto 0) => Q(9 downto 0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
port (
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_clk : in STD_LOGIC;
\out\ : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 9 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gwas.wsts_n_1\ : STD_LOGIC;
signal p_13_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wpntr_n_0 : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_11 : STD_LOGIC;
signal wpntr_n_12 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_14 : STD_LOGIC;
signal wpntr_n_15 : STD_LOGIC;
signal wpntr_n_16 : STD_LOGIC;
signal wpntr_n_17 : STD_LOGIC;
signal wpntr_n_18 : STD_LOGIC;
signal wpntr_n_19 : STD_LOGIC;
signal wpntr_n_20 : STD_LOGIC;
signal wpntr_n_21 : STD_LOGIC;
signal wpntr_n_22 : STD_LOGIC;
signal wpntr_n_23 : STD_LOGIC;
signal wpntr_n_24 : STD_LOGIC;
signal wpntr_n_25 : STD_LOGIC;
signal wpntr_n_26 : STD_LOGIC;
signal wpntr_n_27 : STD_LOGIC;
signal wpntr_n_28 : STD_LOGIC;
signal wpntr_n_29 : STD_LOGIC;
signal wpntr_n_30 : STD_LOGIC;
signal wpntr_n_41 : STD_LOGIC;
signal wpntr_n_42 : STD_LOGIC;
signal wpntr_n_43 : STD_LOGIC;
signal wpntr_n_44 : STD_LOGIC;
signal wpntr_n_45 : STD_LOGIC;
signal wpntr_n_46 : STD_LOGIC;
signal wpntr_n_47 : STD_LOGIC;
signal wpntr_n_48 : STD_LOGIC;
begin
E(0) <= \^e\(0);
Q(9 downto 0) <= \^q\(9 downto 0);
\gwas.gpf.wrpf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(8 downto 0) => p_13_out(8 downto 0),
S(3) => wpntr_n_18,
S(2) => wpntr_n_19,
S(1) => wpntr_n_20,
S(0) => wpntr_n_21,
\gic0.gc0.count_d1_reg[7]\(3) => wpntr_n_12,
\gic0.gc0.count_d1_reg[7]\(2) => wpntr_n_13,
\gic0.gc0.count_d1_reg[7]\(1) => wpntr_n_14,
\gic0.gc0.count_d1_reg[7]\(0) => wpntr_n_15,
\gic0.gc0.count_d1_reg[9]\(1) => wpntr_n_0,
\gic0.gc0.count_d1_reg[9]\(0) => wpntr_n_1,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \out\,
prog_full => prog_full,
ram_full_fb_i_reg => \gwas.wsts_n_1\,
wr_clk => wr_clk
);
\gwas.gwdc0.wdc\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
port map (
AR(0) => AR(0),
Q(8 downto 0) => \^q\(8 downto 0),
S(3) => wpntr_n_45,
S(2) => wpntr_n_46,
S(1) => wpntr_n_47,
S(0) => wpntr_n_48,
\gic0.gc0.count_d2_reg[7]\(3) => wpntr_n_41,
\gic0.gc0.count_d2_reg[7]\(2) => wpntr_n_42,
\gic0.gc0.count_d2_reg[7]\(1) => wpntr_n_43,
\gic0.gc0.count_d2_reg[7]\(0) => wpntr_n_44,
\gic0.gc0.count_d2_reg[9]\(1) => wpntr_n_29,
\gic0.gc0.count_d2_reg[9]\(0) => wpntr_n_30,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0)
);
\gwas.wsts\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
\gic0.gc0.count_d1_reg[1]\ => wpntr_n_23,
\gic0.gc0.count_d1_reg[3]\ => wpntr_n_22,
\gic0.gc0.count_d1_reg[5]\ => wpntr_n_17,
\gic0.gc0.count_d1_reg[7]\ => wpntr_n_16,
\gic0.gc0.count_d1_reg[9]\ => wpntr_n_11,
\gic0.gc0.count_reg[0]\ => wpntr_n_28,
\gic0.gc0.count_reg[3]\ => wpntr_n_27,
\gic0.gc0.count_reg[5]\ => wpntr_n_26,
\gic0.gc0.count_reg[7]\ => wpntr_n_25,
\gic0.gc0.count_reg[9]\ => wpntr_n_24,
\grstd1.grst_full.grst_f.rst_d2_reg\ => \out\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \gwas.wsts_n_1\,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
port map (
AR(0) => AR(0),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \^q\(9 downto 0),
E(0) => \^e\(0),
Q(8 downto 0) => p_13_out(8 downto 0),
RD_PNTR_WR(9 downto 0) => RD_PNTR_WR(9 downto 0),
S(3) => wpntr_n_18,
S(2) => wpntr_n_19,
S(1) => wpntr_n_20,
S(0) => wpntr_n_21,
\gdiff.diff_pntr_pad_reg[10]\(1) => wpntr_n_0,
\gdiff.diff_pntr_pad_reg[10]\(0) => wpntr_n_1,
\gdiff.diff_pntr_pad_reg[8]\(3) => wpntr_n_12,
\gdiff.diff_pntr_pad_reg[8]\(2) => wpntr_n_13,
\gdiff.diff_pntr_pad_reg[8]\(1) => wpntr_n_14,
\gdiff.diff_pntr_pad_reg[8]\(0) => wpntr_n_15,
ram_full_fb_i_reg => wpntr_n_11,
ram_full_fb_i_reg_0 => wpntr_n_16,
ram_full_fb_i_reg_1 => wpntr_n_17,
ram_full_fb_i_reg_2 => wpntr_n_22,
ram_full_fb_i_reg_3 => wpntr_n_23,
ram_full_fb_i_reg_4 => wpntr_n_24,
ram_full_fb_i_reg_5 => wpntr_n_25,
ram_full_fb_i_reg_6 => wpntr_n_26,
ram_full_fb_i_reg_7 => wpntr_n_27,
ram_full_fb_i_reg_8 => wpntr_n_28,
wr_clk => wr_clk,
\wr_data_count_i_reg[3]\(3) => wpntr_n_45,
\wr_data_count_i_reg[3]\(2) => wpntr_n_46,
\wr_data_count_i_reg[3]\(1) => wpntr_n_47,
\wr_data_count_i_reg[3]\(0) => wpntr_n_48,
\wr_data_count_i_reg[7]\(3) => wpntr_n_41,
\wr_data_count_i_reg[7]\(2) => wpntr_n_42,
\wr_data_count_i_reg[7]\(1) => wpntr_n_43,
\wr_data_count_i_reg[7]\(0) => wpntr_n_44,
\wr_data_count_i_reg[9]\(1) => wpntr_n_29,
\wr_data_count_i_reg[9]\(0) => wpntr_n_30
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
port map (
E(0) => E(0),
Q(9 downto 0) => Q(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\out\(0) => \out\(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo is
signal \^wr_rst_busy\ : STD_LOGIC;
signal \gras.rsts/c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gras.rsts/c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 10 downto 1 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
WR_RST_BUSY <= \^wr_rst_busy\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(9 downto 0) => plusOp(10 downto 1),
Q(9 downto 0) => p_0_out_0(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\gic0.gc0.count_d2_reg[9]\(9 downto 0) => p_12_out(9 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
p_0_out => p_0_out,
rd_clk => rd_clk,
\rd_dc_i_reg[9]\(9 downto 0) => minusOp(9 downto 0),
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0),
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(9 downto 0) => plusOp(10 downto 1),
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out_0(9 downto 0),
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
empty => empty,
\gnxpm_cdc.wr_pntr_bin_reg[8]\(9 downto 0) => minusOp(9 downto 0),
\out\ => p_2_out,
p_0_out => p_0_out,
prog_empty => prog_empty,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
v1_reg(4 downto 0) => \gras.rsts/c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \gras.rsts/c1/v1_reg\(4 downto 0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(9 downto 0) => p_12_out(9 downto 0),
RD_PNTR_WR(9 downto 0) => p_23_out(9 downto 0),
full => full,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \^wr_rst_busy\,
\out\ => rst_full_ff_i,
prog_full => prog_full,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
port map (
E(0) => p_18_out,
Q(9 downto 0) => p_12_out(9 downto 0),
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out_0(9 downto 0),
\out\(0) => rd_rst_i(0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
port map (
WR_RST_BUSY => \^wr_rst_busy\,
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top is
begin
\grf.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
port map (
WR_RST_BUSY => WR_RST_BUSY,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
port (
WR_RST_BUSY : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
port map (
WR_RST_BUSY => WR_RST_BUSY,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
port map (
WR_RST_BUSY => wr_rst_busy,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_0,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 1;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 1;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1021;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1020;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => prog_empty,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => prog_full,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => rd_clk,
rd_data_count(9 downto 0) => rd_data_count(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(9 downto 0) => wr_data_count(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- safe_path for dotProduct64 given rtl dir is ./rtl (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE dotProduct64_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END dotProduct64_safe_path;
PACKAGE body dotProduct64_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./rtl/") & path;
END FUNCTION safe_path;
END dotProduct64_safe_path;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 6;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 0;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
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-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Sep 19 09:37:07 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top fifo_generator_0 -prefix
-- fifo_generator_0_ fifo_generator_rx_inst_sim_netlist.vhdl
-- Design : fifo_generator_rx_inst
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end fifo_generator_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 24) => din(34 downto 27),
DIADI(23 downto 16) => din(25 downto 18),
DIADI(15 downto 8) => din(16 downto 9),
DIADI(7 downto 0) => din(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 24) => dout(34 downto 27),
DOBDO(23 downto 16) => dout(25 downto 18),
DOBDO(15 downto 8) => dout(16 downto 9),
DOBDO(7 downto 0) => dout(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => dout(35),
DOPBDOP(2) => dout(26),
DOPBDOP(1) => dout(17),
DOPBDOP(0) => dout(8),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \fifo_generator_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \fifo_generator_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => Q(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => \gc0.count_d1_reg[9]\(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30 downto 24) => din(27 downto 21),
DIADI(23) => '0',
DIADI(22 downto 16) => din(20 downto 14),
DIADI(15) => '0',
DIADI(14 downto 8) => din(13 downto 7),
DIADI(7) => '0',
DIADI(6 downto 0) => din(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53\,
DOBDO(30 downto 24) => dout(27 downto 21),
DOBDO(23) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61\,
DOBDO(22 downto 16) => dout(20 downto 14),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69\,
DOBDO(14 downto 8) => dout(13 downto 7),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77\,
DOBDO(6 downto 0) => dout(6 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89\,
DOPBDOP(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => WEA(0),
ENBWREN => tmp_ram_rd_en,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => srst,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => WEA(0),
WEA(2) => WEA(0),
WEA(1) => WEA(0),
WEA(0) => WEA(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_compare is
port (
ram_full_fb_i_reg : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
comp1 : in STD_LOGIC;
\out\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end fifo_generator_0_compare;
architecture STRUCTURE of fifo_generator_0_compare is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
ram_full_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFC0FFC05500FFC0"
)
port map (
I0 => comp0,
I1 => wr_en,
I2 => comp1,
I3 => \out\,
I4 => rd_en,
I5 => ram_empty_fb_i_reg,
O => ram_full_fb_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_compare_0 is
port (
comp1 : out STD_LOGIC;
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0_compare_0 : entity is "compare";
end fifo_generator_0_compare_0;
architecture STRUCTURE of fifo_generator_0_compare_0 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg_0(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg_0(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_compare_1 is
port (
ram_empty_i_reg : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\out\ : in STD_LOGIC;
comp1 : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0_compare_1 : entity is "compare";
end fifo_generator_0_compare_1;
architecture STRUCTURE of fifo_generator_0_compare_1 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal comp0 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3) => \gcc0.gc0.count_d1_reg[6]\,
S(2) => \gcc0.gc0.count_d1_reg[4]\,
S(1) => \gcc0.gc0.count_d1_reg[2]\,
S(0) => \gcc0.gc0.count_d1_reg[0]\
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp0,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => \gcc0.gc0.count_d1_reg[8]\
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCF0FCF05050FCF0"
)
port map (
I0 => comp0,
I1 => rd_en,
I2 => \out\,
I3 => comp1,
I4 => wr_en,
I5 => ram_full_fb_i_reg,
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_compare_2 is
port (
comp1 : out STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0_compare_2 : entity is "compare";
end fifo_generator_0_compare_2;
architecture STRUCTURE of fifo_generator_0_compare_2 is
signal carrynet_0 : STD_LOGIC;
signal carrynet_1 : STD_LOGIC;
signal carrynet_2 : STD_LOGIC;
signal carrynet_3 : STD_LOGIC;
signal \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \gmux.gm[0].gm1.m1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \gmux.gm[0].gm1.m1_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \gmux.gm[4].gms.ms_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \gmux.gm[4].gms.ms_CARRY4\ : label is "PRIMITIVE";
begin
\gmux.gm[0].gm1.m1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => carrynet_3,
CO(2) => carrynet_2,
CO(1) => carrynet_1,
CO(0) => carrynet_0,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 0) => v1_reg(3 downto 0)
);
\gmux.gm[4].gms.ms_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => carrynet_3,
CO(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED\(3 downto 1),
CO(0) => comp1,
CYINIT => '0',
DI(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED\(3 downto 1),
DI(0) => '0',
O(3 downto 0) => \NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => \NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED\(3 downto 1),
S(0) => v1_reg(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end fifo_generator_0_rd_bin_cntr;
architecture STRUCTURE of fifo_generator_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[7]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gc0.count[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[9]_i_1\ : label is "soft_lutpair0";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gc0.count[9]_i_2_n_0\,
I1 => \^q\(6),
I2 => \^q\(7),
O => plusOp(7)
);
\gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(7),
I3 => \^q\(8),
O => plusOp(8)
);
\gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(7),
I1 => \gc0.count[9]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(8),
I4 => \^q\(9),
O => plusOp(9)
);
\gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \gc0.count[9]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(0),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0),
R => srst
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(1),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1),
R => srst
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(2),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2),
R => srst
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(3),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3),
R => srst
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(4),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4),
R => srst
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(5),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5),
R => srst
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(6),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6),
R => srst
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(7),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7),
R => srst
);
\gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(8),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(8),
R => srst
);
\gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^q\(9),
Q => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9),
R => srst
);
\gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^q\(0),
S => srst
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^q\(1),
R => srst
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^q\(2),
R => srst
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^q\(3),
R => srst
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^q\(4),
R => srst
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^q\(5),
R => srst
);
\gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(6),
Q => \^q\(6),
R => srst
);
\gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(7),
Q => \^q\(7),
R => srst
);
\gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(8),
Q => \^q\(8),
R => srst
);
\gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(9),
Q => \^q\(9),
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_wr_bin_cntr is
port (
v1_reg_0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
srst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
end fifo_generator_0_wr_bin_cntr;
architecture STRUCTURE of fifo_generator_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \gcc0.gc0.count[9]_i_2_n_0\ : STD_LOGIC;
signal p_12_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gcc0.gc0.count[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gcc0.gc0.count[8]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gcc0.gc0.count[9]_i_1\ : label is "soft_lutpair4";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_12_out(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => p_12_out(0),
I1 => p_12_out(1),
I2 => p_12_out(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(1),
I1 => p_12_out(0),
I2 => p_12_out(2),
I3 => p_12_out(3),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(2),
I1 => p_12_out(0),
I2 => p_12_out(1),
I3 => p_12_out(3),
I4 => p_12_out(4),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => p_12_out(3),
I1 => p_12_out(1),
I2 => p_12_out(0),
I3 => p_12_out(2),
I4 => p_12_out(4),
I5 => p_12_out(5),
O => \plusOp__0\(5)
);
\gcc0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
O => \plusOp__0\(6)
);
\gcc0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gcc0.gc0.count[9]_i_2_n_0\,
I1 => p_12_out(6),
I2 => p_12_out(7),
O => \plusOp__0\(7)
);
\gcc0.gc0.count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => p_12_out(6),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(7),
I3 => p_12_out(8),
O => \plusOp__0\(8)
);
\gcc0.gc0.count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => p_12_out(7),
I1 => \gcc0.gc0.count[9]_i_2_n_0\,
I2 => p_12_out(6),
I3 => p_12_out(8),
I4 => p_12_out(9),
O => \plusOp__0\(9)
);
\gcc0.gc0.count[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => p_12_out(5),
I1 => p_12_out(3),
I2 => p_12_out(1),
I3 => p_12_out(0),
I4 => p_12_out(2),
I5 => p_12_out(4),
O => \gcc0.gc0.count[9]_i_2_n_0\
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(0),
Q => \^q\(0),
R => srst
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(1),
Q => \^q\(1),
R => srst
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(2),
Q => \^q\(2),
R => srst
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(3),
Q => \^q\(3),
R => srst
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(4),
Q => \^q\(4),
R => srst
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(5),
Q => \^q\(5),
R => srst
);
\gcc0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(6),
Q => \^q\(6),
R => srst
);
\gcc0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(7),
Q => \^q\(7),
R => srst
);
\gcc0.gc0.count_d1_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(8),
Q => \^q\(8),
R => srst
);
\gcc0.gc0.count_d1_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => p_12_out(9),
Q => \^q\(9),
R => srst
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => p_12_out(0),
S => srst
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => p_12_out(1),
R => srst
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => p_12_out(2),
R => srst
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => p_12_out(3),
R => srst
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => p_12_out(4),
R => srst
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => p_12_out(5),
R => srst
);
\gcc0.gc0.count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(6),
Q => p_12_out(6),
R => srst
);
\gcc0.gc0.count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(7),
Q => p_12_out(7),
R => srst
);
\gcc0.gc0.count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(8),
Q => p_12_out(8),
R => srst
);
\gcc0.gc0.count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(9),
Q => p_12_out(9),
R => srst
);
\gmux.gm[0].gm1.m1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_0(0)
);
\gmux.gm[0].gm1.m1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_reg[9]\(1),
O => v1_reg(0)
);
\gmux.gm[0].gm1.m1_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => p_12_out(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => v1_reg_1(0)
);
\gmux.gm[0].gm1.m1_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(0),
I1 => \gc0.count_d1_reg[9]\(0),
I2 => \^q\(1),
I3 => \gc0.count_d1_reg[9]\(1),
O => ram_empty_i_reg
);
\gmux.gm[1].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_0(1)
);
\gmux.gm[1].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_reg[9]\(3),
O => v1_reg(1)
);
\gmux.gm[1].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => p_12_out(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => v1_reg_1(1)
);
\gmux.gm[1].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_d1_reg[9]\(2),
I2 => \^q\(3),
I3 => \gc0.count_d1_reg[9]\(3),
O => ram_empty_i_reg_0
);
\gmux.gm[2].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_0(2)
);
\gmux.gm[2].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_reg[9]\(5),
O => v1_reg(2)
);
\gmux.gm[2].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => p_12_out(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => v1_reg_1(2)
);
\gmux.gm[2].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(4),
I1 => \gc0.count_d1_reg[9]\(4),
I2 => \^q\(5),
I3 => \gc0.count_d1_reg[9]\(5),
O => ram_empty_i_reg_1
);
\gmux.gm[3].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_0(3)
);
\gmux.gm[3].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_reg[9]\(7),
O => v1_reg(3)
);
\gmux.gm[3].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => p_12_out(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => v1_reg_1(3)
);
\gmux.gm[3].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(6),
I1 => \gc0.count_d1_reg[9]\(6),
I2 => \^q\(7),
I3 => \gc0.count_d1_reg[9]\(7),
O => ram_empty_i_reg_2
);
\gmux.gm[4].gms.ms_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_0(4)
);
\gmux.gm[4].gms.ms_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_reg[9]\(9),
O => v1_reg(4)
);
\gmux.gm[4].gms.ms_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_12_out(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => p_12_out(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => v1_reg_1(4)
);
\gmux.gm[4].gms.ms_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(8),
I1 => \gc0.count_d1_reg[9]\(8),
I2 => \^q\(9),
I3 => \gc0.count_d1_reg[9]\(9),
O => ram_empty_i_reg_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 35 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 35 downto 0 )
);
end fifo_generator_0_blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_0_blk_mem_gen_prim_wrapper
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_0_blk_mem_gen_prim_width__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 27 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 27 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \fifo_generator_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \fifo_generator_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\fifo_generator_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(27 downto 0) => din(27 downto 0),
dout(27 downto 0) => dout(27 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_rd_status_flags_ss is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : out STD_LOGIC;
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end fifo_generator_0_rd_status_flags_ss;
architecture STRUCTURE of fifo_generator_0_rd_status_flags_ss is
signal c1_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= ram_empty_i;
\out\ <= ram_empty_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => srst,
I1 => ram_empty_fb_i,
I2 => rd_en,
O => tmp_ram_rd_en
);
c1: entity work.fifo_generator_0_compare_1
port map (
comp1 => comp1,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => ram_empty_fb_i,
ram_empty_i_reg => c1_n_0,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
wr_en => wr_en
);
c2: entity work.fifo_generator_0_compare_2
port map (
comp1 => comp1,
v1_reg(4 downto 0) => v1_reg(4 downto 0)
);
\gc0.count_d1[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_fb_i,
S => srst
);
ram_empty_i_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => c1_n_0,
Q => ram_empty_i,
S => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_wr_status_flags_ss is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
v1_reg_0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC
);
end fifo_generator_0_wr_status_flags_ss;
architecture STRUCTURE of fifo_generator_0_wr_status_flags_ss is
signal c0_n_0 : STD_LOGIC;
signal comp1 : STD_LOGIC;
signal ram_afull_fb : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_afull_fb : signal is std.standard.true;
signal ram_afull_i : STD_LOGIC;
attribute DONT_TOUCH of ram_afull_i : signal is std.standard.true;
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
full <= ram_full_i;
\out\ <= ram_full_fb_i;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => ram_full_fb_i,
O => E(0)
);
c0: entity work.fifo_generator_0_compare
port map (
comp1 => comp1,
\out\ => ram_full_fb_i,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
ram_full_fb_i_reg => c0_n_0,
rd_en => rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
c1: entity work.fifo_generator_0_compare_0
port map (
comp1 => comp1,
v1_reg_0(4 downto 0) => v1_reg_0(4 downto 0)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_i
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => ram_afull_fb
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_fb_i,
R => srst
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => c0_n_0,
Q => ram_full_i,
R => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_0_blk_mem_gen_prim_width
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(35 downto 0) => din(35 downto 0),
dout(35 downto 0) => dout(35 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\ramloop[1].ram.r\: entity work.\fifo_generator_0_blk_mem_gen_prim_width__parameterized0\
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(27 downto 0) => din(63 downto 36),
dout(27 downto 0) => dout(63 downto 36),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_rd_logic is
port (
\out\ : out STD_LOGIC;
empty : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : out STD_LOGIC_VECTOR ( 9 downto 0 );
\gcc0.gc0.count_d1_reg[0]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[2]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[4]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[6]\ : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[8]\ : in STD_LOGIC;
v1_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
srst : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC
);
end fifo_generator_0_rd_logic;
architecture STRUCTURE of fifo_generator_0_rd_logic is
signal \grss.rsts_n_2\ : STD_LOGIC;
begin
\grss.rsts\: entity work.fifo_generator_0_rd_status_flags_ss
port map (
E(0) => \grss.rsts_n_2\,
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gcc0.gc0.count_d1_reg[0]\,
\gcc0.gc0.count_d1_reg[2]\ => \gcc0.gc0.count_d1_reg[2]\,
\gcc0.gc0.count_d1_reg[4]\ => \gcc0.gc0.count_d1_reg[4]\,
\gcc0.gc0.count_d1_reg[6]\ => \gcc0.gc0.count_d1_reg[6]\,
\gcc0.gc0.count_d1_reg[8]\ => \gcc0.gc0.count_d1_reg[8]\,
\out\ => \out\,
ram_full_fb_i_reg => ram_full_fb_i_reg,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
wr_en => wr_en
);
rpntr: entity work.fifo_generator_0_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0),
E(0) => \grss.rsts_n_2\,
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
srst => srst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_wr_logic is
port (
\out\ : out STD_LOGIC;
full : out STD_LOGIC;
WEA : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
v1_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC;
ram_empty_i_reg_1 : out STD_LOGIC;
ram_empty_i_reg_2 : out STD_LOGIC;
ram_empty_i_reg_3 : out STD_LOGIC;
srst : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end fifo_generator_0_wr_logic;
architecture STRUCTURE of fifo_generator_0_wr_logic is
signal \^wea\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \c0/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \c1/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
WEA(0) <= \^wea\(0);
\gwss.wsts\: entity work.fifo_generator_0_wr_status_flags_ss
port map (
E(0) => \^wea\(0),
clk => clk,
full => full,
\out\ => \out\,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_0(4 downto 0) => \c1/v1_reg\(4 downto 0),
wr_en => wr_en
);
wpntr: entity work.fifo_generator_0_wr_bin_cntr
port map (
E(0) => \^wea\(0),
Q(9 downto 0) => Q(9 downto 0),
clk => clk,
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => \gc0.count_reg[9]\(9 downto 0),
ram_empty_i_reg => ram_empty_i_reg,
ram_empty_i_reg_0 => ram_empty_i_reg_0,
ram_empty_i_reg_1 => ram_empty_i_reg_1,
ram_empty_i_reg_2 => ram_empty_i_reg_2,
ram_empty_i_reg_3 => ram_empty_i_reg_3,
srst => srst,
v1_reg(4 downto 0) => v1_reg(4 downto 0),
v1_reg_0(4 downto 0) => \c0/v1_reg\(4 downto 0),
v1_reg_1(4 downto 0) => \c1/v1_reg\(4 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_0_blk_mem_gen_generic_cstr
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_blk_mem_gen_v8_3_4_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_blk_mem_gen_v8_3_4_synth;
architecture STRUCTURE of fifo_generator_0_blk_mem_gen_v8_3_4_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_0_blk_mem_gen_top
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_blk_mem_gen_v8_3_4 is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_blk_mem_gen_v8_3_4;
architecture STRUCTURE of fifo_generator_0_blk_mem_gen_v8_3_4 is
begin
inst_blk_mem_gen: entity work.fifo_generator_0_blk_mem_gen_v8_3_4_synth
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_memory is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
clk : in STD_LOGIC;
WEA : in STD_LOGIC_VECTOR ( 0 to 0 );
tmp_ram_rd_en : in STD_LOGIC;
srst : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 9 downto 0 );
\gc0.count_d1_reg[9]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_memory;
architecture STRUCTURE of fifo_generator_0_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.fifo_generator_0_blk_mem_gen_v8_3_4
port map (
Q(9 downto 0) => Q(9 downto 0),
WEA(0) => WEA(0),
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => \gc0.count_d1_reg[9]\(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_18\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_19\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_2\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_20\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_21\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_22\ : STD_LOGIC;
signal \grss.rsts/c2/v1_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_0_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(9 downto 0) => p_0_out(9 downto 0),
Q(9 downto 0) => rd_pntr_plus1(9 downto 0),
clk => clk,
empty => empty,
\gcc0.gc0.count_d1_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_18\,
\gcc0.gc0.count_d1_reg[2]\ => \gntv_or_sync_fifo.gl0.wr_n_19\,
\gcc0.gc0.count_d1_reg[4]\ => \gntv_or_sync_fifo.gl0.wr_n_20\,
\gcc0.gc0.count_d1_reg[6]\ => \gntv_or_sync_fifo.gl0.wr_n_21\,
\gcc0.gc0.count_d1_reg[8]\ => \gntv_or_sync_fifo.gl0.wr_n_22\,
\out\ => p_2_out,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_0\,
rd_en => rd_en,
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_0_wr_logic
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
full => full,
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
\gc0.count_reg[9]\(9 downto 0) => rd_pntr_plus1(9 downto 0),
\out\ => \gntv_or_sync_fifo.gl0.wr_n_0\,
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gntv_or_sync_fifo.gl0.wr_n_18\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gl0.wr_n_19\,
ram_empty_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_20\,
ram_empty_i_reg_2 => \gntv_or_sync_fifo.gl0.wr_n_21\,
ram_empty_i_reg_3 => \gntv_or_sync_fifo.gl0.wr_n_22\,
rd_en => rd_en,
srst => srst,
v1_reg(4 downto 0) => \grss.rsts/c2/v1_reg\(4 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_0_memory
port map (
Q(9 downto 0) => p_11_out(9 downto 0),
WEA(0) => \gntv_or_sync_fifo.gl0.wr_n_2\,
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
\gc0.count_d1_reg[9]\(9 downto 0) => p_0_out(9 downto 0),
srst => srst,
tmp_ram_rd_en => tmp_ram_rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_fifo_generator_top;
architecture STRUCTURE of fifo_generator_0_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_0_fifo_generator_ramfifo
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_fifo_generator_v13_1_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 )
);
end fifo_generator_0_fifo_generator_v13_1_2_synth;
architecture STRUCTURE of fifo_generator_0_fifo_generator_v13_1_2_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_0_fifo_generator_top
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0_fifo_generator_v13_1_2 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of fifo_generator_0_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of fifo_generator_0_fifo_generator_v13_1_2 : entity is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of fifo_generator_0_fifo_generator_v13_1_2 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of fifo_generator_0_fifo_generator_v13_1_2 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of fifo_generator_0_fifo_generator_v13_1_2 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of fifo_generator_0_fifo_generator_v13_1_2 : entity is 1;
end fifo_generator_0_fifo_generator_v13_1_2;
architecture STRUCTURE of fifo_generator_0_fifo_generator_v13_1_2 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_0_fifo_generator_v13_1_2_synth
port map (
clk => clk,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
srst => srst,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0 is
port (
clk : in STD_LOGIC;
srst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 63 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 63 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_0 : entity is "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_0 : entity is "fifo_generator_v13_1_2,Vivado 2016.3";
end fifo_generator_0;
architecture STRUCTURE of fifo_generator_0 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 1;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 64;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 1;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.fifo_generator_0_fifo_generator_v13_1_2
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(9 downto 0) => NLW_U0_data_count_UNCONNECTED(9 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(63 downto 0) => din(63 downto 0),
dout(63 downto 0) => dout(63 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => srst,
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(9 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(9 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:13:17 10/06/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/P16_Counter_0_to_19_simulated/Counter_TB.vhd
-- Project Name: P16_Counter_0_to_19_simulated
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Counter_0_to_19
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Counter_TB IS
END Counter_TB;
ARCHITECTURE behavior OF Counter_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Counter_0_to_19
PORT(
Clk : IN std_logic;
Q : OUT std_logic_vector(4 downto 0);
Rst : IN std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
--Outputs
signal Q : std_logic_vector(4 downto 0);
-- Clock period definitions
constant Clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Counter_0_to_19 PORT MAP (
Clk => Clk,
Q => Q,
Rst => Rst
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*1;
-- insert stimulus here
-- reset the counter
Rst <= '1';
wait for 100 ns;
-- counter working
Rst <= '0';
wait for 100 ns;
wait;
end process;
END;
|
--------------------------------------------------------------------------------------------------------------
-- Hazard Detection Unit
-- This unit is the Hazard Detection Unit. It works in tight collaboration with the forwarding unit in the
-- EX stage. Since most of the data hazards are solved by the forwarding unit, the control hazards have their
-- own hazard detection unit, this unit is in charge for checking and solving(by forcing a nop and freezing
-- the decode and fetch stage) hazards due to MEM instruction followed by an ALU instruction
--------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
entity hdu is
port (
-- INPUTS
clk : in std_logic; -- global clock signal
rst : in std_logic; -- global reset signal
idex_mem_read : in std_logic_vector(3 downto 0); -- ID/EX MemRead control signals (lbu, lw, lhu, lb)
idex_rt : in std_logic_vector(4 downto 0); -- ID/EX Rt address
rs : in std_logic_vector(4 downto 0); -- Rs address instruction (25-21)
rt : in std_logic_vector(4 downto 0); -- Rt address instruction (20-16)
-- OUTPUTS
pcwrite : out std_logic; -- control signal write enable for the PC register
ifidwrite : out std_logic; -- control signal write enable for the pipeline register IF/ID
mux_op : out std_logic -- control signal directed to the mux stall
);
end hdu;
-----------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------
architecture behavioral of hdu is
-- Sub-type declarations
type state_type is (RESET, CHECK, STALL);
-- Current state signal
signal current_state : state_type;
-- Next state signal
signal next_state : state_type;
-- Internal signals
signal lbu_i : std_logic;
signal lw_i : std_logic;
signal lhu_i : std_logic;
signal lb_i : std_logic;
begin
-- Cuncurrent statement
lbu_i <= idex_mem_read(3);
lw_i <= idex_mem_read(2);
lhu_i <= idex_mem_read(1);
lb_i <= idex_mem_read(0);
-------------------------
-- State Register
-- Type: Sequential
-- Reset: Synchronous
-- Purpose: Implement
-- state register
-------------------------
state_reg:process(clk)
begin
if(clk = '1' and clk'event) then
if (rst = '1') then
current_state <= RESET;
else
current_state <= next_state;
end if;
end if;
end process;
-----------------------------
-- Comb Logic
-- Type: Combinational
-- Purpose: Implement the
-- combinational logic of
-- the FSM.
-- Note that the FSM is a
-- Melay machine.
-----------------------------
comb_logic:process(lbu_i, lw_i, lhu_i, lb_i, idex_rt,rs,rt, current_state)
begin
case current_state is
when RESET =>
pcwrite <= '1';
ifidwrite <= '1';
mux_op <= '0';
next_state <= CHECK;
when CHECK =>
if ( ((lbu_i = '1') or (lw_i = '1') or (lhu_i = '1') or (lb_i = '1')) and
( (idex_rt = rs) or (idex_rt = rt) ) ) then
pcwrite <= '0';
ifidwrite <= '0';
mux_op <= '1';
next_state <= STALL;
else
pcwrite <= '1';
ifidwrite <= '1';
mux_op <= '0';
next_state <= CHECK;
end if;
when STALL =>
pcwrite <= '1';
ifidwrite <= '1';
mux_op <= '0';
next_state <= CHECK;
when others =>
pcwrite <= '0';
ifidwrite <= '0';
mux_op <= '0';
next_state <= RESET;
end case;
end process;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc270.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p05n01i00270ent IS
END c03s01b03x00p05n01i00270ent;
ARCHITECTURE c03s01b03x00p05n01i00270arch OF c03s01b03x00p05n01i00270ent IS
type T is
range 1 to 100
units
I ;
J = 2 I;
K = 2 P; -- Failure_here
L = 10 K;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p05n01i00270 - Improper unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p05n01i00270arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc270.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p05n01i00270ent IS
END c03s01b03x00p05n01i00270ent;
ARCHITECTURE c03s01b03x00p05n01i00270arch OF c03s01b03x00p05n01i00270ent IS
type T is
range 1 to 100
units
I ;
J = 2 I;
K = 2 P; -- Failure_here
L = 10 K;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p05n01i00270 - Improper unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p05n01i00270arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc270.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p05n01i00270ent IS
END c03s01b03x00p05n01i00270ent;
ARCHITECTURE c03s01b03x00p05n01i00270arch OF c03s01b03x00p05n01i00270ent IS
type T is
range 1 to 100
units
I ;
J = 2 I;
K = 2 P; -- Failure_here
L = 10 K;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b03x00p05n01i00270 - Improper unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p05n01i00270arch;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(2);
sub_wire4 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
locked <= sub_wire3;
c0 <= sub_wire4;
c2 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 2,
clk2_duty_cycle => 50,
clk2_multiply_by => 5,
clk2_phase_shift => "0",
clk3_divide_by => 2,
clk3_duty_cycle => 50,
clk3_multiply_by => 1,
clk3_phase_shift => "0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV GX",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NO_COMPENSATION",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "2"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "25.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "5"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: ahb2mig_grxc6s_2p
-- File: ahb2mig_grxc6s_2p.vhd
-- Author: Jiri Gaisler - Aeroflex Gaisler AB
--
-- This is a AHB-2.0 interface for the Xilinx Spartan-6 MIG.
-- One bidir 32-bit port is used for the main AHB bus, while
-- a second read-only port can be enabled for a VGA frame buffer.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahb2mig_grxc6s_2p is
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
vgamst : integer := 0;
vgaburst : integer := 0;
clkdiv : integer := 2
);
port(
mcb3_dram_dq : inout std_logic_vector(15 downto 0);
mcb3_dram_a : out std_logic_vector(12 downto 0);
mcb3_dram_ba : out std_logic_vector(2 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbmi : out ahb_mst_in_type;
ahbmo : in ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
test_error : out std_logic;
rst_n_syn : out std_logic;
rst_n_async : in std_logic;
clk_amba : out std_logic;
clk_mem_n : in std_logic;
clk_mem_p : in std_logic;
clk_125 : out std_logic;
clk_100 : out std_logic
);
end ;
architecture rtl of ahb2mig_grxc6s_2p is
component mig_37
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000; -- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0; -- # = 1 for active low reset, -- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED"; -- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE"; -- # = TRUE, Enables the soft calibration logic, -- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE"; -- # = TRUE, Simulating the design. Useful to reduce the simulation time, -- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0; -- # = 1, Enable debug signals/controls, -- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- The order in which user address is provided to the memory controller, -- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16; -- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13; -- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3; -- External memory bank address width.
C3_CLKOUT5_DIVIDE : integer := 10 -- Extra clock divider
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
clk_125 : out std_logic; -- 125 MHz for RGMII
clk_100 : out std_logic; -- Extra clock
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic
);
end component;
type bstate_type is (idle, start, read1);
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
-- 5 => ahb_iobar(ioaddr, iomask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hwrite : std_logic;
htrans : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hsize : std_logic_vector(2 downto 0);
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
hmaster : std_logic_vector(3 downto 0);
end record;
type mcb_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
cmd_bl : std_logic_vector(5 downto 0);
cmd_byte_addr : std_logic_vector(29 downto 0);
wr_full : std_logic;
wr_empty : std_logic;
wr_underrun : std_logic;
wr_error : std_logic;
wr_mask : std_logic_vector(3 downto 0);
wr_en : std_logic;
wr_data : std_logic_vector(31 downto 0);
wr_count : std_logic_vector(6 downto 0);
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
rd_en : std_logic;
end record;
type reg2_type is record
bstate : bstate_type;
cmd_bl : std_logic_vector(5 downto 0);
rd_cnt : std_logic_vector(5 downto 0);
hready : std_logic;
hsel : std_logic;
hrdata : std_logic_vector(31 downto 0);
haddr : std_logic_vector(31 downto 0);
end record;
type p2_if_type is record
cmd_en : std_logic;
cmd_instr : std_logic_vector(2 downto 0);
cmd_bl : std_logic_vector(5 downto 0);
cmd_empty : std_logic;
cmd_full : std_logic;
rd_en : std_logic;
rd_data : std_logic_vector(31 downto 0);
rd_full : std_logic;
rd_empty : std_logic;
rd_count : std_logic_vector(6 downto 0);
rd_overflow : std_logic;
rd_error : std_logic;
end record;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
signal i : mcb_type;
signal p2 : p2_if_type;
signal clk_amba_i : std_logic;
signal rst_n_syn_i : std_logic;
signal rst_syn : std_logic;
signal calib_done_i : std_logic;
begin
clk_amba <= clk_amba_i;
rst_n_syn <= rst_n_syn_i and calib_done_i;
rst_n_syn_i <= not rst_syn;
calib_done <= calib_done_i;
comb: process( rst_n_syn_i, r, ahbsi, i )
variable v : reg_type;
variable wmask : std_logic_vector(3 downto 0);
variable wr_en : std_logic;
variable cmd_en : std_logic;
variable cmd_instr : std_logic_vector(2 downto 0);
variable rd_en : std_logic;
variable cmd_bl : std_logic_vector(5 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
variable readdata : std_logic_vector(31 downto 0);
begin
v := r; wr_en := '0'; cmd_en := '0'; cmd_instr := "000";
rd_en := '0';
if (ahbsi.hready = '1') then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hsel := '1'; v.hburst := ahbsi.hburst;
v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize;
v.hmaster := ahbsi.hmaster;
v.hready := '0';
if ahbsi.htrans(0) = '0' then v.haddr := ahbsi.haddr; end if;
else
v.hsel := '0'; v.hready := '1';
end if;
v.htrans := ahbsi.htrans;
end if;
hwdata := ahbsi.hwdata(15 downto 0) & ahbsi.hwdata(31 downto 16);
case r.hsize(1 downto 0) is
when "00" => wmask := not decode(r.haddr(1 downto 0));
case r.haddr(1 downto 0) is
when "00" => wmask := "1101";
when "01" => wmask := "1110";
when "10" => wmask := "0111";
when others => wmask := "1011";
end case;
when "01" => wmask := not decode(r.haddr(1 downto 0));
wmask(3) := wmask(2); wmask(1) := wmask(0);
when others => wmask := "0000";
end case;
i.wr_mask <= wmask;
cmd_bl := r.cmd_bl;
case r.bstate is
when idle =>
if v.hsel = '1' then
v.bstate := start;
v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.haddr := ahbsi.haddr;
end if;
v.cmd_bl := (others => '0');
when start =>
if r.hwrite = '1' then
v.haddr := r.haddr;
if r.hready = '1' then
v.cmd_bl := r.cmd_bl + 1; v.hready := '1'; wr_en := '1';
if (ahbsi.htrans /= "11") then
if v.hsel = '1' then
if (ahbsi.hwrite = '0') or (i.wr_count >= "0000100") then
v.hready := '0';
else v.hready := '1'; end if;
else v.bstate := idle; end if;
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
cmd_en := '1';
elsif (i.cmd_full = '1') then
v.hready := '0';
elsif (i.wr_count >= "0101111") then
v.hready := '0'; cmd_en := '1';
v.cmd_bl := (others => '0'); v.haddr := ahbsi.haddr;
end if;
else
if (i.cmd_full = '0') and (i.wr_count <= "0001111") then
v.hready := '1';
end if;
end if;
else
if i.cmd_full = '0' then
cmd_en := '1'; cmd_instr(0) := '1';
v.cmd_bl := "000" & not r.haddr(4 downto 2);
cmd_bl := v.cmd_bl;
v.bstate := read1;
end if;
end if;
when read1 =>
v.hready := '0';
if (r.rd_cnt = "000000") then -- flush data from previous line
if (i.rd_empty = '0') or ((r.hready = '1') and (ahbsi.htrans /= "11")) then
v.hrdata(31 downto 0) := i.rd_data(15 downto 0) & i.rd_data(31 downto 16);
v.hready := '1';
if (i.rd_empty = '0') then v.cmd_bl := r.cmd_bl - 1; rd_en := '1'; end if;
if (r.cmd_bl = "000000") or (ahbsi.htrans /= "11") then
if (ahbsi.hsel(hindex) = '1') and (ahbsi.htrans = "10") and (r.hready = '1') then
v.bstate := start; v.hready := ahbsi.hwrite and not i.cmd_full and not i.wr_full;
v.cmd_bl := (others => '0');
else
v.bstate := idle;
end if;
if (i.rd_empty = '1') then v.rd_cnt := r.cmd_bl + 1;
else v.rd_cnt := r.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
readdata := (others => '0');
-- case apbi.paddr(5 downto 2) is
-- when "0000" => readdata(nbits-1 downto 0) := r.din2;
-- when "0001" => readdata(nbits-1 downto 0) := r.dout;
-- when others =>
-- end case;
readdata(20 downto 0) :=
i.rd_error & i.rd_overflow & i.wr_error & i.wr_underrun &
i.cmd_full & i.rd_full & i.rd_empty & i.wr_full & i.wr_empty &
r.rd_cnt & r.cmd_bl;
if (r.rd_cnt /= "000000") and (i.rd_empty = '0') then
rd_en := '1'; v.rd_cnt := r.rd_cnt - 1;
end if;
if rst_n_syn_i = '0' then
v.rd_cnt := "000000"; v.bstate := idle; v.hready := '1';
end if;
rin <= v;
apbo.prdata <= readdata;
i.rd_en <= rd_en;
i.wr_en <= wr_en;
i.cmd_bl <= cmd_bl;
i.cmd_en <= cmd_en;
i.cmd_instr <= cmd_instr;
i.wr_data <= hwdata;
end process;
i.cmd_byte_addr <= r.haddr(29 downto 2) & "00";
ahbso.hready <= r.hready;
ahbso.hresp <= "00"; --r.hresp;
ahbso.hrdata <= r.hrdata;
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbso.hsplit <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
regs : process(clk_amba_i)
begin
if rising_edge(clk_amba_i) then
r <= rin;
end if;
end process;
port2 : if vgamst /= 0 generate
comb2: process( rst_n_syn_i, r2, ahbmo, p2 )
variable v2 : reg2_type;
variable cmd_en : std_logic;
variable rd_en : std_logic;
begin
v2 := r2; cmd_en := '0'; rd_en := '0';
case r2.bstate is
when idle =>
if ahbmo.htrans(1) = '1' then
v2.bstate := start;
v2.hready := '0';
v2.haddr := ahbmo.haddr;
else v2.hready := '1'; end if;
v2.cmd_bl := (others => '0');
when start =>
if p2.cmd_full = '0' then
cmd_en := '1';
v2.cmd_bl := conv_std_logic_vector(vgaburst-1, 6);
v2.bstate := read1;
end if;
when read1 =>
v2.hready := '0';
if (r2.rd_cnt = "000000") then -- flush data from previous line
if (p2.rd_empty = '0') or ((r2.hready = '1') and (ahbmo.htrans /= "11")) then
v2.hrdata(31 downto 0) := p2.rd_data(15 downto 0) & p2.rd_data(31 downto 16);
v2.hready := '1';
if (p2.rd_empty = '0') then v2.cmd_bl := r2.cmd_bl - 1; rd_en := '1'; end if;
if (r2.cmd_bl = "000000") or (ahbmo.htrans /= "11") then
if (ahbmo.htrans = "10") and (r2.hready = '1') then
v2.bstate := start; v2.hready := '0';
v2.cmd_bl := (others => '0');
else
v2.bstate := idle;
end if;
if (p2.rd_empty = '1') then v2.rd_cnt := r2.cmd_bl + 1;
else v2.rd_cnt := r2.cmd_bl; end if;
end if;
end if;
end if;
when others =>
end case;
if (r2.rd_cnt /= "000000") and (p2.rd_empty = '0') then
rd_en := '1'; v2.rd_cnt := r2.rd_cnt - 1;
end if;
v2.haddr(1 downto 0) := "00";
if rst_n_syn_i = '0' then
v2.rd_cnt := "000000"; v2.bstate := idle; v2.hready := '1';
end if;
r2in <= v2;
p2.rd_en <= rd_en;
p2.cmd_bl <= v2.cmd_bl;
p2.cmd_en <= cmd_en;
p2.cmd_instr <= "001";
end process;
ahbmi.hrdata <= r2.hrdata;
ahbmi.hresp <= "00";
ahbmi.hgrant <= (others => '1');
ahbmi.hready <= r2.hready;
ahbmi.testen <= '0';
ahbmi.testrst <= '0';
ahbmi.scanen <= '0';
ahbmi.testoen <= '0';
ahbmi.hirq <= (others => '0');
ahbmi.testin <= (others => '0');
regs : process(clk_amba_i)
begin
if rising_edge(clk_amba_i) then
r2 <= r2in;
end if;
end process;
end generate;
noport2 : if vgamst = 0 generate
p2.cmd_en <= '0';
p2.rd_en <= '0';
end generate;
MCB_inst : mig_37 generic map(
C3_P0_MASK_SIZE => 4,
C3_P0_DATA_PORT_SIZE => 32,
C3_P1_MASK_SIZE => 4,
C3_P1_DATA_PORT_SIZE => 32,
C3_MEMCLK_PERIOD => 4000,
C3_RST_ACT_LOW => 1,
-- C3_INPUT_CLK_TYPE => "DIFFERENTIAL",
C3_CALIB_SOFT_IP => "TRUE",
-- pragma translate_off
C3_SIMULATION => "TRUE",
-- pragma translate_on
C3_MEM_ADDR_ORDER => "BANK_ROW_COLUMN",
C3_NUM_DQ_PINS => 16,
C3_MEM_ADDR_WIDTH => 13,
C3_MEM_BANKADDR_WIDTH => 3,
C3_CLKOUT5_DIVIDE => clkdiv
-- C3_MC_CALIB_BYPASS => "YES"
)
port map (
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
-- c3_sys_clk_p => clk_mem_p,
-- c3_sys_clk_n => clk_mem_n,
c3_sys_clk => clk_mem_p,
c3_sys_rst_n => rst_n_async,
c3_calib_done => calib_done_i,
c3_clk0 => clk_amba_i,
c3_rst0 => rst_syn,
clk_125 => clk_125,
clk_100 => clk_100,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
c3_p0_cmd_clk => clk_amba_i,
c3_p0_cmd_en => i.cmd_en,
c3_p0_cmd_instr => i.cmd_instr,
c3_p0_cmd_bl => i.cmd_bl,
c3_p0_cmd_byte_addr => i.cmd_byte_addr,
c3_p0_cmd_empty => i.cmd_empty,
c3_p0_cmd_full => i.cmd_full,
c3_p0_wr_clk => clk_amba_i,
c3_p0_wr_en => i.wr_en,
c3_p0_wr_mask => i.wr_mask,
c3_p0_wr_data => i.wr_data,
c3_p0_wr_full => i.wr_full,
c3_p0_wr_empty => i.wr_empty,
c3_p0_wr_count => i.wr_count,
c3_p0_wr_underrun => i.wr_underrun,
c3_p0_wr_error => i.wr_error,
c3_p0_rd_clk => clk_amba_i,
c3_p0_rd_en => i.rd_en,
c3_p0_rd_data => i.rd_data,
c3_p0_rd_full => i.rd_full,
c3_p0_rd_empty => i.rd_empty,
c3_p0_rd_count => i.rd_count,
c3_p0_rd_overflow => i.rd_overflow,
c3_p0_rd_error => i.rd_error,
c3_p2_cmd_clk => clk_amba_i,
c3_p2_cmd_en => p2.cmd_en,
c3_p2_cmd_instr => p2.cmd_instr,
c3_p2_cmd_bl => p2.cmd_bl,
c3_p2_cmd_byte_addr => r2.haddr(29 downto 0),
c3_p2_cmd_empty => p2.cmd_empty,
c3_p2_cmd_full => p2.cmd_full,
c3_p2_rd_clk => clk_amba_i,
c3_p2_rd_en => p2.rd_en,
c3_p2_rd_data => p2.rd_data,
c3_p2_rd_full => p2.rd_full,
c3_p2_rd_empty => p2.rd_empty,
c3_p2_rd_count => p2.rd_count,
c3_p2_rd_overflow => p2.rd_overflow,
c3_p2_rd_error => p2.rd_error
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use work.memory_types.all;
entity test_rom is
end test_rom;
architecture behavioural of test_rom is
component ROM is
generic (
contents: memory_16b
);
port (
clock : in std_logic;
address : in std_logic_vector(3 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
signal clock : std_logic;
signal addr : std_logic_vector(3 downto 0);
signal output : std_logic_vector(7 downto 0);
constant test_storage : memory_16b := read_mem("rom_lut.mif");
begin
romcell : ROM generic map (test_storage)
port map (clock, addr, output);
process
begin
addr <= "0000";
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000000"
report "result should be 0" severity error;
addr <= "0001";
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000001"
report "result should be 1" severity error;
addr <= "1001";
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "11110000"
report "result should be big" severity error;
wait;
end process;
end behavioural;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: dltj007@gmail.com
-- Date : 08/07/2015 - 19:11
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MX_5 IS
PORT(
MemtoReg : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END MX_5;
ARCHITECTURE ARC_MX_5 OF MX_5 IS
BEGIN
OUT_A <= IN_B WHEN MemtoReg = '0' ELSE IN_A;
END ARC_MX_5;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Computes the Cyclic Redundancy Check (CRC)
--
-- Description:
-- ------------------------------------
-- Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder
-- of the polynomial division of the message by the given generator
-- polynomial (GEN).
--
-- The computation is unrolled so as to process an arbitrary number of
-- message bits per step. The generated CRC is independent from the chosen
-- processing width.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
entity comm_crc is
generic (
GEN : bit_vector; -- Generator Polynomial
BITS : positive; -- Number of Bits to be processed in parallel
STARTUP_RMD : std_logic_vector := "0";
OUTPUT_REGS : boolean := true
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Parallel Preload of Remainder
init : in std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); --
step : in std_logic; -- Process Input Data (MSB first)
din : in std_logic_vector(BITS-1 downto 0); --
rmd : out std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- Remainder
zero : out std_logic -- Remainder is Zero
);
end comm_crc;
architecture rtl of comm_crc is
-----------------------------------------------------------------------------
-- Normalizes the generator representation:
-- - into a 'downto 0' index range and
-- - truncating it just below the most significant and so hidden '1'.
function normalize(G : bit_vector) return bit_vector is
variable GN : bit_vector(G'length-1 downto 0);
begin
GN := G;
for i in GN'left downto 1 loop
if GN(i) = '1' then
return GN(i-1 downto 0);
end if;
end loop;
report "Cannot use absolute constant as generator."
severity failure;
return GN;
end normalize;
-- Normalized Generator
constant GN : std_logic_vector := to_stdlogicvector(normalize(GEN));
-- LFSR Value
signal lfsr : std_logic_vector(GN'range) := resize(descend(STARTUP_RMD), GN'length);
signal lfsn : std_logic_vector(GN'range); -- Next Value
signal lfso : std_logic_vector(GN'range); -- Output
begin
-- Compute next combinational Value
process(lfsr, din)
variable v : std_logic_vector(lfsr'range);
begin
v := lfsr;
for i in BITS-1 downto 0 loop
v := (v(v'left-1 downto 0) & '0') xor
(GN and (GN'range => (din(i) xor v(v'left))));
end loop;
lfsn <= v;
end process;
-- Remainder Register
process(clk)
begin
if rising_edge(clk) then
if set = '1' then
lfsr <= init(lfsr'range);
elsif step = '1' then
lfsr <= lfsn;
end if;
end if;
end process;
-- Provide Outputs
lfso <= lfsr when OUTPUT_REGS else lfsn;
rmd <= lfso;
zero <= '1' when lfso = (lfso'range => '0') else '0';
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Patrick Lehmann
--
-- Module: Computes the Cyclic Redundancy Check (CRC)
--
-- Description:
-- ------------------------------------
-- Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder
-- of the polynomial division of the message by the given generator
-- polynomial (GEN).
--
-- The computation is unrolled so as to process an arbitrary number of
-- message bits per step. The generated CRC is independent from the chosen
-- processing width.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
entity comm_crc is
generic (
GEN : bit_vector; -- Generator Polynomial
BITS : positive; -- Number of Bits to be processed in parallel
STARTUP_RMD : std_logic_vector := "0";
OUTPUT_REGS : boolean := true
);
port (
clk : in std_logic; -- Clock
set : in std_logic; -- Parallel Preload of Remainder
init : in std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); --
step : in std_logic; -- Process Input Data (MSB first)
din : in std_logic_vector(BITS-1 downto 0); --
rmd : out std_logic_vector(abs(mssb_idx(GEN)-GEN'right)-1 downto 0); -- Remainder
zero : out std_logic -- Remainder is Zero
);
end comm_crc;
architecture rtl of comm_crc is
-----------------------------------------------------------------------------
-- Normalizes the generator representation:
-- - into a 'downto 0' index range and
-- - truncating it just below the most significant and so hidden '1'.
function normalize(G : bit_vector) return bit_vector is
variable GN : bit_vector(G'length-1 downto 0);
begin
GN := G;
for i in GN'left downto 1 loop
if GN(i) = '1' then
return GN(i-1 downto 0);
end if;
end loop;
report "Cannot use absolute constant as generator."
severity failure;
return GN;
end normalize;
-- Normalized Generator
constant GN : std_logic_vector := to_stdlogicvector(normalize(GEN));
-- LFSR Value
signal lfsr : std_logic_vector(GN'range) := resize(descend(STARTUP_RMD), GN'length);
signal lfsn : std_logic_vector(GN'range); -- Next Value
signal lfso : std_logic_vector(GN'range); -- Output
begin
-- Compute next combinational Value
process(lfsr, din)
variable v : std_logic_vector(lfsr'range);
begin
v := lfsr;
for i in BITS-1 downto 0 loop
v := (v(v'left-1 downto 0) & '0') xor
(GN and (GN'range => (din(i) xor v(v'left))));
end loop;
lfsn <= v;
end process;
-- Remainder Register
process(clk)
begin
if rising_edge(clk) then
if set = '1' then
lfsr <= init(lfsr'range);
elsif step = '1' then
lfsr <= lfsn;
end if;
end if;
end process;
-- Provide Outputs
lfso <= lfsr when OUTPUT_REGS else lfsn;
rmd <= lfso;
zero <= '1' when lfso = (lfso'range => '0') else '0';
end rtl;
|
-- NICSim-vhd: A VHDL-based modelling and simulation of NIC's buffers
-- Copyright (C) 2013 Godofredo R. Garay <godofredo.garay (-at-) gmail.com>
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
entity dmactrl is
port (
payload_transfer_req : in bit;
descriptor_transfer_req : in bit;
payload_transfer_end : out bit := '0';
descriptor_transfer_end : out bit := '0';
payload_transfer_aborted : out bit := '0';
descriptor_transfer_aborted : out bit := '0';
resume_aborted_payload_transfer : in bit;
resume_aborted_descriptor_transfer : in bit;
irdy : in bit;
trdy : in bit;
gnt : in bit;
payload_size_in_data_blocks : in integer;
dma_cycles_counter_out : out integer := 0;
burst_cycles_counter_out : out integer := 0;
pciclk : in bit
);
end dmactrl;
architecture V1 of dmactrl is
--------------- Bus width configuration ---------------
--constant bus_width_in_bits : integer := 32; -- PCI 33/32
constant bus_width_in_bits : integer := 64; -- PCI 66/64, PCI-X 133/64
constant bus_width_in_bytes : integer := bus_width_in_bits/8;
-- ***To be removed
--constant bus_width_in_bytes : integer := 4; -- PCI bus
--constant bus_width_in_bytes : integer := 8; -- PCI-X bus
--------------- Burst size configuration ---------------
constant dma_burst_size_in_bytes : integer := 256; -- DMA busrt size = 256 bytes
--constant dma_burst_size_in_bytes : integer := 512; -- DMA busrt size = 512 bytes
--constant dma_burst_size_in_bytes : integer := 1024; -- DMA busrt size = 1024 bytes
--constant dma_burst_size_in_bytes : integer := 2048; -- DMA busrt size = 2048 bytes
--constant dma_burst_size_in_bytes : integer := 2048; -- DMA busrt size = 4096 bytes
constant dma_burst_size_in_cycles : integer := dma_burst_size_in_bytes/bus_width_in_bytes;
--constant dma_burst_size_in_cycles : integer := 64; -- DMA busrt size = 512 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 128; -- DMA busrt size = 1024 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 256; -- DMA busrt size = 2048 bytes (PCI-X bus)
--constant dma_burst_size_in_cycles : integer := 512; -- DMA busrt size = 4096 bytes (PCI-X bus)
--------------- Descriptor size configuration ---------------
--constant descriptor_size_in_data_blocks : integer := 2; -- Descriptor size in data blocks (PCI-X bus)
--constant descriptor_size_in_data_blocks : integer := 4; -- Descriptor size in data blocks (PCI bus)
constant descriptor_size_in_bytes : integer := 16; -- Descriptor size in bytes
constant descriptor_size_in_data_blocks : integer := descriptor_size_in_bytes/bus_width_in_bytes;
--------------- Injection rate configuration ---------------
-- ******* To be used in the future, not implemented yet...
--constant nic_injection_rate : natural := 1; -- NIC/PCI bus bandwidth ratio
constant nic_injection_rate : natural := 1; -- NIC/PCI bus bandwidth ratio
-- ****** In the future, constant pcilck_period should be removed a function based on the pciclk signal should be implemented
--constant pciclk_period : time := 0.03030303 us; -- PCI 33
--constant pciclk_period : time := 0.015151515 us; -- PCI 66
constant pciclk_period : time := 0.007518797 us; -- PCI-X 133
--constant pciclk_period : time := 0.003759398 us; -- PCI-X 266
--constant pciclk_period : time := 0.001876173 us; -- PCI-X 533
--------------- Variables Declarations ---------------
shared variable burst_cycles_counter : integer;
-- A variable is declared for each output signal.
shared variable payload_transfer_end_value : bit := '0';
shared variable descriptor_transfer_end_value : bit := '0';
shared variable payload_transfer_aborted_value : bit := '0';
shared variable descriptor_transfer_aborted_value : bit := '0';
shared variable dma_cycles_counter : integer := 0;
begin
dma_controller_fsm: process
type controller_state is (idle,
transferring_payload,
transferring_descriptor,
transferring_payload_stalled,
transferring_descriptor_stalled);
variable state : controller_state := idle;
variable next_state : controller_state := idle;
begin
wait until pciclk'event and pciclk = '1';
case state is
when idle =>
payload_transfer_end_value := '0';
descriptor_transfer_end_value := '0';
payload_transfer_aborted_value := '0';
descriptor_transfer_aborted_value := '0';
burst_cycles_counter := 0;
if payload_transfer_req = '1'
and descriptor_transfer_req = '1'
and resume_aborted_payload_transfer = '1'
and resume_aborted_descriptor_transfer = '1'
then next_state := idle;
elsif payload_transfer_req = '0'
--and descriptor_transfer_req = '1'
and irdy = '0'
and trdy = '0'
--and dma_cycles_counter = 0
then dma_cycles_counter := payload_size_in_data_blocks;
burst_cycles_counter := dma_burst_size_in_cycles;
assert false
report "dma_controller_fsm: transferring_payload"
severity note;
next_state := transferring_payload;
elsif payload_transfer_req = '0'
--and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
-- Descriptor transfer
elsif descriptor_transfer_req = '0'
and payload_transfer_req = '1'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter = 0
then dma_cycles_counter := descriptor_size_in_data_blocks;
burst_cycles_counter := dma_burst_size_in_cycles;
assert false
report "dma_controller_fsm: transferring_descriptor"
severity note;
next_state := transferring_descriptor;
elsif descriptor_transfer_req = '0'
and payload_transfer_req = '1'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
-- Aborted payload transfer
elsif resume_aborted_payload_transfer = '0'
and payload_transfer_req = '1'
and descriptor_transfer_req = '1'
and resume_aborted_descriptor_transfer = '1'
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then assert false
report "Aborted payload transfer, resume_aborted_payload_transfer = 0"
severity note;
burst_cycles_counter := dma_burst_size_in_cycles;
next_state := transferring_payload;
elsif resume_aborted_payload_transfer = '0'
and payload_transfer_req = '1'
and descriptor_transfer_req = '1'
and resume_aborted_descriptor_transfer = '1'
and irdy = '0'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif resume_aborted_payload_transfer = '0'
and dma_cycles_counter = 0
then assert false
report "Illegal resume_aborted_payload_transfer at this moment because dma_cycles_counter = 0. Ignoring signal "
severity warning;
next_state := idle;
-- Aborted descriptor transfer
elsif resume_aborted_descriptor_transfer = '0'
and dma_cycles_counter > 0
and irdy = '0'
and trdy = '0'
then assert false
report "dma_controller_fsm: transferring_descriptor"
severity note;
next_state := transferring_descriptor;
elsif resume_aborted_payload_transfer = '0'
and dma_cycles_counter > 0
and (irdy = '1'
and trdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif resume_aborted_descriptor_transfer = '0'
and dma_cycles_counter > 0
and (irdy = '0'
and trdy = '0')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
elsif resume_aborted_descriptor_transfer = '0'
and dma_cycles_counter = 0
then assert false
report "Illegal resume_aborted_descriptor_transfer signal at this moment. Ignoring signal"
severity warning;
next_state := idle;
end if;
when transferring_payload =>
if burst_cycles_counter = 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
assert false
report "dma_controller_fsm: idle"
severity note;
next_state := idle;
elsif (payload_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then --assert false
--report "decrementing payload cycles counter"
--severity warning;
dma_cycles_counter := dma_cycles_counter - 1;
burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: decrementing dma_cycles_counter"
severity note;
next_state := transferring_payload;
elsif (payload_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
--and gnt = '0'
--and irdy = '0'
--and trdy = '0'
and dma_cycles_counter = 0
then payload_transfer_end_value := '1';
wait for pciclk_period * 8;
assert false
report "dma_controller_fsm: idle"
severity note;
next_state := idle;
elsif payload_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (trdy = '1'
or irdy = '1')
then assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif (payload_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
and gnt = '1'
and dma_cycles_counter > 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
end if;
when transferring_payload_stalled =>
if burst_cycles_counter = 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
elsif payload_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: transferring_payload_stalled"
severity note;
next_state := transferring_payload_stalled;
elsif payload_transfer_req = '0'
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: decrementing burst_cycles_counter"
severity note;
next_state := transferring_payload;
elsif gnt = '1'
--and dma_cycles_counter > 0
then payload_transfer_aborted_value := '1';
wait for pciclk_period * 8;
--descriptor_transfer_aborted <= '0';
next_state := idle;
end if;
when transferring_descriptor =>
if (descriptor_transfer_req = '0'
or resume_aborted_descriptor_transfer = '0')
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then dma_cycles_counter := dma_cycles_counter - 1;
burst_cycles_counter := burst_cycles_counter - 1;
assert false
report "dma_controller_fsm: decrementing dma_cycles_counter"
severity note;
next_state := transferring_descriptor;
elsif (descriptor_transfer_req = '0'
or resume_aborted_payload_transfer = '0')
--and gnt = '0'
--and irdy = '0'
--and trdy = '0'
and dma_cycles_counter = 0
then descriptor_transfer_end_value := '1';
wait for pciclk_period * 8;
assert false
report "dma_controller_fsm: idle"
severity note;
next_state := idle;
elsif descriptor_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (trdy = '1'
or irdy = '1')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
elsif (descriptor_transfer_req = '0'
or resume_aborted_descriptor_transfer = '0')
and gnt = '1'
and dma_cycles_counter > 0
then descriptor_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
end if;
when transferring_descriptor_stalled =>
if descriptor_transfer_req = '0'
and gnt = '0'
and dma_cycles_counter > 0
and (irdy = '1'
or trdy = '1')
then assert false
report "dma_controller_fsm: transferring_descriptor_stalled"
severity note;
next_state := transferring_descriptor_stalled;
elsif descriptor_transfer_req = '0'
and gnt = '0'
and irdy = '0'
and trdy = '0'
and dma_cycles_counter > 0
then next_state := transferring_descriptor;
elsif gnt = '1'
-- and dma_cycles_counter > 0
then descriptor_transfer_aborted_value := '1';
wait for pciclk_period * 8;
next_state := idle;
end if;
end case;
state := next_state;
end process dma_controller_fsm;
output_signals_driver: process
begin
wait until pciclk'event and pciclk = '1';
payload_transfer_end <= payload_transfer_end_value;
descriptor_transfer_end <= descriptor_transfer_end_value;
payload_transfer_aborted <= payload_transfer_aborted_value;
descriptor_transfer_aborted <= descriptor_transfer_aborted_value;
end process output_signals_driver;
dma_cycles_counter_out_driver: process
begin
wait until pciclk'event and pciclk = '0';
dma_cycles_counter_out <= dma_cycles_counter;
burst_cycles_counter_out <= burst_cycles_counter;
end process dma_cycles_counter_out_driver;
end V1;
|
--
-- FIFO (using Altera scfifo for Cyclone II)
--
-- Author: Sebastian Witt
-- Date: 07.03.2008
-- Version: 1.0
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
entity slib_fifo is
generic (
WIDTH : integer := 8; -- FIFO width
SIZE_E : integer := 6 -- FIFO size (2^SIZE_E)
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear FIFO
WRITE : in std_logic; -- Write to FIFO
READ : in std_logic; -- Read from FIFO
D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input
Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output
EMPTY : out std_logic; -- FIFO is empty
FULL : out std_logic; -- FIFO is full
USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage
);
end slib_fifo;
architecture altera of slib_fifo is
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
usedw : OUT STD_LOGIC_VECTOR (SIZE_E-1 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
full : OUT STD_LOGIC
);
END COMPONENT;
begin
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "Cyclone II",
lpm_numwords => 2**SIZE_E,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => WIDTH,
lpm_widthu => SIZE_E,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
rdreq => READ,
sclr => CLEAR,
clock => CLK,
wrreq => WRITE,
data => D,
usedw => USAGE,
empty => EMPTY,
q => Q,
full => FULL
);
end altera;
|
-------------------------------------------------------------------------------
--
-- File: tb_TestConfigADC.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This test bench is used to illustrate the ConfigADC module behavior.
-- It does not represent an extensive test of the module. The external
-- indirect access SPI interface is not used. The AD96xx_92xxSPI_Model is however
-- requested to deliberately insert an error on the InsertError port to test
-- the response of the configuration state machine error reporting circuitry.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity tb_TestConfigADC is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 1;
kADC_ClkDiv : integer range 1 to 8 := 4
);
end tb_TestConfigADC;
architecture Behavioral of tb_TestConfigADC is
signal SysClk100 : std_logic := '1';
signal asRst_n : std_logic := '0';
signal sSPI_Clk, sSDIO : std_logic := 'X';
signal sCS : std_logic := '1';
signal InsertError : std_logic;
signal sCmdTxAxisTvalid : std_logic;
signal sCmdTxAxisTready : std_logic;
signal sCmdTxAxisTdata : std_logic_vector(31 downto 0);
signal sCmdRxAxisTvalid : STD_LOGIC;
signal sCmdRxAxisTready : std_logic;
signal sCmdRxAxisTdata : std_logic_vector (31 downto 0);
signal sInitDoneADC : std_logic;
signal sConfigError : std_logic;
constant kSysClkPeriod : time := 10ns; -- System Clock Period
begin
ConfigADC_inst: entity work.ConfigADC
Generic Map(
kZmodID => kZmodID,
kADC_ClkDiv => kADC_ClkDiv,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth,
kSimulation => true
)
Port Map(
--
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneADC => sInitDoneADC,
sConfigError => sConfigError,
--AD9648 SPI interface signals
sADC_Sclk => sSPI_Clk,
sADC_SDIO => sSDIO,
sADC_CS => sCS,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
TestCmdFIFO: entity work.SPI_IAP_TestModule
Generic Map(
kZmodID => kZmodID
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
sInitDoneADC => sInitDoneADC,
sCmdTxAxisTvalid => sCmdTxAxisTvalid,
sCmdTxAxisTready => sCmdTxAxisTready,
sCmdTxAxisTdata => sCmdTxAxisTdata,
sCmdRxAxisTvalid => sCmdRxAxisTvalid,
sCmdRxAxisTready => sCmdRxAxisTready,
sCmdRxAxisTdata => sCmdRxAxisTdata
);
AD96xx_92xx_inst: entity work.AD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kDataWidth => kSPI_DataWidth,
kCommandWidth => kSPI_CommandWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sSPI_Clk => sSPI_Clk,
sSDIO => sSDIO,
sCS => sCS
);
Clock: process
begin
for i in 0 to (kCount5ms*3) loop
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
wait for kSysClkPeriod/2;
SysClk100 <= not SysClk100;
end loop;
wait;
end process;
Main: process
begin
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
asRst_n <= '0';
InsertError <= '0';
wait for 10 * kSysClkPeriod;
-- Signals are assigned at test bench level on the falling edge of SysClk100.
wait until falling_edge(SysClk100);
-- Release reset and perform the ADC initialization with no error inserted.
asRst_n <= '1';
-- Check if the sInitDoneADC signal is asserted and sConfigError is de-asserted
-- after the configuration timeout period (determined empirically)
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '1')
report "sInitDoneADC signal not asserted when expected" & LF & HT & HT
severity ERROR;
assert (sConfigError = '0')
report "sConfigError signal not de-asserted when expected" & LF & HT & HT
severity ERROR;
-- Hold the reset condition for 10 clock cycles
-- (one clock cycle is sufficient, however 10 clock cycles makes
-- it easier to visualize the reset condition in simulation).
asRst_n <= '0';
wait for 10*kSysClkPeriod;
wait until falling_edge(SysClk100);
-- Request the ADI_2WireSPI_Model to deliberately insert a register read error.
InsertError <= '1';
asRst_n <= '1';
-- Check if the sInitDoneADC signal is de-asserted and sConfigError is asserted
-- after the configuration timeout period (determined empirically) in the case
-- of an erroneous response of the ADC
wait for kCount5ms * kSysClkPeriod;
assert (sInitDoneADC = '0')
report "sInitDoneADC signal is erroneously asserted" & LF & HT & HT
severity ERROR;
assert (sConfigError = '1')
report "sConfigError signal not asserted when expected" & LF & HT & HT
severity ERROR;
wait;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkpad
-- File: clkpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity clkpad is
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0; filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : in std_ulogic := '1'; lock : out std_ulogic);
end;
architecture rtl of clkpad is
begin
gen0 : if has_pads(tech) = 0 generate
o <= to_X01(pad); lock <= '1';
end generate;
xcv2 : if (is_unisim(tech) = 1) generate
u0 : unisim_clkpad generic map (level, voltage, arch, hf, tech) port map (pad, o, rstn, lock);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_clkpad generic map (level, voltage, arch) port map (pad, o); lock <= '1';
end generate;
pa : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
fus : if (tech = actfus) generate
u0 : fusion_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
um : if (tech = umc) generate
u0 : umc_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
saed : if (tech = saed32) generate
u0 : saed32_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
dar : if (tech = dare) generate
u0 : dare_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_clkpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_inpad port map (pad, o); lock <= '1';
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_inpad port map (pad, o); lock <= '1';
end generate;
ut13 : if (tech = ut130) generate
u0 : ut130hbd_inpad generic map (level, voltage, filter)
port map (pad, o); lock <= '1';
end generate;
ut9 : if (tech = ut90) generate
u0 : ut90nhbd_inpad port map (pad, o); lock <= '1';
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_inpad port map (pad, o); lock <= '1';
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_inpad generic map (level, voltage) port map (pad, o); lock <= '1';
end generate;
end;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: rgb565_to_rgb888 - Structural
-- Description: Convert 16-bit rgb565 to 24-bit rgb888
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgb565_to_rgb888 is
port(
rgb_565: in std_logic_vector(15 downto 0);
rgb_888: out std_logic_vector(23 downto 0)
);
end rgb565_to_rgb888;
architecture Structural of rgb565_to_rgb888 is
signal red, green, blue: std_logic_vector(7 downto 0) := "00000000";
begin
red(4 downto 0) <= rgb_565(15 downto 11);
green(5 downto 0) <= rgb_565(10 downto 5);
blue(4 downto 0) <= rgb_565(4 downto 0);
process(red, green, blue)
variable r_1, r_2, g_1, g_2, b_1, b_2: unsigned(7 downto 0);
begin
r_1 := unsigned(red) sll 3;
r_2 := unsigned(red) srl 2;
g_1 := unsigned(green) sll 2;
g_2 := unsigned(green) srl 4;
b_1 := unsigned(blue) sll 3;
b_2 := unsigned(blue) sll 2;
rgb_888(23 downto 16) <= std_logic_vector(r_1 or r_2);
rgb_888(15 downto 8) <= std_logic_vector(g_1 or g_2);
rgb_888(7 downto 0) <= std_logic_vector(b_1 or b_1);
end process;
end Structural;
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: rgb565_to_rgb888 - Structural
-- Description: Convert 16-bit rgb565 to 24-bit rgb888
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgb565_to_rgb888 is
port(
rgb_565: in std_logic_vector(15 downto 0);
rgb_888: out std_logic_vector(23 downto 0)
);
end rgb565_to_rgb888;
architecture Structural of rgb565_to_rgb888 is
signal red, green, blue: std_logic_vector(7 downto 0) := "00000000";
begin
red(4 downto 0) <= rgb_565(15 downto 11);
green(5 downto 0) <= rgb_565(10 downto 5);
blue(4 downto 0) <= rgb_565(4 downto 0);
process(red, green, blue)
variable r_1, r_2, g_1, g_2, b_1, b_2: unsigned(7 downto 0);
begin
r_1 := unsigned(red) sll 3;
r_2 := unsigned(red) srl 2;
g_1 := unsigned(green) sll 2;
g_2 := unsigned(green) srl 4;
b_1 := unsigned(blue) sll 3;
b_2 := unsigned(blue) sll 2;
rgb_888(23 downto 16) <= std_logic_vector(r_1 or r_2);
rgb_888(15 downto 8) <= std_logic_vector(g_1 or g_2);
rgb_888(7 downto 0) <= std_logic_vector(b_1 or b_1);
end process;
end Structural;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Xilinx's Vivado
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an int_const_mult an its content. It exists
/ to circumvent the impossibility of reading the attributes of an unconstrained port signal inside
/ the port declaration of an entity. (so as to declare the output's size, which depends on the
/ input's size).
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.fixed_generic_pkg.all;
use work.fixed_float_types.all;
use work.real_const_mult_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity int_const_mult_s is
generic(
SPEED_opt : T_speed := t_min; --exception: value not set
MULTIPLICANDS : integer_v --compulsory
);
port(
input : in u_sfixed;
clk : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed_v;
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture int_const_mult_s1 of int_const_mult_s is
function to_real(
vector : integer_v)
return real_v is
variable result : real_v(vector'range);
begin
for i in vector'range loop
result(i) := real(vector(i));
end loop;
return result;
end function;
constant MULTIPLICANDS_real : real_v(MULTIPLICANDS'range) := to_real(MULTIPLICANDS);
/*================================================================================================*/
/*================================================================================================*/
begin
real_const_mult_core_s2:
entity work.real_const_mult_core_s
generic map(
SPEED_opt => SPEED_opt,
--ROUND_STYLE_opt => ROUND_STYLE_opt,
--ROUND_TO_BIT_opt => ROUND_TO_BIT_opt,
--MAX_ERROR_PCT_opt => MAX_ERROR_PCT_opt,
CONSTANTS => MULTIPLICANDS_real,
input_high => input'high,
input_low => input'low
)
port map(
input => input,
clk => clk,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
end architecture; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
signal s : pulled_up bit bus;
begin
process is
begin
s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
null after 19 ns, '0' after 25 ns;
wait for 10 ns;
-- code from book:
s <= reject 3 ns inertial null after 10 ns;
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
signal s : pulled_up bit bus;
begin
process is
begin
s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
null after 19 ns, '0' after 25 ns;
wait for 10 ns;
-- code from book:
s <= reject 3 ns inertial null after 10 ns;
-- end of code from book
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
function pulled_up ( drivers : bit_vector ) return bit is
begin
for index in drivers'range loop
if drivers(index) = '0' then
return '0';
end if;
end loop;
return '1';
end function pulled_up;
signal s : pulled_up bit bus;
begin
process is
begin
s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
null after 19 ns, '0' after 25 ns;
wait for 10 ns;
-- code from book:
s <= reject 3 ns inertial null after 10 ns;
-- end of code from book
wait;
end process;
end architecture test;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_data_pkg.all;
use work.cpu_l1mem_data_cache_pkg.all;
entity cpu_l1mem_data_cache is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_data_ctrl_in : out cpu_mmu_data_ctrl_in_type;
cpu_mmu_data_dp_in : out cpu_mmu_data_dp_in_type;
cpu_mmu_data_ctrl_out : in cpu_mmu_data_ctrl_out_type;
cpu_mmu_data_dp_out : in cpu_mmu_data_dp_out_type;
cpu_l1mem_data_cache_ctrl_in : in cpu_l1mem_data_cache_ctrl_in_type;
cpu_l1mem_data_cache_dp_in : in cpu_l1mem_data_cache_dp_in_type;
cpu_l1mem_data_cache_ctrl_out : out cpu_l1mem_data_cache_ctrl_out_type;
cpu_l1mem_data_cache_dp_out : out cpu_l1mem_data_cache_dp_out_type;
sys_master_ctrl_out : out sys_master_ctrl_out_type;
sys_master_dp_out : out sys_master_dp_out_type;
sys_slave_ctrl_out : in sys_slave_ctrl_out_type;
sys_slave_dp_out : in sys_slave_dp_out_type
);
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb : in std_logic;
ddr_clk_fb_out : out std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
rxd : in std_ulogic;
txd : out std_ulogic;
led_rx : out std_ulogic;
led_tx : out std_ulogic;
-- gpio : inout std_logic_vector(31 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
eresetn : out std_ulogic;
etx_slew : out std_logic_vector(1 downto 0);
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
vid_clock : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
hackVector : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
signal gpio : std_logic_vector(31 downto 0); -- I/O port
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, ddrlock : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal duart, rserrx, rsertx, rdsuen, ldsuen : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lresetn, lock, clkml, clk1x : std_ulogic;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := 1;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute keep of ddrlock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
signal stati : ahbstat_in_type;
signal dac_clk,video_clk, clkvga : std_logic; -- Signals to vgaclock.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
attribute keep of clkvga : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
lock <= ddrlock and cgo.clklock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, pciclk, clkm, open, open, open, pciclk, cgi, cgo, open, clk1x);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, lresetn);
rst0 : rstgen -- reset generator
port map (lresetn, clkm, lock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), hackVector);
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
ndsuact <= not dsuo.active;
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 4)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= rxd when dsuen = '1' else '1';
end generate;
led_rx <= rxd;
led_tx <= duo.txd when dsuen = '1' else u1o.txd;
txd <= duo.txd when dsuen = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
-- DDR RAM
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddr0 : ddrspa generic map (
fabtech => fabtech, memtech => 0, ddrbits => 64,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 20, col => CFG_DDRSP_COL,
Mbyte => CFG_DDRSP_SIZE, ahbfreq => CPU_FREQ/1000,
rskew => CFG_DDRSP_RSKEW )
port map (lresetn, rstn, clk1x, clkm, ddrlock, clkml, clkml,
ahbsi, ahbso(3),
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq);
end generate;
noddr : if (CFG_DDRSP = 0) generate ddrlock <= '1'; end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd; u1i.ctsn <= '0'; u1i.extclk <= '0'; --txd1 <= u1o.txd;
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 7, paddr => 7, pirq => 4)
port map(rstn, clkm, apbi, apbo(7), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, clkm, apbi, apbo(6), vgao);
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkm);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, clk0 => 40000,
clk1 => 20000, clk2 => CFG_CLKDIV*10000/CFG_CLKMUL, burstlen => 5)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, virtex2) port map (video_clk, clkvga);
dac_clk <= not video_clk;
video_clock_pad : outpad generic map ( tech => padtech)
port map (vid_clock, clkvga);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
vga_pads : if (CFG_VGA_ENABLE /= 0 or CFG_SVGA_ENABLE /=0) generate
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
end generate;
-- gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
-- grgpio0: grgpio
-- generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK,
-- nbits => CFG_GRGPIO_WIDTH)
-- port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
--
-- pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
-- pio_pad : iopad generic map (tech => padtech)
-- port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
-- end generate;
-- end generate;
-- ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
-- ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
-- nftslv => CFG_AHBSTATN)
-- port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
etx_slew <= "00";
eresetn <= rstn;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(4));
-- pragma translate_on
-----------------------------------------------------------------------
--- Debug ----------------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+1));
-- pragma translate_on
--
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_version
generic map (
msg1 => "LEON3 Digilent Virtex2-Pro XUP Demonstration design",
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
----------------------------------------------------------------------------
--
-- Copyright 2017 International Business Machines
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions AND
-- limitations under the License.
--
----------------------------------------------------------------------------
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_misc.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
USE ieee.numeric_std.all;
ENTITY action_axi_nvme IS
GENERIC (
-- Thread ID Width
C_M_AXI_ID_WIDTH : INTEGER := 1;
-- Width of Address Bus
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
-- Width of Data Bus
C_M_AXI_DATA_WIDTH : INTEGER := 32;
-- Width of User Write Address Bus
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
-- Width of User Read Address Bus
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
-- Width of User Write Data Bus
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
-- Width of User Read Data Bus
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
-- Width of User Response Bus
C_M_AXI_BUSER_WIDTH : INTEGER := 1
);
PORT (
nvme_cmd_valid_i : IN STD_LOGIC;
nvme_cmd_i : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
nvme_mem_addr_i : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
nvme_lba_addr_i : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
nvme_lba_count_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
nvme_busy_o : OUT STD_LOGIC;
nvme_complete_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ACLK : IN STD_LOGIC;
M_AXI_ARESETN : IN STD_LOGIC;
M_AXI_AWID : OUT STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR : OUT STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_AWUSER : OUT STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID : OUT STD_LOGIC;
M_AXI_AWREADY : IN STD_LOGIC;
M_AXI_WDATA : OUT STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB : OUT STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST : OUT STD_LOGIC;
M_AXI_WUSER : OUT STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID : OUT STD_LOGIC;
M_AXI_WREADY : IN STD_LOGIC;
M_AXI_BID : IN STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_BUSER : IN STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 DOWNTO 0);
M_AXI_BVALID : IN STD_LOGIC;
M_AXI_BREADY : OUT STD_LOGIC;
M_AXI_ARUSER : OUT STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARID : OUT STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR : OUT STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_ARVALID : OUT STD_LOGIC;
M_AXI_ARREADY : IN STD_LOGIC;
M_AXI_RID : IN STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_RDATA : IN STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_RLAST : IN STD_LOGIC;
M_AXI_RUSER : IN STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 DOWNTO 0);
M_AXI_RVALID : IN STD_LOGIC;
M_AXI_RREADY : OUT STD_LOGIC
);
END action_axi_nvme;
ARCHITECTURE action_axi_nvme OF action_axi_nvme IS
-- function called clogb2 that returns an integer which has the
-- value of the ceiling of the log base 2
FUNCTION clogb2 (bit_depth : INTEGER) RETURN INTEGER IS
VARIABLE depth : INTEGER := bit_depth;
VARIABLE count : INTEGER := 1;
BEGIN
FOR clogb2 IN 1 TO bit_depth LOOP -- Works for up to 32 bit integers
IF (bit_depth <= 2) THEN
count := 1;
ELSE
IF (depth <= 1) THEN
count := count;
ELSE
depth := depth / 2;
count := count + 1;
END IF;
END IF;
END LOOP;
RETURN(count);
END;
FUNCTION or_reduce (SIGNAL arg : STD_LOGIC_VECTOR) RETURN STD_LOGIC IS
VARIABLE result : STD_LOGIC;
BEGIN
result := '0';
FOR i IN arg'low TO arg'high LOOP
result := result OR arg(i);
END LOOP; -- i
RETURN result;
END or_reduce;
SIGNAL axi_awaddr : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_awvalid : STD_LOGIC;
SIGNAL axi_wdata : STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 DOWNTO 0);
SIGNAL axi_wlast : STD_LOGIC;
SIGNAL axi_wvalid : STD_LOGIC;
SIGNAL axi_wstrb : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL axi_bready : STD_LOGIC;
SIGNAL axi_araddr : STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 DOWNTO 0);
SIGNAL axi_arvalid : STD_LOGIC;
SIGNAL axi_rready : STD_LOGIC;
SIGNAL axi_awlen : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL axi_arlen : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL continue_polling : STD_LOGIC;
SIGNAL start_polling : STD_LOGIC;
SIGNAL cmd_complete : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL wr_count : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL index : STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
M_AXI_AWID <= (OTHERS => '0');
M_AXI_AWADDR <= axi_awaddr;
M_AXI_AWLEN <= axi_awlen;
M_AXI_AWSIZE <= STD_LOGIC_VECTOR( to_unsigned(clogb2((C_M_AXI_DATA_WIDTH/8)-1), 3) );
M_AXI_AWBURST <= "01";
M_AXI_AWLOCK <= "00";
M_AXI_AWCACHE <= "0010";
M_AXI_AWPROT <= "000";
M_AXI_AWQOS <= x"0";
M_AXI_AWUSER <= (OTHERS => '0');
M_AXI_AWVALID <= axi_awvalid;
M_AXI_WDATA <= axi_wdata;
M_AXI_WSTRB <= (OTHERS => '1');
M_AXI_WLAST <= axi_wlast;
M_AXI_WUSER <= (OTHERS => '0');
M_AXI_WVALID <= axi_wvalid;
M_AXI_BREADY <= axi_bready;
M_AXI_ARID <= (OTHERS => '0');
M_AXI_ARADDR <= axi_araddr;
M_AXI_ARLEN <= axi_arlen;
M_AXI_ARSIZE <= STD_LOGIC_VECTOR( to_unsigned( clogb2((C_M_AXI_DATA_WIDTH/8)-1),3 ));
M_AXI_ARBURST <= "01";
M_AXI_ARLOCK <= "00";
M_AXI_ARCACHE <= "0010";
M_AXI_ARPROT <= "000";
M_AXI_ARQOS <= x"0";
M_AXI_ARUSER <= (OTHERS => '0');
M_AXI_ARVALID <= axi_arvalid;
M_AXI_RREADY <= axi_rready;
-- data for NVMe host write burst
WITH wr_count SELECT axi_wdata <=
nvme_mem_addr_i(31 DOWNTO 0) WHEN x"5",
nvme_mem_addr_i(63 DOWNTO 32) WHEN x"4",
nvme_lba_addr_i(31 DOWNTO 0) WHEN x"3",
nvme_lba_addr_i(63 DOWNTO 32) WHEN x"2",
nvme_lba_count_i(31 DOWNTO 0) WHEN x"1",
(31 DOWNTO 12 => '0') & nvme_cmd_i WHEN OTHERS ;
axi_wlast <= '1' WHEN wr_count = x"0" ELSE '0';
axi_awaddr <= (OTHERS => '0');
axi_awlen <= x"05";
axi_w: PROCESS(M_AXI_ACLK)
BEGIN
IF (rising_edge (M_AXI_ACLK)) THEN
-- wait for valid command
IF nvme_cmd_valid_i = '1' THEN
-- send command to NVMe host
axi_awvalid <= '1';
wr_count <= x"5";
axi_wvalid <= '1';
nvme_busy_o <= '1';
END IF;
IF axi_awvalid = '1' AND M_AXI_AWREADY = '1' THEN
axi_awvalid <= '0';
axi_bready <= '1';
END IF;
start_polling <= '0';
-- wait until command has been send to NVMe host
-- and then start polling for completion
IF M_AXI_BVALID = '1' AND axi_bready = '1' THEN
axi_bready <= '0';
nvme_busy_o <= '0';
IF wr_count = x"f" THEN
start_polling <= '1';
END IF;
END IF;
IF axi_wvalid = '1' AND M_AXI_WREADY = '1' THEN
wr_count <= wr_count - '1';
IF wr_count = x"0" THEN
axi_wvalid <= '0';
END IF;
END IF;
IF M_AXI_ARESETN = '0' THEN
axi_awvalid <= '0';
axi_bready <= '0';
axi_wvalid <= '0';
nvme_busy_o <= '0';
END IF;
END IF;
END PROCESS;
axi_arlen <= x"00";
-- poll NVMe host Action Track register until
-- bit 0 (command complete) or
-- bit 1 (error) is set
axi_r: PROCESS(M_AXI_ACLK)
VARIABLE polling_started : STD_LOGIC;
BEGIN
IF (rising_edge (M_AXI_ACLK)) THEN
continue_polling <= '0';
nvme_complete_o(1 DOWNTO 0) <= "00";
IF polling_started = '0' AND start_polling = '1' THEN
continue_polling <= '1';
polling_started := '1';
END IF;
IF continue_polling = '1' THEN
axi_arvalid <= '1';
END IF;
IF axi_arvalid = '1' AND M_AXI_ARREADY = '1' THEN
axi_arvalid <= '0';
axi_rready <= '1';
END IF;
index <= axi_araddr(6 DOWNTO 0) - x"4";
IF M_AXI_RVALID = '1' AND axi_rready = '1' THEN
continue_polling <= '1';
IF axi_araddr(6 DOWNTO 0) = "0000000" THEN
FOR i IN 16 TO 31 LOOP
IF M_AXI_RDATA(i) = '1' THEN
axi_araddr(7 DOWNTO 0) <= x"00" + STD_LOGIC_VECTOR(to_unsigned(i-15,5))* "100";
END IF;
END LOOP; -- i
ELSE
nvme_complete_o <= index(5 DOWNTO 2) & "00" & M_AXI_RDATA(1 DOWNTO 0);
axi_araddr(6 DOWNTO 0) <= "0000000";
END IF;
END IF;
IF (M_AXI_ARESETN = '0' ) THEN
axi_arvalid <= '0';
axi_rready <= '0';
axi_araddr <= x"0000_0000";
polling_started := '0';
END IF;
END IF;
END PROCESS;
END action_axi_nvme;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x_e is port (
a : in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0) );
end x_e;
-- Architecture of the Component
architecture a_x_e of x_e is
begin
-- Moltiplication Process
d(3) <= a(3) xor a(2) xor a(1) xor a(0);
d(2) <= a(2) xor a(1) xor a(0);
d(1) <= a(1) xor a(0);
d(0) <= a(3) xor a(2) xor a(1);
end a_x_e;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity x_e is port (
a : in std_logic_vector (3 downto 0);
d : out std_logic_vector (3 downto 0) );
end x_e;
-- Architecture of the Component
architecture a_x_e of x_e is
begin
-- Moltiplication Process
d(3) <= a(3) xor a(2) xor a(1) xor a(0);
d(2) <= a(2) xor a(1) xor a(0);
d(1) <= a(1) xor a(0);
d(0) <= a(3) xor a(2) xor a(1);
end a_x_e;
|
-- File name: aes.vhd
-- Created: 2009-02-25
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: AES package
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package aes is
subtype byte is unsigned(7 downto 0);
subtype nibble is unsigned(3 downto 0);
subtype pair is unsigned(1 downto 0);
subtype index is integer range 0 to 3;
type pntr is record
i : index;
j : index;
end record pntr;
subtype g_index is integer range 0 to 15;
type subblock_type is
(identity, sub_bytes, mix_columns,
shift_rows, add_round_key, load_pt, store_ct);
subtype round_type is integer range 0 to 11;
type state_type is array (index, index) of byte;
alias key_type is state_type;
type slice is array (index) of byte;
alias row is slice;
alias col is slice;
type sbox_array is array (0 to 255) of byte;
constant sbox : sbox_array :=
(
x"63", x"7C", x"77", x"7B", x"F2", x"6B", x"6F", x"C5",
x"30", x"01", x"67", x"2B", x"FE", x"D7", x"AB", x"76",
x"CA", x"82", x"C9", x"7D", x"FA", x"59", x"47", x"F0",
x"AD", x"D4", x"A2", x"AF", x"9C", x"A4", x"72", x"C0",
x"B7", x"FD", x"93", x"26", x"36", x"3F", x"F7", x"CC",
x"34", x"A5", x"E5", x"F1", x"71", x"D8", x"31", x"15",
x"04", x"C7", x"23", x"C3", x"18", x"96", x"05", x"9A",
x"07", x"12", x"80", x"E2", x"EB", x"27", x"B2", x"75",
x"09", x"83", x"2C", x"1A", x"1B", x"6E", x"5A", x"A0",
x"52", x"3B", x"D6", x"B3", x"29", x"E3", x"2F", x"84",
x"53", x"D1", x"00", x"ED", x"20", x"FC", x"B1", x"5B",
x"6A", x"CB", x"BE", x"39", x"4A", x"4C", x"58", x"CF",
x"D0", x"EF", x"AA", x"FB", x"43", x"4D", x"33", x"85",
x"45", x"F9", x"02", x"7F", x"50", x"3C", x"9F", x"A8",
x"51", x"A3", x"40", x"8F", x"92", x"9D", x"38", x"F5",
x"BC", x"B6", x"DA", x"21", x"10", x"FF", x"F3", x"D2",
x"CD", x"0C", x"13", x"EC", x"5F", x"97", x"44", x"17",
x"C4", x"A7", x"7E", x"3D", x"64", x"5D", x"19", x"73",
x"60", x"81", x"4F", x"DC", x"22", x"2A", x"90", x"88",
x"46", x"EE", x"B8", x"14", x"DE", x"5E", x"0B", x"DB",
x"E0", x"32", x"3A", x"0A", x"49", x"06", x"24", x"5C",
x"C2", x"D3", x"AC", x"62", x"91", x"95", x"E4", x"79",
x"E7", x"C8", x"37", x"6D", x"8D", x"D5", x"4E", x"A9",
x"6C", x"56", x"F4", x"EA", x"65", x"7A", x"AE", x"08",
x"BA", x"78", x"25", x"2E", x"1C", x"A6", x"B4", x"C6",
x"E8", x"DD", x"74", x"1F", x"4B", x"BD", x"8B", x"8A",
x"70", x"3E", x"B5", x"66", x"48", x"03", x"F6", x"0E",
x"61", x"35", x"57", x"B9", x"86", x"C1", x"1D", x"9E",
x"E1", x"F8", x"98", x"11", x"69", x"D9", x"8E", x"94",
x"9B", x"1E", x"87", x"E9", x"CE", x"55", x"28", x"DF",
x"8C", x"A1", x"89", x"0D", x"BF", x"E6", x"42", x"68",
x"41", x"99", x"2D", x"0F", x"B0", x"54", x"BB", x"16"
);
end aes;
package body aes is
end aes;
|
library ieee;
use ieee.std_logic_1164.all;
entity aludec is
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
end entity;
architecture arq_aludec of aludec is
begin
alucontrol <= "010" when aluop = "00" else
"110" when aluop = "01" else
"010" when aluop(0) = '1' and funct = "100000" else
"110" when aluop(0) = '1' and funct = "100010" else
"000" when aluop(0) = '1' and funct = "100100" else
"001" when aluop(0) = '1' and funct = "100101" else
"111" when aluop(0) = '1' and funct = "101010" else
unaffected;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity aludec is
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
end entity;
architecture arq_aludec of aludec is
begin
alucontrol <= "010" when aluop = "00" else
"110" when aluop = "01" else
"010" when aluop(0) = '1' and funct = "100000" else
"110" when aluop(0) = '1' and funct = "100010" else
"000" when aluop(0) = '1' and funct = "100100" else
"001" when aluop(0) = '1' and funct = "100101" else
"111" when aluop(0) = '1' and funct = "101010" else
unaffected;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity aludec is
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
end entity;
architecture arq_aludec of aludec is
begin
alucontrol <= "010" when aluop = "00" else
"110" when aluop = "01" else
"010" when aluop(0) = '1' and funct = "100000" else
"110" when aluop(0) = '1' and funct = "100010" else
"000" when aluop(0) = '1' and funct = "100100" else
"001" when aluop(0) = '1' and funct = "100101" else
"111" when aluop(0) = '1' and funct = "101010" else
unaffected;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity aludec is
port (funct: in std_logic_vector(5 downto 0);
aluop: in std_logic_vector(1 downto 0);
alucontrol: out std_logic_vector(2 downto 0));
end entity;
architecture arq_aludec of aludec is
begin
alucontrol <= "010" when aluop = "00" else
"110" when aluop = "01" else
"010" when aluop(0) = '1' and funct = "100000" else
"110" when aluop(0) = '1' and funct = "100010" else
"000" when aluop(0) = '1' and funct = "100100" else
"001" when aluop(0) = '1' and funct = "100101" else
"111" when aluop(0) = '1' and funct = "101010" else
unaffected;
end architecture;
|
-- $Id: tb_nexys2_fusp_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp_cuff - sim
-- Description: Test bench for nexys2 (base+fusp+cuff)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tbcore/tbcore_rlink_dcm
-- tb_nexys2_core
-- serport/tb/serport_master_tb
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_cuff_aif [UUT]
--
-- To test: generic, any nexys2_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-01-03 469 1.1 add fx2 model and data path
-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys2_fusp_cuff is
end tb_nexys2_fusp_cuff;
architecture sim of tb_nexys2_fusp_cuff is
signal CLKOSC : slbit := '0';
signal CLKCOM : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal TBC_RXDATA : slv8 := (others=>'0');
signal TBC_RXVAL : slbit := '0';
signal TBC_RXHOLD : slbit := '0';
signal TBC_TXDATA : slv8 := (others=>'0');
signal TBC_TXENA : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXENA : slbit := '0';
signal FX2_RXBUSY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXVAL : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal I_FX2_IFCLK : slbit := '0';
signal O_FX2_FIFO : slv2 := (others=>'0');
signal I_FX2_FLAG : slv4 := (others=>'0');
signal O_FX2_SLRD_N : slbit := '1';
signal O_FX2_SLWR_N : slbit := '1';
signal O_FX2_SLOE_N : slbit := '1';
signal O_FX2_PKTEND_N : slbit := '1';
signal IO_FX2_DATA : slv8 := (others=>'Z');
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
DCM_COM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TBC_RXDATA,
RX_VAL => TBC_RXVAL,
RX_HOLD => TBC_RXHOLD,
TX_DATA => TBC_TXDATA,
TX_ENA => TBC_TXENA
);
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_cuff_aif
port map (
I_CLK50 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXOK => '1',
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
FX2 : entity work.fx2_2fifo_core
port map (
CLK => CLKCOM,
RESET => '0',
RXDATA => FX2_RXDATA,
RXENA => FX2_RXENA,
RXBUSY => FX2_RXBUSY,
TXDATA => FX2_TXDATA,
TXVAL => FX2_TXVAL,
IFCLK => I_FX2_IFCLK,
FIFO => O_FX2_FIFO,
FLAG => I_FX2_FLAG,
SLRD_N => O_FX2_SLRD_N,
SLWR_N => O_FX2_SLWR_N,
SLOE_N => O_FX2_SLOE_N,
PKTEND_N => O_FX2_PKTEND_N,
DATA => IO_FX2_DATA
);
proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
)
begin
if R_PORTSEL_FX2 = '0' then -- use serport
UART_TXDATA <= TBC_RXDATA;
UART_TXENA <= TBC_RXVAL;
TBC_RXHOLD <= UART_TXBUSY or RTS_N;
TBC_TXDATA <= UART_RXDATA;
TBC_TXENA <= UART_RXVAL;
else -- otherwise use fx2
FX2_RXDATA <= TBC_RXDATA;
FX2_RXENA <= TBC_RXVAL;
TBC_RXHOLD <= FX2_RXBUSY;
TBC_TXDATA <= FX2_TXDATA;
TBC_TXENA <= FX2_TXVAL;
end if;
end process proc_fx2_mux;
proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_ser_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if UART_RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
end if;
end if;
end process proc_simbus;
end sim;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY test_flopr IS
END test_flopr;
ARCHITECTURE t_flopr OF test_flopr IS
COMPONENT flopr
PORT (d: IN std_logic_vector(31 DOWNTO 0);
clk, reset: IN std_logic;
q: OUT std_logic_vector(31 DOWNTO 0));
END COMPONENT;
SIGNAL d: std_logic_vector(31 DOWNTO 0);
SIGNAL clk: std_logic := '0';
SIGNAL reset: std_logic;
SIGNAL q: std_logic_vector(31 DOWNTO 0);
BEGIN
u0: flopr PORT MAP (d, clk, reset, q);
d <= x"FF000500" after 0 fs, x"AA937110" after 10 fs, x"FFFFFFFF" after 23 fs;
clk <= not clk after 5 fs;
reset <= '0' after 0 fs, '1' after 5 fs, '0' after 10 fs, '0' after 15 fs, '1' after 27 fs;
END t_flopr;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity matrix_extractor is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
OUTVALUE_WIDTH : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
------------------------ matrix out ---------------------
p00 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p01 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p02 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p10 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p11 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p12 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p20 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p21 : out std_logic_vector((PIX_WIDTH-1) downto 0);
p22 : out std_logic_vector((PIX_WIDTH-1) downto 0);
matrix_dv : out std_logic;
---------------------- computed value -------------------
value_data : in std_logic_vector((OUTVALUE_WIDTH-1) downto 0);
value_dv : in std_logic;
------------------------- params ------------------------
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0)
);
end matrix_extractor;
architecture rtl of matrix_extractor is
constant FIFO_LENGHT : integer := LINE_WIDTH_MAX;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
component gp_fifo
generic (
DATA_WIDTH : positive;
FIFO_DEPTH : positive
);
port (
clk : in std_logic;
reset_n : in std_logic;
data_wr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
full : out std_logic;
data_rd : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
empty : out std_logic
);
end component;
signal enable_reg : std_logic;
signal x_pos : unsigned(15 downto 0);
signal y_pos : unsigned(15 downto 0);
signal p00_s, p01_s, p02_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p10_s, p11_s, p12_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal p20_s, p21_s, p22_s : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line_reset : std_logic;
signal line0_read : std_logic;
signal line0_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line0_write : std_logic;
signal line0_empty : std_logic;
signal line0_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line1_read : std_logic;
signal line1_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal line1_write : std_logic;
signal line1_empty : std_logic;
signal line1_pix_out : std_logic_vector((PIX_WIDTH-1) downto 0);
signal dummy_dv : std_logic;
signal out_dv_s : std_logic;
signal cell : std_logic_vector((LINE_WIDTH_MAX-1) downto 0);
begin
line0_fifo : gp_fifo
generic map (
DATA_WIDTH => PIX_WIDTH,
FIFO_DEPTH => FIFO_LENGHT
)
port map (
data_in => p10_s,
clk => clk_proc,
data_wr => line0_write,
data_out => p02_s,
data_rd => line0_read,
reset_n => line_reset,
empty => line0_empty
);
line1_fifo : gp_fifo
generic map (
DATA_WIDTH => PIX_WIDTH,
FIFO_DEPTH => FIFO_LENGHT
)
port map (
data_in => p20_s,
clk => clk_proc,
data_wr => line1_write,
data_out => p12_s,
data_rd => line1_read,
reset_n => line_reset,
empty => line1_empty
);
process (clk_proc, reset_n)
begin
if(reset_n='0') then
x_pos <= to_unsigned(0, 16);
y_pos <= to_unsigned(0, 16);
line0_read <= '0';
line0_write <= '0';
line1_read <= '0';
line1_write <= '0';
line_reset <= '0';
elsif(rising_edge(clk_proc)) then
matrix_dv <= '0';
if(in_fv='0') then
x_pos <= to_unsigned(0, 16);
y_pos <= to_unsigned(0, 16);
line0_read <= '0';
line0_write <= '0';
line1_read <= '0';
line1_write <= '0';
line_reset <= '0';
matrix_dv <= '0';
else
line_reset <= '1';
if (line0_read='1') then
p01_s <= p02_s;
p00_s <= p01_s;
end if;
if (line1_read='1') then
p11_s <= p12_s;
p10_s <= p11_s;
end if;
if (in_dv='1') then
-- counter y_pos and x_pos
x_pos <= x_pos+1;
if(x_pos = unsigned(widthimg_i)-1) then
y_pos <= y_pos + 1;
x_pos <= to_unsigned(0, 16);
end if;
p22_s <= in_data;
p21_s <= p22_s;
p20_s <= p21_s;
-- line1 write command
if((y_pos = to_unsigned(0, 16)) and (x_pos >= to_unsigned(2, 16))) then
line1_write <= '1';
elsif(y_pos > to_unsigned(0, 16)) then
line1_write <= '1';
else
line1_write <= '0';
end if;
-- line0 write command
if(y_pos = to_unsigned(0, 16)) then
line0_write <= '0';
elsif((y_pos = to_unsigned(1, 16)) and (x_pos >= to_unsigned(2, 16))) then
line0_write <= '1';
elsif((y_pos > to_unsigned(1, 16))) then
line0_write <= '1';
else
line0_write <= '0';
end if;
-- matrix_dv_next command
if((x_pos >= to_unsigned(2, 16)) and (y_pos >= to_unsigned(2, 16))) then
matrix_dv <= '1';
end if;
-- line1 read command
if(y_pos = to_unsigned(0, 16)) then
if(x_pos = unsigned(widthimg_i)-2) then
line1_read <= '1';
else
line1_read <= '0';
end if;
else
line1_read <= '1';
end if;
-- line0 read command
if(y_pos = to_unsigned(0, 16)) then
line0_read <= '0';
elsif(y_pos = to_unsigned(1, 16)) then
if(x_pos = unsigned(widthimg_i)-2) then
line0_read <= '1';
else
line0_read <= '0';
end if;
else
line0_read <= '1';
end if;
else
line0_read <= '0';
line0_write <= '0';
line1_read <= '0';
line1_write <= '0';
end if;
end if;
end if;
end process;
p00 <= p00_s; p01 <= p01_s; p02 <= p02_s;
p10 <= p10_s; p11 <= p11_s; p12 <= p12_s;
p20 <= p20_s; p21 <= p21_s; p22 <= p22_s;
out_data <= value_data;
out_dv <= value_dv;
out_fv <= in_fv;
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: gc_command_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity gc_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end gc_command_fifo_top;
architecture xilinx of gc_command_fifo_top is
SIGNAL clk_i : std_logic;
component gc_command_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : gc_command_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity trylock_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end trylock_fsm;
architecture behavioral of trylock_fsm is
-- A type for the states in the try fsm
type try_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the try fsm
signal try_cs : try_state;
signal try_ns : try_state;
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
try_update : process (clk,rst,sysrst,try_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
try_cs <= IDLE;
else
try_cs <= try_ns;
end if;
end if;
end process try_update;
try_controller : process (try_cs,start,mutex,micount,mikind,miowner,milast,minext,thread) is
begin
try_ns <= try_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case try_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
try_ns <= READ;
end if;
when READ =>
try_ns <= DONE;
when DONE =>
if( micount = zero(C_CWIDTH) ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= thread;
monext <= thread;
molast <= thread;
mocount <= one( C_CWIDTH );
mokind <= mikind;
elsif( mikind = SYNCH_RECURS and miowner = thread ) then
moaddr <= mutex;
moena <= '1';
mowea <= '1';
moowner <= miowner;
monext <= minext;
molast <= milast;
mocount <= micount + 1;
mokind <= mikind;
else
data(1) <= '1';
end if;
finish <= '1';
try_ns <= IDLE;
end case;
end process try_controller;
end behavioral;
|
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2017 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/chameleon.html
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Joystick autofire logic
--
-- -----------------------------------------------------------------------
-- autofire_period - Number of micro-seconds between toggling of output.
-- Autofire rate in Hz is 1000000/(2*autofire_period)
-- -----------------------------------------------------------------------
-- clk - system clock input
-- ena_1mhz - Enable must be high for one clk cycle each microsecond
-- button_n - Fire button input from joystick (low active)
-- autofire_n - Auto-fire outout (low active)
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_autofire is
generic (
autofire_period : integer := 75000
);
port (
clk : in std_logic;
ena_1mhz : in std_logic;
button_n : in std_logic;
autofire_n : out std_logic
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_autofire is
signal counter : integer range 0 to autofire_period;
signal autofire_reg : std_logic := '1';
begin
autofire_n <= autofire_reg;
process(clk)
begin
if rising_edge(clk) then
if button_n = '1' then
counter <= 0;
autofire_reg <= '1';
elsif counter = 0 then
counter <= autofire_period;
autofire_reg <= not autofire_reg;
elsif ena_1mhz = '1' then
counter <= counter - 1;
end if;
end if;
end process;
end architecture;
|
package wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean);
procedure wait_until(signal sig : in bit_vector; val : bit_vector);
end package;
package body wait_until_pkg is
procedure wait_until(signal sig : in boolean; val : boolean) is
begin
wait until sig = val; -- This does not work
end procedure;
function fun(x : bit_vector) return bit_vector is
begin
return x;
end function;
procedure wait_until(signal sig : in bit_vector; val : bit_vector) is
begin
wait until sig = fun(val);
end procedure;
end package body;
-------------------------------------------------------------------------------
entity issue163 is
end entity;
use work.wait_until_pkg.all;
architecture test of issue163 is
signal s : boolean;
signal v : bit_vector(7 downto 0);
begin
s <= true after 1 ns, false after 2 ns;
process is
begin
wait_until(s, true);
assert now = 1 ns;
wait_until(s, false);
assert now = 2 ns;
wait;
end process;
v <= X"10" after 1 ns, X"bc" after 2 ns;
process is
begin
wait_until(v, X"10");
assert now = 1 ns;
wait_until(v, X"bc");
assert now = 2 ns;
wait;
end process;
end architecture;
|
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