content stringlengths 1 1.04M ⌀ |
|---|
--
-- This file is part of top_mandelbrot_1b
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either ve... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - ... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_credit_based_checkers is
generic (
cur_addr_rst: integer := 5;
NoC_size: integer := 4
);
port ( empty: in std_logic;
... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use I... |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is'... |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is'... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram3 is
port (raddr : std_logic_vector (3 downto 0);
rdat : out std_logic_vector (7 downto 0);
waddr : std_logic_vector (3 downto 0);
wdat : std_logic_vector (7 downto 0);
clk : std_logic);
end dpram3;
arch... |
-------------------------------------------------------------------------------
--
-- T8048 Microcontroller System
-- 8048 toplevel without tri-states
--
-- $Id: t8048_notri.vhd,v 1.7 2006-07-14 01:13:32 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
... |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License... |
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- ... |
library verilog;
use verilog.vl_types.all;
entity data_gen_submodule is
port(
clk : in vl_logic;
reset_n : in vl_logic;
Data_A : out vl_logic_vector(11 downto 0);
Data_B : out vl_logic_vector(11 downto 0);
Data_C : ... |
-- (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
--!
--! @file: exercise6_6.vhd
--! @brief: Hamming Weight with LOOP
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity hamming_weight is
generic (N: integer :=... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
------------------------------------------------------------------------
-- mouse_controller.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- This f... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
us... |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
-- clock_generator
-- Generates a periodically alternating clock signal.
library ieee;
use ieee.std_logic_1164.all;
library work;
entity clock_generator is
port(clk: out std_logic);
end entity;
architecture behaviorial of clock_generator is
constant clock_period: time := 1 ns;
begin
clock_process: proces... |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... |
-- cb20.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.05.28.12:22:46
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20 is
port (
clk_clk : in std_logic := '0'; -- ... |
--------------------------------------------------------------------------------
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
... |
--Top-Level Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_CNT IS
PORT (
CLK : IN STD_LOGIC; ---THE CLK OF CNT
CLKDSP : IN STD_LOGIC; ---THE CLK OF SACN
RESET : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
SEL : OUT STD_LOGIC_VECTOR (1... |
------------------------------------------------------------------------
-- resolution_mouse_informer.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltn
-- Copyright 2006 Digilent, Inc.
---------------------------------------------------------------------... |
library IEEE;
use IEEE.std_logic_1164.all;
entity com3_pkg1_lib1 is
generic (
WITH_GENERIC: boolean:=TRUE
);
port (
data_i : in std_logic;
data_o : out std_logic
);
end entity com3_pkg1_lib1;
architecture RTL of com3_pkg1_lib1 is
begin
data_o <= data_i;
end architecture RTL;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--
-- VERY simplistic ALU implementation
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU is
Port ( enableF, Go, clk : in std_logic;
F : in std_logic_vector (3 downto 0);
BUSin : in std_logic_vector (15 downto 0);
... |
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity PICtop is
port (
Reset : in std_logic; -- Asynchronous, active low
Clk : in std_logic; -- System clock, 20 MHz, rising_edge
RS... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vec... |
------------------------------------------------------------------------------
-- Engine clear controller; implemented as a Mealy FSM
--
-- Project :
-- File : $URL: svn+ssh://plessl@yosemite.ethz.ch/home/plessl/SVN/simzippy/trunk/vhdl/engclearctrl.vhd $
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity emptyquote is
end;
architecture behav of emptyquote is
procedure proc is
begin
null;
end proc;
begin
process
begin
proc' '
null;
end process;
end;
|
architecture test of test2 is
signal foo, foo2 : bar bus := baz;
begin end;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-------------------------------------------------------------------------------
--! @file cf_pkg.vhd
--! @author Johannes Walter <johannes.walter@cern.ch>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-12-01
--! @brief Critical FPGA package.
--------------------------------------------------------------... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_log... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity WindowsManager is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
cwp : in STD_LOGIC;
... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Entity: tape_speed_control
-- Date:2016-04-17
-- Author: Gideon
--
-- Description: This module controls the tape speed, based on the motor pin.
--------------------------------------------------------------------------------
libr... |
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Versio... |
library verilog;
use verilog.vl_types.all;
entity adjustAdder4_vlg_check_tst is
port(
adjusted : in vl_logic_vector(3 downto 0);
carryAdjusted : in vl_logic;
sampler_rx : in vl_logic
);
end adjustAdder4_vlg_check_tst;
|
library IEEE;
use ieee.std_logic_1164.all;
entity test_bench_multicycle_datapath is
end test_bench_multicycle_datapath;
architecture behav of test_bench_multicycle_datapath is
component multicycle_datapath is
port(
clk, rst, pre, ce : in std_logic
);
end component;
signal clk, rst, pre, ce, finished : std_logic... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:29:29 10/22/2015
-- Design Name:
-- Module Name: C:/Users/Zetta/Desktop/sparcv8/sparcv8_v4_tb.vhd
-- Project Name: sparcv8
-- Target Device:
-- Tool versions:
-- Descrip... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
---------------------------------------
-- 10/JUL/2015 - Pedro Morales Hernandez
-- Modulo del Ecualizador
---------------------------------------
-- Importacion de librerias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY equalizer_tb IS
END equalizer_tb;
ARCHITECTURE behavior OF equalizer_tb IS
-- Compon... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_202 is
port (
output : out std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end add_202;
architecture augh of add_202 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_202 is
port (
output : out std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end add_202;
architecture augh of add_202 is
signal carry_inA : std_l... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package package_with_functions is
function hello return string;
function foo (i : integer) return integer;
end;
package body package_with_functions is
function hello return string is
begin
... |
package pixel_pkg is
generic(
NBITS : natural;
NBR_OF_CHROMA : natural
);
subtype CHROMA is bit_vector(NBITS-1 downto 0);
type TYPE_PIXEL is array (NBR_OF_CHROMA-1 downto 0) of CHROMA;
function bit_vector_to_pixel
(in_vector : in bit_vector... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
entity \--this isn't a comment\ is end;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU Gener... |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 09:45:57 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this fi... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_1_block6.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- --------------------... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.st... |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.st... |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : BusMonCore.vhd
-- /_... |
library ieee;
use ieee.std_logic_1164.all;
-- synchronous reset register
entity MEM_WB_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in ... |
library ieee;
use ieee.std_logic_1164.all;
-- synchronous reset register
entity MEM_WB_Reg is
port (
-- input signals
clk : in std_logic; -- clock source
rst : in std_logic; -- reset signal
controls_in ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity test_s_boxes is
end test_s_boxes;
architecture behavior of test_s_boxes is
signal data_in: std_logic_vector(0 to 5);
signal data_out: std_logic_vector(0 to 3);
begin
uut: entity s1_box port map (data_in, data_out);
testpr... |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_2_block6.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- ------------------------... |
entity e is end entity;
architecture a of e is
type enu is (one, two);
function one return enu is begin
return two;
end function;
begin
end architecture;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
--altera translate_off
library IEEE;
use IEEE.std_logic_1164.all... |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_eaa_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... |
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.display_comp.all;
package text_display_comp is
type text_display_in_t is
record
wx : natural range 0 to TEXT_WIDTH - 1;
wy : natural range 0 to TEXT_HEIGHT - 1;
we : std_logic;
wd ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- $Id: pdp11_cache.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_cache - syn
-- Description: pdp11: ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dec_flechas is
Port ( action : in STD_LOGIC_VECTOR (1 DOWNTO 0);
led_flechas : out STD_LOGIC_VECTOR (6 downto 0);
flecha_ctrl : out STD_LOGIC);
end dec_flechas;
architecture dataflow of dec_flechas is
begin
flecha_ctrl <= '0';
WITH act... |
--
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.5
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIF... |
--
-- UART 16750
--
-- Author: Sebastian Witt
-- Date: 29.01.2008
-- Version: 1.5
--
-- History: 1.0 - Initial version
-- 1.1 - THR empty interrupt register connected to RST
-- 1.2 - Registered outputs
-- 1.3 - Automatic flow control
-- 1.4 - De-assert IIR FIFO64 when FIF... |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_addr_mux.vhd,v 1.10 2006/06/18 10:47:01 arnim Exp $
--
-- Address Multiplexer / Generator
--
------------------------------------------------------------------... |
-----------------------------------------------------------------------------------------------------------------------
-- Author:
--
-- Create Date: 09/11/2016 -- dd/mm/yyyy
-- Module Name: test_spi_side
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Prueba de comunicac... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
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