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-------------------------------------------------------------------------------- --Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de> --All rights reserved. -- --Redistribution and use in source and binary forms, with or without --modification, are permitted provided that the following conditions are met: -- --* Redistributions of source code must retain the above copyright notice, this -- list of conditions and the following disclaimer. -- --* Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- --THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE --IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE --FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL --DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR --SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER --CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, --OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE --OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -------------------------------------------------------------------------------- --! @file lookup_table.vhd --! @brief Lookup table generation with equivalent resolving --! @author Benjamin Bässler --! @email ccl@xunit.de --! @date 2013-06-04 -------------------------------------------------------------------------------- --! Use standard library library ieee; --! Use numeric std use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; use work.types.all; use work.utils.all; --! Lookup generation for the second pass of connected component labeling entity lookup_table is generic( --! Number of max chain elements to store before stall G_MAX_CHAIN : NATURAL := 5 ); port( --! Clock input clk_in : in STD_LOGIC; --! Reset input rst_in : in STD_LOGIC; --! Output if the chain resolution stalls stall_out : out STD_LOGIC; --! Output of the next label next_lable_out : out T_LABEL; --! Generates next label gen_lable_in : in STD_LOGIC; --! Equivalent label equi_in : in T_EQUI; --! equi_in data valid equi_valid_in : in STD_LOGIC; --! High if the lookup table is ready to use. All chains are resolved lookup_ready_out : out STD_LOGIC; --! Lookup label lookup_in : in T_LABEL; --! Looked up label lookup_out : out T_LABEL; --! Last lookup reset after this last_look_up_in : in STD_LOGIC; error_out : out STD_LOGIC ); end entity lookup_table; --! @brief arc description --! @details more detailed description architecture lookup_table_arc of lookup_table is type T_EQUI_TABLE is array (0 to 2**T_LABEL'length) of T_LABEL; type T_CHK_STATE is (READY, RUN, RESTART); signal chk_state_s : T_CHK_STATE; signal chk_ptr_s : T_LABEL; signal equi_table_s : T_EQUI_TABLE; signal lbl_cnt_s : T_LABEL; -- equi ff signals signal eq_ff_di_s : unsigned(2*T_LABEL'length - 1 downto 0); signal eq_ff_do_s : unsigned(2*T_LABEL'length - 1 downto 0); signal eq_ff_full_s : std_logic; signal eq_ff_ep_s : std_logic; signal eq_ff_ae_s : std_logic; signal eq_ff_nx_s : std_logic; signal eq_ff_d_vl_s : std_logic; signal l_dst_s : T_LABEL; signal l_src_s : T_LABEL; signal lo_rdy_s : std_logic; signal lo_rdy_d_s : std_logic; signal last_lo_s : std_logic; begin l_dst_s <= eq_ff_do_s(2*T_LABEL'length-1 downto T_LABEL'length); l_src_s <= eq_ff_do_s(T_LABEL'range); next_lable_out <= lbl_cnt_s + 1 when gen_lable_in = '0' else lbl_cnt_s + 2; lookup_ready_out <= lo_rdy_s and lo_rdy_d_s; stall_out <= '0'; --! Label generation process p_lable_gen : process (rst_in, clk_in, gen_lable_in) begin if rst_in = '1' then lbl_cnt_s <= (others => '0'); last_lo_s <= '0'; elsif rising_edge(clk_in) and rst_in = '0' then if gen_lable_in = '1' then lbl_cnt_s <= lbl_cnt_s + 1; end if; if last_look_up_in = '1' then last_lo_s <= '1'; end if; if last_lo_s = '1' and lo_rdy_s = '1' and lo_rdy_d_s = '1' then -- auto reset lbl_cnt_s <= (others => '0'); last_lo_s <= '0'; end if; end if; end process p_lable_gen; p_equi : process (rst_in, clk_in, gen_lable_in) --! memory stuff to get xst to recognise it -- write data variable wr_data_v : T_LABEL; variable wr_addr_v : T_LABEL; variable wr_en_v : STD_LOGIC; begin if rst_in = '1' then eq_ff_d_vl_s <= '0'; lo_rdy_s <= '0'; lo_rdy_d_s <= '0'; equi_table_s <= (others => (others => '0')); elsif rising_edge(clk_in) and rst_in = '0' then wr_en_v := '0'; eq_ff_d_vl_s <= '0'; if chk_state_s = READY and eq_ff_ep_s = '1' and eq_ff_d_vl_s = '0' then lo_rdy_s <= '1'; else lo_rdy_s <= '0'; end if; lo_rdy_d_s <= lo_rdy_s; if gen_lable_in = '1' then --equi_table_s(to_integer(lbl_cnt_s + 1)) <= lbl_cnt_s + 1; wr_addr_v := lbl_cnt_s + 1; wr_data_v := lbl_cnt_s + 1; wr_en_v := '1'; else if equi_valid_in = '1' then eq_ff_di_s <= equi_in(0) & equi_in(1); eq_ff_d_vl_s <= '1'; else case chk_state_s is when RUN => --resolve chains in equivalent table --equi_table_s(to_integer(chk_ptr_s)) <= equi_table_s(to_integer(equi_table_s(to_integer(chk_ptr_s)))); if equi_table_s(to_integer(chk_ptr_s)) = l_dst_s or chk_ptr_s = l_dst_s then if equi_table_s(to_integer(chk_ptr_s)) > l_src_s then if equi_table_s(to_integer(chk_ptr_s)) /= l_src_s then eq_ff_di_s <= equi_table_s(to_integer(chk_ptr_s)) & l_src_s; eq_ff_d_vl_s <= '1'; end if; elsif equi_table_s(to_integer(chk_ptr_s)) < l_src_s then if l_src_s /= equi_table_s(to_integer(chk_ptr_s)) then eq_ff_di_s <= l_src_s & equi_table_s(to_integer(chk_ptr_s)); eq_ff_d_vl_s <= '1'; end if; else if equi_table_s(to_integer(chk_ptr_s)) > equi_table_s(to_integer(equi_table_s(to_integer(chk_ptr_s)))) then if equi_table_s(to_integer(chk_ptr_s)) /= equi_table_s(to_integer(equi_table_s(to_integer(chk_ptr_s)))) then eq_ff_di_s <= equi_table_s(to_integer(chk_ptr_s)) &equi_table_s(to_integer(equi_table_s(to_integer(chk_ptr_s)))); eq_ff_d_vl_s <= '1'; end if; end if; end if; wr_addr_v := chk_ptr_s; wr_data_v := l_src_s; wr_en_v := '1'; end if; when RESTART => null; when READY => if lookup_in > 0 then -- lookup only possible if lookup table fully processed lookup_out <= equi_table_s(to_integer(lookup_in)); else lookup_out <= (others => '0'); end if; end case; end if; end if; if wr_en_v = '1' then equi_table_s(to_integer(wr_addr_v)) <= wr_data_v; end if; end if; -- clk end process p_equi; p_state : process (rst_in, clk_in) begin if rst_in = '1' then chk_state_s <= READY; eq_ff_nx_s <= '0'; elsif rising_edge(clk_in) and rst_in = '0' then eq_ff_nx_s <= '0'; case chk_state_s is when READY => if eq_ff_ep_s = '0' and eq_ff_nx_s = '0' then chk_state_s <= RUN; chk_ptr_s <= lbl_cnt_s; end if; when RUN => if chk_ptr_s > 1 and gen_lable_in = '0' and equi_valid_in = '0' then chk_ptr_s <= chk_ptr_s - 1; elsif chk_ptr_s <= 1 and eq_ff_ae_s = '1' and equi_valid_in = '0' then chk_state_s <= READY; if eq_ff_ep_s = '0' then eq_ff_nx_s <= '1'; end if; elsif chk_ptr_s <= 1 and (eq_ff_ae_s = '0' or equi_valid_in = '1') then chk_state_s <= RESTART; eq_ff_nx_s <= '1'; end if; when RESTART => chk_state_s <= RUN; chk_ptr_s <= lbl_cnt_s; end case; end if; end process p_state; error_out <= eq_ff_d_vl_s and eq_ff_full_s; equi_fifo : entity work.fifo generic map( --! Size of the fifo in input words G_SIZE => C_MAX_IMAGE_HEIGHT * C_MAX_IMAGE_WIDTH*2, --! input width in bits G_WORD_WIDTH => 2*T_LABEL'LENGTH, --! output width in bits G_ALMOST_EMPTY => 1, --! Threshold for the nearly full signal in input words G_ALMOST_FULL => C_MAX_IMAGE_WIDTH - 1, --! First Word Fall Through G_FWFT => true ) port map( --! Reset input rst_in => rst_in, --! Clock input clk_in => clk_in, --! Data input wr_d_in => eq_ff_di_s, --! Data on write input valid wr_valid_in => eq_ff_d_vl_s, --! Fifo reached the G_ALMOST_FULL threshold almost_full_out => open, --! Fifo is full full_out => eq_ff_full_s, --! Data output rd_d_out => eq_ff_do_s, --! Data on output read -> next rd_next_in => eq_ff_nx_s, --! Fifo reached the G_ALMOST_EMPTY threshold almost_empty_out=> eq_ff_ae_s, --! Fifo is empty empty_out => eq_ff_ep_s, --! Fill level of fifo fill_lvl_out => open ); end architecture lookup_table_arc;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: sdmctrl -- File: sdmctrl.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: SDRAM memory controller to fit with LEON2 memory controller. ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library gaisler; use gaisler.memctrl.all; entity sdmctrl is generic ( pindex : integer := 0; invclk : integer := 0; fast : integer := 0; wprot : integer := 0; sdbits : integer := 32; pageburst : integer := 0; mobile : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; sdi : in sdram_in_type; sdo : out sdram_out_type; apbi : in apb_slv_in_type; wpo : in wprot_out_type; sdmo : out sdram_mctrl_out_type ); end; architecture rtl of sdmctrl is constant WPROTEN : boolean := (wprot /= 0); constant SDINVCLK : boolean := (invclk /= 0); constant BUS64 : boolean := (sdbits = 64); constant PM_PD : std_logic_vector(2 downto 0) := "001"; constant PM_SR : std_logic_vector(2 downto 0) := "010"; constant PM_DPD : std_logic_vector(2 downto 0) := "101"; type mcycletype is (midle, active, leadout); type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8, wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd); type icycletype is (iidle, pre, ref, lmode, emode, finish); -- sdram configuration register type sdram_cfg_type is record command : std_logic_vector(2 downto 0); csize : std_logic_vector(1 downto 0); bsize : std_logic_vector(2 downto 0); casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles trfc : std_logic_vector(2 downto 0); trp : std_ulogic; -- precharge to activate: 2/3 clock cycles refresh : std_logic_vector(14 downto 0); renable : std_ulogic; pageburst : std_ulogic; mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update) tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update) pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update) pmode : std_logic_vector(2 downto 0); -- Power-Saving mode txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing cke : std_ulogic; -- Clock enable end record; -- local registers type reg_type is record hready : std_ulogic; hsel : std_ulogic; bdrive : std_ulogic; burst : std_ulogic; busy : std_ulogic; bdelay : std_ulogic; wprothit : std_ulogic; startsd : std_ulogic; aload : std_ulogic; mstate : mcycletype; sdstate : sdcycletype; cmstate : mcycletype; istate : icycletype; icnt : std_logic_vector(2 downto 0); cfg : sdram_cfg_type; trfc : std_logic_vector(3 downto 0); refresh : std_logic_vector(14 downto 0); sdcsn : std_logic_vector(1 downto 0); sdwen : std_ulogic; rasn : std_ulogic; casn : std_ulogic; dqm : std_logic_vector(7 downto 0); bsel : std_ulogic; haddr : std_logic_vector(31 downto 10); -- only needed to keep address lines from switch too much address : std_logic_vector(16 downto 2); -- memory address idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref end record; signal r, ri : reg_type; begin ctrl : process(rst, apbi, sdi, wpo, r) variable v : reg_type; -- local variables for registers variable startsd : std_ulogic; variable dataout : std_logic_vector(31 downto 0); -- data from memory variable haddr : std_logic_vector(31 downto 0); variable regsd : std_logic_vector(31 downto 0); -- data from registers variable dqm : std_logic_vector(7 downto 0); variable raddr : std_logic_vector(12 downto 0); variable adec : std_ulogic; variable busy : std_ulogic; variable aload : std_ulogic; variable rams : std_logic_vector(1 downto 0); variable hresp : std_logic_vector(1 downto 0); variable ba : std_logic_vector(1 downto 0); variable lline : std_logic_vector(2 downto 0); variable rline : std_logic_vector(2 downto 0); variable lineburst : boolean; variable arefresh : std_logic; begin -- Variable default settings to avoid latches v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY; lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel; rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel; arefresh := '0'; if sdi.hready = '1' then v.hsel := sdi.hsel; end if; if (sdi.hready and sdi.hsel ) = '1' then if sdi.htrans(1) = '1' then v.hready := '0'; end if; end if; if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if; if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then lineburst := true; else lineburst := false; end if; -- main state case sdi.hsize is when "00" => case sdi.rhaddr(1 downto 0) is when "00" => dqm := "11110111"; when "01" => dqm := "11111011"; when "10" => dqm := "11111101"; when others => dqm := "11111110"; end case; when "01" => if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if; when others => dqm := "11110000"; end case; if BUS64 and (r.bsel = '1') then dqm := dqm(3 downto 0) & "1111"; end if; -- main FSM case r.mstate is when midle => if (v.hsel and sdi.nhtrans(1)) = '1' then if (r.sdstate = sidle) and (r.cfg.command = "000") and (r.cmstate = midle) and (sdi.idle = '1') then if fast = 1 then v.startsd := '1'; else startsd := '1'; end if; v.mstate := active; elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd)) and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0') then v.startsd := '1'; if r.sdstate = dpd then -- Error response when on Deep Power-Down mode hresp := HRESP_ERROR; else v.mstate := active; end if; end if; end if; when others => null; end case; startsd := r.startsd or startsd; -- generate row and column address size case r.cfg.csize is when "00" => raddr := haddr(22 downto 10); when "01" => raddr := haddr(23 downto 11); when "10" => raddr := haddr(24 downto 12); when others => if r.cfg.bsize = "111" then raddr := haddr(26 downto 14); else raddr := haddr(25 downto 13); end if; end case; -- generate bank address ba := genmux(r.cfg.bsize, haddr(28 downto 21)) & genmux(r.cfg.bsize, haddr(27 downto 20)); -- generate chip select if BUS64 then adec := genmux(r.cfg.bsize, haddr(30 downto 23)); v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22)); else adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0'; end if; if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if; rams := adec & not adec; if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if; if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if; -- sdram access FSM case r.sdstate is when sidle => v.bdelay := '0'; if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then v.address(16 downto 2) := ba & raddr; v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1; v.startsd := '0'; elsif (r.idlecnt = "0000") and (r.cfg.command = "000") and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then case r.cfg.pmode is when PM_SR => v.cfg.cke := '0'; v.sdstate := sref; v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS) when PM_PD => v.cfg.cke := '0'; v.sdstate := pd; when PM_DPD => v.cfg.cke := '0'; v.sdstate := dpd; v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1'; when others => end case; end if; when act1 => v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10); if r.cfg.casdel = '1' then v.sdstate := act2; else v.sdstate := act3; v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1); end if; if WPROTEN then v.wprothit := wpo.wprothit; if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if; end if; when act2 => v.sdstate := act3; v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1); if WPROTEN and (r.wprothit = '1') then hresp := HRESP_ERROR; v.hready := '0'; end if; when act3 => v.casn := '0'; v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2); v.dqm := dqm; v.burst := r.hready; if sdi.hwrite = '1' then v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1'; if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if; if WPROTEN and (r.wprothit = '1') then hresp := HRESP_ERROR; v.hready := '1'; v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1'; end if; else v.sdstate := rd1; end if; when wr1 => v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2); if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11")) and not (WPROTEN and (r.wprothit = '1')) then v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready; if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh v.hready := '0'; end if; else v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1'; v.dqm := (others => '1'); end if; when wr2 => if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3; elsif (r.trfc(2 downto 1) = "00") then if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if; v.sdstate := wr3; end if; when wr3 => if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3; elsif (r.cfg.trp = '1') then v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; else v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; if r.trfc = "0000" then v.sdstate := sidle; end if; end if; when wr4 => v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; if (r.cfg.trp = '1') then v.sdstate := wr5; else if r.trfc = "0000" then v.sdstate := sidle; end if; end if; when wr5 => if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if; when rd1 => v.casn := '1'; v.sdstate := rd7; if lineburst and (sdi.htrans = "11") then if sdi.rhaddr(4 downto 2) = "111" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; when rd7 => v.casn := '1'; if r.cfg.casdel = '1' then v.sdstate := rd2; if lineburst and (sdi.htrans = "11") then if sdi.rhaddr(4 downto 2) = "110" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; else v.sdstate := rd3; if sdi.htrans /= "11" then if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if; elsif lineburst then if sdi.rhaddr(4 downto 2) = "110" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; end if; when rd2 => v.casn := '1'; v.sdstate := rd3; if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0'; if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if; elsif lineburst then if sdi.rhaddr(4 downto 2) = "101" then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; if v.sdwen = '0' then v.dqm := (others => '1'); end if; when rd3 => v.sdstate := rd4; v.hready := '1'; v.casn := '1'; if r.sdwen = '0' then v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1'); elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; when rd4 => v.hready := '1'; v.casn := '1'; if (sdi.htrans /= "11") or (r.sdcsn = "11") or ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh then v.hready := '0'; v.dqm := (others => '1'); if (r.sdcsn /= "11") then v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5; else if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; end if; elsif lineburst then if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then v.address(9 downto 5) := r.address(9 downto 5) + 1; v.address(4 downto 2) := "000"; v.casn := '0'; end if; end if; when rd5 => if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if; v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1'); v.casn := '1'; when rd6 => v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1'); v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; when sref => if (startsd = '1') -- and (r.hio = '0')) or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then if r.trfc = "0000" then -- Minimum duration (= tRAS) v.cfg.cke := '1'; v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1'; end if; if r.cfg.cke = '1' then if (r.idlecnt = "0000") then -- tXSR ns with NOP v.sdstate := sidle; v.idlecnt := (others => '1'); v.sref_tmpcom := r.cfg.command; v.cfg.command := "100"; end if; else v.idlecnt := r.cfg.txsr; end if; end if; when pd => if (startsd = '1') -- and (r.hio = '0')) or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then v.cfg.cke := '1'; v.sdstate := sidle; v.idlecnt := (others => '1'); end if; when dpd => v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1'; v.cfg.renable := '0'; if (startsd = '1') then -- and r.hio = '0') then v.hready := '1'; -- ack all accesses with Error response v.startsd := '0'; hresp := HRESP_ERROR; elsif r.cfg.pmode /= PM_DPD then v.cfg.cke := '1'; if r.cfg.cke = '1' then v.sdstate := sidle; v.idlecnt := (others => '1'); v.cfg.renable := '1'; end if; end if; when others => v.sdstate := sidle; v.idlecnt := (others => '1'); end case; -- sdram commands case r.cmstate is when midle => if r.sdstate = sidle then case r.cfg.command is when "010" => -- precharge if (sdi.idle = '1') then v.busy := '1'; v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0'; v.address(12) := '1'; v.cmstate := active; end if; when "100" => -- auto-refresh v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.cmstate := active; when "110" => if (sdi.idle = '1') then v.busy := '1'; v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.sdwen := '0'; v.cmstate := active; if lineburst then v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011"; else v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111"; end if; end if; when "111" => -- Load Ext-Mode Reg if (sdi.idle = '1') then v.busy := '1'; v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0'; v.sdwen := '0'; v.cmstate := active; v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0); end if; when others => null; end case; end if; when active => v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1'; v.sdwen := '1'; --v.cfg.command := "000"; v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000"; v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; when leadout => if r.trfc = "0000" then v.cmstate := midle; end if; end case; -- sdram init case r.istate is when iidle => v.cfg.cke := '1'; if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then v.cfg.command := "010"; v.istate := pre; end if; when pre => if r.cfg.command = "000" then v.cfg.command := "100"; v.istate := ref; v.icnt := "111"; end if; when ref => if r.cfg.command = "000" then v.cfg.command := "100"; v.icnt := r.icnt - 1; if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if; end if; when lmode => if r.cfg.command = "000" then if r.cfg.mobileen = "11" then v.cfg.command := "111"; v.istate := emode; else v.istate := finish; end if; end if; when emode => if r.cfg.command = "000" then v.istate := finish; end if; when others => if sdi.enable = '0' and r.sdstate /= dpd then v.istate := iidle; end if; end case; if (sdi.hready and sdi.hsel ) = '1' then if sdi.htrans(1) = '0' then v.hready := '1'; end if; end if; -- second part of main fsm case r.mstate is when active => if v.hready = '1' then v.mstate := midle; end if; when others => null; end case; -- sdram refresh counter if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then v.refresh := r.refresh - 1; if (v.refresh(14) and not r.refresh(14)) = '1' then v.refresh := r.cfg.refresh; v.cfg.command := "100"; arefresh := '1'; end if; end if; -- APB register access if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case apbi.paddr(3 downto 2) is when "01" => if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if; if sdi.enable = '1' then v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19); end if; v.cfg.csize := apbi.pwdata(22 downto 21); v.cfg.bsize := apbi.pwdata(25 downto 23); v.cfg.casdel := apbi.pwdata(26); v.cfg.trfc := apbi.pwdata(29 downto 27); v.cfg.trp := apbi.pwdata(30); v.cfg.renable := apbi.pwdata(31); when "10" => v.cfg.refresh := apbi.pwdata(26 downto 12); v.refresh := (others => '0'); when "11" => if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if; if r.cfg.pmode = "000" then v.cfg.cke := apbi.pwdata(30); end if; if r.cfg.mobileen(1) = '1' then if sdi.enable = '1' then v.cfg.command(0) := apbi.pwdata(29); end if; v.cfg.txsr := apbi.pwdata(23 downto 20); v.cfg.pmode := apbi.pwdata(18 downto 16); v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5); v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3); v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0); end if; when others => end case; end if; -- Disable CS and DPD when Mobile SDR is Disabled if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if; -- Update EMR when ds, tcsr or pasr change if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2); end if; if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2); end if; if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3); end if; end if; regsd := (others => '0'); case apbi.paddr(3 downto 2) is when "01" => regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc & r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1); if not lineburst then regsd(17) := '1'; end if; regsd(16) := r.cfg.mobileen(1); when "11" => regsd(31) := r.cfg.mobileen(0); regsd(30) := r.cfg.cke; regsd(30) := r.cfg.command(0); regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0); when others => regsd(26 downto 12) := r.cfg.refresh; end case; sdmo.prdata <= regsd; -- synchronise with sram/prom controller if fast = 0 then if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if; else if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if; end if; v.busy := v.busy or r.bdelay; busy := v.busy or r.busy; v.aload := r.busy and not v.busy; aload := v.aload; -- generate memory address sdmo.address <= v.address; -- reset if rst = '0' then v.sdstate := sidle; v.mstate := midle; v.istate := iidle; v.cmstate := midle; v.hsel := '0'; v.cfg.command := "000"; v.cfg.csize := "10"; v.cfg.bsize := "000"; v.cfg.casdel := '1'; v.cfg.trfc := "111"; v.cfg.renable := '0'; v.cfg.trp := '1'; v.dqm := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1'; v.hready := '1'; v.startsd := '0'; if (pageburst = 2) then v.cfg.pageburst := '0'; end if; if mobile >= 2 then v.cfg.mobileen := "11"; elsif mobile = 1 then v.cfg.mobileen := "10"; else v.cfg.mobileen := "00"; end if; v.cfg.txsr := (others => '1'); v.cfg.pmode := (others => '0'); v.cfg.ds := (others => '0'); v.cfg.tcsr := (others => '0'); v.cfg.pasr := (others => '0'); if mobile >= 2 then v.cfg.cke := '0'; else v.cfg.cke := '1'; end if; v.sref_tmpcom := "000"; v.idlecnt := (others => '1'); end if; ri <= v; sdmo.bdrive <= v.bdrive; --sdo.sdcke <= (others => '1'); sdo.sdcke <= (others => r.cfg.cke); sdo.sdcsn <= r.sdcsn; sdo.sdwen <= r.sdwen; sdo.dqm <= r.dqm; sdo.rasn <= r.rasn; sdo.casn <= r.casn; sdmo.busy <= busy; sdmo.aload <= aload; sdmo.hready <= r.hready; sdmo.vhready <= v.hready; sdmo.hresp <= hresp; sdmo.hsel <= r.hsel; sdmo.bsel <= r.bsel; end process; regs : process(clk,rst) begin if rising_edge(clk) then r <= ri; if rst = '0' then r.icnt <= (others => '0'); end if; end if; if rst = '0' then r.bdrive <= '0'; r.sdcsn <= (others => '1'); end if; end process; end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1018.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s03b00x00p10n01i01018ent IS port (p : in bit); END c06s03b00x00p10n01i01018ent; ARCHITECTURE c06s03b00x00p10n01i01018arch OF c06s03b00x00p10n01i01018ent IS BEGIN b1 : block type chars is ('a','b','c'); signal bs1 : BIT; begin B2: block signal bs2 : BIT; begin process begin NULL; end process; b3 : block signal bs3a : BIT; signal bs3b : BIT; begin bs3b <= B1.bs2; -- ERROR: Entity defined by selected -- suffix not declared within construct -- denoted by selected prefix. end block b3; end block B2; end block b1; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c06s03b00x00p10n01i01018 - Entity declaration does not occur in construct specifed by the prefix." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p10n01i01018arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1018.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s03b00x00p10n01i01018ent IS port (p : in bit); END c06s03b00x00p10n01i01018ent; ARCHITECTURE c06s03b00x00p10n01i01018arch OF c06s03b00x00p10n01i01018ent IS BEGIN b1 : block type chars is ('a','b','c'); signal bs1 : BIT; begin B2: block signal bs2 : BIT; begin process begin NULL; end process; b3 : block signal bs3a : BIT; signal bs3b : BIT; begin bs3b <= B1.bs2; -- ERROR: Entity defined by selected -- suffix not declared within construct -- denoted by selected prefix. end block b3; end block B2; end block b1; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c06s03b00x00p10n01i01018 - Entity declaration does not occur in construct specifed by the prefix." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p10n01i01018arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1018.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c06s03b00x00p10n01i01018ent IS port (p : in bit); END c06s03b00x00p10n01i01018ent; ARCHITECTURE c06s03b00x00p10n01i01018arch OF c06s03b00x00p10n01i01018ent IS BEGIN b1 : block type chars is ('a','b','c'); signal bs1 : BIT; begin B2: block signal bs2 : BIT; begin process begin NULL; end process; b3 : block signal bs3a : BIT; signal bs3b : BIT; begin bs3b <= B1.bs2; -- ERROR: Entity defined by selected -- suffix not declared within construct -- denoted by selected prefix. end block b3; end block B2; end block b1; TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c06s03b00x00p10n01i01018 - Entity declaration does not occur in construct specifed by the prefix." severity ERROR; wait; END PROCESS TESTING; END c06s03b00x00p10n01i01018arch;
-- $Id: sys_conf2_sim.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> -- ------------------------------------------------------------------------------ -- Package Name: sys_conf -- Description: Definitions for sys_tst_serloop2_n4d (for test bench) -- -- Dependencies: - -- Tool versions: 2016.2; ghdl 0.33 -- Revision History: -- Date Rev Version Comment -- 2017-01-04 838 1.0 Initial version ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use work.slvtypes.all; package sys_conf is -- in simulation a usec stays to 120 cycles (1.0 usec) and a msec to -- 240 cycles (2 usec). This affects mainly the autobauder. A break will be -- detected after 128 msec periods, this in simulation after 256 usec or -- 30720 cycles. This is compatible with bitrates of 115200 baud or higher -- (115200 <-> 8.68 usec <-> 1040 cycles) -- configure clocks -------------------------------------------------------- constant sys_conf_clksys_vcodivide : positive := 5; -- f 20 Mhz constant sys_conf_clksys_vcomultiply : positive := 36; -- vco 720 MHz constant sys_conf_clksys_outdivide : positive := 10; -- sys 72 MHz constant sys_conf_clksys_gentype : string := "MMCM"; constant sys_conf_clksys_msecdiv : integer := 2; -- shortened !! constant sys_conf_clkser_vcodivide : positive := 1; constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz constant sys_conf_clkser_gentype : string := "PLL"; constant sys_conf_clkser_msecdiv : integer := 2; -- shortened !! -- configure hio interfaces ----------------------------------------------- constant sys_conf_hio_debounce : boolean := false; -- no debouncers -- configure serport ------------------------------------------------------ constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim -- derived constants ======================================================= constant sys_conf_clksys : integer := ((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) / sys_conf_clksys_outdivide; constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000; constant sys_conf_clkser : integer := ((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) / sys_conf_clkser_outdivide; constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000; end package sys_conf;
library ieee; use ieee.std_logic_1164.all; use work.arch_defs.all; entity linkMux is port ( Link : in ctrl_t; pc : in word_t; memToRegMux: in word_t; output: out word_t ); end entity; architecture behav of linkMux is begin output <= pc when Link = '1' else memToRegMux; end architecture behav;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity sub_345 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end sub_345; architecture augh of sub_345 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '0' - CI -- If CI is not present, the operation is '0' - '0' carry_inA <= '0' & in_a & '0'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity sub_345 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end sub_345; architecture augh of sub_345 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '0' - CI -- If CI is not present, the operation is '0' - '0' carry_inA <= '0' & in_a & '0'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Sun Apr 09 09:37:58 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl -- Design : system_vga_sync_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_vga_sync_0_0_vga_sync is port ( xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); hsync : out STD_LOGIC; vsync : out STD_LOGIC; active : out STD_LOGIC; clk_25 : in STD_LOGIC; rst : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_vga_sync_0_0_vga_sync : entity is "vga_sync"; end system_vga_sync_0_0_vga_sync; architecture STRUCTURE of system_vga_sync_0_0_vga_sync is signal active_INST_0_i_1_n_0 : STD_LOGIC; signal h_count_next : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \h_count_reg[4]_i_1_n_0\ : STD_LOGIC; signal \h_count_reg[5]_i_2_n_0\ : STD_LOGIC; signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC; signal \h_count_reg[9]_i_3_n_0\ : STD_LOGIC; signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC; signal h_sync_next : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 ); signal sel : STD_LOGIC; signal \v_count_reg[3]_i_2_n_0\ : STD_LOGIC; signal \v_count_reg[6]_i_1_n_0\ : STD_LOGIC; signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC; signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC; signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC; signal v_sync_next : STD_LOGIC; signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of active_INST_0_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \h_count_reg[5]_i_2\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \h_count_reg[9]_i_3\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \v_count_reg[3]_i_2\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \v_count_reg[6]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair0"; begin xaddr(9 downto 0) <= \^xaddr\(9 downto 0); yaddr(9 downto 0) <= \^yaddr\(9 downto 0); active_INST_0: unisim.vcomponents.LUT5 generic map( INIT => X"000002AA" ) port map ( I0 => active_INST_0_i_1_n_0, I1 => \^xaddr\(8), I2 => \^xaddr\(7), I3 => \^xaddr\(9), I4 => \^yaddr\(9), O => active ); active_INST_0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \^yaddr\(6), I1 => \^yaddr\(5), I2 => \^yaddr\(7), I3 => \^yaddr\(8), O => active_INST_0_i_1_n_0 ); \h_count_reg[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^xaddr\(0), O => h_count_next(0) ); \h_count_reg[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^xaddr\(0), I1 => \^xaddr\(1), O => h_count_next(1) ); \h_count_reg[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^xaddr\(0), I1 => \^xaddr\(1), I2 => \^xaddr\(2), O => h_count_next(2) ); \h_count_reg[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \^xaddr\(3), I1 => \^xaddr\(0), I2 => \^xaddr\(1), I3 => \^xaddr\(2), O => h_count_next(3) ); \h_count_reg[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \^xaddr\(4), I1 => \^xaddr\(2), I2 => \^xaddr\(1), I3 => \^xaddr\(0), I4 => \^xaddr\(3), O => \h_count_reg[4]_i_1_n_0\ ); \h_count_reg[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF00000000FFBF" ) port map ( I0 => \^xaddr\(6), I1 => \^xaddr\(8), I2 => \^xaddr\(9), I3 => \^xaddr\(7), I4 => \h_count_reg[5]_i_2_n_0\, I5 => \^xaddr\(5), O => h_count_next(5) ); \h_count_reg[5]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => \^xaddr\(2), I1 => \^xaddr\(1), I2 => \^xaddr\(0), I3 => \^xaddr\(3), I4 => \^xaddr\(4), O => \h_count_reg[5]_i_2_n_0\ ); \h_count_reg[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA6A" ) port map ( I0 => \^xaddr\(6), I1 => \^xaddr\(4), I2 => \^xaddr\(5), I3 => \h_count_reg[9]_i_3_n_0\, O => h_count_next(6) ); \h_count_reg[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAAA" ) port map ( I0 => \^xaddr\(7), I1 => \h_count_reg[9]_i_3_n_0\, I2 => \^xaddr\(5), I3 => \^xaddr\(4), I4 => \^xaddr\(6), O => h_count_next(7) ); \h_count_reg[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FF0B00B0" ) port map ( I0 => \h_count_reg[9]_i_2_n_0\, I1 => \^xaddr\(4), I2 => \h_count_reg[9]_i_4_n_0\, I3 => \h_count_reg[9]_i_3_n_0\, I4 => \^xaddr\(8), O => h_count_next(8) ); \h_count_reg[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0FBFBFB0B000000" ) port map ( I0 => \h_count_reg[9]_i_2_n_0\, I1 => \^xaddr\(4), I2 => \h_count_reg[9]_i_3_n_0\, I3 => \h_count_reg[9]_i_4_n_0\, I4 => \^xaddr\(8), I5 => \^xaddr\(9), O => h_count_next(9) ); \h_count_reg[9]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFEFFF" ) port map ( I0 => \^xaddr\(6), I1 => \^xaddr\(5), I2 => \^xaddr\(8), I3 => \^xaddr\(9), I4 => \^xaddr\(7), O => \h_count_reg[9]_i_2_n_0\ ); \h_count_reg[9]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \^xaddr\(3), I1 => \^xaddr\(0), I2 => \^xaddr\(1), I3 => \^xaddr\(2), O => \h_count_reg[9]_i_3_n_0\ ); \h_count_reg[9]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \^xaddr\(7), I1 => \^xaddr\(6), I2 => \^xaddr\(5), I3 => \^xaddr\(4), O => \h_count_reg[9]_i_4_n_0\ ); \h_count_reg_reg[0]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(0), Q => \^xaddr\(0) ); \h_count_reg_reg[1]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(1), Q => \^xaddr\(1) ); \h_count_reg_reg[2]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(2), Q => \^xaddr\(2) ); \h_count_reg_reg[3]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(3), Q => \^xaddr\(3) ); \h_count_reg_reg[4]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => \h_count_reg[4]_i_1_n_0\, Q => \^xaddr\(4) ); \h_count_reg_reg[5]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(5), Q => \^xaddr\(5) ); \h_count_reg_reg[6]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(6), Q => \^xaddr\(6) ); \h_count_reg_reg[7]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(7), Q => \^xaddr\(7) ); \h_count_reg_reg[8]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(8), Q => \^xaddr\(8) ); \h_count_reg_reg[9]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => '1', CLR => rst, D => h_count_next(9), Q => \^xaddr\(9) ); h_sync_reg_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00002AA800000000" ) port map ( I0 => \^xaddr\(7), I1 => \^xaddr\(6), I2 => \^xaddr\(5), I3 => \^xaddr\(4), I4 => \^xaddr\(8), I5 => \^xaddr\(9), O => h_sync_next ); h_sync_reg_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => clk_25, CE => '1', D => h_sync_next, PRE => rst, Q => hsync ); \v_count_reg[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"5555555545555555" ) port map ( I0 => \^yaddr\(0), I1 => \v_count_reg[9]_i_4_n_0\, I2 => \^yaddr\(9), I3 => \^yaddr\(2), I4 => \^yaddr\(3), I5 => \^yaddr\(7), O => p_0_in(0) ); \v_count_reg[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^yaddr\(0), I1 => \^yaddr\(1), O => p_0_in(1) ); \v_count_reg[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"55AA55AA45AA55AA" ) port map ( I0 => \v_count_reg[3]_i_2_n_0\, I1 => \v_count_reg[9]_i_4_n_0\, I2 => \^yaddr\(9), I3 => \^yaddr\(2), I4 => \^yaddr\(3), I5 => \^yaddr\(7), O => p_0_in(2) ); \v_count_reg[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"55FFAA0045FFAA00" ) port map ( I0 => \v_count_reg[3]_i_2_n_0\, I1 => \v_count_reg[9]_i_4_n_0\, I2 => \^yaddr\(9), I3 => \^yaddr\(2), I4 => \^yaddr\(3), I5 => \^yaddr\(7), O => p_0_in(3) ); \v_count_reg[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^yaddr\(0), I1 => \^yaddr\(1), O => \v_count_reg[3]_i_2_n_0\ ); \v_count_reg[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \^yaddr\(4), I1 => \^yaddr\(2), I2 => \^yaddr\(3), I3 => \^yaddr\(0), I4 => \^yaddr\(1), O => p_0_in(4) ); \v_count_reg[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \^yaddr\(5), I1 => \^yaddr\(1), I2 => \^yaddr\(0), I3 => \^yaddr\(3), I4 => \^yaddr\(2), I5 => \^yaddr\(4), O => p_0_in(5) ); \v_count_reg[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \^yaddr\(6), I1 => \v_count_reg[9]_i_5_n_0\, I2 => \^yaddr\(5), O => \v_count_reg[6]_i_1_n_0\ ); \v_count_reg[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \^yaddr\(7), I1 => \^yaddr\(5), I2 => \v_count_reg[9]_i_5_n_0\, I3 => \^yaddr\(6), O => p_0_in(7) ); \v_count_reg[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \^yaddr\(8), I1 => \^yaddr\(6), I2 => \v_count_reg[9]_i_5_n_0\, I3 => \^yaddr\(5), I4 => \^yaddr\(7), O => p_0_in(8) ); \v_count_reg[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000001000" ) port map ( I0 => \^xaddr\(6), I1 => \^xaddr\(5), I2 => \^xaddr\(8), I3 => \^xaddr\(9), I4 => \^xaddr\(7), I5 => \h_count_reg[5]_i_2_n_0\, O => sel ); \v_count_reg[9]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"D0D00DD0" ) port map ( I0 => \v_count_reg[9]_i_3_n_0\, I1 => \v_count_reg[9]_i_4_n_0\, I2 => \^yaddr\(9), I3 => \v_count_reg[9]_i_5_n_0\, I4 => active_INST_0_i_1_n_0, O => p_0_in(9) ); \v_count_reg[9]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \^yaddr\(9), I1 => \^yaddr\(2), I2 => \^yaddr\(3), I3 => \^yaddr\(7), O => \v_count_reg[9]_i_3_n_0\ ); \v_count_reg[9]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \^yaddr\(1), I1 => \^yaddr\(0), I2 => \^yaddr\(6), I3 => \^yaddr\(8), I4 => \^yaddr\(4), I5 => \^yaddr\(5), O => \v_count_reg[9]_i_4_n_0\ ); \v_count_reg[9]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => \^yaddr\(4), I1 => \^yaddr\(2), I2 => \^yaddr\(3), I3 => \^yaddr\(0), I4 => \^yaddr\(1), O => \v_count_reg[9]_i_5_n_0\ ); \v_count_reg_reg[0]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(0), Q => \^yaddr\(0) ); \v_count_reg_reg[1]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(1), Q => \^yaddr\(1) ); \v_count_reg_reg[2]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(2), Q => \^yaddr\(2) ); \v_count_reg_reg[3]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(3), Q => \^yaddr\(3) ); \v_count_reg_reg[4]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(4), Q => \^yaddr\(4) ); \v_count_reg_reg[5]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(5), Q => \^yaddr\(5) ); \v_count_reg_reg[6]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => \v_count_reg[6]_i_1_n_0\, Q => \^yaddr\(6) ); \v_count_reg_reg[7]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(7), Q => \^yaddr\(7) ); \v_count_reg_reg[8]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(8), Q => \^yaddr\(8) ); \v_count_reg_reg[9]\: unisim.vcomponents.FDCE port map ( C => clk_25, CE => sel, CLR => rst, D => p_0_in(9), Q => \^yaddr\(9) ); v_sync_reg_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000040000" ) port map ( I0 => \^yaddr\(9), I1 => \^yaddr\(3), I2 => \^yaddr\(4), I3 => \^yaddr\(2), I4 => \^yaddr\(1), I5 => active_INST_0_i_1_n_0, O => v_sync_next ); v_sync_reg_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => clk_25, CE => '1', D => v_sync_next, PRE => rst, Q => vsync ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_vga_sync_0_0 is port ( clk_25 : in STD_LOGIC; rst : in STD_LOGIC; active : out STD_LOGIC; hsync : out STD_LOGIC; vsync : out STD_LOGIC; xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4"; end system_vga_sync_0_0; architecture STRUCTURE of system_vga_sync_0_0 is begin U0: entity work.system_vga_sync_0_0_vga_sync port map ( active => active, clk_25 => clk_25, hsync => hsync, rst => rst, vsync => vsync, xaddr(9 downto 0) => xaddr(9 downto 0), yaddr(9 downto 0) => yaddr(9 downto 0) ); end STRUCTURE;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1592.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s11b00x00p03n01i01592ent IS END c08s11b00x00p03n01i01592ent; ARCHITECTURE c08s11b00x00p03n01i01592arch OF c08s11b00x00p03n01i01592ent IS BEGIN TESTING: PROCESS BEGIN for i in 1 to 10 loop exit L; end loop; assert FALSE report "***FAILED TEST: c08s11b00x00p03n01i01592 - A loop label is not allowed in an exit statement which is in an unlabeled loop" severity ERROR; wait; END PROCESS TESTING; END c08s11b00x00p03n01i01592arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1592.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s11b00x00p03n01i01592ent IS END c08s11b00x00p03n01i01592ent; ARCHITECTURE c08s11b00x00p03n01i01592arch OF c08s11b00x00p03n01i01592ent IS BEGIN TESTING: PROCESS BEGIN for i in 1 to 10 loop exit L; end loop; assert FALSE report "***FAILED TEST: c08s11b00x00p03n01i01592 - A loop label is not allowed in an exit statement which is in an unlabeled loop" severity ERROR; wait; END PROCESS TESTING; END c08s11b00x00p03n01i01592arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1592.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s11b00x00p03n01i01592ent IS END c08s11b00x00p03n01i01592ent; ARCHITECTURE c08s11b00x00p03n01i01592arch OF c08s11b00x00p03n01i01592ent IS BEGIN TESTING: PROCESS BEGIN for i in 1 to 10 loop exit L; end loop; assert FALSE report "***FAILED TEST: c08s11b00x00p03n01i01592 - A loop label is not allowed in an exit statement which is in an unlabeled loop" severity ERROR; wait; END PROCESS TESTING; END c08s11b00x00p03n01i01592arch;
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd) -- Written by Gandhi Puvvada -- date of last rivision: 7/23/2008 -- -- A package file to define the instruction stream to be placed in the instr_cache. -- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module. -- We will use several files similar to this containining different instruction streams. -- The package name will remain the same, namely instr_stream_pkg. -- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd -- to say mult_test_stream_instr_stream_pkg.vhd. -- Depending on which instr_stream_pkg file was analysed/compiled most recently, -- that stream will be used for simulation/synthesis. ---------------------------------------------------------- library std, ieee; use ieee.std_logic_1164.all; package instr_stream_pkg is constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache -- type declarations type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0); --------------------------------------------------- --------------------------------------------------- -- All instructions are div $2 $3 $2 --------------------------------------------------- --------------------------------------------------- signal mem : mem_type := (X"0062101B_0062101B_0062101B_0062101B", -- Loc 0C, 08, 04, 00 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1C, 18, 14, 10 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2C, 28, 24, 20 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3C, 38, 34, 30 X"0062101B_0062101B_0062101B_0062101B", -- Loc 4C, 48, 44, 40 X"0062101B_0062101B_0062101B_0062101B", -- Loc 5C, 58, 54, 50 X"0062101B_0062101B_0062101B_0062101B", -- Loc 6C, 68, 64, 60 X"0062101B_0062101B_0062101B_0062101B", -- Loc 7C, 78, 74, 70 X"0062101B_0062101B_0062101B_0062101B", -- Loc 8C, 88, 84, 80 X"0062101B_0062101B_0062101B_0062101B", -- Loc 9C, 98, 94, 90 X"0062101B_0062101B_0062101B_0062101B", -- Loc AC, A8, A4, A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc BC, B8, B4, B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc CC, C8, C4, C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc DC, D8, D4, D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc EC, E8, E4, E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc FC, F8, F4, F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 10C, 108, 104, 100 X"0062101B_0062101B_0062101B_0062101B", -- Loc 11C, 118, 114, 110 X"0062101B_0062101B_0062101B_0062101B", -- Loc 12C, 128, 124, 120 X"0062101B_0062101B_0062101B_0062101B", -- Loc 13C, 138, 134, 130 X"0062101B_0062101B_0062101B_0062101B", -- Loc 14C, 148, 144, 140 X"0062101B_0062101B_0062101B_0062101B", -- Loc 15C, 158, 154, 150 X"0062101B_0062101B_0062101B_0062101B", -- Loc 16C, 168, 164, 160 X"0062101B_0062101B_0062101B_0062101B", -- Loc 17C, 178, 174, 170 X"0062101B_0062101B_0062101B_0062101B", -- Loc 18C, 188, 184, 180 X"0062101B_0062101B_0062101B_0062101B", -- Loc 19C, 198, 194, 190 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1AC, 1A8, 1A4, 1A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1BC, 1B8, 1B4, 1B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1CC, 1C8, 1C4, 1C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1DC, 1D8, 1D4, 1D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1EC, 1E8, 1E4, 1E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1FC, 1F8, 1F4, 1F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 20C, 208, 204, 200 X"0062101B_0062101B_0062101B_0062101B", -- Loc 21C, 218, 214, 221 X"0062101B_0062101B_0062101B_0062101B", -- Loc 22C, 228, 224, 220 X"0062101B_0062101B_0062101B_0062101B", -- Loc 23C, 238, 234, 230 X"0062101B_0062101B_0062101B_0062101B", -- Loc 24C, 248, 244, 240 X"0062101B_0062101B_0062101B_0062101B", -- Loc 25C, 258, 254, 250 X"0062101B_0062101B_0062101B_0062101B", -- Loc 26C, 268, 264, 260 X"0062101B_0062101B_0062101B_0062101B", -- Loc 27C, 278, 274, 270 X"0062101B_0062101B_0062101B_0062101B", -- Loc 28C, 288, 284, 280 X"0062101B_0062101B_0062101B_0062101B", -- Loc 29C, 298, 294, 290 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2AC, 2A8, 2A4, 2A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2BC, 2B8, 2B4, 2B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2CC, 2C8, 2C4, 2C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2DC, 2D8, 2D4, 2D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2EC, 2E8, 2E4, 2E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2FC, 2F8, 2F4, 2F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 30C, 308, 304, 300 X"0062101B_0062101B_0062101B_0062101B", -- Loc 31C, 318, 314, 331 X"0062101B_0062101B_0062101B_0062101B", -- Loc 32C, 328, 324, 320 X"0062101B_0062101B_0062101B_0062101B", -- Loc 33C, 338, 334, 330 X"0062101B_0062101B_0062101B_0062101B", -- Loc 34C, 348, 344, 340 X"0062101B_0062101B_0062101B_0062101B", -- Loc 35C, 358, 354, 350 X"0062101B_0062101B_0062101B_0062101B", -- Loc 36C, 368, 364, 360 X"0062101B_0062101B_0062101B_0062101B", -- Loc 37C, 378, 374, 370 X"0062101B_0062101B_0062101B_0062101B", -- Loc 38C, 388, 384, 380 X"0062101B_0062101B_0062101B_0062101B", -- Loc 39C, 398, 394, 390 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3AC, 3A8, 3A4, 3A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3BC, 3B8, 3B4, 3B0 -- the last 16 instructions are looping ump instructions X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0 X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0 X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0 X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0 ) ; -- the last 16 instructions are looping jump instructions -- of the type: loop: j loop -- This is to make sure that neither instruction fetching -- nor instruction execution proceeds beyond the end of this memory. -- Loc 3C0 -- 080000F0 => J 240 -- Loc 3C4 -- 080000F1 => J 241 -- Loc 3C8 -- 080000F2 => J 242 -- Loc 3CC -- 080000F3 => J 243 -- -- Loc 3D0 -- 080000F4 => J 244 -- Loc 3D4 -- 080000F5 => J 245 -- Loc 3D8 -- 080000F6 => J 246 -- Loc 3DC -- 080000F7 => J 247 -- -- Loc 3E0 -- 080000F8 => J 248 -- Loc 3E4 -- 080000F9 => J 249 -- Loc 3E8 -- 080000FA => J 250 -- Loc 3EC -- 080000FB => J 251 -- -- Loc 3F0 -- 080000FC => J 252 -- Loc 3F4 -- 080000FD => J 253 -- Loc 3F8 -- 080000FE => J 254 -- Loc 3FC -- 080000FF => J 255 end package instr_stream_pkg; -- -- No need for s package body here -- package body instr_stream_pkg is -- -- end package body instr_stream_pkg;
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd) -- Written by Gandhi Puvvada -- date of last rivision: 7/23/2008 -- -- A package file to define the instruction stream to be placed in the instr_cache. -- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module. -- We will use several files similar to this containining different instruction streams. -- The package name will remain the same, namely instr_stream_pkg. -- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd -- to say mult_test_stream_instr_stream_pkg.vhd. -- Depending on which instr_stream_pkg file was analysed/compiled most recently, -- that stream will be used for simulation/synthesis. ---------------------------------------------------------- library std, ieee; use ieee.std_logic_1164.all; package instr_stream_pkg is constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache -- type declarations type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0); --------------------------------------------------- --------------------------------------------------- -- All instructions are div $2 $3 $2 --------------------------------------------------- --------------------------------------------------- signal mem : mem_type := (X"0062101B_0062101B_0062101B_0062101B", -- Loc 0C, 08, 04, 00 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1C, 18, 14, 10 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2C, 28, 24, 20 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3C, 38, 34, 30 X"0062101B_0062101B_0062101B_0062101B", -- Loc 4C, 48, 44, 40 X"0062101B_0062101B_0062101B_0062101B", -- Loc 5C, 58, 54, 50 X"0062101B_0062101B_0062101B_0062101B", -- Loc 6C, 68, 64, 60 X"0062101B_0062101B_0062101B_0062101B", -- Loc 7C, 78, 74, 70 X"0062101B_0062101B_0062101B_0062101B", -- Loc 8C, 88, 84, 80 X"0062101B_0062101B_0062101B_0062101B", -- Loc 9C, 98, 94, 90 X"0062101B_0062101B_0062101B_0062101B", -- Loc AC, A8, A4, A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc BC, B8, B4, B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc CC, C8, C4, C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc DC, D8, D4, D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc EC, E8, E4, E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc FC, F8, F4, F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 10C, 108, 104, 100 X"0062101B_0062101B_0062101B_0062101B", -- Loc 11C, 118, 114, 110 X"0062101B_0062101B_0062101B_0062101B", -- Loc 12C, 128, 124, 120 X"0062101B_0062101B_0062101B_0062101B", -- Loc 13C, 138, 134, 130 X"0062101B_0062101B_0062101B_0062101B", -- Loc 14C, 148, 144, 140 X"0062101B_0062101B_0062101B_0062101B", -- Loc 15C, 158, 154, 150 X"0062101B_0062101B_0062101B_0062101B", -- Loc 16C, 168, 164, 160 X"0062101B_0062101B_0062101B_0062101B", -- Loc 17C, 178, 174, 170 X"0062101B_0062101B_0062101B_0062101B", -- Loc 18C, 188, 184, 180 X"0062101B_0062101B_0062101B_0062101B", -- Loc 19C, 198, 194, 190 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1AC, 1A8, 1A4, 1A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1BC, 1B8, 1B4, 1B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1CC, 1C8, 1C4, 1C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1DC, 1D8, 1D4, 1D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1EC, 1E8, 1E4, 1E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1FC, 1F8, 1F4, 1F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 20C, 208, 204, 200 X"0062101B_0062101B_0062101B_0062101B", -- Loc 21C, 218, 214, 221 X"0062101B_0062101B_0062101B_0062101B", -- Loc 22C, 228, 224, 220 X"0062101B_0062101B_0062101B_0062101B", -- Loc 23C, 238, 234, 230 X"0062101B_0062101B_0062101B_0062101B", -- Loc 24C, 248, 244, 240 X"0062101B_0062101B_0062101B_0062101B", -- Loc 25C, 258, 254, 250 X"0062101B_0062101B_0062101B_0062101B", -- Loc 26C, 268, 264, 260 X"0062101B_0062101B_0062101B_0062101B", -- Loc 27C, 278, 274, 270 X"0062101B_0062101B_0062101B_0062101B", -- Loc 28C, 288, 284, 280 X"0062101B_0062101B_0062101B_0062101B", -- Loc 29C, 298, 294, 290 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2AC, 2A8, 2A4, 2A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2BC, 2B8, 2B4, 2B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2CC, 2C8, 2C4, 2C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2DC, 2D8, 2D4, 2D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2EC, 2E8, 2E4, 2E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2FC, 2F8, 2F4, 2F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 30C, 308, 304, 300 X"0062101B_0062101B_0062101B_0062101B", -- Loc 31C, 318, 314, 331 X"0062101B_0062101B_0062101B_0062101B", -- Loc 32C, 328, 324, 320 X"0062101B_0062101B_0062101B_0062101B", -- Loc 33C, 338, 334, 330 X"0062101B_0062101B_0062101B_0062101B", -- Loc 34C, 348, 344, 340 X"0062101B_0062101B_0062101B_0062101B", -- Loc 35C, 358, 354, 350 X"0062101B_0062101B_0062101B_0062101B", -- Loc 36C, 368, 364, 360 X"0062101B_0062101B_0062101B_0062101B", -- Loc 37C, 378, 374, 370 X"0062101B_0062101B_0062101B_0062101B", -- Loc 38C, 388, 384, 380 X"0062101B_0062101B_0062101B_0062101B", -- Loc 39C, 398, 394, 390 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3AC, 3A8, 3A4, 3A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3BC, 3B8, 3B4, 3B0 -- the last 16 instructions are looping ump instructions X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0 X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0 X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0 X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0 ) ; -- the last 16 instructions are looping jump instructions -- of the type: loop: j loop -- This is to make sure that neither instruction fetching -- nor instruction execution proceeds beyond the end of this memory. -- Loc 3C0 -- 080000F0 => J 240 -- Loc 3C4 -- 080000F1 => J 241 -- Loc 3C8 -- 080000F2 => J 242 -- Loc 3CC -- 080000F3 => J 243 -- -- Loc 3D0 -- 080000F4 => J 244 -- Loc 3D4 -- 080000F5 => J 245 -- Loc 3D8 -- 080000F6 => J 246 -- Loc 3DC -- 080000F7 => J 247 -- -- Loc 3E0 -- 080000F8 => J 248 -- Loc 3E4 -- 080000F9 => J 249 -- Loc 3E8 -- 080000FA => J 250 -- Loc 3EC -- 080000FB => J 251 -- -- Loc 3F0 -- 080000FC => J 252 -- Loc 3F4 -- 080000FD => J 253 -- Loc 3F8 -- 080000FE => J 254 -- Loc 3FC -- 080000FF => J 255 end package instr_stream_pkg; -- -- No need for s package body here -- package body instr_stream_pkg is -- -- end package body instr_stream_pkg;
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd) -- Written by Gandhi Puvvada -- date of last rivision: 7/23/2008 -- -- A package file to define the instruction stream to be placed in the instr_cache. -- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module. -- We will use several files similar to this containining different instruction streams. -- The package name will remain the same, namely instr_stream_pkg. -- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd -- to say mult_test_stream_instr_stream_pkg.vhd. -- Depending on which instr_stream_pkg file was analysed/compiled most recently, -- that stream will be used for simulation/synthesis. ---------------------------------------------------------- library std, ieee; use ieee.std_logic_1164.all; package instr_stream_pkg is constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache -- type declarations type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0); --------------------------------------------------- --------------------------------------------------- -- All instructions are div $2 $3 $2 --------------------------------------------------- --------------------------------------------------- signal mem : mem_type := (X"0062101B_0062101B_0062101B_0062101B", -- Loc 0C, 08, 04, 00 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1C, 18, 14, 10 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2C, 28, 24, 20 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3C, 38, 34, 30 X"0062101B_0062101B_0062101B_0062101B", -- Loc 4C, 48, 44, 40 X"0062101B_0062101B_0062101B_0062101B", -- Loc 5C, 58, 54, 50 X"0062101B_0062101B_0062101B_0062101B", -- Loc 6C, 68, 64, 60 X"0062101B_0062101B_0062101B_0062101B", -- Loc 7C, 78, 74, 70 X"0062101B_0062101B_0062101B_0062101B", -- Loc 8C, 88, 84, 80 X"0062101B_0062101B_0062101B_0062101B", -- Loc 9C, 98, 94, 90 X"0062101B_0062101B_0062101B_0062101B", -- Loc AC, A8, A4, A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc BC, B8, B4, B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc CC, C8, C4, C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc DC, D8, D4, D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc EC, E8, E4, E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc FC, F8, F4, F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 10C, 108, 104, 100 X"0062101B_0062101B_0062101B_0062101B", -- Loc 11C, 118, 114, 110 X"0062101B_0062101B_0062101B_0062101B", -- Loc 12C, 128, 124, 120 X"0062101B_0062101B_0062101B_0062101B", -- Loc 13C, 138, 134, 130 X"0062101B_0062101B_0062101B_0062101B", -- Loc 14C, 148, 144, 140 X"0062101B_0062101B_0062101B_0062101B", -- Loc 15C, 158, 154, 150 X"0062101B_0062101B_0062101B_0062101B", -- Loc 16C, 168, 164, 160 X"0062101B_0062101B_0062101B_0062101B", -- Loc 17C, 178, 174, 170 X"0062101B_0062101B_0062101B_0062101B", -- Loc 18C, 188, 184, 180 X"0062101B_0062101B_0062101B_0062101B", -- Loc 19C, 198, 194, 190 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1AC, 1A8, 1A4, 1A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1BC, 1B8, 1B4, 1B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1CC, 1C8, 1C4, 1C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1DC, 1D8, 1D4, 1D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1EC, 1E8, 1E4, 1E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 1FC, 1F8, 1F4, 1F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 20C, 208, 204, 200 X"0062101B_0062101B_0062101B_0062101B", -- Loc 21C, 218, 214, 221 X"0062101B_0062101B_0062101B_0062101B", -- Loc 22C, 228, 224, 220 X"0062101B_0062101B_0062101B_0062101B", -- Loc 23C, 238, 234, 230 X"0062101B_0062101B_0062101B_0062101B", -- Loc 24C, 248, 244, 240 X"0062101B_0062101B_0062101B_0062101B", -- Loc 25C, 258, 254, 250 X"0062101B_0062101B_0062101B_0062101B", -- Loc 26C, 268, 264, 260 X"0062101B_0062101B_0062101B_0062101B", -- Loc 27C, 278, 274, 270 X"0062101B_0062101B_0062101B_0062101B", -- Loc 28C, 288, 284, 280 X"0062101B_0062101B_0062101B_0062101B", -- Loc 29C, 298, 294, 290 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2AC, 2A8, 2A4, 2A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2BC, 2B8, 2B4, 2B0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2CC, 2C8, 2C4, 2C0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2DC, 2D8, 2D4, 2D0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2EC, 2E8, 2E4, 2E0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 2FC, 2F8, 2F4, 2F0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 30C, 308, 304, 300 X"0062101B_0062101B_0062101B_0062101B", -- Loc 31C, 318, 314, 331 X"0062101B_0062101B_0062101B_0062101B", -- Loc 32C, 328, 324, 320 X"0062101B_0062101B_0062101B_0062101B", -- Loc 33C, 338, 334, 330 X"0062101B_0062101B_0062101B_0062101B", -- Loc 34C, 348, 344, 340 X"0062101B_0062101B_0062101B_0062101B", -- Loc 35C, 358, 354, 350 X"0062101B_0062101B_0062101B_0062101B", -- Loc 36C, 368, 364, 360 X"0062101B_0062101B_0062101B_0062101B", -- Loc 37C, 378, 374, 370 X"0062101B_0062101B_0062101B_0062101B", -- Loc 38C, 388, 384, 380 X"0062101B_0062101B_0062101B_0062101B", -- Loc 39C, 398, 394, 390 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3AC, 3A8, 3A4, 3A0 X"0062101B_0062101B_0062101B_0062101B", -- Loc 3BC, 3B8, 3B4, 3B0 -- the last 16 instructions are looping ump instructions X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0 X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0 X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0 X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0 ) ; -- the last 16 instructions are looping jump instructions -- of the type: loop: j loop -- This is to make sure that neither instruction fetching -- nor instruction execution proceeds beyond the end of this memory. -- Loc 3C0 -- 080000F0 => J 240 -- Loc 3C4 -- 080000F1 => J 241 -- Loc 3C8 -- 080000F2 => J 242 -- Loc 3CC -- 080000F3 => J 243 -- -- Loc 3D0 -- 080000F4 => J 244 -- Loc 3D4 -- 080000F5 => J 245 -- Loc 3D8 -- 080000F6 => J 246 -- Loc 3DC -- 080000F7 => J 247 -- -- Loc 3E0 -- 080000F8 => J 248 -- Loc 3E4 -- 080000F9 => J 249 -- Loc 3E8 -- 080000FA => J 250 -- Loc 3EC -- 080000FB => J 251 -- -- Loc 3F0 -- 080000FC => J 252 -- Loc 3F4 -- 080000FD => J 253 -- Loc 3F8 -- 080000FE => J 254 -- Loc 3FC -- 080000FF => J 255 end package instr_stream_pkg; -- -- No need for s package body here -- package body instr_stream_pkg is -- -- end package body instr_stream_pkg;
------------------------------------------------------------------------------- -- Title : Testbench for design "beacon_robot" ------------------------------------------------------------------------------- -- Author : strongly-typed ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.spislave_pkg.all; use work.bus_pkg.all; use work.motor_control_pkg.all; use work.adc_ltc2351_pkg.all; use work.uss_tx_pkg.all; ------------------------------------------------------------------------------- entity toplevel_tb is end toplevel_tb; ------------------------------------------------------------------------------- architecture tb of toplevel_tb is component toplevel port ( cs_np : in std_logic; sck_p : in std_logic; miso_p : out std_logic; mosi_p : in std_logic; sram_addr_p : out std_logic_vector(18 downto 0); sram_data_p : inout std_logic_vector(7 downto 0); sram_oe_np : out std_logic; sram_we_np : out std_logic; sram_ce_np : out std_logic; us_tx0_p : out half_bridge_type; us_tx1_p : out half_bridge_type; us_tx2_p : out half_bridge_type; us_rx_spi_in_p : in adc_ltc2351_spi_in_type; us_rx_spi_out_p : out adc_ltc2351_spi_out_type; ir_tx_p : out std_logic; ir_rx_spi_out_p : out adc_ltc2351_spi_out_type; ir_rx0_spi_in_p : in adc_ltc2351_spi_in_type; ir_rx1_spi_in_p : in adc_ltc2351_spi_in_type; ir_ack_p : in std_logic; ir_irq_p : out std_logic; us_ack_p : in std_logic; us_irq_p : out std_logic; clk : in std_logic); end component; -- signals for component ports signal us_tx0 : half_bridge_type; signal us_tx1 : half_bridge_type; signal us_tx2 : half_bridge_type; signal ir_tx : std_logic; signal cs_n : std_logic := '1'; signal sck : std_logic; signal miso : std_logic; signal mosi : std_logic; signal irq : std_logic; signal sram_addr : std_logic_vector(18 downto 0) := (others => '0'); signal sram_data : std_logic_vector(7 downto 0) := (others => '0'); signal sram_oe_n : std_logic := '1'; signal sram_we_n : std_logic := '1'; signal sram_ce_n : std_logic := '1'; signal us_rx_spi_in : adc_ltc2351_spi_in_type; signal us_rx_spi_out : adc_ltc2351_spi_out_type; signal ir_rx0_spi_in : adc_ltc2351_spi_in_type; signal ir_rx1_spi_in : adc_ltc2351_spi_in_type; signal ir_rx_spi_out : adc_ltc2351_spi_out_type; signal reset_n : std_logic := '1'; signal clk : std_logic := '0'; begin -- tb toplevel_1 : toplevel port map ( cs_np => cs_n, sck_p => sck, miso_p => miso, mosi_p => mosi, sram_addr_p => sram_addr, sram_data_p => sram_data, sram_oe_np => sram_oe_n, sram_we_np => sram_we_n, sram_ce_np => sram_ce_n, us_tx0_p => us_tx0, us_tx1_p => us_tx1, us_tx2_p => us_tx2, us_rx_spi_in_p => us_rx_spi_in, us_rx_spi_out_p => us_rx_spi_out, ir_tx_p => ir_tx, ir_rx_spi_out_p => ir_rx_spi_out, ir_rx0_spi_in_p => ir_rx0_spi_in, ir_rx1_spi_in_p => ir_rx1_spi_in, ir_ack_p => '0', ir_irq_p => open, us_ack_p => '0', us_irq_p => open, clk => clk); -- clock generation Clk <= not Clk after 5.0 ns; process begin wait for 25 ns; reset_n <= '0'; end process; end tb;
library IEEE; use IEEE.std_logic_1164.all; package pkg1_lib3 is component com1_pkg1_lib3 is generic ( WITH_GENERIC: boolean:=TRUE ); port ( data_i : in std_logic; data_o : out std_logic ); end component com1_pkg1_lib3; end package pkg1_lib3;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Synthesis Packages -- : (NUMERIC_STD package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC Synthesis Working Group, -- : Accellera VHDL-TC, and IEEE P1076 Working Group -- : -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number -- : in vector form -- : -- > UNRESOLVED_SIGNED: represents a SIGNED number -- : in vector form -- : The base element type is type STD_ULOGIC. -- : Aliases U_UNSIGNED and U_SIGNED are defined for the types -- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively. -- : Two numeric subtypes are defined: -- : -- > UNSIGNED: represents UNSIGNED number in vector form -- : -- > SIGNED: represents a SIGNED number in vector form -- : The element subtypes are the same subtype as STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions, clock detection -- : functions, and other utility functions. -- : -- : If any argument to a function is a null array, a null array -- : is returned (exceptions, if any, are noted individually). -- -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body NUMERIC_STD is -- null range array constants constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0'); constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0'); -- implementation controls constant NO_WARNING : BOOLEAN := false; -- default to emit warnings -- =========================Local Subprograms ================================= function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin if ARG >= 0 then N := ARG; else N := -(ARG+1); end if; NBITS := 1; while N > 0 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function SIGNED_NUM_BITS; function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin N := ARG; NBITS := 1; while N > 1 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function UNSIGNED_NUM_BITS; ------------------------------------------------------------------------ -- this internal function computes the addition of two UNRESOLVED_UNSIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_UNSIGNED; -- this internal function computes the addition of two UNRESOLVED_SIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_SIGNED; ----------------------------------------------------------------------------- -- this internal procedure computes UNSIGNED division -- giving the quotient and remainder. procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED; XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0); variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0); alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM; variable TOPBIT : INTEGER; begin TEMP := "0"&NUM; QUOT := (others => '0'); TOPBIT := -1; for J in DENOM'range loop if DENOM(J) = '1' then TOPBIT := J; exit; end if; end loop; assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero" severity error; for J in NUM'length-(TOPBIT+1) downto 0 loop if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J)) -("0"&DENOM(TOPBIT downto 0)); QUOT(J) := '1'; end if; assert TEMP(TOPBIT+J+1) = '0' report "NUMERIC_STD.DIVMOD: internal error in the division algorithm" severity error; end loop; XQUOT := RESIZE(QUOT, XQUOT'length); XREMAIN := RESIZE(TEMP, XREMAIN'length); end procedure DIVMOD; -----------------Local Subprograms - shift/rotate ops------------------------- function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); end if; return RESULT; end function XSLL; function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); end if; return RESULT; end function XSRL; function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0); variable XCOUNT : NATURAL := COUNT; begin if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG; else if (XCOUNT > ARG_L) then XCOUNT := ARG_L; end if; RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); end if; return RESULT; end function XSRA; function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); end if; return RESULT; end function XROL; function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); end if; return RESULT; end function XROR; -----------------Local Subprograms - Relational ops--------------------------- -- -- General "=" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function UNSIGNED_EQUAL; -- -- General "=" for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function SIGNED_EQUAL; -- -- General "<" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS; -- -- General "<" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS; -- -- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS_OR_EQUAL; -- -- General "<=" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is -- Need aliases to assure index direction variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS_OR_EQUAL; -- =========================Exported Functions ========================== -- Id: A.1 function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0); begin if ARG'length < 1 then return NAS; end if; RESULT := TO_01(XARG, 'X'); if (RESULT(RESULT'left) = 'X') then return RESULT; end if; if RESULT(RESULT'left) = '1' then RESULT := -RESULT; end if; return RESULT; end function "abs"; -- Id: A.2 function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0); variable CBIT : STD_LOGIC := '1'; begin if ARG'length < 1 then return NAS; end if; XARG01 := TO_01(ARG, 'X'); if (XARG01(XARG01'left) = 'X') then return XARG01; end if; for I in 0 to RESULT'left loop RESULT(I) := not(XARG01(I)) xor CBIT; CBIT := CBIT and not(XARG01(I)); end loop; return RESULT; end function "-"; -- ============================================================================ -- Id: A.3 function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, R01, '0'); end function "+"; -- Id: A.3R function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.3L function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.4 function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, R01, '0'); end function "+"; -- Id: A.4R function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.4L function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.5 function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L + TO_UNSIGNED(R, L'length); end function "+"; -- Id: A.6 function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) + R; end function "+"; -- Id: A.7 function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L + TO_SIGNED(R, L'length); end function "+"; -- Id: A.8 function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) + R; end function "+"; -- ============================================================================ -- Id: A.9 function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.9R function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.9L function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.10 function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.10R function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.10L function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.11 function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L - TO_UNSIGNED(R, L'length); end function "-"; -- Id: A.12 function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) - R; end function "-"; -- Id: A.13 function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L - TO_SIGNED(R, L'length); end function "-"; -- Id: A.14 function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) - R; end function "-"; -- ============================================================================ -- Id: A.15 function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; return RESULT; end function "*"; -- Id: A.16 function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0); begin if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS; end if; XL := TO_01(L, 'X'); XR := TO_01(R, 'X'); if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT-1 loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; if XL(L_LEFT) = '1' then RESULT := RESULT - ADVAL; end if; return RESULT; end function "*"; -- Id: A.17 function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L * TO_UNSIGNED(R, L'length); end function "*"; -- Id: A.18 function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) * R; end function "*"; -- Id: A.19 function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L * TO_SIGNED(R, L'length); end function "*"; -- Id: A.20 function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) * R; end function "*"; -- ============================================================================ -- Id: A.21 function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return FQUOT; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FQUOT; end function "/"; -- Id: A.22 function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable QNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return UNRESOLVED_SIGNED(FQUOT); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); QNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); QNEG := not QNEG; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if QNEG then FQUOT := "0"-FQUOT; end if; return UNRESOLVED_SIGNED(FQUOT); end function "/"; -- Id: A.23 function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_UNSIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.24 function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- Id: A.25 function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_SIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.26 function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => QUOT(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- ============================================================================ -- Id: A.27 function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "rem"; -- Id: A.28 function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X')); XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X')); if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XNUM(XNUM'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM)); RNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XNUM); end if; if XDENOM(XDENOM'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM)); else XDENOM := UNRESOLVED_UNSIGNED(XDENOM); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG then FREMAIN := "0"-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "rem"; -- Id: A.29 function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := L rem XR; if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.30 function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin XL := TO_UNSIGNED(L, L_LENGTH); XREM := XL rem R; if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- Id: A.31 function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L rem XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.32 function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL rem R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- ============================================================================ -- Id: A.33 function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "mod"; -- Id: A.34 function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); RNEG := true; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG and L(L'left) = '1' then FREMAIN := "0"-FREMAIN; elsif RNEG and FREMAIN /= "0" then FREMAIN := FREMAIN-XDENOM; elsif L(L'left) = '1' and FREMAIN /= "0" then FREMAIN := XDENOM-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "mod"; -- Id: A.35 function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.36 function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- Id: A.37 function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.38 function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- ============================================================================ -- Id: A.39 function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.40 function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.41 function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- Id: A.42 function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- ============================================================================ -- Id: C.1 function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.2 function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.3 function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function ">"; -- Id: C.4 function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function ">"; -- Id: C.5 function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function ">"; -- Id: C.6 function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function ">"; -- ============================================================================ -- Id: C.7 function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.8 function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.9 function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function "<"; -- Id: C.10 function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function "<"; -- Id: C.11 function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function "<"; -- Id: C.12 function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function "<"; -- ============================================================================ -- Id: C.13 function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.14 function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.15 function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "<="; -- Id: C.16 function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function "<="; -- Id: C.17 function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "<="; -- Id: C.18 function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "<="; -- ============================================================================ -- Id: C.19 function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.20 function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.21 function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function ">="; -- Id: C.22 function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function ">="; -- Id: C.23 function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function ">="; -- Id: C.24 function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function ">="; -- ============================================================================ -- Id: C.25 function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.26 function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.27 function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return false; end if; return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "="; -- Id: C.28 function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return false; end if; return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01); end function "="; -- Id: C.29 function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "="; -- Id: C.30 function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return false; end if; return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "="; -- ============================================================================ -- Id: C.31 function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.32 function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.33 function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01)); end function "/="; -- Id: C.34 function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(L) > R'length then return true; end if; return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01)); end function "/="; -- Id: C.35 function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(R) > L'length then return true; end if; return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length))); end function "/="; -- Id: C.36 function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(R) > L'length then return true; end if; return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length))); end function "/="; -- ============================================================================ -- Id: C.37 function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.38 function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.39 function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MINIMUM(TO_UNSIGNED(L, R'length), R); end function MINIMUM; -- Id: C.40 function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MINIMUM(TO_SIGNED(L, R'length), R); end function MINIMUM; -- Id: C.41 function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MINIMUM(L, TO_UNSIGNED(R, L'length)); end function MINIMUM; -- Id: C.42 function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MINIMUM(L, TO_SIGNED(R, L'length)); end function MINIMUM; -- ============================================================================ -- Id: C.43 function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.44 function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.45 function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(TO_UNSIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.46 function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MAXIMUM(TO_SIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.47 function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(L, TO_UNSIGNED(R, L'length)); end function MAXIMUM; -- Id: C.48 function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MAXIMUM(L, TO_SIGNED(R, L'length)); end function MAXIMUM; -- ============================================================================ -- Id: C.49 function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.50 function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.51 function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.52 function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.53 function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?> TO_UNSIGNED(R, L'length); end function "?>"; -- Id: C.54 function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?> TO_SIGNED(R, L'length); end function "?>"; -- ============================================================================ -- Id: C.55 function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.56 function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.57 function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.58 function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.59 function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?< TO_UNSIGNED(R, L'length); end function "?<"; -- Id: C.60 function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?< TO_SIGNED(R, L'length); end function "?<"; -- ============================================================================ -- Id: C.61 function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.62 function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.63 function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.64 function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.65 function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?<= TO_UNSIGNED(R, L'length); end function "?<="; -- Id: C.66 function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?<= TO_SIGNED(R, L'length); end function "?<="; -- ============================================================================ -- Id: C.67 function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.68 function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.69 function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.70 function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.71 function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?>= TO_UNSIGNED(R, L'length); end function "?>="; -- Id: C.72 function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?>= TO_SIGNED(R, L'length); end function "?>="; -- ============================================================================ -- Id: C.73 function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- Logically identical to an "=" operator. if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.74 function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.75 function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?= R; end function "?="; -- Id: C.76 function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?= R; end function "?="; -- Id: C.77 function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?= TO_UNSIGNED(R, L'length); end function "?="; -- Id: C.78 function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?= TO_SIGNED(R, L'length); end function "?="; -- ============================================================================ -- Id: C.79 function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.80 function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.81 function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.82 function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.83 function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?/= TO_UNSIGNED(R, L'length); end function "?/="; -- Id: C.84 function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?/= TO_SIGNED(R, L'length); end function "?/="; -- ============================================================================ -- Id: S.1 function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.2 function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- Id: S.3 function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.4 function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- ============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.6 function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- Id: S.7 function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.8 function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- ============================================================================ ------------------------------------------------------------------------------ -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.9 function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.10 function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT)); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.12 function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT)); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.13 function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.14 function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.17 function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.18 function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.19 function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; ------------------------------------------------------------------------------ -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.20 function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; -- ============================================================================ -- Id: D.1 function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is constant ARG_LEFT : INTEGER := ARG'length-1; alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0); variable RESULT : NATURAL := 0; begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(XXARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; for I in XARG'range loop RESULT := RESULT+RESULT; if XARG(I) = '1' then RESULT := RESULT + 1; end if; end loop; return RESULT; end function TO_INTEGER; -- Id: D.2 function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0); begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(ARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; if XARG(XARG'left) = '0' then return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG)); else return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1); end if; end function TO_INTEGER; -- Id: D.3 function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable I_VAL : NATURAL := ARG; begin if (SIZE < 1) then return NAU; end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := '0'; else RESULT(I) := '1'; end if; I_VAL := I_VAL/2; end loop; if not(I_VAL = 0) then assert NO_WARNING report "NUMERIC_STD.TO_UNSIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_UNSIGNED; -- Id: D.4 function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable B_VAL : STD_LOGIC := '0'; variable I_VAL : INTEGER := ARG; begin if (SIZE < 1) then return NAS; end if; if (ARG < 0) then B_VAL := '1'; I_VAL := -(ARG+1); end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := B_VAL; else RESULT(I) := not B_VAL; end if; I_VAL := I_VAL/2; end loop; if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then assert NO_WARNING report "NUMERIC_STD.TO_SIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_SIGNED; function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_UNSIGNED; function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_SIGNED; -- ============================================================================ -- Id: R.1 function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED is alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) := (others => '0'); constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2; begin if (NEW_SIZE < 1) then return NAS; end if; if (ARG'length = 0) then return RESULT; end if; RESULT := (others => ARG(ARG'left)); if BOUND >= 0 then RESULT(BOUND downto 0) := INVEC(BOUND downto 0); end if; return RESULT; end function RESIZE; -- Id: R.2 function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0'); begin if (NEW_SIZE < 1) then return NAU; end if; if XARG'length = 0 then return RESULT; end if; if (RESULT'length < ARG'length) then RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0); else RESULT(RESULT'left downto XARG'left+1) := (others => '0'); RESULT(XARG'left downto 0) := XARG; end if; return RESULT; end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; -- ============================================================================ -- Id: L.1 function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.2 function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.3 function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.4 function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.5 function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.6 function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.7 function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.8 function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.9 function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.10 function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.11 function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.12 function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.13 function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.14 function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.15 function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.16 function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.17 function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.18 function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.19 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.20 function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.21 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.22 function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.23 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.24 function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.25 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.26 function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; -- Id: L.27 function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.28 function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.29 function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.30 function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.31 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.32 function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.33 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.34 function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.35 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.36 function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.37 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.38 function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.39 function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.40 function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.41 function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.42 function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.43 function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.44 function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.45 function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.46 function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.47 function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.48 function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.49 function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.50 function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; -- ============================================================================ -- support constants for STD_MATCH: type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN; constant MATCH_TABLE : BOOLEAN_TABLE := ( -------------------------------------------------------------------------- -- U X 0 1 Z W L H - -------------------------------------------------------------------------- (false, false, false, false, false, false, false, false, true), -- | U | (false, false, false, false, false, false, false, false, true), -- | X | (false, false, true, false, false, false, true, false, true), -- | 0 | (false, false, false, true, false, false, false, true, true), -- | 1 | (false, false, false, false, false, false, false, false, true), -- | Z | (false, false, false, false, false, false, false, false, true), -- | W | (false, false, true, false, false, false, true, false, true), -- | L | (false, false, false, true, false, false, false, true, true), -- | H | (true, true, true, true, true, true, true, true, true) -- | - | ); -- Id: M.1 function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is variable VALUE : STD_ULOGIC; begin return MATCH_TABLE(L, R); end function STD_MATCH; -- Id: M.2 function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L; alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.3 function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is alias LV : UNRESOLVED_SIGNED(1 to L'length) is L; alias RV : UNRESOLVED_SIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.5 function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L; alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- ============================================================================ -- function TO_01 is used to convert vectors to the -- correct form for exported functions, -- and to report if there is an element which -- is not in (0, 1, H, L). -- Id: T.1 function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAU" severity warning; return NAU; end if; return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.2 function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAS" severity warning; return NAS; end if; return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.3 function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.4 function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.5 function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.6 function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.7 function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.8 function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.9 function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- Id: T.10 function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- ============================================================================ -- string conversion and write operations -- ============================================================================ function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_ostring(STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_ostring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+2)/3; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_ostring(pad & STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_hstring(STD_ULOGIC_VECTOR (value)); end function to_hstring; function to_hstring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_hstring(pad & STD_ULOGIC_VECTOR (value)); end function to_hstring; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := SIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := SIGNED (ivalue); end procedure READ; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); -- Bail out if there was a bad read if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.OREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.HREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is constant ne : INTEGER := (VALUE'length+2)/3; constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1) := (others => VALUE (VALUE'left)); variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); constant ne : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1) := (others => VALUE(VALUE'left)); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; end package body NUMERIC_STD;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Synthesis Packages -- : (NUMERIC_STD package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC Synthesis Working Group, -- : Accellera VHDL-TC, and IEEE P1076 Working Group -- : -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number -- : in vector form -- : -- > UNRESOLVED_SIGNED: represents a SIGNED number -- : in vector form -- : The base element type is type STD_ULOGIC. -- : Aliases U_UNSIGNED and U_SIGNED are defined for the types -- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively. -- : Two numeric subtypes are defined: -- : -- > UNSIGNED: represents UNSIGNED number in vector form -- : -- > SIGNED: represents a SIGNED number in vector form -- : The element subtypes are the same subtype as STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions, clock detection -- : functions, and other utility functions. -- : -- : If any argument to a function is a null array, a null array -- : is returned (exceptions, if any, are noted individually). -- -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body NUMERIC_STD is -- null range array constants constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0'); constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0'); -- implementation controls constant NO_WARNING : BOOLEAN := false; -- default to emit warnings -- =========================Local Subprograms ================================= function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin if ARG >= 0 then N := ARG; else N := -(ARG+1); end if; NBITS := 1; while N > 0 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function SIGNED_NUM_BITS; function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin N := ARG; NBITS := 1; while N > 1 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function UNSIGNED_NUM_BITS; ------------------------------------------------------------------------ -- this internal function computes the addition of two UNRESOLVED_UNSIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_UNSIGNED; -- this internal function computes the addition of two UNRESOLVED_SIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_SIGNED; ----------------------------------------------------------------------------- -- this internal procedure computes UNSIGNED division -- giving the quotient and remainder. procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED; XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0); variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0); alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM; variable TOPBIT : INTEGER; begin TEMP := "0"&NUM; QUOT := (others => '0'); TOPBIT := -1; for J in DENOM'range loop if DENOM(J) = '1' then TOPBIT := J; exit; end if; end loop; assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero" severity error; for J in NUM'length-(TOPBIT+1) downto 0 loop if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J)) -("0"&DENOM(TOPBIT downto 0)); QUOT(J) := '1'; end if; assert TEMP(TOPBIT+J+1) = '0' report "NUMERIC_STD.DIVMOD: internal error in the division algorithm" severity error; end loop; XQUOT := RESIZE(QUOT, XQUOT'length); XREMAIN := RESIZE(TEMP, XREMAIN'length); end procedure DIVMOD; -----------------Local Subprograms - shift/rotate ops------------------------- function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); end if; return RESULT; end function XSLL; function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); end if; return RESULT; end function XSRL; function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0); variable XCOUNT : NATURAL := COUNT; begin if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG; else if (XCOUNT > ARG_L) then XCOUNT := ARG_L; end if; RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); end if; return RESULT; end function XSRA; function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); end if; return RESULT; end function XROL; function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); end if; return RESULT; end function XROR; -----------------Local Subprograms - Relational ops--------------------------- -- -- General "=" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function UNSIGNED_EQUAL; -- -- General "=" for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function SIGNED_EQUAL; -- -- General "<" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS; -- -- General "<" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS; -- -- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS_OR_EQUAL; -- -- General "<=" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is -- Need aliases to assure index direction variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS_OR_EQUAL; -- =========================Exported Functions ========================== -- Id: A.1 function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0); begin if ARG'length < 1 then return NAS; end if; RESULT := TO_01(XARG, 'X'); if (RESULT(RESULT'left) = 'X') then return RESULT; end if; if RESULT(RESULT'left) = '1' then RESULT := -RESULT; end if; return RESULT; end function "abs"; -- Id: A.2 function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0); variable CBIT : STD_LOGIC := '1'; begin if ARG'length < 1 then return NAS; end if; XARG01 := TO_01(ARG, 'X'); if (XARG01(XARG01'left) = 'X') then return XARG01; end if; for I in 0 to RESULT'left loop RESULT(I) := not(XARG01(I)) xor CBIT; CBIT := CBIT and not(XARG01(I)); end loop; return RESULT; end function "-"; -- ============================================================================ -- Id: A.3 function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, R01, '0'); end function "+"; -- Id: A.3R function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.3L function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.4 function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, R01, '0'); end function "+"; -- Id: A.4R function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.4L function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.5 function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L + TO_UNSIGNED(R, L'length); end function "+"; -- Id: A.6 function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) + R; end function "+"; -- Id: A.7 function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L + TO_SIGNED(R, L'length); end function "+"; -- Id: A.8 function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) + R; end function "+"; -- ============================================================================ -- Id: A.9 function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.9R function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.9L function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.10 function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.10R function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.10L function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.11 function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L - TO_UNSIGNED(R, L'length); end function "-"; -- Id: A.12 function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) - R; end function "-"; -- Id: A.13 function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L - TO_SIGNED(R, L'length); end function "-"; -- Id: A.14 function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) - R; end function "-"; -- ============================================================================ -- Id: A.15 function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; return RESULT; end function "*"; -- Id: A.16 function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0); begin if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS; end if; XL := TO_01(L, 'X'); XR := TO_01(R, 'X'); if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT-1 loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; if XL(L_LEFT) = '1' then RESULT := RESULT - ADVAL; end if; return RESULT; end function "*"; -- Id: A.17 function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L * TO_UNSIGNED(R, L'length); end function "*"; -- Id: A.18 function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) * R; end function "*"; -- Id: A.19 function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L * TO_SIGNED(R, L'length); end function "*"; -- Id: A.20 function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) * R; end function "*"; -- ============================================================================ -- Id: A.21 function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return FQUOT; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FQUOT; end function "/"; -- Id: A.22 function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable QNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return UNRESOLVED_SIGNED(FQUOT); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); QNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); QNEG := not QNEG; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if QNEG then FQUOT := "0"-FQUOT; end if; return UNRESOLVED_SIGNED(FQUOT); end function "/"; -- Id: A.23 function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_UNSIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.24 function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- Id: A.25 function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_SIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.26 function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => QUOT(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- ============================================================================ -- Id: A.27 function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "rem"; -- Id: A.28 function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X')); XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X')); if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XNUM(XNUM'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM)); RNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XNUM); end if; if XDENOM(XDENOM'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM)); else XDENOM := UNRESOLVED_UNSIGNED(XDENOM); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG then FREMAIN := "0"-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "rem"; -- Id: A.29 function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := L rem XR; if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.30 function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin XL := TO_UNSIGNED(L, L_LENGTH); XREM := XL rem R; if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- Id: A.31 function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L rem XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.32 function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL rem R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- ============================================================================ -- Id: A.33 function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "mod"; -- Id: A.34 function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); RNEG := true; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG and L(L'left) = '1' then FREMAIN := "0"-FREMAIN; elsif RNEG and FREMAIN /= "0" then FREMAIN := FREMAIN-XDENOM; elsif L(L'left) = '1' and FREMAIN /= "0" then FREMAIN := XDENOM-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "mod"; -- Id: A.35 function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.36 function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- Id: A.37 function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.38 function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- ============================================================================ -- Id: A.39 function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.40 function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.41 function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- Id: A.42 function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- ============================================================================ -- Id: C.1 function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.2 function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.3 function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function ">"; -- Id: C.4 function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function ">"; -- Id: C.5 function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function ">"; -- Id: C.6 function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function ">"; -- ============================================================================ -- Id: C.7 function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.8 function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.9 function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function "<"; -- Id: C.10 function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function "<"; -- Id: C.11 function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function "<"; -- Id: C.12 function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function "<"; -- ============================================================================ -- Id: C.13 function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.14 function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.15 function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "<="; -- Id: C.16 function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function "<="; -- Id: C.17 function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "<="; -- Id: C.18 function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "<="; -- ============================================================================ -- Id: C.19 function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.20 function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.21 function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function ">="; -- Id: C.22 function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function ">="; -- Id: C.23 function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function ">="; -- Id: C.24 function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function ">="; -- ============================================================================ -- Id: C.25 function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.26 function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.27 function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return false; end if; return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "="; -- Id: C.28 function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return false; end if; return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01); end function "="; -- Id: C.29 function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "="; -- Id: C.30 function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return false; end if; return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "="; -- ============================================================================ -- Id: C.31 function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.32 function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.33 function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01)); end function "/="; -- Id: C.34 function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(L) > R'length then return true; end if; return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01)); end function "/="; -- Id: C.35 function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(R) > L'length then return true; end if; return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length))); end function "/="; -- Id: C.36 function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(R) > L'length then return true; end if; return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length))); end function "/="; -- ============================================================================ -- Id: C.37 function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.38 function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.39 function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MINIMUM(TO_UNSIGNED(L, R'length), R); end function MINIMUM; -- Id: C.40 function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MINIMUM(TO_SIGNED(L, R'length), R); end function MINIMUM; -- Id: C.41 function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MINIMUM(L, TO_UNSIGNED(R, L'length)); end function MINIMUM; -- Id: C.42 function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MINIMUM(L, TO_SIGNED(R, L'length)); end function MINIMUM; -- ============================================================================ -- Id: C.43 function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.44 function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.45 function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(TO_UNSIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.46 function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MAXIMUM(TO_SIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.47 function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(L, TO_UNSIGNED(R, L'length)); end function MAXIMUM; -- Id: C.48 function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MAXIMUM(L, TO_SIGNED(R, L'length)); end function MAXIMUM; -- ============================================================================ -- Id: C.49 function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.50 function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.51 function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.52 function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.53 function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?> TO_UNSIGNED(R, L'length); end function "?>"; -- Id: C.54 function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?> TO_SIGNED(R, L'length); end function "?>"; -- ============================================================================ -- Id: C.55 function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.56 function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.57 function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.58 function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.59 function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?< TO_UNSIGNED(R, L'length); end function "?<"; -- Id: C.60 function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?< TO_SIGNED(R, L'length); end function "?<"; -- ============================================================================ -- Id: C.61 function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.62 function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.63 function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.64 function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.65 function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?<= TO_UNSIGNED(R, L'length); end function "?<="; -- Id: C.66 function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?<= TO_SIGNED(R, L'length); end function "?<="; -- ============================================================================ -- Id: C.67 function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.68 function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.69 function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.70 function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.71 function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?>= TO_UNSIGNED(R, L'length); end function "?>="; -- Id: C.72 function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?>= TO_SIGNED(R, L'length); end function "?>="; -- ============================================================================ -- Id: C.73 function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- Logically identical to an "=" operator. if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.74 function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.75 function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?= R; end function "?="; -- Id: C.76 function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?= R; end function "?="; -- Id: C.77 function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?= TO_UNSIGNED(R, L'length); end function "?="; -- Id: C.78 function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?= TO_SIGNED(R, L'length); end function "?="; -- ============================================================================ -- Id: C.79 function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.80 function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.81 function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.82 function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.83 function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?/= TO_UNSIGNED(R, L'length); end function "?/="; -- Id: C.84 function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?/= TO_SIGNED(R, L'length); end function "?/="; -- ============================================================================ -- Id: S.1 function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.2 function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- Id: S.3 function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.4 function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- ============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.6 function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- Id: S.7 function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.8 function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- ============================================================================ ------------------------------------------------------------------------------ -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.9 function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.10 function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT)); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.12 function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT)); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.13 function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.14 function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.17 function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.18 function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.19 function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; ------------------------------------------------------------------------------ -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.20 function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; -- ============================================================================ -- Id: D.1 function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is constant ARG_LEFT : INTEGER := ARG'length-1; alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0); variable RESULT : NATURAL := 0; begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(XXARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; for I in XARG'range loop RESULT := RESULT+RESULT; if XARG(I) = '1' then RESULT := RESULT + 1; end if; end loop; return RESULT; end function TO_INTEGER; -- Id: D.2 function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0); begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(ARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; if XARG(XARG'left) = '0' then return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG)); else return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1); end if; end function TO_INTEGER; -- Id: D.3 function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable I_VAL : NATURAL := ARG; begin if (SIZE < 1) then return NAU; end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := '0'; else RESULT(I) := '1'; end if; I_VAL := I_VAL/2; end loop; if not(I_VAL = 0) then assert NO_WARNING report "NUMERIC_STD.TO_UNSIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_UNSIGNED; -- Id: D.4 function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable B_VAL : STD_LOGIC := '0'; variable I_VAL : INTEGER := ARG; begin if (SIZE < 1) then return NAS; end if; if (ARG < 0) then B_VAL := '1'; I_VAL := -(ARG+1); end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := B_VAL; else RESULT(I) := not B_VAL; end if; I_VAL := I_VAL/2; end loop; if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then assert NO_WARNING report "NUMERIC_STD.TO_SIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_SIGNED; function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_UNSIGNED; function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_SIGNED; -- ============================================================================ -- Id: R.1 function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED is alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) := (others => '0'); constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2; begin if (NEW_SIZE < 1) then return NAS; end if; if (ARG'length = 0) then return RESULT; end if; RESULT := (others => ARG(ARG'left)); if BOUND >= 0 then RESULT(BOUND downto 0) := INVEC(BOUND downto 0); end if; return RESULT; end function RESIZE; -- Id: R.2 function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0'); begin if (NEW_SIZE < 1) then return NAU; end if; if XARG'length = 0 then return RESULT; end if; if (RESULT'length < ARG'length) then RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0); else RESULT(RESULT'left downto XARG'left+1) := (others => '0'); RESULT(XARG'left downto 0) := XARG; end if; return RESULT; end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; -- ============================================================================ -- Id: L.1 function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.2 function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.3 function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.4 function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.5 function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.6 function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.7 function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.8 function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.9 function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.10 function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.11 function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.12 function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.13 function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.14 function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.15 function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.16 function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.17 function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.18 function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.19 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.20 function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.21 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.22 function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.23 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.24 function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.25 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.26 function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; -- Id: L.27 function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.28 function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.29 function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.30 function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.31 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.32 function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.33 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.34 function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.35 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.36 function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.37 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.38 function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.39 function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.40 function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.41 function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.42 function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.43 function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.44 function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.45 function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.46 function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.47 function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.48 function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.49 function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.50 function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; -- ============================================================================ -- support constants for STD_MATCH: type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN; constant MATCH_TABLE : BOOLEAN_TABLE := ( -------------------------------------------------------------------------- -- U X 0 1 Z W L H - -------------------------------------------------------------------------- (false, false, false, false, false, false, false, false, true), -- | U | (false, false, false, false, false, false, false, false, true), -- | X | (false, false, true, false, false, false, true, false, true), -- | 0 | (false, false, false, true, false, false, false, true, true), -- | 1 | (false, false, false, false, false, false, false, false, true), -- | Z | (false, false, false, false, false, false, false, false, true), -- | W | (false, false, true, false, false, false, true, false, true), -- | L | (false, false, false, true, false, false, false, true, true), -- | H | (true, true, true, true, true, true, true, true, true) -- | - | ); -- Id: M.1 function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is variable VALUE : STD_ULOGIC; begin return MATCH_TABLE(L, R); end function STD_MATCH; -- Id: M.2 function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L; alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.3 function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is alias LV : UNRESOLVED_SIGNED(1 to L'length) is L; alias RV : UNRESOLVED_SIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.5 function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L; alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- ============================================================================ -- function TO_01 is used to convert vectors to the -- correct form for exported functions, -- and to report if there is an element which -- is not in (0, 1, H, L). -- Id: T.1 function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAU" severity warning; return NAU; end if; return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.2 function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAS" severity warning; return NAS; end if; return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.3 function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.4 function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.5 function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.6 function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.7 function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.8 function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.9 function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- Id: T.10 function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- ============================================================================ -- string conversion and write operations -- ============================================================================ function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_ostring(STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_ostring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+2)/3; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_ostring(pad & STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_hstring(STD_ULOGIC_VECTOR (value)); end function to_hstring; function to_hstring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_hstring(pad & STD_ULOGIC_VECTOR (value)); end function to_hstring; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := SIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := SIGNED (ivalue); end procedure READ; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); -- Bail out if there was a bad read if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.OREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.HREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is constant ne : INTEGER := (VALUE'length+2)/3; constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1) := (others => VALUE (VALUE'left)); variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); constant ne : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1) := (others => VALUE(VALUE'left)); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; end package body NUMERIC_STD;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Synthesis Packages -- : (NUMERIC_STD package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC Synthesis Working Group, -- : Accellera VHDL-TC, and IEEE P1076 Working Group -- : -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number -- : in vector form -- : -- > UNRESOLVED_SIGNED: represents a SIGNED number -- : in vector form -- : The base element type is type STD_ULOGIC. -- : Aliases U_UNSIGNED and U_SIGNED are defined for the types -- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively. -- : Two numeric subtypes are defined: -- : -- > UNSIGNED: represents UNSIGNED number in vector form -- : -- > SIGNED: represents a SIGNED number in vector form -- : The element subtypes are the same subtype as STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions, clock detection -- : functions, and other utility functions. -- : -- : If any argument to a function is a null array, a null array -- : is returned (exceptions, if any, are noted individually). -- -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body NUMERIC_STD is -- null range array constants constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0'); constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0'); -- implementation controls constant NO_WARNING : BOOLEAN := false; -- default to emit warnings -- =========================Local Subprograms ================================= function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin if ARG >= 0 then N := ARG; else N := -(ARG+1); end if; NBITS := 1; while N > 0 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function SIGNED_NUM_BITS; function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin N := ARG; NBITS := 1; while N > 1 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function UNSIGNED_NUM_BITS; ------------------------------------------------------------------------ -- this internal function computes the addition of two UNRESOLVED_UNSIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_UNSIGNED; -- this internal function computes the addition of two UNRESOLVED_SIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_SIGNED; ----------------------------------------------------------------------------- -- this internal procedure computes UNSIGNED division -- giving the quotient and remainder. procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED; XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0); variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0); alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM; variable TOPBIT : INTEGER; begin TEMP := "0"&NUM; QUOT := (others => '0'); TOPBIT := -1; for J in DENOM'range loop if DENOM(J) = '1' then TOPBIT := J; exit; end if; end loop; assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero" severity error; for J in NUM'length-(TOPBIT+1) downto 0 loop if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J)) -("0"&DENOM(TOPBIT downto 0)); QUOT(J) := '1'; end if; assert TEMP(TOPBIT+J+1) = '0' report "NUMERIC_STD.DIVMOD: internal error in the division algorithm" severity error; end loop; XQUOT := RESIZE(QUOT, XQUOT'length); XREMAIN := RESIZE(TEMP, XREMAIN'length); end procedure DIVMOD; -----------------Local Subprograms - shift/rotate ops------------------------- function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); end if; return RESULT; end function XSLL; function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); end if; return RESULT; end function XSRL; function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0); variable XCOUNT : NATURAL := COUNT; begin if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG; else if (XCOUNT > ARG_L) then XCOUNT := ARG_L; end if; RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); end if; return RESULT; end function XSRA; function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); end if; return RESULT; end function XROL; function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); end if; return RESULT; end function XROR; -----------------Local Subprograms - Relational ops--------------------------- -- -- General "=" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function UNSIGNED_EQUAL; -- -- General "=" for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function SIGNED_EQUAL; -- -- General "<" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS; -- -- General "<" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS; -- -- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS_OR_EQUAL; -- -- General "<=" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is -- Need aliases to assure index direction variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS_OR_EQUAL; -- =========================Exported Functions ========================== -- Id: A.1 function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0); begin if ARG'length < 1 then return NAS; end if; RESULT := TO_01(XARG, 'X'); if (RESULT(RESULT'left) = 'X') then return RESULT; end if; if RESULT(RESULT'left) = '1' then RESULT := -RESULT; end if; return RESULT; end function "abs"; -- Id: A.2 function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0); variable CBIT : STD_LOGIC := '1'; begin if ARG'length < 1 then return NAS; end if; XARG01 := TO_01(ARG, 'X'); if (XARG01(XARG01'left) = 'X') then return XARG01; end if; for I in 0 to RESULT'left loop RESULT(I) := not(XARG01(I)) xor CBIT; CBIT := CBIT and not(XARG01(I)); end loop; return RESULT; end function "-"; -- ============================================================================ -- Id: A.3 function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, R01, '0'); end function "+"; -- Id: A.3R function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.3L function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.4 function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, R01, '0'); end function "+"; -- Id: A.4R function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.4L function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.5 function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L + TO_UNSIGNED(R, L'length); end function "+"; -- Id: A.6 function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) + R; end function "+"; -- Id: A.7 function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L + TO_SIGNED(R, L'length); end function "+"; -- Id: A.8 function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) + R; end function "+"; -- ============================================================================ -- Id: A.9 function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.9R function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.9L function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.10 function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.10R function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.10L function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.11 function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L - TO_UNSIGNED(R, L'length); end function "-"; -- Id: A.12 function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) - R; end function "-"; -- Id: A.13 function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L - TO_SIGNED(R, L'length); end function "-"; -- Id: A.14 function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) - R; end function "-"; -- ============================================================================ -- Id: A.15 function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; return RESULT; end function "*"; -- Id: A.16 function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0); begin if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS; end if; XL := TO_01(L, 'X'); XR := TO_01(R, 'X'); if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT-1 loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; if XL(L_LEFT) = '1' then RESULT := RESULT - ADVAL; end if; return RESULT; end function "*"; -- Id: A.17 function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L * TO_UNSIGNED(R, L'length); end function "*"; -- Id: A.18 function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) * R; end function "*"; -- Id: A.19 function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L * TO_SIGNED(R, L'length); end function "*"; -- Id: A.20 function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) * R; end function "*"; -- ============================================================================ -- Id: A.21 function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return FQUOT; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FQUOT; end function "/"; -- Id: A.22 function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable QNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return UNRESOLVED_SIGNED(FQUOT); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); QNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); QNEG := not QNEG; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if QNEG then FQUOT := "0"-FQUOT; end if; return UNRESOLVED_SIGNED(FQUOT); end function "/"; -- Id: A.23 function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_UNSIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.24 function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- Id: A.25 function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_SIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.26 function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => QUOT(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- ============================================================================ -- Id: A.27 function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "rem"; -- Id: A.28 function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X')); XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X')); if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XNUM(XNUM'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM)); RNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XNUM); end if; if XDENOM(XDENOM'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM)); else XDENOM := UNRESOLVED_UNSIGNED(XDENOM); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG then FREMAIN := "0"-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "rem"; -- Id: A.29 function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := L rem XR; if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.30 function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin XL := TO_UNSIGNED(L, L_LENGTH); XREM := XL rem R; if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- Id: A.31 function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L rem XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.32 function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL rem R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- ============================================================================ -- Id: A.33 function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "mod"; -- Id: A.34 function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); RNEG := true; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG and L(L'left) = '1' then FREMAIN := "0"-FREMAIN; elsif RNEG and FREMAIN /= "0" then FREMAIN := FREMAIN-XDENOM; elsif L(L'left) = '1' and FREMAIN /= "0" then FREMAIN := XDENOM-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "mod"; -- Id: A.35 function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.36 function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- Id: A.37 function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.38 function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- ============================================================================ -- Id: A.39 function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.40 function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.41 function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- Id: A.42 function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- ============================================================================ -- Id: C.1 function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.2 function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.3 function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function ">"; -- Id: C.4 function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function ">"; -- Id: C.5 function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function ">"; -- Id: C.6 function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function ">"; -- ============================================================================ -- Id: C.7 function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.8 function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.9 function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function "<"; -- Id: C.10 function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function "<"; -- Id: C.11 function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function "<"; -- Id: C.12 function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function "<"; -- ============================================================================ -- Id: C.13 function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.14 function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.15 function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "<="; -- Id: C.16 function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function "<="; -- Id: C.17 function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "<="; -- Id: C.18 function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "<="; -- ============================================================================ -- Id: C.19 function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.20 function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.21 function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function ">="; -- Id: C.22 function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function ">="; -- Id: C.23 function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function ">="; -- Id: C.24 function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function ">="; -- ============================================================================ -- Id: C.25 function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.26 function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.27 function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return false; end if; return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "="; -- Id: C.28 function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return false; end if; return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01); end function "="; -- Id: C.29 function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "="; -- Id: C.30 function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return false; end if; return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "="; -- ============================================================================ -- Id: C.31 function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.32 function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.33 function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01)); end function "/="; -- Id: C.34 function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(L) > R'length then return true; end if; return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01)); end function "/="; -- Id: C.35 function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(R) > L'length then return true; end if; return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length))); end function "/="; -- Id: C.36 function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(R) > L'length then return true; end if; return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length))); end function "/="; -- ============================================================================ -- Id: C.37 function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.38 function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.39 function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MINIMUM(TO_UNSIGNED(L, R'length), R); end function MINIMUM; -- Id: C.40 function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MINIMUM(TO_SIGNED(L, R'length), R); end function MINIMUM; -- Id: C.41 function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MINIMUM(L, TO_UNSIGNED(R, L'length)); end function MINIMUM; -- Id: C.42 function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MINIMUM(L, TO_SIGNED(R, L'length)); end function MINIMUM; -- ============================================================================ -- Id: C.43 function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.44 function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.45 function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(TO_UNSIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.46 function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MAXIMUM(TO_SIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.47 function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(L, TO_UNSIGNED(R, L'length)); end function MAXIMUM; -- Id: C.48 function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MAXIMUM(L, TO_SIGNED(R, L'length)); end function MAXIMUM; -- ============================================================================ -- Id: C.49 function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.50 function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.51 function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.52 function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.53 function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?> TO_UNSIGNED(R, L'length); end function "?>"; -- Id: C.54 function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?> TO_SIGNED(R, L'length); end function "?>"; -- ============================================================================ -- Id: C.55 function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.56 function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.57 function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.58 function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.59 function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?< TO_UNSIGNED(R, L'length); end function "?<"; -- Id: C.60 function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?< TO_SIGNED(R, L'length); end function "?<"; -- ============================================================================ -- Id: C.61 function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.62 function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.63 function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.64 function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.65 function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?<= TO_UNSIGNED(R, L'length); end function "?<="; -- Id: C.66 function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?<= TO_SIGNED(R, L'length); end function "?<="; -- ============================================================================ -- Id: C.67 function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.68 function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.69 function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.70 function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.71 function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?>= TO_UNSIGNED(R, L'length); end function "?>="; -- Id: C.72 function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?>= TO_SIGNED(R, L'length); end function "?>="; -- ============================================================================ -- Id: C.73 function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- Logically identical to an "=" operator. if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.74 function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.75 function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?= R; end function "?="; -- Id: C.76 function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?= R; end function "?="; -- Id: C.77 function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?= TO_UNSIGNED(R, L'length); end function "?="; -- Id: C.78 function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?= TO_SIGNED(R, L'length); end function "?="; -- ============================================================================ -- Id: C.79 function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.80 function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.81 function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.82 function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.83 function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?/= TO_UNSIGNED(R, L'length); end function "?/="; -- Id: C.84 function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?/= TO_SIGNED(R, L'length); end function "?/="; -- ============================================================================ -- Id: S.1 function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.2 function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- Id: S.3 function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.4 function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- ============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.6 function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- Id: S.7 function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.8 function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- ============================================================================ ------------------------------------------------------------------------------ -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.9 function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.10 function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT)); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.12 function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT)); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.13 function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.14 function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.17 function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.18 function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.19 function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; ------------------------------------------------------------------------------ -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.20 function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; -- ============================================================================ -- Id: D.1 function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is constant ARG_LEFT : INTEGER := ARG'length-1; alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0); variable RESULT : NATURAL := 0; begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(XXARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; for I in XARG'range loop RESULT := RESULT+RESULT; if XARG(I) = '1' then RESULT := RESULT + 1; end if; end loop; return RESULT; end function TO_INTEGER; -- Id: D.2 function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0); begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(ARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; if XARG(XARG'left) = '0' then return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG)); else return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1); end if; end function TO_INTEGER; -- Id: D.3 function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable I_VAL : NATURAL := ARG; begin if (SIZE < 1) then return NAU; end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := '0'; else RESULT(I) := '1'; end if; I_VAL := I_VAL/2; end loop; if not(I_VAL = 0) then assert NO_WARNING report "NUMERIC_STD.TO_UNSIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_UNSIGNED; -- Id: D.4 function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable B_VAL : STD_LOGIC := '0'; variable I_VAL : INTEGER := ARG; begin if (SIZE < 1) then return NAS; end if; if (ARG < 0) then B_VAL := '1'; I_VAL := -(ARG+1); end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := B_VAL; else RESULT(I) := not B_VAL; end if; I_VAL := I_VAL/2; end loop; if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then assert NO_WARNING report "NUMERIC_STD.TO_SIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_SIGNED; function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_UNSIGNED; function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_SIGNED; -- ============================================================================ -- Id: R.1 function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED is alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) := (others => '0'); constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2; begin if (NEW_SIZE < 1) then return NAS; end if; if (ARG'length = 0) then return RESULT; end if; RESULT := (others => ARG(ARG'left)); if BOUND >= 0 then RESULT(BOUND downto 0) := INVEC(BOUND downto 0); end if; return RESULT; end function RESIZE; -- Id: R.2 function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0'); begin if (NEW_SIZE < 1) then return NAU; end if; if XARG'length = 0 then return RESULT; end if; if (RESULT'length < ARG'length) then RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0); else RESULT(RESULT'left downto XARG'left+1) := (others => '0'); RESULT(XARG'left downto 0) := XARG; end if; return RESULT; end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; -- ============================================================================ -- Id: L.1 function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.2 function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.3 function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.4 function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.5 function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.6 function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.7 function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.8 function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.9 function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.10 function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.11 function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.12 function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.13 function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.14 function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.15 function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.16 function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.17 function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.18 function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.19 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.20 function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.21 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.22 function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.23 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.24 function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.25 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.26 function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; -- Id: L.27 function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.28 function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.29 function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.30 function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.31 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.32 function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.33 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.34 function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.35 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.36 function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.37 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.38 function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.39 function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.40 function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.41 function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.42 function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.43 function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.44 function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.45 function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.46 function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.47 function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.48 function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.49 function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.50 function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; -- ============================================================================ -- support constants for STD_MATCH: type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN; constant MATCH_TABLE : BOOLEAN_TABLE := ( -------------------------------------------------------------------------- -- U X 0 1 Z W L H - -------------------------------------------------------------------------- (false, false, false, false, false, false, false, false, true), -- | U | (false, false, false, false, false, false, false, false, true), -- | X | (false, false, true, false, false, false, true, false, true), -- | 0 | (false, false, false, true, false, false, false, true, true), -- | 1 | (false, false, false, false, false, false, false, false, true), -- | Z | (false, false, false, false, false, false, false, false, true), -- | W | (false, false, true, false, false, false, true, false, true), -- | L | (false, false, false, true, false, false, false, true, true), -- | H | (true, true, true, true, true, true, true, true, true) -- | - | ); -- Id: M.1 function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is variable VALUE : STD_ULOGIC; begin return MATCH_TABLE(L, R); end function STD_MATCH; -- Id: M.2 function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L; alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.3 function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is alias LV : UNRESOLVED_SIGNED(1 to L'length) is L; alias RV : UNRESOLVED_SIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.5 function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L; alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- ============================================================================ -- function TO_01 is used to convert vectors to the -- correct form for exported functions, -- and to report if there is an element which -- is not in (0, 1, H, L). -- Id: T.1 function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAU" severity warning; return NAU; end if; return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.2 function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAS" severity warning; return NAS; end if; return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.3 function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.4 function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.5 function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.6 function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.7 function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.8 function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.9 function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- Id: T.10 function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- ============================================================================ -- string conversion and write operations -- ============================================================================ function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_ostring(STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_ostring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+2)/3; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_ostring(pad & STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_hstring(STD_ULOGIC_VECTOR (value)); end function to_hstring; function to_hstring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_hstring(pad & STD_ULOGIC_VECTOR (value)); end function to_hstring; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := SIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := SIGNED (ivalue); end procedure READ; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); -- Bail out if there was a bad read if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.OREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.HREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is constant ne : INTEGER := (VALUE'length+2)/3; constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1) := (others => VALUE (VALUE'left)); variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); constant ne : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1) := (others => VALUE(VALUE'left)); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; end package body NUMERIC_STD;
-- -------------------------------------------------------------------- -- -- Copyright © 2008 by IEEE. All rights reserved. -- -- This source file is an essential part of IEEE Std 1076-2008, -- IEEE Standard VHDL Language Reference Manual. This source file may not be -- copied, sold, or included with software that is sold without written -- permission from the IEEE Standards Department. This source file may be -- copied for individual use between licensed users. This source file is -- provided on an AS IS basis. The IEEE disclaims ANY WARRANTY EXPRESS OR -- IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY AND FITNESS FOR USE -- FOR A PARTICULAR PURPOSE. The user of the source file shall indemnify -- and hold IEEE harmless from any damages or liability arising out of the -- use thereof. -- -- Title : Standard VHDL Synthesis Packages -- : (NUMERIC_STD package body) -- : -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE DASC Synthesis Working Group, -- : Accellera VHDL-TC, and IEEE P1076 Working Group -- : -- Purpose : This package defines numeric types and arithmetic functions -- : for use with synthesis tools. Two numeric types are defined: -- : -- > UNRESOLVED_UNSIGNED: represents an UNSIGNED number -- : in vector form -- : -- > UNRESOLVED_SIGNED: represents a SIGNED number -- : in vector form -- : The base element type is type STD_ULOGIC. -- : Aliases U_UNSIGNED and U_SIGNED are defined for the types -- : UNRESOLVED_UNSIGNED and UNRESOLVED_SIGNED, respectively. -- : Two numeric subtypes are defined: -- : -- > UNSIGNED: represents UNSIGNED number in vector form -- : -- > SIGNED: represents a SIGNED number in vector form -- : The element subtypes are the same subtype as STD_LOGIC. -- : The leftmost bit is treated as the most significant bit. -- : Signed vectors are represented in two's complement form. -- : This package contains overloaded arithmetic operators on -- : the SIGNED and UNSIGNED types. The package also contains -- : useful type conversions functions, clock detection -- : functions, and other utility functions. -- : -- : If any argument to a function is a null array, a null array -- : is returned (exceptions, if any, are noted individually). -- -- Note : This package may be modified to include additional data -- : required by tools, but it must in no way change the -- : external interfaces or simulation behavior of the -- : description. It is permissible to add comments and/or -- : attributes to the package declarations, but not to change -- : or delete any original lines of the package declaration. -- : The package body may be changed only in accordance with -- : the terms of Clause 16 of this standard. -- : -- -------------------------------------------------------------------- -- $Revision: 1220 $ -- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $ -- -------------------------------------------------------------------- package body NUMERIC_STD is -- null range array constants constant NAU : UNRESOLVED_UNSIGNED (0 downto 1) := (others => '0'); constant NAS : UNRESOLVED_SIGNED (0 downto 1) := (others => '0'); -- implementation controls constant NO_WARNING : BOOLEAN := false; -- default to emit warnings -- =========================Local Subprograms ================================= function SIGNED_NUM_BITS (ARG : INTEGER) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin if ARG >= 0 then N := ARG; else N := -(ARG+1); end if; NBITS := 1; while N > 0 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function SIGNED_NUM_BITS; function UNSIGNED_NUM_BITS (ARG : NATURAL) return NATURAL is variable NBITS : NATURAL; variable N : NATURAL; begin N := ARG; NBITS := 1; while N > 1 loop NBITS := NBITS+1; N := N / 2; end loop; return NBITS; end function UNSIGNED_NUM_BITS; ------------------------------------------------------------------------ -- this internal function computes the addition of two UNRESOLVED_UNSIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_UNSIGNED (L, R : UNRESOLVED_UNSIGNED; C : STD_LOGIC) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_UNSIGNED; -- this internal function computes the addition of two UNRESOLVED_SIGNED -- with input CARRY -- * the two arguments are of the same length function ADD_SIGNED (L, R : UNRESOLVED_SIGNED; C : STD_LOGIC) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(L_LEFT downto 0) is R; variable RESULT : UNRESOLVED_SIGNED(L_LEFT downto 0); variable CBIT : STD_LOGIC := C; begin for I in 0 to L_LEFT loop RESULT(I) := CBIT xor XL(I) xor XR(I); CBIT := (CBIT and XL(I)) or (CBIT and XR(I)) or (XL(I) and XR(I)); end loop; return RESULT; end function ADD_SIGNED; ----------------------------------------------------------------------------- -- this internal procedure computes UNSIGNED division -- giving the quotient and remainder. procedure DIVMOD (NUM, XDENOM : UNRESOLVED_UNSIGNED; XQUOT, XREMAIN : out UNRESOLVED_UNSIGNED) is variable TEMP : UNRESOLVED_UNSIGNED(NUM'length downto 0); variable QUOT : UNRESOLVED_UNSIGNED(MAXIMUM(NUM'length, XDENOM'length)-1 downto 0); alias DENOM : UNRESOLVED_UNSIGNED(XDENOM'length-1 downto 0) is XDENOM; variable TOPBIT : INTEGER; begin TEMP := "0"&NUM; QUOT := (others => '0'); TOPBIT := -1; for J in DENOM'range loop if DENOM(J) = '1' then TOPBIT := J; exit; end if; end loop; assert TOPBIT >= 0 report "NUMERIC_STD.DIVMOD: DIV, MOD, or REM by zero" severity error; for J in NUM'length-(TOPBIT+1) downto 0 loop if TEMP(TOPBIT+J+1 downto J) >= "0"&DENOM(TOPBIT downto 0) then TEMP(TOPBIT+J+1 downto J) := (TEMP(TOPBIT+J+1 downto J)) -("0"&DENOM(TOPBIT downto 0)); QUOT(J) := '1'; end if; assert TEMP(TOPBIT+J+1) = '0' report "NUMERIC_STD.DIVMOD: internal error in the division algorithm" severity error; end loop; XQUOT := RESIZE(QUOT, XQUOT'length); XREMAIN := RESIZE(TEMP, XREMAIN'length); end procedure DIVMOD; -----------------Local Subprograms - shift/rotate ops------------------------- function XSLL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L downto COUNT) := XARG(ARG_L-COUNT downto 0); end if; return RESULT; end function XSLL; function XSRL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := (others => '0'); begin if COUNT <= ARG_L then RESULT(ARG_L-COUNT downto 0) := XARG(ARG_L downto COUNT); end if; return RESULT; end function XSRL; function XSRA (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0); variable XCOUNT : NATURAL := COUNT; begin if ((ARG'length <= 1) or (XCOUNT = 0)) then return ARG; else if (XCOUNT > ARG_L) then XCOUNT := ARG_L; end if; RESULT(ARG_L-XCOUNT downto 0) := XARG(ARG_L downto XCOUNT); RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others => XARG(ARG_L)); end if; return RESULT; end function XSRA; function XROL (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L downto COUNTM) := XARG(ARG_L-COUNTM downto 0); RESULT(COUNTM-1 downto 0) := XARG(ARG_L downto ARG_L-COUNTM+1); end if; return RESULT; end function XROL; function XROR (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL) return STD_ULOGIC_VECTOR is constant ARG_L : INTEGER := ARG'length-1; alias XARG : STD_ULOGIC_VECTOR(ARG_L downto 0) is ARG; variable RESULT : STD_ULOGIC_VECTOR(ARG_L downto 0) := XARG; variable COUNTM : INTEGER; begin COUNTM := COUNT mod (ARG_L + 1); if COUNTM /= 0 then RESULT(ARG_L-COUNTM downto 0) := XARG(ARG_L downto COUNTM); RESULT(ARG_L downto ARG_L-COUNTM+1) := XARG(COUNTM-1 downto 0); end if; return RESULT; end function XROR; -----------------Local Subprograms - Relational ops--------------------------- -- -- General "=" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function UNSIGNED_EQUAL; -- -- General "=" for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) = STD_ULOGIC_VECTOR(R); end function SIGNED_EQUAL; -- -- General "<" for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) < STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS; -- -- General "<" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS (L, R : UNRESOLVED_SIGNED) return BOOLEAN is variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) < STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS; -- -- General "<=" function for UNRESOLVED_UNSIGNED vectors, same length -- function UNSIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return STD_ULOGIC_VECTOR(L) <= STD_ULOGIC_VECTOR(R); end function UNSIGNED_LESS_OR_EQUAL; -- -- General "<=" function for UNRESOLVED_SIGNED vectors, same length -- function SIGNED_LESS_OR_EQUAL (L, R : UNRESOLVED_SIGNED) return BOOLEAN is -- Need aliases to assure index direction variable INTERN_L : UNRESOLVED_SIGNED(0 to L'length-1); variable INTERN_R : UNRESOLVED_SIGNED(0 to R'length-1); begin INTERN_L := L; INTERN_R := R; INTERN_L(0) := not INTERN_L(0); INTERN_R(0) := not INTERN_R(0); return STD_ULOGIC_VECTOR(INTERN_L) <= STD_ULOGIC_VECTOR(INTERN_R); end function SIGNED_LESS_OR_EQUAL; -- =========================Exported Functions ========================== -- Id: A.1 function "abs" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(ARG_LEFT downto 0); begin if ARG'length < 1 then return NAS; end if; RESULT := TO_01(XARG, 'X'); if (RESULT(RESULT'left) = 'X') then return RESULT; end if; if RESULT(RESULT'left) = '1' then RESULT := -RESULT; end if; return RESULT; end function "abs"; -- Id: A.2 function "-" (ARG : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_SIGNED(ARG_LEFT downto 0) is ARG; variable RESULT, XARG01 : UNRESOLVED_SIGNED(ARG_LEFT downto 0); variable CBIT : STD_LOGIC := '1'; begin if ARG'length < 1 then return NAS; end if; XARG01 := TO_01(ARG, 'X'); if (XARG01(XARG01'left) = 'X') then return XARG01; end if; for I in 0 to RESULT'left loop RESULT(I) := not(XARG01(I)) xor CBIT; CBIT := CBIT and not(XARG01(I)); end loop; return RESULT; end function "-"; -- ============================================================================ -- Id: A.3 function "+" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, R01, '0'); end function "+"; -- Id: A.3R function "+" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.3L function "+" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.4 function "+" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, R01, '0'); end function "+"; -- Id: A.4R function "+" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L + XR); end function "+"; -- Id: A.4L function "+" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL + R); end function "+"; -- Id: A.5 function "+" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L + TO_UNSIGNED(R, L'length); end function "+"; -- Id: A.6 function "+" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) + R; end function "+"; -- Id: A.7 function "+" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L + TO_SIGNED(R, L'length); end function "+"; -- Id: A.8 function "+" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) + R; end function "+"; -- ============================================================================ -- Id: A.9 function "-" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_UNSIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.9R function "-" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is variable XR : UNRESOLVED_UNSIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.9L function "-" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable XL : UNRESOLVED_UNSIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.10 function "-" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; return ADD_SIGNED(L01, not(R01), '1'); end function "-"; -- Id: A.10R function "-" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is variable XR : UNRESOLVED_SIGNED(L'length-1 downto 0) := (others => '0'); begin XR(0) := R; return (L - XR); end function "-"; -- Id: A.10L function "-" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable XL : UNRESOLVED_SIGNED(R'length-1 downto 0) := (others => '0'); begin XL(0) := L; return (XL - R); end function "-"; -- Id: A.11 function "-" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L - TO_UNSIGNED(R, L'length); end function "-"; -- Id: A.12 function "-" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) - R; end function "-"; -- Id: A.13 function "-" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L - TO_SIGNED(R, L'length); end function "-"; -- Id: A.14 function "-" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) - R; end function "-"; -- ============================================================================ -- Id: A.15 function "*" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_UNSIGNED((L'length+R'length-1) downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; return RESULT; end function "*"; -- Id: A.16 function "*" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable RESULT : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0) := (others => '0'); variable ADVAL : UNRESOLVED_SIGNED((L_LEFT+R_LEFT+1) downto 0); begin if ((L_LEFT < 0) or (R_LEFT < 0)) then return NAS; end if; XL := TO_01(L, 'X'); XR := TO_01(R, 'X'); if ((XL(L_LEFT) = 'X') or (XR(R_LEFT) = 'X')) then RESULT := (others => 'X'); return RESULT; end if; ADVAL := RESIZE(XR, RESULT'length); for I in 0 to L_LEFT-1 loop if XL(I) = '1' then RESULT := RESULT + ADVAL; end if; ADVAL := SHIFT_LEFT(ADVAL, 1); end loop; if XL(L_LEFT) = '1' then RESULT := RESULT - ADVAL; end if; return RESULT; end function "*"; -- Id: A.17 function "*" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return L * TO_UNSIGNED(R, L'length); end function "*"; -- Id: A.18 function "*" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED(L, R'length) * R; end function "*"; -- Id: A.19 function "*" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return L * TO_SIGNED(R, L'length); end function "*"; -- Id: A.20 function "*" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED(L, R'length) * R; end function "*"; -- ============================================================================ -- Id: A.21 function "/" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return FQUOT; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FQUOT; end function "/"; -- Id: A.22 function "/" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable QNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FQUOT := (others => 'X'); return UNRESOLVED_SIGNED(FQUOT); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); QNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); QNEG := not QNEG; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if QNEG then FQUOT := "0"-FQUOT; end if; return UNRESOLVED_SIGNED(FQUOT); end function "/"; -- Id: A.23 function "/" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_UNSIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.24 function "/" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- Id: A.25 function "/" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, QUOT : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; if (R_LENGTH > L'length) then QUOT := (others => '0'); return RESIZE(QUOT, L'length); end if; XR := TO_SIGNED(R, R_LENGTH); QUOT := RESIZE((L / XR), QUOT'length); return RESIZE(QUOT, L'length); end function "/"; -- Id: A.26 function "/" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, QUOT : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); QUOT := RESIZE((XL / R), QUOT'length); if L_LENGTH > R'length and QUOT(0) /= 'X' and QUOT(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => QUOT(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""/"": Quotient Truncated" severity warning; end if; return RESIZE(QUOT, R'length); end function "/"; -- ============================================================================ -- Id: A.27 function "rem" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "rem"; -- Id: A.28 function "rem" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XNUM := UNRESOLVED_UNSIGNED(TO_01(XXL, 'X')); XDENOM := UNRESOLVED_UNSIGNED(TO_01(XXR, 'X')); if ((XNUM(XNUM'left) = 'X') or (XDENOM(XDENOM'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XNUM(XNUM'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XNUM)); RNEG := true; else XNUM := UNRESOLVED_UNSIGNED(XNUM); end if; if XDENOM(XDENOM'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-UNRESOLVED_SIGNED(XDENOM)); else XDENOM := UNRESOLVED_UNSIGNED(XDENOM); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG then FREMAIN := "0"-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "rem"; -- Id: A.29 function "rem" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := L rem XR; if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.30 function "rem" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin XL := TO_UNSIGNED(L, L_LENGTH); XREM := XL rem R; if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- Id: A.31 function "rem" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L rem XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "rem"; -- Id: A.32 function "rem" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL rem R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""rem"": Remainder Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "rem"; -- ============================================================================ -- Id: A.33 function "mod" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return FREMAIN; end if; DIVMOD(XL, XR, FQUOT, FREMAIN); return FREMAIN; end function "mod"; -- Id: A.34 function "mod" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XXL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XXR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable XL : UNRESOLVED_SIGNED(L_LEFT downto 0); variable XR : UNRESOLVED_SIGNED(R_LEFT downto 0); variable FQUOT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable FREMAIN : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable XNUM : UNRESOLVED_UNSIGNED(L'length-1 downto 0); variable XDENOM : UNRESOLVED_UNSIGNED(R'length-1 downto 0); variable RNEG : BOOLEAN := false; begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; XL := TO_01(XXL, 'X'); XR := TO_01(XXR, 'X'); if ((XL(XL'left) = 'X') or (XR(XR'left) = 'X')) then FREMAIN := (others => 'X'); return UNRESOLVED_SIGNED(FREMAIN); end if; if XL(XL'left) = '1' then XNUM := UNRESOLVED_UNSIGNED(-XL); else XNUM := UNRESOLVED_UNSIGNED(XL); end if; if XR(XR'left) = '1' then XDENOM := UNRESOLVED_UNSIGNED(-XR); RNEG := true; else XDENOM := UNRESOLVED_UNSIGNED(XR); end if; DIVMOD(XNUM, XDENOM, FQUOT, FREMAIN); if RNEG and L(L'left) = '1' then FREMAIN := "0"-FREMAIN; elsif RNEG and FREMAIN /= "0" then FREMAIN := FREMAIN-XDENOM; elsif L(L'left) = '1' and FREMAIN /= "0" then FREMAIN := XDENOM-FREMAIN; end if; return UNRESOLVED_SIGNED(FREMAIN); end function "mod"; -- Id: A.35 function "mod" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, UNSIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_UNSIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAU; end if; XR := TO_UNSIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.36 function "mod" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant L_LENGTH : NATURAL := MAXIMUM(UNSIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_UNSIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAU; end if; XL := TO_UNSIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => '0') then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- Id: A.37 function "mod" (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is constant R_LENGTH : NATURAL := MAXIMUM(L'length, SIGNED_NUM_BITS(R)); variable XR, XREM : UNRESOLVED_SIGNED(R_LENGTH-1 downto 0); begin if (L'length < 1) then return NAS; end if; XR := TO_SIGNED(R, R_LENGTH); XREM := RESIZE((L mod XR), XREM'length); if R_LENGTH > L'length and XREM(0) /= 'X' and XREM(R_LENGTH-1 downto L'length) /= (R_LENGTH-1 downto L'length => XREM(L'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, L'length); end function "mod"; -- Id: A.38 function "mod" (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant L_LENGTH : NATURAL := MAXIMUM(SIGNED_NUM_BITS(L), R'length); variable XL, XREM : UNRESOLVED_SIGNED(L_LENGTH-1 downto 0); begin if (R'length < 1) then return NAS; end if; XL := TO_SIGNED(L, L_LENGTH); XREM := RESIZE((XL mod R), XREM'length); if L_LENGTH > R'length and XREM(0) /= 'X' and XREM(L_LENGTH-1 downto R'length) /= (L_LENGTH-1 downto R'length => XREM(R'length-1)) then assert NO_WARNING report "NUMERIC_STD.""mod"": Modulus Truncated" severity warning; end if; return RESIZE(XREM, R'length); end function "mod"; -- ============================================================================ -- Id: A.39 function find_leftmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.40 function find_leftmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_leftmost; -- Id: A.41 function find_rightmost (ARG : UNRESOLVED_UNSIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- Id: A.42 function find_rightmost (ARG : UNRESOLVED_SIGNED; Y : STD_ULOGIC) return INTEGER is begin for INDEX in ARG'reverse_range loop if ARG(INDEX) ?= Y then return INDEX; end if; end loop; return -1; end function find_rightmost; -- ============================================================================ -- Id: C.1 function ">" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.2 function ">" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">"; -- Id: C.3 function ">" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function ">"; -- Id: C.4 function ">" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function ">"; -- Id: C.5 function ">" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return not UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function ">"; -- Id: C.6 function ">" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function ">"; -- ============================================================================ -- Id: C.7 function "<" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.8 function "<" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<"; -- Id: C.9 function "<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function "<"; -- Id: C.10 function "<" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function "<"; -- Id: C.11 function "<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function "<"; -- Id: C.12 function "<" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<"": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<"": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function "<"; -- ============================================================================ -- Id: C.13 function "<=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.14 function "<=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_LESS_OR_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "<="; -- Id: C.15 function "<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return UNSIGNED_LESS_OR_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "<="; -- Id: C.16 function "<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L < 0; end if; return SIGNED_LESS_OR_EQUAL(TO_SIGNED(L, R01'length), R01); end function "<="; -- Id: C.17 function "<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return UNSIGNED_LESS_OR_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "<="; -- Id: C.18 function "<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L_LEFT < 0) then assert NO_WARNING report "NUMERIC_STD.""<="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""<="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 < R; end if; return SIGNED_LESS_OR_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "<="; -- ============================================================================ -- Id: C.19 function ">=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not UNSIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.20 function ">=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; return not SIGNED_LESS(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function ">="; -- Id: C.21 function ">=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not UNSIGNED_LESS(TO_UNSIGNED(L, R01'length), R01); end function ">="; -- Id: C.22 function ">=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return L > 0; end if; return not SIGNED_LESS(TO_SIGNED(L, R01'length), R01); end function ">="; -- Id: C.23 function ">=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not UNSIGNED_LESS(L01, TO_UNSIGNED(R, L01'length)); end function ">="; -- Id: C.24 function ">=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD."">="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD."">="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return 0 > R; end if; return not SIGNED_LESS(L01, TO_SIGNED(R, L01'length)); end function ">="; -- ============================================================================ -- Id: C.25 function "=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.26 function "=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; return SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE)); end function "="; -- Id: C.27 function "=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(L) > R'length then return false; end if; return UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01); end function "="; -- Id: C.28 function "=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(L) > R'length then return false; end if; return SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01); end function "="; -- Id: C.29 function "=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if UNSIGNED_NUM_BITS(R) > L'length then return false; end if; return UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length)); end function "="; -- Id: C.30 function "=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""="": null argument detected, returning FALSE" severity warning; return false; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""="": metavalue detected, returning FALSE" severity warning; return false; end if; if SIGNED_NUM_BITS(R) > L'length then return false; end if; return SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length)); end function "="; -- ============================================================================ -- Id: C.31 function "/=" (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(UNSIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.32 function "/=" (L, R : UNRESOLVED_SIGNED) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); R01 := TO_01(XR, 'X'); if ((L01(L01'left) = 'X') or (R01(R01'left) = 'X')) then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; return not(SIGNED_EQUAL(RESIZE(L01, SIZE), RESIZE(R01, SIZE))); end function "/="; -- Id: C.33 function "/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_UNSIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(L) > R'length then return true; end if; return not(UNSIGNED_EQUAL(TO_UNSIGNED(L, R01'length), R01)); end function "/="; -- Id: C.34 function "/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return BOOLEAN is constant R_LEFT : INTEGER := R'length-1; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; variable R01 : UNRESOLVED_SIGNED(R_LEFT downto 0); begin if (R'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; R01 := TO_01(XR, 'X'); if (R01(R01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(L) > R'length then return true; end if; return not(SIGNED_EQUAL(TO_SIGNED(L, R01'length), R01)); end function "/="; -- Id: C.35 function "/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_UNSIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if UNSIGNED_NUM_BITS(R) > L'length then return true; end if; return not(UNSIGNED_EQUAL(L01, TO_UNSIGNED(R, L01'length))); end function "/="; -- Id: C.36 function "/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return BOOLEAN is constant L_LEFT : INTEGER := L'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; variable L01 : UNRESOLVED_SIGNED(L_LEFT downto 0); begin if (L'length < 1) then assert NO_WARNING report "NUMERIC_STD.""/="": null argument detected, returning TRUE" severity warning; return true; end if; L01 := TO_01(XL, 'X'); if (L01(L01'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.""/="": metavalue detected, returning TRUE" severity warning; return true; end if; if SIGNED_NUM_BITS(R) > L'length then return true; end if; return not(SIGNED_EQUAL(L01, TO_SIGNED(R, L01'length))); end function "/="; -- ============================================================================ -- Id: C.37 function MINIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.38 function MINIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return L01; else return R01; end if; end function MINIMUM; -- Id: C.39 function MINIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MINIMUM(TO_UNSIGNED(L, R'length), R); end function MINIMUM; -- Id: C.40 function MINIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MINIMUM(TO_SIGNED(L, R'length), R); end function MINIMUM; -- Id: C.41 function MINIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MINIMUM(L, TO_UNSIGNED(R, L'length)); end function MINIMUM; -- Id: C.42 function MINIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MINIMUM(L, TO_SIGNED(R, L'length)); end function MINIMUM; -- ============================================================================ -- Id: C.43 function MAXIMUM (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAU; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if UNSIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.44 function MAXIMUM (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable L01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable R01 : UNRESOLVED_SIGNED(SIZE-1 downto 0); begin if ((L'length < 1) or (R'length < 1)) then return NAS; end if; L01 := TO_01(RESIZE(L, SIZE), 'X'); if (L01(L01'left) = 'X') then return L01; end if; R01 := TO_01(RESIZE(R, SIZE), 'X'); if (R01(R01'left) = 'X') then return R01; end if; if SIGNED_LESS(L01, R01) then return R01; else return L01; end if; end function MAXIMUM; -- Id: C.45 function MAXIMUM (L : NATURAL; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(TO_UNSIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.46 function MAXIMUM (L : INTEGER; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return MAXIMUM(TO_SIGNED(L, R'length), R); end function MAXIMUM; -- Id: C.47 function MAXIMUM (L : UNRESOLVED_UNSIGNED; R : NATURAL) return UNRESOLVED_UNSIGNED is begin return MAXIMUM(L, TO_UNSIGNED(R, L'length)); end function MAXIMUM; -- Id: C.48 function MAXIMUM (L : UNRESOLVED_SIGNED; R : INTEGER) return UNRESOLVED_SIGNED is begin return MAXIMUM(L, TO_SIGNED(R, L'length)); end function MAXIMUM; -- ============================================================================ -- Id: C.49 function "?>" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.50 function "?>" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L > R then return '1'; else return '0'; end if; end if; end function "?>"; -- Id: C.51 function "?>" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.52 function "?>" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?> R; end function "?>"; -- Id: C.53 function "?>" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?> TO_UNSIGNED(R, L'length); end function "?>"; -- Id: C.54 function "?>" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?> TO_SIGNED(R, L'length); end function "?>"; -- ============================================================================ -- Id: C.55 function "?<" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.56 function "?<" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<"": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<"": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L < R then return '1'; else return '0'; end if; end if; end function "?<"; -- Id: C.57 function "?<" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.58 function "?<" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?< R; end function "?<"; -- Id: C.59 function "?<" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?< TO_UNSIGNED(R, L'length); end function "?<"; -- Id: C.60 function "?<" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?< TO_SIGNED(R, L'length); end function "?<"; -- ============================================================================ -- Id: C.61 function "?<=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.62 function "?<=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?<="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?<="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L <= R then return '1'; else return '0'; end if; end if; end function "?<="; -- Id: C.63 function "?<=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.64 function "?<=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?<= R; end function "?<="; -- Id: C.65 function "?<=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?<= TO_UNSIGNED(R, L'length); end function "?<="; -- Id: C.66 function "?<=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?<= TO_SIGNED(R, L'length); end function "?<="; -- ============================================================================ -- Id: C.67 function "?>=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.68 function "?>=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?>="": null detected, returning X" severity warning; return 'X'; else for i in L'range loop if L(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; for i in R'range loop if R(i) = '-' then report "NUMERIC_STD.""?>="": '-' found in compare string" severity error; return 'X'; end if; end loop; if Is_X(L) or Is_X(R) then return 'X'; elsif L >= R then return '1'; else return '0'; end if; end if; end function "?>="; -- Id: C.69 function "?>=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.70 function "?>=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?>= R; end function "?>="; -- Id: C.71 function "?>=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?>= TO_UNSIGNED(R, L'length); end function "?>="; -- Id: C.72 function "?>=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?>= TO_SIGNED(R, L'length); end function "?>="; -- ============================================================================ -- Id: C.73 function "?=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- Logically identical to an "=" operator. if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.74 function "?=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '1'; for i in LX'low to LX'high loop result1 := LX(i) ?= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result and result1; end if; end loop; return result; end if; end function "?="; -- Id: C.75 function "?=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?= R; end function "?="; -- Id: C.76 function "?=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?= R; end function "?="; -- Id: C.77 function "?=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?= TO_UNSIGNED(R, L'length); end function "?="; -- Id: C.78 function "?=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?= TO_SIGNED(R, L'length); end function "?="; -- ============================================================================ -- Id: C.79 function "?/=" (L, R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_UNSIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_UNSIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.80 function "?/=" (L, R : UNRESOLVED_SIGNED) return STD_ULOGIC is constant L_LEFT : INTEGER := L'length-1; constant R_LEFT : INTEGER := R'length-1; alias XL : UNRESOLVED_SIGNED(L_LEFT downto 0) is L; alias XR : UNRESOLVED_SIGNED(R_LEFT downto 0) is R; constant SIZE : NATURAL := MAXIMUM(L'length, R'length); variable LX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable RX : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable result, result1 : STD_ULOGIC; -- result begin -- ?= if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.""?/="": null detected, returning X" severity warning; return 'X'; else LX := RESIZE(XL, SIZE); RX := RESIZE(XR, SIZE); result := '0'; for i in LX'low to LX'high loop result1 := LX(i) ?/= RX(i); if result1 = 'U' then return 'U'; elsif result1 = 'X' or result = 'X' then result := 'X'; else result := result or result1; end if; end loop; return result; end if; end function "?/="; -- Id: C.81 function "?/=" (L : NATURAL; R : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return TO_UNSIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.82 function "?/=" (L : INTEGER; R : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return TO_SIGNED(L, R'length) ?/= R; end function "?/="; -- Id: C.83 function "?/=" (L : UNRESOLVED_UNSIGNED; R : NATURAL) return STD_ULOGIC is begin return L ?/= TO_UNSIGNED(R, L'length); end function "?/="; -- Id: C.84 function "?/=" (L : UNRESOLVED_SIGNED; R : INTEGER) return STD_ULOGIC is begin return L ?/= TO_SIGNED(R, L'length); end function "?/="; -- ============================================================================ -- Id: S.1 function SHIFT_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.2 function SHIFT_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XSRL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- Id: S.3 function SHIFT_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSLL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_LEFT; -- Id: S.4 function SHIFT_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XSRA(STD_ULOGIC_VECTOR(ARG), COUNT)); end function SHIFT_RIGHT; -- ============================================================================ -- Id: S.5 function ROTATE_LEFT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.6 function ROTATE_RIGHT (ARG : UNRESOLVED_UNSIGNED; COUNT : NATURAL) return UNRESOLVED_UNSIGNED is begin if (ARG'length < 1) then return NAU; end if; return UNRESOLVED_UNSIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- Id: S.7 function ROTATE_LEFT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROL(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_LEFT; -- Id: S.8 function ROTATE_RIGHT (ARG : UNRESOLVED_SIGNED; COUNT : NATURAL) return UNRESOLVED_SIGNED is begin if (ARG'length < 1) then return NAS; end if; return UNRESOLVED_SIGNED(XROR(STD_ULOGIC_VECTOR(ARG), COUNT)); end function ROTATE_RIGHT; -- ============================================================================ ------------------------------------------------------------------------------ -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.9 function "sll" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.10 function "sll" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), -COUNT)); end if; end function "sll"; ------------------------------------------------------------------------------ -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.11 function "srl" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.12 function "srl" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return UNRESOLVED_SIGNED(SHIFT_RIGHT(UNRESOLVED_UNSIGNED(ARG), COUNT)); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "srl"; ------------------------------------------------------------------------------ -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.13 function "rol" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.14 function "rol" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_LEFT(ARG, COUNT); else return ROTATE_RIGHT(ARG, -COUNT); end if; end function "rol"; ------------------------------------------------------------------------------ -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.15 function "ror" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.16 function "ror" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return ROTATE_RIGHT(ARG, COUNT); else return ROTATE_LEFT(ARG, -COUNT); end if; end function "ror"; ------------------------------------------------------------------------------ -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.17 function "sla" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.18 function "sla" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_LEFT(ARG, COUNT); else return SHIFT_RIGHT(ARG, -COUNT); end if; end function "sla"; ------------------------------------------------------------------------------ -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.19 function "sra" (ARG : UNRESOLVED_UNSIGNED; COUNT : INTEGER) return UNRESOLVED_UNSIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; ------------------------------------------------------------------------------ -- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: S.20 function "sra" (ARG : UNRESOLVED_SIGNED; COUNT : INTEGER) return UNRESOLVED_SIGNED is begin if (COUNT >= 0) then return SHIFT_RIGHT(ARG, COUNT); else return SHIFT_LEFT(ARG, -COUNT); end if; end function "sra"; -- ============================================================================ -- Id: D.1 function TO_INTEGER (ARG : UNRESOLVED_UNSIGNED) return NATURAL is constant ARG_LEFT : INTEGER := ARG'length-1; alias XXARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0); variable RESULT : NATURAL := 0; begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(XXARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; for I in XARG'range loop RESULT := RESULT+RESULT; if XARG(I) = '1' then RESULT := RESULT + 1; end if; end loop; return RESULT; end function TO_INTEGER; -- Id: D.2 function TO_INTEGER (ARG : UNRESOLVED_SIGNED) return INTEGER is variable XARG : UNRESOLVED_SIGNED(ARG'length-1 downto 0); begin if (ARG'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: null detected, returning 0" severity warning; return 0; end if; XARG := TO_01(ARG, 'X'); if (XARG(XARG'left) = 'X') then assert NO_WARNING report "NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0" severity warning; return 0; end if; if XARG(XARG'left) = '0' then return TO_INTEGER(UNRESOLVED_UNSIGNED(XARG)); else return (- (TO_INTEGER(UNRESOLVED_UNSIGNED(- (XARG + 1)))) -1); end if; end function TO_INTEGER; -- Id: D.3 function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(SIZE-1 downto 0); variable I_VAL : NATURAL := ARG; begin if (SIZE < 1) then return NAU; end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := '0'; else RESULT(I) := '1'; end if; I_VAL := I_VAL/2; end loop; if not(I_VAL = 0) then assert NO_WARNING report "NUMERIC_STD.TO_UNSIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_UNSIGNED; -- Id: D.4 function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(SIZE-1 downto 0); variable B_VAL : STD_LOGIC := '0'; variable I_VAL : INTEGER := ARG; begin if (SIZE < 1) then return NAS; end if; if (ARG < 0) then B_VAL := '1'; I_VAL := -(ARG+1); end if; for I in 0 to RESULT'left loop if (I_VAL mod 2) = 0 then RESULT(I) := B_VAL; else RESULT(I) := not B_VAL; end if; I_VAL := I_VAL/2; end loop; if ((I_VAL /= 0) or (B_VAL /= RESULT(RESULT'left))) then assert NO_WARNING report "NUMERIC_STD.TO_SIGNED: vector truncated" severity warning; end if; return RESULT; end function TO_SIGNED; function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return TO_UNSIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_UNSIGNED; function TO_SIGNED (ARG : INTEGER; SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return TO_SIGNED (ARG => ARG, SIZE => SIZE_RES'length); end function TO_SIGNED; -- ============================================================================ -- Id: R.1 function RESIZE (ARG : UNRESOLVED_SIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_SIGNED is alias INVEC : UNRESOLVED_SIGNED(ARG'length-1 downto 0) is ARG; variable RESULT : UNRESOLVED_SIGNED(NEW_SIZE-1 downto 0) := (others => '0'); constant BOUND : INTEGER := MINIMUM(ARG'length, RESULT'length)-2; begin if (NEW_SIZE < 1) then return NAS; end if; if (ARG'length = 0) then return RESULT; end if; RESULT := (others => ARG(ARG'left)); if BOUND >= 0 then RESULT(BOUND downto 0) := INVEC(BOUND downto 0); end if; return RESULT; end function RESIZE; -- Id: R.2 function RESIZE (ARG : UNRESOLVED_UNSIGNED; NEW_SIZE : NATURAL) return UNRESOLVED_UNSIGNED is constant ARG_LEFT : INTEGER := ARG'length-1; alias XARG : UNRESOLVED_UNSIGNED(ARG_LEFT downto 0) is ARG; variable RESULT : UNRESOLVED_UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0'); begin if (NEW_SIZE < 1) then return NAU; end if; if XARG'length = 0 then return RESULT; end if; if (RESULT'length < ARG'length) then RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0); else RESULT(RESULT'left downto XARG'left+1) := (others => '0'); RESULT(XARG'left downto 0) := XARG; end if; return RESULT; end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; function RESIZE (ARG, SIZE_RES : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return RESIZE (ARG => ARG, NEW_SIZE => SIZE_RES'length); end function RESIZE; -- ============================================================================ -- Id: L.1 function "not" (L : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.2 function "and" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.3 function "or" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.4 function "nand" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.5 function "nor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.6 function "xor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.7 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.7 function "xnor" (L, R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is variable RESULT : UNRESOLVED_UNSIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_UNSIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.8 function "not" (L : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(not(STD_ULOGIC_VECTOR(L))); return RESULT; end function "not"; -- Id: L.9 function "and" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) and STD_ULOGIC_VECTOR(R)); return RESULT; end function "and"; -- Id: L.10 function "or" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) or STD_ULOGIC_VECTOR(R)); return RESULT; end function "or"; -- Id: L.11 function "nand" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nand STD_ULOGIC_VECTOR(R)); return RESULT; end function "nand"; -- Id: L.12 function "nor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) nor STD_ULOGIC_VECTOR(R)); return RESULT; end function "nor"; -- Id: L.13 function "xor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.14 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.14 function "xnor" (L, R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is variable RESULT : UNRESOLVED_SIGNED(L'length-1 downto 0); begin RESULT := UNRESOLVED_SIGNED(STD_ULOGIC_VECTOR(L) xnor STD_ULOGIC_VECTOR(R)); return RESULT; end function "xnor"; -- Id: L.15 function "and" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.16 function "and" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.17 function "or" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.18 function "or" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.19 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.20 function "nand" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.21 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.22 function "nor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.23 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.24 function "xor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.25 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.25 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.26 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.26 function "xnor" (L : UNRESOLVED_UNSIGNED; R : STD_ULOGIC) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; -- Id: L.27 function "and" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L and STD_ULOGIC_VECTOR(R)); end function "and"; -- Id: L.28 function "and" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) and R); end function "and"; -- Id: L.29 function "or" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L or STD_ULOGIC_VECTOR(R)); end function "or"; -- Id: L.30 function "or" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) or R); end function "or"; -- Id: L.31 function "nand" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nand STD_ULOGIC_VECTOR(R)); end function "nand"; -- Id: L.32 function "nand" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nand R); end function "nand"; -- Id: L.33 function "nor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L nor STD_ULOGIC_VECTOR(R)); end function "nor"; -- Id: L.34 function "nor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) nor R); end function "nor"; -- Id: L.35 function "xor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xor STD_ULOGIC_VECTOR(R)); end function "xor"; -- Id: L.36 function "xor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xor R); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.37 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.37 function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (L xnor STD_ULOGIC_VECTOR(R)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.38 is not compatible with IEEE Std 1076-1987. Comment -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility. ------------------------------------------------------------------------------ -- Id: L.38 function "xnor" (L : UNRESOLVED_SIGNED; R : STD_ULOGIC) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED (STD_ULOGIC_VECTOR(L) xnor R); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.39 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.39 function "and" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.40 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.40 function "and" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return and (STD_ULOGIC_VECTOR (L)); end function "and"; ------------------------------------------------------------------------------ -- Note: Function L.41 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.41 function "nand" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.42 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.42 function "nand" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nand (STD_ULOGIC_VECTOR (L)); end function "nand"; ------------------------------------------------------------------------------ -- Note: Function L.43 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.43 function "or" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.44 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.44 function "or" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return or (STD_ULOGIC_VECTOR (L)); end function "or"; ------------------------------------------------------------------------------ -- Note: Function L.45 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.45 function "nor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.46 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.46 function "nor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return nor (STD_ULOGIC_VECTOR (L)); end function "nor"; ------------------------------------------------------------------------------ -- Note: Function L.47 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.47 function "xor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.48 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.48 function "xor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xor (STD_ULOGIC_VECTOR (L)); end function "xor"; ------------------------------------------------------------------------------ -- Note: Function L.49 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.49 function "xnor" (L : UNRESOLVED_SIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; ------------------------------------------------------------------------------ -- Note: Function L.50 is not compatible with editions of IEEE Std 1076 from -- 1987 through 2002. Comment out the function (declaration and body) for -- compatibility with these editions. ------------------------------------------------------------------------------ -- Id: L.50 function "xnor" (L : UNRESOLVED_UNSIGNED) return STD_ULOGIC is begin return xnor (STD_ULOGIC_VECTOR (L)); end function "xnor"; -- ============================================================================ -- support constants for STD_MATCH: type BOOLEAN_TABLE is array(STD_ULOGIC, STD_ULOGIC) of BOOLEAN; constant MATCH_TABLE : BOOLEAN_TABLE := ( -------------------------------------------------------------------------- -- U X 0 1 Z W L H - -------------------------------------------------------------------------- (false, false, false, false, false, false, false, false, true), -- | U | (false, false, false, false, false, false, false, false, true), -- | X | (false, false, true, false, false, false, true, false, true), -- | 0 | (false, false, false, true, false, false, false, true, true), -- | 1 | (false, false, false, false, false, false, false, false, true), -- | Z | (false, false, false, false, false, false, false, false, true), -- | W | (false, false, true, false, false, false, true, false, true), -- | L | (false, false, false, true, false, false, false, true, true), -- | H | (true, true, true, true, true, true, true, true, true) -- | - | ); -- Id: M.1 function STD_MATCH (L, R : STD_ULOGIC) return BOOLEAN is variable VALUE : STD_ULOGIC; begin return MATCH_TABLE(L, R); end function STD_MATCH; -- Id: M.2 function STD_MATCH (L, R : UNRESOLVED_UNSIGNED) return BOOLEAN is alias LV : UNRESOLVED_UNSIGNED(1 to L'length) is L; alias RV : UNRESOLVED_UNSIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.3 function STD_MATCH (L, R : UNRESOLVED_SIGNED) return BOOLEAN is alias LV : UNRESOLVED_SIGNED(1 to L'length) is L; alias RV : UNRESOLVED_SIGNED(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- Id: M.5 function STD_MATCH (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is alias LV : STD_ULOGIC_VECTOR(1 to L'length) is L; alias RV : STD_ULOGIC_VECTOR(1 to R'length) is R; begin if ((L'length < 1) or (R'length < 1)) then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: null detected, returning FALSE" severity warning; return false; end if; if LV'length /= RV'length then assert NO_WARNING report "NUMERIC_STD.STD_MATCH: L'LENGTH /= R'LENGTH, returning FALSE" severity warning; return false; else for I in LV'low to LV'high loop if not (MATCH_TABLE(LV(I), RV(I))) then return false; end if; end loop; return true; end if; end function STD_MATCH; -- ============================================================================ -- function TO_01 is used to convert vectors to the -- correct form for exported functions, -- and to report if there is an element which -- is not in (0, 1, H, L). -- Id: T.1 function TO_01 (S : UNRESOLVED_UNSIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_UNSIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAU" severity warning; return NAU; end if; return UNRESOLVED_UNSIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.2 function TO_01 (S : UNRESOLVED_SIGNED; XMAP : STD_ULOGIC := '0') return UNRESOLVED_SIGNED is begin if (S'length < 1) then assert NO_WARNING report "NUMERIC_STD.TO_01: null detected, returning NAS" severity warning; return NAS; end if; return UNRESOLVED_SIGNED(TO_01(STD_ULOGIC_VECTOR(S), XMAP)); end function TO_01; -- Id: T.3 function TO_X01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.4 function TO_X01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01(STD_ULOGIC_VECTOR(S))); end function TO_X01; -- Id: T.5 function TO_X01Z (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.6 function TO_X01Z (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_X01Z(STD_ULOGIC_VECTOR(S))); end function TO_X01Z; -- Id: T.7 function TO_UX01 (S : UNRESOLVED_UNSIGNED) return UNRESOLVED_UNSIGNED is begin return UNRESOLVED_UNSIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.8 function TO_UX01 (S : UNRESOLVED_SIGNED) return UNRESOLVED_SIGNED is begin return UNRESOLVED_SIGNED(TO_UX01(STD_ULOGIC_VECTOR(S))); end function TO_UX01; -- Id: T.9 function IS_X (S : UNRESOLVED_UNSIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- Id: T.10 function IS_X (S : UNRESOLVED_SIGNED) return BOOLEAN is begin return IS_X(STD_ULOGIC_VECTOR(S)); end function IS_X; -- ============================================================================ -- string conversion and write operations -- ============================================================================ function to_ostring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_ostring(STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_ostring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+2)/3; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*3 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_ostring(pad & STD_ULOGIC_VECTOR (value)); end function to_ostring; function to_hstring (value : UNRESOLVED_UNSIGNED) return STRING is begin return to_hstring(STD_ULOGIC_VECTOR (value)); end function to_hstring; function to_hstring (value : UNRESOLVED_SIGNED) return STRING is constant result_length : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(1 to (result_length*4 - value'length)) := (others => value (value'left)); -- Extend sign bit begin return to_hstring(pad & STD_ULOGIC_VECTOR (value)); end function to_hstring; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := SIGNED(ivalue); end procedure READ; procedure READ (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin READ (L => L, VALUE => ivalue); VALUE := SIGNED (ivalue); end procedure READ; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure WRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); WRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure WRITE; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); -- Bail out if there was a bad read if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin OREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure OREAD; procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+2)/3; constant pad : INTEGER := ne*3 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin OREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.OREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure OREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED; GOOD : out BOOLEAN) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue, GOOD => GOOD); VALUE := UNSIGNED(ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED; GOOD : out BOOLEAN) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable ok : BOOLEAN; variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue, -- Read padded STRING GOOD => ok); if not ok then GOOD := false; return; end if; expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then GOOD := false; else GOOD := true; VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_UNSIGNED) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin HREAD (L => L, VALUE => ivalue); VALUE := UNSIGNED (ivalue); end procedure HREAD; procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_SIGNED) is constant ne : INTEGER := (value'length+3)/4; constant pad : INTEGER := ne*4 - value'length; variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1); variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1); begin HREAD (L => L, VALUE => ivalue); -- Read padded string expected_padding := (others => ivalue(pad)); if ivalue(0 to pad-1) /= expected_padding then assert false report "NUMERIC_STD.HREAD Error: Signed vector truncated" severity error; else VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high)); end if; end procedure HREAD; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure OWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is constant ne : INTEGER := (VALUE'length+2)/3; constant pad : STD_ULOGIC_VECTOR(0 to (ne*3 - VALUE'length) - 1) := (others => VALUE (VALUE'left)); variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); OWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure OWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_UNSIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; procedure HWRITE (L : inout LINE; VALUE : in UNRESOLVED_SIGNED; JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is variable ivalue : STD_ULOGIC_VECTOR(value'range); constant ne : INTEGER := (value'length+3)/4; constant pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1) := (others => VALUE(VALUE'left)); begin ivalue := STD_ULOGIC_VECTOR (VALUE); HWRITE (L => L, VALUE => pad & ivalue, JUSTIFIED => JUSTIFIED, FIELD => FIELD); end procedure HWRITE; end package body NUMERIC_STD;
library ieee; use ieee.std_logic_1164.all; entity FA_tb is end FA_tb; architecture tb of FA_tb is component FA is port( A, B, Cin : in std_logic; Sout, Cout : out std_logic); end component; signal A, B, Cin, Sout, Cout : std_logic; begin mapping: FA port map(A, B, Cin, Sout, Cout); --concurrent processes process begin Cin <= '0'; wait for 5 ns; Cin <= '1'; wait for 5 ns; end process; process variable errCnt : integer := 0; begin --TEST 1 A <= '0'; B <= '1'; wait for 10 ns; assert(Sout = '0') report "Sout error 1" severity error; assert(Cout = '1') report "Cout error 1" severity error; if(Sout /= '1' or Cout /= '0') then errCnt := errCnt + 1; end if; --TEST 2 A <= '1'; B <= '1'; wait for 10 ns; assert(Sout = '1') report "Sout error 2" severity error; assert(Cout = '1') report "Cout error 2" severity error; if(Sout /= '0' or Cout /= '1') then errCnt := errCnt + 1; end if; --TEST 3 A <= '1'; B <= '0'; wait for 10 ns; assert(Sout = '0') report "Sout error 3" severity error; assert(Cout = '1') report "Cout error 3" severity error; if(Sout /= '1' or Cout /= '0') then errCnt := errCnt + 1; end if; ---- SoutMARY ---- if(errCnt = 0) then assert false report "Success!" severity note; else assert false report "Faillure!" severity note; end if; end process; end tb; ------------------------------------------------------------- configuration cfg_tb of FA_tb is for tb end for; end cfg_tb; ----------------------------------------------------------END ----------------------------------------------------------END
-- Copyright (c) University of Florida -- -- This file is part of window_gen. -- -- window_gen is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- window_gen is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with window_gen. If not, see <http://www.gnu.org/licenses/>. -- Greg Stitt -- University of Florida -- Description: This entity maintains the FIFO pointers for a -- an array of FIFOs in the window buffer. The front pointer always -- points to the FIFO that stores the top row of window pixels, while the back -- pointer always points to the FIFO with the bottom row. Every time the window -- slides down one row these pointers are updated to ensure correct windows. -- -- This entity tracks the number of times that a current row has been read in -- order to determine when the window has reached the end of a row, which -- determines when the pointers should be updated. The entity also determines -- when the current reads represent the start (left edge_ of a window (is_edge). -- For example, the generator only produces fully immersed windows, so pixels -- towards the end of a will never form the left edge of a window. library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; use work.math_custom.all; ------------------------------------------------------------------------------- -- Generics Description -- PARALLEL_IO : Specifies the number of inputs and outputs provided at a time, -- DATA_WIDTH : The width in bits of each element. -- MAX_WINDOW_ROWS : The maximum number of rows in a generated window -- MAX_IMAGE_COLS : The maximum number of cols in an input image/stream -- MAX_BUFFER_SIZE : The maximum size/words of each FIFO ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Port Descriptions (all control signals are active high) -- clk: clock -- rst: asynchronous reset -- en : '1' to enable -- edge : pointer to a FIFO -- changed : asserted when the edge changes -- is_window_edge : '1' if the current pointer value is the edge of a window. -- One bit for each PARALLEL_IO element, which the first at -- the MSB and the last at the LSB. -- buffer_size : The actual size of the FIFO buffers -- window_per_row : The number of windows generated from each image row ------------------------------------------------------------------------------- entity wg_fifo_edge_control is generic ( PARALLEL_IO : positive; MAX_BUFFER_SIZE : positive; MAX_WINDOW_ROWS : positive; MAX_IMAGE_COLS : positive); port ( clk : in std_logic; rst : in std_logic; en : in std_logic; edge : out unsigned(bitsNeeded(MAX_WINDOW_ROWS-1)-1 downto 0); changed : out std_logic; is_window_edge : out std_logic_vector(PARALLEL_IO-1 downto 0); buffer_size : in std_logic_vector(bitsNeeded(MAX_BUFFER_SIZE)-1 downto 0); windows_per_row : in std_logic_vector(bitsNeeded(MAX_IMAGE_COLS)-1 downto 0)); end wg_fifo_edge_control; architecture BHV of wg_fifo_edge_control is signal count, next_count : integer range 0 to MAX_BUFFER_SIZE; signal addr, next_addr : unsigned(bitsNeeded(MAX_WINDOW_ROWS-1)-1 downto 0); begin -- registers process(clk, rst) begin if (rst = '1') then count <= 0; addr <= (others => '0'); elsif (clk = '1' and clk'event) then count <= next_count; addr <= next_addr; end if; end process; -- combinational logic process(en, count, addr, buffer_size) variable temp_count : integer range 0 to MAX_BUFFER_SIZE; begin -- count inputs if (en = '1') then temp_count := count + 1; else temp_count := count; end if; -- if at the end of a row, update the edge to point to a new fifo if (temp_count >= unsigned(buffer_size)) then -- addr passes last FIFO, reset to first FIFO, otherwise increment addr if (addr = MAX_WINDOW_ROWS-1) then next_addr <= (others => '0'); else next_addr <= addr + 1; end if; -- edge changes anytime an entire row has been read changed <= '1'; --temp_count := (others => '0'); temp_count := 0; else -- if still processing a row, don't change anything changed <= '0'; next_addr <= addr; end if; next_count <= temp_count; end process; -- determine if the next PARALLEL_IO elements are the leftmost edge of a -- generated window process(count, windows_per_row) begin for i in 0 to PARALLEL_IO-1 loop -- each count value corresponds to PARALLEL_IO elements if (count*PARALLEL_IO+i < unsigned(windows_per_row)) then is_window_edge(PARALLEL_IO-1-i) <= '1'; else is_window_edge(PARALLEL_IO-1-i) <= '0'; end if; end loop; end process; edge <= addr; end BHV;
library verilog; use verilog.vl_types.all; entity \block\ is generic( Block_X_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); Block_X_Max : vl_logic_vector(9 downto 0) := (Hi1, Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1, Hi1); Block_Y_Min : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0); Block_Y_Max : vl_logic_vector(9 downto 0) := (Hi0, Hi1, Hi1, Hi1, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1); Block_X_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1); Block_Y_Step : vl_logic_vector(9 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1) ); port( Reset : in vl_logic; frame_clk : in vl_logic; Block_X_Center : in vl_logic_vector(9 downto 0); BlockX : out vl_logic_vector(9 downto 0); BlockY : out vl_logic_vector(9 downto 0); BlockS : out vl_logic_vector(9 downto 0) ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of Block_X_Min : constant is 2; attribute mti_svvh_generic_type of Block_X_Max : constant is 2; attribute mti_svvh_generic_type of Block_Y_Min : constant is 2; attribute mti_svvh_generic_type of Block_Y_Max : constant is 2; attribute mti_svvh_generic_type of Block_X_Step : constant is 2; attribute mti_svvh_generic_type of Block_Y_Step : constant is 2; end \block\;
-------------------------------------------------------------------------------- -- Designer: Paolo Fulgoni <pfulgoni@opencores.org> -- -- Create Date: 02/19/2008 -- Last Update: 04/02/2008 -- Project Name: camellia-vhdl -- Description: VHDL Test Bench for module camellia -- -- Copyright (C) 2008 Paolo Fulgoni -- This file is part of camellia-vhdl. -- camellia-vhdl is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- camellia-vhdl is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- The Camellia cipher algorithm is 128 bit cipher developed by NTT and -- Mitsubishi Electric researchers. -- http://info.isl.ntt.co.jp/crypt/eng/camellia/ -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity camellia_tb is end camellia_tb; architecture RTL of camellia_tb is component camellia is port ( clk : in STD_LOGIC; reset : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (0 to 127); enc_dec : in STD_LOGIC; data_rdy : in STD_LOGIC; data_acq : out STD_LOGIC; key : in STD_LOGIC_VECTOR (0 to 255); k_len : in STD_LOGIC_VECTOR (0 to 1); key_rdy : in STD_LOGIC; key_acq : out STD_LOGIC; data_out : out STD_LOGIC_VECTOR (0 to 127); output_rdy : out STD_LOGIC ); end component; signal clk : STD_LOGIC; signal reset : STD_LOGIC; signal data_in : STD_LOGIC_VECTOR (0 to 127); signal enc_dec : STD_LOGIC; signal data_rdy : STD_LOGIC; signal data_acq : STD_LOGIC; signal key : STD_LOGIC_VECTOR (0 to 255); signal k_len : STD_LOGIC_VECTOR (0 to 1); signal key_rdy : STD_LOGIC; signal key_acq : STD_LOGIC; signal data_out : STD_LOGIC_VECTOR (0 to 127); signal output_rdy : STD_LOGIC; -- constants constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00"; constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01"; constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10"; constant ENC : STD_LOGIC := '0'; constant DEC : STD_LOGIC := '1'; constant CLK_PERIOD : TIME := 100 ns; begin uut : camellia port map(clk, reset, data_in, enc_dec, data_rdy, data_acq, key, k_len, key_rdy, key_acq, data_out, output_rdy); tb : process begin reset <= '1'; wait for 80 ns; reset <= '0'; wait until clk = '1'; data_in <= X"0123456789abcdeffedcba9876543210"; enc_dec <= ENC; data_rdy <= '1'; key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff"; k_len <= KLEN_128; key_rdy <= '1'; wait until key_acq = '1'; key_rdy <= '0'; wait until data_acq = '1'; data_in <= X"67673138549669730857065648eabe43"; enc_dec <= DEC; wait until data_acq = '1'; data_in <= X"0123456789abcdeffedcba9876543210"; enc_dec <= ENC; data_rdy <= '1'; key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff"; k_len <= KLEN_192; key_rdy <= '1'; wait until key_acq = '1'; key_rdy <= '0'; wait until data_acq = '1'; data_rdy <= '0'; wait; end process; clk_gen : process begin clk <= '0'; wait for CLK_PERIOD / 2; clk <= '1'; wait for CLK_PERIOD / 2; end process; end RTL;
library ieee; use ieee.std_logic_1164.all; entity ALU_x16 is port ( opcode : IN STD_LOGIC_VECTOR(3 downto 0); negate : IN STD_LOGIC; input_A, input_B : IN STD_LOGIC_VECTOR(15 downto 0); output, overflowMultDiv : OUT STD_LOGIC_VECTOR(15 downto 0) ); end ALU_x16; architecture skeleton of ALU_x16 is component Multiplexer_4x16 is Port ( Selector : in STD_LOGIC_VECTOR (3 downto 0); input_A, input_B, input_C, input_D, input_E, input_F, input_G, input_H: in STD_LOGIC_VECTOR (15 downto 0); input_I, input_J, input_K, input_L, input_M, input_N, input_O, input_P: in STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; component Adder_2x16 is port ( isSubtraction: in STD_LOGIC; input_A, input_B: in STD_LOGIC_VECTOR(15 DOWNTO 0); carry_out: out STD_LOGIC; output: out STD_LOGIC_VECTOR(15 DOWNTO 0)); end component; component ArithmeticalRightShifter_x16 is Port ( input : STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; component LogicalRightShifter_x16 is Port ( input : STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; component ArithmeticalLogicalLeftShifter_x16 is Port ( input : STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; component ArithmeticalComparator_x16 is Port ( opcodeComp : STD_LOGIC_VECTOR(2 downto 0); input_A, input_B : STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; component Multiplier_2x16 is Port ( input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0); outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0); carryOut : out STD_LOGIC); end component; component Divider_2x16 is Port ( input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0); outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0); carryOut : out STD_LOGIC); end component; component LogicalAND_2x16 is Port ( input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; component LogicalOR_2x16 is Port ( input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; component LogicalXOR_2x16 is Port ( input_A, input_B: in STD_LOGIC_VECTOR (15 downto 0); output : out STD_LOGIC_VECTOR (15 downto 0)); end component; signal output1, output2, output3, output4, output5, output6 : STD_LOGIC_VECTOR(15 DOWNTO 0); signal output7, outputComparator : STD_LOGIC_VECTOR(15 DOWNTO 0); signal output14, output15, output0, outputand, outputor, outputxor : STD_LOGIC_VECTOR(15 DOWNTO 0); signal carryoutMul, carryoutDiv, carryoutAddSub : STD_LOGIC; signal overMult, overDiv : STD_LOGIC_VECTOR(15 downto 0); begin -- 0000 -- 12 -- Soma e Subtração P0: Adder_2x16 port map(negate, input_A, input_B, carryoutAddSub, output0); -- 0001 -- Retorna o segundo valor output1 <= input_B; P2: LogicalAND_2x16 port map(input_A, input_B, outputand); P3: LogicalOR_2x16 port map(input_A, input_B, outputor); P4: LogicalXOR_2x16 port map(input_A, input_B, outputxor); process(input_A, input_B) begin if(negate = '0') then -- 0010 -- 1 -- And output2 <= outputand; -- 0011 -- 1 -- Or output3 <= outputor; -- 0100 -- 1 -- Xor output4 <= outputxor; else -- 0010 -- 1 -- Nand output2 <= not outputand; -- 0011 -- 1 -- Nor output3 <= not outputor; -- 0100 -- 1 -- Xnor output4 <= not outputxor; end if; if(opcode(0) = '0') then overflowMultDiv <= overMult; else overflowMultDiv <= overDiv; end if; end process; -- 0101 -- Shift aritmetico para direita P5: ArithmeticalRightShifter_x16 port map(input_A, output5); -- 0110 -- Shift logico para direita P6: LogicalRightShifter_x16 port map(input_A, output6); -- 0111 -- Shift aritmetico e logico para esquerda P7: ArithmeticalLogicalLeftShifter_x16 port map(input_A, output7); -- 1000 -- Comparadores P8: ArithmeticalComparator_x16 port map(opcode(2 downto 0), input_A, input_B, outputComparator); -- 1110 -- 12 -- Multiplicação p14: Multiplier_2x16 port map(input_A, input_B, output14, overMult, carryoutMul); -- 1111 -- 12 -- Divisão p15: Divider_2x16 port map(input_A, input_B, output15, overDiv, carryoutDiv); Poutput: Multiplexer_4x16 port map (opcode, output0, output1, output2, output3, output4, output5, output6, output7, outputComparator, outputComparator, outputComparator, outputComparator, outputComparator, outputComparator, output14, output15, output); end skeleton;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc433.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY model IS PORT ( F1: OUT integer := 3; F2: INOUT integer := 3; F3: IN integer ); END model; architecture model of model is begin process begin wait for 1 ns; assert F3= 3 report"wrong initialization of F3 through type conversion" severity failure; assert F2 = 3 report"wrong initialization of F2 through type conversion" severity failure; wait; end process; end; ENTITY c03s02b01x01p19n01i00433ent IS END c03s02b01x01p19n01i00433ent; ARCHITECTURE c03s02b01x01p19n01i00433arch OF c03s02b01x01p19n01i00433ent IS type column is range 1 to 2; type row is range 1 to 8; type s2integer_cons_vector is array (row,column) of integer; constant C1 : s2integer_cons_vector := (others => (others => 3)); function complex_scalar(s : s2integer_cons_vector) return integer is begin return 3; end complex_scalar; function scalar_complex(s : integer) return s2integer_cons_vector is begin return C1; end scalar_complex; component model1 PORT ( F1: OUT integer; F2: INOUT integer; F3: IN integer ); end component; for T1 : model1 use entity work.model(model); signal S1 : s2integer_cons_vector; signal S2 : s2integer_cons_vector; signal S3 : s2integer_cons_vector := C1; BEGIN T1: model1 port map ( scalar_complex(F1) => S1, scalar_complex(F2) => complex_scalar(S2), F3 => complex_scalar(S3) ); TESTING: PROCESS BEGIN wait for 1 ns; assert NOT((S1 = C1) and (S2 = C1)) report "***PASSED TEST: c03s02b01x01p19n01i00433" severity NOTE; assert ((S1 = C1) and (S2 = C1)) report "***FAILED TEST: c03s02b01x01p19n01i00433 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p19n01i00433arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc433.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY model IS PORT ( F1: OUT integer := 3; F2: INOUT integer := 3; F3: IN integer ); END model; architecture model of model is begin process begin wait for 1 ns; assert F3= 3 report"wrong initialization of F3 through type conversion" severity failure; assert F2 = 3 report"wrong initialization of F2 through type conversion" severity failure; wait; end process; end; ENTITY c03s02b01x01p19n01i00433ent IS END c03s02b01x01p19n01i00433ent; ARCHITECTURE c03s02b01x01p19n01i00433arch OF c03s02b01x01p19n01i00433ent IS type column is range 1 to 2; type row is range 1 to 8; type s2integer_cons_vector is array (row,column) of integer; constant C1 : s2integer_cons_vector := (others => (others => 3)); function complex_scalar(s : s2integer_cons_vector) return integer is begin return 3; end complex_scalar; function scalar_complex(s : integer) return s2integer_cons_vector is begin return C1; end scalar_complex; component model1 PORT ( F1: OUT integer; F2: INOUT integer; F3: IN integer ); end component; for T1 : model1 use entity work.model(model); signal S1 : s2integer_cons_vector; signal S2 : s2integer_cons_vector; signal S3 : s2integer_cons_vector := C1; BEGIN T1: model1 port map ( scalar_complex(F1) => S1, scalar_complex(F2) => complex_scalar(S2), F3 => complex_scalar(S3) ); TESTING: PROCESS BEGIN wait for 1 ns; assert NOT((S1 = C1) and (S2 = C1)) report "***PASSED TEST: c03s02b01x01p19n01i00433" severity NOTE; assert ((S1 = C1) and (S2 = C1)) report "***FAILED TEST: c03s02b01x01p19n01i00433 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p19n01i00433arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc433.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY model IS PORT ( F1: OUT integer := 3; F2: INOUT integer := 3; F3: IN integer ); END model; architecture model of model is begin process begin wait for 1 ns; assert F3= 3 report"wrong initialization of F3 through type conversion" severity failure; assert F2 = 3 report"wrong initialization of F2 through type conversion" severity failure; wait; end process; end; ENTITY c03s02b01x01p19n01i00433ent IS END c03s02b01x01p19n01i00433ent; ARCHITECTURE c03s02b01x01p19n01i00433arch OF c03s02b01x01p19n01i00433ent IS type column is range 1 to 2; type row is range 1 to 8; type s2integer_cons_vector is array (row,column) of integer; constant C1 : s2integer_cons_vector := (others => (others => 3)); function complex_scalar(s : s2integer_cons_vector) return integer is begin return 3; end complex_scalar; function scalar_complex(s : integer) return s2integer_cons_vector is begin return C1; end scalar_complex; component model1 PORT ( F1: OUT integer; F2: INOUT integer; F3: IN integer ); end component; for T1 : model1 use entity work.model(model); signal S1 : s2integer_cons_vector; signal S2 : s2integer_cons_vector; signal S3 : s2integer_cons_vector := C1; BEGIN T1: model1 port map ( scalar_complex(F1) => S1, scalar_complex(F2) => complex_scalar(S2), F3 => complex_scalar(S3) ); TESTING: PROCESS BEGIN wait for 1 ns; assert NOT((S1 = C1) and (S2 = C1)) report "***PASSED TEST: c03s02b01x01p19n01i00433" severity NOTE; assert ((S1 = C1) and (S2 = C1)) report "***FAILED TEST: c03s02b01x01p19n01i00433 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p19n01i00433arch;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_t_e -- -- Generated -- by: wig -- on: Mon Mar 5 13:21:41 2007 -- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Calculate -nodelta ../../macro.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_t_e-e.vhd,v 1.1 2007/03/05 13:22:43 wig Exp $ -- $Date: 2007/03/05 13:22:43 $ -- $Log: inst_t_e-e.vhd,v $ -- Revision 1.1 2007/03/05 13:22:43 wig -- Added testcase for selection of macros with ::variant switch -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.47 , wilfried.gaensheimer@micronas.com -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_t_e -- entity inst_t_e is -- Generics: -- No Generated Generics for Entity inst_t_e -- Generated Port Declaration: port( -- Generated Port for Entity inst_t_e macro_sig1_k1_k2 : in std_ulogic_vector(3 downto 0); macro_sig1_k1_k4 : in std_ulogic_vector(3 downto 0); macro_sig1_k3_k2 : in std_ulogic_vector(3 downto 0); macro_sig1_k3_k4 : in std_ulogic_vector(3 downto 0); macro_sig2_k1_k2 : in std_ulogic_vector(3 downto 0); macro_sig2_k1_k4 : in std_ulogic_vector(3 downto 0); macro_sig2_k3_k2 : in std_ulogic_vector(3 downto 0); macro_sig2_k3_k4 : in std_ulogic_vector(3 downto 0); macro_sig4_k1_k2 : out std_ulogic_vector(6 downto 0); macro_sig4_k1_k4 : out std_ulogic_vector(6 downto 0); macro_sig4_k3_k2 : out std_ulogic_vector(6 downto 0); macro_sig4_k3_k4 : out std_ulogic_vector(6 downto 0); macro_sign_0 : in std_ulogic_vector(3 downto 0); macro_sign_1 : in std_ulogic_vector(3 downto 0); macro_sign_2 : in std_ulogic_vector(3 downto 0); macro_sign_3 : in std_ulogic_vector(3 downto 0) -- End of Generated Port for Entity inst_t_e ); end inst_t_e; -- -- End of Generated Entity inst_t_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Ijw7mPXRT1pNoLg2oZU/N1EGzVifLbU9Cdn5uq+lr5L4PRcM4ABxEl30L70XZTF9k00TvnkF/u2d Zt7NqyvlCw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EnBPR1CJ+sKXHJQOWPpfUePtXRmoggIjQ+IqYHROTJFHS4eUt1oER1RJukmaXVw7jLTuRUPrPLhu GY8TCXkJ3zcT1Fa9G8LSDdU30Dz5CZVYWTf4ovjsihy77YiML1+pjuOPzvLe6MRIa9zPGvKkO7Tk /cwFVpYlJSoUy1a2eT4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Ijw7mPXRT1pNoLg2oZU/N1EGzVifLbU9Cdn5uq+lr5L4PRcM4ABxEl30L70XZTF9k00TvnkF/u2d Zt7NqyvlCw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EnBPR1CJ+sKXHJQOWPpfUePtXRmoggIjQ+IqYHROTJFHS4eUt1oER1RJukmaXVw7jLTuRUPrPLhu GY8TCXkJ3zcT1Fa9G8LSDdU30Dz5CZVYWTf4ovjsihy77YiML1+pjuOPzvLe6MRIa9zPGvKkO7Tk /cwFVpYlJSoUy1a2eT4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Ijw7mPXRT1pNoLg2oZU/N1EGzVifLbU9Cdn5uq+lr5L4PRcM4ABxEl30L70XZTF9k00TvnkF/u2d Zt7NqyvlCw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EnBPR1CJ+sKXHJQOWPpfUePtXRmoggIjQ+IqYHROTJFHS4eUt1oER1RJukmaXVw7jLTuRUPrPLhu GY8TCXkJ3zcT1Fa9G8LSDdU30Dz5CZVYWTf4ovjsihy77YiML1+pjuOPzvLe6MRIa9zPGvKkO7Tk /cwFVpYlJSoUy1a2eT4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc52.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c04s03b01x01p04n01i00052pkg is constant test: integer; end c04s03b01x01p04n01i00052pkg; package body c04s03b01x01p04n01i00052pkg is constant test, test2: integer := 10; -- No_failure_here end c04s03b01x01p04n01i00052pkg; use work.c04s03b01x01p04n01i00052pkg.all; ENTITY c04s03b01x01p04n01i00052ent IS END c04s03b01x01p04n01i00052ent; ARCHITECTURE c04s03b01x01p04n01i00052arch OF c04s03b01x01p04n01i00052ent IS BEGIN TESTING: PROCESS BEGIN assert NOT( test = 10 ) report "***PASSED TEST: c04s03b01x01p04n01i00052" severity NOTE; assert ( test = 10 ) report "***FAILED TEST: c04s03b01x01p04n01i00052 - A deferred constant declaration appear in a package declaration test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x01p04n01i00052arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc52.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c04s03b01x01p04n01i00052pkg is constant test: integer; end c04s03b01x01p04n01i00052pkg; package body c04s03b01x01p04n01i00052pkg is constant test, test2: integer := 10; -- No_failure_here end c04s03b01x01p04n01i00052pkg; use work.c04s03b01x01p04n01i00052pkg.all; ENTITY c04s03b01x01p04n01i00052ent IS END c04s03b01x01p04n01i00052ent; ARCHITECTURE c04s03b01x01p04n01i00052arch OF c04s03b01x01p04n01i00052ent IS BEGIN TESTING: PROCESS BEGIN assert NOT( test = 10 ) report "***PASSED TEST: c04s03b01x01p04n01i00052" severity NOTE; assert ( test = 10 ) report "***FAILED TEST: c04s03b01x01p04n01i00052 - A deferred constant declaration appear in a package declaration test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x01p04n01i00052arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc52.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- package c04s03b01x01p04n01i00052pkg is constant test: integer; end c04s03b01x01p04n01i00052pkg; package body c04s03b01x01p04n01i00052pkg is constant test, test2: integer := 10; -- No_failure_here end c04s03b01x01p04n01i00052pkg; use work.c04s03b01x01p04n01i00052pkg.all; ENTITY c04s03b01x01p04n01i00052ent IS END c04s03b01x01p04n01i00052ent; ARCHITECTURE c04s03b01x01p04n01i00052arch OF c04s03b01x01p04n01i00052ent IS BEGIN TESTING: PROCESS BEGIN assert NOT( test = 10 ) report "***PASSED TEST: c04s03b01x01p04n01i00052" severity NOTE; assert ( test = 10 ) report "***FAILED TEST: c04s03b01x01p04n01i00052 - A deferred constant declaration appear in a package declaration test failed." severity ERROR; wait; END PROCESS TESTING; END c04s03b01x01p04n01i00052arch;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:28:56 07/06/2014 -- Design Name: -- Module Name: wishbone_led_matrix_ctrl - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -- This controller is based on Glen Atkins work (http://bikerglen.com/projects/lighting/led-panel-1up/) -- Minor modification on controller behavior to adapt to wishbone bus -- Major modification on coding style to meet XST guidelines ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; library work; use work.logi_utils_pack.all ; use work.control_pack.all ; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity wishbone_led_matrix_ctrl is generic(wb_size : positive := 16; clk_div : positive := 10; -- TODO: nb_panels is untested, still need to be validated nb_panels : positive := 1 ; bits_per_color : INTEGER RANGE 1 TO 4 := 4 ; expose_step_cycle : positive := 1910 ); port( -- Syscon signals gls_reset : in std_logic ; gls_clk : in std_logic ; -- Wishbone signals wbs_address : in std_logic_vector(15 downto 0) ; wbs_writedata : in std_logic_vector( wb_size-1 downto 0); wbs_readdata : out std_logic_vector( wb_size-1 downto 0); wbs_strobe : in std_logic ; wbs_cycle : in std_logic ; wbs_write : in std_logic ; wbs_ack : out std_logic; SCLK_OUT : out std_logic ; BLANK_OUT : out std_logic ; LATCH_OUT : out std_logic ; A_OUT : out std_logic_vector(3 downto 0); R_out : out std_logic_vector(1 downto 0); G_out : out std_logic_vector(1 downto 0); B_out : out std_logic_vector(1 downto 0) ); end wishbone_led_matrix_ctrl; architecture Behavioral of wishbone_led_matrix_ctrl is signal read_ack : std_logic ; signal write_ack, write_pixel: std_logic ; signal pixel_addr : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0); begin -- wishbone related logic wbs_ack <= read_ack or write_ack; write_bloc : process(gls_clk,gls_reset) begin if gls_reset = '1' then write_ack <= '0'; elsif rising_edge(gls_clk) then if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then write_ack <= '1'; else write_ack <= '0'; end if; end if; end process write_bloc; read_bloc : process(gls_clk, gls_reset) begin if gls_reset = '1' then elsif rising_edge(gls_clk) then if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then read_ack <= '1'; else read_ack <= '0'; end if; end if; end process read_bloc; -- ram buffer instanciation write_pixel <= wbs_strobe and wbs_write and wbs_cycle ; pixel_addr <= wbs_address(pixel_addr'high downto 0); matrix_ctrl0 : rgb_32_32_matrix_ctrl generic map( clk_div => clk_div, nb_panels => nb_panels, expose_step_cycle => expose_step_cycle, bits_per_color => bits_per_color ) port map( clk => gls_clk, reset => gls_reset, pixel_addr => pixel_addr, pixel_value_in => wbs_writedata((bits_per_color*3)-1 downto 0), pixel_value_out => wbs_readdata((bits_per_color*3)-1 downto 0), write_pixel => write_pixel, SCLK_OUT => SCLK_OUT, BLANK_OUT => BLANK_OUT, LATCH_OUT => LATCH_OUT, A_OUT => A_OUT, R_out => R_OUT, G_out => G_OUT, B_out => B_OUT ); wbs_readdata (15 downto (bits_per_color*3)) <= (others => '0'); end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:28:56 07/06/2014 -- Design Name: -- Module Name: wishbone_led_matrix_ctrl - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -- This controller is based on Glen Atkins work (http://bikerglen.com/projects/lighting/led-panel-1up/) -- Minor modification on controller behavior to adapt to wishbone bus -- Major modification on coding style to meet XST guidelines ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; library work; use work.logi_utils_pack.all ; use work.control_pack.all ; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity wishbone_led_matrix_ctrl is generic(wb_size : positive := 16; clk_div : positive := 10; -- TODO: nb_panels is untested, still need to be validated nb_panels : positive := 1 ; bits_per_color : INTEGER RANGE 1 TO 4 := 4 ; expose_step_cycle : positive := 1910 ); port( -- Syscon signals gls_reset : in std_logic ; gls_clk : in std_logic ; -- Wishbone signals wbs_address : in std_logic_vector(15 downto 0) ; wbs_writedata : in std_logic_vector( wb_size-1 downto 0); wbs_readdata : out std_logic_vector( wb_size-1 downto 0); wbs_strobe : in std_logic ; wbs_cycle : in std_logic ; wbs_write : in std_logic ; wbs_ack : out std_logic; SCLK_OUT : out std_logic ; BLANK_OUT : out std_logic ; LATCH_OUT : out std_logic ; A_OUT : out std_logic_vector(3 downto 0); R_out : out std_logic_vector(1 downto 0); G_out : out std_logic_vector(1 downto 0); B_out : out std_logic_vector(1 downto 0) ); end wishbone_led_matrix_ctrl; architecture Behavioral of wishbone_led_matrix_ctrl is signal read_ack : std_logic ; signal write_ack, write_pixel: std_logic ; signal pixel_addr : std_logic_vector((nbit(32*32*nb_panels))-1 downto 0); begin -- wishbone related logic wbs_ack <= read_ack or write_ack; write_bloc : process(gls_clk,gls_reset) begin if gls_reset = '1' then write_ack <= '0'; elsif rising_edge(gls_clk) then if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then write_ack <= '1'; else write_ack <= '0'; end if; end if; end process write_bloc; read_bloc : process(gls_clk, gls_reset) begin if gls_reset = '1' then elsif rising_edge(gls_clk) then if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then read_ack <= '1'; else read_ack <= '0'; end if; end if; end process read_bloc; -- ram buffer instanciation write_pixel <= wbs_strobe and wbs_write and wbs_cycle ; pixel_addr <= wbs_address(pixel_addr'high downto 0); matrix_ctrl0 : rgb_32_32_matrix_ctrl generic map( clk_div => clk_div, nb_panels => nb_panels, expose_step_cycle => expose_step_cycle, bits_per_color => bits_per_color ) port map( clk => gls_clk, reset => gls_reset, pixel_addr => pixel_addr, pixel_value_in => wbs_writedata((bits_per_color*3)-1 downto 0), pixel_value_out => wbs_readdata((bits_per_color*3)-1 downto 0), write_pixel => write_pixel, SCLK_OUT => SCLK_OUT, BLANK_OUT => BLANK_OUT, LATCH_OUT => LATCH_OUT, A_OUT => A_OUT, R_out => R_OUT, G_out => G_OUT, B_out => B_OUT ); wbs_readdata (15 downto (bits_per_color*3)) <= (others => '0'); end Behavioral;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Mon Feb 27 15:47:58 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -- c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0/system_clk_wiz_0_0_stub.vhdl -- Design : system_clk_wiz_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity system_clk_wiz_0_0 is Port ( clk_out1 : out STD_LOGIC; resetn : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); end system_clk_wiz_0_0; architecture stub of system_clk_wiz_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "clk_out1,resetn,locked,clk_in1"; begin end;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2051.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p01n01i02051ent IS END c07s02b04x00p01n01i02051ent; ARCHITECTURE c07s02b04x00p01n01i02051arch OF c07s02b04x00p01n01i02051ent IS BEGIN TESTING: PROCESS variable BITSTRV : BIT_VECTOR( 0 to 7 ); BEGIN BITSTRV := BITSTRV + "01010101"; assert FALSE report "***FAILED TEST: c07s02b04x00p01n01i02051 - The adding operators + and - are predefined for any numeric type." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p01n01i02051arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2051.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p01n01i02051ent IS END c07s02b04x00p01n01i02051ent; ARCHITECTURE c07s02b04x00p01n01i02051arch OF c07s02b04x00p01n01i02051ent IS BEGIN TESTING: PROCESS variable BITSTRV : BIT_VECTOR( 0 to 7 ); BEGIN BITSTRV := BITSTRV + "01010101"; assert FALSE report "***FAILED TEST: c07s02b04x00p01n01i02051 - The adding operators + and - are predefined for any numeric type." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p01n01i02051arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2051.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b04x00p01n01i02051ent IS END c07s02b04x00p01n01i02051ent; ARCHITECTURE c07s02b04x00p01n01i02051arch OF c07s02b04x00p01n01i02051ent IS BEGIN TESTING: PROCESS variable BITSTRV : BIT_VECTOR( 0 to 7 ); BEGIN BITSTRV := BITSTRV + "01010101"; assert FALSE report "***FAILED TEST: c07s02b04x00p01n01i02051 - The adding operators + and - are predefined for any numeric type." severity ERROR; wait; END PROCESS TESTING; END c07s02b04x00p01n01i02051arch;
-- This file is not intended for synthesis, is is present so that simulators -- see a complete view of the system. -- You may use the entity declaration from this file as the basis for a -- component declaration in a VHDL file instantiating this entity. library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; entity alt_dspbuilder_delay is generic ( CLOCKPHASE : string := "1"; DELAY : positive := 1; USE_INIT : natural := 0; BITPATTERN : string := "00000001"; WIDTH : positive := 8 ); port ( input : in std_logic_vector(width-1 downto 0) := (others=>'0'); clock : in std_logic := '0'; sclr : in std_logic := '0'; aclr : in std_logic := '0'; output : out std_logic_vector(width-1 downto 0); ena : in std_logic := '0' ); end entity alt_dspbuilder_delay; architecture rtl of alt_dspbuilder_delay is component alt_dspbuilder_delay_GNHYCSAEGT is generic ( CLOCKPHASE : string := "1"; DELAY : positive := 1; USE_INIT : natural := 0; BITPATTERN : string := "0"; WIDTH : positive := 1 ); port ( aclr : in std_logic := '0'; clock : in std_logic := '0'; ena : in std_logic := '0'; input : in std_logic_vector(1-1 downto 0) := (others=>'0'); output : out std_logic_vector(1-1 downto 0); sclr : in std_logic := '0' ); end component alt_dspbuilder_delay_GNHYCSAEGT; component alt_dspbuilder_delay_GNUECIBFDH is generic ( CLOCKPHASE : string := "1"; DELAY : positive := 1; USE_INIT : natural := 1; BITPATTERN : string := "0"; WIDTH : positive := 1 ); port ( aclr : in std_logic := '0'; clock : in std_logic := '0'; ena : in std_logic := '0'; input : in std_logic_vector(1-1 downto 0) := (others=>'0'); output : out std_logic_vector(1-1 downto 0); sclr : in std_logic := '0' ); end component alt_dspbuilder_delay_GNUECIBFDH; component alt_dspbuilder_delay_GNVCBR7UZP is generic ( CLOCKPHASE : string := "1"; DELAY : positive := 1; USE_INIT : natural := 0; BITPATTERN : string := "000000000001"; WIDTH : positive := 12 ); port ( aclr : in std_logic := '0'; clock : in std_logic := '0'; ena : in std_logic := '0'; input : in std_logic_vector(12-1 downto 0) := (others=>'0'); output : out std_logic_vector(12-1 downto 0); sclr : in std_logic := '0' ); end component alt_dspbuilder_delay_GNVCBR7UZP; component alt_dspbuilder_delay_GNGQ56ZS4N is generic ( CLOCKPHASE : string := "1"; DELAY : positive := 1; USE_INIT : natural := 0; BITPATTERN : string := "1"; WIDTH : positive := 1 ); port ( aclr : in std_logic := '0'; clock : in std_logic := '0'; ena : in std_logic := '0'; input : in std_logic_vector(1-1 downto 0) := (others=>'0'); output : out std_logic_vector(1-1 downto 0); sclr : in std_logic := '0' ); end component alt_dspbuilder_delay_GNGQ56ZS4N; component alt_dspbuilder_delay_GNWON5MXYC is generic ( CLOCKPHASE : string := "1"; DELAY : positive := 1; USE_INIT : natural := 1; BITPATTERN : string := "0000000000001010"; WIDTH : positive := 16 ); port ( aclr : in std_logic := '0'; clock : in std_logic := '0'; ena : in std_logic := '0'; input : in std_logic_vector(16-1 downto 0) := (others=>'0'); output : out std_logic_vector(16-1 downto 0); sclr : in std_logic := '0' ); end component alt_dspbuilder_delay_GNWON5MXYC; begin alt_dspbuilder_delay_GNHYCSAEGT_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate inst_alt_dspbuilder_delay_GNHYCSAEGT_0: alt_dspbuilder_delay_GNHYCSAEGT generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1) port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr); end generate; alt_dspbuilder_delay_GNUECIBFDH_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate inst_alt_dspbuilder_delay_GNUECIBFDH_1: alt_dspbuilder_delay_GNUECIBFDH generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1) port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr); end generate; alt_dspbuilder_delay_GNVCBR7UZP_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000001") and (WIDTH = 12)) generate inst_alt_dspbuilder_delay_GNVCBR7UZP_2: alt_dspbuilder_delay_GNVCBR7UZP generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "000000000001", WIDTH => 12) port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr); end generate; alt_dspbuilder_delay_GNGQ56ZS4N_3: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "1") and (WIDTH = 1)) generate inst_alt_dspbuilder_delay_GNGQ56ZS4N_3: alt_dspbuilder_delay_GNGQ56ZS4N generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "1", WIDTH => 1) port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr); end generate; alt_dspbuilder_delay_GNWON5MXYC_4: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0000000000001010") and (WIDTH = 16)) generate inst_alt_dspbuilder_delay_GNWON5MXYC_4: alt_dspbuilder_delay_GNWON5MXYC generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0000000000001010", WIDTH => 16) port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr); end generate; assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "000000000001") and (WIDTH = 12)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "1") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0000000000001010") and (WIDTH = 16))) report "Please run generate again" severity error; end architecture rtl;
entity sub is port ( o1 : out bit; o2 : out real := 0.0; i1 : in bit ); end entity; architecture test of sub is begin p1: process is begin o1 <= '1'; o2 <= 1.0; wait for 1 ns; o1 <= '0'; o2 <= 0.0; assert i1 = '1'; wait; end process; end architecture; ------------------------------------------------------------------------------- entity conv2 is end entity; architecture test of conv2 is type t is (zero, one); signal x : real; signal y : bit; signal z : integer := 0; signal p : real; signal q : real := 0.0; signal r : t; type tmap_t is array (t) of bit; constant tmap : tmap_t := (zero => '0', one => '1'); function table_to_bit(x : t) return bit is begin report "table_to_bit " & t'image(x); return tmap(x); end function; function bit_to_real(b : bit) return real is begin report "bit_to_real " & bit'image(b); if b = '1' then return 1.0; else return 0.0; end if; end function; function real_to_bit(r : real) return bit is begin report "real_to_bit " & real'image(r); if r = 1.0 then return '1'; elsif r = 0.0 then return '0'; else report "invalid real value " & real'image(r) severity failure; end if; end function; function bit_to_int(b : bit) return integer is begin report "bit_to_int " & bit'image(b); if b = '1' then return integer'high; else return integer'low; end if; end function; function real_to_limit(r : real) return real is begin report "real_to_limit " & real'image(r); if r = 1.0 then return real'high; elsif r = 0.0 then return real'low; else report "invalid real value " & real'image(r) severity failure; end if; end function; begin uut1: entity work.sub port map ( bit_to_real(o1) => x, real_to_bit(o2) => y, i1 => real_to_bit(q) ); uut2: entity work.sub port map ( bit_to_int(o1) => z, real_to_limit(o2) => p, i1 => table_to_bit(r) ); p2: process is begin assert x = 0.0; assert y = '0'; assert z = integer'low; assert p = real'low; wait for 0 ns; q <= 1.0; r <= one; assert x = 1.0; assert y = '1'; assert z = integer'high; assert p = real'high; wait for 2 ns; assert x = 0.0; assert y = '0'; assert z = integer'low; assert p = real'low; wait; end process; end architecture;
---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2009 Aeroflex Gaisler ----------------------------------------------------------------------------- -- Entity: ahbrom -- File: ahbrom.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: AHB rom. 0/1-waitstate read ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; entity ahbrom is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; pipe : integer := 0; tech : integer := 0; kbytes : integer := 1); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end; architecture rtl of ahbrom is constant abits : integer := 9; constant bytes : integer := 368; constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); signal romdata : std_logic_vector(31 downto 0); signal addr : std_logic_vector(abits-1 downto 2); signal hsel, hready : std_ulogic; begin ahbso.hresp <= "00"; ahbso.hsplit <= (others => '0'); ahbso.hirq <= (others => '0'); ahbso.hconfig <= hconfig; ahbso.hindex <= hindex; reg : process (clk) begin if rising_edge(clk) then addr <= ahbsi.haddr(abits-1 downto 2); end if; end process; p0 : if pipe = 0 generate ahbso.hrdata <= ahbdrivedata(romdata); ahbso.hready <= '1'; end generate; p1 : if pipe = 1 generate reg2 : process (clk) begin if rising_edge(clk) then hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); hready <= ahbsi.hready; ahbso.hready <= (not rst) or (hsel and hready) or (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); ahbso.hrdata <= ahbdrivedata(romdata); end if; end process; end generate; comb : process (addr) begin case conv_integer(addr) is when 16#00000# => romdata <= X"81D82000"; when 16#00001# => romdata <= X"03000004"; when 16#00002# => romdata <= X"821060E0"; when 16#00003# => romdata <= X"81884000"; when 16#00004# => romdata <= X"81900000"; when 16#00005# => romdata <= X"81980000"; when 16#00006# => romdata <= X"81800000"; when 16#00007# => romdata <= X"01000000"; when 16#00008# => romdata <= X"03002040"; when 16#00009# => romdata <= X"8210600F"; when 16#0000A# => romdata <= X"C2A00040"; when 16#0000B# => romdata <= X"87444000"; when 16#0000C# => romdata <= X"8608E01F"; when 16#0000D# => romdata <= X"88100000"; when 16#0000E# => romdata <= X"8A100000"; when 16#0000F# => romdata <= X"8C100000"; when 16#00010# => romdata <= X"8E100000"; when 16#00011# => romdata <= X"A0100000"; when 16#00012# => romdata <= X"A2100000"; when 16#00013# => romdata <= X"A4100000"; when 16#00014# => romdata <= X"A6100000"; when 16#00015# => romdata <= X"A8100000"; when 16#00016# => romdata <= X"AA100000"; when 16#00017# => romdata <= X"AC100000"; when 16#00018# => romdata <= X"AE100000"; when 16#00019# => romdata <= X"90100000"; when 16#0001A# => romdata <= X"92100000"; when 16#0001B# => romdata <= X"94100000"; when 16#0001C# => romdata <= X"96100000"; when 16#0001D# => romdata <= X"98100000"; when 16#0001E# => romdata <= X"9A100000"; when 16#0001F# => romdata <= X"9C100000"; when 16#00020# => romdata <= X"9E100000"; when 16#00021# => romdata <= X"86A0E001"; when 16#00022# => romdata <= X"16BFFFEF"; when 16#00023# => romdata <= X"81E00000"; when 16#00024# => romdata <= X"82102002"; when 16#00025# => romdata <= X"81904000"; when 16#00026# => romdata <= X"03000004"; when 16#00027# => romdata <= X"821060E0"; when 16#00028# => romdata <= X"81884000"; when 16#00029# => romdata <= X"01000000"; when 16#0002A# => romdata <= X"01000000"; when 16#0002B# => romdata <= X"01000000"; when 16#0002C# => romdata <= X"83480000"; when 16#0002D# => romdata <= X"8330600C"; when 16#0002E# => romdata <= X"80886001"; when 16#0002F# => romdata <= X"02800019"; when 16#00030# => romdata <= X"01000000"; when 16#00031# => romdata <= X"07000000"; when 16#00032# => romdata <= X"8610E118"; when 16#00033# => romdata <= X"C108C000"; when 16#00034# => romdata <= X"C118C000"; when 16#00035# => romdata <= X"C518C000"; when 16#00036# => romdata <= X"C918C000"; when 16#00037# => romdata <= X"CD18E008"; when 16#00038# => romdata <= X"D118C000"; when 16#00039# => romdata <= X"D518C000"; when 16#0003A# => romdata <= X"D918C000"; when 16#0003B# => romdata <= X"DD18C000"; when 16#0003C# => romdata <= X"E118C000"; when 16#0003D# => romdata <= X"E518C000"; when 16#0003E# => romdata <= X"E918C000"; when 16#0003F# => romdata <= X"ED18C000"; when 16#00040# => romdata <= X"F118C000"; when 16#00041# => romdata <= X"F518C000"; when 16#00042# => romdata <= X"F918C000"; when 16#00043# => romdata <= X"10800005"; when 16#00044# => romdata <= X"FD18C000"; when 16#00045# => romdata <= X"01000000"; when 16#00046# => romdata <= X"00000000"; when 16#00047# => romdata <= X"00000000"; when 16#00048# => romdata <= X"05000008"; when 16#00049# => romdata <= X"82100000"; when 16#0004A# => romdata <= X"3D1003FF"; when 16#0004B# => romdata <= X"BC17A3E0"; when 16#0004C# => romdata <= X"BC278001"; when 16#0004D# => romdata <= X"9C27A060"; when 16#0004E# => romdata <= X"03100000"; when 16#0004F# => romdata <= X"81C04000"; when 16#00050# => romdata <= X"01000000"; when 16#00051# => romdata <= X"01000000"; when 16#00052# => romdata <= X"01000000"; when 16#00053# => romdata <= X"01000000"; when 16#00054# => romdata <= X"01000000"; when 16#00055# => romdata <= X"01000000"; when 16#00056# => romdata <= X"01000000"; when 16#00057# => romdata <= X"01000000"; when 16#00058# => romdata <= X"00000000"; when 16#00059# => romdata <= X"00000000"; when 16#0005A# => romdata <= X"00000000"; when 16#0005B# => romdata <= X"00000000"; when 16#0005C# => romdata <= X"00000000"; when others => romdata <= (others => '-'); end case; end process; -- pragma translate_off bootmsg : report_version generic map ("ahbrom" & tost(hindex) & ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); -- pragma translate_on end;
---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2009 Aeroflex Gaisler ----------------------------------------------------------------------------- -- Entity: ahbrom -- File: ahbrom.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: AHB rom. 0/1-waitstate read ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; entity ahbrom is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; pipe : integer := 0; tech : integer := 0; kbytes : integer := 1); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end; architecture rtl of ahbrom is constant abits : integer := 9; constant bytes : integer := 368; constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); signal romdata : std_logic_vector(31 downto 0); signal addr : std_logic_vector(abits-1 downto 2); signal hsel, hready : std_ulogic; begin ahbso.hresp <= "00"; ahbso.hsplit <= (others => '0'); ahbso.hirq <= (others => '0'); ahbso.hconfig <= hconfig; ahbso.hindex <= hindex; reg : process (clk) begin if rising_edge(clk) then addr <= ahbsi.haddr(abits-1 downto 2); end if; end process; p0 : if pipe = 0 generate ahbso.hrdata <= ahbdrivedata(romdata); ahbso.hready <= '1'; end generate; p1 : if pipe = 1 generate reg2 : process (clk) begin if rising_edge(clk) then hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); hready <= ahbsi.hready; ahbso.hready <= (not rst) or (hsel and hready) or (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); ahbso.hrdata <= ahbdrivedata(romdata); end if; end process; end generate; comb : process (addr) begin case conv_integer(addr) is when 16#00000# => romdata <= X"81D82000"; when 16#00001# => romdata <= X"03000004"; when 16#00002# => romdata <= X"821060E0"; when 16#00003# => romdata <= X"81884000"; when 16#00004# => romdata <= X"81900000"; when 16#00005# => romdata <= X"81980000"; when 16#00006# => romdata <= X"81800000"; when 16#00007# => romdata <= X"01000000"; when 16#00008# => romdata <= X"03002040"; when 16#00009# => romdata <= X"8210600F"; when 16#0000A# => romdata <= X"C2A00040"; when 16#0000B# => romdata <= X"87444000"; when 16#0000C# => romdata <= X"8608E01F"; when 16#0000D# => romdata <= X"88100000"; when 16#0000E# => romdata <= X"8A100000"; when 16#0000F# => romdata <= X"8C100000"; when 16#00010# => romdata <= X"8E100000"; when 16#00011# => romdata <= X"A0100000"; when 16#00012# => romdata <= X"A2100000"; when 16#00013# => romdata <= X"A4100000"; when 16#00014# => romdata <= X"A6100000"; when 16#00015# => romdata <= X"A8100000"; when 16#00016# => romdata <= X"AA100000"; when 16#00017# => romdata <= X"AC100000"; when 16#00018# => romdata <= X"AE100000"; when 16#00019# => romdata <= X"90100000"; when 16#0001A# => romdata <= X"92100000"; when 16#0001B# => romdata <= X"94100000"; when 16#0001C# => romdata <= X"96100000"; when 16#0001D# => romdata <= X"98100000"; when 16#0001E# => romdata <= X"9A100000"; when 16#0001F# => romdata <= X"9C100000"; when 16#00020# => romdata <= X"9E100000"; when 16#00021# => romdata <= X"86A0E001"; when 16#00022# => romdata <= X"16BFFFEF"; when 16#00023# => romdata <= X"81E00000"; when 16#00024# => romdata <= X"82102002"; when 16#00025# => romdata <= X"81904000"; when 16#00026# => romdata <= X"03000004"; when 16#00027# => romdata <= X"821060E0"; when 16#00028# => romdata <= X"81884000"; when 16#00029# => romdata <= X"01000000"; when 16#0002A# => romdata <= X"01000000"; when 16#0002B# => romdata <= X"01000000"; when 16#0002C# => romdata <= X"83480000"; when 16#0002D# => romdata <= X"8330600C"; when 16#0002E# => romdata <= X"80886001"; when 16#0002F# => romdata <= X"02800019"; when 16#00030# => romdata <= X"01000000"; when 16#00031# => romdata <= X"07000000"; when 16#00032# => romdata <= X"8610E118"; when 16#00033# => romdata <= X"C108C000"; when 16#00034# => romdata <= X"C118C000"; when 16#00035# => romdata <= X"C518C000"; when 16#00036# => romdata <= X"C918C000"; when 16#00037# => romdata <= X"CD18E008"; when 16#00038# => romdata <= X"D118C000"; when 16#00039# => romdata <= X"D518C000"; when 16#0003A# => romdata <= X"D918C000"; when 16#0003B# => romdata <= X"DD18C000"; when 16#0003C# => romdata <= X"E118C000"; when 16#0003D# => romdata <= X"E518C000"; when 16#0003E# => romdata <= X"E918C000"; when 16#0003F# => romdata <= X"ED18C000"; when 16#00040# => romdata <= X"F118C000"; when 16#00041# => romdata <= X"F518C000"; when 16#00042# => romdata <= X"F918C000"; when 16#00043# => romdata <= X"10800005"; when 16#00044# => romdata <= X"FD18C000"; when 16#00045# => romdata <= X"01000000"; when 16#00046# => romdata <= X"00000000"; when 16#00047# => romdata <= X"00000000"; when 16#00048# => romdata <= X"05000008"; when 16#00049# => romdata <= X"82100000"; when 16#0004A# => romdata <= X"3D1003FF"; when 16#0004B# => romdata <= X"BC17A3E0"; when 16#0004C# => romdata <= X"BC278001"; when 16#0004D# => romdata <= X"9C27A060"; when 16#0004E# => romdata <= X"03100000"; when 16#0004F# => romdata <= X"81C04000"; when 16#00050# => romdata <= X"01000000"; when 16#00051# => romdata <= X"01000000"; when 16#00052# => romdata <= X"01000000"; when 16#00053# => romdata <= X"01000000"; when 16#00054# => romdata <= X"01000000"; when 16#00055# => romdata <= X"01000000"; when 16#00056# => romdata <= X"01000000"; when 16#00057# => romdata <= X"01000000"; when 16#00058# => romdata <= X"00000000"; when 16#00059# => romdata <= X"00000000"; when 16#0005A# => romdata <= X"00000000"; when 16#0005B# => romdata <= X"00000000"; when 16#0005C# => romdata <= X"00000000"; when others => romdata <= (others => '-'); end case; end process; -- pragma translate_off bootmsg : report_version generic map ("ahbrom" & tost(hindex) & ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); -- pragma translate_on end;
---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2009 Aeroflex Gaisler ----------------------------------------------------------------------------- -- Entity: ahbrom -- File: ahbrom.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: AHB rom. 0/1-waitstate read ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; entity ahbrom is generic ( hindex : integer := 0; haddr : integer := 0; hmask : integer := 16#fff#; pipe : integer := 0; tech : integer := 0; kbytes : integer := 1); port ( rst : in std_ulogic; clk : in std_ulogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type ); end; architecture rtl of ahbrom is constant abits : integer := 9; constant bytes : integer := 368; constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); signal romdata : std_logic_vector(31 downto 0); signal addr : std_logic_vector(abits-1 downto 2); signal hsel, hready : std_ulogic; begin ahbso.hresp <= "00"; ahbso.hsplit <= (others => '0'); ahbso.hirq <= (others => '0'); ahbso.hconfig <= hconfig; ahbso.hindex <= hindex; reg : process (clk) begin if rising_edge(clk) then addr <= ahbsi.haddr(abits-1 downto 2); end if; end process; p0 : if pipe = 0 generate ahbso.hrdata <= ahbdrivedata(romdata); ahbso.hready <= '1'; end generate; p1 : if pipe = 1 generate reg2 : process (clk) begin if rising_edge(clk) then hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); hready <= ahbsi.hready; ahbso.hready <= (not rst) or (hsel and hready) or (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); ahbso.hrdata <= ahbdrivedata(romdata); end if; end process; end generate; comb : process (addr) begin case conv_integer(addr) is when 16#00000# => romdata <= X"81D82000"; when 16#00001# => romdata <= X"03000004"; when 16#00002# => romdata <= X"821060E0"; when 16#00003# => romdata <= X"81884000"; when 16#00004# => romdata <= X"81900000"; when 16#00005# => romdata <= X"81980000"; when 16#00006# => romdata <= X"81800000"; when 16#00007# => romdata <= X"01000000"; when 16#00008# => romdata <= X"03002040"; when 16#00009# => romdata <= X"8210600F"; when 16#0000A# => romdata <= X"C2A00040"; when 16#0000B# => romdata <= X"87444000"; when 16#0000C# => romdata <= X"8608E01F"; when 16#0000D# => romdata <= X"88100000"; when 16#0000E# => romdata <= X"8A100000"; when 16#0000F# => romdata <= X"8C100000"; when 16#00010# => romdata <= X"8E100000"; when 16#00011# => romdata <= X"A0100000"; when 16#00012# => romdata <= X"A2100000"; when 16#00013# => romdata <= X"A4100000"; when 16#00014# => romdata <= X"A6100000"; when 16#00015# => romdata <= X"A8100000"; when 16#00016# => romdata <= X"AA100000"; when 16#00017# => romdata <= X"AC100000"; when 16#00018# => romdata <= X"AE100000"; when 16#00019# => romdata <= X"90100000"; when 16#0001A# => romdata <= X"92100000"; when 16#0001B# => romdata <= X"94100000"; when 16#0001C# => romdata <= X"96100000"; when 16#0001D# => romdata <= X"98100000"; when 16#0001E# => romdata <= X"9A100000"; when 16#0001F# => romdata <= X"9C100000"; when 16#00020# => romdata <= X"9E100000"; when 16#00021# => romdata <= X"86A0E001"; when 16#00022# => romdata <= X"16BFFFEF"; when 16#00023# => romdata <= X"81E00000"; when 16#00024# => romdata <= X"82102002"; when 16#00025# => romdata <= X"81904000"; when 16#00026# => romdata <= X"03000004"; when 16#00027# => romdata <= X"821060E0"; when 16#00028# => romdata <= X"81884000"; when 16#00029# => romdata <= X"01000000"; when 16#0002A# => romdata <= X"01000000"; when 16#0002B# => romdata <= X"01000000"; when 16#0002C# => romdata <= X"83480000"; when 16#0002D# => romdata <= X"8330600C"; when 16#0002E# => romdata <= X"80886001"; when 16#0002F# => romdata <= X"02800019"; when 16#00030# => romdata <= X"01000000"; when 16#00031# => romdata <= X"07000000"; when 16#00032# => romdata <= X"8610E118"; when 16#00033# => romdata <= X"C108C000"; when 16#00034# => romdata <= X"C118C000"; when 16#00035# => romdata <= X"C518C000"; when 16#00036# => romdata <= X"C918C000"; when 16#00037# => romdata <= X"CD18E008"; when 16#00038# => romdata <= X"D118C000"; when 16#00039# => romdata <= X"D518C000"; when 16#0003A# => romdata <= X"D918C000"; when 16#0003B# => romdata <= X"DD18C000"; when 16#0003C# => romdata <= X"E118C000"; when 16#0003D# => romdata <= X"E518C000"; when 16#0003E# => romdata <= X"E918C000"; when 16#0003F# => romdata <= X"ED18C000"; when 16#00040# => romdata <= X"F118C000"; when 16#00041# => romdata <= X"F518C000"; when 16#00042# => romdata <= X"F918C000"; when 16#00043# => romdata <= X"10800005"; when 16#00044# => romdata <= X"FD18C000"; when 16#00045# => romdata <= X"01000000"; when 16#00046# => romdata <= X"00000000"; when 16#00047# => romdata <= X"00000000"; when 16#00048# => romdata <= X"05000008"; when 16#00049# => romdata <= X"82100000"; when 16#0004A# => romdata <= X"3D1003FF"; when 16#0004B# => romdata <= X"BC17A3E0"; when 16#0004C# => romdata <= X"BC278001"; when 16#0004D# => romdata <= X"9C27A060"; when 16#0004E# => romdata <= X"03100000"; when 16#0004F# => romdata <= X"81C04000"; when 16#00050# => romdata <= X"01000000"; when 16#00051# => romdata <= X"01000000"; when 16#00052# => romdata <= X"01000000"; when 16#00053# => romdata <= X"01000000"; when 16#00054# => romdata <= X"01000000"; when 16#00055# => romdata <= X"01000000"; when 16#00056# => romdata <= X"01000000"; when 16#00057# => romdata <= X"01000000"; when 16#00058# => romdata <= X"00000000"; when 16#00059# => romdata <= X"00000000"; when 16#0005A# => romdata <= X"00000000"; when 16#0005B# => romdata <= X"00000000"; when 16#0005C# => romdata <= X"00000000"; when others => romdata <= (others => '-'); end case; end process; -- pragma translate_off bootmsg : report_version generic map ("ahbrom" & tost(hindex) & ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); -- pragma translate_on end;
--- $Id: $ -- File name: controller.vhd -- Created: 4/7/2012 -- Author: Spencer Julian -- Lab Section: 337-02 -- Version: 1.0 Initial Design Entry -- Description: Controller for the USB Sniffer LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; entity controller is port ( clk : in std_logic; rst : in std_logic; fifo_full : in std_logic; decoder_instruction : in std_logic_vector(3 downto 0); data_ready : in std_logic_vector(1 downto 0); eop_found : in std_logic; data_read : in std_logic; fifo_read : out std_logic; fifo_write : out std_logic; intercept : out std_logic ); end entity controller; architecture controller_arch of controller is type usbState is (idle,requestIntercept,prepareIntercept,doIntercept,waitTrans,writeDelay,writePrep,write,eop); type sdState is (idle,fifoRead); signal usb, nextUsb: usbState; signal sd, nextSd: sdState; signal beginSd: std_logic; signal dr1, dr2, dr : std_logic; signal eopCount, nexteopCount: std_logic_vector(2 downto 0); signal writeCount, nextWriteCount : std_logic_vector(2 downto 0); signal eop1, eop2, eopf: std_logic; begin GREGI: process(rst, clk) begin if(rst = '0') then --Reset everything usb <= idle; sd <= idle; eopCount <= "000"; writeCount <= "000"; eop1 <= '0'; eop2 <= '0'; dr1 <= '0'; dr2 <= '0'; dr <= '0'; elsif(rising_edge(clk)) then --Clock edge usb <= nextUsb; --Next states sd <= nextSd; eopCount <= nexteopCount; writeCount <= nextWriteCount; if (eop2 = '0' and eop1 = '1') then --Edge detector on our eop signal, only want to do things once. eopf <= '1'; else eopf <= '0'; end if; if(dr2 = '0' and dr1 = '1') then --Edge detector for the "data_read" signal, don't want to continously empty the fifo dr <= '1'; else dr <= '0'; end if; dr2 <= dr1; dr1 <= data_read; eop2 <= eop1; eop1 <= eop_found; end if; end process GREGI; NXT: process(fifo_full,decoder_instruction,data_ready,eopf,writeCount,nextWriteCount,eopCount,nexteopCount,eop_found,dr,beginSd,nextUsb,nextSd,usb,sd) begin nexteopCount <= eopCount; nextWriteCount <= writeCount; nextUsb <= usb; case usb is --State machine 1 when idle => --Idle, waiting for PID (PIDs are inverse due to LSB first) nexteopCount <= "000"; nextWriteCount <= "000"; if (decoder_instruction = "1101") then nextUsb <= requestIntercept; elsif (decoder_instruction = "0011") then nextUsb <= writeDelay; elsif (decoder_instruction = "1011") then nextUsb <= writeDelay; elsif (decoder_instruction = "0111") then nextUsb <= writeDelay; else nextUsb <= idle; end if; when requestIntercept => --if PID was a setup PID, wait for "IN" PID nexteopCount <= "000"; nextWriteCount <= "000"; if (decoder_instruction = "1001") then nextUsb <= prepareIntercept; else nextUsb <= requestIntercept; end if; when prepareIntercept => --Now if the PID is an "IN" PID, wait for "Data" PID nexteopCount <= "000"; nextWriteCount <= "000"; if (decoder_instruction = "1011") then nextUsb <= doIntercept; else nextUsb <= prepareIntercept; end if; when doIntercept => --Once we see Data PID, we know we're transmitting data, so prepare to intercept. nexteopCount <= "000"; nextWriteCount <= "000"; nextUsb <= waitTrans; when waitTrans => -- Now we need to wait until we see the appropriate number of "eop's" so we know we're done with the device descriptor packet. nextWriteCount <= "000"; if (eopCount = "101") then nexteopCount <= "000"; nextUsb <= idle; elsif (eopCount < 5 and eopf = '1') then nexteopCount <= eopCount + 1; nextUsb <= waitTrans; else nexteopCount <= eopCount; nextUsb <= waitTrans; end if; when writeDelay => --This delays the write state due to internal delays nexteopCount <= "000"; if (data_ready = "01") then nextUsb <= writePrep; else nextUsb <= writeDelay; end if; when writePrep => --This delays the write state until we have a full byte to write nexteopCount <= "000"; if (data_ready = "11") then nextUsb <= write; else nextUsb <= writePrep; end if; when write => --This allows bytes to enter the fifo until it's full or we see an eop. nexteopCount <= "000"; nextWriteCount <= writeCount + 1; if (eop_found = '1' or fifo_full = '1' or writeCount = 7) then nextUsb <= eop; else nextUsb <= writeDelay; end if; when eop => --Once we see an eop (or a full fifo), begin the next state machine (below). nextWriteCount <= "000"; nexteopCount <= "000"; nextUsb <= idle; when others => nextUsb <= idle; end case; nextSd <= sd; case sd is --Next state machine when idle => --If data hasn't been read by the sd controller yet, just sit there. if (dr = '1') then nextSd <= fifoRead; else nextSd <= idle; end if; when fifoRead => --Otherwise, increment the fifo's counter. nextSd <= idle; when others => nextSd <= idle; end case; end process NXT; OUTL: process(usb, nextUsb, sd, nextSd) --This process just outputs specific values. It's seperated for readability. The states are described above. begin fifo_write <= '0'; intercept <= '0'; beginSd <= '0'; case usb is --fifo_write, intercept, beginSd, lockCode when idle => fifo_write <= '0'; intercept <= '0'; beginSd <= '0'; when requestIntercept => fifo_write <= '0'; intercept <= '0'; beginSd <= '0'; when prepareIntercept => fifo_write <= '0'; intercept <= '0'; beginSd <= '0'; when doIntercept => fifo_write <= '0'; intercept <= '1'; beginSd <= '0'; when waitTrans => fifo_write <= '0'; intercept <= '0'; beginSd <= '0'; when writeDelay => fifo_write <= '0'; intercept <= '0'; beginSd <= '0'; when writePrep => fifo_write <= '0'; intercept <= '0'; beginSd <= '0'; when write => fifo_write <= '1'; intercept <= '0'; beginSd <= '0'; when eop => fifo_write <= '0'; intercept <= '0'; beginSd <= '1'; --when others => nextUsb <= idle; end case; fifo_read <= '0'; case sd is --sd_enable(!), sd_clock, fifo_read, nextBitCount, gregister_read when idle => fifo_read <= '0'; when fifoRead => fifo_read <= '1'; --when others => nextSd <= idle; end case; end process OUTL; end controller_arch;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.reu_pkg.all; use work.mem_bus_pkg.all; use work.dma_bus_pkg.all; use work.slot_bus_pkg.all; -- Standard: 433 LUT/148 FF -- Extended: 564 LUT/195 FF entity reu is generic ( g_ram_tag : std_logic_vector(7 downto 0) := X"10"; g_extended : boolean := true; g_ram_base : unsigned(27 downto 0) := X"1000000" ); -- second (=upper 16M) port ( clock : in std_logic; reset : in std_logic; -- register interface slot_req : in t_slot_req; slot_resp : out t_slot_resp; -- system interface phi2_tick : in std_logic := '0'; reu_dma_n : out std_logic := '1'; size_ctrl : in std_logic_vector(2 downto 0) := "001"; enable : in std_logic; -- memory interface mem_req : out t_mem_req; mem_resp : in t_mem_resp; dma_req : out t_dma_req; dma_resp : in t_dma_resp ); end reu; -- The REU is actually really simple. -- There are 4 modes of operation, and 4 active states: -- r = reu read, w = reu write, R = c64 read, W = c64 write -- Copy from c64 to reu (00): Rw -- Copy from reu to c64 (01): rW -- Swap (10): rRwW (RrWw or rRWw or RrwW or rRwW) -- Verify (11): rR (Rr or rR) -- The smallest implementation is very likely when only one bit is needed to select between -- transition options, and reducing the total number of transitions makes sense too. architecture gideon of reu is type t_state is (idle, do_read_c64, do_write_c64, do_read_reu, do_write_reu, check_end, delay); signal state : t_state; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; signal io_wdatau : unsigned(7 downto 0); signal io_rdata : std_logic_vector(7 downto 0); signal io_write : std_logic; signal io_read : std_logic; signal c64_base : unsigned(15 downto 0) := (others => '0'); signal reu_base : unsigned(23 downto 0) := (others => '0'); signal length_reg : unsigned(23 downto 0) := (others => '1'); signal c64_addr : unsigned(15 downto 0) := (others => '0'); signal reu_addr : unsigned(23 downto 0) := (others => '0'); signal count : unsigned(23 downto 0) := (others => '1'); signal c64_req : std_logic; signal c64_rack : std_logic; signal c64_dack : std_logic; signal reu_req : std_logic; signal reu_rack : std_logic; signal reu_dack : std_logic; signal glob_rwn : std_logic; signal write_ff00 : std_logic; signal masked_reu_addr : unsigned(23 downto 0); signal mask : unsigned(7 downto 0); signal c64_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal reu_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal verify_error : std_logic; signal trans_done : std_logic; signal irq_pend : std_logic; signal reserved : std_logic_vector(2 downto 0); type t_control is record irq_en : std_logic; irq_done : std_logic; irq_error : std_logic; fix_reu : std_logic; fix_c64 : std_logic; end record; type t_command is record execute : std_logic; autoload : std_logic; ff00 : std_logic; mode : std_logic_vector(1 downto 0); end record; constant c_control_def : t_control := (others => '0'); constant c_command_def : t_command := ( mode => "00", execute => '0', ff00 => '1', autoload => '0' ); signal control : t_control; signal command : t_command; -- signals for extended mode signal rate_div : unsigned(7 downto 0) := (others => '0'); signal start_delay : unsigned(7 downto 0) := (others => '0'); signal ext_count : unsigned(7 downto 0) := (others => '0'); begin write_ff00 <= '1' when slot_req.late_write='1' and slot_req.io_address=X"FF00" else '0'; with size_ctrl select mask <= "00000001" when "000", "00000011" when "001", "00000111" when "010", "00001111" when "011", "00011111" when "100", "00111111" when "101", "01111111" when "110", "11111111" when others; masked_reu_addr(23 downto 19) <= (reu_base(23 downto 19) and mask(7 downto 3)) when not g_extended else (reu_addr(23 downto 19) and mask(7 downto 3)); masked_reu_addr(18 downto 16) <= (reu_addr(18 downto 16) and mask(2 downto 0)); masked_reu_addr(15 downto 0) <= reu_addr(15 downto 0); reu_rack <= '1' when mem_resp.rack_tag = g_ram_tag else '0'; reu_dack <= '1' when mem_resp.dack_tag = g_ram_tag else '0'; io_wdatau <= unsigned(slot_req.data); -- fill mem request structure mem_req.tag <= g_ram_tag; mem_req.request <= reu_req; mem_req.address <= g_ram_base(25 downto 24) & masked_reu_addr; mem_req.read_writen <= glob_rwn; mem_req.data <= c64_read_reg; mem_req.size <= "00"; -- 1 byte at a time -- fill dma request structure dma_req.request <= c64_req; dma_req.address <= c64_addr; dma_req.read_writen <= glob_rwn; dma_req.data <= reu_read_reg; c64_rack <= dma_resp.rack; c64_dack <= dma_resp.dack; p_main: process(clock) procedure next_address is begin if control.fix_c64='0' then c64_addr <= c64_addr + 1; end if; if control.fix_reu='0' then reu_addr <= reu_addr + 1; end if; if (count(15 downto 0) = 1 and not g_extended) or (count = 1 and g_extended) then trans_done <= '1'; else count <= count - 1; end if; end procedure; procedure transfer_end is begin if command.autoload='1' then c64_addr <= c64_base; reu_addr <= reu_base(reu_addr'range); if g_extended then count <= length_reg; else count(15 downto 0) <= length_reg(15 downto 0); end if; end if; command.ff00 <= '1'; -- reset to default state state <= idle; end procedure; procedure dispatch is begin glob_rwn <= '1'; -- we're going to read. case command.mode is when c_mode_toreu => -- C64 to REU c64_req <= '1'; state <= do_read_c64; when others => -- in all other cases, read reu first reu_req <= '1'; state <= do_read_reu; end case; end procedure; begin if rising_edge(clock) then if io_write='1' then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_c64base_l => c64_base(7 downto 0) <= io_wdatau; c64_addr <= c64_base(15 downto 8) & io_wdatau; -- half autoload bug when c_c64base_h => c64_base(15 downto 8) <= io_wdatau; c64_addr <= io_wdatau & c64_base(7 downto 0); -- half autoload bug when c_reubase_l => reu_base(7 downto 0) <= io_wdatau; reu_addr(15 downto 0) <= reu_base(15 downto 8) & io_wdatau; -- half autoload bug when c_reubase_m => reu_base(15 downto 8) <= io_wdatau; reu_addr(15 downto 0) <= io_wdatau & reu_base(7 downto 0); -- half autoload bug when c_reubase_h => reu_base(23 downto 16) <= io_wdatau; reu_addr(23 downto 16) <= io_wdatau; when c_translen_l => length_reg(7 downto 0) <= io_wdatau; count(15 downto 0) <= length_reg(15 downto 8) & io_wdatau; -- half autoload bug when c_translen_h => length_reg(15 downto 8) <= io_wdatau; count(15 downto 0) <= io_wdatau & length_reg(7 downto 0); -- half autoload bug when c_irqmask => control.irq_en <= io_wdatau(7); control.irq_done <= io_wdatau(6); control.irq_error <= io_wdatau(5); when c_control => control.fix_reu <= io_wdatau(6); control.fix_c64 <= io_wdatau(7); when c_command => command.execute <= io_wdatau(7); reserved(2) <= io_wdatau(6); command.autoload <= io_wdatau(5); command.ff00 <= io_wdatau(4); reserved(1) <= io_wdatau(3); reserved(0) <= io_wdatau(2); command.mode <= slot_req.data(1 downto 0); when others => null; end case; end if; -- extended registers if io_write='1' and g_extended then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_start_delay => start_delay <= io_wdatau; when c_rate_div => rate_div <= io_wdatau; when c_translen_x => length_reg(23 downto 16) <= io_wdatau; count(23 downto 16) <= io_wdatau; when others => null; end case; end if; -- clear on read flags if io_read='1' then if slot_req.io_address(4 downto 0) = c_status then verify_error <= '0'; trans_done <= '0'; end if; end if; case state is when idle => reu_dma_n <= '1'; glob_rwn <= '1'; ext_count <= start_delay; if command.execute='1' then if (command.ff00='0' and write_ff00='1') or (command.ff00='1') then verify_error <= '0'; trans_done <= '0'; command.execute <= '0'; if g_extended then state <= delay; else dispatch; reu_dma_n <= '0'; end if; end if; end if; when delay => if ext_count = 0 then dispatch; reu_dma_n <= '0'; elsif phi2_tick='1' then ext_count <= ext_count - 1; end if; when do_read_reu => if reu_rack='1' then reu_req <= '0'; end if; if reu_dack='1' then reu_read_reg <= mem_resp.data; case command.mode is when c_mode_swap | c_mode_verify => c64_req <= '1'; glob_rwn <= '1'; state <= do_read_c64; when others => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; end case; end if; when do_write_c64 => if c64_rack='1' then c64_req <= '0'; next_address; state <= check_end; end if; when do_read_c64 => if c64_rack='1' then c64_req <= '0'; end if; if c64_dack='1' then c64_read_reg <= dma_resp.data; case command.mode is when c_mode_verify => if dma_resp.data /= reu_read_reg then verify_error <= '1'; state <= idle; else next_address; state <= check_end; end if; when others => reu_req <= '1'; glob_rwn <= '0'; state <= do_write_reu; end case; end if; when do_write_reu => if reu_rack='1' then reu_req <= '0'; case command.mode is when c_mode_swap => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; when others => next_address; state <= check_end; end case; end if; when check_end => ext_count <= rate_div; if trans_done='1' then transfer_end; elsif g_extended then state <= delay; else dispatch; end if; when others => null; end case; if reset='1' then reu_req <= '0'; c64_req <= '0'; glob_rwn <= '1'; control <= c_control_def; command <= c_command_def; state <= idle; reserved <= (others => '0'); verify_error <= '0'; trans_done <= '0'; reu_dma_n <= '1'; c64_base <= (others => '0'); reu_base <= (others => '0'); length_reg <= X"00FFFF"; c64_addr <= (others => '0'); reu_addr <= (others => '0'); count <= (others => '1'); rate_div <= (others => '0'); start_delay <= (others => '0'); rate_div <= (others => '0'); ext_count <= (others => '0'); end if; end if; end process; p_read: process(slot_req, control, command, count, c64_addr, reu_addr, verify_error, trans_done, irq_pend, c64_base, reu_base, length_reg, reserved, mask, start_delay, rate_div) begin io_rdata <= X"FF"; case slot_req.bus_address(4 downto 0) is when c_status => io_rdata(7) <= irq_pend; io_rdata(6) <= trans_done; io_rdata(5) <= verify_error; io_rdata(4) <= mask(1); -- for 256k and larger, this is set to '1'. io_rdata(3 downto 0) <= X"0"; -- version when c_command => io_rdata(7) <= command.execute; io_rdata(6) <= reserved(2); io_rdata(5) <= command.autoload; io_rdata(4) <= command.ff00; io_rdata(3 downto 2) <= reserved(1 downto 0); io_rdata(1 downto 0) <= command.mode; when c_irqmask => io_rdata(7) <= control.irq_en; io_rdata(6) <= control.irq_done; io_rdata(5) <= control.irq_error; when c_control => io_rdata(7) <= control.fix_c64; io_rdata(6) <= control.fix_reu; when c_c64base_l => io_rdata <= std_logic_vector(c64_addr(7 downto 0)); when c_c64base_h => io_rdata <= std_logic_vector(c64_addr(15 downto 8)); when c_reubase_l => io_rdata <= std_logic_vector(reu_addr(7 downto 0)); when c_reubase_m => io_rdata <= std_logic_vector(reu_addr(15 downto 8)); when c_reubase_h => if g_extended then io_rdata <= std_logic_vector(reu_addr(23 downto 16)); else io_rdata <= "11111" & std_logic_vector(reu_addr(18 downto 16)); -- maximum 19 bits end if; when c_translen_l => io_rdata <= std_logic_vector(count(7 downto 0)); when c_translen_h => io_rdata <= std_logic_vector(count(15 downto 8)); when c_size_read => if g_extended then io_rdata <= std_logic_vector(mask); end if; when c_start_delay => if g_extended then io_rdata <= std_logic_vector(start_delay); end if; when c_rate_div => if g_extended then io_rdata <= std_logic_vector(rate_div); end if; when others => null; end case; end process; irq_pend <= control.irq_en and ((control.irq_done and trans_done) or (control.irq_error and verify_error)); slot_resp.irq <= irq_pend; slot_resp.data <= io_rdata; slot_resp.reg_output <= enable when slot_req.bus_address(8 downto 5)=X"8" and slot_req.bus_address(4 downto 2)/="111" and (state = idle) else '0'; io_write <= (enable and slot_req.io_write) when slot_req.io_address(8 downto 5)=X"8" else '0'; io_read <= (enable and slot_req.io_read) when slot_req.io_address(8 downto 5)=X"8" else '0'; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.reu_pkg.all; use work.mem_bus_pkg.all; use work.dma_bus_pkg.all; use work.slot_bus_pkg.all; -- Standard: 433 LUT/148 FF -- Extended: 564 LUT/195 FF entity reu is generic ( g_ram_tag : std_logic_vector(7 downto 0) := X"10"; g_extended : boolean := true; g_ram_base : unsigned(27 downto 0) := X"1000000" ); -- second (=upper 16M) port ( clock : in std_logic; reset : in std_logic; -- register interface slot_req : in t_slot_req; slot_resp : out t_slot_resp; -- system interface phi2_tick : in std_logic := '0'; reu_dma_n : out std_logic := '1'; size_ctrl : in std_logic_vector(2 downto 0) := "001"; enable : in std_logic; -- memory interface mem_req : out t_mem_req; mem_resp : in t_mem_resp; dma_req : out t_dma_req; dma_resp : in t_dma_resp ); end reu; -- The REU is actually really simple. -- There are 4 modes of operation, and 4 active states: -- r = reu read, w = reu write, R = c64 read, W = c64 write -- Copy from c64 to reu (00): Rw -- Copy from reu to c64 (01): rW -- Swap (10): rRwW (RrWw or rRWw or RrwW or rRwW) -- Verify (11): rR (Rr or rR) -- The smallest implementation is very likely when only one bit is needed to select between -- transition options, and reducing the total number of transitions makes sense too. architecture gideon of reu is type t_state is (idle, do_read_c64, do_write_c64, do_read_reu, do_write_reu, check_end, delay); signal state : t_state; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; signal io_wdatau : unsigned(7 downto 0); signal io_rdata : std_logic_vector(7 downto 0); signal io_write : std_logic; signal io_read : std_logic; signal c64_base : unsigned(15 downto 0) := (others => '0'); signal reu_base : unsigned(23 downto 0) := (others => '0'); signal length_reg : unsigned(23 downto 0) := (others => '1'); signal c64_addr : unsigned(15 downto 0) := (others => '0'); signal reu_addr : unsigned(23 downto 0) := (others => '0'); signal count : unsigned(23 downto 0) := (others => '1'); signal c64_req : std_logic; signal c64_rack : std_logic; signal c64_dack : std_logic; signal reu_req : std_logic; signal reu_rack : std_logic; signal reu_dack : std_logic; signal glob_rwn : std_logic; signal write_ff00 : std_logic; signal masked_reu_addr : unsigned(23 downto 0); signal mask : unsigned(7 downto 0); signal c64_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal reu_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal verify_error : std_logic; signal trans_done : std_logic; signal irq_pend : std_logic; signal reserved : std_logic_vector(2 downto 0); type t_control is record irq_en : std_logic; irq_done : std_logic; irq_error : std_logic; fix_reu : std_logic; fix_c64 : std_logic; end record; type t_command is record execute : std_logic; autoload : std_logic; ff00 : std_logic; mode : std_logic_vector(1 downto 0); end record; constant c_control_def : t_control := (others => '0'); constant c_command_def : t_command := ( mode => "00", execute => '0', ff00 => '1', autoload => '0' ); signal control : t_control; signal command : t_command; -- signals for extended mode signal rate_div : unsigned(7 downto 0) := (others => '0'); signal start_delay : unsigned(7 downto 0) := (others => '0'); signal ext_count : unsigned(7 downto 0) := (others => '0'); begin write_ff00 <= '1' when slot_req.late_write='1' and slot_req.io_address=X"FF00" else '0'; with size_ctrl select mask <= "00000001" when "000", "00000011" when "001", "00000111" when "010", "00001111" when "011", "00011111" when "100", "00111111" when "101", "01111111" when "110", "11111111" when others; masked_reu_addr(23 downto 19) <= (reu_base(23 downto 19) and mask(7 downto 3)) when not g_extended else (reu_addr(23 downto 19) and mask(7 downto 3)); masked_reu_addr(18 downto 16) <= (reu_addr(18 downto 16) and mask(2 downto 0)); masked_reu_addr(15 downto 0) <= reu_addr(15 downto 0); reu_rack <= '1' when mem_resp.rack_tag = g_ram_tag else '0'; reu_dack <= '1' when mem_resp.dack_tag = g_ram_tag else '0'; io_wdatau <= unsigned(slot_req.data); -- fill mem request structure mem_req.tag <= g_ram_tag; mem_req.request <= reu_req; mem_req.address <= g_ram_base(25 downto 24) & masked_reu_addr; mem_req.read_writen <= glob_rwn; mem_req.data <= c64_read_reg; mem_req.size <= "00"; -- 1 byte at a time -- fill dma request structure dma_req.request <= c64_req; dma_req.address <= c64_addr; dma_req.read_writen <= glob_rwn; dma_req.data <= reu_read_reg; c64_rack <= dma_resp.rack; c64_dack <= dma_resp.dack; p_main: process(clock) procedure next_address is begin if control.fix_c64='0' then c64_addr <= c64_addr + 1; end if; if control.fix_reu='0' then reu_addr <= reu_addr + 1; end if; if (count(15 downto 0) = 1 and not g_extended) or (count = 1 and g_extended) then trans_done <= '1'; else count <= count - 1; end if; end procedure; procedure transfer_end is begin if command.autoload='1' then c64_addr <= c64_base; reu_addr <= reu_base(reu_addr'range); if g_extended then count <= length_reg; else count(15 downto 0) <= length_reg(15 downto 0); end if; end if; command.ff00 <= '1'; -- reset to default state state <= idle; end procedure; procedure dispatch is begin glob_rwn <= '1'; -- we're going to read. case command.mode is when c_mode_toreu => -- C64 to REU c64_req <= '1'; state <= do_read_c64; when others => -- in all other cases, read reu first reu_req <= '1'; state <= do_read_reu; end case; end procedure; begin if rising_edge(clock) then if io_write='1' then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_c64base_l => c64_base(7 downto 0) <= io_wdatau; c64_addr <= c64_base(15 downto 8) & io_wdatau; -- half autoload bug when c_c64base_h => c64_base(15 downto 8) <= io_wdatau; c64_addr <= io_wdatau & c64_base(7 downto 0); -- half autoload bug when c_reubase_l => reu_base(7 downto 0) <= io_wdatau; reu_addr(15 downto 0) <= reu_base(15 downto 8) & io_wdatau; -- half autoload bug when c_reubase_m => reu_base(15 downto 8) <= io_wdatau; reu_addr(15 downto 0) <= io_wdatau & reu_base(7 downto 0); -- half autoload bug when c_reubase_h => reu_base(23 downto 16) <= io_wdatau; reu_addr(23 downto 16) <= io_wdatau; when c_translen_l => length_reg(7 downto 0) <= io_wdatau; count(15 downto 0) <= length_reg(15 downto 8) & io_wdatau; -- half autoload bug when c_translen_h => length_reg(15 downto 8) <= io_wdatau; count(15 downto 0) <= io_wdatau & length_reg(7 downto 0); -- half autoload bug when c_irqmask => control.irq_en <= io_wdatau(7); control.irq_done <= io_wdatau(6); control.irq_error <= io_wdatau(5); when c_control => control.fix_reu <= io_wdatau(6); control.fix_c64 <= io_wdatau(7); when c_command => command.execute <= io_wdatau(7); reserved(2) <= io_wdatau(6); command.autoload <= io_wdatau(5); command.ff00 <= io_wdatau(4); reserved(1) <= io_wdatau(3); reserved(0) <= io_wdatau(2); command.mode <= slot_req.data(1 downto 0); when others => null; end case; end if; -- extended registers if io_write='1' and g_extended then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_start_delay => start_delay <= io_wdatau; when c_rate_div => rate_div <= io_wdatau; when c_translen_x => length_reg(23 downto 16) <= io_wdatau; count(23 downto 16) <= io_wdatau; when others => null; end case; end if; -- clear on read flags if io_read='1' then if slot_req.io_address(4 downto 0) = c_status then verify_error <= '0'; trans_done <= '0'; end if; end if; case state is when idle => reu_dma_n <= '1'; glob_rwn <= '1'; ext_count <= start_delay; if command.execute='1' then if (command.ff00='0' and write_ff00='1') or (command.ff00='1') then verify_error <= '0'; trans_done <= '0'; command.execute <= '0'; if g_extended then state <= delay; else dispatch; reu_dma_n <= '0'; end if; end if; end if; when delay => if ext_count = 0 then dispatch; reu_dma_n <= '0'; elsif phi2_tick='1' then ext_count <= ext_count - 1; end if; when do_read_reu => if reu_rack='1' then reu_req <= '0'; end if; if reu_dack='1' then reu_read_reg <= mem_resp.data; case command.mode is when c_mode_swap | c_mode_verify => c64_req <= '1'; glob_rwn <= '1'; state <= do_read_c64; when others => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; end case; end if; when do_write_c64 => if c64_rack='1' then c64_req <= '0'; next_address; state <= check_end; end if; when do_read_c64 => if c64_rack='1' then c64_req <= '0'; end if; if c64_dack='1' then c64_read_reg <= dma_resp.data; case command.mode is when c_mode_verify => if dma_resp.data /= reu_read_reg then verify_error <= '1'; state <= idle; else next_address; state <= check_end; end if; when others => reu_req <= '1'; glob_rwn <= '0'; state <= do_write_reu; end case; end if; when do_write_reu => if reu_rack='1' then reu_req <= '0'; case command.mode is when c_mode_swap => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; when others => next_address; state <= check_end; end case; end if; when check_end => ext_count <= rate_div; if trans_done='1' then transfer_end; elsif g_extended then state <= delay; else dispatch; end if; when others => null; end case; if reset='1' then reu_req <= '0'; c64_req <= '0'; glob_rwn <= '1'; control <= c_control_def; command <= c_command_def; state <= idle; reserved <= (others => '0'); verify_error <= '0'; trans_done <= '0'; reu_dma_n <= '1'; c64_base <= (others => '0'); reu_base <= (others => '0'); length_reg <= X"00FFFF"; c64_addr <= (others => '0'); reu_addr <= (others => '0'); count <= (others => '1'); rate_div <= (others => '0'); start_delay <= (others => '0'); rate_div <= (others => '0'); ext_count <= (others => '0'); end if; end if; end process; p_read: process(slot_req, control, command, count, c64_addr, reu_addr, verify_error, trans_done, irq_pend, c64_base, reu_base, length_reg, reserved, mask, start_delay, rate_div) begin io_rdata <= X"FF"; case slot_req.bus_address(4 downto 0) is when c_status => io_rdata(7) <= irq_pend; io_rdata(6) <= trans_done; io_rdata(5) <= verify_error; io_rdata(4) <= mask(1); -- for 256k and larger, this is set to '1'. io_rdata(3 downto 0) <= X"0"; -- version when c_command => io_rdata(7) <= command.execute; io_rdata(6) <= reserved(2); io_rdata(5) <= command.autoload; io_rdata(4) <= command.ff00; io_rdata(3 downto 2) <= reserved(1 downto 0); io_rdata(1 downto 0) <= command.mode; when c_irqmask => io_rdata(7) <= control.irq_en; io_rdata(6) <= control.irq_done; io_rdata(5) <= control.irq_error; when c_control => io_rdata(7) <= control.fix_c64; io_rdata(6) <= control.fix_reu; when c_c64base_l => io_rdata <= std_logic_vector(c64_addr(7 downto 0)); when c_c64base_h => io_rdata <= std_logic_vector(c64_addr(15 downto 8)); when c_reubase_l => io_rdata <= std_logic_vector(reu_addr(7 downto 0)); when c_reubase_m => io_rdata <= std_logic_vector(reu_addr(15 downto 8)); when c_reubase_h => if g_extended then io_rdata <= std_logic_vector(reu_addr(23 downto 16)); else io_rdata <= "11111" & std_logic_vector(reu_addr(18 downto 16)); -- maximum 19 bits end if; when c_translen_l => io_rdata <= std_logic_vector(count(7 downto 0)); when c_translen_h => io_rdata <= std_logic_vector(count(15 downto 8)); when c_size_read => if g_extended then io_rdata <= std_logic_vector(mask); end if; when c_start_delay => if g_extended then io_rdata <= std_logic_vector(start_delay); end if; when c_rate_div => if g_extended then io_rdata <= std_logic_vector(rate_div); end if; when others => null; end case; end process; irq_pend <= control.irq_en and ((control.irq_done and trans_done) or (control.irq_error and verify_error)); slot_resp.irq <= irq_pend; slot_resp.data <= io_rdata; slot_resp.reg_output <= enable when slot_req.bus_address(8 downto 5)=X"8" and slot_req.bus_address(4 downto 2)/="111" and (state = idle) else '0'; io_write <= (enable and slot_req.io_write) when slot_req.io_address(8 downto 5)=X"8" else '0'; io_read <= (enable and slot_req.io_read) when slot_req.io_address(8 downto 5)=X"8" else '0'; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.reu_pkg.all; use work.mem_bus_pkg.all; use work.dma_bus_pkg.all; use work.slot_bus_pkg.all; -- Standard: 433 LUT/148 FF -- Extended: 564 LUT/195 FF entity reu is generic ( g_ram_tag : std_logic_vector(7 downto 0) := X"10"; g_extended : boolean := true; g_ram_base : unsigned(27 downto 0) := X"1000000" ); -- second (=upper 16M) port ( clock : in std_logic; reset : in std_logic; -- register interface slot_req : in t_slot_req; slot_resp : out t_slot_resp; -- system interface phi2_tick : in std_logic := '0'; reu_dma_n : out std_logic := '1'; size_ctrl : in std_logic_vector(2 downto 0) := "001"; enable : in std_logic; -- memory interface mem_req : out t_mem_req; mem_resp : in t_mem_resp; dma_req : out t_dma_req; dma_resp : in t_dma_resp ); end reu; -- The REU is actually really simple. -- There are 4 modes of operation, and 4 active states: -- r = reu read, w = reu write, R = c64 read, W = c64 write -- Copy from c64 to reu (00): Rw -- Copy from reu to c64 (01): rW -- Swap (10): rRwW (RrWw or rRWw or RrwW or rRwW) -- Verify (11): rR (Rr or rR) -- The smallest implementation is very likely when only one bit is needed to select between -- transition options, and reducing the total number of transitions makes sense too. architecture gideon of reu is type t_state is (idle, do_read_c64, do_write_c64, do_read_reu, do_write_reu, check_end, delay); signal state : t_state; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; signal io_wdatau : unsigned(7 downto 0); signal io_rdata : std_logic_vector(7 downto 0); signal io_write : std_logic; signal io_read : std_logic; signal c64_base : unsigned(15 downto 0) := (others => '0'); signal reu_base : unsigned(23 downto 0) := (others => '0'); signal length_reg : unsigned(23 downto 0) := (others => '1'); signal c64_addr : unsigned(15 downto 0) := (others => '0'); signal reu_addr : unsigned(23 downto 0) := (others => '0'); signal count : unsigned(23 downto 0) := (others => '1'); signal c64_req : std_logic; signal c64_rack : std_logic; signal c64_dack : std_logic; signal reu_req : std_logic; signal reu_rack : std_logic; signal reu_dack : std_logic; signal glob_rwn : std_logic; signal write_ff00 : std_logic; signal masked_reu_addr : unsigned(23 downto 0); signal mask : unsigned(7 downto 0); signal c64_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal reu_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal verify_error : std_logic; signal trans_done : std_logic; signal irq_pend : std_logic; signal reserved : std_logic_vector(2 downto 0); type t_control is record irq_en : std_logic; irq_done : std_logic; irq_error : std_logic; fix_reu : std_logic; fix_c64 : std_logic; end record; type t_command is record execute : std_logic; autoload : std_logic; ff00 : std_logic; mode : std_logic_vector(1 downto 0); end record; constant c_control_def : t_control := (others => '0'); constant c_command_def : t_command := ( mode => "00", execute => '0', ff00 => '1', autoload => '0' ); signal control : t_control; signal command : t_command; -- signals for extended mode signal rate_div : unsigned(7 downto 0) := (others => '0'); signal start_delay : unsigned(7 downto 0) := (others => '0'); signal ext_count : unsigned(7 downto 0) := (others => '0'); begin write_ff00 <= '1' when slot_req.late_write='1' and slot_req.io_address=X"FF00" else '0'; with size_ctrl select mask <= "00000001" when "000", "00000011" when "001", "00000111" when "010", "00001111" when "011", "00011111" when "100", "00111111" when "101", "01111111" when "110", "11111111" when others; masked_reu_addr(23 downto 19) <= (reu_base(23 downto 19) and mask(7 downto 3)) when not g_extended else (reu_addr(23 downto 19) and mask(7 downto 3)); masked_reu_addr(18 downto 16) <= (reu_addr(18 downto 16) and mask(2 downto 0)); masked_reu_addr(15 downto 0) <= reu_addr(15 downto 0); reu_rack <= '1' when mem_resp.rack_tag = g_ram_tag else '0'; reu_dack <= '1' when mem_resp.dack_tag = g_ram_tag else '0'; io_wdatau <= unsigned(slot_req.data); -- fill mem request structure mem_req.tag <= g_ram_tag; mem_req.request <= reu_req; mem_req.address <= g_ram_base(25 downto 24) & masked_reu_addr; mem_req.read_writen <= glob_rwn; mem_req.data <= c64_read_reg; mem_req.size <= "00"; -- 1 byte at a time -- fill dma request structure dma_req.request <= c64_req; dma_req.address <= c64_addr; dma_req.read_writen <= glob_rwn; dma_req.data <= reu_read_reg; c64_rack <= dma_resp.rack; c64_dack <= dma_resp.dack; p_main: process(clock) procedure next_address is begin if control.fix_c64='0' then c64_addr <= c64_addr + 1; end if; if control.fix_reu='0' then reu_addr <= reu_addr + 1; end if; if (count(15 downto 0) = 1 and not g_extended) or (count = 1 and g_extended) then trans_done <= '1'; else count <= count - 1; end if; end procedure; procedure transfer_end is begin if command.autoload='1' then c64_addr <= c64_base; reu_addr <= reu_base(reu_addr'range); if g_extended then count <= length_reg; else count(15 downto 0) <= length_reg(15 downto 0); end if; end if; command.ff00 <= '1'; -- reset to default state state <= idle; end procedure; procedure dispatch is begin glob_rwn <= '1'; -- we're going to read. case command.mode is when c_mode_toreu => -- C64 to REU c64_req <= '1'; state <= do_read_c64; when others => -- in all other cases, read reu first reu_req <= '1'; state <= do_read_reu; end case; end procedure; begin if rising_edge(clock) then if io_write='1' then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_c64base_l => c64_base(7 downto 0) <= io_wdatau; c64_addr <= c64_base(15 downto 8) & io_wdatau; -- half autoload bug when c_c64base_h => c64_base(15 downto 8) <= io_wdatau; c64_addr <= io_wdatau & c64_base(7 downto 0); -- half autoload bug when c_reubase_l => reu_base(7 downto 0) <= io_wdatau; reu_addr(15 downto 0) <= reu_base(15 downto 8) & io_wdatau; -- half autoload bug when c_reubase_m => reu_base(15 downto 8) <= io_wdatau; reu_addr(15 downto 0) <= io_wdatau & reu_base(7 downto 0); -- half autoload bug when c_reubase_h => reu_base(23 downto 16) <= io_wdatau; reu_addr(23 downto 16) <= io_wdatau; when c_translen_l => length_reg(7 downto 0) <= io_wdatau; count(15 downto 0) <= length_reg(15 downto 8) & io_wdatau; -- half autoload bug when c_translen_h => length_reg(15 downto 8) <= io_wdatau; count(15 downto 0) <= io_wdatau & length_reg(7 downto 0); -- half autoload bug when c_irqmask => control.irq_en <= io_wdatau(7); control.irq_done <= io_wdatau(6); control.irq_error <= io_wdatau(5); when c_control => control.fix_reu <= io_wdatau(6); control.fix_c64 <= io_wdatau(7); when c_command => command.execute <= io_wdatau(7); reserved(2) <= io_wdatau(6); command.autoload <= io_wdatau(5); command.ff00 <= io_wdatau(4); reserved(1) <= io_wdatau(3); reserved(0) <= io_wdatau(2); command.mode <= slot_req.data(1 downto 0); when others => null; end case; end if; -- extended registers if io_write='1' and g_extended then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_start_delay => start_delay <= io_wdatau; when c_rate_div => rate_div <= io_wdatau; when c_translen_x => length_reg(23 downto 16) <= io_wdatau; count(23 downto 16) <= io_wdatau; when others => null; end case; end if; -- clear on read flags if io_read='1' then if slot_req.io_address(4 downto 0) = c_status then verify_error <= '0'; trans_done <= '0'; end if; end if; case state is when idle => reu_dma_n <= '1'; glob_rwn <= '1'; ext_count <= start_delay; if command.execute='1' then if (command.ff00='0' and write_ff00='1') or (command.ff00='1') then verify_error <= '0'; trans_done <= '0'; command.execute <= '0'; if g_extended then state <= delay; else dispatch; reu_dma_n <= '0'; end if; end if; end if; when delay => if ext_count = 0 then dispatch; reu_dma_n <= '0'; elsif phi2_tick='1' then ext_count <= ext_count - 1; end if; when do_read_reu => if reu_rack='1' then reu_req <= '0'; end if; if reu_dack='1' then reu_read_reg <= mem_resp.data; case command.mode is when c_mode_swap | c_mode_verify => c64_req <= '1'; glob_rwn <= '1'; state <= do_read_c64; when others => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; end case; end if; when do_write_c64 => if c64_rack='1' then c64_req <= '0'; next_address; state <= check_end; end if; when do_read_c64 => if c64_rack='1' then c64_req <= '0'; end if; if c64_dack='1' then c64_read_reg <= dma_resp.data; case command.mode is when c_mode_verify => if dma_resp.data /= reu_read_reg then verify_error <= '1'; state <= idle; else next_address; state <= check_end; end if; when others => reu_req <= '1'; glob_rwn <= '0'; state <= do_write_reu; end case; end if; when do_write_reu => if reu_rack='1' then reu_req <= '0'; case command.mode is when c_mode_swap => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; when others => next_address; state <= check_end; end case; end if; when check_end => ext_count <= rate_div; if trans_done='1' then transfer_end; elsif g_extended then state <= delay; else dispatch; end if; when others => null; end case; if reset='1' then reu_req <= '0'; c64_req <= '0'; glob_rwn <= '1'; control <= c_control_def; command <= c_command_def; state <= idle; reserved <= (others => '0'); verify_error <= '0'; trans_done <= '0'; reu_dma_n <= '1'; c64_base <= (others => '0'); reu_base <= (others => '0'); length_reg <= X"00FFFF"; c64_addr <= (others => '0'); reu_addr <= (others => '0'); count <= (others => '1'); rate_div <= (others => '0'); start_delay <= (others => '0'); rate_div <= (others => '0'); ext_count <= (others => '0'); end if; end if; end process; p_read: process(slot_req, control, command, count, c64_addr, reu_addr, verify_error, trans_done, irq_pend, c64_base, reu_base, length_reg, reserved, mask, start_delay, rate_div) begin io_rdata <= X"FF"; case slot_req.bus_address(4 downto 0) is when c_status => io_rdata(7) <= irq_pend; io_rdata(6) <= trans_done; io_rdata(5) <= verify_error; io_rdata(4) <= mask(1); -- for 256k and larger, this is set to '1'. io_rdata(3 downto 0) <= X"0"; -- version when c_command => io_rdata(7) <= command.execute; io_rdata(6) <= reserved(2); io_rdata(5) <= command.autoload; io_rdata(4) <= command.ff00; io_rdata(3 downto 2) <= reserved(1 downto 0); io_rdata(1 downto 0) <= command.mode; when c_irqmask => io_rdata(7) <= control.irq_en; io_rdata(6) <= control.irq_done; io_rdata(5) <= control.irq_error; when c_control => io_rdata(7) <= control.fix_c64; io_rdata(6) <= control.fix_reu; when c_c64base_l => io_rdata <= std_logic_vector(c64_addr(7 downto 0)); when c_c64base_h => io_rdata <= std_logic_vector(c64_addr(15 downto 8)); when c_reubase_l => io_rdata <= std_logic_vector(reu_addr(7 downto 0)); when c_reubase_m => io_rdata <= std_logic_vector(reu_addr(15 downto 8)); when c_reubase_h => if g_extended then io_rdata <= std_logic_vector(reu_addr(23 downto 16)); else io_rdata <= "11111" & std_logic_vector(reu_addr(18 downto 16)); -- maximum 19 bits end if; when c_translen_l => io_rdata <= std_logic_vector(count(7 downto 0)); when c_translen_h => io_rdata <= std_logic_vector(count(15 downto 8)); when c_size_read => if g_extended then io_rdata <= std_logic_vector(mask); end if; when c_start_delay => if g_extended then io_rdata <= std_logic_vector(start_delay); end if; when c_rate_div => if g_extended then io_rdata <= std_logic_vector(rate_div); end if; when others => null; end case; end process; irq_pend <= control.irq_en and ((control.irq_done and trans_done) or (control.irq_error and verify_error)); slot_resp.irq <= irq_pend; slot_resp.data <= io_rdata; slot_resp.reg_output <= enable when slot_req.bus_address(8 downto 5)=X"8" and slot_req.bus_address(4 downto 2)/="111" and (state = idle) else '0'; io_write <= (enable and slot_req.io_write) when slot_req.io_address(8 downto 5)=X"8" else '0'; io_read <= (enable and slot_req.io_read) when slot_req.io_address(8 downto 5)=X"8" else '0'; end gideon;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.reu_pkg.all; use work.mem_bus_pkg.all; use work.dma_bus_pkg.all; use work.slot_bus_pkg.all; -- Standard: 433 LUT/148 FF -- Extended: 564 LUT/195 FF entity reu is generic ( g_ram_tag : std_logic_vector(7 downto 0) := X"10"; g_extended : boolean := true; g_ram_base : unsigned(27 downto 0) := X"1000000" ); -- second (=upper 16M) port ( clock : in std_logic; reset : in std_logic; -- register interface slot_req : in t_slot_req; slot_resp : out t_slot_resp; -- system interface phi2_tick : in std_logic := '0'; reu_dma_n : out std_logic := '1'; size_ctrl : in std_logic_vector(2 downto 0) := "001"; enable : in std_logic; -- memory interface mem_req : out t_mem_req; mem_resp : in t_mem_resp; dma_req : out t_dma_req; dma_resp : in t_dma_resp ); end reu; -- The REU is actually really simple. -- There are 4 modes of operation, and 4 active states: -- r = reu read, w = reu write, R = c64 read, W = c64 write -- Copy from c64 to reu (00): Rw -- Copy from reu to c64 (01): rW -- Swap (10): rRwW (RrWw or rRWw or RrwW or rRwW) -- Verify (11): rR (Rr or rR) -- The smallest implementation is very likely when only one bit is needed to select between -- transition options, and reducing the total number of transitions makes sense too. architecture gideon of reu is type t_state is (idle, do_read_c64, do_write_c64, do_read_reu, do_write_reu, check_end, delay); signal state : t_state; attribute fsm_encoding : string; attribute fsm_encoding of state : signal is "one-hot"; signal io_wdatau : unsigned(7 downto 0); signal io_rdata : std_logic_vector(7 downto 0); signal io_write : std_logic; signal io_read : std_logic; signal c64_base : unsigned(15 downto 0) := (others => '0'); signal reu_base : unsigned(23 downto 0) := (others => '0'); signal length_reg : unsigned(23 downto 0) := (others => '1'); signal c64_addr : unsigned(15 downto 0) := (others => '0'); signal reu_addr : unsigned(23 downto 0) := (others => '0'); signal count : unsigned(23 downto 0) := (others => '1'); signal c64_req : std_logic; signal c64_rack : std_logic; signal c64_dack : std_logic; signal reu_req : std_logic; signal reu_rack : std_logic; signal reu_dack : std_logic; signal glob_rwn : std_logic; signal write_ff00 : std_logic; signal masked_reu_addr : unsigned(23 downto 0); signal mask : unsigned(7 downto 0); signal c64_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal reu_read_reg : std_logic_vector(7 downto 0) := (others => '0'); signal verify_error : std_logic; signal trans_done : std_logic; signal irq_pend : std_logic; signal reserved : std_logic_vector(2 downto 0); type t_control is record irq_en : std_logic; irq_done : std_logic; irq_error : std_logic; fix_reu : std_logic; fix_c64 : std_logic; end record; type t_command is record execute : std_logic; autoload : std_logic; ff00 : std_logic; mode : std_logic_vector(1 downto 0); end record; constant c_control_def : t_control := (others => '0'); constant c_command_def : t_command := ( mode => "00", execute => '0', ff00 => '1', autoload => '0' ); signal control : t_control; signal command : t_command; -- signals for extended mode signal rate_div : unsigned(7 downto 0) := (others => '0'); signal start_delay : unsigned(7 downto 0) := (others => '0'); signal ext_count : unsigned(7 downto 0) := (others => '0'); begin write_ff00 <= '1' when slot_req.late_write='1' and slot_req.io_address=X"FF00" else '0'; with size_ctrl select mask <= "00000001" when "000", "00000011" when "001", "00000111" when "010", "00001111" when "011", "00011111" when "100", "00111111" when "101", "01111111" when "110", "11111111" when others; masked_reu_addr(23 downto 19) <= (reu_base(23 downto 19) and mask(7 downto 3)) when not g_extended else (reu_addr(23 downto 19) and mask(7 downto 3)); masked_reu_addr(18 downto 16) <= (reu_addr(18 downto 16) and mask(2 downto 0)); masked_reu_addr(15 downto 0) <= reu_addr(15 downto 0); reu_rack <= '1' when mem_resp.rack_tag = g_ram_tag else '0'; reu_dack <= '1' when mem_resp.dack_tag = g_ram_tag else '0'; io_wdatau <= unsigned(slot_req.data); -- fill mem request structure mem_req.tag <= g_ram_tag; mem_req.request <= reu_req; mem_req.address <= g_ram_base(25 downto 24) & masked_reu_addr; mem_req.read_writen <= glob_rwn; mem_req.data <= c64_read_reg; mem_req.size <= "00"; -- 1 byte at a time -- fill dma request structure dma_req.request <= c64_req; dma_req.address <= c64_addr; dma_req.read_writen <= glob_rwn; dma_req.data <= reu_read_reg; c64_rack <= dma_resp.rack; c64_dack <= dma_resp.dack; p_main: process(clock) procedure next_address is begin if control.fix_c64='0' then c64_addr <= c64_addr + 1; end if; if control.fix_reu='0' then reu_addr <= reu_addr + 1; end if; if (count(15 downto 0) = 1 and not g_extended) or (count = 1 and g_extended) then trans_done <= '1'; else count <= count - 1; end if; end procedure; procedure transfer_end is begin if command.autoload='1' then c64_addr <= c64_base; reu_addr <= reu_base(reu_addr'range); if g_extended then count <= length_reg; else count(15 downto 0) <= length_reg(15 downto 0); end if; end if; command.ff00 <= '1'; -- reset to default state state <= idle; end procedure; procedure dispatch is begin glob_rwn <= '1'; -- we're going to read. case command.mode is when c_mode_toreu => -- C64 to REU c64_req <= '1'; state <= do_read_c64; when others => -- in all other cases, read reu first reu_req <= '1'; state <= do_read_reu; end case; end procedure; begin if rising_edge(clock) then if io_write='1' then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_c64base_l => c64_base(7 downto 0) <= io_wdatau; c64_addr <= c64_base(15 downto 8) & io_wdatau; -- half autoload bug when c_c64base_h => c64_base(15 downto 8) <= io_wdatau; c64_addr <= io_wdatau & c64_base(7 downto 0); -- half autoload bug when c_reubase_l => reu_base(7 downto 0) <= io_wdatau; reu_addr(15 downto 0) <= reu_base(15 downto 8) & io_wdatau; -- half autoload bug when c_reubase_m => reu_base(15 downto 8) <= io_wdatau; reu_addr(15 downto 0) <= io_wdatau & reu_base(7 downto 0); -- half autoload bug when c_reubase_h => reu_base(23 downto 16) <= io_wdatau; reu_addr(23 downto 16) <= io_wdatau; when c_translen_l => length_reg(7 downto 0) <= io_wdatau; count(15 downto 0) <= length_reg(15 downto 8) & io_wdatau; -- half autoload bug when c_translen_h => length_reg(15 downto 8) <= io_wdatau; count(15 downto 0) <= io_wdatau & length_reg(7 downto 0); -- half autoload bug when c_irqmask => control.irq_en <= io_wdatau(7); control.irq_done <= io_wdatau(6); control.irq_error <= io_wdatau(5); when c_control => control.fix_reu <= io_wdatau(6); control.fix_c64 <= io_wdatau(7); when c_command => command.execute <= io_wdatau(7); reserved(2) <= io_wdatau(6); command.autoload <= io_wdatau(5); command.ff00 <= io_wdatau(4); reserved(1) <= io_wdatau(3); reserved(0) <= io_wdatau(2); command.mode <= slot_req.data(1 downto 0); when others => null; end case; end if; -- extended registers if io_write='1' and g_extended then --$DF00-$DF1F, decoded below in a concurrent statement case slot_req.io_address(4 downto 0) is when c_start_delay => start_delay <= io_wdatau; when c_rate_div => rate_div <= io_wdatau; when c_translen_x => length_reg(23 downto 16) <= io_wdatau; count(23 downto 16) <= io_wdatau; when others => null; end case; end if; -- clear on read flags if io_read='1' then if slot_req.io_address(4 downto 0) = c_status then verify_error <= '0'; trans_done <= '0'; end if; end if; case state is when idle => reu_dma_n <= '1'; glob_rwn <= '1'; ext_count <= start_delay; if command.execute='1' then if (command.ff00='0' and write_ff00='1') or (command.ff00='1') then verify_error <= '0'; trans_done <= '0'; command.execute <= '0'; if g_extended then state <= delay; else dispatch; reu_dma_n <= '0'; end if; end if; end if; when delay => if ext_count = 0 then dispatch; reu_dma_n <= '0'; elsif phi2_tick='1' then ext_count <= ext_count - 1; end if; when do_read_reu => if reu_rack='1' then reu_req <= '0'; end if; if reu_dack='1' then reu_read_reg <= mem_resp.data; case command.mode is when c_mode_swap | c_mode_verify => c64_req <= '1'; glob_rwn <= '1'; state <= do_read_c64; when others => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; end case; end if; when do_write_c64 => if c64_rack='1' then c64_req <= '0'; next_address; state <= check_end; end if; when do_read_c64 => if c64_rack='1' then c64_req <= '0'; end if; if c64_dack='1' then c64_read_reg <= dma_resp.data; case command.mode is when c_mode_verify => if dma_resp.data /= reu_read_reg then verify_error <= '1'; state <= idle; else next_address; state <= check_end; end if; when others => reu_req <= '1'; glob_rwn <= '0'; state <= do_write_reu; end case; end if; when do_write_reu => if reu_rack='1' then reu_req <= '0'; case command.mode is when c_mode_swap => c64_req <= '1'; glob_rwn <= '0'; state <= do_write_c64; when others => next_address; state <= check_end; end case; end if; when check_end => ext_count <= rate_div; if trans_done='1' then transfer_end; elsif g_extended then state <= delay; else dispatch; end if; when others => null; end case; if reset='1' then reu_req <= '0'; c64_req <= '0'; glob_rwn <= '1'; control <= c_control_def; command <= c_command_def; state <= idle; reserved <= (others => '0'); verify_error <= '0'; trans_done <= '0'; reu_dma_n <= '1'; c64_base <= (others => '0'); reu_base <= (others => '0'); length_reg <= X"00FFFF"; c64_addr <= (others => '0'); reu_addr <= (others => '0'); count <= (others => '1'); rate_div <= (others => '0'); start_delay <= (others => '0'); rate_div <= (others => '0'); ext_count <= (others => '0'); end if; end if; end process; p_read: process(slot_req, control, command, count, c64_addr, reu_addr, verify_error, trans_done, irq_pend, c64_base, reu_base, length_reg, reserved, mask, start_delay, rate_div) begin io_rdata <= X"FF"; case slot_req.bus_address(4 downto 0) is when c_status => io_rdata(7) <= irq_pend; io_rdata(6) <= trans_done; io_rdata(5) <= verify_error; io_rdata(4) <= mask(1); -- for 256k and larger, this is set to '1'. io_rdata(3 downto 0) <= X"0"; -- version when c_command => io_rdata(7) <= command.execute; io_rdata(6) <= reserved(2); io_rdata(5) <= command.autoload; io_rdata(4) <= command.ff00; io_rdata(3 downto 2) <= reserved(1 downto 0); io_rdata(1 downto 0) <= command.mode; when c_irqmask => io_rdata(7) <= control.irq_en; io_rdata(6) <= control.irq_done; io_rdata(5) <= control.irq_error; when c_control => io_rdata(7) <= control.fix_c64; io_rdata(6) <= control.fix_reu; when c_c64base_l => io_rdata <= std_logic_vector(c64_addr(7 downto 0)); when c_c64base_h => io_rdata <= std_logic_vector(c64_addr(15 downto 8)); when c_reubase_l => io_rdata <= std_logic_vector(reu_addr(7 downto 0)); when c_reubase_m => io_rdata <= std_logic_vector(reu_addr(15 downto 8)); when c_reubase_h => if g_extended then io_rdata <= std_logic_vector(reu_addr(23 downto 16)); else io_rdata <= "11111" & std_logic_vector(reu_addr(18 downto 16)); -- maximum 19 bits end if; when c_translen_l => io_rdata <= std_logic_vector(count(7 downto 0)); when c_translen_h => io_rdata <= std_logic_vector(count(15 downto 8)); when c_size_read => if g_extended then io_rdata <= std_logic_vector(mask); end if; when c_start_delay => if g_extended then io_rdata <= std_logic_vector(start_delay); end if; when c_rate_div => if g_extended then io_rdata <= std_logic_vector(rate_div); end if; when others => null; end case; end process; irq_pend <= control.irq_en and ((control.irq_done and trans_done) or (control.irq_error and verify_error)); slot_resp.irq <= irq_pend; slot_resp.data <= io_rdata; slot_resp.reg_output <= enable when slot_req.bus_address(8 downto 5)=X"8" and slot_req.bus_address(4 downto 2)/="111" and (state = idle) else '0'; io_write <= (enable and slot_req.io_write) when slot_req.io_address(8 downto 5)=X"8" else '0'; io_read <= (enable and slot_req.io_read) when slot_req.io_address(8 downto 5)=X"8" else '0'; end gideon;
library IEEE; use IEEE.STD_LOGIC_1164.all; entity top is generic( N: integer := 4; M: integer := 8 ); port( clk : in STD_LOGIC; rst : in STD_LOGIC; COP : in std_logic; d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0); d2 : in STD_LOGIC_VECTOR(N-1 downto 0); r : out STD_LOGIC_VECTOR(2*N-1 downto 0); IRQ1, IRQ2 : out std_logic ); end top; architecture top of top is component control_unit port ( clk,rst : in STD_LOGIC; X: in STD_LOGIC_vector(10 downto 0); Y: out STD_LOGIC_vector(25 downto 1)); end component; component operational_unit port( clk,rst : in STD_LOGIC; y : in STD_LOGIC_VECTOR(25 downto 1); COP : in std_logic; d1 : in STD_LOGIC_VECTOR(2*N-1 downto 0); d2 : in STD_LOGIC_VECTOR(N-1 downto 0); rl, rh : out STD_LOGIC_VECTOR(N-1 downto 0); x : out STD_LOGIC_vector(10 downto 0); IRQ1, IRQ2 : out std_logic ); end component; signal y : std_logic_vector(25 downto 1); signal x : std_logic_vector(10 downto 0); signal nclk : std_logic; signal rl, rh : std_logic_vector(N-1 downto 0); begin nclk <= not clk; dd1 : control_unit port map (clk=>clk, rst=>rst, x=>x, y=>y); dd2 : operational_unit port map ( clk => clk, rst => rst, d1 => d1, d2 => d2, y => y, x => x, rl => rl, rh => rh, COP => COP, IRQ1 => IRQ1, IRQ2 => IRQ2 ); r <= rh & rl; end top;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library std; entity dynroi_process is generic ( CLK_PROC_FREQ : integer; BINIMG_SIZE : integer; IMG_SIZE : integer; ROI_SIZE : integer; COORD_SIZE : integer ); port ( clk_proc : in std_logic; reset_n : in std_logic; ---------------- dynamic parameters ports --------------- status_reg_enable_bit : in std_logic; status_reg_bypass_bit : in std_logic; status_reg_static_res_bit : in std_logic; inImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0); inImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0); BinImg_size_reg_in_w_reg : in std_logic_vector(11 downto 0); BinImg_size_reg_in_h_reg : in std_logic_vector(11 downto 0); out_size_reg_out_w_reg : in std_logic_vector(11 downto 0); out_size_reg_out_h_reg : in std_logic_vector(11 downto 0); ----------------------- BinImg flow --------------------- BinImg_data : in std_logic_vector(BINIMG_SIZE-1 downto 0); BinImg_fv : in std_logic; BinImg_dv : in std_logic; ------------------------ Img flow ----------------------- Img_data : in std_logic_vector(IMG_SIZE-1 downto 0); Img_fv : in std_logic; Img_dv : in std_logic; ------------------------ roi flow ----------------------- roi_data : out std_logic_vector(ROI_SIZE-1 downto 0); roi_fv : out std_logic; roi_dv : out std_logic; ----------------------- coord flow ---------------------- coord_data : out std_logic_vector(COORD_SIZE-1 downto 0); coord_fv : out std_logic; coord_dv : out std_logic ); end dynroi_process; architecture rtl of dynroi_process is constant X_COUNTER_SIZE : integer := 12; constant Y_COUNTER_SIZE : integer := 12; --process data_process vars --bin image reference coordinates signal xBin_pos : unsigned(X_COUNTER_SIZE-1 downto 0); signal yBin_pos : unsigned(Y_COUNTER_SIZE-1 downto 0); signal x_min : unsigned(X_COUNTER_SIZE-1 downto 0); signal x_max : unsigned(X_COUNTER_SIZE-1 downto 0); signal y_min : unsigned(Y_COUNTER_SIZE-1 downto 0); signal y_max : unsigned(Y_COUNTER_SIZE-1 downto 0); signal enabled : std_logic; --conversion offset from binImg to img signal conv_offset_x : unsigned(X_COUNTER_SIZE-1 downto 0); signal conv_offset_y : unsigned(Y_COUNTER_SIZE-1 downto 0); --Coord over serial line related vars signal frame_buffer : std_logic_vector(63 downto 0); signal frame_buffer_has_been_filled : std_logic; signal frame_buffer_has_been_sent : std_logic; signal frame_buffer_position : unsigned(6 downto 0); --Apply_roi signals signal x_temp : unsigned(X_COUNTER_SIZE-1 downto 0); signal y_temp : unsigned(Y_COUNTER_SIZE-1 downto 0); signal w_temp : unsigned(X_COUNTER_SIZE-1 downto 0); signal h_temp : unsigned(Y_COUNTER_SIZE-1 downto 0); begin ------------------------------------------------------------------------ apply_roi : process(clk_proc, reset_n) --img reference coordinates variable x : unsigned(X_COUNTER_SIZE-1 downto 0); variable y : unsigned(Y_COUNTER_SIZE-1 downto 0); variable w : unsigned(X_COUNTER_SIZE-1 downto 0); variable h : unsigned(Y_COUNTER_SIZE-1 downto 0); variable xImg_pos : unsigned(X_COUNTER_SIZE-1 downto 0); variable yImg_pos : unsigned(Y_COUNTER_SIZE-1 downto 0); begin if(reset_n='0') then -- reset pixel counters xImg_pos := to_unsigned(0, X_COUNTER_SIZE); yImg_pos := to_unsigned(0, Y_COUNTER_SIZE); -- reset ROI coord : default is central frame with param.w/h values x := (others => '0'); y := (others => '0'); w := (others => '0'); h := (others => '0'); x_temp <= (others => '0'); y_temp <= (others => '0'); w_temp <= (others => '0'); h_temp <= (others => '0'); roi_data <= (others => '0'); roi_dv <= '0'; roi_fv <= '0'; elsif(rising_edge(clk_proc)) then if Img_fv = '1' and enabled = '1' then roi_fv <= '1'; else roi_fv <= '0'; end if; roi_dv <= '0'; roi_data <= (others => '1'); --Updating last frame coordinates if frame_buffer_has_been_filled = '1' and enabled = '1' then x_temp <= unsigned(frame_buffer(X_COUNTER_SIZE-1 downto 0)); y_temp <= unsigned(frame_buffer(Y_COUNTER_SIZE+15 downto 16)); w_temp <= unsigned(frame_buffer(X_COUNTER_SIZE+31 downto 32)); h_temp <= unsigned(frame_buffer(Y_COUNTER_SIZE+47 downto 48)); end if; -- ROI action if Img_fv = '0' then --Update ROI coords x := x_temp; y := y_temp; w := w_temp; h := h_temp; --Reset pixel counters xImg_pos := to_unsigned(0, X_COUNTER_SIZE); yImg_pos := to_unsigned(0, Y_COUNTER_SIZE); else if Img_dv = '1' and enabled = '1' then --ROI if(yBin_pos >= y and yBin_pos < y + h and xBin_pos >= x and xBin_pos < x + w )then roi_dv <= '1'; roi_data <= Img_data; end if; --Pixel counter in img xImg_pos := xImg_pos + 1; if(xImg_pos=unsigned(inImg_size_reg_in_w_reg)) then yImg_pos := yImg_pos + 1; xImg_pos := to_unsigned(0, X_COUNTER_SIZE); end if; end if; end if; end if; end process; ------------------------------------------------------------------------ ------------------------------------------------------------------------ data_process : process (clk_proc, reset_n) -- Vars used to fill frame_buffer variable x_to_send : unsigned(X_COUNTER_SIZE-1 downto 0); variable y_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0); variable w_to_send : unsigned(X_COUNTER_SIZE-1 downto 0); variable h_to_send : unsigned(Y_COUNTER_SIZE-1 downto 0); begin if(reset_n='0') then xBin_pos <= to_unsigned(0, X_COUNTER_SIZE); yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE); --Cleaning frame coordinates x_max <= (others=>'0'); y_max <= (others=>'0'); x_min <= (others => '0'); y_min <= (others => '0'); --Cleaning frame buffer frame_buffer <= (others=>'0'); --Cleaning signals used to fill buffer frame_buffer_has_been_filled <= '0'; frame_buffer_has_been_sent <= '0'; coord_fv <= '0'; coord_dv <= '0'; coord_data <= (others=>'0'); --Cleaning flags enabled <= '0'; --Cleaning conv offset conv_offset_x <= (others => '0'); conv_offset_y <= (others => '0'); elsif(rising_edge(clk_proc)) then coord_fv <= '0'; coord_dv <= '0'; coord_data <= (others=>'0'); --offset calculation conv_offset_x <= (unsigned(inImg_size_reg_in_w_reg)-unsigned(BinImg_size_reg_in_w_reg))/2; conv_offset_y <= (unsigned(inImg_size_reg_in_h_reg)-unsigned(BinImg_size_reg_in_h_reg))/2; if(BinImg_fv = '0') then xBin_pos <= to_unsigned(0, X_COUNTER_SIZE); yBin_pos <= to_unsigned(0, Y_COUNTER_SIZE); -- if frame_buffer_has_been_filled = '0' then --We send frame coordinates only if there is something to send if enabled = '1' and frame_buffer_has_been_sent = '0' then if status_reg_bypass_bit = '1' then x_to_send := (others=>'0'); y_to_send := (others=>'0'); w_to_send := unsigned(inImg_size_reg_in_w_reg); h_to_send := unsigned(inImg_size_reg_in_h_reg); else ----roi resolution fixed by user if status_reg_static_res_bit = '1' then --something was detected if x_max > 0 then --checking top left corner position to ensure frame width is matching static_res if x_min + conv_offset_x > (unsigned(inImg_size_reg_in_w_reg)-unsigned(out_size_reg_out_w_reg)) then x_to_send := unsigned(inImg_size_reg_in_w_reg) - unsigned(out_size_reg_out_w_reg); else x_to_send := x_min + conv_offset_x; end if; if y_min + conv_offset_y > (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg)) then y_to_send := (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg)); else y_to_send := y_min + conv_offset_y; end if; w_to_send := unsigned(out_size_reg_out_w_reg) ; h_to_send := unsigned(out_size_reg_out_h_reg); else --nothing found x_to_send := (unsigned(inImg_size_reg_in_w_reg)-unsigned(out_size_reg_out_w_reg))/2 ; y_to_send := (unsigned(inImg_size_reg_in_h_reg)-unsigned(out_size_reg_out_h_reg))/2; w_to_send := unsigned(out_size_reg_out_w_reg); h_to_send := unsigned(out_size_reg_out_h_reg); end if; ----dynamic resolution for roi else --something was detected if x_max > 0 then x_to_send := x_min + conv_offset_x; y_to_send := y_min + conv_offset_y; w_to_send := x_max-x_min; h_to_send := y_max-y_min; else --nothing found -> empty rectangle at image center x_to_send := unsigned(inImg_size_reg_in_w_reg)/2; y_to_send := unsigned(inImg_size_reg_in_h_reg)/2; w_to_send := (others=>'0'); h_to_send := (others=>'0'); end if; end if; end if; --filling buffer with matching coordinates frame_buffer(X_COUNTER_SIZE-1 downto 0) <= std_logic_vector(x_to_send); frame_buffer(Y_COUNTER_SIZE+15 downto 16) <= std_logic_vector(y_to_send); frame_buffer(X_COUNTER_SIZE+31 downto 32) <= std_logic_vector(w_to_send); frame_buffer(Y_COUNTER_SIZE+47 downto 48) <= std_logic_vector(h_to_send); --zero padding, each value has 16 bits but only uses XY_COUNTER_SIZE bits frame_buffer(15 downto X_COUNTER_SIZE) <= (others=>'0'); frame_buffer(31 downto X_COUNTER_SIZE+16) <= (others=>'0'); frame_buffer(47 downto X_COUNTER_SIZE+32) <= (others=>'0'); frame_buffer(63 downto X_COUNTER_SIZE+48) <= (others=>'0'); -- Get buffer ready to send frame_buffer_has_been_filled <= '1'; frame_buffer_position <= (others=>'0') ; end if; --Cleaning frame coordinates x_max <= (others=>'0'); y_max <= (others=>'0'); x_min <= unsigned(BinImg_size_reg_in_w_reg); y_min <= unsigned(BinImg_size_reg_in_h_reg); --To prevent sending coord after reset of x/y_min/max frame_buffer_has_been_sent <= '1'; else --send roi coord coord_fv <= '1'; coord_dv <= '1'; coord_data <= frame_buffer(to_integer(frame_buffer_position)+7 downto to_integer(frame_buffer_position)); if frame_buffer_position >= 56 then frame_buffer_has_been_filled <= '0'; frame_buffer_has_been_sent <= '1'; else frame_buffer_position <= frame_buffer_position + to_unsigned(8, 7); end if; end if; enabled <= status_reg_enable_bit; else coord_fv <= '0'; coord_dv <= '0'; coord_data <= (others=>'0'); frame_buffer_has_been_sent <= '0'; if status_reg_enable_bit = '1' and enabled = '1' then if(BinImg_dv = '1' ) then --bin img pixel counter xBin_pos <= xBin_pos + 1; if(xBin_pos=unsigned(BinImg_size_reg_in_w_reg)-1) then yBin_pos <= yBin_pos + 1; xBin_pos <= to_unsigned(0, X_COUNTER_SIZE); end if; -- This will give the smallest area including all non-black points if BinImg_data /= (BinImg_data'range => '0') then if xBin_pos < x_min then x_min <= xBin_pos; end if; if xBin_pos > x_max then x_max <= xBin_pos; end if; -- if yBin_pos < y_min then y_min <= yBin_pos; end if; if yBin_pos > y_max then y_max <= yBin_pos; end if; end if; end if; else enabled <= '0'; end if; end if; end if; end process; end rtl;
----------------------------------------------------------------------------------------------------------------------- -- Author: -- -- Create Date: 09/11/2016 -- dd/mm/yyyy -- Module Name: test_spi_slaves -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Este bloque instancia dos bloques spi escalvos tal que la salida de datos de uno esta conectada a la entrada -- de datos del otro. Lo mismo sucede con la salida que indica un dato valido y la entrada write enable. Por lo tanto, -- si un bloque recibe un dato, en el proximo ciclo spi ese dato sera enviado por el otro bloque spi. -- ----------------------------------------------------------------------------------------------------------------------- LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; LIBRARY lpm; USE lpm.lpm_components.ALL; ENTITY test_spi_slaves IS PORT( m_clk : in std_logic; -- master clock m_reset : in std_logic; -- master reset ---- serial interface 1 ---- slave1_ssel_i : in std_logic := 'X'; -- spi bus slave select line slave1_sck_i : in std_logic := 'X'; -- spi bus sck slave1_mosi_i : in std_logic := 'X'; -- spi bus mosi output slave1_miso_o : out std_logic := 'X'; -- spi bus spi_miso_i input ---- serial interface 2 ---- slave2_ssel_i : in std_logic := 'X'; -- spi bus slave select line slave2_sck_i : in std_logic := 'X'; -- spi bus sck slave2_mosi_i : in std_logic := 'X'; -- spi bus mosi output slave2_miso_o : out std_logic := 'X' -- spi bus spi_miso_i input ); END test_spi_slaves; ARCHITECTURE synth OF test_spi_slaves IS ---- COMPONENTS COMPONENT spi_slave IS Generic ( N : positive := 16; -- 32bit serial word length is default CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default) CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase. PREFETCH : positive := 2); -- prefetch lookahead cycles Port ( clk_i : in std_logic := 'X'; -- internal interface clock (clocks di/do registers) spi_ssel_i : in std_logic := 'X'; -- spi bus slave select line spi_sck_i : in std_logic := 'X'; -- spi bus sck clock (clocks the shift register core) spi_mosi_i : in std_logic := 'X'; -- spi bus mosi input spi_miso_o : out std_logic := 'X'; -- spi bus spi_miso_o output di_req_o : out std_logic; -- preload lookahead data request line di_i : in std_logic_vector (N-1 downto 0) := (others => 'X'); -- parallel load data in (clocked in on rising edge of clk_i) wren_i : in std_logic := 'X'; -- user data write enable wr_ack_o : out std_logic; -- write acknowledge do_valid_o : out std_logic; -- do_o data valid strobe, valid during one clk_i rising edge. do_o : out std_logic_vector (N-1 downto 0); -- parallel output (clocked out on falling clk_i) --- debug ports: can be removed for the application circuit --- do_transfer_o : out std_logic; -- debug: internal transfer driver wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher rx_bit_next_o : out std_logic; -- debug: internal rx bit state_dbg_o : out std_logic_vector (3 downto 0); -- debug: internal state register sh_reg_dbg_o : out std_logic_vector (N-1 downto 0) -- debug: internal shift register ); END COMPONENT; ---- SIGNALS SIGNAL sg_slave1_di, sg_slave2_di : std_logic_vector(15 downto 0); SIGNAL sg_slave1_wren, sg_slave2_wren : std_logic; BEGIN ---- INSTANCES SLAVE_1: spi_slave PORT MAP ( clk_i => m_clk, spi_ssel_i => slave1_ssel_i, spi_sck_i => slave1_sck_i, spi_mosi_i => slave1_mosi_i, spi_miso_o => slave1_miso_o, di_i => sg_slave1_di, wren_i => sg_slave1_wren, do_valid_o => sg_slave2_wren, do_o => sg_slave2_di ); SLAVE_2: spi_slave PORT MAP ( clk_i => m_clk, spi_ssel_i => slave2_ssel_i, spi_sck_i => slave2_sck_i, spi_mosi_i => slave2_mosi_i, spi_miso_o => slave2_miso_o, di_i => sg_slave2_di, wren_i => sg_slave2_wren, do_valid_o => sg_slave1_wren, do_o => sg_slave1_di ); END synth;
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin -- federico.madotto (at) gmail.com -- coline.doebelin (at) gmail.com -- https://github.com/fmadotto/DS_bitcoin_miner -- sigma_0.vhd is part of DS_bitcoin_miner. -- DS_bitcoin_miner is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- DS_bitcoin_miner is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. library ieee; use ieee.std_logic_1164.all; entity sigma_0 is port ( x : in std_ulogic_vector(31 downto 0); -- first binary input o : out std_ulogic_vector(31 downto 0) -- output ); end entity sigma_0; architecture behav of sigma_0 is begin process(x) -- the process is woken up whenever the input change begin o <= to_stdulogicvector((to_bitvector(x) ror 7) xor (to_bitvector(x) ror 18) xor (to_bitvector(x) srl 3)); end process; end architecture behav;
------------------------------------------------------------------------------------- -- FILE NAME : pulse2pulse.vhd -- -- AUTHOR : Peter Kortekaas -- -- COMPANY : 4DSP -- -- ITEM : 1 -- -- UNITS : Entity - pulse2pulse -- architecture - pulse2pulse_syn -- -- LANGUAGE : VHDL -- ------------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------- -- DESCRIPTION -- =========== -- -- This file transfers a pulse from one clock domain (in_clk) to another (out_clk). -- ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_unsigned.all ; use ieee.std_logic_misc.all ; entity pulse2pulse is port ( in_clk : in std_logic; out_clk : in std_logic; rst : in std_logic; pulsein : in std_logic; inbusy : out std_logic; pulseout : out std_logic ); end pulse2pulse; architecture syn of pulse2pulse is ----------------------------------------------------------------------------------- --constant declarations ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --constant declarations ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --signal declarations ----------------------------------------------------------------------------------- signal out_set :std_logic; signal out_set_prev :std_logic; signal out_set_prev2 :std_logic; signal in_set :std_logic; signal outreset :std_logic; signal in_reset :std_logic; signal in_reset_prev :std_logic; signal in_reset_prev2:std_logic; ----------------------------------------------------------------------------------- --component declarations ----------------------------------------------------------------------------------- --********************************************************************************* begin --********************************************************************************* ----------------------------------------------------------------------------------- --component instantiations ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --synchronous processes ----------------------------------------------------------------------------------- in_proc:process(in_clk,rst) begin if(rst = '1') then in_reset <= '0'; in_reset_prev <= '0'; in_reset_prev2<= '0'; in_set <= '0'; elsif(in_clk'event and in_clk = '1') then --regitser a pulse on the pulse in port --reset the signal when the ouput has registerred the pulse if (in_reset_prev = '1' and in_reset_prev2 = '1') then in_set <= '0'; elsif (pulsein = '1') then in_set <= '1'; end if; --register the reset signal from the other clock domain --three times. double stage synchronising circuit --reduces the MTB in_reset <= outreset; in_reset_prev <= in_reset; in_reset_prev2 <= in_reset_prev; end if; end process in_proc; out_proc:process(out_clk,rst) begin if(rst = '1') then out_set <= '0'; out_set_prev <= '0'; out_set_prev2 <= '0'; outreset <= '0'; pulseout <= '0'; elsif(out_clk'event and out_clk = '1') then --generate a pulse on the outpput when the --set signal has travelled through the synchronising fip flops if (out_set_prev = '1' and out_set_prev2 = '0') then pulseout <= '1'; else pulseout <= '0'; end if; --feedback the corret reception of the set signal to reset the set pulse if (out_set_prev = '1' and out_set_prev2 = '1') then outreset <= '1'; elsif (out_set_prev = '0' and out_set_prev2 = '0') then outreset <= '0'; end if; --register the reset signal from the other clock domain --three times. double stage synchronising circuit --reduces the MTB out_set <= in_set; out_set_prev <= out_set; out_set_prev2 <= out_set_prev; end if; end process out_proc; ----------------------------------------------------------------------------------- --asynchronous processes ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --asynchronous mapping ----------------------------------------------------------------------------------- inbusy <= in_set or in_reset_prev; ------------------- ------------------- end syn;
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block S+NPt87NQpxvGaf7XnzMdP/fozLeYxnmGHUKXjdEjEGgTytddUHon/69Ruf3u2MpijL8bYh3YMYT BA51J62O2g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eWhq3M+oG4VhbsxAoFhy2N5ckPuOqfzYjFoOdIvnmFjZB0XUaUK9OjRWeAWJ+64PFaQYopky0Fq5 SkBYJ6qTTu19vcRrPzkFhidefwIdFd3RbpMr2hTYt72GeQEFiOqvjNTqKCDsYNOsePTj71Ipj5wd dL4PQcpPvGjWJDGFpag= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BKY5exne6X+eJLRV3fLUX3qUSafuGMa0WOMANSIXiCFfs+cajksxAlVfV88tCmYYHaWrhJlEPvQR xkT8LQoAnw+tZL4Ln8RKebWTRuAOjySqiXbo8wKwJn3Xv39necQ8/vETp7moOCtgUe3/HeVPPce4 baRQNPLxEaKezVhSVCk= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block a0XmVcGfv5DYijcftaZb1VKT3qaG0lBBjuA11+j48/VERbpZ0nci3Ixv6vTTp2coLRgRkdIm88X7 sH+2l+X74rn0QMI/s1D33046hbEIOJxTLbL/oRGFYB9Xatbwev8bjLFHBgV0G3dZlZKOwckD83JE wSFvi/Z0yJ195Mm8+UWSAsv33yOqFHNkAdlkHj7wtoZe6hAGcT4huN7BgmT60GSLVo24qBZKcJSe W4d2AVEllk5wTRpWTaC7c9QgQ1W+dk3140cdFRGBUXtynaV2aRH91pHkcVG9sQ3XqjBKvDbu4v6q FeyykQLxCbA7TH/GFMdp5XhjCoj9KE6GpRplQw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block I77KOiMugv8wDv3Qpz9ol3oVg4VmT2J8j1hDucKPSch2XyHXgKzaFSUzI0stUpCF6mhMBJJKaB7C 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------------------------------------------------------------------------------- -- Entity : openMAC Testbench ------------------------------------------------------------------------------- -- -- (c) B&R, 2012 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact office@br-automation.com -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- Design unit header -- library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; library work; use global.all; entity tbOpenMAC is end tbOpenMAC; architecture bhv of tbOpenMAC is ---- Component declarations ----- component busMaster generic( gAddrWidth : integer := 32; gDataWidth : integer := 32; gStimuliFile : string := "name_TB_stim.txt" ); port ( iAck : in std_logic; iClk : in std_logic; iEnable : in std_logic; iReaddata : in std_logic_vector(gDataWidth-1 downto 0); iRst : in std_logic; oAddress : out std_logic_vector(gAddrWidth-1 downto 0); oByteenable : out std_logic_vector(gDataWidth/8-1 downto 0); oDone : out std_logic; oRead : out std_logic; oSelect : out std_logic; oWrite : out std_logic; oWritedata : out std_logic_vector(gDataWidth-1 downto 0) ); end component; component clkgen generic( gPeriod : time := 20 ns ); port ( iDone : in std_logic; oClk : out std_logic ); end component; component edgeDet port ( clk : in std_logic; din : in std_logic; rst : in std_logic; any : out std_logic; falling : out std_logic; rising : out std_logic ); end component; component enableGen generic( gEnableDelay : time := 100 ns ); port ( iReset : in std_logic; oEnable : out std_logic; onEnable : out std_logic ); end component; component OpenMAC_DMAFifo generic( fifo_data_width_g : natural := 16; fifo_word_size_g : natural := 32; fifo_word_size_log2_g : natural := 5 ); port ( aclr : in std_logic; rd_clk : in std_logic; rd_req : in std_logic; wr_clk : in std_logic; wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0); wr_req : in std_logic; rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0); rd_empty : out std_logic; rd_full : out std_logic; rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); wr_empty : out std_logic; wr_full : out std_logic; wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) ); end component; component openmac_ethernet generic( dma_highadr_g : integer := 31; endian_g : string := "little"; gNumSmi : integer := 2; gen2ndCmpTimer_g : boolean := false; genHub_g : boolean := false; genPhyActLed_g : boolean := false; genSmiIO : boolean := true; gen_dma_observer_g : boolean := true; iPktBufSizeLog2_g : integer := 10; iPktBufSize_g : integer := 1024; m_burstcount_const_g : boolean := true; m_burstcount_width_g : integer := 4; m_data_width_g : integer := 16; m_rx_burst_size_g : integer := 16; m_rx_fifo_size_g : integer := 16; m_tx_burst_size_g : integer := 16; m_tx_fifo_size_g : integer := 16; simulate : boolean := false; useIntPktBuf_g : boolean := false; useRmii_g : boolean := true; useRxIntPktBuf_g : boolean := false ); port ( clk : in std_logic; clkx2 : in std_logic; m_clk : in std_logic; m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0'); m_readdatavalid : in std_logic; m_waitrequest : in std_logic; phy0_rx_dat : in std_logic_vector(1 downto 0); phy0_rx_dv : in std_logic; phy0_rx_err : in std_logic; phy0_smi_dio_I : in std_logic; phy1_rx_dat : in std_logic_vector(1 downto 0); phy1_rx_dv : in std_logic; phy1_rx_err : in std_logic; phy1_smi_dio_I : in std_logic; phyMii0_rx_clk : in std_logic; phyMii0_rx_dat : in std_logic_vector(3 downto 0); phyMii0_rx_dv : in std_logic; phyMii0_rx_err : in std_logic; phyMii0_tx_clk : in std_logic; phyMii1_rx_clk : in std_logic; phyMii1_rx_dat : in std_logic_vector(3 downto 0); phyMii1_rx_dv : in std_logic; phyMii1_rx_err : in std_logic; phyMii1_tx_clk : in std_logic; phy_smi_dio_I : in std_logic; pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0) := (others => '0'); pkt_byteenable : in std_logic_vector(3 downto 0); pkt_chipselect : in std_logic; pkt_clk : in std_logic; pkt_read : in std_logic; pkt_write : in std_logic; pkt_writedata : in std_logic_vector(31 downto 0); rst : in std_logic; s_address : in std_logic_vector(11 downto 0); s_byteenable : in std_logic_vector(1 downto 0); s_chipselect : in std_logic; s_read : in std_logic; s_write : in std_logic; s_writedata : in std_logic_vector(15 downto 0); t_address : in std_logic_vector(1 downto 0); t_byteenable : in std_logic_vector(3 downto 0); t_chipselect : in std_logic; t_read : in std_logic; t_write : in std_logic; t_writedata : in std_logic_vector(31 downto 0); act_led : out std_logic; m_address : out std_logic_vector(29 downto 0); m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0); m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0); m_read : out std_logic; m_write : out std_logic; m_writedata : out std_logic_vector(m_data_width_g-1 downto 0); mac_rx_irq : out std_logic; mac_tx_irq : out std_logic; phy0_rst_n : out std_logic; phy0_smi_clk : out std_logic; phy0_smi_dio_O : out std_logic; phy0_smi_dio_T : out std_logic; phy0_tx_dat : out std_logic_vector(1 downto 0); phy0_tx_en : out std_logic; phy1_rst_n : out std_logic; phy1_smi_clk : out std_logic; phy1_smi_dio_O : out std_logic; phy1_smi_dio_T : out std_logic; phy1_tx_dat : out std_logic_vector(1 downto 0); phy1_tx_en : out std_logic; phyMii0_tx_dat : out std_logic_vector(3 downto 0); phyMii0_tx_en : out std_logic; phyMii1_tx_dat : out std_logic_vector(3 downto 0); phyMii1_tx_en : out std_logic; phy_rst_n : out std_logic; phy_smi_clk : out std_logic; phy_smi_dio_O : out std_logic; phy_smi_dio_T : out std_logic; pkt_readdata : out std_logic_vector(31 downto 0); pkt_waitrequest : out std_logic; s_irq : out std_logic; s_readdata : out std_logic_vector(15 downto 0); s_waitrequest : out std_logic; t_irq : out std_logic; t_readdata : out std_logic_vector(31 downto 0); t_tog : out std_logic; t_waitrequest : out std_logic; phy0_smi_dio : inout std_logic := '1'; phy1_smi_dio : inout std_logic := '1'; phy_smi_dio : inout std_logic := '1' ); end component; component req_ack generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port ( clk : in std_logic; enable : in std_logic; rst : in std_logic; ack : out std_logic ); end component; ---- Architecture declarations ----- -- Click here to add additional declarations -- constant cAddrwidth : integer := 32; constant cDatawidth : integer := 16; constant cEnableLoop : boolean := true; constant cRmiiDelayExp : integer := 20; -- 2**10 constant cGenManCol : boolean := false; --collision with manual tx frame constant cGenAutoCol : boolean := false; --collision with auto tx frame constant cDmaDataWidth : integer := 32; constant cDmaBurstWidth : integer := 6; ---- Constants ----- constant DANGLING_INPUT_CONSTANT : std_logic := 'Z'; constant GND_CONSTANT : std_logic := '0'; ---- Signal declarations used on the diagram ---- signal ack : std_logic; signal busMasterDone : std_logic; signal clk100 : std_logic; signal clk50 : std_logic; signal done : std_logic := '1'; signal enable : std_logic; signal fifo_rd_empty : std_logic; signal fifo_rd_req : std_logic; signal fifo_wr_req : std_logic; signal fifo_wr_req_falling : std_logic; signal GND : std_logic; signal macDone : std_logic; signal m_read : std_logic; signal m_readdatavalid : std_logic; signal m_waitrequest : std_logic; signal m_write : std_logic; signal NET799 : std_logic; signal NET808 : std_logic; signal phy0_rx_dv : std_logic; signal phy0_rx_err : std_logic; signal phy0_tx_en : std_logic; signal phy1_rx_dv : std_logic; signal phy1_rx_err : std_logic; signal phy1_tx_en : std_logic; signal read : std_logic; signal reset : std_logic; signal rst : std_logic; signal sel : std_logic; signal s_chipselect : std_logic; signal s_read : std_logic; signal s_waitrequest : std_logic; signal s_write : std_logic; signal write : std_logic; signal address : std_logic_vector (cAddrwidth-1 downto 0); signal byteenable : std_logic_vector (cDatawidth/8-1 downto 0); signal fifo_rd_data : std_logic_vector (1 downto 0); signal fifo_rd_usedw : std_logic_vector (cRmiiDelayExp-1 downto 0); signal fifo_wr_data : std_logic_vector (1 downto 0); signal fifo_wr_done : std_logic_vector (31 downto 0); signal m_burstcount : std_logic_vector (cDmaBurstWidth-1 downto 0); signal m_burstcounter : std_logic_vector (cDmaBurstWidth-1 downto 0); signal phy0_rx_dat : std_logic_vector (1 downto 0); signal phy0_tx_dat : std_logic_vector (1 downto 0); signal phy1_rx_dat : std_logic_vector (1 downto 0); signal phy1_tx_dat : std_logic_vector (1 downto 0); signal readdata : std_logic_vector (cDatawidth-1 downto 0); signal s_address : std_logic_vector (11 downto 0); signal s_byteenable : std_logic_vector (1 downto 0); signal s_readdata : std_logic_vector (15 downto 0); signal s_writedata : std_logic_vector (15 downto 0); signal writedata : std_logic_vector (cDatawidth-1 downto 0); ---- Declaration for Dangling input ---- signal Dangling_Input_Signal : STD_LOGIC; begin ---- User Signal Assignments ---- --generate done signal done <= busMasterDone and macDone; --mac macDone <= '1'; -- write s_chipselect <= sel; s_read <= read; s_write <= write; s_address <= address(s_address'high+1 downto 1); s_byteenable <= byteenable; s_writedata <= writedata; -- read readdata <= s_readdata; ack <= not s_waitrequest; --master m_waitrequest <= not(m_read or m_write); m_readdatavalid <= '0' when unsigned(m_burstcounter) = 0 or m_write = '1' else not m_read; --phy if genNoRx : if not cEnableLoop generate begin phy0_rx_dv <= '0'; phy0_rx_err <= '0'; phy0_rx_dat <= "00"; end generate; phy1_rx_dv <= phy0_tx_en after 2500 ns when cGenManCol else phy0_tx_en after 2500 ns when cGenAutoCol and unsigned(fifo_wr_done) = 1 else '0'; phy1_rx_err <= '0'; phy1_rx_dat <= phy0_tx_dat after 2500 ns when cGenManCol else phy0_tx_dat after 2500 ns when cGenAutoCol and unsigned(fifo_wr_done) = 1 else "00"; fifo_wr_req <= phy0_tx_en; genLoop : if cEnableLoop generate begin fifo_wr_data <= phy0_tx_dat; phy0_rx_dv <= fifo_rd_req; phy0_rx_dat <= fifo_rd_data(1 downto 0); phy0_rx_err <= '0'; end generate; procFifoRdReq : process(clk50, reset) begin if reset = '1' then fifo_rd_req <= '0'; fifo_wr_done <= (others => '0'); elsif rising_edge(clk50) then if fifo_rd_empty = '1' then fifo_rd_req <= '0'; elsif fifo_wr_req_falling = '1' then fifo_rd_req <= '1' after 1 us; fifo_wr_done <= std_logic_vector(unsigned(fifo_wr_done) + 1); -- elsif unsigned(fifo_rd_usedw) > 106 and unsigned(fifo_wr_done) = 0 then -- fifo_rd_req <= '1'; -- after 1 us; -- fifo_wr_done <= std_logic_vector(unsigned(fifo_wr_done) + 1); end if; end if; end process; ---- Component instantiations ---- DUT : openmac_ethernet generic map ( dma_highadr_g => 29, endian_g => "little", gNumSmi => 2, gen2ndCmpTimer_g => false, genHub_g => true, genPhyActLed_g => false, genSmiIO => true, gen_dma_observer_g => true, iPktBufSizeLog2_g => 10, iPktBufSize_g => 1024, m_burstcount_const_g => true, m_burstcount_width_g => cDmaBurstWidth, m_data_width_g => cDmaDataWidth, m_rx_burst_size_g => 2**(cDmaBurstWidth-1), m_rx_fifo_size_g => 3*2**cDmaBurstWidth, m_tx_burst_size_g => 2**(cDmaBurstWidth-1), m_tx_fifo_size_g => 3*2**cDmaBurstWidth, simulate => false, useIntPktBuf_g => false, useRmii_g => true, useRxIntPktBuf_g => false ) port map( phyMii0_rx_dat(0) => Dangling_Input_Signal, phyMii0_rx_dat(1) => Dangling_Input_Signal, phyMii0_rx_dat(2) => Dangling_Input_Signal, phyMii0_rx_dat(3) => Dangling_Input_Signal, phyMii1_rx_dat(0) => Dangling_Input_Signal, phyMii1_rx_dat(1) => Dangling_Input_Signal, phyMii1_rx_dat(2) => Dangling_Input_Signal, phyMii1_rx_dat(3) => Dangling_Input_Signal, pkt_byteenable(0) => Dangling_Input_Signal, pkt_byteenable(1) => Dangling_Input_Signal, pkt_byteenable(2) => Dangling_Input_Signal, pkt_byteenable(3) => Dangling_Input_Signal, pkt_writedata(0) => Dangling_Input_Signal, pkt_writedata(1) => Dangling_Input_Signal, pkt_writedata(2) => Dangling_Input_Signal, pkt_writedata(3) => Dangling_Input_Signal, pkt_writedata(4) => Dangling_Input_Signal, pkt_writedata(5) => Dangling_Input_Signal, pkt_writedata(6) => Dangling_Input_Signal, pkt_writedata(7) => Dangling_Input_Signal, pkt_writedata(8) => Dangling_Input_Signal, pkt_writedata(9) => Dangling_Input_Signal, pkt_writedata(10) => Dangling_Input_Signal, pkt_writedata(11) => Dangling_Input_Signal, pkt_writedata(12) => Dangling_Input_Signal, pkt_writedata(13) => Dangling_Input_Signal, pkt_writedata(14) => Dangling_Input_Signal, pkt_writedata(15) => Dangling_Input_Signal, pkt_writedata(16) => Dangling_Input_Signal, pkt_writedata(17) => Dangling_Input_Signal, pkt_writedata(18) => Dangling_Input_Signal, pkt_writedata(19) => Dangling_Input_Signal, pkt_writedata(20) => Dangling_Input_Signal, pkt_writedata(21) => Dangling_Input_Signal, pkt_writedata(22) => Dangling_Input_Signal, pkt_writedata(23) => Dangling_Input_Signal, pkt_writedata(24) => Dangling_Input_Signal, pkt_writedata(25) => Dangling_Input_Signal, pkt_writedata(26) => Dangling_Input_Signal, pkt_writedata(27) => Dangling_Input_Signal, pkt_writedata(28) => Dangling_Input_Signal, pkt_writedata(29) => Dangling_Input_Signal, pkt_writedata(30) => Dangling_Input_Signal, pkt_writedata(31) => Dangling_Input_Signal, t_address(0) => Dangling_Input_Signal, t_address(1) => Dangling_Input_Signal, t_byteenable(0) => Dangling_Input_Signal, t_byteenable(1) => Dangling_Input_Signal, t_byteenable(2) => Dangling_Input_Signal, t_byteenable(3) => Dangling_Input_Signal, t_writedata(0) => Dangling_Input_Signal, t_writedata(1) => Dangling_Input_Signal, t_writedata(2) => Dangling_Input_Signal, t_writedata(3) => Dangling_Input_Signal, t_writedata(4) => Dangling_Input_Signal, t_writedata(5) => Dangling_Input_Signal, t_writedata(6) => Dangling_Input_Signal, t_writedata(7) => Dangling_Input_Signal, t_writedata(8) => Dangling_Input_Signal, t_writedata(9) => Dangling_Input_Signal, t_writedata(10) => Dangling_Input_Signal, t_writedata(11) => Dangling_Input_Signal, t_writedata(12) => Dangling_Input_Signal, t_writedata(13) => Dangling_Input_Signal, t_writedata(14) => Dangling_Input_Signal, t_writedata(15) => Dangling_Input_Signal, t_writedata(16) => Dangling_Input_Signal, t_writedata(17) => Dangling_Input_Signal, t_writedata(18) => Dangling_Input_Signal, t_writedata(19) => Dangling_Input_Signal, t_writedata(20) => Dangling_Input_Signal, t_writedata(21) => Dangling_Input_Signal, t_writedata(22) => Dangling_Input_Signal, t_writedata(23) => Dangling_Input_Signal, t_writedata(24) => Dangling_Input_Signal, t_writedata(25) => Dangling_Input_Signal, t_writedata(26) => Dangling_Input_Signal, t_writedata(27) => Dangling_Input_Signal, t_writedata(28) => Dangling_Input_Signal, t_writedata(29) => Dangling_Input_Signal, t_writedata(30) => Dangling_Input_Signal, t_writedata(31) => Dangling_Input_Signal, clk => clk50, clkx2 => clk100, m_burstcount => m_burstcount( cDmaBurstWidth-1 downto 0 ), m_burstcounter => m_burstcounter( cDmaBurstWidth-1 downto 0 ), m_clk => clk100, m_read => m_read, m_readdatavalid => m_readdatavalid, m_waitrequest => m_waitrequest, m_write => m_write, phy0_rx_dat => phy0_rx_dat, phy0_rx_dv => phy0_rx_dv, phy0_rx_err => phy0_rx_err, phy0_smi_dio_I => Dangling_Input_Signal, phy0_tx_dat => phy0_tx_dat, phy0_tx_en => phy0_tx_en, phy1_rx_dat => phy1_rx_dat, phy1_rx_dv => phy1_rx_dv, phy1_rx_err => phy1_rx_err, phy1_smi_dio_I => Dangling_Input_Signal, phy1_tx_dat => phy1_tx_dat, phy1_tx_en => phy1_tx_en, phyMii0_rx_clk => Dangling_Input_Signal, phyMii0_rx_dv => Dangling_Input_Signal, phyMii0_rx_err => Dangling_Input_Signal, phyMii0_tx_clk => Dangling_Input_Signal, phyMii1_rx_clk => Dangling_Input_Signal, phyMii1_rx_dv => Dangling_Input_Signal, phyMii1_rx_err => Dangling_Input_Signal, phyMii1_tx_clk => Dangling_Input_Signal, phy_smi_dio_I => Dangling_Input_Signal, pkt_chipselect => Dangling_Input_Signal, pkt_clk => Dangling_Input_Signal, pkt_read => Dangling_Input_Signal, pkt_write => Dangling_Input_Signal, rst => reset, s_address => s_address, s_byteenable => s_byteenable, s_chipselect => s_chipselect, s_read => s_read, s_readdata => s_readdata, s_waitrequest => s_waitrequest, s_write => s_write, s_writedata => s_writedata, t_chipselect => Dangling_Input_Signal, t_read => Dangling_Input_Signal, t_write => Dangling_Input_Signal ); RMII_DELAY : OpenMAC_DMAFifo generic map ( fifo_data_width_g => 2, fifo_word_size_g => 2**cRmiiDelayExp, fifo_word_size_log2_g => cRmiiDelayExp ) port map( aclr => reset, rd_clk => clk50, rd_data => fifo_rd_data( 1 downto 0 ), rd_empty => fifo_rd_empty, rd_req => fifo_rd_req, rd_usedw => fifo_rd_usedw( cRmiiDelayExp-1 downto 0 ), wr_clk => clk50, wr_data => fifo_wr_data( 1 downto 0 ), wr_req => fifo_wr_req ); TRIG_READ : edgeDet port map( clk => clk50, din => fifo_wr_req, falling => fifo_wr_req_falling, rst => rst ); U1 : clkgen generic map ( gPeriod => 20 ns ) port map( iDone => done, oClk => clk50 ); U2 : enableGen generic map ( gEnableDelay => 50 ns ) port map( iReset => GND, onEnable => reset ); U3 : enableGen generic map ( gEnableDelay => 100 ns ) port map( iReset => reset, oEnable => enable ); U4 : busMaster generic map ( gAddrWidth => cAddrwidth, gDataWidth => cDatawidth, gStimuliFile => "openMAC/tb/tbOpenMAC_stim.txt" ) port map( iAck => ack, iClk => clk50, iEnable => enable, iReaddata => readdata( cDatawidth-1 downto 0 ), iRst => reset, oAddress => address( cAddrwidth-1 downto 0 ), oByteenable => byteenable( cDatawidth/8-1 downto 0 ), oDone => busMasterDone, oRead => read, oSelect => sel, oWrite => write, oWritedata => writedata( cDatawidth-1 downto 0 ) ); U5 : req_ack generic map ( ack_delay_g => 1, zero_delay_g => true ) port map( ack => NET799, clk => clk50, enable => write, rst => reset ); U6 : req_ack generic map ( ack_delay_g => 1, zero_delay_g => false ) port map( ack => NET808, clk => clk50, enable => read, rst => reset ); ack <= NET808 or NET799; U8 : clkgen generic map ( gPeriod => 10 ns ) port map( iDone => done, oClk => clk100 ); ---- Power , ground assignment ---- GND <= GND_CONSTANT; ---- Dangling input signal assignment ---- Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT; end bhv;
architecture rtl of fifo is constant sig8 : record_type_3( element1(7 downto 0), element2(4 downto 0)(7 downto 0)( elementA(7 downto 0) , elementB(3 downto 0) ), element3(3 downto 0)(elementC(4 downto 1), elementD(1 downto 0)), element5( elementE (3 downto 0) (6 downto 0) , elementF(7 downto 0) ), element6(4 downto 0), element7(7 downto 0)); constant sig9 : t_data_struct(data(7 downto 0)); constant sig9 : t_data_struct( data(7 downto 0) ); begin end architecture rtl;
------------------------------------------------------------------------------- -- $Id: or_with_enable_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_with_enable_f ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. 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The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: or_with_enable_f.vhd -- -- Description: Y <= or_reduce(OR_bits) and Enable -- -- i.e., OR together the OR_bits and AND the result with Enable. -- -- The implementation uses a single LUT if possible. -- Otherwise, if C_FAMILY supports the carry chain concept, -- it uses a minimal number of LUTs on a carry chain. -- The native LUT size of C_FAMILY is taken into account. -- ------------------------------------------------------------------------------- -- Structure: Common use module ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 05/06/06 -- First version -- ~~~~~~ -- FLO 05/25/06 -- ^^^^^^ -- -Using native_lut_size function from family_support. -- -Moved C_FAMILY to end of generics. -- -Minor cleanup. -- ~~~~~~ -- FLO 11/17/07 -- ^^^^^^ -- -Work around because XST doesn't yet support or_reduce with null argument. -- ~~~~~~ -- -- DET 1/17/2008 v3_00_a -- ~~~~~~ -- - Changed proc_common library version to v3_00_a -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity or_with_enable_f is generic ( C_OR_WIDTH : natural; C_FAMILY : string := "nofamily" ); port ( OR_bits : in std_logic_vector(0 to C_OR_WIDTH-1); Enable : in std_logic; Y : out std_logic ); end or_with_enable_f; library proc_common_v3_00_a; use proc_common_v3_00_a.family_support.all; -- Makes visible the function 'supported' and related types, -- including enumeration literals for the unisim primitives (e.g. -- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.). library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture implementation of or_with_enable_f is ---------------------------------------------------------------------------- -- Here is determined the largest LUT width supported by the target family. -- If no LUT is supported, the width is set to a very large number, which, -- as things are structured, will cause an inferred implementation -- to be used. ---------------------------------------------------------------------------- constant LUT_SIZE : integer := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => integer'high ); ---------------------------------------------------------------------------- -- Here is determined which structural or inferred implementation to use. ---------------------------------------------------------------------------- constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and OR_bits'length + 1 > LUT_SIZE; -- Structural implementation not needed if the number of logic -- inputs, i.e., the Enable plus the number of bits to be ORed, -- will fit into a single LUT. constant USE_INFERRED : boolean := not USE_STRUCTURAL_A; ---------------------------------------------------------------------------- -- Reduction OR function. ---------------------------------------------------------------------------- function or_reduce (v : std_logic_vector) return std_logic is variable r : std_logic := '0'; begin for i in v'range loop r := r or v(i); end loop; return r; end; ---------------------------------------------------------------------------- -- Signal to recast OR_bits into a local array whose index bounds and -- direction are known. ---------------------------------------------------------------------------- signal OB : std_logic_vector(0 to OR_bits'length-1); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin OB <= OR_bits; ---------------------------------------------------------------------------- -- Inferred implementation. ---------------------------------------------------------------------------- INFERRED_GEN : if USE_INFERRED generate begin Y <= Enable and or_reduce(OB); end generate INFERRED_GEN; ---------------------------------------------------------------------------- -- Structural implementation. ---------------------------------------------------------------------------- STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate constant NUM_PURE_OR_LUTS : positive := (OB'length / LUT_SIZE); signal cy : std_logic_vector(0 to NUM_PURE_OR_LUTS); signal final_lut : std_logic; begin -- cy(0) <= '0'; -- PURE_OR_GEN : for i in 0 to NUM_PURE_OR_LUTS-1 generate signal lut : std_logic; begin lut <= not or_reduce(OB(i*LUT_SIZE to (i+1)*LUT_SIZE-1)); -- I_MUXCY : component MUXCY port map (O =>cy(i+1), CI=>cy(i), DI=>'1', S =>lut); end generate; -- XST_WA_GEN : if (OB'length mod LUT_SIZE) = 0 generate begin final_lut <= Enable; end generate; -- ORIG_GEN : if (OB'length mod LUT_SIZE) /= 0 generate begin final_lut <= Enable and not or_reduce(OB(NUM_PURE_OR_LUTS*LUT_SIZE to OB'right)); end generate; -- I_MUXCY_FINAL : component MUXCY port map (O =>Y, CI=>cy(NUM_PURE_OR_LUTS), DI=>Enable, S =>final_lut); -- end generate STRUCTURAL_A_GEN; end implementation;
-- ------------------------------------------------------------- -- -- Generated Configuration for ent_ae -- -- Generated -- by: wig -- on: Mon Jul 18 16:07:27 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: ent_ae-rtl-conf-c.vhd,v 1.4 2005/07/19 07:13:20 wig Exp $ -- $Date: 2005/07/19 07:13:20 $ -- $Log: ent_ae-rtl-conf-c.vhd,v $ -- Revision 1.4 2005/07/19 07:13:20 wig -- Update testcases. Added highlow/nolowbus -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration ent_ae_rtl_conf / ent_ae -- configuration ent_ae_rtl_conf of ent_ae is for rtl -- Generated Configuration end for; end ent_ae_rtl_conf; -- -- End of Generated Configuration ent_ae_rtl_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use ieee.math_real.all; use std.textio.all; use ieee.std_logic_misc.all; package TB_Package is function CX_GEN(current_address, network_x, network_y : integer) return integer; procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; -- NI configuration signal reserved_address : in std_logic_vector(29 downto 0); signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O signal counter_address : in std_logic_vector(29 downto 0); signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register -- NI signals signal enable: out std_logic; signal write_byte_enable: out std_logic_vector(3 downto 0); signal address: out std_logic_vector(31 downto 2); signal data_write: out std_logic_vector(31 downto 0); signal data_read: in std_logic_vector(31 downto 0); signal test: out std_logic_vector(31 downto 0)); end TB_Package; package body TB_Package is constant Header_type : std_logic_vector := "001"; constant Body_type : std_logic_vector := "010"; constant Tail_type : std_logic_vector := "100"; function CX_GEN(current_address, network_x, network_y: integer) return integer is variable X, Y : integer := 0; variable CN, CE, CW, CS : std_logic := '0'; variable CX : std_logic_vector(3 downto 0); begin X := current_address mod network_x; Y := current_address / network_x; if X /= 0 then CW := '1'; end if; if X /= network_x-1 then CE := '1'; end if; if Y /= 0 then CN := '1'; end if; if Y /= network_y-1 then CS := '1'; end if; CX := CS&CW&CE&CN; return to_integer(unsigned(CX)); end CX_GEN; procedure NI_control(network_x, network_y, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer; finish_time: in time; signal clk: in std_logic; -- NI configuration signal reserved_address : in std_logic_vector(29 downto 0); signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O signal counter_address : in std_logic_vector(29 downto 0); signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register -- NI signals signal enable: out std_logic; signal write_byte_enable: out std_logic_vector(3 downto 0); signal address: out std_logic_vector(31 downto 2); signal data_write: out std_logic_vector(31 downto 0); signal data_read: in std_logic_vector(31 downto 0); signal test: out std_logic_vector(31 downto 0)) is -- variables for random functions constant DATA_WIDTH : integer := 32; variable seed1 :positive := current_address+1; variable seed2 :positive := current_address+1; variable rand : real ; --file handling variables variable SEND_LINEVARIABLE : line; file SEND_FILE : text; variable RECEIVED_LINEVARIABLE : line; file RECEIVED_FILE : text; -- receiving variables variable receive_source_node, receive_destination_node, receive_packet_id, receive_counter, receive_packet_length: integer; -- sending variables variable send_destination_node, send_counter, send_id_counter: integer:= 0; variable send_packet_length: integer:= 8; type state_type is (Idle, Header_flit, Body_flit, Body_flit_1, Tail_flit); variable state : state_type; variable frame_starting_delay : integer:= 0; variable frame_counter: integer:= 0; variable first_packet : boolean := True; begin file_open(RECEIVED_FILE,"received.txt",WRITE_MODE); file_open(SEND_FILE,"sent.txt",WRITE_MODE); enable <= '1'; state := Idle; send_packet_length := min_packet_size; uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size-1)))/100); wait until clk'event and clk ='0'; address <= reconfiguration_address; wait until clk'event and clk ='0'; write_byte_enable <= "1111"; data_write <= "00000000000000000000" & std_logic_vector(to_unsigned(CX_GEN(current_address, network_x, network_y), 4)) & std_logic_vector(to_unsigned(60, 8)); wait until clk'event and clk ='0'; write_byte_enable <= "0000"; data_write <= (others =>'0'); while true loop -- read the flag status address <= flag_address; write_byte_enable <= "0000"; wait until clk'event and clk ='0'; --flag register is organized like this: -- .-------------------------------------------------. -- | N2P_empty | P2N_full | ...| -- '-------------------------------------------------' if data_read(31) = '0' then -- N2P is not empty, can receive flit -- read the received data status address <= counter_address; write_byte_enable <= "0000"; wait until clk'event and clk ='0'; -- read the received data status address <= reserved_address; write_byte_enable <= "0000"; wait until clk'event and clk ='0'; if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit receive_destination_node := to_integer(unsigned(data_read(14 downto 8)))* network_x+to_integer(unsigned(data_read(7 downto 1))); receive_source_node :=to_integer(unsigned(data_read(28 downto 22)))* network_x+to_integer(unsigned(data_read(21 downto 15))); receive_counter := 1; end if; if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit if receive_counter = 1 then receive_packet_length := to_integer(unsigned(data_read(28 downto 15))); receive_packet_id := to_integer(unsigned(data_read(14 downto 1))); end if; receive_counter := receive_counter+1; end if; if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit receive_counter := receive_counter+1; write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id)); writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE); end if; elsif data_read(30) = '0' then -- P2N is not full, can send flit if frame_counter >= frame_starting_delay then if state = Idle and now < finish_time then if frame_counter < frame_starting_delay+1 then state := Header_flit; send_counter := send_counter+1; -- generating the destination address uniform(seed1, seed2, rand); send_destination_node := integer(rand*real((network_x*network_y)-1)); while (send_destination_node = current_address) loop uniform(seed1, seed2, rand); send_destination_node := integer(rand*real((network_x*network_y)-1)); end loop; --generating the packet length uniform(seed1, seed2, rand); send_packet_length := integer((integer(rand*100.0)*frame_length)/300); if (send_packet_length < min_packet_size) then send_packet_length:=min_packet_size; end if; if (send_packet_length > max_packet_size) then send_packet_length:=max_packet_size; end if; -- this is the header flit address <= reserved_address; write_byte_enable <= "1111"; data_write <= "0000" & std_logic_vector(to_unsigned(current_address/network_x, 7)) & std_logic_vector(to_unsigned(current_address mod network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node/network_x, 7)) & std_logic_vector(to_unsigned(send_destination_node mod network_x, 7)); write(SEND_LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(current_address) & " to " & integer'image(send_destination_node) & " with length: "& integer'image(send_packet_length) & " id: " & integer'image(send_id_counter)); writeline(SEND_FILE, SEND_LINEVARIABLE); else state := Idle; end if; elsif state = Header_flit then -- first body flit address <= reserved_address; write_byte_enable <= "1111"; if first_packet = True then data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14)); else data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14)); end if; send_counter := send_counter+1; state := Body_flit; elsif state = Body_flit then -- rest of body flits address <= reserved_address; write_byte_enable <= "1111"; uniform(seed1, seed2, rand); data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28)); send_counter := send_counter+1; if send_counter = send_packet_length-1 then state := Tail_flit; else state := Body_flit; end if; elsif state = Tail_flit then -- tail flit address <= reserved_address; write_byte_enable <= "1111"; if first_packet = True then data_write <= "0000" & "0000000000000000000000000000"; first_packet := False; else uniform(seed1, seed2, rand); data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28)); end if; send_counter := 0; state := Idle; send_id_counter := send_id_counter + 1; if send_id_counter = 16384 then send_id_counter := 0; end if; end if; end if; frame_counter := frame_counter + 1; if frame_counter = frame_length then frame_counter := 0; uniform(seed1, seed2, rand); frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size)))/100); end if; wait until clk'event and clk ='0'; end if; end loop; file_close(SEND_FILE); file_close(RECEIVED_FILE); end NI_control; end TB_Package;
package fred2 is function hi_there return string; end package fred2; package body fred2 is type line is access string; function hi_there return string is variable ln : line; begin if null = ln then -- Was error return "Proper initial value for access type."; else return "Compiler error."; end if; end function hi_there; end package body fred2;
package fred2 is function hi_there return string; end package fred2; package body fred2 is type line is access string; function hi_there return string is variable ln : line; begin if null = ln then -- Was error return "Proper initial value for access type."; else return "Compiler error."; end if; end function hi_there; end package body fred2;
package fred2 is function hi_there return string; end package fred2; package body fred2 is type line is access string; function hi_there return string is variable ln : line; begin if null = ln then -- Was error return "Proper initial value for access type."; else return "Compiler error."; end if; end function hi_there; end package body fred2;
package fred2 is function hi_there return string; end package fred2; package body fred2 is type line is access string; function hi_there return string is variable ln : line; begin if null = ln then -- Was error return "Proper initial value for access type."; else return "Compiler error."; end if; end function hi_there; end package body fred2;
package fred2 is function hi_there return string; end package fred2; package body fred2 is type line is access string; function hi_there return string is variable ln : line; begin if null = ln then -- Was error return "Proper initial value for access type."; else return "Compiler error."; end if; end function hi_there; end package body fred2;
-------------------------------------------------------------------------------- --Copyright (c) 2014, Benjamin Bässler <ccl@xunit.de> --All rights reserved. -- --Redistribution and use in source and binary forms, with or without --modification, are permitted provided that the following conditions are met: -- --* Redistributions of source code must retain the above copyright notice, this -- list of conditions and the following disclaimer. -- --* Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- --THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" --AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE --IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE --DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE --FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL --DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR --SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER --CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, --OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE --OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -------------------------------------------------------------------------------- --! @file labeling_box.vhd --! @brief Connected Component Labeling two pass and computation of bound boxes --! @author Benjamin Bässler --! @email ccl@xunit.de --! @date 2013-06-04 -------------------------------------------------------------------------------- --! Use standard library library ieee; --! Use numeric std use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; use work.types.all; use work.utils.all; --! The two pass algorithem implemented in labeling.vhd --! will be run and the output of labels used to compute --! the bound boxes with the boundbox.vhd. --! The boundbox has a internal heap to store boundboxes --! if the memory is to small the the error signal will --! rise and the output of the boxes is incompleat entity labeling_box is generic( --! Max image width means 2^... G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH; --! Max image width means 2^... G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT ); port( --! Clock input clk_in : in STD_LOGIC; --! Reset input rst_in : in STD_LOGIC; --! Output if the labeling stalls stall_out : out STD_LOGIC; --! Input to stall the output of the labeling stall_in : in STD_LOGIC; --! input data are valid data_valid_in : in STD_LOGIC; --! Pixel input 0 => background, 1=> foreground px_in : in STD_LOGIC; --! width of the image at the input img_width_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) downto 0); --! height of the image img_height_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) downto 0); --! High if the boundbox output valid box_valid_out : out STD_LOGIC; --! output of bound box upper x box_start_x_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0); --! output of bound box upper y box_start_y_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) - 1 downto 0); --! output of bound box lower x box_end_x_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0); --! output of bound box lower y box_end_y_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) - 1 downto 0); --! high if all boxes are computed box_done_out : out STD_LOGIC; --! Error Type out error_type_out : out STD_LOGIC_VECTOR(C_ERR_REF_SIZE - 1 downto 0) ); end entity labeling_box; --! @brief arc description --! @details more detailed description architecture labeling_box_arc of labeling_box is --! How many boxing instances should be provided constant C_BOX_INSTANCES : NATURAL := 2; type T_BOXES is array (C_BOX_INSTANCES - 1 downto 0) of T_BOX; --! State machine type T_STATE is (IDLE, LABELING, BOXES, FIFO_READ); type T_STATES is array(C_BOX_INSTANCES - 1 downto 0) of T_STATE; signal pipe_state : T_STATES; signal stall_lbl_s : STD_LOGIC; signal data_valid_lbl_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0); signal valid_lbl_out_s : STD_LOGIC; signal last_lbl_s : STD_LOGIC; signal label_s : STD_LOGIC_VECTOR(T_LABEL'RANGE); signal box_rst_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0); signal box_done_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0); signal ff_box_out_s : T_BOXES; signal ff_box_in_s : T_BOXES; signal ff_wr_valid_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0); signal ff_rd_next_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0); signal ff_empty_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0); signal err_lbl_s : STD_LOGIC_VECTOR(C_BOX_INSTANCES-1 downto 0); signal box_out_s : T_BOX; --! instance to use for first stage input signal use_st_1_in_s : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0); signal use_st_1_out_s : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0); --! which boundbox should be used for input next signal next_input_s : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0); function inst_inc ( inst : in unsigned) return unsigned is variable ret_val : unsigned(log2_ceil(C_BOX_INSTANCES)-1 downto 0); begin if inst = C_BOX_INSTANCES - 1 then ret_val := (others => '0'); else ret_val := inst + 1; end if; return ret_val; end function inst_inc; begin box_start_x_out <= STD_LOGIC_VECTOR(box_out_s(T_X_START)); box_start_y_out <= STD_LOGIC_VECTOR(box_out_s(T_Y_START)); box_end_x_out <= STD_LOGIC_VECTOR(box_out_s(T_X_END)); box_end_y_out <= STD_LOGIC_VECTOR(box_out_s(T_Y_END)); box_out_s <= ff_box_out_s(to_integer(use_st_1_out_s)); error_type_out(0) <= '0'; p_valid_out : process(clk_in) is begin if rising_edge(clk_in) then if pipe_state(to_integer(use_st_1_out_s)) = FIFO_READ and ff_empty_s(to_integer(use_st_1_out_s)) = '0'then box_valid_out <= '1'; else box_valid_out <= '0'; end if; end if; end process; p_pipe_state : process(clk_in) is variable next_input_sel_v : boolean; begin if rising_edge(clk_in) then if rst_in = '1' then pipe_state <= (others => IDLE); pipe_state(0) <= LABELING; next_input_s <= to_unsigned(1, next_input_s'length); use_st_1_out_s <= (others => '0'); use_st_1_in_s <= (others => '0'); box_rst_s <= (others => '1'); box_done_out <= '0'; else next_input_sel_v := false; box_done_out <= '0'; for i in C_BOX_INSTANCES - 1 downto 0 loop box_rst_s(i) <= '0'; case pipe_state(i) is when IDLE => if next_input_s = i and last_lbl_s = '1' then pipe_state(i) <= LABELING; next_input_s <= inst_inc(next_input_s); end if; when LABELING => if last_lbl_s = '1' then pipe_state(i) <= BOXES; use_st_1_in_s <= next_input_s; end if; when BOXES => if box_done_s(i) = '1' then pipe_state(i) <= FIFO_READ; box_rst_s(i) <= '1'; end if; when FIFO_READ => if ff_empty_s(i) = '1' then pipe_state(i) <= IDLE; use_st_1_out_s <= inst_inc(use_st_1_out_s); box_done_out <= '1'; end if; end case; end loop; end if; -- rst end if; --clk end process p_pipe_state; my_labeling : entity work.labeling PORT MAP( clk_in => clk_in, rst_in => rst_in, stall_out => stall_lbl_s, stall_in => stall_in, px_in => px_in, img_width_in => img_width_in, img_height_in => img_height_in, data_valid_out => valid_lbl_out_s, data_valid_in => data_valid_in, last_lbl_out => last_lbl_s, label_out => label_s, error_out => error_lbl_s ); gen_boxes : for i in C_BOX_INSTANCES - 1 downto 0 generate boundbox : entity work.boundbox PORT MAP( clk_in => clk_in, rst_in => box_rst_s(i), stall_in => stall_in, lbl_valid_in => data_valid_lbl_s(i), label_in => UNSIGNED(label_s), box_valid_out => ff_wr_valid_s(i), box_out => ff_box_in_s(i), box_done_out => box_done_s(i), error_out => open, img_width_in => UNSIGNED(img_width_in), img_height_in => UNSIGNED(img_height_in) ); box_fifo : entity work.fifo GENERIC MAP( G_SIZE => G_MAX_IMG_WIDTH/2*G_MAX_IMG_HEIGHT/2, G_WORD_WIDTH => T_BOX'LENGTH, G_ALMOST_EMPTY => 1, G_ALMOST_FULL => 64 - 1 ) PORT MAP( rst_in => rst_in, clk_in => clk_in, wr_d_in => ff_box_in_s(i), wr_valid_in => ff_wr_valid_s(i), almost_full_out => open, full_out => open, rd_d_out => ff_box_out_s(i), rd_next_in => ff_rd_next_s(i), almost_empty_out => open, empty_out => ff_empty_s(i) ); data_valid_lbl_s(i) <= valid_lbl_out_s when i = use_st_1_in_s else '0'; ff_rd_next_s(i) <= not ff_empty_s(i) when pipe_state(to_integer(use_st_1_out_s)) = FIFO_READ else '0'; end generate gen_boxes; end labeling_box_arc;
library ieee; use ieee.std_logic_1164.all; entity cmp_160 is port ( eq : out std_logic; in0 : in std_logic_vector(2 downto 0); in1 : in std_logic_vector(2 downto 0) ); end cmp_160; architecture augh of cmp_160 is signal tmp : std_logic; begin -- Compute the result tmp <= '0' when in0 /= in1 else '1'; -- Set the outputs eq <= tmp; end architecture;
library ieee; use ieee.std_logic_1164.all; entity cmp_160 is port ( eq : out std_logic; in0 : in std_logic_vector(2 downto 0); in1 : in std_logic_vector(2 downto 0) ); end cmp_160; architecture augh of cmp_160 is signal tmp : std_logic; begin -- Compute the result tmp <= '0' when in0 /= in1 else '1'; -- Set the outputs eq <= tmp; end architecture;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc400.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p08n01i00400ent IS END c03s02b01x01p08n01i00400ent; ARCHITECTURE c03s02b01x01p08n01i00400arch OF c03s02b01x01p08n01i00400ent IS type MEM is array (positive range <>) of BIT; attribute X : MEM; attribute X of MEM: type is ('1','0','1') ; -- No_failure_here BEGIN TESTING: PROCESS BEGIN assert NOT(MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1') report "***PASSED TEST: c03s02b01x01p08n01i00400" severity NOTE; assert (MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1') report "***FAILED TEST: c03s02b01x01p08n01i00400 - " severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p08n01i00400arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc400.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p08n01i00400ent IS END c03s02b01x01p08n01i00400ent; ARCHITECTURE c03s02b01x01p08n01i00400arch OF c03s02b01x01p08n01i00400ent IS type MEM is array (positive range <>) of BIT; attribute X : MEM; attribute X of MEM: type is ('1','0','1') ; -- No_failure_here BEGIN TESTING: PROCESS BEGIN assert NOT(MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1') report "***PASSED TEST: c03s02b01x01p08n01i00400" severity NOTE; assert (MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1') report "***FAILED TEST: c03s02b01x01p08n01i00400 - " severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p08n01i00400arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc400.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x01p08n01i00400ent IS END c03s02b01x01p08n01i00400ent; ARCHITECTURE c03s02b01x01p08n01i00400arch OF c03s02b01x01p08n01i00400ent IS type MEM is array (positive range <>) of BIT; attribute X : MEM; attribute X of MEM: type is ('1','0','1') ; -- No_failure_here BEGIN TESTING: PROCESS BEGIN assert NOT(MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1') report "***PASSED TEST: c03s02b01x01p08n01i00400" severity NOTE; assert (MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1') report "***FAILED TEST: c03s02b01x01p08n01i00400 - " severity ERROR; wait; END PROCESS TESTING; END c03s02b01x01p08n01i00400arch;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes is PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0); WR_ACK : OUT std_logic; VALID : OUT std_logic; ALMOST_EMPTY : OUT std_logic; SRST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(74-1 DOWNTO 0); DOUT : OUT std_logic_vector(74-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes; architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_3_3_exdes is signal clk_i : std_logic; component system_axi_vdma_0_wrapper_fifo_generator_v9_3_3 is PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0); WR_ACK : OUT std_logic; VALID : OUT std_logic; ALMOST_EMPTY : OUT std_logic; SRST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(74-1 DOWNTO 0); DOUT : OUT std_logic_vector(74-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin clk_buf: bufg PORT map( i => CLK, o => clk_i ); exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_3_3 PORT MAP ( CLK => clk_i, DATA_COUNT => data_count, WR_ACK => wr_ack, VALID => valid, ALMOST_EMPTY => almost_empty, SRST => srst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ library techmap; use techmap.gencomp.all; package config is -- Technology and synthesis options constant CFG_FABTECH : integer := stratix2; constant CFG_MEMTECH : integer := stratix2; constant CFG_PADTECH : integer := stratix2; constant CFG_TRANSTECH : integer := GTP0; constant CFG_NOASYNC : integer := 0; constant CFG_SCAN : integer := 0; -- Clock generator constant CFG_CLKTECH : integer := stratix2; constant CFG_CLKMUL : integer := (5); constant CFG_CLKDIV : integer := (5); constant CFG_OCLKDIV : integer := 1; constant CFG_OCLKBDIV : integer := 0; constant CFG_OCLKCDIV : integer := 0; constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 16#32# + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; constant CFG_SVT : integer := 1; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 0; constant CFG_NWP : integer := (2); constant CFG_PWD : integer := 1*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 2; constant CFG_ISETSZ : integer := 4; constant CFG_ILINE : integer := 8; constant CFG_IREPL : integer := 2; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 1; constant CFG_DSETSZ : integer := 4; constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; constant CFG_MMUEN : integer := 0; constant CFG_ITLBNUM : integer := 2; constant CFG_DTLBNUM : integer := 2; constant CFG_TLB_TYPE : integer := 1 + 0*2; constant CFG_TLB_REP : integer := 1; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; constant CFG_ITBSZ : integer := 2 + 64*0; constant CFG_ATBSZ : integer := 2; constant CFG_AHBPF : integer := 0; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; constant CFG_RF_ERRINJ : integer := 0; constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; constant CFG_NP_ASI : integer := 0; constant CFG_WRPSR : integer := 0; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 0; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; constant CFG_AHB_MONERR : integer := 0; constant CFG_AHB_MONWAR : integer := 0; constant CFG_AHB_DTRACE : integer := 0; -- DSU UART constant CFG_AHB_UART : integer := 1; -- JTAG based DSU interface constant CFG_AHB_JTAG : integer := 1; -- SDRAM controller constant CFG_SDCTRL : integer := 1; constant CFG_SDCTRL_INVCLK : integer := 0; constant CFG_SDCTRL_SD64 : integer := 0; constant CFG_SDCTRL_PAGE : integer := 0 + 0; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 1; constant CFG_MCTRL_RAM16BIT : integer := 0; constant CFG_MCTRL_5CS : integer := 0; constant CFG_MCTRL_SDEN : integer := 0; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; constant CFG_MCTRL_PAGE : integer := 0 + 0; -- AHB status register constant CFG_AHBSTAT : integer := 1; constant CFG_AHBSTATN : integer := (1); -- AHB RAM constant CFG_AHBRAMEN : integer := 0; constant CFG_AHBRSZ : integer := 1; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 4; -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 1; constant CFG_IRQ3_NSEC : integer := 0; -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); constant CFG_GPT_SW : integer := (16); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; constant CFG_GRGPIO_IMASK : integer := 16#fe#; constant CFG_GRGPIO_WIDTH : integer := (32); -- Second GPIO port constant CFG_GRGPIO2_ENABLE : integer := 1; constant CFG_GRGPIO2_IMASK : integer := 16#fe#; constant CFG_GRGPIO2_WIDTH : integer := (32); -- VGA and PS2/ interface constant CFG_KBD_ENABLE : integer := 1; constant CFG_VGA_ENABLE : integer := 0; constant CFG_SVGA_ENABLE : integer := 1; -- GRLIB debugging constant CFG_DUART : integer := 0; end;
-- utils_pkg.vhd -- Jan Viktorin <xvikto03@stud.fit.vutbr.cz> -- Copyright (C) 2011, 2012 Jan Viktorin library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package utils_pkg is constant IPIF_RO : integer := 0; constant IPIF_WO : integer := 1; constant IPIF_RW : integer := 2; function width_of_be(dwidth : in integer) return integer; end package; package body utils_pkg is function width_of_be(dwidth : in integer) return integer is variable bwidth : integer; variable brest : integer; begin assert dwidth > 0 report "Invalid dwidth, must be greater then zero" severity failure; brest := dwidth mod 8; if brest = 0 then bwidth := dwidth / 8; else bwidth := dwidth / 8 + 1; end if; return bwidth; end function; end package body;
-- Automatically generated: write_netlist -wrapapp -vhdl -module reconflogic-wrapadt7410.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MyReconfigLogic is port ( Reset_n_i : in std_logic; Clk_i : in std_logic; AdcConvComplete_i : in std_logic; AdcDoConvert_o : out std_logic; AdcValue_i : in std_logic_vector(9 downto 0); I2C_Busy_i : in std_logic; I2C_DataIn_o : out std_logic_vector(7 downto 0); I2C_DataOut_i : in std_logic_vector(7 downto 0); I2C_Divider800_o : out std_logic_vector(15 downto 0); I2C_ErrAckParam_o : out std_logic; I2C_Error_i : in std_logic; I2C_F100_400_n_o : out std_logic; I2C_FIFOEmpty_i : in std_logic; I2C_FIFOFull_i : in std_logic; I2C_FIFOReadNext_o : out std_logic; I2C_FIFOWrite_o : out std_logic; I2C_ReadCount_o : out std_logic_vector(3 downto 0); I2C_ReceiveSend_n_o : out std_logic; I2C_StartProcess_o : out std_logic; Inputs_i : in std_logic_vector(7 downto 0); Outputs_o : out std_logic_vector(7 downto 0); ReconfModuleIRQs_o : out std_logic_vector(4 downto 0); SPI_CPHA_o : out std_logic; SPI_CPOL_o : out std_logic; SPI_DataIn_o : out std_logic_vector(7 downto 0); SPI_DataOut_i : in std_logic_vector(7 downto 0); SPI_FIFOEmpty_i : in std_logic; SPI_FIFOFull_i : in std_logic; SPI_LSBFE_o : out std_logic; SPI_ReadNext_o : out std_logic; SPI_SPPR_SPR_o : out std_logic_vector(7 downto 0); SPI_Transmission_i : in std_logic; SPI_Write_o : out std_logic; ReconfModuleIn_i : in std_logic_vector(7 downto 0); ReconfModuleOut_o : out std_logic_vector(7 downto 0); I2C_Errors_i : in std_logic_vector(7 downto 0); PerAddr_i : in std_logic_vector(13 downto 0); PerDIn_i : in std_logic_vector(15 downto 0); PerWr_i : in std_logic_vector(1 downto 0); PerEn_i : in std_logic; CfgIntfDOut_o : out std_logic_vector(15 downto 0); ParamIntfDOut_o : out std_logic_vector(15 downto 0) ); end MyReconfigLogic; architecture WrapADT7410 of MyReconfigLogic is component ADT7410 port ( Reset_n_i : in std_logic; Clk_i : in std_logic; Enable_i : in std_logic; CpuIntr_o : out std_logic; I2C_ReceiveSend_n_o : out std_logic; I2C_ReadCount_o : out std_logic_vector(7 downto 0); I2C_StartProcess_o : out std_logic; I2C_Busy_i : in std_logic; I2C_FIFOReadNext_o : out std_logic; I2C_FIFOWrite_o : out std_logic; I2C_Data_o : out std_logic_vector(7 downto 0); I2C_Data_i : in std_logic_vector(7 downto 0); I2C_Error_i : in std_logic; PeriodCounterPreset_i : in std_logic_vector(15 downto 0); SensorValue_o : out std_logic_vector(15 downto 0); Threshold_i : in std_logic_vector(15 downto 0); WaitCounterPreset_i : in std_logic_vector(15 downto 0) ); end component; component CfgIntf generic ( -- Number of configuration chains NumCfgs : integer := 3; BaseAddr : integer := 16#0180# ); port ( Reset_n_i : in std_logic; Clk_i : in std_logic; -- OpenMSP430 Interface PerAddr_i : in std_logic_vector(13 downto 0); PerDIn_i : in std_logic_vector(15 downto 0); PerDOut_o : out std_logic_vector(15 downto 0); PerWr_i : in std_logic_vector(1 downto 0); PerEn_i : in std_logic; CfgClk_o : out std_logic_vector(NumCfgs-1 downto 0); CfgMode_o : out std_logic; CfgShift_o : out std_logic_vector(NumCfgs-1 downto 0); CfgDataOut_o : out std_logic; CfgDataIn_i : in std_logic_vector(NumCfgs-1 downto 0) ); end component; component ParamIntf generic ( WrAddrWidth : integer range 1 to 15 := 4; RdAddrWidth : integer range 1 to 15 := 4; BaseAddr : integer := 16#0180# ); port ( Reset_n_i : in std_logic; Clk_i : in std_logic; -- OpenMSP430 Interface PerAddr_i : in std_logic_vector(13 downto 0); PerDIn_i : in std_logic_vector(15 downto 0); PerDOut_o : out std_logic_vector(15 downto 0); PerWr_i : in std_logic_vector(1 downto 0); PerEn_i : in std_logic; -- Param Out ParamWrAddr_o : out std_logic_vector(WrAddrWidth-1 downto 0); ParamWrData_o : out std_logic_vector(15 downto 0); ParamWr_o : out std_logic; -- Param In ParamRdAddr_o : out std_logic_vector(RdAddrWidth-1 downto 0); ParamRdData_i : in std_logic_vector(15 downto 0) ); end component; component ParamOutReg generic ( Width : integer := 16 ); port ( Reset_n_i : in std_logic; Clk_i : in std_logic; Enable_i : in std_logic; ParamWrData_i : in std_logic_vector(Width-1 downto 0); Param_o : out std_logic_vector(Width-1 downto 0) ); end component; signal I2C_ReadCount_s : std_logic_vector(7 downto 0); signal PeriodCounterPreset_s : std_logic_vector(15 downto 0); signal SensorValue_s : std_logic_vector(15 downto 0); signal Threshold_s : std_logic_vector(15 downto 0); signal WaitCounterPreset_s : std_logic_vector(15 downto 0); signal CfgClk_s : std_logic_vector(0 downto 0); signal CfgMode_s : std_logic; signal CfgShift_s : std_logic_vector(0 downto 0); signal CfgDataOut_s : std_logic; signal CfgDataIn_s : std_logic_vector(0 downto 0); signal ParamWrAddr_s : std_logic_vector(2 downto 0); signal ParamWrData_s : std_logic_vector(15 downto 0); signal ParamWr_s : std_logic; signal ParamRdAddr_s : std_logic_vector(0 downto 0); signal ParamRdData_s : std_logic_vector(15 downto 0); type Params_t is array(0 to 1) of std_logic_vector(15 downto 0); signal Params_s : Params_t; signal I2C_ErrAckParam_s : std_logic_vector(0 downto 0); signal ParamI2C_Divider800Enable_s : std_logic; signal ParamI2C_ErrAckParamEnable_s : std_logic; signal ParamPeriodCounterPresetEnable_s : std_logic; signal ParamThresholdEnable_s : std_logic; signal ParamWaitCounterPresetEnable_s : std_logic; begin -- Configuration Interface CfgIntf_0: CfgIntf generic map ( BaseAddr => 16#0180#, NumCfgs => 1 ) port map ( Reset_n_i => Reset_n_i, Clk_i => Clk_i, PerAddr_i => PerAddr_i, PerDIn_i => PerDIn_i, PerDOut_o => CfgIntfDOut_o, PerWr_i => PerWr_i, PerEn_i => PerEn_i, CfgClk_o => CfgClk_s, CfgMode_o => CfgMode_s, CfgShift_o => CfgShift_s, CfgDataOut_o => CfgDataOut_s, CfgDataIn_i => CfgDataIn_s ); -- Parameterization Interface: 5 write addresses, 2 read addresses ParamIntf_0: ParamIntf generic map ( BaseAddr => 16#0188#, WrAddrWidth => 3, RdAddrWidth => 1 ) port map ( Reset_n_i => Reset_n_i, Clk_i => Clk_i, PerAddr_i => PerAddr_i, PerDIn_i => PerDIn_i, PerDOut_o => ParamIntfDOut_o, PerWr_i => PerWr_i, PerEn_i => PerEn_i, ParamWrAddr_o => ParamWrAddr_s, ParamWrData_o => ParamWrData_s, ParamWr_o => ParamWr_s, ParamRdAddr_o => ParamRdAddr_s, ParamRdData_i => ParamRdData_s ); ADT7410_0: ADT7410 port map ( I2C_Busy_i => I2C_Busy_i, I2C_Data_o => I2C_DataIn_o, I2C_Data_i => I2C_DataOut_i, I2C_Error_i => I2C_Error_i, I2C_FIFOReadNext_o => I2C_FIFOReadNext_o, I2C_FIFOWrite_o => I2C_FIFOWrite_o, I2C_ReadCount_o => I2C_ReadCount_s, I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o, I2C_StartProcess_o => I2C_StartProcess_o, CpuIntr_o => ReconfModuleIRQs_o(0), Enable_i => ReconfModuleIn_i(0), Clk_i => Clk_i, Reset_n_i => Reset_n_i, PeriodCounterPreset_i => PeriodCounterPreset_s, SensorValue_o => SensorValue_s, Threshold_i => Threshold_s, WaitCounterPreset_i => WaitCounterPreset_s ); AdcDoConvert_o <= '0'; I2C_F100_400_n_o <= '1'; I2C_ReadCount_o <= I2C_ReadCount_s(3 downto 0); Outputs_o(0) <= '0'; Outputs_o(1) <= '0'; Outputs_o(2) <= '0'; Outputs_o(3) <= '0'; Outputs_o(4) <= '0'; Outputs_o(5) <= '0'; Outputs_o(6) <= '0'; Outputs_o(7) <= '0'; ReconfModuleIRQs_o(1) <= '0'; ReconfModuleIRQs_o(2) <= '0'; ReconfModuleIRQs_o(3) <= '0'; ReconfModuleIRQs_o(4) <= '0'; SPI_CPHA_o <= '0'; SPI_CPOL_o <= '0'; SPI_DataIn_o <= "00000000"; SPI_LSBFE_o <= '0'; SPI_ReadNext_o <= '0'; SPI_SPPR_SPR_o <= "00000000"; SPI_Write_o <= '0'; ReconfModuleOut_o(0) <= '0'; ReconfModuleOut_o(1) <= '0'; ReconfModuleOut_o(2) <= '0'; ReconfModuleOut_o(3) <= '0'; ReconfModuleOut_o(4) <= '0'; ReconfModuleOut_o(5) <= '0'; ReconfModuleOut_o(6) <= '0'; ReconfModuleOut_o(7) <= '0'; -- just a fixed value for the config interface CfgDataIn_s <= "0"; -- Param read address decoder -- Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and -- hope that the synthesis optimizes the MUX -- Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range -- 0 to n.", even during param write cycles, because ParamRdAddr has the -- source as ParamWrAddr. Use the parameter "-noindexcheck" during -- compilation ("vcom"). Simulation works fine then, but ModelSim generates -- numerous "INTERNAL ERROR"s to stdout, which seem harmless. ParamRdData_s <= Params_s(to_integer(unsigned(ParamRdAddr_s))); ParamOutReg_I2C_Divider800: ParamOutReg generic map ( Width => 16 ) port map ( Reset_n_i => Reset_n_i, Clk_i => Clk_i, Param_o => I2C_Divider800_o, Enable_i => ParamI2C_Divider800Enable_s, ParamWrData_i => ParamWrData_s ); ParamOutReg_I2C_ErrAckParam: ParamOutReg generic map ( Width => 1 ) port map ( Reset_n_i => Reset_n_i, Clk_i => Clk_i, Param_o => I2C_ErrAckParam_s, Enable_i => ParamI2C_ErrAckParamEnable_s, ParamWrData_i => ParamWrData_s(0 downto 0) ); ParamOutReg_PeriodCounterPreset: ParamOutReg generic map ( Width => 16 ) port map ( Reset_n_i => Reset_n_i, Clk_i => Clk_i, Param_o => PeriodCounterPreset_s, Enable_i => ParamPeriodCounterPresetEnable_s, ParamWrData_i => ParamWrData_s ); ParamOutReg_Threshold: ParamOutReg generic map ( Width => 16 ) port map ( Reset_n_i => Reset_n_i, Clk_i => Clk_i, Param_o => Threshold_s, Enable_i => ParamThresholdEnable_s, ParamWrData_i => ParamWrData_s ); ParamOutReg_WaitCounterPreset: ParamOutReg generic map ( Width => 16 ) port map ( Reset_n_i => Reset_n_i, Clk_i => Clk_i, Param_o => WaitCounterPreset_s, Enable_i => ParamWaitCounterPresetEnable_s, ParamWrData_i => ParamWrData_s ); I2C_ErrAckParam_o <= I2C_ErrAckParam_s(0); -- Address $00 Params_s(0) <= "00000000" & I2C_Errors_i; -- Address $01 Params_s(1) <= SensorValue_s; -- Address $00 ParamI2C_Divider800Enable_s <= ParamWr_s when ParamWrAddr_s = "000" else '0'; -- Address $01 ParamI2C_ErrAckParamEnable_s <= ParamWr_s when ParamWrAddr_s = "001" else '0'; -- Address $02 ParamPeriodCounterPresetEnable_s <= ParamWr_s when ParamWrAddr_s = "010" else '0'; -- Address $03 ParamThresholdEnable_s <= ParamWr_s when ParamWrAddr_s = "011" else '0'; -- Address $04 ParamWaitCounterPresetEnable_s <= ParamWr_s when ParamWrAddr_s = "100" else '0'; end WrapADT7410;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.all; entity rng is port ( output: out std_logic_vector(31 downto 0); clk: in std_logic; seed_btn: in std_logic); end rng; architecture Behavioral of rng is signal r1,r2,r3,r4,r_out: std_logic_vector(31 downto 0) := x"00000000"; signal clk_cnt:integer range 0 to 65536 :=0; signal rnd_begin: std_logic :='0'; begin process(clk) begin if rising_edge(clk) then if clk_cnt=65535 then clk_cnt<=0; end if; clk_cnt<=clk_cnt+1; end if; if rnd_begin='1' then r_out<=r4; r4<=r3; r3<=r2; r2<=r1; r1<= ((r2(11 downto 0) & x"00000") xor (x"0000" & r3(31 downto 16))) xor ((r4(21 downto 0) & "0000000000") xor ("000000" & r_out(31 downto 6))) ; output<=r_out; elsif rnd_begin='0' then r4<= std_logic_vector(to_unsigned(clk_cnt,16)) & std_logic_vector(to_unsigned(clk_cnt,16)); r3<= x"D3C4B5A6"; r2<= x"19202122"; r1<= x"184674A2"; end if; end process; process(seed_btn) begin if rising_edge(seed_btn) then rnd_begin<='1'; end if; end process; end Behavioral;
-------------------------------------------------------------------------------- --This file is part of fpga_gpib_controller. -- -- Fpga_gpib_controller is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- Fpga_gpib_controller is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>. -------------------------------------------------------------------------------- -- Entity: InterruptGenerator -- Date:2011-11-25 -- Author: Andrzej Paluch -- -- Description ${cursor} -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use work.helperComponents.all; entity InterruptGenerator is port ( reset : std_logic; clk : in std_logic; interrupt : out std_logic; -------------------- gpib device --------------------- -- device is local controlled isLocal : in std_logic; -- input buffer ready in_buf_ready : in std_logic; -- output buffer ready out_buf_ready : in std_logic; -- clear device (DC) clr : in std_logic; -- trigger device (DT) trg : in std_logic; -- addressed to talk(L or LE) att : in std_logic; -- addressed to listen (T or TE) atl : in std_logic; -- seriall poll active spa : in std_logic; -------------------- gpib controller --------------------- -- controller write commands cwrc : in std_logic; -- controller write data cwrd : in std_logic; -- service requested srq : in std_logic; -- parallel poll ready ppr : in std_logic; -- stb received stb_received : in std_logic; REN : in std_logic; ATN : in std_logic; IFC : in std_logic ); end InterruptGenerator; architecture arch of InterruptGenerator is constant PULSE_WIDTH : integer := 10; signal p0, p1, p2, p3, p4, p5, p6, p7 : std_logic; begin interrupt <= p0 or p1 or p2 or p3 or p4 or p5 or p6 or p7; ed0: EdgeDetector generic map (RISING => '1', FALLING => '0', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => in_buf_ready, pulse => p0 ); ed1: EdgeDetector generic map (RISING => '1', FALLING => '0', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => out_buf_ready, pulse => p1 ); ed2: EdgeDetector generic map (RISING => '1', FALLING => '0', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => clr, pulse => p2 ); ed3: EdgeDetector generic map (RISING => '1', FALLING => '0', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => trg, pulse => p3 ); ed4: EdgeDetector generic map (RISING => '1', FALLING => '0', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => srq, pulse => p4 ); ed5: EdgeDetector generic map (RISING => '1', FALLING => '0', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => ppr, pulse => p5 ); ed6: EdgeDetector generic map (RISING => '1', FALLING => '0', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => stb_received, pulse => p6 ); ed7: EdgeDetector generic map (RISING => '1', FALLING => '1', PULSE_WIDTH => PULSE_WIDTH) port map ( reset => reset, clk => clk, in_data => isLocal, pulse => p7 ); end arch;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_pctrl.vhd -- -- Description: -- Used for protocol control on write and read interface stimulus and status generation -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_pctrl IS GENERIC( AXI_CHANNEL : STRING :="NONE"; C_APPLICATION_TYPE : INTEGER := 0; C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_WR_PNTR_WIDTH : INTEGER := 0; C_RD_PNTR_WIDTH : INTEGER := 0; C_CH_TYPE : INTEGER := 0; FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 2; TB_SEED : INTEGER := 2 ); PORT( RESET_WR : IN STD_LOGIC; RESET_RD : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; FULL : IN STD_LOGIC; EMPTY : IN STD_LOGIC; ALMOST_FULL : IN STD_LOGIC; ALMOST_EMPTY : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); DOUT_CHK : IN STD_LOGIC; PRC_WR_EN : OUT STD_LOGIC; PRC_RD_EN : OUT STD_LOGIC; RESET_EN : OUT STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY; ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_en_i : STD_LOGIC := '0'; SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL state : STD_LOGIC := '0'; SIGNAL wr_control : STD_LOGIC := '0'; SIGNAL rd_control : STD_LOGIC := '0'; SIGNAL stop_on_err : STD_LOGIC := '0'; SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); SIGNAL sim_done_i : STD_LOGIC := '0'; SIGNAL reset_ex1 : STD_LOGIC := '0'; SIGNAL reset_ex2 : STD_LOGIC := '0'; SIGNAL reset_ex3 : STD_LOGIC := '0'; SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); SIGNAL prc_we_i : STD_LOGIC := '0'; SIGNAL prc_re_i : STD_LOGIC := '0'; SIGNAL reset_en_i : STD_LOGIC := '0'; SIGNAL sim_done_d1 : STD_LOGIC := '0'; SIGNAL sim_done_wr1 : STD_LOGIC := '0'; SIGNAL sim_done_wr2 : STD_LOGIC := '0'; SIGNAL empty_d1 : STD_LOGIC := '0'; SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; SIGNAL state_d1 : STD_LOGIC := '0'; SIGNAL state_rd_dom1 : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '0'; SIGNAL rd_en_wr1 : STD_LOGIC := '0'; SIGNAL wr_en_d1 : STD_LOGIC := '0'; SIGNAL wr_en_rd1 : STD_LOGIC := '0'; SIGNAL full_chk_d1 : STD_LOGIC := '0'; SIGNAL full_chk_rd1 : STD_LOGIC := '0'; SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; SIGNAL state_rd_dom2 : STD_LOGIC := '0'; SIGNAL state_rd_dom3 : STD_LOGIC := '0'; SIGNAL rd_en_wr2 : STD_LOGIC := '0'; SIGNAL wr_en_rd2 : STD_LOGIC := '0'; SIGNAL full_chk_rd2 : STD_LOGIC := '0'; SIGNAL reset_en_d1 : STD_LOGIC := '0'; SIGNAL reset_en_rd1 : STD_LOGIC := '0'; SIGNAL reset_en_rd2 : STD_LOGIC := '0'; SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; SIGNAL data_chk_rd1 : STD_LOGIC := '0'; SIGNAL data_chk_rd2 : STD_LOGIC := '0'; SIGNAL full_d1 : STD_LOGIC := '0'; SIGNAL full_rd_dom1 : STD_LOGIC := '0'; SIGNAL full_rd_dom2 : STD_LOGIC := '0'; SIGNAL af_chk_d1 : STD_LOGIC := '0'; SIGNAL af_chk_rd1 : STD_LOGIC := '0'; SIGNAL af_chk_rd2 : STD_LOGIC := '0'; SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); BEGIN status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i; STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; SIM_DONE <= sim_done_i; rdw_gt_wrw <= (OTHERS => '1'); PROCESS(RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(prc_re_i = '1') THEN rd_activ_cont <= rd_activ_cont + "1"; END IF; END IF; END PROCESS; PROCESS(sim_done_i) BEGIN assert sim_done_i = '0' report "Simulation Complete for:" & AXI_CHANNEL severity note; END PROCESS; ----------------------------------------------------- -- SIM_DONE SIGNAL GENERATION ----------------------------------------------------- PROCESS (RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN --sim_done_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN sim_done_i <= '1'; END IF; END IF; END PROCESS; -- TB Timeout/Stop fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN sim_stop_cntr <= sim_stop_cntr - "1"; END IF; END IF; END PROCESS; END GENERATE fifo_tb_stop_run; -- Stop when error found PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(sim_done_i = '0') THEN status_d1_i <= status_i OR status_d1_i; END IF; IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN stop_on_err <= '1'; END IF; END IF; END PROCESS; ----------------------------------------------------- ----------------------------------------------------- -- CHECKS FOR FIFO ----------------------------------------------------- -- Reset pulse extension require for FULL flags checks -- FULL flag may stay high for 3 clocks after reset is removed. PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN reset_ex1 <= '1'; reset_ex2 <= '1'; reset_ex3 <= '1'; ELSIF (WR_CLK'event AND WR_CLK='1') THEN reset_ex1 <= '0'; reset_ex2 <= reset_ex1; reset_ex3 <= reset_ex2; END IF; END PROCESS; PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN post_rst_dly_rd <= (OTHERS => '1'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); END IF; END PROCESS; PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN post_rst_dly_wr <= (OTHERS => '1'); ELSIF (WR_CLK'event AND WR_CLK='1') THEN post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); END IF; END PROCESS; PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wrw_gt_rdw <= (OTHERS => '1'); ELSIF (WR_CLK'event AND WR_CLK='1') THEN IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN wrw_gt_rdw <= wrw_gt_rdw + '1'; END IF; END IF; END PROCESS; -- FULL de-assert Counter PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN full_ds_timeout <= (OTHERS => '0'); ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN full_ds_timeout <= full_ds_timeout + '1'; END IF; ELSE full_ds_timeout <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- EMPTY deassert counter PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_ds_timeout <= (OTHERS => '0'); ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state = '0') THEN IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN empty_ds_timeout <= empty_ds_timeout + '1'; END IF; ELSE empty_ds_timeout <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- Full check signal generation PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN full_chk_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN full_chk_i <= '0'; ELSE full_chk_i <= AND_REDUCE(full_as_timeout) OR AND_REDUCE(full_ds_timeout); END IF; END IF; END PROCESS; -- Empty checks PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_chk_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN empty_chk_i <= '0'; ELSE empty_chk_i <= AND_REDUCE(empty_as_timeout) OR AND_REDUCE(empty_ds_timeout); END IF; END IF; END PROCESS; fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE PRC_WR_EN <= prc_we_i AFTER 24 ns; PRC_RD_EN <= prc_re_i AFTER 12 ns; data_chk_i <= dout_chk; END GENERATE fifo_d_chk; -- Almost full flag checks PROCESS(WR_CLK,reset_ex3) BEGIN IF(reset_ex3 = '1') THEN af_chk_i <= '0'; ELSIF (WR_CLK'event AND WR_CLK='1') THEN IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN af_chk_i <= '1'; ELSE af_chk_i <= '0'; END IF; END IF; END PROCESS; -- Almost empty flag checks PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN ae_chk_i <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR (state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN ae_chk_i <= '1'; ELSE ae_chk_i <= '0'; END IF; END IF; END PROCESS; ----------------------------------------------------- ----------------------------------------------------- -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN empty_wr_dom1 <= '1'; empty_wr_dom2 <= '1'; state_d1 <= '0'; wr_en_d1 <= '0'; rd_en_wr1 <= '0'; rd_en_wr2 <= '0'; full_chk_d1 <= '0'; af_chk_d1 <= '0'; full_d1 <= '0'; reset_en_d1 <= '0'; sim_done_wr1 <= '0'; sim_done_wr2 <= '0'; ELSIF (WR_CLK'event AND WR_CLK='1') THEN sim_done_wr1 <= sim_done_d1; sim_done_wr2 <= sim_done_wr1; reset_en_d1 <= reset_en_i; full_d1 <= FULL; state_d1 <= state; empty_wr_dom1 <= empty_d1; empty_wr_dom2 <= empty_wr_dom1; wr_en_d1 <= wr_en_i; rd_en_wr1 <= rd_en_d1; rd_en_wr2 <= rd_en_wr1; full_chk_d1 <= full_chk_i; af_chk_d1 <= af_chk_i; END IF; END PROCESS; PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_d1 <= '1'; state_rd_dom1 <= '0'; state_rd_dom2 <= '0'; state_rd_dom3 <= '0'; wr_en_rd1 <= '0'; wr_en_rd2 <= '0'; rd_en_d1 <= '0'; full_chk_rd1 <= '0'; full_chk_rd2 <= '0'; af_chk_rd1 <= '0'; af_chk_rd2 <= '0'; full_rd_dom1 <= '0'; full_rd_dom2 <= '0'; reset_en_rd1 <= '0'; reset_en_rd2 <= '0'; sim_done_d1 <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN sim_done_d1 <= sim_done_i; reset_en_rd1 <= reset_en_d1; reset_en_rd2 <= reset_en_rd1; empty_d1 <= EMPTY; rd_en_d1 <= rd_en_i; state_rd_dom1 <= state_d1; state_rd_dom2 <= state_rd_dom1; state_rd_dom3 <= state_rd_dom2; wr_en_rd1 <= wr_en_d1; wr_en_rd2 <= wr_en_rd1; full_chk_rd1 <= full_chk_d1; full_chk_rd2 <= full_chk_rd1; af_chk_rd1 <= af_chk_d1; af_chk_rd2 <= af_chk_rd1; full_rd_dom1 <= full_d1; full_rd_dom2 <= full_rd_dom1; END IF; END PROCESS; RESET_EN <= reset_en_rd2; data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE ----------------------------------------------------- -- WR_EN GENERATION ----------------------------------------------------- gen_rand_wr_en:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+1 ) PORT MAP( CLK => WR_CLK, RESET => RESET_WR, RANDOM_NUM => wr_en_gen, ENABLE => '1' ); PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wr_en_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; ELSE wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); END IF; END IF; END PROCESS; ----------------------------------------------------- -- WR_EN CONTROL ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wr_cntr <= (OTHERS => '0'); wr_control <= '1'; full_as_timeout <= (OTHERS => '0'); ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN IF(wr_en_i = '1') THEN wr_cntr <= wr_cntr + "1"; END IF; full_as_timeout <= (OTHERS => '0'); ELSE wr_cntr <= (OTHERS => '0'); IF(rd_en_wr2 = '0') THEN IF(wr_en_i = '1') THEN full_as_timeout <= full_as_timeout + "1"; END IF; ELSE full_as_timeout <= (OTHERS => '0'); END IF; END IF; wr_control <= NOT wr_cntr(wr_cntr'high); END IF; END PROCESS; ----------------------------------------------------- -- RD_EN GENERATION ----------------------------------------------------- gen_rand_rd_en:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED ) PORT MAP( CLK => RD_CLK, RESET => RESET_RD, RANDOM_NUM => rd_en_gen, ENABLE => '1' ); PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN rd_en_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state_rd_dom2 = '0') THEN rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); ELSE rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); END IF; END IF; END PROCESS; ----------------------------------------------------- -- RD_EN CONTROL ----------------------------------------------------- PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN rd_cntr <= (OTHERS => '0'); rd_control <= '1'; empty_as_timeout <= (OTHERS => '0'); ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state_rd_dom2 = '0') THEN IF(rd_en_i = '1') THEN rd_cntr <= rd_cntr + "1"; END IF; empty_as_timeout <= (OTHERS => '0'); ELSE rd_cntr <= (OTHERS => '0'); IF(wr_en_rd2 = '0') THEN IF(rd_en_i = '1') THEN empty_as_timeout <= empty_as_timeout + "1"; END IF; ELSE empty_as_timeout <= (OTHERS => '0'); END IF; END IF; rd_control <= NOT rd_cntr(rd_cntr'high); END IF; END PROCESS; ----------------------------------------------------- -- STIMULUS CONTROL ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN state <= '0'; reset_en_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN CASE state IS WHEN '0' => IF(FULL = '1' AND empty_wr_dom2 = '0') THEN state <= '1'; reset_en_i <= '0'; END IF; WHEN '1' => IF(empty_wr_dom2 = '1' AND FULL = '0') THEN state <= '0'; reset_en_i <= '1'; END IF; WHEN OTHERS => state <= state; END CASE; END IF; END PROCESS; END GENERATE data_fifo_en; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_pctrl.vhd -- -- Description: -- Used for protocol control on write and read interface stimulus and status generation -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_misc.all; LIBRARY work; USE work.fg_tb_pkg.ALL; ENTITY fg_tb_pctrl IS GENERIC( AXI_CHANNEL : STRING :="NONE"; C_APPLICATION_TYPE : INTEGER := 0; C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_WR_PNTR_WIDTH : INTEGER := 0; C_RD_PNTR_WIDTH : INTEGER := 0; C_CH_TYPE : INTEGER := 0; FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 2; TB_SEED : INTEGER := 2 ); PORT( RESET_WR : IN STD_LOGIC; RESET_RD : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; FULL : IN STD_LOGIC; EMPTY : IN STD_LOGIC; ALMOST_FULL : IN STD_LOGIC; ALMOST_EMPTY : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); DOUT_CHK : IN STD_LOGIC; PRC_WR_EN : OUT STD_LOGIC; PRC_RD_EN : OUT STD_LOGIC; RESET_EN : OUT STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY; ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH); CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8); CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH); SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0'); SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); SIGNAL wr_en_i : STD_LOGIC := '0'; SIGNAL rd_en_i : STD_LOGIC := '0'; SIGNAL state : STD_LOGIC := '0'; SIGNAL wr_control : STD_LOGIC := '0'; SIGNAL rd_control : STD_LOGIC := '0'; SIGNAL stop_on_err : STD_LOGIC := '0'; SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8); SIGNAL sim_done_i : STD_LOGIC := '0'; SIGNAL reset_ex1 : STD_LOGIC := '0'; SIGNAL reset_ex2 : STD_LOGIC := '0'; SIGNAL reset_ex3 : STD_LOGIC := '0'; SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0'); SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1'); SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0'); SIGNAL prc_we_i : STD_LOGIC := '0'; SIGNAL prc_re_i : STD_LOGIC := '0'; SIGNAL reset_en_i : STD_LOGIC := '0'; SIGNAL sim_done_d1 : STD_LOGIC := '0'; SIGNAL sim_done_wr1 : STD_LOGIC := '0'; SIGNAL sim_done_wr2 : STD_LOGIC := '0'; SIGNAL empty_d1 : STD_LOGIC := '0'; SIGNAL empty_wr_dom1 : STD_LOGIC := '0'; SIGNAL state_d1 : STD_LOGIC := '0'; SIGNAL state_rd_dom1 : STD_LOGIC := '0'; SIGNAL rd_en_d1 : STD_LOGIC := '0'; SIGNAL rd_en_wr1 : STD_LOGIC := '0'; SIGNAL wr_en_d1 : STD_LOGIC := '0'; SIGNAL wr_en_rd1 : STD_LOGIC := '0'; SIGNAL full_chk_d1 : STD_LOGIC := '0'; SIGNAL full_chk_rd1 : STD_LOGIC := '0'; SIGNAL empty_wr_dom2 : STD_LOGIC := '0'; SIGNAL state_rd_dom2 : STD_LOGIC := '0'; SIGNAL state_rd_dom3 : STD_LOGIC := '0'; SIGNAL rd_en_wr2 : STD_LOGIC := '0'; SIGNAL wr_en_rd2 : STD_LOGIC := '0'; SIGNAL full_chk_rd2 : STD_LOGIC := '0'; SIGNAL reset_en_d1 : STD_LOGIC := '0'; SIGNAL reset_en_rd1 : STD_LOGIC := '0'; SIGNAL reset_en_rd2 : STD_LOGIC := '0'; SIGNAL data_chk_wr_d1 : STD_LOGIC := '0'; SIGNAL data_chk_rd1 : STD_LOGIC := '0'; SIGNAL data_chk_rd2 : STD_LOGIC := '0'; SIGNAL full_d1 : STD_LOGIC := '0'; SIGNAL full_rd_dom1 : STD_LOGIC := '0'; SIGNAL full_rd_dom2 : STD_LOGIC := '0'; SIGNAL af_chk_d1 : STD_LOGIC := '0'; SIGNAL af_chk_rd1 : STD_LOGIC := '0'; SIGNAL af_chk_rd2 : STD_LOGIC := '0'; SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1'); BEGIN status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i; STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high); prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0'; prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0'; SIM_DONE <= sim_done_i; rdw_gt_wrw <= (OTHERS => '1'); PROCESS(RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(prc_re_i = '1') THEN rd_activ_cont <= rd_activ_cont + "1"; END IF; END IF; END PROCESS; PROCESS(sim_done_i) BEGIN assert sim_done_i = '0' report "Simulation Complete for:" & AXI_CHANNEL severity note; END PROCESS; ----------------------------------------------------- -- SIM_DONE SIGNAL GENERATION ----------------------------------------------------- PROCESS (RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN --sim_done_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN sim_done_i <= '1'; END IF; END IF; END PROCESS; -- TB Timeout/Stop fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN sim_stop_cntr <= sim_stop_cntr - "1"; END IF; END IF; END PROCESS; END GENERATE fifo_tb_stop_run; -- Stop when error found PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK='1') THEN IF(sim_done_i = '0') THEN status_d1_i <= status_i OR status_d1_i; END IF; IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN stop_on_err <= '1'; END IF; END IF; END PROCESS; ----------------------------------------------------- ----------------------------------------------------- -- CHECKS FOR FIFO ----------------------------------------------------- -- Reset pulse extension require for FULL flags checks -- FULL flag may stay high for 3 clocks after reset is removed. PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN reset_ex1 <= '1'; reset_ex2 <= '1'; reset_ex3 <= '1'; ELSIF (WR_CLK'event AND WR_CLK='1') THEN reset_ex1 <= '0'; reset_ex2 <= reset_ex1; reset_ex3 <= reset_ex2; END IF; END PROCESS; PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN post_rst_dly_rd <= (OTHERS => '1'); ELSIF (RD_CLK'event AND RD_CLK='1') THEN post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4); END IF; END PROCESS; PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN post_rst_dly_wr <= (OTHERS => '1'); ELSIF (WR_CLK'event AND WR_CLK='1') THEN post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4); END IF; END PROCESS; PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wrw_gt_rdw <= (OTHERS => '1'); ELSIF (WR_CLK'event AND WR_CLK='1') THEN IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN wrw_gt_rdw <= wrw_gt_rdw + '1'; END IF; END IF; END PROCESS; -- FULL de-assert Counter PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN full_ds_timeout <= (OTHERS => '0'); ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN full_ds_timeout <= full_ds_timeout + '1'; END IF; ELSE full_ds_timeout <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- EMPTY deassert counter PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_ds_timeout <= (OTHERS => '0'); ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state = '0') THEN IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN empty_ds_timeout <= empty_ds_timeout + '1'; END IF; ELSE empty_ds_timeout <= (OTHERS => '0'); END IF; END IF; END PROCESS; -- Full check signal generation PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN full_chk_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN full_chk_i <= '0'; ELSE full_chk_i <= AND_REDUCE(full_as_timeout) OR AND_REDUCE(full_ds_timeout); END IF; END IF; END PROCESS; -- Empty checks PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_chk_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN empty_chk_i <= '0'; ELSE empty_chk_i <= AND_REDUCE(empty_as_timeout) OR AND_REDUCE(empty_ds_timeout); END IF; END IF; END PROCESS; fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE PRC_WR_EN <= prc_we_i AFTER 24 ns; PRC_RD_EN <= prc_re_i AFTER 12 ns; data_chk_i <= dout_chk; END GENERATE fifo_d_chk; -- Almost full flag checks PROCESS(WR_CLK,reset_ex3) BEGIN IF(reset_ex3 = '1') THEN af_chk_i <= '0'; ELSIF (WR_CLK'event AND WR_CLK='1') THEN IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN af_chk_i <= '1'; ELSE af_chk_i <= '0'; END IF; END IF; END PROCESS; -- Almost empty flag checks PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN ae_chk_i <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR (state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN ae_chk_i <= '1'; ELSE ae_chk_i <= '0'; END IF; END IF; END PROCESS; ----------------------------------------------------- ----------------------------------------------------- -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN empty_wr_dom1 <= '1'; empty_wr_dom2 <= '1'; state_d1 <= '0'; wr_en_d1 <= '0'; rd_en_wr1 <= '0'; rd_en_wr2 <= '0'; full_chk_d1 <= '0'; af_chk_d1 <= '0'; full_d1 <= '0'; reset_en_d1 <= '0'; sim_done_wr1 <= '0'; sim_done_wr2 <= '0'; ELSIF (WR_CLK'event AND WR_CLK='1') THEN sim_done_wr1 <= sim_done_d1; sim_done_wr2 <= sim_done_wr1; reset_en_d1 <= reset_en_i; full_d1 <= FULL; state_d1 <= state; empty_wr_dom1 <= empty_d1; empty_wr_dom2 <= empty_wr_dom1; wr_en_d1 <= wr_en_i; rd_en_wr1 <= rd_en_d1; rd_en_wr2 <= rd_en_wr1; full_chk_d1 <= full_chk_i; af_chk_d1 <= af_chk_i; END IF; END PROCESS; PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN empty_d1 <= '1'; state_rd_dom1 <= '0'; state_rd_dom2 <= '0'; state_rd_dom3 <= '0'; wr_en_rd1 <= '0'; wr_en_rd2 <= '0'; rd_en_d1 <= '0'; full_chk_rd1 <= '0'; full_chk_rd2 <= '0'; af_chk_rd1 <= '0'; af_chk_rd2 <= '0'; full_rd_dom1 <= '0'; full_rd_dom2 <= '0'; reset_en_rd1 <= '0'; reset_en_rd2 <= '0'; sim_done_d1 <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN sim_done_d1 <= sim_done_i; reset_en_rd1 <= reset_en_d1; reset_en_rd2 <= reset_en_rd1; empty_d1 <= EMPTY; rd_en_d1 <= rd_en_i; state_rd_dom1 <= state_d1; state_rd_dom2 <= state_rd_dom1; state_rd_dom3 <= state_rd_dom2; wr_en_rd1 <= wr_en_d1; wr_en_rd2 <= wr_en_rd1; full_chk_rd1 <= full_chk_d1; full_chk_rd2 <= full_chk_rd1; af_chk_rd1 <= af_chk_d1; af_chk_rd2 <= af_chk_rd1; full_rd_dom1 <= full_d1; full_rd_dom2 <= full_rd_dom1; END IF; END PROCESS; RESET_EN <= reset_en_rd2; data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE ----------------------------------------------------- -- WR_EN GENERATION ----------------------------------------------------- gen_rand_wr_en:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED+1 ) PORT MAP( CLK => WR_CLK, RESET => RESET_WR, RANDOM_NUM => wr_en_gen, ENABLE => '1' ); PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wr_en_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control; ELSE wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); END IF; END IF; END PROCESS; ----------------------------------------------------- -- WR_EN CONTROL ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN wr_cntr <= (OTHERS => '0'); wr_control <= '1'; full_as_timeout <= (OTHERS => '0'); ELSIF(WR_CLK'event AND WR_CLK='1') THEN IF(state = '1') THEN IF(wr_en_i = '1') THEN wr_cntr <= wr_cntr + "1"; END IF; full_as_timeout <= (OTHERS => '0'); ELSE wr_cntr <= (OTHERS => '0'); IF(rd_en_wr2 = '0') THEN IF(wr_en_i = '1') THEN full_as_timeout <= full_as_timeout + "1"; END IF; ELSE full_as_timeout <= (OTHERS => '0'); END IF; END IF; wr_control <= NOT wr_cntr(wr_cntr'high); END IF; END PROCESS; ----------------------------------------------------- -- RD_EN GENERATION ----------------------------------------------------- gen_rand_rd_en:fg_tb_rng GENERIC MAP( WIDTH => 8, SEED => TB_SEED ) PORT MAP( CLK => RD_CLK, RESET => RESET_RD, RANDOM_NUM => rd_en_gen, ENABLE => '1' ); PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN rd_en_i <= '0'; ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state_rd_dom2 = '0') THEN rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4)); ELSE rd_en_i <= rd_en_gen(0) OR rd_en_gen(6); END IF; END IF; END PROCESS; ----------------------------------------------------- -- RD_EN CONTROL ----------------------------------------------------- PROCESS(RD_CLK,RESET_RD) BEGIN IF(RESET_RD = '1') THEN rd_cntr <= (OTHERS => '0'); rd_control <= '1'; empty_as_timeout <= (OTHERS => '0'); ELSIF(RD_CLK'event AND RD_CLK='1') THEN IF(state_rd_dom2 = '0') THEN IF(rd_en_i = '1') THEN rd_cntr <= rd_cntr + "1"; END IF; empty_as_timeout <= (OTHERS => '0'); ELSE rd_cntr <= (OTHERS => '0'); IF(wr_en_rd2 = '0') THEN IF(rd_en_i = '1') THEN empty_as_timeout <= empty_as_timeout + "1"; END IF; ELSE empty_as_timeout <= (OTHERS => '0'); END IF; END IF; rd_control <= NOT rd_cntr(rd_cntr'high); END IF; END PROCESS; ----------------------------------------------------- -- STIMULUS CONTROL ----------------------------------------------------- PROCESS(WR_CLK,RESET_WR) BEGIN IF(RESET_WR = '1') THEN state <= '0'; reset_en_i <= '0'; ELSIF(WR_CLK'event AND WR_CLK='1') THEN CASE state IS WHEN '0' => IF(FULL = '1' AND empty_wr_dom2 = '0') THEN state <= '1'; reset_en_i <= '0'; END IF; WHEN '1' => IF(empty_wr_dom2 = '1' AND FULL = '0') THEN state <= '0'; reset_en_i <= '1'; END IF; WHEN OTHERS => state <= state; END CASE; END IF; END PROCESS; END GENERATE data_fifo_en; END ARCHITECTURE;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:44:13 05/29/2015 -- Design Name: -- Module Name: module_sp - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity module_SP is port( clk_SP: in std_logic; nreset: in std_logic; SP_CS: in std_logic; --Ƭѡ SP_UP: in std_logic; -- +1£¬¼´³öÕ» SP_DN: in std_logic; -- -1£¬¼´ÈëÕ» nSP_EN: in std_logic; --µ±Õâ¸öΪ0ʱ£¬upÓëdownÓÐЧ£»µ±Õâ¸öΪ1ʱ±íʾÐèÒª¸üÐÂSPÁË ARo: out std_logic_vector(6 downto 0); ao: out std_logic; datai: in std_logic_vector(7 downto 0)); end module_SP; architecture Behavioral of module_SP is signal SP: std_logic_vector(6 downto 0); begin process(clk_SP, nreset) begin if nreset = '0' then SP <= (others => '1'); -- ³õʼʱspÓ¦¸ÃÔÚ7F´¦£¬¼´×îµ×Ï elsif rising_edge(clk_SP) then if SP_CS = '1' then if nSP_EN = '1' then -- ¸üÐÂSP SP <= datai(6 downto 0); ARo <= (others => 'Z'); ao <= '0'; else if SP_UP = '1' then -- ÉÏÉý ARo <= SP; -- ÕâÑùÊÇ¶ÔµÄ ao <= '1'; SP <= std_logic_vector(unsigned(SP) - 1); elsif SP_DN = '1' then -- Ͻµ ARo <= std_logic_vector(unsigned(SP) + 1); -- ÕâÑùÊÇ¶ÔµÄ ao <= '1'; SP <= std_logic_vector(unsigned(SP) + 1); else ARo <= (others => 'Z'); ao <= '0'; end if; end if; else ARo <= (others => 'Z'); ao <= '0'; end if; end if; end process; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity psl_test_cover is end entity psl_test_cover; architecture test of psl_test_cover is signal s_rst_n : std_logic := '0'; signal s_clk : std_logic := '0'; signal s_write : std_logic; signal s_read : std_logic; begin s_rst_n <= '1' after 100 ns; s_clk <= not s_clk after 10 ns; TestP : process is begin report "RUNNING PSL_TEST_COVER test case"; report "================================"; s_write <= '0'; s_read <= '0'; wait until s_rst_n = '1' and rising_edge(s_clk); s_write <= '1'; -- cover should hit wait until rising_edge(s_clk); s_read <= '1'; -- assertion should hit wait until rising_edge(s_clk); s_write <= '0'; s_read <= '0'; wait; end process TestP; -- -psl statements -- psl default clock is rising_edge(s_clk); -- cover directive seems not supported (ignored by GHDL) -- psl cover always (s_write -> not(s_read)); end architecture test;