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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.core_defs.all;
use work.functions_and_types.all;
entity regfile is
port
(
clk : in std_logic; -- Clock signal
reset : in std_logic; -- Reset signal
ida : in integer range 0 to ireg_num_registers; -- Operand A register ID
idb : in integer range 0 to ireg_num_registers; -- Operand B register ID
idd : in integer range 0 to ireg_num_registers; -- destination register ID
ind : in std_logic_vector (data_bits-1 downto 0); -- data input
we : in std_logic; -- write enable
outa : out std_logic_vector (data_bits-1 downto 0); -- Operand A port read
outb : out std_logic_vector (data_bits-1 downto 0) -- Operand B port read
);
end regfile;
architecture regfile_impl of regfile is
subtype registerarray is array_1d_logic_vector (ireg_num_registers downto 1) (data_bits-1 downto 0);
signal registers : registerarray;
begin
-- Writing Process. Implied memory for signals without default values or default cases.
process(clk,reset) begin
if reset = '0' then
registers <= (others => (others => '0'));
elsif rising_edge(clk) then
if idd /= 0 and we = '1' then
registers(idd) <= ind;
end if;
end if;
end process;
process(all)
begin
case ida is
when 0 => outa <= sign_extend('0',outa'length);
when others => outa <= registers(ida); -- read operand a
end case;
case idb is
when 0 => outb <= sign_extend('0',outb'length);
when others => outb <= registers(idb); -- read operand a
end case;
end process;
end regfile_impl;
|
------------------------------------------------------------------------------
-- ZUnit Decoder
--
-- Project :
-- File : decoder.vhd
-- Authors : Rolf Enzler <enzler@ife.ee.ethz.ch>
-- Christian Plessl <plessl@tik.ee.ethz.ch>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/26
-- Last changed: $LastChangedDate: 2005-04-07 11:17:51 +0200 (Thu, 07 Apr 2005) $
------------------------------------------------------------------------------
-- address decoder that decodes the read/write commands on the host
-- interface and generates the appropriate control signals
-------------------------------------------------------------------------------
-- Changes:
-- 2004-10-06 CP added documentation
-------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- see ZArchPkg for ZUnit Register Mapping and Functions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
entity Decoder is
generic (
REGWIDTH : integer);
port (
RstxRB : in std_logic;
WrReqxEI : in std_logic;
RdReqxEI : in std_logic;
RegNrxDI : in std_logic_vector(REGWIDTH-1 downto 0);
SystRstxRBO : out std_logic; -- system reset
CCloadxEO : out std_logic; -- cycle counter load
VirtContextNoxEO : out std_logic; -- load number of contexts for
-- virtualization (temporal partitioning)
ContextSchedulerSelectxEO : out std_logic;
Fifo0WExEO : out std_logic; -- FIFO0 WE
Fifo0RExEO : out std_logic; -- FIFO0 RE
Fifo1WExEO : out std_logic; -- FIFO1 WE
Fifo1RExEO : out std_logic; -- FIFO1 RE
CMWExEO : out std_logic_vector(N_CONTEXTS-1 downto 0); -- CfgMem WE
CMLoadPtrxEO : out std_logic_vector(N_CONTEXTS-1 downto 0); -- CfgMemPtr
CSRxEO : out std_logic; -- context sel. load
EngClrCntxtxEO : out std_logic; -- engine clear context
SSWExEO : out std_logic; -- schedule store WE
SSIAddrxDO : out std_logic_vector(SIW_ADRWIDTH-1 downto 0); -- address
ScheduleStartxE : out std_logic; -- schedule start
DoutMuxSO : out std_logic_vector(2 downto 0)); -- Dout mux
end Decoder;
architecture simple of Decoder is
signal SoftRstxRB : std_logic;
begin -- simple
-- system reset
SystRstxRBO <= RstxRB and SoftRstxRB;
Decode : process (WrReqxEI, RdReqxEI, RegNrxDI)
begin -- process Decode
-- default signal assignments
SoftRstxRB <= '1';
CCloadxEO <= '0';
Fifo0WExEO <= '0';
Fifo0RExEO <= '0';
Fifo1WExEO <= '0';
Fifo1RExEO <= '0';
CMWExEO <= (others => '0');
CMLoadPtrxEO <= (others => '0');
CSRxEO <= '0';
EngClrCntxtxEO <= '0';
SSWExEO <= '0';
SSIAddrxDO <= (others => '0');
ScheduleStartxE <= '0';
DoutMuxSO <= (others => '0');
VirtContextNoxEO <= '0';
ContextSchedulerSelectxEO <= '0';
if WrReqxEI = '1' then -- WRITE REQUESTS
case to_integer(unsigned(RegNrxDI)) is
when ZREG_RST =>
SoftRstxRB <= '0';
when ZREG_FIFO0 =>
Fifo0WExEO <= '1';
when ZREG_FIFO1 =>
Fifo1WExEO <= '1';
when ZREG_CYCLECNT =>
CCloadxEO <= '1';
when ZREG_VIRTCONTEXTNO =>
VirtContextNoxEO <= '1';
when ZREG_CONTEXTSCHEDSEL =>
ContextSchedulerSelectxEO <= '1';
when ZREG_CFGMEM0 =>
CMWExEO(0) <= '1';
when ZREG_CFGMEM0PTR =>
CMLoadPtrxEO(0) <= '1';
when ZREG_CFGMEM1 =>
CMWExEO(1) <= '1';
when ZREG_CFGMEM1PTR =>
CMLoadPtrxEO(1) <= '1';
when ZREG_CFGMEM2 =>
CMWExEO(2) <= '1';
when ZREG_CFGMEM2PTR =>
CMLoadPtrxEO(2) <= '1';
when ZREG_CFGMEM3 =>
CMWExEO(3) <= '1';
when ZREG_CFGMEM3PTR =>
CMLoadPtrxEO(3) <= '1';
when ZREG_CFGMEM4 =>
CMWExEO(4) <= '1';
when ZREG_CFGMEM4PTR =>
CMLoadPtrxEO(4) <= '1';
when ZREG_CFGMEM5 =>
CMWExEO(5) <= '1';
when ZREG_CFGMEM5PTR =>
CMLoadPtrxEO(5) <= '1';
when ZREG_CFGMEM6 =>
CMWExEO(6) <= '1';
when ZREG_CFGMEM6PTR =>
CMLoadPtrxEO(6) <= '1';
when ZREG_CFGMEM7 =>
CMWExEO(7) <= '1';
when ZREG_CFGMEM7PTR =>
CMLoadPtrxEO(7) <= '1';
when ZREG_CONTEXTSEL =>
CSRxEO <= '1';
when ZREG_CONTEXTSELCLR =>
CSRxEO <= '1';
EngClrCntxtxEO <= '1';
when ZREG_SCHEDSTART =>
ScheduleStartxE <= '1';
when ZREG_SCHEDIWORD00 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "000";
when ZREG_SCHEDIWORD01 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "001";
when ZREG_SCHEDIWORD02 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "010";
when ZREG_SCHEDIWORD03 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "011";
when ZREG_SCHEDIWORD04 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "100";
when ZREG_SCHEDIWORD05 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "101";
when ZREG_SCHEDIWORD06 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "110";
when ZREG_SCHEDIWORD07 =>
SSWExEO <= '1';
SSIAddrxDO(2 downto 0) <= "111";
when others => assert false report "Corrupt ZREG access" severity error;
end case;
elsif RdReqxEI = '1' then -- READ REQUESTS
case to_integer(unsigned(RegNrxDI)) is
when ZREG_FIFO0 =>
Fifo0RExEO <= '1';
DoutMuxSO <= O"0";
when ZREG_FIFO0LEV =>
DoutMuxSO <= O"1";
when ZREG_FIFO1 =>
Fifo1RExEO <= '1';
DoutMuxSO <= O"2";
when ZREG_FIFO1LEV =>
DoutMuxSO <= O"3";
when ZREG_VIRTCONTEXTNO =>
DoutMuxSO <= O"4";
when ZREG_SCHEDSTATUS =>
DoutMuxSO <= O"6";
when ZREG_CYCLECNT =>
DoutMuxSO <= O"7";
when others => assert false report "Corrupt ZREG access" severity error;
end case;
end if;
end process Decode;
end simple;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity top_module_tb is -- entity declaration
end top_module_tb;
architecture sim of top_module_tb is
-- 100.00 MHz clock
constant c_clk_period : time := 10.00 ns;
constant c_sim_time : time := 1000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
signal clk100 : std_logic := '0';
signal s_locked : std_logic;
signal s_blink : std_logic_vector(7 downto 0);
-- Components
component top_module
port(
clk_i : in std_logic;
locked_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end component;
-- Functions
--function calculate_next_input_sample(sample_number : in integer) return std_logic_vector is
-- variable A : real := 1.0; -- Amplitude for wave
-- variable F : real := 100.0; -- Frequency for wave
-- variable P : real := 0.0; -- Phase for wave
-- variable theta : real;
-- variable y : real; -- The calculated value as a real
-- variable y_int : integer; -- The calculated value as an integer
-- variable result : std_logic_vector(c_ip_width-1 downto 0);
-- variable number_of_samples : real := 100.0 * real(47);
--begin
-- theta := (2.0 * MATH_PI * F * real(sample_number mod integer(number_of_samples))) / number_of_samples;
--y := A * sin(theta + P);
--y_int := integer(round(y * real(2**(c_ip_width-2))));
--result := std_logic_vector(to_signed(y_int, c_ip_width));
--return result;
--end function calculate_next_input_sample;
begin
cmp_top_module : top_module
port map
(
clk_i => clk100,
locked_i => s_locked,
blink_o => s_blink
);
--p_locked : process
--begin
-- s_locked <= '0';
-- wait for 20 ns;
--wait until rising_edge(clk100);
--wait until rising_edge(clk100);
--wait until rising_edge(clk100);
-- s_locked <= '1';
--end process p_locked;
p_clk_gen : process is
begin
while g_end_simulation = false loop
wait for c_clk_period/2;
clk100 <= not clk100;
wait for c_clk_period/2;
clk100 <= not clk100;
end loop;
wait; -- simulation stops here
end process p_clk_gen;
p_main_simulation : process is
begin
-- wait for c_sim_time;
-- g_end_simulation <= true;
-- wait;
s_locked <= '0';
wait for 2*c_clk_period;
s_locked <= '1';
wait for 100*c_clk_period;
-- End simualtion
g_end_simulation <= true;
end process p_main_simulation;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ClockGenerator is
generic(
count : natural := 50000000
);
port(
clk : in std_logic;
rst : in std_logic;
q : out std_logic
);
end entity ClockGenerator;
architecture RTL of ClockGenerator is
begin
process(clk, rst)
variable value : integer range 0 to count := 0;
begin
if (rst = '0') then
value := 0;
elsif (clk'event) and (clk = '1') then
value := value + 1;
end if;
if (value = count) then
value := 0;
q <= '1';
else
q <= '0';
end if;
end process;
end architecture RTL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axis_accelerator_adapter:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axis_accelerator_adapter_v2_1_6;
USE axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter;
ENTITY zc702_get_0_if_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_vld : IN STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END zc702_get_0_if_0;
ARCHITECTURE zc702_get_0_if_0_arch OF zc702_get_0_if_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_get_0_if_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_accelerator_adapter IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_AP_ADAPTER_ID : INTEGER;
C_N_INPUT_ARGS : INTEGER;
C_N_OUTPUT_ARGS : INTEGER;
C_S_AXIS_TDATA_WIDTH : INTEGER;
C_S_AXIS_TUSER_WIDTH : INTEGER;
C_S_AXIS_TID_WIDTH : INTEGER;
C_S_AXIS_TDEST_WIDTH : INTEGER;
C_AP_IARG_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_IARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_IARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_0_DWIDTH : INTEGER;
C_AP_IARG_1_DWIDTH : INTEGER;
C_AP_IARG_2_DWIDTH : INTEGER;
C_AP_IARG_3_DWIDTH : INTEGER;
C_AP_IARG_4_DWIDTH : INTEGER;
C_AP_IARG_5_DWIDTH : INTEGER;
C_AP_IARG_6_DWIDTH : INTEGER;
C_AP_IARG_7_DWIDTH : INTEGER;
C_M_AXIS_TDATA_WIDTH : INTEGER;
C_M_AXIS_TUSER_WIDTH : INTEGER;
C_M_AXIS_TID_WIDTH : INTEGER;
C_M_AXIS_TDEST_WIDTH : INTEGER;
C_AP_OARG_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_OARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_OARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_0_DWIDTH : INTEGER;
C_AP_OARG_1_DWIDTH : INTEGER;
C_AP_OARG_2_DWIDTH : INTEGER;
C_AP_OARG_3_DWIDTH : INTEGER;
C_AP_OARG_4_DWIDTH : INTEGER;
C_AP_OARG_5_DWIDTH : INTEGER;
C_AP_OARG_6_DWIDTH : INTEGER;
C_AP_OARG_7_DWIDTH : INTEGER;
C_N_INOUT_SCALARS : INTEGER;
C_N_INPUT_SCALARS : INTEGER;
C_INPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_INPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_OUTPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_AP_ISCALAR_DOUT_WIDTH : INTEGER;
C_AP_ISCALAR_IO_DOUT_WIDTH : INTEGER;
C_INPUT_SCALAR_0_WIDTH : INTEGER;
C_INPUT_SCALAR_1_WIDTH : INTEGER;
C_INPUT_SCALAR_2_WIDTH : INTEGER;
C_INPUT_SCALAR_3_WIDTH : INTEGER;
C_INPUT_SCALAR_4_WIDTH : INTEGER;
C_INPUT_SCALAR_5_WIDTH : INTEGER;
C_INPUT_SCALAR_6_WIDTH : INTEGER;
C_INPUT_SCALAR_7_WIDTH : INTEGER;
C_INPUT_SCALAR_8_WIDTH : INTEGER;
C_INPUT_SCALAR_9_WIDTH : INTEGER;
C_INPUT_SCALAR_10_WIDTH : INTEGER;
C_INPUT_SCALAR_11_WIDTH : INTEGER;
C_INPUT_SCALAR_12_WIDTH : INTEGER;
C_INPUT_SCALAR_13_WIDTH : INTEGER;
C_INPUT_SCALAR_14_WIDTH : INTEGER;
C_INPUT_SCALAR_15_WIDTH : INTEGER;
C_OUTPUT_SCALAR_0_WIDTH : INTEGER;
C_OUTPUT_SCALAR_1_WIDTH : INTEGER;
C_OUTPUT_SCALAR_2_WIDTH : INTEGER;
C_OUTPUT_SCALAR_3_WIDTH : INTEGER;
C_OUTPUT_SCALAR_4_WIDTH : INTEGER;
C_OUTPUT_SCALAR_5_WIDTH : INTEGER;
C_OUTPUT_SCALAR_6_WIDTH : INTEGER;
C_OUTPUT_SCALAR_7_WIDTH : INTEGER;
C_OUTPUT_SCALAR_8_WIDTH : INTEGER;
C_OUTPUT_SCALAR_9_WIDTH : INTEGER;
C_OUTPUT_SCALAR_10_WIDTH : INTEGER;
C_OUTPUT_SCALAR_11_WIDTH : INTEGER;
C_OUTPUT_SCALAR_12_WIDTH : INTEGER;
C_OUTPUT_SCALAR_13_WIDTH : INTEGER;
C_OUTPUT_SCALAR_14_WIDTH : INTEGER;
C_OUTPUT_SCALAR_15_WIDTH : INTEGER;
C_N_OUTPUT_SCALARS : INTEGER;
C_OUTPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_AP_OSCALAR_DIN_WIDTH : INTEGER;
C_AP_OSCALAR_IO_DIN_WIDTH : INTEGER;
C_ENABLE_STREAM_CLK : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_S_AXIS_HAS_TSTRB : INTEGER;
C_S_AXIS_HAS_TKEEP : INTEGER;
C_NONE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_aresetn : IN STD_LOGIC;
s_axis_0_aclk : IN STD_LOGIC;
s_axis_0_aresetn : IN STD_LOGIC;
s_axis_0_tvalid : IN STD_LOGIC;
s_axis_0_tready : OUT STD_LOGIC;
s_axis_0_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_0_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tlast : IN STD_LOGIC;
s_axis_0_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_aclk : IN STD_LOGIC;
s_axis_1_aresetn : IN STD_LOGIC;
s_axis_1_tvalid : IN STD_LOGIC;
s_axis_1_tready : OUT STD_LOGIC;
s_axis_1_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_1_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tlast : IN STD_LOGIC;
s_axis_1_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_aclk : IN STD_LOGIC;
s_axis_2_aresetn : IN STD_LOGIC;
s_axis_2_tvalid : IN STD_LOGIC;
s_axis_2_tready : OUT STD_LOGIC;
s_axis_2_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_2_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tlast : IN STD_LOGIC;
s_axis_2_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_aclk : IN STD_LOGIC;
s_axis_3_aresetn : IN STD_LOGIC;
s_axis_3_tvalid : IN STD_LOGIC;
s_axis_3_tready : OUT STD_LOGIC;
s_axis_3_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_3_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tlast : IN STD_LOGIC;
s_axis_3_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_aclk : IN STD_LOGIC;
s_axis_4_aresetn : IN STD_LOGIC;
s_axis_4_tvalid : IN STD_LOGIC;
s_axis_4_tready : OUT STD_LOGIC;
s_axis_4_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_4_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tlast : IN STD_LOGIC;
s_axis_4_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_aclk : IN STD_LOGIC;
s_axis_5_aresetn : IN STD_LOGIC;
s_axis_5_tvalid : IN STD_LOGIC;
s_axis_5_tready : OUT STD_LOGIC;
s_axis_5_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_5_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tlast : IN STD_LOGIC;
s_axis_5_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_aclk : IN STD_LOGIC;
s_axis_6_aresetn : IN STD_LOGIC;
s_axis_6_tvalid : IN STD_LOGIC;
s_axis_6_tready : OUT STD_LOGIC;
s_axis_6_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_6_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tlast : IN STD_LOGIC;
s_axis_6_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_aclk : IN STD_LOGIC;
s_axis_7_aresetn : IN STD_LOGIC;
s_axis_7_tvalid : IN STD_LOGIC;
s_axis_7_tready : OUT STD_LOGIC;
s_axis_7_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_7_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tlast : IN STD_LOGIC;
s_axis_7_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_iarg_0_clk : IN STD_LOGIC;
ap_iarg_0_rst : IN STD_LOGIC;
ap_iarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_ce : IN STD_LOGIC;
ap_iarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_clk : IN STD_LOGIC;
ap_iarg_1_rst : IN STD_LOGIC;
ap_iarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_ce : IN STD_LOGIC;
ap_iarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_clk : IN STD_LOGIC;
ap_iarg_2_rst : IN STD_LOGIC;
ap_iarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_ce : IN STD_LOGIC;
ap_iarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_clk : IN STD_LOGIC;
ap_iarg_3_rst : IN STD_LOGIC;
ap_iarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_ce : IN STD_LOGIC;
ap_iarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_clk : IN STD_LOGIC;
ap_iarg_4_rst : IN STD_LOGIC;
ap_iarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_ce : IN STD_LOGIC;
ap_iarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_clk : IN STD_LOGIC;
ap_iarg_5_rst : IN STD_LOGIC;
ap_iarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_ce : IN STD_LOGIC;
ap_iarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_clk : IN STD_LOGIC;
ap_iarg_6_rst : IN STD_LOGIC;
ap_iarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_ce : IN STD_LOGIC;
ap_iarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_clk : IN STD_LOGIC;
ap_iarg_7_rst : IN STD_LOGIC;
ap_iarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_ce : IN STD_LOGIC;
ap_iarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_read : IN STD_LOGIC;
ap_fifo_iarg_0_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_1_read : IN STD_LOGIC;
ap_fifo_iarg_1_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_2_read : IN STD_LOGIC;
ap_fifo_iarg_2_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_3_read : IN STD_LOGIC;
ap_fifo_iarg_3_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_4_read : IN STD_LOGIC;
ap_fifo_iarg_4_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_5_read : IN STD_LOGIC;
ap_fifo_iarg_5_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_6_read : IN STD_LOGIC;
ap_fifo_iarg_6_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_7_read : IN STD_LOGIC;
ap_fifo_iarg_7_empty_n : OUT STD_LOGIC;
m_axis_aclk : IN STD_LOGIC;
m_axis_aresetn : IN STD_LOGIC;
m_axis_0_aclk : IN STD_LOGIC;
m_axis_0_aresetn : IN STD_LOGIC;
m_axis_0_tvalid : OUT STD_LOGIC;
m_axis_0_tready : IN STD_LOGIC;
m_axis_0_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_0_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tlast : OUT STD_LOGIC;
m_axis_0_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_aclk : IN STD_LOGIC;
m_axis_1_aresetn : IN STD_LOGIC;
m_axis_1_tvalid : OUT STD_LOGIC;
m_axis_1_tready : IN STD_LOGIC;
m_axis_1_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_1_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tlast : OUT STD_LOGIC;
m_axis_1_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_aclk : IN STD_LOGIC;
m_axis_2_aresetn : IN STD_LOGIC;
m_axis_2_tvalid : OUT STD_LOGIC;
m_axis_2_tready : IN STD_LOGIC;
m_axis_2_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_2_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tlast : OUT STD_LOGIC;
m_axis_2_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_aclk : IN STD_LOGIC;
m_axis_3_aresetn : IN STD_LOGIC;
m_axis_3_tvalid : OUT STD_LOGIC;
m_axis_3_tready : IN STD_LOGIC;
m_axis_3_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_3_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tlast : OUT STD_LOGIC;
m_axis_3_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_aclk : IN STD_LOGIC;
m_axis_4_aresetn : IN STD_LOGIC;
m_axis_4_tvalid : OUT STD_LOGIC;
m_axis_4_tready : IN STD_LOGIC;
m_axis_4_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_4_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tlast : OUT STD_LOGIC;
m_axis_4_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_aclk : IN STD_LOGIC;
m_axis_5_aresetn : IN STD_LOGIC;
m_axis_5_tvalid : OUT STD_LOGIC;
m_axis_5_tready : IN STD_LOGIC;
m_axis_5_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_5_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tlast : OUT STD_LOGIC;
m_axis_5_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_aclk : IN STD_LOGIC;
m_axis_6_aresetn : IN STD_LOGIC;
m_axis_6_tvalid : OUT STD_LOGIC;
m_axis_6_tready : IN STD_LOGIC;
m_axis_6_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_6_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tlast : OUT STD_LOGIC;
m_axis_6_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_aclk : IN STD_LOGIC;
m_axis_7_aresetn : IN STD_LOGIC;
m_axis_7_tvalid : OUT STD_LOGIC;
m_axis_7_tready : IN STD_LOGIC;
m_axis_7_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_7_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tlast : OUT STD_LOGIC;
m_axis_7_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_oarg_0_clk : IN STD_LOGIC;
ap_oarg_0_rst : IN STD_LOGIC;
ap_oarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_ce : IN STD_LOGIC;
ap_oarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_clk : IN STD_LOGIC;
ap_oarg_1_rst : IN STD_LOGIC;
ap_oarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_ce : IN STD_LOGIC;
ap_oarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_clk : IN STD_LOGIC;
ap_oarg_2_rst : IN STD_LOGIC;
ap_oarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_ce : IN STD_LOGIC;
ap_oarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_clk : IN STD_LOGIC;
ap_oarg_3_rst : IN STD_LOGIC;
ap_oarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_ce : IN STD_LOGIC;
ap_oarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_clk : IN STD_LOGIC;
ap_oarg_4_rst : IN STD_LOGIC;
ap_oarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_ce : IN STD_LOGIC;
ap_oarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_clk : IN STD_LOGIC;
ap_oarg_5_rst : IN STD_LOGIC;
ap_oarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_ce : IN STD_LOGIC;
ap_oarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_clk : IN STD_LOGIC;
ap_oarg_6_rst : IN STD_LOGIC;
ap_oarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_ce : IN STD_LOGIC;
ap_oarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_clk : IN STD_LOGIC;
ap_oarg_7_rst : IN STD_LOGIC;
ap_oarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_ce : IN STD_LOGIC;
ap_oarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_write : IN STD_LOGIC;
ap_fifo_oarg_0_full_n : OUT STD_LOGIC;
ap_fifo_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_1_write : IN STD_LOGIC;
ap_fifo_oarg_1_full_n : OUT STD_LOGIC;
ap_fifo_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_2_write : IN STD_LOGIC;
ap_fifo_oarg_2_full_n : OUT STD_LOGIC;
ap_fifo_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_3_write : IN STD_LOGIC;
ap_fifo_oarg_3_full_n : OUT STD_LOGIC;
ap_fifo_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_4_write : IN STD_LOGIC;
ap_fifo_oarg_4_full_n : OUT STD_LOGIC;
ap_fifo_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_5_write : IN STD_LOGIC;
ap_fifo_oarg_5_full_n : OUT STD_LOGIC;
ap_fifo_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_6_write : IN STD_LOGIC;
ap_fifo_oarg_6_full_n : OUT STD_LOGIC;
ap_fifo_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_7_write : IN STD_LOGIC;
ap_fifo_oarg_7_full_n : OUT STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_8_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_9_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_10_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_11_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_12_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_13_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_14_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_15_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_8_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_9_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_10_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_11_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_12_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_13_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_14_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_15_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_vld : IN STD_LOGIC;
ap_oscalar_1_vld : IN STD_LOGIC;
ap_oscalar_2_vld : IN STD_LOGIC;
ap_oscalar_3_vld : IN STD_LOGIC;
ap_oscalar_4_vld : IN STD_LOGIC;
ap_oscalar_5_vld : IN STD_LOGIC;
ap_oscalar_6_vld : IN STD_LOGIC;
ap_oscalar_7_vld : IN STD_LOGIC;
ap_oscalar_8_vld : IN STD_LOGIC;
ap_oscalar_9_vld : IN STD_LOGIC;
ap_oscalar_10_vld : IN STD_LOGIC;
ap_oscalar_11_vld : IN STD_LOGIC;
ap_oscalar_12_vld : IN STD_LOGIC;
ap_oscalar_13_vld : IN STD_LOGIC;
ap_oscalar_14_vld : IN STD_LOGIC;
ap_oscalar_15_vld : IN STD_LOGIC;
ap_oscalar_0_ack : OUT STD_LOGIC;
ap_oscalar_1_ack : OUT STD_LOGIC;
ap_oscalar_2_ack : OUT STD_LOGIC;
ap_oscalar_3_ack : OUT STD_LOGIC;
ap_oscalar_4_ack : OUT STD_LOGIC;
ap_oscalar_5_ack : OUT STD_LOGIC;
ap_oscalar_6_ack : OUT STD_LOGIC;
ap_oscalar_7_ack : OUT STD_LOGIC;
ap_oscalar_8_ack : OUT STD_LOGIC;
ap_oscalar_9_ack : OUT STD_LOGIC;
ap_oscalar_10_ack : OUT STD_LOGIC;
ap_oscalar_11_ack : OUT STD_LOGIC;
ap_oscalar_12_ack : OUT STD_LOGIC;
ap_oscalar_13_ack : OUT STD_LOGIC;
ap_oscalar_14_ack : OUT STD_LOGIC;
ap_oscalar_15_ack : OUT STD_LOGIC;
ap_iscalar_0_ack : IN STD_LOGIC;
ap_iscalar_1_ack : IN STD_LOGIC;
ap_iscalar_2_ack : IN STD_LOGIC;
ap_iscalar_3_ack : IN STD_LOGIC;
ap_iscalar_4_ack : IN STD_LOGIC;
ap_iscalar_5_ack : IN STD_LOGIC;
ap_iscalar_6_ack : IN STD_LOGIC;
ap_iscalar_7_ack : IN STD_LOGIC;
ap_iscalar_8_ack : IN STD_LOGIC;
ap_iscalar_9_ack : IN STD_LOGIC;
ap_iscalar_10_ack : IN STD_LOGIC;
ap_iscalar_11_ack : IN STD_LOGIC;
ap_iscalar_12_ack : IN STD_LOGIC;
ap_iscalar_13_ack : IN STD_LOGIC;
ap_iscalar_14_ack : IN STD_LOGIC;
ap_iscalar_15_ack : IN STD_LOGIC;
ap_iscalar_0_vld : OUT STD_LOGIC;
ap_iscalar_1_vld : OUT STD_LOGIC;
ap_iscalar_2_vld : OUT STD_LOGIC;
ap_iscalar_3_vld : OUT STD_LOGIC;
ap_iscalar_4_vld : OUT STD_LOGIC;
ap_iscalar_5_vld : OUT STD_LOGIC;
ap_iscalar_6_vld : OUT STD_LOGIC;
ap_iscalar_7_vld : OUT STD_LOGIC;
ap_iscalar_8_vld : OUT STD_LOGIC;
ap_iscalar_9_vld : OUT STD_LOGIC;
ap_iscalar_10_vld : OUT STD_LOGIC;
ap_iscalar_11_vld : OUT STD_LOGIC;
ap_iscalar_12_vld : OUT STD_LOGIC;
ap_iscalar_13_vld : OUT STD_LOGIC;
ap_iscalar_14_vld : OUT STD_LOGIC;
ap_iscalar_15_vld : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT axis_accelerator_adapter;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL start";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done";
ATTRIBUTE X_INTERFACE_INFO OF ap_continue: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL continue";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL idle";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axis_accelerator_adapter
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_AP_ADAPTER_ID => 1,
C_N_INPUT_ARGS => 0,
C_N_OUTPUT_ARGS => 0,
C_S_AXIS_TDATA_WIDTH => 64,
C_S_AXIS_TUSER_WIDTH => 8,
C_S_AXIS_TID_WIDTH => 4,
C_S_AXIS_TDEST_WIDTH => 4,
C_AP_IARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_IARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_IARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_IARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_0_DWIDTH => 32,
C_AP_IARG_1_DWIDTH => 32,
C_AP_IARG_2_DWIDTH => 32,
C_AP_IARG_3_DWIDTH => 32,
C_AP_IARG_4_DWIDTH => 32,
C_AP_IARG_5_DWIDTH => 32,
C_AP_IARG_6_DWIDTH => 32,
C_AP_IARG_7_DWIDTH => 32,
C_M_AXIS_TDATA_WIDTH => 64,
C_M_AXIS_TUSER_WIDTH => 8,
C_M_AXIS_TID_WIDTH => 4,
C_M_AXIS_TDEST_WIDTH => 4,
C_AP_OARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_OARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_OARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_DIM => X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008",
C_AP_OARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_OARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_0_DWIDTH => 32,
C_AP_OARG_1_DWIDTH => 32,
C_AP_OARG_2_DWIDTH => 32,
C_AP_OARG_3_DWIDTH => 32,
C_AP_OARG_4_DWIDTH => 32,
C_AP_OARG_5_DWIDTH => 32,
C_AP_OARG_6_DWIDTH => 32,
C_AP_OARG_7_DWIDTH => 32,
C_N_INOUT_SCALARS => 0,
C_N_INPUT_SCALARS => 2,
C_INPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_INPUT_SCALAR_MODE => X"0000000000000000",
C_OUTPUT_SCALAR_MODE => X"0000000000000010",
C_AP_ISCALAR_DOUT_WIDTH => 64,
C_AP_ISCALAR_IO_DOUT_WIDTH => 32,
C_INPUT_SCALAR_0_WIDTH => 32,
C_INPUT_SCALAR_1_WIDTH => 32,
C_INPUT_SCALAR_2_WIDTH => 32,
C_INPUT_SCALAR_3_WIDTH => 32,
C_INPUT_SCALAR_4_WIDTH => 32,
C_INPUT_SCALAR_5_WIDTH => 32,
C_INPUT_SCALAR_6_WIDTH => 32,
C_INPUT_SCALAR_7_WIDTH => 32,
C_INPUT_SCALAR_8_WIDTH => 32,
C_INPUT_SCALAR_9_WIDTH => 32,
C_INPUT_SCALAR_10_WIDTH => 32,
C_INPUT_SCALAR_11_WIDTH => 32,
C_INPUT_SCALAR_12_WIDTH => 32,
C_INPUT_SCALAR_13_WIDTH => 32,
C_INPUT_SCALAR_14_WIDTH => 32,
C_INPUT_SCALAR_15_WIDTH => 32,
C_OUTPUT_SCALAR_0_WIDTH => 32,
C_OUTPUT_SCALAR_1_WIDTH => 32,
C_OUTPUT_SCALAR_2_WIDTH => 32,
C_OUTPUT_SCALAR_3_WIDTH => 32,
C_OUTPUT_SCALAR_4_WIDTH => 32,
C_OUTPUT_SCALAR_5_WIDTH => 32,
C_OUTPUT_SCALAR_6_WIDTH => 32,
C_OUTPUT_SCALAR_7_WIDTH => 32,
C_OUTPUT_SCALAR_8_WIDTH => 32,
C_OUTPUT_SCALAR_9_WIDTH => 32,
C_OUTPUT_SCALAR_10_WIDTH => 32,
C_OUTPUT_SCALAR_11_WIDTH => 32,
C_OUTPUT_SCALAR_12_WIDTH => 32,
C_OUTPUT_SCALAR_13_WIDTH => 32,
C_OUTPUT_SCALAR_14_WIDTH => 32,
C_OUTPUT_SCALAR_15_WIDTH => 32,
C_N_OUTPUT_SCALARS => 2,
C_OUTPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_AP_OSCALAR_DIN_WIDTH => 64,
C_AP_OSCALAR_IO_DIN_WIDTH => 32,
C_ENABLE_STREAM_CLK => 0,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_S_AXIS_HAS_TSTRB => 0,
C_S_AXIS_HAS_TKEEP => 0,
C_NONE => 2
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axis_aclk => '0',
s_axis_aresetn => '0',
s_axis_0_aclk => '0',
s_axis_0_aresetn => '0',
s_axis_0_tvalid => '0',
s_axis_0_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_0_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tlast => '0',
s_axis_0_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_aclk => '0',
s_axis_1_aresetn => '0',
s_axis_1_tvalid => '0',
s_axis_1_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_1_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tlast => '0',
s_axis_1_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_aclk => '0',
s_axis_2_aresetn => '0',
s_axis_2_tvalid => '0',
s_axis_2_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_2_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tlast => '0',
s_axis_2_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_aclk => '0',
s_axis_3_aresetn => '0',
s_axis_3_tvalid => '0',
s_axis_3_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_3_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tlast => '0',
s_axis_3_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_aclk => '0',
s_axis_4_aresetn => '0',
s_axis_4_tvalid => '0',
s_axis_4_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_4_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tlast => '0',
s_axis_4_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_aclk => '0',
s_axis_5_aresetn => '0',
s_axis_5_tvalid => '0',
s_axis_5_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_5_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tlast => '0',
s_axis_5_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_aclk => '0',
s_axis_6_aresetn => '0',
s_axis_6_tvalid => '0',
s_axis_6_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_6_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tlast => '0',
s_axis_6_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_aclk => '0',
s_axis_7_aresetn => '0',
s_axis_7_tvalid => '0',
s_axis_7_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_7_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tlast => '0',
s_axis_7_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ap_iarg_0_clk => '0',
ap_iarg_0_rst => '0',
ap_iarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_0_ce => '0',
ap_iarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_clk => '0',
ap_iarg_1_rst => '0',
ap_iarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_ce => '0',
ap_iarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_clk => '0',
ap_iarg_2_rst => '0',
ap_iarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_ce => '0',
ap_iarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_clk => '0',
ap_iarg_3_rst => '0',
ap_iarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_ce => '0',
ap_iarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_clk => '0',
ap_iarg_4_rst => '0',
ap_iarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_ce => '0',
ap_iarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_clk => '0',
ap_iarg_5_rst => '0',
ap_iarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_ce => '0',
ap_iarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_clk => '0',
ap_iarg_6_rst => '0',
ap_iarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_ce => '0',
ap_iarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_clk => '0',
ap_iarg_7_rst => '0',
ap_iarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_ce => '0',
ap_iarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_iarg_0_read => '0',
ap_fifo_iarg_1_read => '0',
ap_fifo_iarg_2_read => '0',
ap_fifo_iarg_3_read => '0',
ap_fifo_iarg_4_read => '0',
ap_fifo_iarg_5_read => '0',
ap_fifo_iarg_6_read => '0',
ap_fifo_iarg_7_read => '0',
m_axis_aclk => '0',
m_axis_aresetn => '0',
m_axis_0_aclk => '0',
m_axis_0_aresetn => '0',
m_axis_0_tready => '0',
m_axis_1_aclk => '0',
m_axis_1_aresetn => '0',
m_axis_1_tready => '0',
m_axis_2_aclk => '0',
m_axis_2_aresetn => '0',
m_axis_2_tready => '0',
m_axis_3_aclk => '0',
m_axis_3_aresetn => '0',
m_axis_3_tready => '0',
m_axis_4_aclk => '0',
m_axis_4_aresetn => '0',
m_axis_4_tready => '0',
m_axis_5_aclk => '0',
m_axis_5_aresetn => '0',
m_axis_5_tready => '0',
m_axis_6_aclk => '0',
m_axis_6_aresetn => '0',
m_axis_6_tready => '0',
m_axis_7_aclk => '0',
m_axis_7_aresetn => '0',
m_axis_7_tready => '0',
ap_oarg_0_clk => '0',
ap_oarg_0_rst => '0',
ap_oarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_0_ce => '0',
ap_oarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_clk => '0',
ap_oarg_1_rst => '0',
ap_oarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_ce => '0',
ap_oarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_clk => '0',
ap_oarg_2_rst => '0',
ap_oarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_ce => '0',
ap_oarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_clk => '0',
ap_oarg_3_rst => '0',
ap_oarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_ce => '0',
ap_oarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_clk => '0',
ap_oarg_4_rst => '0',
ap_oarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_ce => '0',
ap_oarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_clk => '0',
ap_oarg_5_rst => '0',
ap_oarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_ce => '0',
ap_oarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_clk => '0',
ap_oarg_6_rst => '0',
ap_oarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_ce => '0',
ap_oarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_clk => '0',
ap_oarg_7_rst => '0',
ap_oarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_ce => '0',
ap_oarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_write => '0',
ap_fifo_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_1_write => '0',
ap_fifo_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_2_write => '0',
ap_fifo_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_3_write => '0',
ap_fifo_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_4_write => '0',
ap_fifo_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_5_write => '0',
ap_fifo_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_6_write => '0',
ap_fifo_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_7_write => '0',
aclk => aclk,
aresetn => aresetn,
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_iscalar_0_dout => ap_iscalar_0_dout,
ap_iscalar_1_dout => ap_iscalar_1_dout,
ap_oscalar_0_din => ap_oscalar_0_din,
ap_oscalar_1_din => ap_oscalar_1_din,
ap_oscalar_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_8_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_9_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_10_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_11_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_12_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_13_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_14_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_15_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_0_vld => '0',
ap_oscalar_1_vld => ap_oscalar_1_vld,
ap_oscalar_2_vld => '0',
ap_oscalar_3_vld => '0',
ap_oscalar_4_vld => '0',
ap_oscalar_5_vld => '0',
ap_oscalar_6_vld => '0',
ap_oscalar_7_vld => '0',
ap_oscalar_8_vld => '0',
ap_oscalar_9_vld => '0',
ap_oscalar_10_vld => '0',
ap_oscalar_11_vld => '0',
ap_oscalar_12_vld => '0',
ap_oscalar_13_vld => '0',
ap_oscalar_14_vld => '0',
ap_oscalar_15_vld => '0',
ap_iscalar_0_ack => '0',
ap_iscalar_1_ack => '0',
ap_iscalar_2_ack => '0',
ap_iscalar_3_ack => '0',
ap_iscalar_4_ack => '0',
ap_iscalar_5_ack => '0',
ap_iscalar_6_ack => '0',
ap_iscalar_7_ack => '0',
ap_iscalar_8_ack => '0',
ap_iscalar_9_ack => '0',
ap_iscalar_10_ack => '0',
ap_iscalar_11_ack => '0',
ap_iscalar_12_ack => '0',
ap_iscalar_13_ack => '0',
ap_iscalar_14_ack => '0',
ap_iscalar_15_ack => '0',
interrupt => interrupt
);
END zc702_get_0_if_0_arch;
|
architecture rtl of fifo is
constant sig8 : record_type_3
(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)
(elementC(4 downto 1), elementD(1 downto 0)),
element5
(
elementE
(3 downto
0)
(6
downto 0)
,
elementF(7 downto 0)
),
element6(4 downto
0),
element7(7 downto 0));
constant sig9 : t_data_struct
(data(7 downto 0));
constant sig9 : t_data_struct
(
data(7 downto 0)
);
begin
end architecture rtl;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:01:11 05/24/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_oscilloscope_display.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: oscilloscope_display
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
USE work.types.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_oscilloscope_display IS
END test_oscilloscope_display;
ARCHITECTURE behavior OF test_oscilloscope_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT oscilloscope_display
PORT(
nrst : IN std_logic;
clk108 : IN std_logic;
is_reading_active : in std_logic;
trigger_event : in TRIGGER_EVENT_T;
red_enable : in std_logic;
green_enable : in std_logic;
blue_enable : in std_logic;
continue_after_reading : in std_logic;
time_resolution : in integer range 0 to 15;
addrb : OUT std_logic_vector(12 downto 0);
doutb : IN std_logic_vector(8 downto 0);
vout : OUT std_logic_vector(7 downto 0);
vsync : OUT std_logic;
hsync : OUT std_logic
);
END COMPONENT;
--Inputs
signal nrst : std_logic := '0';
signal clk108 : std_logic := '0';
signal doutb : std_logic_vector(8 downto 0) := (others => '0');
signal is_reading_active : std_logic := '0';
signal trigger_event : TRIGGER_EVENT_T := BUTTON_TRIGGER_T;
signal red_enable : std_logic := '1';
signal green_enable : std_logic := '1';
signal blue_enable : std_logic := '1';
signal continue_after_reading : std_logic := '0';
signal time_resolution : integer range 0 to 15;
--Outputs
signal addrb : std_logic_vector(12 downto 0);
signal vout : std_logic_vector(7 downto 0);
signal vsync : std_logic;
signal hsync : std_logic;
-- Clock period definitions
constant clk108_period : time := 10 ns;
-- Locals
signal clock_periods : std_logic_vector (15 downto 0) := (others => '0');
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: oscilloscope_display PORT MAP (
nrst => nrst,
clk108 => clk108,
is_reading_active => is_reading_active,
trigger_event => trigger_event,
red_enable => red_enable,
green_enable => green_enable,
blue_enable => blue_enable,
continue_after_reading => continue_after_reading,
time_resolution => time_resolution,
addrb => addrb,
doutb => doutb,
vout => vout,
vsync => vsync,
hsync => hsync
);
-- Clock process definitions
clk108_process :process
begin
clk108 <= '0';
wait for clk108_period/2;
clk108 <= '1';
if nrst = '1' then
clock_periods <= clock_periods + 1;
end if;
wait for clk108_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
nrst <= '0';
wait for clk108_period * 10;
nrst <= '1';
wait for clk108_period * 10;
-- insert stimulus here
wait;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hamcdtb IS
END hamcdtb;
ARCHITECTURE behavior OF hamcdtb IS
COMPONENT hamtm
PORT(
datain : IN std_logic_vector(31 downto 0);
data_out : OUT std_logic_vector(31 downto 0);
se : OUT std_logic;
de : OUT std_logic;
ne : OUT std_logic
);
END COMPONENT;
--Inputs
signal datain : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal data_out : std_logic_vector(31 downto 0);
signal se : std_logic;
signal de : std_logic;
signal ne : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hamtm PORT MAP (
datain => datain,
data_out => data_out,
se => se,
de => de,
ne => ne
);
stim_proc: process
begin
wait for 100 ns;
datain <="10101100101010111010101001111101";
end process;
END;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic arbiter
--
-- Description:
-- ------------------------------------
-- This module implements a generic arbiter. It currently support the
-- following arbitration strategies:
-- - Round Robin (RR)
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity bus_Arbiter is
generic (
STRATEGY : STRING := "RR"; -- RR, LOT
PORTS : POSITIVE := 1;
WEIGHTS : T_INTVEC := (0 => 1);
OUTPUT_REG : BOOLEAN := TRUE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Arbitrate : in STD_LOGIC;
Request_Vector : in STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Arbitrated : out STD_LOGIC;
Grant_Vector : out STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Grant_Index : out STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0)
);
end;
architecture rtl of bus_Arbiter is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
begin
-- Assert STRATEGY for known strings
-- ==========================================================================================================================================================
assert ((STRATEGY = "RR") OR (STRATEGY = "LOT"))
report "Unknown arbiter strategy." severity FAILURE;
-- Round Robin Arbiter
-- ==========================================================================================================================================================
genRR : if (STRATEGY = "RR") generate
signal RequestLeft : UNSIGNED(PORTS - 1 downto 0);
signal SelectLeft : UNSIGNED(PORTS - 1 downto 0);
signal SelectRight : UNSIGNED(PORTS - 1 downto 0);
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := to_slv(1, PORTS);
signal ChannelPointer_nxt : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
begin
ChannelPointer_en <= Arbitrate;
RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(Request_Vector);
SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft;
SelectRight <= (unsigned(not Request_Vector) + 1) and unsigned(Request_Vector);
ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft));
-- generate ChannelPointer register and unregistered outputs
genREG0 : if (OUTPUT_REG = FALSE) generate
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(1, PORTS);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
end if;
end if;
end process;
Arbitrated <= Arbitrate;
Grant_Vector <= ChannelPointer_nxt;
Grant_Index <= std_logic_vector(onehot2bin(ChannelPointer_nxt));
end generate;
-- generate ChannelPointer register and registered outputs
genREG1 : if (OUTPUT_REG = TRUE) generate
signal ChannelPointer_bin_d : STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0) := to_slv(0, log2ceilnz(PORTS) - 1);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(1, PORTS);
ChannelPointer_bin_d <= to_slv(0, log2ceilnz(PORTS) - 1);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
ChannelPointer_bin_d <= std_logic_vector(onehot2bin(ChannelPointer_nxt));
end if;
end if;
end process;
Arbitrated <= Arbitrate when rising_edge(Clock);
Grant_Vector <= ChannelPointer_d;
Grant_Index <= ChannelPointer_bin_d;
end generate;
end generate;
-- Lottery Arbiter
-- ==========================================================================================================================================================
-- genLOT : if (STRATEGY = "RR") generate
-- begin
--
-- end generate;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Generic arbiter
--
-- Description:
-- ------------------------------------
-- This module implements a generic arbiter. It currently support the
-- following arbitration strategies:
-- - Round Robin (RR)
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity bus_Arbiter is
generic (
STRATEGY : STRING := "RR"; -- RR, LOT
PORTS : POSITIVE := 1;
WEIGHTS : T_INTVEC := (0 => 1);
OUTPUT_REG : BOOLEAN := TRUE
);
port (
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Arbitrate : in STD_LOGIC;
Request_Vector : in STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Arbitrated : out STD_LOGIC;
Grant_Vector : out STD_LOGIC_VECTOR(PORTS - 1 downto 0);
Grant_Index : out STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0)
);
end;
architecture rtl of bus_Arbiter is
attribute KEEP : BOOLEAN;
attribute FSM_ENCODING : STRING;
begin
-- Assert STRATEGY for known strings
-- ==========================================================================================================================================================
assert ((STRATEGY = "RR") OR (STRATEGY = "LOT"))
report "Unknown arbiter strategy." severity FAILURE;
-- Round Robin Arbiter
-- ==========================================================================================================================================================
genRR : if (STRATEGY = "RR") generate
signal RequestLeft : UNSIGNED(PORTS - 1 downto 0);
signal SelectLeft : UNSIGNED(PORTS - 1 downto 0);
signal SelectRight : UNSIGNED(PORTS - 1 downto 0);
signal ChannelPointer_en : STD_LOGIC;
signal ChannelPointer : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
signal ChannelPointer_d : STD_LOGIC_VECTOR(PORTS - 1 downto 0) := to_slv(1, PORTS);
signal ChannelPointer_nxt : STD_LOGIC_VECTOR(PORTS - 1 downto 0);
begin
ChannelPointer_en <= Arbitrate;
RequestLeft <= (not ((unsigned(ChannelPointer_d) - 1) or unsigned(ChannelPointer_d))) and unsigned(Request_Vector);
SelectLeft <= (unsigned(not RequestLeft) + 1) and RequestLeft;
SelectRight <= (unsigned(not Request_Vector) + 1) and unsigned(Request_Vector);
ChannelPointer_nxt <= std_logic_vector(ite((RequestLeft = (RequestLeft'range => '0')), SelectRight, SelectLeft));
-- generate ChannelPointer register and unregistered outputs
genREG0 : if (OUTPUT_REG = FALSE) generate
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(1, PORTS);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
end if;
end if;
end process;
Arbitrated <= Arbitrate;
Grant_Vector <= ChannelPointer_nxt;
Grant_Index <= std_logic_vector(onehot2bin(ChannelPointer_nxt));
end generate;
-- generate ChannelPointer register and registered outputs
genREG1 : if (OUTPUT_REG = TRUE) generate
signal ChannelPointer_bin_d : STD_LOGIC_VECTOR(log2ceilnz(PORTS) - 1 downto 0) := to_slv(0, log2ceilnz(PORTS) - 1);
begin
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
ChannelPointer_d <= to_slv(1, PORTS);
ChannelPointer_bin_d <= to_slv(0, log2ceilnz(PORTS) - 1);
elsif (ChannelPointer_en = '1') then
ChannelPointer_d <= ChannelPointer_nxt;
ChannelPointer_bin_d <= std_logic_vector(onehot2bin(ChannelPointer_nxt));
end if;
end if;
end process;
Arbitrated <= Arbitrate when rising_edge(Clock);
Grant_Vector <= ChannelPointer_d;
Grant_Index <= ChannelPointer_bin_d;
end generate;
end generate;
-- Lottery Arbiter
-- ==========================================================================================================================================================
-- genLOT : if (STRATEGY = "RR") generate
-- begin
--
-- end generate;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a
--
-- Generated
-- by: wig
-- on: Thu Feb 10 18:54:13 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../typecast.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a-rtl-conf-c.vhd,v 1.3 2005/04/14 06:53:00 wig Exp $
-- $Date: 2005/04/14 06:53:00 $
-- $Log: inst_a-rtl-conf-c.vhd,v $
-- Revision 1.3 2005/04/14 06:53:00 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.33 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_rtl_conf / inst_a
--
configuration inst_a_rtl_conf of inst_a is
for rtl
-- Generated Configuration
for inst_aa_i : inst_aa
use configuration work.inst_aa_rtl_conf;
end for;
for inst_ab_i : inst_ab
use configuration work.inst_ab_rtl_conf;
end for;
end for;
end inst_a_rtl_conf;
--
-- End of Generated Configuration inst_a_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task1_ent_tb3 is
end entity Task1_ent_tb3;
architecture Task1_arch_tb3 of Task1_ent_tb3 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task1 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task1;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task1
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test reset - state(i)
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
-- Test length 14
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task1_arch_tb3;
configuration Task1_cfg_tb3 of Task1_ent_tb3 is
for Task1_arch_tb3
for UUT : Task1 use entity work.Task1(Beh);
end for;
end for;
end Task1_cfg_tb3;
|
-------------------------------------------------------------------------------
-- correct_one_bit.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
-- Filename: correct_one_bit.vhd
--
-- Description: Identifies single bit to correct in 32-bit word of
-- data read from memory as indicated by the syndrome input
-- vector.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/1/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity Correct_One_Bit is
generic (
C_USE_LUT6 : boolean := true;
Correct_Value : std_logic_vector(0 to 6));
port (
DIn : in std_logic;
Syndrome : in std_logic_vector(0 to 6);
DCorr : out std_logic);
end entity Correct_One_Bit;
architecture IMP of Correct_One_Bit is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
-----------------------------------------------------------------------------
-- Find which bit that has a '1'
-- There is always one bit which has a '1'
-----------------------------------------------------------------------------
function find_one (Syn : std_logic_vector(0 to 6)) return natural is
begin -- function find_one
for I in 0 to 6 loop
if (Syn(I) = '1') then
return I;
end if;
end loop; -- I
return 0; -- Should never reach this statement
end function find_one;
constant di_index : natural := find_one(Correct_Value);
signal corr_sel : std_logic;
signal corr_c : std_logic;
signal lut_compare : std_logic_vector(0 to 5);
signal lut_corr_val : std_logic_vector(0 to 5);
begin -- architecture IMP
Remove_DI_Index : process (Syndrome) is
begin -- process Remove_DI_Index
if (di_index = 0) then
lut_compare <= Syndrome(1 to 6);
lut_corr_val <= Correct_Value(1 to 6);
elsif (di_index = 6) then
lut_compare <= Syndrome(0 to 5);
lut_corr_val <= Correct_Value(0 to 5);
else
lut_compare <= Syndrome(0 to di_index-1) & Syndrome(di_index+1 to 6);
lut_corr_val <= Correct_Value(0 to di_index-1) & Correct_Value(di_index+1 to 6);
end if;
end process Remove_DI_Index;
-- Corr_LUT : LUT6
-- generic map(
-- INIT => X"6996966996696996"
-- )
-- port map(
-- O => corr_sel, -- [out]
-- I0 => InA(5), -- [in]
-- I1 => InA(4), -- [in]
-- I2 => InA(3), -- [in]
-- I3 => InA(2), -- [in]
-- I4 => InA(1), -- [in]
-- I5 => InA(0) -- [in]
-- );
corr_sel <= '0' when lut_compare = lut_corr_val else '1';
Corr_MUXCY : MUXCY_L
port map (
DI => Syndrome(di_index),
CI => '0',
S => corr_sel,
LO => corr_c);
Corr_XORCY : XORCY
port map (
LI => DIn,
CI => corr_c,
O => DCorr);
end architecture IMP;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1009.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01009pkg is
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
end c06s03b00x00p09n01i01009pkg;
use work.c06s03b00x00p09n01i01009pkg.all;
ENTITY c06s03b00x00p09n01i01009ent IS
END c06s03b00x00p09n01i01009ent;
ARCHITECTURE c06s03b00x00p09n01i01009arch OF c06s03b00x00p09n01i01009ent IS
BEGIN
TESTING: PROCESS
variable V1 : work.c06s03b00x00p09n01i01009pkg.T2 ; -- No_failure_here
BEGIN
V1.S11 := '1';
V1.S12.S1 := '1';
V1.S12.S2 := 1 ;
assert NOT(V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***PASSED TEST: c06s03b00x00p09n01i01009"
severity NOTE;
assert (V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***FAILED TEST: c06s03b00x00p09n01i01009 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01009arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1009.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01009pkg is
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
end c06s03b00x00p09n01i01009pkg;
use work.c06s03b00x00p09n01i01009pkg.all;
ENTITY c06s03b00x00p09n01i01009ent IS
END c06s03b00x00p09n01i01009ent;
ARCHITECTURE c06s03b00x00p09n01i01009arch OF c06s03b00x00p09n01i01009ent IS
BEGIN
TESTING: PROCESS
variable V1 : work.c06s03b00x00p09n01i01009pkg.T2 ; -- No_failure_here
BEGIN
V1.S11 := '1';
V1.S12.S1 := '1';
V1.S12.S2 := 1 ;
assert NOT(V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***PASSED TEST: c06s03b00x00p09n01i01009"
severity NOTE;
assert (V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***FAILED TEST: c06s03b00x00p09n01i01009 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01009arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1009.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p09n01i01009pkg is
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
end c06s03b00x00p09n01i01009pkg;
use work.c06s03b00x00p09n01i01009pkg.all;
ENTITY c06s03b00x00p09n01i01009ent IS
END c06s03b00x00p09n01i01009ent;
ARCHITECTURE c06s03b00x00p09n01i01009arch OF c06s03b00x00p09n01i01009ent IS
BEGIN
TESTING: PROCESS
variable V1 : work.c06s03b00x00p09n01i01009pkg.T2 ; -- No_failure_here
BEGIN
V1.S11 := '1';
V1.S12.S1 := '1';
V1.S12.S2 := 1 ;
assert NOT(V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***PASSED TEST: c06s03b00x00p09n01i01009"
severity NOTE;
assert (V1.S11 = '1' and
V1.S12.S1 = '1' and
V1.S12.S2 = 1 )
report "***FAILED TEST: c06s03b00x00p09n01i01009 - Expanded name is illegal."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p09n01i01009arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2131.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02131ent IS
END c07s02b04x00p20n01i02131ent;
ARCHITECTURE c07s02b04x00p20n01i02131arch OF c07s02b04x00p20n01i02131ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_8 is integer_v (1 to 8);
BEGIN
TESTING: PROCESS
variable r_operand : integer_4 := ( 5,6,7,8 );
variable l_operand1: integer := 1;
variable l_operand2: integer := 2;
variable l_operand3: integer := 3;
variable l_operand4: integer := 4;
variable result : integer_8;
BEGIN
result := l_operand1 &
l_operand2 &
l_operand3 &
l_operand4 &
r_operand;
assert (result = (1,2,3,4,5,6,7,8))
report "integer implicit array concatenation failed"
severity FAILURE;
assert NOT(result = (1,2,3,4,5,6,7,8))
report "***PASSED TEST: c07s02b04x00p20n01i02131"
severity NOTE;
assert (result = (1,2,3,4,5,6,7,8))
report "***FAILED TEST: c07s02b04x00p20n01i02131 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02131arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2131.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02131ent IS
END c07s02b04x00p20n01i02131ent;
ARCHITECTURE c07s02b04x00p20n01i02131arch OF c07s02b04x00p20n01i02131ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_8 is integer_v (1 to 8);
BEGIN
TESTING: PROCESS
variable r_operand : integer_4 := ( 5,6,7,8 );
variable l_operand1: integer := 1;
variable l_operand2: integer := 2;
variable l_operand3: integer := 3;
variable l_operand4: integer := 4;
variable result : integer_8;
BEGIN
result := l_operand1 &
l_operand2 &
l_operand3 &
l_operand4 &
r_operand;
assert (result = (1,2,3,4,5,6,7,8))
report "integer implicit array concatenation failed"
severity FAILURE;
assert NOT(result = (1,2,3,4,5,6,7,8))
report "***PASSED TEST: c07s02b04x00p20n01i02131"
severity NOTE;
assert (result = (1,2,3,4,5,6,7,8))
report "***FAILED TEST: c07s02b04x00p20n01i02131 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02131arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2131.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02131ent IS
END c07s02b04x00p20n01i02131ent;
ARCHITECTURE c07s02b04x00p20n01i02131arch OF c07s02b04x00p20n01i02131ent IS
TYPE integer_v is array (integer range <>) of integer;
SUBTYPE integer_4 is integer_v (1 to 4);
SUBTYPE integer_8 is integer_v (1 to 8);
BEGIN
TESTING: PROCESS
variable r_operand : integer_4 := ( 5,6,7,8 );
variable l_operand1: integer := 1;
variable l_operand2: integer := 2;
variable l_operand3: integer := 3;
variable l_operand4: integer := 4;
variable result : integer_8;
BEGIN
result := l_operand1 &
l_operand2 &
l_operand3 &
l_operand4 &
r_operand;
assert (result = (1,2,3,4,5,6,7,8))
report "integer implicit array concatenation failed"
severity FAILURE;
assert NOT(result = (1,2,3,4,5,6,7,8))
report "***PASSED TEST: c07s02b04x00p20n01i02131"
severity NOTE;
assert (result = (1,2,3,4,5,6,7,8))
report "***FAILED TEST: c07s02b04x00p20n01i02131 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02131arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc473.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00473ent IS
END c03s02b01x01p19n01i00473ent;
ARCHITECTURE c03s02b01x01p19n01i00473arch OF c03s02b01x01p19n01i00473ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type array_rec_2cons is array (integer range <>) of record_2cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C66 : array_rec_2cons(0 to 7) := (others => C52) ;
function complex_scalar(s : array_rec_2cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_2cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_2cons(0 to 7);
signal S2 : array_rec_2cons(0 to 7);
signal S3 : array_rec_2cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00473"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00473 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00473arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc473.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00473ent IS
END c03s02b01x01p19n01i00473ent;
ARCHITECTURE c03s02b01x01p19n01i00473arch OF c03s02b01x01p19n01i00473ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type array_rec_2cons is array (integer range <>) of record_2cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C66 : array_rec_2cons(0 to 7) := (others => C52) ;
function complex_scalar(s : array_rec_2cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_2cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_2cons(0 to 7);
signal S2 : array_rec_2cons(0 to 7);
signal S3 : array_rec_2cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00473"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00473 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00473arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc473.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00473ent IS
END c03s02b01x01p19n01i00473ent;
ARCHITECTURE c03s02b01x01p19n01i00473arch OF c03s02b01x01p19n01i00473ent IS
type column is range 1 to 2;
type row is range 1 to 8;
type s2boolean_cons_vector is array (row,column) of boolean;
type s2bit_cons_vector is array (row,column) of bit;
type s2char_cons_vector is array (row,column) of character;
type s2severity_level_cons_vector is array (row,column) of severity_level;
type s2integer_cons_vector is array (row,column) of integer;
type s2real_cons_vector is array (row,column) of real;
type s2time_cons_vector is array (row,column) of time;
type s2natural_cons_vector is array (row,column) of natural;
type s2positive_cons_vector is array (row,column) of positive;
type record_2cons_array is record
a:s2boolean_cons_vector;
b:s2bit_cons_vector;
c:s2char_cons_vector;
d:s2severity_level_cons_vector;
e:s2integer_cons_vector;
f:s2real_cons_vector;
g:s2time_cons_vector;
h:s2natural_cons_vector;
i:s2positive_cons_vector;
end record;
type array_rec_2cons is array (integer range <>) of record_2cons_array;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C41 : s2boolean_cons_vector := (others => (others => C1));
constant C42 : s2bit_cons_vector := (others => (others => C2));
constant C43 : s2char_cons_vector := (others => (others => C3));
constant C44 : s2severity_level_cons_vector := (others => (others => C4));
constant C45 : s2integer_cons_vector := (others => (others => C5));
constant C46 : s2real_cons_vector := (others => (others => C6));
constant C47 : s2time_cons_vector := (others => (others => C7));
constant C48 : s2natural_cons_vector := (others => (others => C8));
constant C49 : s2positive_cons_vector := (others => (others => C9));
constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
constant C66 : array_rec_2cons(0 to 7) := (others => C52) ;
function complex_scalar(s : array_rec_2cons(0 to 7)) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_2cons is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_2cons(0 to 7);
signal S2 : array_rec_2cons(0 to 7);
signal S3 : array_rec_2cons(0 to 7):= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00473"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00473 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00473arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity video is
Port (
CLK : in std_logic; -- Pixel clock 32.5MHz
RESET : in std_logic; -- Reset (active low)
CACHE_SWAP : out std_logic; -- Active buffer
CACHE_A : out std_logic_vector(5 downto 0); -- Cache address
CACHE_D : in std_logic_vector(7 downto 0); -- Cache data
CURRENT_LINE : out std_logic_vector(7 downto 0); -- Current line to read in cache
COLORS : in std_logic_vector(6 downto 0);
R : out std_logic_vector(3 downto 0); -- Red
G : out std_logic_vector(3 downto 0); -- Green
B : out std_logic_vector(3 downto 0); -- Blue
HSYNC : out std_logic; -- Hor. sync
VSYNC : out std_logic -- Ver. sync
);
end video;
architecture BEHAVIORAL of video is
-- VGA timing constants (XGA - 1024x768@60) (512x768@60)
-- HOR
constant HSIZE : INTEGER := 512; -- Visible area
constant HFP : INTEGER := 12; -- Front porch
constant HS : INTEGER := 68; -- HSync pulse
constant HB : INTEGER := 80; -- Back porch
constant HOFFSET : INTEGER := 0; -- HSync offset
-- VER
constant VSIZE : INTEGER := 768; -- Visible area
constant VFP : INTEGER := 3; -- Front porch
constant VS : INTEGER := 6; -- VSync pulse
constant VB : INTEGER := 29; -- Back porch
constant VOFFSET : INTEGER := 0; -- VSync offset
------------------------------------------------------------
signal H_COUNTER : UNSIGNED(9 downto 0); -- Horizontal Counter
signal V_COUNTER : UNSIGNED(9 downto 0); -- Vertical Counter
signal THREE_ROW_CNT : UNSIGNED(1 downto 0); -- 3 Row Counter
signal ROW_COUNTER : UNSIGNED(7 downto 0); -- Korvet Row Counter
signal PAPER : STD_LOGIC; -- Paper zone
signal PAPER_L : STD_LOGIC; -- Paper zone latched
signal COLOR_R : STD_LOGIC;
signal COLOR_G : STD_LOGIC;
signal COLOR_B : STD_LOGIC;
signal PIX0 : STD_LOGIC_VECTOR(3 downto 0);
signal PIX1 : STD_LOGIC_VECTOR(3 downto 0);
begin
u_COLOR_MUX : entity work.clr_mux
port map(
color => PIX1(3 - to_integer(H_COUNTER(2 downto 1))) & PIX0(3 - to_integer(H_COUNTER(2 downto 1))),
portb => COLORS,
out_r => COLOR_R,
out_g => COLOR_G,
out_b => COLOR_B );
CURRENT_LINE <= std_logic_vector(ROW_COUNTER);
process (CLK) -- H/V Counters
begin
if rising_edge(CLK) then
if RESET = '0' then
H_COUNTER <= (others=>'0');
V_COUNTER <= (others=>'0');
else
H_COUNTER <= H_COUNTER + 1;
if H_COUNTER = (HSIZE + HFP + HS + HB - 1) then
H_COUNTER <= (others=>'0');
V_COUNTER <= V_COUNTER + 1;
if V_COUNTER = (VSIZE + VFP + VS + VB - 1) then
V_COUNTER <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if RESET = '0' then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= (others=>'0');
CACHE_SWAP <= '0';
else
CACHE_SWAP <= '0';
if H_COUNTER = 544 then
if V_COUNTER < 768 then
THREE_ROW_CNT <= THREE_ROW_CNT + 1;
if THREE_ROW_CNT = 2 then
THREE_ROW_CNT <= (others=>'0');
ROW_COUNTER <= ROW_COUNTER + 1;
CACHE_SWAP <= '1';
end if;
else
ROW_COUNTER <= (others=>'0');
THREE_ROW_CNT <= (others=>'0');
end if;
end if;
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
HSYNC <= '1';
VSYNC <= '1';
PAPER <= '0';
if H_COUNTER >= (HSIZE + HOFFSET + HFP) and H_COUNTER < (HSIZE + HOFFSET + HFP + HS) then
HSYNC <= '0';
end if;
if V_COUNTER >= (VSIZE + VOFFSET + VFP) and V_COUNTER < (VSIZE + VOFFSET + VFP + VS) then
VSYNC <= '0';
end if;
if H_COUNTER < HSIZE and V_COUNTER < VSIZE then
PAPER <= '1';
end if;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
case H_COUNTER(2 downto 0) is
when "001" =>
CACHE_A <= std_logic_vector(H_COUNTER(8 downto 3));
when "111" =>
PIX0 <= CACHE_D(3 downto 0);
PIX1 <= CACHE_D(7 downto 4);
PAPER_L <= PAPER;
when OTHERS =>
null;
end case;
end if;
end process;
process (CLK)
begin
if rising_edge(CLK) then
if PAPER_L = '1' then
if THREE_ROW_CNT = "01" then
R <= COLOR_R & COLOR_R & COLOR_R & COLOR_R;
G <= COLOR_G & COLOR_G & COLOR_G & COLOR_G;
B <= COLOR_B & COLOR_B & COLOR_B & COLOR_B;
else
R <= COLOR_R & "000";
G <= COLOR_G & "000";
B <= COLOR_B & "000";
end if;
else
R <= (others=>'0');
G <= (others=>'0');
B <= (others=>'0');
end if;
end if;
end process;
end BEHAVIORAL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc281.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p08n02i00281ent IS
END c03s01b03x00p08n02i00281ent;
ARCHITECTURE c03s01b03x00p08n02i00281arch OF c03s01b03x00p08n02i00281ent IS
type UPLE is range 1 to 8
units
single;
duple = 2 single;
triple = 3 single;
quadruple = 2 duple;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
variable k : UPLE := 1 duple;
BEGIN
assert NOT(k = 2 single)
report "***PASSED TEST: c03s01b03x00p08n02i00281"
severity NOTE;
assert (k = 2 single)
report "***FAILED TEST: c03s01b03x00p08n02i00281 - The relative order of secondary unit declarations is not fixed as long as units are not used before they are declared."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p08n02i00281arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc281.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p08n02i00281ent IS
END c03s01b03x00p08n02i00281ent;
ARCHITECTURE c03s01b03x00p08n02i00281arch OF c03s01b03x00p08n02i00281ent IS
type UPLE is range 1 to 8
units
single;
duple = 2 single;
triple = 3 single;
quadruple = 2 duple;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
variable k : UPLE := 1 duple;
BEGIN
assert NOT(k = 2 single)
report "***PASSED TEST: c03s01b03x00p08n02i00281"
severity NOTE;
assert (k = 2 single)
report "***FAILED TEST: c03s01b03x00p08n02i00281 - The relative order of secondary unit declarations is not fixed as long as units are not used before they are declared."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p08n02i00281arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc281.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p08n02i00281ent IS
END c03s01b03x00p08n02i00281ent;
ARCHITECTURE c03s01b03x00p08n02i00281arch OF c03s01b03x00p08n02i00281ent IS
type UPLE is range 1 to 8
units
single;
duple = 2 single;
triple = 3 single;
quadruple = 2 duple;
pentuple = 5 single;
sextuple = 2 triple;
septuple = 7 single;
octuple = 2 quadruple;
end units;
BEGIN
TESTING: PROCESS
variable k : UPLE := 1 duple;
BEGIN
assert NOT(k = 2 single)
report "***PASSED TEST: c03s01b03x00p08n02i00281"
severity NOTE;
assert (k = 2 single)
report "***FAILED TEST: c03s01b03x00p08n02i00281 - The relative order of secondary unit declarations is not fixed as long as units are not used before they are declared."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p08n02i00281arch;
|
-- Execute module
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY Execute IS
PORT(
read_data_1 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2 : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALUSrc : IN STD_LOGIC;
SignExtend : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
PC : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Zero : OUT STD_LOGIC;
ADDResult : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Sl : IN STD_LOGIC;
Sr : IN STD_LOGIC;
Shamt : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
-- *** ACRESCENTE AS ENTRADAS ABAIXO,
-- Function vem direto da top level e ALUOp vem do control
-- Function são os 6 bits menos significativos da instrução
ALUOp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 );
Function_opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 )
);
END Execute;
ARCHITECTURE behavior OF Execute IS
-- *** ACRESCENTE A DECLARAÇÃO DE AINPUT
SIGNAL AInput : STD_LOGIC_VECTOR(31 DOWNTO 0 );
SIGNAL ALU_ctl : STD_LOGIC_VECTOR( 3 DOWNTO 0 );
SIGNAL BInput : STD_LOGIC_VECTOR(31 DOWNTO 0 );
SIGNAL ALU_output_mux : STD_LOGIC_VECTOR(31 DOWNTO 0 );
BEGIN
-- *** ACRESCENTE A ATRIBUIÇÃO A AINPUT
AInput <= read_data_1;
BInput <= read_data_2 WHEN ALUSrc = '0' ELSE SignExtend;
-- *** SUBSTITUA A DESCRIÇÃO DE SOMA ABAIXO PELA ATRIBUIÇÃO E PELO PROCESS A SEGUIR
-- ALU_Result <= Read_data_1 + BImput;
-- Gera ALU control bits (de acordo com PATERSON)
ALU_ctl( 0 ) <= ( Function_opcode( 0 ) OR Function_opcode( 3 ) ) AND ALUOp(1 );
ALU_ctl( 1 ) <= ( NOT Function_opcode( 2 ) ) OR (NOT ALUOp( 1 ) );
ALU_ctl( 2 ) <= ( Function_opcode( 1 ) AND ALUOp( 1 )) OR ALUOp( 0 );
ALU_ctl( 3 ) <= Sl OR Sr;
Zero <= '1' WHEN ( ALU_output_mux( 31 DOWNTO 0 ) = X"00000000" ) ELSE '0';
--Calcula próximo endereco de acordo com o SignExtend (endereco de pulo)
ADDResult <= PC + 1 + SignExtend(7 DOWNTO 0);
ALU_result <= X"0000000"&B"000"&ALU_output_mux( 31 ) WHEN ALU_ctl = "0111" ELSE ALU_output_mux( 31 DOWNTO 0 );
PROCESS ( ALU_ctl, Ainput, Binput )
BEGIN
-- Select ALU operation
CASE ALU_ctl IS
-- ALU performs ALUresult = A_input AND B_input
WHEN "0000" => ALU_output_mux <= Ainput AND Binput;
-- ALU performs ALUresult = A_input OR B_input
WHEN "0001" => ALU_output_mux <= Ainput OR Binput;
-- ALU performs ALUresult = A_input + B_input
WHEN "0010" => ALU_output_mux <= Ainput + Binput;
-- ALU performs ALUresult = A_input -B_input
WHEN "0110" => ALU_output_mux <= Ainput - Binput;
-- ALU performs SLT
WHEN "0111" => ALU_output_mux <= Ainput - Binput;
-- ALU performs Srl
WHEN "1110" => ALU_output_mux <= SHR(Binput, Shamt);
-- ALU performs Sll
WHEN "1010" => ALU_output_mux <= SHL(Binput, Shamt);
WHEN OTHERS => ALU_output_mux <= X"00000000" ;
END CASE;
END PROCESS;
END behavior; |
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 17:57:06 10/19/2015
-- Design Name:
-- Module Name: Universal_Shift_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: 4 bit Bidirectional Universal Shift Register
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Universal_Shift_Register is
Port ( Clr : in STD_LOGIC;
S0 : in STD_LOGIC;
S1 : in STD_LOGIC;
Clk : in STD_LOGIC;
SerialL : in STD_LOGIC;
SerialR : in STD_LOGIC;
ParallelInput : in STD_LOGIC_VECTOR (3 downto 0);
Output : out STD_LOGIC_VECTOR (3 downto 0));
end Universal_Shift_Register;
architecture Behavioral of Universal_Shift_Register is
--Embedded signal
signal Reg : STD_LOGIC_VECTOR (3 downto 0);
--frequency devider
--Declaraciones de constantes
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 1; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
--Declaracion de signals
signal Cont : integer range 0 to CtaMax;
signal ClkOut : STD_LOGIC;
begin
--Proceso que Divide la Frecuencia de entrada para obtener una Frecuencia de 1 Hz
process (Clr, Clk)
begin
if Clr = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process;
shift_reg: process(Clk, Clr, ClkOut)
begin
if (Clr = '1') then
Reg <= (others => '0');
elsif (rising_edge(Clk) and ClkOut='1') then
if S1 = '1' and S0 = '1' then
Reg <= ParallelInput;
elsif S1 = '0' and S0 = '1' then
Reg <= SerialR & Reg(3 downto 1);
elsif S1 = '1' and S0 = '0' then
Reg <= Reg(2 downto 0) & SerialL;
end if;
end if;
end process shift_reg;
Output <= Reg;
end Behavioral;
|
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8656)
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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4DkiBxiHsXx9/4ewIaY0c6deiFDTv/RCOaWQSv35DItMUMuYlAkogLcNJlgKoyayYVI4y0BOsy/u
5LVFbvDIH5TM03/sO1G9LOzNOwj8EPhTOEKK+D+A6d+iO2eV01nWTgEsl1gnSqnjuYgh+sUBVB4S
nsx+FsE44fk5ZO6+rmDInbain9Bq5wOVVa2HMWYcum07NKTnkO928jzdMkWFkwqB8hn6fsScG+iQ
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oIX6OomMAZFmArGPrTWxQsMQ+A+tV70FrcjuYkNpRz8rnJBVDJyqg6M2UpRozyqLKw==
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_oci_compute_input_tm_cnt is
port(
atm_valid : in vl_logic;
dtm_valid : in vl_logic;
itm_valid : in vl_logic;
compute_input_tm_cnt: out vl_logic_vector(1 downto 0)
);
end usb_system_cpu_nios2_oci_compute_input_tm_cnt;
|
-- nios.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios is
port (
altmemddr_0_auxfull_clk : out std_logic; -- altmemddr_0_auxfull.clk
altmemddr_0_auxhalf_clk : out std_logic; -- altmemddr_0_auxhalf.clk
clk50_clk : in std_logic := '0'; -- clk50.clk
io_ack : in std_logic := '0'; -- io.ack
io_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_read : out std_logic; -- .read
io_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_write : out std_logic; -- .write
io_address : out std_logic_vector(19 downto 0); -- .address
io_irq : in std_logic := '0'; -- .irq
mem32_address : in std_logic_vector(25 downto 0) := (others => '0'); -- mem32.address
mem32_direction : in std_logic := '0'; -- .direction
mem32_byte_en : in std_logic_vector(3 downto 0) := (others => '0'); -- .byte_en
mem32_wdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .wdata
mem32_request : in std_logic := '0'; -- .request
mem32_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .tag
mem32_dack_tag : out std_logic_vector(7 downto 0); -- .dack_tag
mem32_rdata : out std_logic_vector(31 downto 0); -- .rdata
mem32_rack : out std_logic; -- .rack
mem32_rack_tag : out std_logic_vector(7 downto 0); -- .rack_tag
mem_external_local_refresh_ack : out std_logic; -- mem_external.local_refresh_ack
mem_external_local_init_done : out std_logic; -- .local_init_done
mem_external_reset_phy_clk_n : out std_logic; -- .reset_phy_clk_n
memory_mem_odt : out std_logic_vector(0 downto 0); -- memory.mem_odt
memory_mem_clk : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_clk
memory_mem_clk_n : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_clk_n
memory_mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
memory_mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
memory_mem_addr : out std_logic_vector(13 downto 0); -- .mem_addr
memory_mem_ba : out std_logic_vector(1 downto 0); -- .mem_ba
memory_mem_ras_n : out std_logic; -- .mem_ras_n
memory_mem_cas_n : out std_logic; -- .mem_cas_n
memory_mem_we_n : out std_logic; -- .mem_we_n
memory_mem_dq : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dq
memory_mem_dqs : inout std_logic_vector(0 downto 0) := (others => '0'); -- .mem_dqs
memory_mem_dm : out std_logic_vector(0 downto 0); -- .mem_dm
pio_in_port : in std_logic_vector(31 downto 0) := (others => '0'); -- pio.in_port
pio_out_port : out std_logic_vector(31 downto 0); -- .out_port
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sys_clock_clk : out std_logic; -- sys_clock.clk
sys_reset_reset_n : out std_logic -- sys_reset.reset_n
);
end entity nios;
architecture rtl of nios is
component nios_altmemddr_0 is
port (
local_address : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
local_write_req : in std_logic := 'X'; -- write
local_read_req : in std_logic := 'X'; -- read
local_burstbegin : in std_logic := 'X'; -- beginbursttransfer
local_ready : out std_logic; -- waitrequest_n
local_rdata : out std_logic_vector(31 downto 0); -- readdata
local_rdata_valid : out std_logic; -- readdatavalid
local_wdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
local_be : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
local_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
local_refresh_ack : out std_logic; -- export
local_init_done : out std_logic; -- export
reset_phy_clk_n : out std_logic; -- export
mem_odt : out std_logic_vector(0 downto 0); -- mem_odt
mem_clk : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_clk
mem_clk_n : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_clk_n
mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n
mem_cke : out std_logic_vector(0 downto 0); -- mem_cke
mem_addr : out std_logic_vector(13 downto 0); -- mem_addr
mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
mem_ras_n : out std_logic; -- mem_ras_n
mem_cas_n : out std_logic; -- mem_cas_n
mem_we_n : out std_logic; -- mem_we_n
mem_dq : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dq
mem_dqs : inout std_logic_vector(0 downto 0) := (others => 'X'); -- mem_dqs
mem_dm : out std_logic_vector(0 downto 0); -- mem_dm
pll_ref_clk : in std_logic := 'X'; -- clk
soft_reset_n : in std_logic := 'X'; -- reset_n
global_reset_n : in std_logic := 'X'; -- reset_n
reset_request_n : out std_logic; -- reset_n
phy_clk : out std_logic; -- clk
aux_full_rate_clk : out std_logic; -- clk
aux_half_rate_clk : out std_logic -- clk
);
end component nios_altmemddr_0;
component avalon_to_io_bridge is
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(7 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
avs_irq : out std_logic -- irq
);
end component avalon_to_io_bridge;
component mem32_to_avalon_bridge is
port (
reset : in std_logic := 'X'; -- reset
clock : in std_logic := 'X'; -- clk
memreq_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
memreq_read_writen : in std_logic := 'X'; -- direction
memreq_byte_en : in std_logic_vector(3 downto 0) := (others => 'X'); -- byte_en
memreq_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- wdata
memreq_request : in std_logic := 'X'; -- request
memreq_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- tag
memresp_dack_tag : out std_logic_vector(7 downto 0); -- dack_tag
memresp_data : out std_logic_vector(31 downto 0); -- rdata
memresp_rack : out std_logic; -- rack
memresp_rack_tag : out std_logic_vector(7 downto 0); -- rack_tag
avm_read : out std_logic; -- read
avm_write : out std_logic; -- write
avm_address : out std_logic_vector(25 downto 0); -- address
avm_writedata : out std_logic_vector(31 downto 0); -- writedata
avm_byte_enable : out std_logic_vector(3 downto 0); -- byteenable
avm_ready : in std_logic := 'X'; -- waitrequest_n
avm_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avm_readdatavalid : in std_logic := 'X' -- readdatavalid
);
end component mem32_to_avalon_bridge;
component nios_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(28 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(28 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component nios_nios2_gen2_0;
component nios_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port : out std_logic_vector(31 downto 0); -- export
irq : out std_logic -- irq
);
end component nios_pio_0;
component nios_mm_interconnect_0 is
port (
altmemddr_0_sysclk_clk : in std_logic := 'X'; -- clk
mem32_to_avalon_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
mem32_to_avalon_0_avalon_master_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
mem32_to_avalon_0_avalon_master_waitrequest : out std_logic; -- waitrequest
mem32_to_avalon_0_avalon_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
mem32_to_avalon_0_avalon_master_read : in std_logic := 'X'; -- read
mem32_to_avalon_0_avalon_master_readdata : out std_logic_vector(31 downto 0); -- readdata
mem32_to_avalon_0_avalon_master_readdatavalid : out std_logic; -- readdatavalid
mem32_to_avalon_0_avalon_master_write : in std_logic := 'X'; -- write
mem32_to_avalon_0_avalon_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(28 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(28 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
altmemddr_0_s1_address : out std_logic_vector(23 downto 0); -- address
altmemddr_0_s1_write : out std_logic; -- write
altmemddr_0_s1_read : out std_logic; -- read
altmemddr_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altmemddr_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
altmemddr_0_s1_beginbursttransfer : out std_logic; -- beginbursttransfer
altmemddr_0_s1_burstcount : out std_logic_vector(2 downto 0); -- burstcount
altmemddr_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
altmemddr_0_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
altmemddr_0_s1_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_0_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_0_avalon_slave_0_write : out std_logic; -- write
io_bridge_0_avalon_slave_0_read : out std_logic; -- read
io_bridge_0_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_0_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
pio_0_s1_address : out std_logic_vector(2 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic -- chipselect
);
end component nios_mm_interconnect_0;
component nios_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component nios_irq_mapper;
component nios_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component nios_rst_controller;
component nios_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component nios_rst_controller_001;
signal altmemddr_0_sysclk_clk : std_logic; -- altmemddr_0:phy_clk -> [sys_clock_clk, io_bridge_0:clock, irq_mapper:clk, mem32_to_avalon_0:clock, mm_interconnect_0:altmemddr_0_sysclk_clk, nios2_gen2_0:clk, pio_0:clk, rst_controller:clk, rst_controller_001:clk]
signal mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest : std_logic; -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_waitrequest -> mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest:in
signal mem32_to_avalon_0_avalon_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_readdata -> mem32_to_avalon_0:avm_readdata
signal mem32_to_avalon_0_avalon_master_read : std_logic; -- mem32_to_avalon_0:avm_read -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_read
signal mem32_to_avalon_0_avalon_master_address : std_logic_vector(25 downto 0); -- mem32_to_avalon_0:avm_address -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_address
signal mem32_to_avalon_0_avalon_master_byteenable : std_logic_vector(3 downto 0); -- mem32_to_avalon_0:avm_byte_enable -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_byteenable
signal mem32_to_avalon_0_avalon_master_readdatavalid : std_logic; -- mm_interconnect_0:mem32_to_avalon_0_avalon_master_readdatavalid -> mem32_to_avalon_0:avm_readdatavalid
signal mem32_to_avalon_0_avalon_master_write : std_logic; -- mem32_to_avalon_0:avm_write -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_write
signal mem32_to_avalon_0_avalon_master_writedata : std_logic_vector(31 downto 0); -- mem32_to_avalon_0:avm_writedata -> mm_interconnect_0:mem32_to_avalon_0_avalon_master_writedata
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(28 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(28 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_altmemddr_0_s1_beginbursttransfer : std_logic; -- mm_interconnect_0:altmemddr_0_s1_beginbursttransfer -> altmemddr_0:local_burstbegin
signal mm_interconnect_0_altmemddr_0_s1_readdata : std_logic_vector(31 downto 0); -- altmemddr_0:local_rdata -> mm_interconnect_0:altmemddr_0_s1_readdata
signal altmemddr_0_s1_waitrequest : std_logic; -- altmemddr_0:local_ready -> altmemddr_0_s1_waitrequest:in
signal mm_interconnect_0_altmemddr_0_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:altmemddr_0_s1_address -> altmemddr_0:local_address
signal mm_interconnect_0_altmemddr_0_s1_read : std_logic; -- mm_interconnect_0:altmemddr_0_s1_read -> altmemddr_0:local_read_req
signal mm_interconnect_0_altmemddr_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:altmemddr_0_s1_byteenable -> altmemddr_0:local_be
signal mm_interconnect_0_altmemddr_0_s1_readdatavalid : std_logic; -- altmemddr_0:local_rdata_valid -> mm_interconnect_0:altmemddr_0_s1_readdatavalid
signal mm_interconnect_0_altmemddr_0_s1_write : std_logic; -- mm_interconnect_0:altmemddr_0_s1_write -> altmemddr_0:local_write_req
signal mm_interconnect_0_altmemddr_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altmemddr_0_s1_writedata -> altmemddr_0:local_wdata
signal mm_interconnect_0_altmemddr_0_s1_burstcount : std_logic_vector(2 downto 0); -- mm_interconnect_0:altmemddr_0_s1_burstcount -> altmemddr_0:local_size
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_0:avs_readdata -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdata
signal io_bridge_0_avalon_slave_0_waitrequest : std_logic; -- io_bridge_0:avs_ready -> io_bridge_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_address -> io_bridge_0:avs_address
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_read -> io_bridge_0:avs_read
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_0:avs_readdatavalid -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_write -> io_bridge_0:avs_write
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_writedata -> io_bridge_0:avs_writedata
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal irq_mapper_receiver0_irq : std_logic; -- io_bridge_0:avs_irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- pio_0:irq -> irq_mapper:receiver1_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [io_bridge_0:reset, mem32_to_avalon_0:reset, mm_interconnect_0:mem32_to_avalon_0_reset_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in]
signal nios2_gen2_0_debug_reset_request_reset : std_logic; -- nios2_gen2_0:debug_reset_request -> rst_controller:reset_in0
signal altmemddr_0_reset_request_n_reset : std_logic; -- altmemddr_0:reset_request_n -> altmemddr_0_reset_request_n_reset:in
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, rst_controller_001_reset_out_reset:in]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, rst_translator:reset_req_in]
signal mem32_to_avalon_0_avalon_master_inv : std_logic; -- mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest:inv -> mem32_to_avalon_0:avm_ready
signal mm_interconnect_0_altmemddr_0_s1_inv : std_logic; -- altmemddr_0_s1_waitrequest:inv -> mm_interconnect_0:altmemddr_0_s1_waitrequest
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_inv : std_logic; -- io_bridge_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [sys_reset_reset_n, pio_0:reset_n]
signal altmemddr_0_reset_request_n_reset_ports_inv : std_logic; -- altmemddr_0_reset_request_n_reset:inv -> [rst_controller:reset_in1, rst_controller_001:reset_in0]
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> nios2_gen2_0:reset_n
begin
altmemddr_0 : component nios_altmemddr_0
port map (
local_address => mm_interconnect_0_altmemddr_0_s1_address, -- s1.address
local_write_req => mm_interconnect_0_altmemddr_0_s1_write, -- .write
local_read_req => mm_interconnect_0_altmemddr_0_s1_read, -- .read
local_burstbegin => mm_interconnect_0_altmemddr_0_s1_beginbursttransfer, -- .beginbursttransfer
local_ready => altmemddr_0_s1_waitrequest, -- .waitrequest_n
local_rdata => mm_interconnect_0_altmemddr_0_s1_readdata, -- .readdata
local_rdata_valid => mm_interconnect_0_altmemddr_0_s1_readdatavalid, -- .readdatavalid
local_wdata => mm_interconnect_0_altmemddr_0_s1_writedata, -- .writedata
local_be => mm_interconnect_0_altmemddr_0_s1_byteenable, -- .byteenable
local_size => mm_interconnect_0_altmemddr_0_s1_burstcount, -- .burstcount
local_refresh_ack => mem_external_local_refresh_ack, -- external_connection.export
local_init_done => mem_external_local_init_done, -- .export
reset_phy_clk_n => mem_external_reset_phy_clk_n, -- .export
mem_odt => memory_mem_odt, -- memory.mem_odt
mem_clk => memory_mem_clk, -- .mem_clk
mem_clk_n => memory_mem_clk_n, -- .mem_clk_n
mem_cs_n => memory_mem_cs_n, -- .mem_cs_n
mem_cke => memory_mem_cke, -- .mem_cke
mem_addr => memory_mem_addr, -- .mem_addr
mem_ba => memory_mem_ba, -- .mem_ba
mem_ras_n => memory_mem_ras_n, -- .mem_ras_n
mem_cas_n => memory_mem_cas_n, -- .mem_cas_n
mem_we_n => memory_mem_we_n, -- .mem_we_n
mem_dq => memory_mem_dq, -- .mem_dq
mem_dqs => memory_mem_dqs, -- .mem_dqs
mem_dm => memory_mem_dm, -- .mem_dm
pll_ref_clk => clk50_clk, -- refclk.clk
soft_reset_n => reset_reset_n, -- soft_reset_n.reset_n
global_reset_n => reset_reset_n, -- global_reset_n.reset_n
reset_request_n => altmemddr_0_reset_request_n_reset, -- reset_request_n.reset_n
phy_clk => altmemddr_0_sysclk_clk, -- sysclk.clk
aux_full_rate_clk => altmemddr_0_auxfull_clk, -- auxfull.clk
aux_half_rate_clk => altmemddr_0_auxhalf_clk -- auxhalf.clk
);
io_bridge_0 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => altmemddr_0_sysclk_clk, -- clock.clk
io_ack => io_ack, -- io.ack
io_rdata => io_rdata, -- .rdata
io_read => io_read, -- .read
io_wdata => io_wdata, -- .wdata
io_write => io_write, -- .write
io_address => io_address, -- .address
io_irq => io_irq, -- .irq
avs_irq => irq_mapper_receiver0_irq -- irq.irq
);
mem32_to_avalon_0 : component mem32_to_avalon_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
clock => altmemddr_0_sysclk_clk, -- clock.clk
memreq_address => mem32_address, -- mem32_slave.address
memreq_read_writen => mem32_direction, -- .direction
memreq_byte_en => mem32_byte_en, -- .byte_en
memreq_data => mem32_wdata, -- .wdata
memreq_request => mem32_request, -- .request
memreq_tag => mem32_tag, -- .tag
memresp_dack_tag => mem32_dack_tag, -- .dack_tag
memresp_data => mem32_rdata, -- .rdata
memresp_rack => mem32_rack, -- .rack
memresp_rack_tag => mem32_rack_tag, -- .rack_tag
avm_read => mem32_to_avalon_0_avalon_master_read, -- avalon_master.read
avm_write => mem32_to_avalon_0_avalon_master_write, -- .write
avm_address => mem32_to_avalon_0_avalon_master_address, -- .address
avm_writedata => mem32_to_avalon_0_avalon_master_writedata, -- .writedata
avm_byte_enable => mem32_to_avalon_0_avalon_master_byteenable, -- .byteenable
avm_ready => mem32_to_avalon_0_avalon_master_inv, -- .waitrequest_n
avm_readdata => mem32_to_avalon_0_avalon_master_readdata, -- .readdata
avm_readdatavalid => mem32_to_avalon_0_avalon_master_readdatavalid -- .readdatavalid
);
nios2_gen2_0 : component nios_nios2_gen2_0
port map (
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => nios2_gen2_0_debug_reset_request_reset, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
pio_0 : component nios_pio_0
port map (
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
in_port => pio_in_port, -- external_connection.export
out_port => pio_out_port, -- .export
irq => irq_mapper_receiver1_irq -- irq.irq
);
mm_interconnect_0 : component nios_mm_interconnect_0
port map (
altmemddr_0_sysclk_clk => altmemddr_0_sysclk_clk, -- altmemddr_0_sysclk.clk
mem32_to_avalon_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- mem32_to_avalon_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
mem32_to_avalon_0_avalon_master_address => mem32_to_avalon_0_avalon_master_address, -- mem32_to_avalon_0_avalon_master.address
mem32_to_avalon_0_avalon_master_waitrequest => mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest, -- .waitrequest
mem32_to_avalon_0_avalon_master_byteenable => mem32_to_avalon_0_avalon_master_byteenable, -- .byteenable
mem32_to_avalon_0_avalon_master_read => mem32_to_avalon_0_avalon_master_read, -- .read
mem32_to_avalon_0_avalon_master_readdata => mem32_to_avalon_0_avalon_master_readdata, -- .readdata
mem32_to_avalon_0_avalon_master_readdatavalid => mem32_to_avalon_0_avalon_master_readdatavalid, -- .readdatavalid
mem32_to_avalon_0_avalon_master_write => mem32_to_avalon_0_avalon_master_write, -- .write
mem32_to_avalon_0_avalon_master_writedata => mem32_to_avalon_0_avalon_master_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
altmemddr_0_s1_address => mm_interconnect_0_altmemddr_0_s1_address, -- altmemddr_0_s1.address
altmemddr_0_s1_write => mm_interconnect_0_altmemddr_0_s1_write, -- .write
altmemddr_0_s1_read => mm_interconnect_0_altmemddr_0_s1_read, -- .read
altmemddr_0_s1_readdata => mm_interconnect_0_altmemddr_0_s1_readdata, -- .readdata
altmemddr_0_s1_writedata => mm_interconnect_0_altmemddr_0_s1_writedata, -- .writedata
altmemddr_0_s1_beginbursttransfer => mm_interconnect_0_altmemddr_0_s1_beginbursttransfer, -- .beginbursttransfer
altmemddr_0_s1_burstcount => mm_interconnect_0_altmemddr_0_s1_burstcount, -- .burstcount
altmemddr_0_s1_byteenable => mm_interconnect_0_altmemddr_0_s1_byteenable, -- .byteenable
altmemddr_0_s1_readdatavalid => mm_interconnect_0_altmemddr_0_s1_readdatavalid, -- .readdatavalid
altmemddr_0_s1_waitrequest => mm_interconnect_0_altmemddr_0_s1_inv, -- .waitrequest
io_bridge_0_avalon_slave_0_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- io_bridge_0_avalon_slave_0.address
io_bridge_0_avalon_slave_0_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
io_bridge_0_avalon_slave_0_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- .read
io_bridge_0_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
io_bridge_0_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
io_bridge_0_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_0_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_0_avalon_slave_0_inv, -- .waitrequest
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect -- .chipselect
);
irq_mapper : component nios_irq_mapper
port map (
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component nios_rst_controller
generic map (
NUM_RESET_INPUTS => 2,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => nios2_gen2_0_debug_reset_request_reset, -- reset_in0.reset
reset_in1 => altmemddr_0_reset_request_n_reset_ports_inv, -- reset_in1.reset
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component nios_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => altmemddr_0_reset_request_n_reset_ports_inv, -- reset_in0.reset
clk => altmemddr_0_sysclk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
mem32_to_avalon_0_avalon_master_inv <= not mm_interconnect_0_mem32_to_avalon_0_avalon_master_waitrequest;
mm_interconnect_0_altmemddr_0_s1_inv <= not altmemddr_0_s1_waitrequest;
mm_interconnect_0_io_bridge_0_avalon_slave_0_inv <= not io_bridge_0_avalon_slave_0_waitrequest;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
altmemddr_0_reset_request_n_reset_ports_inv <= not altmemddr_0_reset_request_n_reset;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
sys_clock_clk <= altmemddr_0_sysclk_clk;
sys_reset_reset_n <= rst_controller_reset_out_reset_ports_inv;
end architecture rtl; -- of nios
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll2 is
port
(-- Clock in ports
CLKIN_IN : in std_logic;
-- Clock out ports
CLK0_OUT : out std_logic;
CLK1_OUT : out std_logic;
CLK2_OUT : out std_logic;
CLK3_OUT : out std_logic
);
end pll2;
architecture xilinx of pll2 is
signal GND_BIT : std_logic;
signal CLKFBOUT : std_logic;
signal CLKFB : std_logic;
signal CLKFBIN : std_logic;
signal CLKIN : std_logic;
signal CLK0 : std_logic;
signal CLK0_BUF : std_logic;
signal CLK1 : std_logic;
signal CLK1_BUF : std_logic;
signal CLK2 : std_logic;
signal CLK2_BUF : std_logic;
signal CLK3 : std_logic;
signal CLK3_BUF : std_logic;
begin
GND_BIT <= '0';
-- Clock feedback output buffer
CLKFB_BUFG_INST : BUFG
port map (I => CLKFBOUT, O => CLKFB);
-- Clock feedback io2 buffer
CLKFB_BUFIO2FB_INST : BUFIO2FB
port map (I => CLKFB, O => CLKFBIN);
-- CLK0 output buffer
CLK0_BUFG_INST : BUFG
port map (I => CLK0, O => CLK0_BUF);
CLK0_OUT <= CLK0_BUF;
-- CLK1 output buffer
CLK1_BUFG_INST : BUFG
port map (I => CLK1, O => CLK1_BUF);
CLK1_OUT <= CLK1_BUF;
-- CLK2 output buffer
CLK2_BUFG_INST : BUFG
port map (I => CLK2, O => CLK2_BUF);
CLK2_OUT <= CLK2_BUF;
-- CLK3 output buffer
CLK3_BUFG_INST : BUFG
port map (I => CLK3, O => CLK3_BUF);
CLK3_OUT <= CLK3_BUF;
INST_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS", -- not sure this is correct
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 15, -- 32 x 15 = 480MHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 30, -- 480 / 30 = 16MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 20, -- 480 / 20 = 24 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 15, -- 480 / 15 = 32 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 12, -- 480 / 12 = 40 MHZ
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map (
-- Input clock control
CLKIN => CLKIN_IN,
CLKFBIN => CLKFBIN,
-- Output clocks
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLK0,
CLKOUT1 => CLK1,
CLKOUT2 => CLK2,
CLKOUT3 => CLK3,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => GND_BIT
);
end xilinx;
|
-- Codeslot
--
-- gemaakt door
--
-- __ ___ _
-- / |/ /___ ___ _______(_)_______
-- / /|_/ / __ `/ / / / ___/ / ___/ _ \
-- / / / / /_/ / /_/ / / / / /__/ __/
-- /_/ /_/\__,_/\__,_/_/ /_/\___/\___/
-- ____ __ ____
-- / __ \____ __ _____ ______ _____ / /___/ / /_
-- / / / / __ `/ | / / _ \/ ___/ | / / _ \/ / __ / __/
-- / /_/ / /_/ /| |/ / __/ / | |/ / __/ / /_/ / /_
-- /_____/\__,_/ |___/\___/_/ |___/\___/_/\__,_/\__/
--
-- Maurice Daverveldt
-- Ev3a
-- 1531491
--
-- gebruikte wachtwoord binair:
-- 0001010010010001
-- dit bestand bevat de beschrijvingen voor alle onderdelen
-- dit onderdeel zorgt voor de werking van het codeslot
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity opdr6_FSM is
port( druk : in std_logic;
DIP : in std_logic_vector(3 downto 0);
uit : out std_logic_vector(3 downto 0);
LED : out std_logic);
end entity;
architecture RTL of opdr6_FSM is
type stand is(st0, st1, st2, st3, st4, st5);
signal VT, HT : stand;
signal ok : unsigned(15 downto 0) := (others => '0') ;
begin
combi : process(HT)
begin
case HT is
-- selecteer volgende standen
when st0 => VT <= st1;
when st1 => VT <= st2;
when st2 => VT <= st3;
when st3 => VT <= st4;
when st4 => VT <= st5;
when st5 => VT <= st0;
end case;
end process;
seq : process(druk)
begin
if rising_edge(druk) then
-- selecteer volgende stand
HT <= VT;
-- zet bij de juiste stand de juiste waarde in ok register
case HT is
when st0 => ok <= (others => '0');
when st1 => ok(15 downto 12) <= unsigned(DIP);
when st2 => ok(11 downto 8) <= unsigned(DIP);
when st3 => ok(7 downto 4) <= unsigned(DIP);
when st4 => ok(3 downto 0) <= unsigned(DIP);
when st5 => ok <= ok;
end case;
end if;
end process;
output : process(HT, ok)
begin
-- zet de uitgangen bij de juiste stand
case HT is
when st0 =>
uit <= "0000";
led <= '0';
when st1 =>
uit <= "0001";
led <= '0';
when st2 =>
uit <= "0010";
led <= '0';
when st3 =>
uit <= "0011";
led <= '0';
when st4 =>
uit <= "0100";
led <= '0';
-- check of ok register overeenkomt met studenten nummer
when st5 =>
if (ok = "0001010010010001") then
uit <= "1001";
led <= '1';
else
uit <= "1000";
led <= '0';
end if;
end case;
end process;
end RTL;
-- dit onderdeel stuurt het display aan
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity opdr6_Disp is
port( ingang : in std_logic_vector(31 downto 0);
AN : out std_logic_vector(3 downto 0);
SEG : out std_logic_vector(7 downto 0);
clk : in std_logic);
end opdr6_Disp;
architecture RTL of opdr6_Disp is
signal clk_3k : std_logic;
signal selectie : unsigned(1 downto 0) := "00";
constant clk_deler : integer := 2;
begin
-- dit onderdeel is de klokdeler
klok_deler : process(clk)
variable teller : integer range 0 to clk_deler := 0;
begin
if rising_edge(clk) then
-- verhoog teller
teller := teller + 1;
-- als teller te groot is maak hem dan 0
if teller = clk_deler then teller := 0;
end if;
-- als teller voor de helft is maak dan clk_3k laag
-- maak teller anders hoog
if teller < clk_deler/2 then
clk_3k <= '0';
else
clk_3k <= '1';
end if;
end if;
end process;
-- dit onderdeel selecteerd het display
selector : process(clk_3k)
begin
if rising_edge(clk_3k) then
-- verhoog selectie met 1
-- omdat selectie 2 bit getal is kan hij niet groter worden dan 4
selectie <= selectie + 1;
end if;
end process;
-- dit onderdeel combineert het juiste display met de juiste segmenten
decoder : process(selectie, ingang)
begin
case selectie is
when "00" =>
AN <= "0111";
seg <= ingang(31 downto 24);
when "01" =>
AN <= "1011";
seg <= ingang(23 downto 16);
when "10" =>
AN <= "1101";
seg <= ingang(15 downto 8);
when "11" =>
AN <= "1110";
seg <= ingang(7 downto 0);
when others =>
AN <= "1111";
seg <= (others => '0');
end case;
end process;
end RTL;
-- dit onderdeel zorgt voor een antidender schakeling voor de drukknop
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity opdr6_dender is
port( druk : in std_logic;
clk : in std_logic;
uit : out std_logic);
end opdr6_dender;
architecture RTL of opdr6_dender is
signal clk_200 : std_logic;
signal shift : unsigned(3 downto 0) := "0000";
constant clk_deler : integer := 2;
begin
-- dit onderdeel verlaagt de 50mhz klok
-- werking is hetzelfde als vorige frequentie deler
klok_deler : process(clk)
variable teller : integer range 0 to clk_deler := 0;
begin
if rising_edge(clk) then
teller := teller + 1;
if teller = clk_deler then teller := 0;
end if;
if teller < clk_deler/2 then
clk_200 <= '0';
else
clk_200 <= '1';
end if;
end if;
end process;
-- dit onderdeel vult een 4 bit schuifregister
process(clk_200)
begin
if rising_edge(clk_200) then
shift <= druk & shift(3 downto 1);
end if;
end process;
-- zorg ervoor dat als het schuifregister gevuld is met enen de uitgang hoog wordt
uit <= '1' when shift = "1111" else
'0';
end RTL;
-- dit onderdeel converteerd de waarde van de DIP switch en van de FSM
-- naar waardes die geschikt zijn voor 7 segment display
library ieee;
use ieee.std_logic_1164.all;
entity opdr6_conv is
port( FSM : in std_logic_vector(3 downto 0);
DIP : in std_logic_vector(3 downto 0);
uit : out std_logic_vector(31 downto 0));
end opdr6_conv;
architecture RTL of opdr6_conv is
signal seg1 : std_logic_vector(7 downto 0);
signal seg2 : std_logic_vector(7 downto 0);
signal seg3 : std_logic_vector(7 downto 0);
signal seg4 : std_logic_vector(7 downto 0);
begin
-- dit onderdeel zet de waardes van het FSM om in waardes voor het display
-- segment 1
process(FSM)
begin
case FSM is
when "0000" => seg1 <= "01001001";
when "0001" => seg1 <= "10011110";
when "0010" => seg1 <= "00100100";
when "0011" => seg1 <= "00001100";
when "0100" => seg1 <= "00011000";
when "1000" => seg1 <= "00110001";
when "1001" => seg1 <= "00001001";
when others => seg1 <= (others => '0');
end case;
end process;
-- segment 2 moet altijd uit staan
seg2 <= (others => '1');
-- segment 3 moet altijd uit staan
seg3 <= (others => '1');
-- dit onderdeel zorgt ervoor dat de waardes van de DIP switch overeenkomen
-- met getallen op 7 segment displays
-- segment 4
process(DIP)
begin
case DIP is
when "0000" => seg4 <= "00000010";
when "0001" => seg4 <= "10011110";
when "0010" => seg4 <= "00100100";
when "0011" => seg4 <= "00001100";
when "0100" => seg4 <= "00011000";
when "0101" => seg4 <= "01001000";
when "0110" => seg4 <= "01000000";
when "0111" => seg4 <= "00011110";
when "1000" => seg4 <= "00000000";
when "1001" => seg4 <= "00001000";
when others => seg4 <= "11111101";
end case;
end process;
-- zet alles op de uitgang
uit <= seg1 & seg2 & seg3 & seg4;
end RTL;
-- maak van alle onderdelen een package
library ieee;
use ieee.std_logic_1164.all;
package opdr6 is
component opdr6_FSM is
port( druk : in std_logic;
DIP : in std_logic_vector(3 downto 0);
uit : out std_logic_vector(3 downto 0);
LED : out std_logic);
end component;
component opdr6_Disp is
port( ingang : in std_logic_vector(31 downto 0);
AN : out std_logic_vector(3 downto 0);
SEG : out std_logic_vector(7 downto 0);
clk : in std_logic);
end component;
component opdr6_dender is
port( druk : in std_logic;
clk : in std_logic;
uit : out std_logic);
end component;
component opdr6_conv is
port( FSM : in std_logic_vector(3 downto 0);
DIP : in std_logic_vector(3 downto 0);
uit : out std_logic_vector(31 downto 0));
end component;
end package;
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
COMPONENT fifo is --Some Comemnt
-- Some COmment
end component fifo;
Component fifo is--Other comment
-- Some Comment
end component fifo;
begin
end architecture RTL;
|
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: L2P serializer (l2p_ser_s6.vhd)
--
-- authors: Simon Deprez (simon.deprez@cern.ch)
-- Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: Generates the DDR L2P bus from SDR that is synchronous to the
-- core clock. Spartan6 FPGAs version.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Always active high reset for FFs.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity l2p_ser is
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- L2P SDR inputs
l2p_valid_i : in std_logic;
l2p_dframe_i : in std_logic;
l2p_data_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------
-- L2P DDR outputs
l2p_clk_p_o : out std_logic;
l2p_clk_n_o : out std_logic;
l2p_valid_o : out std_logic;
l2p_dframe_o : out std_logic;
l2p_data_o : out std_logic_vector(15 downto 0)
);
end l2p_ser;
architecture rtl of l2p_ser is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_n_to_1_s2_se
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_se;
component serdes_n_to_1_s2_diff
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 1) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0); -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_diff;
-----------------------------------------------------------------------------
-- Comnstants declaration
-----------------------------------------------------------------------------
constant S : integer := 2; -- Set the serdes factor to 2
constant D : integer := 16; -- Set the number of outputs
constant c_TX_CLK : std_logic_vector(1 downto 0) := "01";
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal l2p_dframe_t : std_logic_vector(1 downto 0);
signal l2p_valid_t : std_logic_vector(1 downto 0);
signal l2p_dframe_v : std_logic_vector(0 downto 0);
signal l2p_valid_v : std_logic_vector(0 downto 0);
signal l2p_clk_p_v : std_logic_vector(0 downto 0);
signal l2p_clk_n_v : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset for DDR FF
------------------------------------------------------------------------------
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- Instantiate serialiser to generate forwarded clock
------------------------------------------------------------------------------
cmp_clk_out : serdes_n_to_1_s2_diff
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => c_TX_CLK, -- Transmit a constant to make the clock
dataout_p => l2p_clk_p_v,
dataout_n => l2p_clk_n_v);
-- Type conversion, std_logic_vector to std_logic
l2p_clk_p_o <= l2p_clk_p_v(0);
l2p_clk_n_o <= l2p_clk_n_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for output data lines
------------------------------------------------------------------------------
cmp_data_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => D)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_data_i,
dataout => l2p_data_o);
------------------------------------------------------------------------------
-- Instantiate serialisers for dframe
------------------------------------------------------------------------------
cmp_dframe_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_dframe_t,
dataout => l2p_dframe_v);
-- Serialize two times the same value
l2p_dframe_t <= l2p_dframe_i & l2p_dframe_i;
-- Type conversion, std_logic_vector to std_logic
l2p_dframe_o <= l2p_dframe_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for valid
------------------------------------------------------------------------------
cmp_valid_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_valid_t,
dataout => l2p_valid_v);
-- Serialize two times the same value
l2p_valid_t <= l2p_valid_i & l2p_valid_i;
-- Type conversion, std_logic_vector to std_logic
l2p_valid_o <= l2p_valid_v(0);
end rtl;
|
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: L2P serializer (l2p_ser_s6.vhd)
--
-- authors: Simon Deprez (simon.deprez@cern.ch)
-- Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: Generates the DDR L2P bus from SDR that is synchronous to the
-- core clock. Spartan6 FPGAs version.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin) Always active high reset for FFs.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity l2p_ser is
port
(
---------------------------------------------------------
-- Reset and clock
rst_n_i : in std_logic;
sys_clk_i : in std_logic;
io_clk_i : in std_logic;
serdes_strobe_i : in std_logic;
---------------------------------------------------------
-- L2P SDR inputs
l2p_valid_i : in std_logic;
l2p_dframe_i : in std_logic;
l2p_data_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------
-- L2P DDR outputs
l2p_clk_p_o : out std_logic;
l2p_clk_n_o : out std_logic;
l2p_valid_o : out std_logic;
l2p_dframe_o : out std_logic;
l2p_data_o : out std_logic_vector(15 downto 0)
);
end l2p_ser;
architecture rtl of l2p_ser is
-----------------------------------------------------------------------------
-- Components declaration
-----------------------------------------------------------------------------
component serdes_n_to_1_s2_se
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_se;
component serdes_n_to_1_s2_diff
generic (
S : integer := 2; -- Parameter to set the serdes factor 1..8
D : integer := 1) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic; -- IO Clock network
txserdesstrobe : in std_logic; -- Parallel data capture strobe
reset : in std_logic; -- Reset
gclk : in std_logic; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0); -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0); -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component serdes_n_to_1_s2_diff;
-----------------------------------------------------------------------------
-- Comnstants declaration
-----------------------------------------------------------------------------
constant S : integer := 2; -- Set the serdes factor to 2
constant D : integer := 16; -- Set the number of outputs
constant c_TX_CLK : std_logic_vector(1 downto 0) := "01";
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Serdes reset
signal rst : std_logic;
-- SDR signals
signal l2p_dframe_t : std_logic_vector(1 downto 0);
signal l2p_valid_t : std_logic_vector(1 downto 0);
signal l2p_dframe_v : std_logic_vector(0 downto 0);
signal l2p_valid_v : std_logic_vector(0 downto 0);
signal l2p_clk_p_v : std_logic_vector(0 downto 0);
signal l2p_clk_n_v : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Active high reset for DDR FF
------------------------------------------------------------------------------
gen_fifo_rst_n : if c_RST_ACTIVE = '0' generate
rst <= not(rst_n_i);
end generate;
gen_fifo_rst : if c_RST_ACTIVE = '1' generate
rst <= rst_n_i;
end generate;
------------------------------------------------------------------------------
-- Instantiate serialiser to generate forwarded clock
------------------------------------------------------------------------------
cmp_clk_out : serdes_n_to_1_s2_diff
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => c_TX_CLK, -- Transmit a constant to make the clock
dataout_p => l2p_clk_p_v,
dataout_n => l2p_clk_n_v);
-- Type conversion, std_logic_vector to std_logic
l2p_clk_p_o <= l2p_clk_p_v(0);
l2p_clk_n_o <= l2p_clk_n_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for output data lines
------------------------------------------------------------------------------
cmp_data_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => D)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_data_i,
dataout => l2p_data_o);
------------------------------------------------------------------------------
-- Instantiate serialisers for dframe
------------------------------------------------------------------------------
cmp_dframe_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_dframe_t,
dataout => l2p_dframe_v);
-- Serialize two times the same value
l2p_dframe_t <= l2p_dframe_i & l2p_dframe_i;
-- Type conversion, std_logic_vector to std_logic
l2p_dframe_o <= l2p_dframe_v(0);
------------------------------------------------------------------------------
-- Instantiate serialisers for valid
------------------------------------------------------------------------------
cmp_valid_out : serdes_n_to_1_s2_se
generic map(
S => S,
D => 1)
port map (
txioclk => io_clk_i,
txserdesstrobe => serdes_strobe_i,
gclk => sys_clk_i,
reset => rst,
datain => l2p_valid_t,
dataout => l2p_valid_v);
-- Serialize two times the same value
l2p_valid_t <= l2p_valid_i & l2p_valid_i;
-- Type conversion, std_logic_vector to std_logic
l2p_valid_o <= l2p_valid_v(0);
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- jan@gaisler.com
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- jan@gaisler.com
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- jan@gaisler.com
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11216)
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`protect end_protected
|
-- Simple DBE simple design
-- Created by Lucas Russo <lucas.russo@lnls.br>
-- Date: 11/10/2012
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_simple_top is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- FMC150 pins
-----------------------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_simple_top;
architecture rtl of dbe_bpm_simple_top is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 7; -- LED, Button, Dual-port memory, UART, DMA control port, FMC150
-- Number of masters
constant c_masters : natural := 4; -- LM32 master. Data + Instruction, DMA read+write master
--constant c_dpram_size : natural := 16384; -- in 32-bit words (64KB)
constant c_dpram_size : natural := 22528; -- in 32-bit words (64KB)
-- Number of source/sink Wishbone stream components
constant c_sinks : natural := 1;
constant c_sources : natural := c_sinks;
-- GPIO num pins
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 32;
-- Number of reset clock cycles (FF)
constant c_button_rst_width : natural := 255;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 64KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(c_xwb_dma_sdb, x"20000400"), -- DMA control port
3 => f_sdb_embed_device(c_xwb_fmc150_sdb, x"20000500"), -- FMC control port
4 => f_sdb_embed_device(c_xwb_uart_sdb, x"20000600"), -- UART control port
5 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000700"), -- GPIO LED
6 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000800") -- GPIO Button
--7 => f_sdb_embed_device(c_xwb_irqmngr_sdb, x"20000900") -- IRQ_MNGR
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"20000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- Wishbone Stream source/sinks arrays
signal wbs_src_i : t_wbs_source_in_array(c_sources-1 downto 0);
signal wbs_src_o : t_wbs_source_out_array(c_sources-1 downto 0);
-- Check the use of this kind of alias
alias wbs_sink_i is wbs_src_o;
alias wbs_sink_o is wbs_src_i;
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
signal clk_adc_rstn : std_logic;
signal rst_button_sys_pp : std_logic;
signal rst_button_adc_pp : std_logic;
signal rst_button_sys : std_logic;
signal rst_button_adc : std_logic;
signal rst_button_sys_n : std_logic;
signal rst_button_adc_n : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(1 downto 0);
signal reset_rstn : std_logic_vector(1 downto 0);
-- 200 Mhz clocck for iodelatctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal s_leds : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- IRQ manager signals
--signal gpio_slave_irqmngr_o : t_wishbone_slave_out;
--signal gpio_slave_irqmngr_i : t_wishbone_slave_in;
-- LEDS, button and irq manager signals
--signal r_leds : std_logic_vector(7 downto 0);
--signal r_reset : std_logic;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
constant s_counter_full : integer := 100000000;
-- FMC150 signals
signal clk_adc : std_logic;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
component chipscope_icon_2_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking and generate necessary clocks
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed.
-- Is this a safe approach to ADC reset domain?
cmp_reset : gc_reset
generic map(
g_clocks => 2 -- CLK_SYS + CLK_ADC
)
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
-- Generate button reset synchronous to each clock domain
-- Detect button positive edge of clk_sys
cmp_button_sys_ffs : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_sys_pp
);
-- Detect button positive edge of clk_adc
cmp_button_adc_ffs : gc_sync_ffs
port map (
clk_i => clk_adc,
rst_n_i => '1',
data_i => sys_rst_button_i,
ppulse_o => rst_button_adc_pp
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_sys_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_sys,
rst_n_i => '1',
pulse_i => rst_button_sys_pp,
extended_o => rst_button_sys
);
-- Generate the reset signal based on positive edge
-- of synched sys_rst_button_i
cmp_button_adc_rst : gc_extend_pulse
generic map (
g_width => c_button_rst_width
)
port map(
clk_i => clk_adc,
rst_n_i => '1',
pulse_i => rst_button_adc_pp,
extended_o => rst_button_adc
);
rst_button_sys_n <= not rst_button_sys;
rst_button_adc_n <= not rst_button_adc;
reset_clks(0) <= clk_sys;
reset_clks(1) <= clk_adc;
clk_sys_rstn <= reset_rstn(0) and rst_button_sys_n;
clk_adc_rstn <= reset_rstn(1) and rst_button_adc_n;
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupts 31 downto 1 disabled for now.
-- Interrupt '0' is DMA completion.
lm32_interrupt(31 downto 1) <= (others => '0');
-- A DMA controller is master 2+3, slave 2, and interrupt 0
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => lm32_interrupt(0)
);
-- Slave 0+1 is the RAM. Load a input file containing a simple led blink program!
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../../embedded-sw/dbe.ram",--"../../top/ml_605/dbe_bpm_simple/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
--slave2_i => cc_dummy_slave_in, -- CYC always low
--slave2_o => open
);
-- Slave 3 is the FMC150 interface
cmp_xwb_fmc150 : xwb_fmc150
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => BYTE
--g_packet_size => 32,
--g_sim => 0
)
port map(
rst_n_i => clk_sys_rstn,
clk_sys_i => clk_sys,
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(3),
wb_slv_o => cbar_master_i(3),
-----------------------------
-- Simulation Only ports!
-----------------------------
sim_adc_clk_i => '0',
sim_adc_clk2x_i => '0',
sim_adc_cha_data_i => f_zeros(14),
sim_adc_chb_data_i => f_zeros(14),
sim_adc_data_valid => '0',
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => adc_clk_ab_p_i,
adc_clk_ab_n_i => adc_clk_ab_n_i,
adc_cha_p_i => adc_cha_p_i,
adc_cha_n_i => adc_cha_n_i,
adc_chb_p_i => adc_chb_p_i,
adc_chb_n_i => adc_chb_n_i,
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o => dac_dclk_p_o,
dac_dclk_n_o => dac_dclk_n_o,
dac_data_p_o => dac_data_p_o,
dac_data_n_o => dac_data_n_o,
dac_frame_p_o => dac_frame_p_o,
dac_frame_n_o => dac_frame_n_o,
txenable_o => txenable_o,
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o => spi_sclk_o, -- Shared SPI clock line
spi_sdata_o => spi_sdata_o,-- Shared SPI data line
-- ADC specific signals
adc_n_en_o => adc_n_en_o, -- SPI chip select
adc_sdo_i => adc_sdo_i, -- SPI data out
adc_reset_o => adc_reset_o,-- SPI reset
-- CDCE specific signals
cdce_n_en_o => cdce_n_en_o, -- SPI chip select
cdce_sdo_i => cdce_sdo_i, -- SPI data out
cdce_n_reset_o => cdce_n_reset_o,
cdce_n_pd_o => cdce_n_pd_o,
cdce_ref_en_o => cdce_ref_en_o,
cdce_pll_status_i => cdce_pll_status_i,
-- DAC specific signals
dac_n_en_o => dac_n_en_o, -- SPI chip select
dac_sdo_i => dac_sdo_i, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => mon_n_en_o, -- SPI chip select
mon_sdo_i => mon_sdo_i, -- SPI data out
mon_n_reset_o => mon_n_reset_o,
mon_n_int_i => mon_n_int_i,
--FMC Present status
prsnt_m2c_l_i => prsnt_m2c_l_i,
-- ADC output signals
-- ADC data is interfaced through the wishbone stream interface (wbs_src_o)
adc_dout_o => open,
clk_adc_o => clk_adc,
-- Wishbone Streaming Interface Source
wbs_source_i => wbs_src_i(0),
wbs_source_o => wbs_src_o(0)
);
-- Slave 4 is the UART
cmp_uart : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(4),
slave_o => cbar_master_i(4),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
-- Slave 5 is the example LED driver
cmp_leds : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_leds_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(5),
slave_o => cbar_master_i(5),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => s_leds,
--gpio_out_o => open,
gpio_in_i => s_leds,
gpio_oen_o => open
);
leds_o <= s_leds;
--p_test_leds : process (clk_adc)
--begin
-- if rising_edge(clk_adc) then
-- if clk_adc_rstn = '0' then
-- s_counter <= (others => '0');
-- s_leds <= x"55";
-- else
-- if (s_counter = s_counter_full-1) then
-- s_counter <= (others => '0');
-- s_leds <= s_leds(c_leds_num_pins-2 downto 0) & s_leds(c_leds_num_pins-1);
-- else
-- s_counter <= s_counter + 1;
-- end if;
-- end if;
-- end if;
--end process;
-- Slave 1 is the example LED driver
--gpio_slave_led_i <= cbar_master_o(1);
--cbar_master_i(1) <= gpio_slave_led_o;
--leds_o <= not r_leds;
-- There is a tool called 'wbgen2' which can autogenerate a Wishbone
-- interface and C header file, but this is a simple example.
--gpio : process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- It is vitally important that for each occurance of
-- (cyc and stb and not stall) there is (ack or rty or err)
-- sometime later on the bus.
--
-- This is an easy solution for a device that never stalls:
-- gpio_slave_led_o.ack <= gpio_slave_led_i.cyc and gpio_slave_led_i.stb;
-- Detect a write to the register byte
-- if gpio_slave_led_i.cyc = '1' and gpio_slave_led_i.stb = '1' and
-- gpio_slave_led_i.we = '1' and gpio_slave_led_i.sel(0) = '1' then
-- Register 0x0 = LEDs, 0x4 = CPU reset
-- if gpio_slave_led_i.adr(2) = '0' then
-- r_leds <= gpio_slave_led_i.dat(7 downto 0);
-- else
-- r_reset <= gpio_slave_led_i.dat(0);
-- end if;
-- end if;
-- Read to the register byte
-- if gpio_slave_led_i.adr(2) = '0' then
-- gpio_slave_led_o.dat(31 downto 8) <= (others => '0');
-- gpio_slave_led_o.dat(7 downto 0) <= r_leds;
-- else
-- gpio_slave_led_o.dat(31 downto 2) <= (others => '0');
-- gpio_slave_led_o.dat(0) <= r_reset;
-- end if;
--end if;
--end process;
--gpio_slave_led_o.int <= '0';
--gpio_slave_led_o.err <= '0';
--gpio_slave_led_o.rty <= '0';
--gpio_slave_led_o.stall <= '0'; -- This simple example is always ready
-- Slave 6 is the example Button driver
cmp_buttons : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_buttons_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(6),
slave_o => cbar_master_i(6),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => open,
gpio_in_i => buttons_i,
gpio_oen_o => open
);
-- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_2_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1
);
cmp_chipscope_ila_0 : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys,
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- FMC150 master output (slave input) control data
TRIG_ILA0_0 <= cbar_master_o(3).dat;
-- FMC150 master input (slave output) control data
TRIG_ILA0_1 <= cbar_master_i(3).dat;
-- FMC150 master control output (slave input) control signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA0_2(16 downto 0) <= cbar_master_o(3).cyc &
cbar_master_o(3).stb &
cbar_master_o(3).adr(9 downto 0) &
cbar_master_o(3).sel &
cbar_master_o(3).we;
--TRIG_ILA0_2(31 downto 11) <= (others => '0');
TRIG_ILA0_2(31 downto 17) <= (others => '0');
-- FMC150 master control input (slave output) control signals
TRIG_ILA0_3(4 downto 0) <= cbar_master_i(3).ack &
cbar_master_i(3).err &
cbar_master_i(3).rty &
cbar_master_i(3).stall &
cbar_master_i(3).int;
TRIG_ILA0_3(31 downto 5) <= (others => '0');
cmp_chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL1,
CLK => clk_adc,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- FMC150 source output (sink input) stream data
TRIG_ILA1_0 <= wbs_src_o(0).dat;
-- FMC150 source input (sink output) stream data
--TRIG_ILA1_1 <= wbs_src_i(0).dat;
-- FMC150 source control output (sink input) stream signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA1_1(10 downto 0) <= wbs_src_o(0).cyc &
wbs_src_o(0).stb &
wbs_src_o(0).adr(3 downto 0) &
wbs_src_o(0).sel &
wbs_src_o(0).we;
TRIG_ILA1_1(31 downto 11) <= (others => '0');
-- FMC150 master control input (slave output) stream signals
TRIG_ILA1_2(3 downto 0) <= wbs_src_i(0).ack &
wbs_src_i(0).err &
wbs_src_i(0).rty &
wbs_src_i(0).stall;
TRIG_ILA1_2(31 downto 4) <= (others => '0');
TRIG_ILA1_3(31 downto 0) <= (others => '0');
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc958.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00958ent IS
END c06s03b00x00p02n01i00958ent;
ARCHITECTURE c06s03b00x00p02n01i00958arch OF c06s03b00x00p02n01i00958ent IS
BEGIN
TESTING: PROCESS
type ONE is range 1 to 1;
type R0 is record X: ONE; RE: BOOLEAN; end record;
type R1 is record X: ONE; RE: R0; end record;
type R2 is record X: ONE; RE: R1; end record;
type R3 is record X: ONE; RE: R2; end record;
type R4 is record X: ONE; RE: R3; end record;
type R5 is record X: ONE; RE: R4; end record;
type R6 is record X: ONE; RE: R5; end record;
type R7 is record X: ONE; RE: R6; end record;
type R8 is record X: ONE; RE: R7; end record;
type R9 is record X: ONE; RE: R8; end record;
variable V1: R9;
BEGIN
assert NOT(V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***PASSED TEST: c06s03b00x00p02n01i00958"
severity NOTE;
assert (V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***FAILED TEST: c06s03b00x00p02n01i00958 - The selected name consists of a prefix, a dot (.), and a suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00958arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc958.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00958ent IS
END c06s03b00x00p02n01i00958ent;
ARCHITECTURE c06s03b00x00p02n01i00958arch OF c06s03b00x00p02n01i00958ent IS
BEGIN
TESTING: PROCESS
type ONE is range 1 to 1;
type R0 is record X: ONE; RE: BOOLEAN; end record;
type R1 is record X: ONE; RE: R0; end record;
type R2 is record X: ONE; RE: R1; end record;
type R3 is record X: ONE; RE: R2; end record;
type R4 is record X: ONE; RE: R3; end record;
type R5 is record X: ONE; RE: R4; end record;
type R6 is record X: ONE; RE: R5; end record;
type R7 is record X: ONE; RE: R6; end record;
type R8 is record X: ONE; RE: R7; end record;
type R9 is record X: ONE; RE: R8; end record;
variable V1: R9;
BEGIN
assert NOT(V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***PASSED TEST: c06s03b00x00p02n01i00958"
severity NOTE;
assert (V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***FAILED TEST: c06s03b00x00p02n01i00958 - The selected name consists of a prefix, a dot (.), and a suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00958arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc958.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p02n01i00958ent IS
END c06s03b00x00p02n01i00958ent;
ARCHITECTURE c06s03b00x00p02n01i00958arch OF c06s03b00x00p02n01i00958ent IS
BEGIN
TESTING: PROCESS
type ONE is range 1 to 1;
type R0 is record X: ONE; RE: BOOLEAN; end record;
type R1 is record X: ONE; RE: R0; end record;
type R2 is record X: ONE; RE: R1; end record;
type R3 is record X: ONE; RE: R2; end record;
type R4 is record X: ONE; RE: R3; end record;
type R5 is record X: ONE; RE: R4; end record;
type R6 is record X: ONE; RE: R5; end record;
type R7 is record X: ONE; RE: R6; end record;
type R8 is record X: ONE; RE: R7; end record;
type R9 is record X: ONE; RE: R8; end record;
variable V1: R9;
BEGIN
assert NOT(V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***PASSED TEST: c06s03b00x00p02n01i00958"
severity NOTE;
assert (V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
report "***FAILED TEST: c06s03b00x00p02n01i00958 - The selected name consists of a prefix, a dot (.), and a suffix."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p02n01i00958arch;
|
--##############################################################################
--
-- lowpass
-- generic all-pole lowpass filter
--
-- This circuit simulates an analog ladder filter by replacing the integral
-- relations of the LC elements by digital accumulators.
--
--------------------------------------------------------------------------------
--
-- Versions / Authors
-- 1.1 Francois Corthay added additional w(0) AND w(filterOrder+1)
-- 1.0 Romain Cheviron first implementation
--
-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html>
--
-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
-- <http://isi.hevs.ch/switzerland/robust-electronics.html>.
--
--------------------------------------------------------------------------------
--
-- Usage
-- Set the input signal bit number with the generic "inputBitNb".
--
-- Set the output signal bit number with the generic "outputBitNb". This
-- value must be greater or equal than "inputBitNb". The additional bits
-- are added as LSBs. They allow to increas the resolution as the bandwidth
-- is reduced.
--
-- Define the cutoff frequency with the generic "shiftBitNb". Every
-- increment in this value shifts the cutoff frequency down by an octave
-- (a factor of 2).
--
-- In order to define the filter function, the first lines of the
-- architecture have to be edited:
-- constant "filterOrder" obviously gives the filter order.
-- constant "coefficientBitNb" obviously gives the number of bits of
-- the coefficients.
-- constant "coefficient" give the time constants as unsigned numbers
-- ranging from 1 to (2**coefficientBitNb)-1. The relative values
-- of the coefficients give the shape of the transfer function.
-- The cutoff frequency is furthermore given by the "shiftBitNb"
-- generic.
-- constant "additionalInternalWBitNb" gives the number of additional
-- bits assigned to the internal signals corresponding to the state
-- variables of the analog filter. They are used to avoid overflows
-- on these signals.
-- The values for "shiftBitNb" and "constant additionalInternalWBitNb" can
-- be dertermined analytically, but a frequency sweep simulation allows to
-- set them iteratively.
--
-- The input samples are read from the signal "filterIn" at the rising edge
-- of "clock" when "en" is '1'.
--
-- With this, a new output sample is calculated and provided on
-- "filterOut". The output changes at the end of the iterative calculation
-- of the multiplication, which is roughly n clock periods after "en"
-- was '1'. The number of clock periods, n, is equal to the number of bits
-- of the coefficients. The output sample remains stable until the next
-- sample has been calculated.
--
-- The "reset" signal is active high.
--
--------------------------------------------------------------------------------
--
-- Synthesis results
--
-- A 3rd order filter with 16 bit input, 16 bit output and 4 bit shift
-- gives the following synthesis result on a Xilinx Spartan3-1000:
-- Number of Slice Flip Flops: 162 out of 15,360 1%
-- Number of 4 input LUTs: 282 out of 15,360 1%
-- Average Fanout of Non-Clock Nets: 2.73
--
-- A 6th order filter with 16 bit input, 16 bit output and 4 bit shift
-- gives the following synthesis result on a Xilinx Spartan3-1000:
-- Number of Slice Flip Flops: 333 out of 15,360 2%
-- Number of 4 input LUTs: 604 out of 15,360 3%
-- Average Fanout of Non-Clock Nets: 2.81
--
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY lowpass IS
GENERIC(
inputBitNb : positive := 16;
outputBitNb : positive := 16;
shiftBitNb : positive := 4
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
en : IN std_ulogic;
filterIn : IN signed (inputBitNb-1 DOWNTO 0);
filterOut : OUT signed (outputBitNb-1 DOWNTO 0)
);
END lowpass ;
--==============================================================================
ARCHITECTURE RTL OF lowpass IS
-- 3rd order Butterworth
--
-- constant filterOrder : natural := 3;
-- constant coefficientBitNb : natural := 8;
-- type unsigned_vector_c is array(1 to filterOrder)
-- of unsigned(coefficientBitNb-1 downto 0);
-- constant coefficient : unsigned_vector_c := (
-- to_unsigned(2**7, coefficientBitNb),
-- to_unsigned(2**6, coefficientBitNb),
-- to_unsigned(2**7, coefficientBitNb)
-- );
-- constant additionalInternalWBitNb: positive := 2;
-- 6th order Bessel
--
constant filterOrder : natural := 6;
constant coefficientBitNb : natural := 8;
type unsigned_vector_c is array(1 to filterOrder)
of unsigned(coefficientBitNb-1 downto 0);
constant coefficient : unsigned_vector_c := (
to_unsigned(215, coefficientBitNb),
to_unsigned( 88, coefficientBitNb),
to_unsigned( 81, coefficientBitNb),
to_unsigned( 61, coefficientBitNb),
to_unsigned( 38, coefficientBitNb),
to_unsigned( 13, coefficientBitNb)
);
constant additionalInternalWBitNb: positive := 4;
constant internalWBitNb: positive := filterOut'length + additionalInternalWBitNb;
signal inputSignalScaled : signed(internalWBitNb-1 downto 0);
constant internalAccumulatorBitNb : positive := internalWBitNb + shiftBitNb;
type signed_vector_accumulator is array(1 to filterOrder)
of signed(internalAccumulatorBitNb-1 downto 0);
type signed_vector_w is array(0 to filterOrder+1)
of signed(internalWBitNb-1 downto 0);
signal accumulator : signed_vector_accumulator;
signal w : signed_vector_w;
type unsigned_vector_coeffShiftReg is array(1 to filterOrder)
of unsigned(coefficientBitNb-1 downto 0);
signal coefficientShiftRegister: unsigned_vector_coeffShiftReg;
signal multiplicandBit: std_ulogic_vector(1 to filterOrder);
type signed_vector_multAcc is array(1 to filterOrder)
of signed(internalAccumulatorBitNb+coefficientBitNb-1 downto 0);
signal multiplicationAccumulator: signed_vector_multAcc;
signal cycleCounterShiftReg: unsigned(coefficientBitNb downto 0);
signal endOfCycle: std_ulogic;
signal calculating: std_ulogic;
signal wDebug : signed_vector_w;
BEGIN
------------------------------------------------------------------------------
-- Scale input signal to internal state variables size
inputSignalScaled <= SHIFT_LEFT(
RESIZE(filterIn, inputSignalScaled'length),
filterOut'length - filterIn'length
);
------------------------------------------------------------------------------
-- Accumulator chain
process(reset, clock)
begin
if reset = '1' then
accumulator <= (others => (others => '0'));
elsif rising_edge(clock) then
if en = '1' then
for index in 1 to filterOrder loop
accumulator(index) <= accumulator(index) + (
RESIZE(w(index-1), w(index)'length+1) -
RESIZE(w(index+1), w(index)'length+1)
);
end loop;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Multiplication sequence
-- Coefficient shift
process(reset, clock)
begin
if reset = '1' then
coefficientShiftregister <= (others => (others => '0'));
elsif rising_edge(clock) then
for index in 1 to filterOrder loop
if en = '1' then
coefficientShiftregister(index) <= coefficient(index);
else
coefficientShiftregister(index) <=
shift_right(coefficientShiftregister(index), 1);
end if;
end loop;
end if;
end process;
process(coefficientShiftregister)
begin
for index in 1 to filterOrder loop
multiplicandBit(index) <= coefficientShiftregister(index)(0);
end loop;
end process;
-- Multiplication accumulator
process(reset, clock)
begin
if reset = '1' then
multiplicationAccumulator <= (others => (others => '0'));
elsif rising_edge(clock) then
for index in 1 to filterOrder loop
if en = '1' then
multiplicationAccumulator(index) <= (others => '0');
elsif calculating = '1' then
if multiplicandBit(index) = '0' then
multiplicationAccumulator(index) <=
shift_right(multiplicationAccumulator(index), 1);
else
multiplicationAccumulator(index) <=
shift_right(multiplicationAccumulator(index), 1) +
shift_left(
resize(accumulator(index), multiplicationAccumulator(index)'length),
coefficientBitNb
);
end if;
end if;
end loop;
end if;
end process;
------------------------------------------------------------------------------
-- Analog filter state variables
process(multiplicationAccumulator, w, inputSignalScaled)
begin
for index in 1 to filterOrder loop
w(index) <= RESIZE(
SHIFT_RIGHT(
multiplicationAccumulator(index),
coefficientBitNb + shiftBitNb
),
w(index)'length
);
end loop;
-- w(0) combines input and w(1) for first accumulator
w(0) <= inputSignalScaled - w(1);
-- w(filterOrder+1) is a copy of w(filterOrder) for last accumulator
w(filterOrder+1) <= w(filterOrder);
end process;
------------------------------------------------------------------------------
-- Scale last state variables to output size and latch
process(reset, clock)
begin
if reset = '1' then
filterOut <= (others => '0');
elsif rising_edge(clock) then
if calculating = '0' then
filterOut <= RESIZE(w(w'high), filterOut'length);
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Multiplication cycle counter
process(reset, clock)
begin
if reset = '1' then
cycleCounterShiftReg <= (others => '0');
elsif rising_edge(clock) then
cycleCounterShiftReg <= shift_right(cycleCounterShiftReg, 1);
cycleCounterShiftReg(cycleCounterShiftReg'high) <= en;
end if;
end process;
endOfCycle <= cycleCounterShiftReg(0);
calculating <= '1' when cycleCounterShiftReg /= 0
else '0';
------------------------------------------------------------------------------
-- Debug information
process(reset, clock)
begin
if reset = '1' then
wDebug <= (others => (others => '0'));
elsif rising_edge(clock) then
for index in 1 to filterOrder loop
if calculating = '0' then
wDebug <= w;
end if;
end loop;
end if;
end process;
END ARCHITECTURE RTL; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/08 22:15:22
-- Nombre del módulo: clk_rom_1_512BPM - Behavioral
-- Comentarios adicionales:
-- Este componente une la ROM de 512 localidades de 28 bits, con el divisor de
-- frecuencia que toma valor de la ROM, con un reloj de 3.125MHz para lograr un
-- "divisor de frecuencia variable" de 1 a 512 BPM.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/metronomo-en-vhdl-2/
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_rom_1_512BPM is
GENERIC (
NBITS : integer := 28 -- Cantidad de bits que tiene cada registro en la ROM.
);
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC; -- Señal de reset.
addr : in STD_LOGIC_VECTOR(8 downto 0); -- Dirección de la ROM.
clk_out : out STD_LOGIC -- Reloj de salida.
);
end clk_rom_1_512BPM;
architecture Behavioral of clk_rom_1_512BPM is
-- Señal de 3.125MHZ para entrar en divisor de frecuencia con ROM.
signal clk3M125: STD_LOGIC := '0';
-- Señal intermedia para pasar de la ROM al componente del divisor.
signal escala: STD_LOGIC_VECTOR(NBITS-1 downto 0);
-- Señal para habilitar lectura de la ROM.
signal rom_en: STD_LOGIC := '0';
begin
-- La ROM se habilita siempre que no está el estado de reset.
rom_en <= NOT reset;
clk3M125Hz_i: entity work.clk3M125Hz(Behavioral)
PORT MAP(clk, reset, clk3M125);
rom512_28b_i: entity work.rom512_28b(Behavioral)
PORT MAP(clk, rom_en, addr, escala);
clk_rom_i: entity work.clk_rom(Behavioral)
PORT MAP(clk3M125, reset, escala, clk_out);
end Behavioral; |
----------------------------------------------------------------------------------
-- Compañía: Estado Finito
-- Ingeniero: Carlos Ramos
--
-- Fecha de creación: 2014/05/08 22:15:22
-- Nombre del módulo: clk_rom_1_512BPM - Behavioral
-- Comentarios adicionales:
-- Este componente une la ROM de 512 localidades de 28 bits, con el divisor de
-- frecuencia que toma valor de la ROM, con un reloj de 3.125MHz para lograr un
-- "divisor de frecuencia variable" de 1 a 512 BPM.
--
-- Comentarios adicionales:
-- Se puede encontrar más información en la siguiente dirección:
-- http://www.estadofinito.com/metronomo-en-vhdl-2/
--
-- Revisión:
-- Revisión 0.01 - Archivo creado.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_rom_1_512BPM is
GENERIC (
NBITS : integer := 28 -- Cantidad de bits que tiene cada registro en la ROM.
);
PORT (
clk : in STD_LOGIC; -- Reloj de entrada de 50MHz.
reset : in STD_LOGIC; -- Señal de reset.
addr : in STD_LOGIC_VECTOR(8 downto 0); -- Dirección de la ROM.
clk_out : out STD_LOGIC -- Reloj de salida.
);
end clk_rom_1_512BPM;
architecture Behavioral of clk_rom_1_512BPM is
-- Señal de 3.125MHZ para entrar en divisor de frecuencia con ROM.
signal clk3M125: STD_LOGIC := '0';
-- Señal intermedia para pasar de la ROM al componente del divisor.
signal escala: STD_LOGIC_VECTOR(NBITS-1 downto 0);
-- Señal para habilitar lectura de la ROM.
signal rom_en: STD_LOGIC := '0';
begin
-- La ROM se habilita siempre que no está el estado de reset.
rom_en <= NOT reset;
clk3M125Hz_i: entity work.clk3M125Hz(Behavioral)
PORT MAP(clk, reset, clk3M125);
rom512_28b_i: entity work.rom512_28b(Behavioral)
PORT MAP(clk, rom_en, addr, escala);
clk_rom_i: entity work.clk_rom(Behavioral)
PORT MAP(clk3M125, reset, escala, clk_out);
end Behavioral; |
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
-- Date : Wed Sep 10 03:37:56 2014
-- Host : Dtysky running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/spira_heaven/0-myworks/ld3320_axi/ld3320_axi_1.0/src/VOICE_ROM_INIT/VOICE_ROM_INIT_funcsim.vhdl
-- Design : VOICE_ROM_INIT
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity VOICE_ROM_INIT_blk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end VOICE_ROM_INIT_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_prim_wrapper is
signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12) => '0',
ADDRARDADDR(11) => '0',
ADDRARDADDR(10 downto 5) => addrb(5 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10 downto 5) => addra(5 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clkb,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11 downto 8) => dina(7 downto 4),
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11 downto 8) => dina(15 downto 12),
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3 downto 0) => dina(11 downto 8),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(11 downto 8) => doutb(7 downto 4),
DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(3 downto 0) => doutb(3 downto 0),
DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(11 downto 8) => doutb(15 downto 12),
DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(3 downto 0) => doutb(11 downto 8),
DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
ENARDEN => '1',
ENBWREN => wea(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '1',
WEBWE(2) => '1',
WEBWE(1) => '1',
WEBWE(0) => '1'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity VOICE_ROM_INIT_blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end VOICE_ROM_INIT_blk_mem_gen_prim_width;
architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.VOICE_ROM_INIT_blk_mem_gen_prim_wrapper
port map (
addra(5 downto 0) => addra(5 downto 0),
addrb(5 downto 0) => addrb(5 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity VOICE_ROM_INIT_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end VOICE_ROM_INIT_blk_mem_gen_generic_cstr;
architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.VOICE_ROM_INIT_blk_mem_gen_prim_width
port map (
addra(5 downto 0) => addra(5 downto 0),
addrb(5 downto 0) => addrb(5 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity VOICE_ROM_INIT_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_top : entity is "blk_mem_gen_top";
end VOICE_ROM_INIT_blk_mem_gen_top;
architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_top is
begin
\valid.cstr\: entity work.VOICE_ROM_INIT_blk_mem_gen_generic_cstr
port map (
addra(5 downto 0) => addra(5 downto 0),
addrb(5 downto 0) => addrb(5 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity VOICE_ROM_INIT_blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of VOICE_ROM_INIT_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end VOICE_ROM_INIT_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of VOICE_ROM_INIT_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.VOICE_ROM_INIT_blk_mem_gen_top
port map (
addra(5 downto 0) => addra(5 downto 0),
addrb(5 downto 0) => addrb(5 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
douta : out STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 15 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "VOICE_ROM_INIT.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 6;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 16;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 64;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 6;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 3.01735 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(15) <= \<const0>\;
douta(14) <= \<const0>\;
douta(13) <= \<const0>\;
douta(12) <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.VOICE_ROM_INIT_blk_mem_gen_v8_2_synth
port map (
addra(5 downto 0) => addra(5 downto 0),
addrb(5 downto 0) => addrb(5 downto 0),
clka => clka,
clkb => clkb,
dina(15 downto 0) => dina(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity VOICE_ROM_INIT is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 15 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of VOICE_ROM_INIT : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of VOICE_ROM_INIT : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of VOICE_ROM_INIT : entity is "blk_mem_gen_v8_2,Vivado 2014.2";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of VOICE_ROM_INIT : entity is "VOICE_ROM_INIT,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of VOICE_ROM_INIT : entity is "VOICE_ROM_INIT,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=VOICE_ROM_INIT.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.01735 mW}";
end VOICE_ROM_INIT;
architecture STRUCTURE of VOICE_ROM_INIT is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 6;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 6;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.01735 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "VOICE_ROM_INIT.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 64;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 64;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 16;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 16;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 64;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 64;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 16;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 16;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\VOICE_ROM_INIT_blk_mem_gen_v8_2__parameterized0\
port map (
addra(5 downto 0) => addra(5 downto 0),
addrb(5 downto 0) => addrb(5 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(15 downto 0) => dina(15 downto 0),
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(15 downto 0) => NLW_U0_douta_UNCONNECTED(15 downto 0),
doutb(15 downto 0) => doutb(15 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(5 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(5 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(5 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(5 downto 0),
s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package mdctrom2048 is
--n = 2048
constant rom_lenght_br: integer:=512;
constant rom_lenght: integer:=2560;
type rom_table is array (0 to rom_lenght-1) of std_logic_vector (31 downto 0);
type rom_bitrev is array (0 to rom_lenght_br-1) of std_logic_vector (31 downto 0);
constant bitrev: rom_bitrev:= rom_bitrev'(
X"000003fe",
X"00000000",
X"000001fe",
X"00000200",
X"000002fe",
X"00000100",
X"000000fe",
X"00000300",
X"0000037e",
X"00000080",
X"0000017e",
X"00000280",
X"0000027e",
X"00000180",
X"0000007e",
X"00000380",
X"000003be",
X"00000040",
X"000001be",
X"00000240",
X"000002be",
X"00000140",
X"000000be",
X"00000340",
X"0000033e",
X"000000c0",
X"0000013e",
X"000002c0",
X"0000023e",
X"000001c0",
X"0000003e",
X"000003c0",
X"000003de",
X"00000020",
X"000001de",
X"00000220",
X"000002de",
X"00000120",
X"000000de",
X"00000320",
X"0000035e",
X"000000a0",
X"0000015e",
X"000002a0",
X"0000025e",
X"000001a0",
X"0000005e",
X"000003a0",
X"0000039e",
X"00000060",
X"0000019e",
X"00000260",
X"0000029e",
X"00000160",
X"0000009e",
X"00000360",
X"0000031e",
X"000000e0",
X"0000011e",
X"000002e0",
X"0000021e",
X"000001e0",
X"0000001e",
X"000003e0",
X"000003ee",
X"00000010",
X"000001ee",
X"00000210",
X"000002ee",
X"00000110",
X"000000ee",
X"00000310",
X"0000036e",
X"00000090",
X"0000016e",
X"00000290",
X"0000026e",
X"00000190",
X"0000006e",
X"00000390",
X"000003ae",
X"00000050",
X"000001ae",
X"00000250",
X"000002ae",
X"00000150",
X"000000ae",
X"00000350",
X"0000032e",
X"000000d0",
X"0000012e",
X"000002d0",
X"0000022e",
X"000001d0",
X"0000002e",
X"000003d0",
X"000003ce",
X"00000030",
X"000001ce",
X"00000230",
X"000002ce",
X"00000130",
X"000000ce",
X"00000330",
X"0000034e",
X"000000b0",
X"0000014e",
X"000002b0",
X"0000024e",
X"000001b0",
X"0000004e",
X"000003b0",
X"0000038e",
X"00000070",
X"0000018e",
X"00000270",
X"0000028e",
X"00000170",
X"0000008e",
X"00000370",
X"0000030e",
X"000000f0",
X"0000010e",
X"000002f0",
X"0000020e",
X"000001f0",
X"0000000e",
X"000003f0",
X"000003f6",
X"00000008",
X"000001f6",
X"00000208",
X"000002f6",
X"00000108",
X"000000f6",
X"00000308",
X"00000376",
X"00000088",
X"00000176",
X"00000288",
X"00000276",
X"00000188",
X"00000076",
X"00000388",
X"000003b6",
X"00000048",
X"000001b6",
X"00000248",
X"000002b6",
X"00000148",
X"000000b6",
X"00000348",
X"00000336",
X"000000c8",
X"00000136",
X"000002c8",
X"00000236",
X"000001c8",
X"00000036",
X"000003c8",
X"000003d6",
X"00000028",
X"000001d6",
X"00000228",
X"000002d6",
X"00000128",
X"000000d6",
X"00000328",
X"00000356",
X"000000a8",
X"00000156",
X"000002a8",
X"00000256",
X"000001a8",
X"00000056",
X"000003a8",
X"00000396",
X"00000068",
X"00000196",
X"00000268",
X"00000296",
X"00000168",
X"00000096",
X"00000368",
X"00000316",
X"000000e8",
X"00000116",
X"000002e8",
X"00000216",
X"000001e8",
X"00000016",
X"000003e8",
X"000003e6",
X"00000018",
X"000001e6",
X"00000218",
X"000002e6",
X"00000118",
X"000000e6",
X"00000318",
X"00000366",
X"00000098",
X"00000166",
X"00000298",
X"00000266",
X"00000198",
X"00000066",
X"00000398",
X"000003a6",
X"00000058",
X"000001a6",
X"00000258",
X"000002a6",
X"00000158",
X"000000a6",
X"00000358",
X"00000326",
X"000000d8",
X"00000126",
X"000002d8",
X"00000226",
X"000001d8",
X"00000026",
X"000003d8",
X"000003c6",
X"00000038",
X"000001c6",
X"00000238",
X"000002c6",
X"00000138",
X"000000c6",
X"00000338",
X"00000346",
X"000000b8",
X"00000146",
X"000002b8",
X"00000246",
X"000001b8",
X"00000046",
X"000003b8",
X"00000386",
X"00000078",
X"00000186",
X"00000278",
X"00000286",
X"00000178",
X"00000086",
X"00000378",
X"00000306",
X"000000f8",
X"00000106",
X"000002f8",
X"00000206",
X"000001f8",
X"00000006",
X"000003f8",
X"000003fa",
X"00000004",
X"000001fa",
X"00000204",
X"000002fa",
X"00000104",
X"000000fa",
X"00000304",
X"0000037a",
X"00000084",
X"0000017a",
X"00000284",
X"0000027a",
X"00000184",
X"0000007a",
X"00000384",
X"000003ba",
X"00000044",
X"000001ba",
X"00000244",
X"000002ba",
X"00000144",
X"000000ba",
X"00000344",
X"0000033a",
X"000000c4",
X"0000013a",
X"000002c4",
X"0000023a",
X"000001c4",
X"0000003a",
X"000003c4",
X"000003da",
X"00000024",
X"000001da",
X"00000224",
X"000002da",
X"00000124",
X"000000da",
X"00000324",
X"0000035a",
X"000000a4",
X"0000015a",
X"000002a4",
X"0000025a",
X"000001a4",
X"0000005a",
X"000003a4",
X"0000039a",
X"00000064",
X"0000019a",
X"00000264",
X"0000029a",
X"00000164",
X"0000009a",
X"00000364",
X"0000031a",
X"000000e4",
X"0000011a",
X"000002e4",
X"0000021a",
X"000001e4",
X"0000001a",
X"000003e4",
X"000003ea",
X"00000014",
X"000001ea",
X"00000214",
X"000002ea",
X"00000114",
X"000000ea",
X"00000314",
X"0000036a",
X"00000094",
X"0000016a",
X"00000294",
X"0000026a",
X"00000194",
X"0000006a",
X"00000394",
X"000003aa",
X"00000054",
X"000001aa",
X"00000254",
X"000002aa",
X"00000154",
X"000000aa",
X"00000354",
X"0000032a",
X"000000d4",
X"0000012a",
X"000002d4",
X"0000022a",
X"000001d4",
X"0000002a",
X"000003d4",
X"000003ca",
X"00000034",
X"000001ca",
X"00000234",
X"000002ca",
X"00000134",
X"000000ca",
X"00000334",
X"0000034a",
X"000000b4",
X"0000014a",
X"000002b4",
X"0000024a",
X"000001b4",
X"0000004a",
X"000003b4",
X"0000038a",
X"00000074",
X"0000018a",
X"00000274",
X"0000028a",
X"00000174",
X"0000008a",
X"00000374",
X"0000030a",
X"000000f4",
X"0000010a",
X"000002f4",
X"0000020a",
X"000001f4",
X"0000000a",
X"000003f4",
X"000003f2",
X"0000000c",
X"000001f2",
X"0000020c",
X"000002f2",
X"0000010c",
X"000000f2",
X"0000030c",
X"00000372",
X"0000008c",
X"00000172",
X"0000028c",
X"00000272",
X"0000018c",
X"00000072",
X"0000038c",
X"000003b2",
X"0000004c",
X"000001b2",
X"0000024c",
X"000002b2",
X"0000014c",
X"000000b2",
X"0000034c",
X"00000332",
X"000000cc",
X"00000132",
X"000002cc",
X"00000232",
X"000001cc",
X"00000032",
X"000003cc",
X"000003d2",
X"0000002c",
X"000001d2",
X"0000022c",
X"000002d2",
X"0000012c",
X"000000d2",
X"0000032c",
X"00000352",
X"000000ac",
X"00000152",
X"000002ac",
X"00000252",
X"000001ac",
X"00000052",
X"000003ac",
X"00000392",
X"0000006c",
X"00000192",
X"0000026c",
X"00000292",
X"0000016c",
X"00000092",
X"0000036c",
X"00000312",
X"000000ec",
X"00000112",
X"000002ec",
X"00000212",
X"000001ec",
X"00000012",
X"000003ec",
X"000003e2",
X"0000001c",
X"000001e2",
X"0000021c",
X"000002e2",
X"0000011c",
X"000000e2",
X"0000031c",
X"00000362",
X"0000009c",
X"00000162",
X"0000029c",
X"00000262",
X"0000019c",
X"00000062",
X"0000039c",
X"000003a2",
X"0000005c",
X"000001a2",
X"0000025c",
X"000002a2",
X"0000015c",
X"000000a2",
X"0000035c",
X"00000322",
X"000000dc",
X"00000122",
X"000002dc",
X"00000222",
X"000001dc",
X"00000022",
X"000003dc",
X"000003c2",
X"0000003c",
X"000001c2",
X"0000023c",
X"000002c2",
X"0000013c",
X"000000c2",
X"0000033c",
X"00000342",
X"000000bc",
X"00000142",
X"000002bc",
X"00000242",
X"000001bc",
X"00000042",
X"000003bc",
X"00000382",
X"0000007c",
X"00000182",
X"0000027c",
X"00000282",
X"0000017c",
X"00000082",
X"0000037c",
X"00000302",
X"000000fc",
X"00000102",
X"000002fc",
X"00000202",
X"000001fc",
X"00000002",
X"000003fc"
);
--T:
constant T: rom_table:= rom_table'(
X"00004000",
X"00000000",
X"00003ffe",
X"ffffff9c",
X"00003ffd",
X"ffffff37",
X"00003ffc",
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X"00002c2a",
X"00002e3f",
X"00002c3c",
X"00002e2e",
X"00002c4e",
X"00002e1c",
X"00002c60",
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X"00002c72",
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X"00002c84",
X"00002de7",
X"00002c96",
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X"00002ca8",
X"00002dc4",
X"00002cba",
X"00002db3",
X"00002ccc",
X"00002da1",
X"00002cde",
X"00002d90",
X"00002cf0",
X"00002d7e",
X"00002d02",
X"00002d6c",
X"00002d14",
X"00002d5b",
X"00002d26",
X"00002d49",
X"00002d38",
X"00001fff",
X"ffffffe7",
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X"ffffffb5",
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X"ffffff83",
X"00001ffd",
X"ffffff51",
X"00001ffc",
X"ffffff1e",
X"00001ffa",
X"fffffeec",
X"00001ff8",
X"fffffeba",
X"00001ff6",
X"fffffe88",
X"00001ff4",
X"fffffe55",
X"00001ff1",
X"fffffe23",
X"00001fee",
X"fffffdf1",
X"00001feb",
X"fffffdbf",
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X"fffffd8d",
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X"fffffd5b",
X"00001fdf",
X"fffffd29",
X"00001fda",
X"fffffcf7",
X"00001fd5",
X"fffffcc4",
X"00001fd0",
X"fffffc92",
X"00001fca",
X"fffffc60",
X"00001fc5",
X"fffffc2e",
X"00001fbf",
X"fffffbfd",
X"00001fb8",
X"fffffbcb",
X"00001fb1",
X"fffffb99",
X"00001faa",
X"fffffb67",
X"00001fa3",
X"fffffb36",
X"00001f9b",
X"fffffb04",
X"00001f93",
X"fffffad2",
X"00001f8b",
X"fffffaa1",
X"00001f82",
X"fffffa6f",
X"00001f79",
X"fffffa3e",
X"00001f70",
X"fffffa0d",
X"00001f67",
X"fffff9db",
X"00001f5d",
X"fffff9aa",
X"00001f52",
X"fffff979",
X"00001f48",
X"fffff947",
X"00001f3e",
X"fffff916",
X"00001f33",
X"fffff8e5",
X"00001f27",
X"fffff8b4",
X"00001f1b",
X"fffff883",
X"00001f10",
X"fffff852",
X"00001f04",
X"fffff822",
X"00001ef7",
X"fffff7f1",
X"00001eea",
X"fffff7c0",
X"00001edd",
X"fffff790",
X"00001ed0",
X"fffff75f",
X"00001ec2",
X"fffff72f",
X"00001eb4",
X"fffff6ff",
X"00001ea6",
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X"fffff60f",
X"00001e5a",
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X"00001e49",
X"fffff5b0",
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X"fffff580",
X"00001e29",
X"fffff550",
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X"fffff521",
X"00001e06",
X"fffff4f2",
X"00001df5",
X"fffff4c3",
X"00001de3",
X"fffff494",
X"00001dd1",
X"fffff465",
X"00001dbf",
X"fffff436",
X"00001dac",
X"fffff407",
X"00001d99",
X"fffff3d9",
X"00001d86",
X"fffff3aa",
X"00001d72",
X"fffff37c",
X"00001d5e",
X"fffff34e",
X"00001d4a",
X"fffff320",
X"00001d36",
X"fffff2f2",
X"00001d21",
X"fffff2c4",
X"00001d0c",
X"fffff297",
X"00001cf7",
X"fffff269",
X"00001ce2",
X"fffff23b",
X"00001ccc",
X"fffff20e",
X"00001cb6",
X"fffff1e1",
X"00001ca0",
X"fffff1b4",
X"00001c89",
X"fffff187",
X"00001c72",
X"fffff15b",
X"00001c5b",
X"fffff12e",
X"00001c44",
X"fffff101",
X"00001c2c",
X"fffff0d5",
X"00001c14",
X"fffff0a9",
X"00001bfc",
X"fffff07d",
X"00001be4",
X"fffff051",
X"00001bcb",
X"fffff025",
X"00001bb1",
X"ffffeff9",
X"00001b98",
X"ffffefce",
X"00001b7f",
X"ffffefa3",
X"00001b65",
X"ffffef78",
X"00001b4a",
X"ffffef4d",
X"00001b30",
X"ffffef22",
X"00001b16",
X"ffffeef7",
X"00001afb",
X"ffffeecd",
X"00001adf",
X"ffffeea3",
X"00001ac4",
X"ffffee79",
X"00001aa9",
X"ffffee4f",
X"00001a8d",
X"ffffee25",
X"00001a70",
X"ffffedfb",
X"00001a54",
X"ffffedd2",
X"00001a37",
X"ffffeda8",
X"00001a1a",
X"ffffed7f",
X"000019fd",
X"ffffed56",
X"000019e0",
X"ffffed2e",
X"000019c2",
X"ffffed05",
X"000019a4",
X"ffffecdc",
X"00001986",
X"ffffecb4",
X"00001967",
X"ffffec8c",
X"00001949",
X"ffffec64",
X"0000192a",
X"ffffec3d",
X"0000190a",
X"ffffec16",
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X"000018cc",
X"ffffebc7",
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X"0000052e",
X"ffffe06d",
X"000004fc",
X"ffffe065",
X"000004ca",
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X"00000499",
X"ffffe056",
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X"00000435",
X"ffffe048",
X"00000403",
X"ffffe041",
X"000003d2",
X"ffffe03b",
X"000003a0",
X"ffffe036",
X"0000036e",
X"ffffe030",
X"0000033c",
X"ffffe02b",
X"00000309",
X"ffffe026",
X"000002d7",
X"ffffe021",
X"000002a5",
X"ffffe01d",
X"00000273",
X"ffffe019",
X"00000241",
X"ffffe015",
X"0000020f",
X"ffffe012",
X"000001dd",
X"ffffe00f",
X"000001ab",
X"ffffe00c",
X"00000178",
X"ffffe00a",
X"00000146",
X"ffffe008",
X"00000114",
X"ffffe006",
X"000000e2",
X"ffffe004",
X"000000af",
X"ffffe003",
X"0000007d",
X"ffffe002",
X"0000004b",
X"ffffe001",
X"00000019",
X"ffffe001"
);
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set is
generic (
C_M_AXI_GMEM_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_ID_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_DATA_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_BUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_CACHE_VALUE : INTEGER := 3;
C_M_AXI_GMEM_USER_VALUE : INTEGER := 0;
C_M_AXI_GMEM_PROT_VALUE : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_gmem_AWVALID : OUT STD_LOGIC;
m_axi_gmem_AWREADY : IN STD_LOGIC;
m_axi_gmem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_AWUSER_WIDTH-1 downto 0);
m_axi_gmem_WVALID : OUT STD_LOGIC;
m_axi_gmem_WREADY : IN STD_LOGIC;
m_axi_gmem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH/8-1 downto 0);
m_axi_gmem_WLAST : OUT STD_LOGIC;
m_axi_gmem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_WUSER_WIDTH-1 downto 0);
m_axi_gmem_ARVALID : OUT STD_LOGIC;
m_axi_gmem_ARREADY : IN STD_LOGIC;
m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ARUSER_WIDTH-1 downto 0);
m_axi_gmem_RVALID : IN STD_LOGIC;
m_axi_gmem_RREADY : OUT STD_LOGIC;
m_axi_gmem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_RLAST : IN STD_LOGIC;
m_axi_gmem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_RUSER_WIDTH-1 downto 0);
m_axi_gmem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BVALID : IN STD_LOGIC;
m_axi_gmem_BREADY : OUT STD_LOGIC;
m_axi_gmem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_BUSER_WIDTH-1 downto 0);
data : IN STD_LOGIC_VECTOR (31 downto 0);
key : IN STD_LOGIC_VECTOR (31 downto 0);
val_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"set,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.500000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.437500,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=623,HLS_SYN_LUT=743}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal gmem_AWVALID : STD_LOGIC;
signal gmem_AWREADY : STD_LOGIC;
signal gmem_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WVALID : STD_LOGIC;
signal gmem_WREADY : STD_LOGIC;
signal gmem_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_WLAST : STD_LOGIC;
signal gmem_WID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARVALID : STD_LOGIC;
signal gmem_ARREADY : STD_LOGIC;
signal gmem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RVALID : STD_LOGIC;
signal gmem_RREADY : STD_LOGIC;
signal gmem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_RLAST : STD_LOGIC;
signal gmem_RID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BVALID : STD_LOGIC;
signal gmem_BREADY : STD_LOGIC;
signal gmem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal set_gmem_m_axi_U_ap_dummy_ce : STD_LOGIC;
signal data1_reg_90 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_ap_start : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_done : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_idle : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_ready : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_data1 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_tmp : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_src : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component set_assign_val IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
component set_gmem_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
set_gmem_m_axi_U : component set_gmem_m_axi
generic map (
USER_DW => 32,
USER_AW => 32,
USER_MAXREQS => 5,
C_M_AXI_ID_WIDTH => C_M_AXI_GMEM_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_GMEM_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_GMEM_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_GMEM_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_GMEM_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_GMEM_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_GMEM_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_GMEM_BUSER_WIDTH,
C_USER_VALUE => C_M_AXI_GMEM_USER_VALUE,
C_PROT_VALUE => C_M_AXI_GMEM_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_GMEM_CACHE_VALUE)
port map (
AWVALID => m_axi_gmem_AWVALID,
AWREADY => m_axi_gmem_AWREADY,
AWADDR => m_axi_gmem_AWADDR,
AWID => m_axi_gmem_AWID,
AWLEN => m_axi_gmem_AWLEN,
AWSIZE => m_axi_gmem_AWSIZE,
AWBURST => m_axi_gmem_AWBURST,
AWLOCK => m_axi_gmem_AWLOCK,
AWCACHE => m_axi_gmem_AWCACHE,
AWPROT => m_axi_gmem_AWPROT,
AWQOS => m_axi_gmem_AWQOS,
AWREGION => m_axi_gmem_AWREGION,
AWUSER => m_axi_gmem_AWUSER,
WVALID => m_axi_gmem_WVALID,
WREADY => m_axi_gmem_WREADY,
WDATA => m_axi_gmem_WDATA,
WSTRB => m_axi_gmem_WSTRB,
WLAST => m_axi_gmem_WLAST,
WID => m_axi_gmem_WID,
WUSER => m_axi_gmem_WUSER,
ARVALID => m_axi_gmem_ARVALID,
ARREADY => m_axi_gmem_ARREADY,
ARADDR => m_axi_gmem_ARADDR,
ARID => m_axi_gmem_ARID,
ARLEN => m_axi_gmem_ARLEN,
ARSIZE => m_axi_gmem_ARSIZE,
ARBURST => m_axi_gmem_ARBURST,
ARLOCK => m_axi_gmem_ARLOCK,
ARCACHE => m_axi_gmem_ARCACHE,
ARPROT => m_axi_gmem_ARPROT,
ARQOS => m_axi_gmem_ARQOS,
ARREGION => m_axi_gmem_ARREGION,
ARUSER => m_axi_gmem_ARUSER,
RVALID => m_axi_gmem_RVALID,
RREADY => m_axi_gmem_RREADY,
RDATA => m_axi_gmem_RDATA,
RLAST => m_axi_gmem_RLAST,
RID => m_axi_gmem_RID,
RUSER => m_axi_gmem_RUSER,
RRESP => m_axi_gmem_RRESP,
BVALID => m_axi_gmem_BVALID,
BREADY => m_axi_gmem_BREADY,
BRESP => m_axi_gmem_BRESP,
BID => m_axi_gmem_BID,
BUSER => m_axi_gmem_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => set_gmem_m_axi_U_ap_dummy_ce,
I_ARVALID => gmem_ARVALID,
I_ARREADY => gmem_ARREADY,
I_ARADDR => gmem_ARADDR,
I_ARID => gmem_ARID,
I_ARLEN => gmem_ARLEN,
I_ARSIZE => gmem_ARSIZE,
I_ARLOCK => gmem_ARLOCK,
I_ARCACHE => gmem_ARCACHE,
I_ARQOS => gmem_ARQOS,
I_ARPROT => gmem_ARPROT,
I_ARUSER => gmem_ARUSER,
I_ARBURST => gmem_ARBURST,
I_ARREGION => gmem_ARREGION,
I_RVALID => gmem_RVALID,
I_RREADY => gmem_RREADY,
I_RDATA => gmem_RDATA,
I_RID => gmem_RID,
I_RUSER => gmem_RUSER,
I_RRESP => gmem_RRESP,
I_RLAST => gmem_RLAST,
I_AWVALID => gmem_AWVALID,
I_AWREADY => gmem_AWREADY,
I_AWADDR => gmem_AWADDR,
I_AWID => gmem_AWID,
I_AWLEN => gmem_AWLEN,
I_AWSIZE => gmem_AWSIZE,
I_AWLOCK => gmem_AWLOCK,
I_AWCACHE => gmem_AWCACHE,
I_AWQOS => gmem_AWQOS,
I_AWPROT => gmem_AWPROT,
I_AWUSER => gmem_AWUSER,
I_AWBURST => gmem_AWBURST,
I_AWREGION => gmem_AWREGION,
I_WVALID => gmem_WVALID,
I_WREADY => gmem_WREADY,
I_WDATA => gmem_WDATA,
I_WID => gmem_WID,
I_WUSER => gmem_WUSER,
I_WLAST => gmem_WLAST,
I_WSTRB => gmem_WSTRB,
I_BVALID => gmem_BVALID,
I_BREADY => gmem_BREADY,
I_BRESP => gmem_BRESP,
I_BID => gmem_BID,
I_BUSER => gmem_BUSER);
grp_set_assign_val_fu_58 : component set_assign_val
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_set_assign_val_fu_58_ap_start,
ap_done => grp_set_assign_val_fu_58_ap_done,
ap_idle => grp_set_assign_val_fu_58_ap_idle,
ap_ready => grp_set_assign_val_fu_58_ap_ready,
m_axi_dest_AWVALID => grp_set_assign_val_fu_58_m_axi_dest_AWVALID,
m_axi_dest_AWREADY => grp_set_assign_val_fu_58_m_axi_dest_AWREADY,
m_axi_dest_AWADDR => grp_set_assign_val_fu_58_m_axi_dest_AWADDR,
m_axi_dest_AWID => grp_set_assign_val_fu_58_m_axi_dest_AWID,
m_axi_dest_AWLEN => grp_set_assign_val_fu_58_m_axi_dest_AWLEN,
m_axi_dest_AWSIZE => grp_set_assign_val_fu_58_m_axi_dest_AWSIZE,
m_axi_dest_AWBURST => grp_set_assign_val_fu_58_m_axi_dest_AWBURST,
m_axi_dest_AWLOCK => grp_set_assign_val_fu_58_m_axi_dest_AWLOCK,
m_axi_dest_AWCACHE => grp_set_assign_val_fu_58_m_axi_dest_AWCACHE,
m_axi_dest_AWPROT => grp_set_assign_val_fu_58_m_axi_dest_AWPROT,
m_axi_dest_AWQOS => grp_set_assign_val_fu_58_m_axi_dest_AWQOS,
m_axi_dest_AWREGION => grp_set_assign_val_fu_58_m_axi_dest_AWREGION,
m_axi_dest_AWUSER => grp_set_assign_val_fu_58_m_axi_dest_AWUSER,
m_axi_dest_WVALID => grp_set_assign_val_fu_58_m_axi_dest_WVALID,
m_axi_dest_WREADY => grp_set_assign_val_fu_58_m_axi_dest_WREADY,
m_axi_dest_WDATA => grp_set_assign_val_fu_58_m_axi_dest_WDATA,
m_axi_dest_WSTRB => grp_set_assign_val_fu_58_m_axi_dest_WSTRB,
m_axi_dest_WLAST => grp_set_assign_val_fu_58_m_axi_dest_WLAST,
m_axi_dest_WID => grp_set_assign_val_fu_58_m_axi_dest_WID,
m_axi_dest_WUSER => grp_set_assign_val_fu_58_m_axi_dest_WUSER,
m_axi_dest_ARVALID => grp_set_assign_val_fu_58_m_axi_dest_ARVALID,
m_axi_dest_ARREADY => grp_set_assign_val_fu_58_m_axi_dest_ARREADY,
m_axi_dest_ARADDR => grp_set_assign_val_fu_58_m_axi_dest_ARADDR,
m_axi_dest_ARID => grp_set_assign_val_fu_58_m_axi_dest_ARID,
m_axi_dest_ARLEN => grp_set_assign_val_fu_58_m_axi_dest_ARLEN,
m_axi_dest_ARSIZE => grp_set_assign_val_fu_58_m_axi_dest_ARSIZE,
m_axi_dest_ARBURST => grp_set_assign_val_fu_58_m_axi_dest_ARBURST,
m_axi_dest_ARLOCK => grp_set_assign_val_fu_58_m_axi_dest_ARLOCK,
m_axi_dest_ARCACHE => grp_set_assign_val_fu_58_m_axi_dest_ARCACHE,
m_axi_dest_ARPROT => grp_set_assign_val_fu_58_m_axi_dest_ARPROT,
m_axi_dest_ARQOS => grp_set_assign_val_fu_58_m_axi_dest_ARQOS,
m_axi_dest_ARREGION => grp_set_assign_val_fu_58_m_axi_dest_ARREGION,
m_axi_dest_ARUSER => grp_set_assign_val_fu_58_m_axi_dest_ARUSER,
m_axi_dest_RVALID => grp_set_assign_val_fu_58_m_axi_dest_RVALID,
m_axi_dest_RREADY => grp_set_assign_val_fu_58_m_axi_dest_RREADY,
m_axi_dest_RDATA => grp_set_assign_val_fu_58_m_axi_dest_RDATA,
m_axi_dest_RLAST => grp_set_assign_val_fu_58_m_axi_dest_RLAST,
m_axi_dest_RID => grp_set_assign_val_fu_58_m_axi_dest_RID,
m_axi_dest_RUSER => grp_set_assign_val_fu_58_m_axi_dest_RUSER,
m_axi_dest_RRESP => grp_set_assign_val_fu_58_m_axi_dest_RRESP,
m_axi_dest_BVALID => grp_set_assign_val_fu_58_m_axi_dest_BVALID,
m_axi_dest_BREADY => grp_set_assign_val_fu_58_m_axi_dest_BREADY,
m_axi_dest_BRESP => grp_set_assign_val_fu_58_m_axi_dest_BRESP,
m_axi_dest_BID => grp_set_assign_val_fu_58_m_axi_dest_BID,
m_axi_dest_BUSER => grp_set_assign_val_fu_58_m_axi_dest_BUSER,
data1 => grp_set_assign_val_fu_58_data1,
tmp => grp_set_assign_val_fu_58_tmp,
src => grp_set_assign_val_fu_58_src);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_set_assign_val_fu_58_ap_start_ap_start_reg assign process. --
grp_set_assign_val_fu_58_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_set_assign_val_fu_58_ap_ready)) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
data1_reg_90 <= data(31 downto 2);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, grp_set_assign_val_fu_58_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
gmem_ARADDR <= ap_const_lv32_0;
gmem_ARBURST <= ap_const_lv2_0;
gmem_ARCACHE <= ap_const_lv4_0;
gmem_ARID <= ap_const_lv1_0;
gmem_ARLEN <= ap_const_lv32_0;
gmem_ARLOCK <= ap_const_lv2_0;
gmem_ARPROT <= ap_const_lv3_0;
gmem_ARQOS <= ap_const_lv4_0;
gmem_ARREGION <= ap_const_lv4_0;
gmem_ARSIZE <= ap_const_lv3_0;
gmem_ARUSER <= ap_const_lv1_0;
gmem_ARVALID <= ap_const_logic_0;
gmem_AWADDR <= grp_set_assign_val_fu_58_m_axi_dest_AWADDR;
gmem_AWBURST <= grp_set_assign_val_fu_58_m_axi_dest_AWBURST;
gmem_AWCACHE <= grp_set_assign_val_fu_58_m_axi_dest_AWCACHE;
gmem_AWID <= grp_set_assign_val_fu_58_m_axi_dest_AWID;
gmem_AWLEN <= grp_set_assign_val_fu_58_m_axi_dest_AWLEN;
gmem_AWLOCK <= grp_set_assign_val_fu_58_m_axi_dest_AWLOCK;
gmem_AWPROT <= grp_set_assign_val_fu_58_m_axi_dest_AWPROT;
gmem_AWQOS <= grp_set_assign_val_fu_58_m_axi_dest_AWQOS;
gmem_AWREGION <= grp_set_assign_val_fu_58_m_axi_dest_AWREGION;
gmem_AWSIZE <= grp_set_assign_val_fu_58_m_axi_dest_AWSIZE;
gmem_AWUSER <= grp_set_assign_val_fu_58_m_axi_dest_AWUSER;
-- gmem_AWVALID assign process. --
gmem_AWVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_AWVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_AWVALID <= grp_set_assign_val_fu_58_m_axi_dest_AWVALID;
else
gmem_AWVALID <= ap_const_logic_0;
end if;
end process;
-- gmem_BREADY assign process. --
gmem_BREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_BREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_BREADY <= grp_set_assign_val_fu_58_m_axi_dest_BREADY;
else
gmem_BREADY <= ap_const_logic_0;
end if;
end process;
gmem_RREADY <= ap_const_logic_0;
gmem_WDATA <= grp_set_assign_val_fu_58_m_axi_dest_WDATA;
gmem_WID <= grp_set_assign_val_fu_58_m_axi_dest_WID;
gmem_WLAST <= grp_set_assign_val_fu_58_m_axi_dest_WLAST;
gmem_WSTRB <= grp_set_assign_val_fu_58_m_axi_dest_WSTRB;
gmem_WUSER <= grp_set_assign_val_fu_58_m_axi_dest_WUSER;
-- gmem_WVALID assign process. --
gmem_WVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_WVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_WVALID <= grp_set_assign_val_fu_58_m_axi_dest_WVALID;
else
gmem_WVALID <= ap_const_logic_0;
end if;
end process;
grp_set_assign_val_fu_58_ap_start <= grp_set_assign_val_fu_58_ap_start_ap_start_reg;
grp_set_assign_val_fu_58_data1 <= data1_reg_90;
grp_set_assign_val_fu_58_m_axi_dest_ARREADY <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_AWREADY <= gmem_AWREADY;
grp_set_assign_val_fu_58_m_axi_dest_BID <= gmem_BID;
grp_set_assign_val_fu_58_m_axi_dest_BRESP <= gmem_BRESP;
grp_set_assign_val_fu_58_m_axi_dest_BUSER <= gmem_BUSER;
grp_set_assign_val_fu_58_m_axi_dest_BVALID <= gmem_BVALID;
grp_set_assign_val_fu_58_m_axi_dest_RDATA <= ap_const_lv32_0;
grp_set_assign_val_fu_58_m_axi_dest_RID <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RLAST <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_RRESP <= ap_const_lv2_0;
grp_set_assign_val_fu_58_m_axi_dest_RUSER <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RVALID <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_WREADY <= gmem_WREADY;
grp_set_assign_val_fu_58_src <= val_r;
grp_set_assign_val_fu_58_tmp <= key;
set_gmem_m_axi_U_ap_dummy_ce <= ap_const_logic_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set is
generic (
C_M_AXI_GMEM_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_ID_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_DATA_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_BUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_CACHE_VALUE : INTEGER := 3;
C_M_AXI_GMEM_USER_VALUE : INTEGER := 0;
C_M_AXI_GMEM_PROT_VALUE : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_gmem_AWVALID : OUT STD_LOGIC;
m_axi_gmem_AWREADY : IN STD_LOGIC;
m_axi_gmem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_AWUSER_WIDTH-1 downto 0);
m_axi_gmem_WVALID : OUT STD_LOGIC;
m_axi_gmem_WREADY : IN STD_LOGIC;
m_axi_gmem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH/8-1 downto 0);
m_axi_gmem_WLAST : OUT STD_LOGIC;
m_axi_gmem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_WUSER_WIDTH-1 downto 0);
m_axi_gmem_ARVALID : OUT STD_LOGIC;
m_axi_gmem_ARREADY : IN STD_LOGIC;
m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ARUSER_WIDTH-1 downto 0);
m_axi_gmem_RVALID : IN STD_LOGIC;
m_axi_gmem_RREADY : OUT STD_LOGIC;
m_axi_gmem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_RLAST : IN STD_LOGIC;
m_axi_gmem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_RUSER_WIDTH-1 downto 0);
m_axi_gmem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BVALID : IN STD_LOGIC;
m_axi_gmem_BREADY : OUT STD_LOGIC;
m_axi_gmem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_BUSER_WIDTH-1 downto 0);
data : IN STD_LOGIC_VECTOR (31 downto 0);
key : IN STD_LOGIC_VECTOR (31 downto 0);
val_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"set,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.500000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.437500,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=623,HLS_SYN_LUT=743}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal gmem_AWVALID : STD_LOGIC;
signal gmem_AWREADY : STD_LOGIC;
signal gmem_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WVALID : STD_LOGIC;
signal gmem_WREADY : STD_LOGIC;
signal gmem_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_WLAST : STD_LOGIC;
signal gmem_WID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARVALID : STD_LOGIC;
signal gmem_ARREADY : STD_LOGIC;
signal gmem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RVALID : STD_LOGIC;
signal gmem_RREADY : STD_LOGIC;
signal gmem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_RLAST : STD_LOGIC;
signal gmem_RID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BVALID : STD_LOGIC;
signal gmem_BREADY : STD_LOGIC;
signal gmem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal set_gmem_m_axi_U_ap_dummy_ce : STD_LOGIC;
signal data1_reg_90 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_ap_start : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_done : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_idle : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_ready : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_data1 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_tmp : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_src : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component set_assign_val IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
component set_gmem_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
set_gmem_m_axi_U : component set_gmem_m_axi
generic map (
USER_DW => 32,
USER_AW => 32,
USER_MAXREQS => 5,
C_M_AXI_ID_WIDTH => C_M_AXI_GMEM_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_GMEM_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_GMEM_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_GMEM_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_GMEM_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_GMEM_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_GMEM_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_GMEM_BUSER_WIDTH,
C_USER_VALUE => C_M_AXI_GMEM_USER_VALUE,
C_PROT_VALUE => C_M_AXI_GMEM_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_GMEM_CACHE_VALUE)
port map (
AWVALID => m_axi_gmem_AWVALID,
AWREADY => m_axi_gmem_AWREADY,
AWADDR => m_axi_gmem_AWADDR,
AWID => m_axi_gmem_AWID,
AWLEN => m_axi_gmem_AWLEN,
AWSIZE => m_axi_gmem_AWSIZE,
AWBURST => m_axi_gmem_AWBURST,
AWLOCK => m_axi_gmem_AWLOCK,
AWCACHE => m_axi_gmem_AWCACHE,
AWPROT => m_axi_gmem_AWPROT,
AWQOS => m_axi_gmem_AWQOS,
AWREGION => m_axi_gmem_AWREGION,
AWUSER => m_axi_gmem_AWUSER,
WVALID => m_axi_gmem_WVALID,
WREADY => m_axi_gmem_WREADY,
WDATA => m_axi_gmem_WDATA,
WSTRB => m_axi_gmem_WSTRB,
WLAST => m_axi_gmem_WLAST,
WID => m_axi_gmem_WID,
WUSER => m_axi_gmem_WUSER,
ARVALID => m_axi_gmem_ARVALID,
ARREADY => m_axi_gmem_ARREADY,
ARADDR => m_axi_gmem_ARADDR,
ARID => m_axi_gmem_ARID,
ARLEN => m_axi_gmem_ARLEN,
ARSIZE => m_axi_gmem_ARSIZE,
ARBURST => m_axi_gmem_ARBURST,
ARLOCK => m_axi_gmem_ARLOCK,
ARCACHE => m_axi_gmem_ARCACHE,
ARPROT => m_axi_gmem_ARPROT,
ARQOS => m_axi_gmem_ARQOS,
ARREGION => m_axi_gmem_ARREGION,
ARUSER => m_axi_gmem_ARUSER,
RVALID => m_axi_gmem_RVALID,
RREADY => m_axi_gmem_RREADY,
RDATA => m_axi_gmem_RDATA,
RLAST => m_axi_gmem_RLAST,
RID => m_axi_gmem_RID,
RUSER => m_axi_gmem_RUSER,
RRESP => m_axi_gmem_RRESP,
BVALID => m_axi_gmem_BVALID,
BREADY => m_axi_gmem_BREADY,
BRESP => m_axi_gmem_BRESP,
BID => m_axi_gmem_BID,
BUSER => m_axi_gmem_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => set_gmem_m_axi_U_ap_dummy_ce,
I_ARVALID => gmem_ARVALID,
I_ARREADY => gmem_ARREADY,
I_ARADDR => gmem_ARADDR,
I_ARID => gmem_ARID,
I_ARLEN => gmem_ARLEN,
I_ARSIZE => gmem_ARSIZE,
I_ARLOCK => gmem_ARLOCK,
I_ARCACHE => gmem_ARCACHE,
I_ARQOS => gmem_ARQOS,
I_ARPROT => gmem_ARPROT,
I_ARUSER => gmem_ARUSER,
I_ARBURST => gmem_ARBURST,
I_ARREGION => gmem_ARREGION,
I_RVALID => gmem_RVALID,
I_RREADY => gmem_RREADY,
I_RDATA => gmem_RDATA,
I_RID => gmem_RID,
I_RUSER => gmem_RUSER,
I_RRESP => gmem_RRESP,
I_RLAST => gmem_RLAST,
I_AWVALID => gmem_AWVALID,
I_AWREADY => gmem_AWREADY,
I_AWADDR => gmem_AWADDR,
I_AWID => gmem_AWID,
I_AWLEN => gmem_AWLEN,
I_AWSIZE => gmem_AWSIZE,
I_AWLOCK => gmem_AWLOCK,
I_AWCACHE => gmem_AWCACHE,
I_AWQOS => gmem_AWQOS,
I_AWPROT => gmem_AWPROT,
I_AWUSER => gmem_AWUSER,
I_AWBURST => gmem_AWBURST,
I_AWREGION => gmem_AWREGION,
I_WVALID => gmem_WVALID,
I_WREADY => gmem_WREADY,
I_WDATA => gmem_WDATA,
I_WID => gmem_WID,
I_WUSER => gmem_WUSER,
I_WLAST => gmem_WLAST,
I_WSTRB => gmem_WSTRB,
I_BVALID => gmem_BVALID,
I_BREADY => gmem_BREADY,
I_BRESP => gmem_BRESP,
I_BID => gmem_BID,
I_BUSER => gmem_BUSER);
grp_set_assign_val_fu_58 : component set_assign_val
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_set_assign_val_fu_58_ap_start,
ap_done => grp_set_assign_val_fu_58_ap_done,
ap_idle => grp_set_assign_val_fu_58_ap_idle,
ap_ready => grp_set_assign_val_fu_58_ap_ready,
m_axi_dest_AWVALID => grp_set_assign_val_fu_58_m_axi_dest_AWVALID,
m_axi_dest_AWREADY => grp_set_assign_val_fu_58_m_axi_dest_AWREADY,
m_axi_dest_AWADDR => grp_set_assign_val_fu_58_m_axi_dest_AWADDR,
m_axi_dest_AWID => grp_set_assign_val_fu_58_m_axi_dest_AWID,
m_axi_dest_AWLEN => grp_set_assign_val_fu_58_m_axi_dest_AWLEN,
m_axi_dest_AWSIZE => grp_set_assign_val_fu_58_m_axi_dest_AWSIZE,
m_axi_dest_AWBURST => grp_set_assign_val_fu_58_m_axi_dest_AWBURST,
m_axi_dest_AWLOCK => grp_set_assign_val_fu_58_m_axi_dest_AWLOCK,
m_axi_dest_AWCACHE => grp_set_assign_val_fu_58_m_axi_dest_AWCACHE,
m_axi_dest_AWPROT => grp_set_assign_val_fu_58_m_axi_dest_AWPROT,
m_axi_dest_AWQOS => grp_set_assign_val_fu_58_m_axi_dest_AWQOS,
m_axi_dest_AWREGION => grp_set_assign_val_fu_58_m_axi_dest_AWREGION,
m_axi_dest_AWUSER => grp_set_assign_val_fu_58_m_axi_dest_AWUSER,
m_axi_dest_WVALID => grp_set_assign_val_fu_58_m_axi_dest_WVALID,
m_axi_dest_WREADY => grp_set_assign_val_fu_58_m_axi_dest_WREADY,
m_axi_dest_WDATA => grp_set_assign_val_fu_58_m_axi_dest_WDATA,
m_axi_dest_WSTRB => grp_set_assign_val_fu_58_m_axi_dest_WSTRB,
m_axi_dest_WLAST => grp_set_assign_val_fu_58_m_axi_dest_WLAST,
m_axi_dest_WID => grp_set_assign_val_fu_58_m_axi_dest_WID,
m_axi_dest_WUSER => grp_set_assign_val_fu_58_m_axi_dest_WUSER,
m_axi_dest_ARVALID => grp_set_assign_val_fu_58_m_axi_dest_ARVALID,
m_axi_dest_ARREADY => grp_set_assign_val_fu_58_m_axi_dest_ARREADY,
m_axi_dest_ARADDR => grp_set_assign_val_fu_58_m_axi_dest_ARADDR,
m_axi_dest_ARID => grp_set_assign_val_fu_58_m_axi_dest_ARID,
m_axi_dest_ARLEN => grp_set_assign_val_fu_58_m_axi_dest_ARLEN,
m_axi_dest_ARSIZE => grp_set_assign_val_fu_58_m_axi_dest_ARSIZE,
m_axi_dest_ARBURST => grp_set_assign_val_fu_58_m_axi_dest_ARBURST,
m_axi_dest_ARLOCK => grp_set_assign_val_fu_58_m_axi_dest_ARLOCK,
m_axi_dest_ARCACHE => grp_set_assign_val_fu_58_m_axi_dest_ARCACHE,
m_axi_dest_ARPROT => grp_set_assign_val_fu_58_m_axi_dest_ARPROT,
m_axi_dest_ARQOS => grp_set_assign_val_fu_58_m_axi_dest_ARQOS,
m_axi_dest_ARREGION => grp_set_assign_val_fu_58_m_axi_dest_ARREGION,
m_axi_dest_ARUSER => grp_set_assign_val_fu_58_m_axi_dest_ARUSER,
m_axi_dest_RVALID => grp_set_assign_val_fu_58_m_axi_dest_RVALID,
m_axi_dest_RREADY => grp_set_assign_val_fu_58_m_axi_dest_RREADY,
m_axi_dest_RDATA => grp_set_assign_val_fu_58_m_axi_dest_RDATA,
m_axi_dest_RLAST => grp_set_assign_val_fu_58_m_axi_dest_RLAST,
m_axi_dest_RID => grp_set_assign_val_fu_58_m_axi_dest_RID,
m_axi_dest_RUSER => grp_set_assign_val_fu_58_m_axi_dest_RUSER,
m_axi_dest_RRESP => grp_set_assign_val_fu_58_m_axi_dest_RRESP,
m_axi_dest_BVALID => grp_set_assign_val_fu_58_m_axi_dest_BVALID,
m_axi_dest_BREADY => grp_set_assign_val_fu_58_m_axi_dest_BREADY,
m_axi_dest_BRESP => grp_set_assign_val_fu_58_m_axi_dest_BRESP,
m_axi_dest_BID => grp_set_assign_val_fu_58_m_axi_dest_BID,
m_axi_dest_BUSER => grp_set_assign_val_fu_58_m_axi_dest_BUSER,
data1 => grp_set_assign_val_fu_58_data1,
tmp => grp_set_assign_val_fu_58_tmp,
src => grp_set_assign_val_fu_58_src);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_set_assign_val_fu_58_ap_start_ap_start_reg assign process. --
grp_set_assign_val_fu_58_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_set_assign_val_fu_58_ap_ready)) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
data1_reg_90 <= data(31 downto 2);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, grp_set_assign_val_fu_58_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
gmem_ARADDR <= ap_const_lv32_0;
gmem_ARBURST <= ap_const_lv2_0;
gmem_ARCACHE <= ap_const_lv4_0;
gmem_ARID <= ap_const_lv1_0;
gmem_ARLEN <= ap_const_lv32_0;
gmem_ARLOCK <= ap_const_lv2_0;
gmem_ARPROT <= ap_const_lv3_0;
gmem_ARQOS <= ap_const_lv4_0;
gmem_ARREGION <= ap_const_lv4_0;
gmem_ARSIZE <= ap_const_lv3_0;
gmem_ARUSER <= ap_const_lv1_0;
gmem_ARVALID <= ap_const_logic_0;
gmem_AWADDR <= grp_set_assign_val_fu_58_m_axi_dest_AWADDR;
gmem_AWBURST <= grp_set_assign_val_fu_58_m_axi_dest_AWBURST;
gmem_AWCACHE <= grp_set_assign_val_fu_58_m_axi_dest_AWCACHE;
gmem_AWID <= grp_set_assign_val_fu_58_m_axi_dest_AWID;
gmem_AWLEN <= grp_set_assign_val_fu_58_m_axi_dest_AWLEN;
gmem_AWLOCK <= grp_set_assign_val_fu_58_m_axi_dest_AWLOCK;
gmem_AWPROT <= grp_set_assign_val_fu_58_m_axi_dest_AWPROT;
gmem_AWQOS <= grp_set_assign_val_fu_58_m_axi_dest_AWQOS;
gmem_AWREGION <= grp_set_assign_val_fu_58_m_axi_dest_AWREGION;
gmem_AWSIZE <= grp_set_assign_val_fu_58_m_axi_dest_AWSIZE;
gmem_AWUSER <= grp_set_assign_val_fu_58_m_axi_dest_AWUSER;
-- gmem_AWVALID assign process. --
gmem_AWVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_AWVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_AWVALID <= grp_set_assign_val_fu_58_m_axi_dest_AWVALID;
else
gmem_AWVALID <= ap_const_logic_0;
end if;
end process;
-- gmem_BREADY assign process. --
gmem_BREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_BREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_BREADY <= grp_set_assign_val_fu_58_m_axi_dest_BREADY;
else
gmem_BREADY <= ap_const_logic_0;
end if;
end process;
gmem_RREADY <= ap_const_logic_0;
gmem_WDATA <= grp_set_assign_val_fu_58_m_axi_dest_WDATA;
gmem_WID <= grp_set_assign_val_fu_58_m_axi_dest_WID;
gmem_WLAST <= grp_set_assign_val_fu_58_m_axi_dest_WLAST;
gmem_WSTRB <= grp_set_assign_val_fu_58_m_axi_dest_WSTRB;
gmem_WUSER <= grp_set_assign_val_fu_58_m_axi_dest_WUSER;
-- gmem_WVALID assign process. --
gmem_WVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_WVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_WVALID <= grp_set_assign_val_fu_58_m_axi_dest_WVALID;
else
gmem_WVALID <= ap_const_logic_0;
end if;
end process;
grp_set_assign_val_fu_58_ap_start <= grp_set_assign_val_fu_58_ap_start_ap_start_reg;
grp_set_assign_val_fu_58_data1 <= data1_reg_90;
grp_set_assign_val_fu_58_m_axi_dest_ARREADY <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_AWREADY <= gmem_AWREADY;
grp_set_assign_val_fu_58_m_axi_dest_BID <= gmem_BID;
grp_set_assign_val_fu_58_m_axi_dest_BRESP <= gmem_BRESP;
grp_set_assign_val_fu_58_m_axi_dest_BUSER <= gmem_BUSER;
grp_set_assign_val_fu_58_m_axi_dest_BVALID <= gmem_BVALID;
grp_set_assign_val_fu_58_m_axi_dest_RDATA <= ap_const_lv32_0;
grp_set_assign_val_fu_58_m_axi_dest_RID <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RLAST <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_RRESP <= ap_const_lv2_0;
grp_set_assign_val_fu_58_m_axi_dest_RUSER <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RVALID <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_WREADY <= gmem_WREADY;
grp_set_assign_val_fu_58_src <= val_r;
grp_set_assign_val_fu_58_tmp <= key;
set_gmem_m_axi_U_ap_dummy_ce <= ap_const_logic_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set is
generic (
C_M_AXI_GMEM_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_ID_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_DATA_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_BUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_CACHE_VALUE : INTEGER := 3;
C_M_AXI_GMEM_USER_VALUE : INTEGER := 0;
C_M_AXI_GMEM_PROT_VALUE : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_gmem_AWVALID : OUT STD_LOGIC;
m_axi_gmem_AWREADY : IN STD_LOGIC;
m_axi_gmem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_AWUSER_WIDTH-1 downto 0);
m_axi_gmem_WVALID : OUT STD_LOGIC;
m_axi_gmem_WREADY : IN STD_LOGIC;
m_axi_gmem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH/8-1 downto 0);
m_axi_gmem_WLAST : OUT STD_LOGIC;
m_axi_gmem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_WUSER_WIDTH-1 downto 0);
m_axi_gmem_ARVALID : OUT STD_LOGIC;
m_axi_gmem_ARREADY : IN STD_LOGIC;
m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ARUSER_WIDTH-1 downto 0);
m_axi_gmem_RVALID : IN STD_LOGIC;
m_axi_gmem_RREADY : OUT STD_LOGIC;
m_axi_gmem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_RLAST : IN STD_LOGIC;
m_axi_gmem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_RUSER_WIDTH-1 downto 0);
m_axi_gmem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BVALID : IN STD_LOGIC;
m_axi_gmem_BREADY : OUT STD_LOGIC;
m_axi_gmem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_BUSER_WIDTH-1 downto 0);
data : IN STD_LOGIC_VECTOR (31 downto 0);
key : IN STD_LOGIC_VECTOR (31 downto 0);
val_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"set,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.500000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.437500,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=623,HLS_SYN_LUT=743}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal gmem_AWVALID : STD_LOGIC;
signal gmem_AWREADY : STD_LOGIC;
signal gmem_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WVALID : STD_LOGIC;
signal gmem_WREADY : STD_LOGIC;
signal gmem_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_WLAST : STD_LOGIC;
signal gmem_WID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARVALID : STD_LOGIC;
signal gmem_ARREADY : STD_LOGIC;
signal gmem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RVALID : STD_LOGIC;
signal gmem_RREADY : STD_LOGIC;
signal gmem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_RLAST : STD_LOGIC;
signal gmem_RID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BVALID : STD_LOGIC;
signal gmem_BREADY : STD_LOGIC;
signal gmem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal set_gmem_m_axi_U_ap_dummy_ce : STD_LOGIC;
signal data1_reg_90 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_ap_start : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_done : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_idle : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_ready : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_data1 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_tmp : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_src : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component set_assign_val IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
component set_gmem_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
set_gmem_m_axi_U : component set_gmem_m_axi
generic map (
USER_DW => 32,
USER_AW => 32,
USER_MAXREQS => 5,
C_M_AXI_ID_WIDTH => C_M_AXI_GMEM_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_GMEM_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_GMEM_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_GMEM_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_GMEM_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_GMEM_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_GMEM_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_GMEM_BUSER_WIDTH,
C_USER_VALUE => C_M_AXI_GMEM_USER_VALUE,
C_PROT_VALUE => C_M_AXI_GMEM_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_GMEM_CACHE_VALUE)
port map (
AWVALID => m_axi_gmem_AWVALID,
AWREADY => m_axi_gmem_AWREADY,
AWADDR => m_axi_gmem_AWADDR,
AWID => m_axi_gmem_AWID,
AWLEN => m_axi_gmem_AWLEN,
AWSIZE => m_axi_gmem_AWSIZE,
AWBURST => m_axi_gmem_AWBURST,
AWLOCK => m_axi_gmem_AWLOCK,
AWCACHE => m_axi_gmem_AWCACHE,
AWPROT => m_axi_gmem_AWPROT,
AWQOS => m_axi_gmem_AWQOS,
AWREGION => m_axi_gmem_AWREGION,
AWUSER => m_axi_gmem_AWUSER,
WVALID => m_axi_gmem_WVALID,
WREADY => m_axi_gmem_WREADY,
WDATA => m_axi_gmem_WDATA,
WSTRB => m_axi_gmem_WSTRB,
WLAST => m_axi_gmem_WLAST,
WID => m_axi_gmem_WID,
WUSER => m_axi_gmem_WUSER,
ARVALID => m_axi_gmem_ARVALID,
ARREADY => m_axi_gmem_ARREADY,
ARADDR => m_axi_gmem_ARADDR,
ARID => m_axi_gmem_ARID,
ARLEN => m_axi_gmem_ARLEN,
ARSIZE => m_axi_gmem_ARSIZE,
ARBURST => m_axi_gmem_ARBURST,
ARLOCK => m_axi_gmem_ARLOCK,
ARCACHE => m_axi_gmem_ARCACHE,
ARPROT => m_axi_gmem_ARPROT,
ARQOS => m_axi_gmem_ARQOS,
ARREGION => m_axi_gmem_ARREGION,
ARUSER => m_axi_gmem_ARUSER,
RVALID => m_axi_gmem_RVALID,
RREADY => m_axi_gmem_RREADY,
RDATA => m_axi_gmem_RDATA,
RLAST => m_axi_gmem_RLAST,
RID => m_axi_gmem_RID,
RUSER => m_axi_gmem_RUSER,
RRESP => m_axi_gmem_RRESP,
BVALID => m_axi_gmem_BVALID,
BREADY => m_axi_gmem_BREADY,
BRESP => m_axi_gmem_BRESP,
BID => m_axi_gmem_BID,
BUSER => m_axi_gmem_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => set_gmem_m_axi_U_ap_dummy_ce,
I_ARVALID => gmem_ARVALID,
I_ARREADY => gmem_ARREADY,
I_ARADDR => gmem_ARADDR,
I_ARID => gmem_ARID,
I_ARLEN => gmem_ARLEN,
I_ARSIZE => gmem_ARSIZE,
I_ARLOCK => gmem_ARLOCK,
I_ARCACHE => gmem_ARCACHE,
I_ARQOS => gmem_ARQOS,
I_ARPROT => gmem_ARPROT,
I_ARUSER => gmem_ARUSER,
I_ARBURST => gmem_ARBURST,
I_ARREGION => gmem_ARREGION,
I_RVALID => gmem_RVALID,
I_RREADY => gmem_RREADY,
I_RDATA => gmem_RDATA,
I_RID => gmem_RID,
I_RUSER => gmem_RUSER,
I_RRESP => gmem_RRESP,
I_RLAST => gmem_RLAST,
I_AWVALID => gmem_AWVALID,
I_AWREADY => gmem_AWREADY,
I_AWADDR => gmem_AWADDR,
I_AWID => gmem_AWID,
I_AWLEN => gmem_AWLEN,
I_AWSIZE => gmem_AWSIZE,
I_AWLOCK => gmem_AWLOCK,
I_AWCACHE => gmem_AWCACHE,
I_AWQOS => gmem_AWQOS,
I_AWPROT => gmem_AWPROT,
I_AWUSER => gmem_AWUSER,
I_AWBURST => gmem_AWBURST,
I_AWREGION => gmem_AWREGION,
I_WVALID => gmem_WVALID,
I_WREADY => gmem_WREADY,
I_WDATA => gmem_WDATA,
I_WID => gmem_WID,
I_WUSER => gmem_WUSER,
I_WLAST => gmem_WLAST,
I_WSTRB => gmem_WSTRB,
I_BVALID => gmem_BVALID,
I_BREADY => gmem_BREADY,
I_BRESP => gmem_BRESP,
I_BID => gmem_BID,
I_BUSER => gmem_BUSER);
grp_set_assign_val_fu_58 : component set_assign_val
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_set_assign_val_fu_58_ap_start,
ap_done => grp_set_assign_val_fu_58_ap_done,
ap_idle => grp_set_assign_val_fu_58_ap_idle,
ap_ready => grp_set_assign_val_fu_58_ap_ready,
m_axi_dest_AWVALID => grp_set_assign_val_fu_58_m_axi_dest_AWVALID,
m_axi_dest_AWREADY => grp_set_assign_val_fu_58_m_axi_dest_AWREADY,
m_axi_dest_AWADDR => grp_set_assign_val_fu_58_m_axi_dest_AWADDR,
m_axi_dest_AWID => grp_set_assign_val_fu_58_m_axi_dest_AWID,
m_axi_dest_AWLEN => grp_set_assign_val_fu_58_m_axi_dest_AWLEN,
m_axi_dest_AWSIZE => grp_set_assign_val_fu_58_m_axi_dest_AWSIZE,
m_axi_dest_AWBURST => grp_set_assign_val_fu_58_m_axi_dest_AWBURST,
m_axi_dest_AWLOCK => grp_set_assign_val_fu_58_m_axi_dest_AWLOCK,
m_axi_dest_AWCACHE => grp_set_assign_val_fu_58_m_axi_dest_AWCACHE,
m_axi_dest_AWPROT => grp_set_assign_val_fu_58_m_axi_dest_AWPROT,
m_axi_dest_AWQOS => grp_set_assign_val_fu_58_m_axi_dest_AWQOS,
m_axi_dest_AWREGION => grp_set_assign_val_fu_58_m_axi_dest_AWREGION,
m_axi_dest_AWUSER => grp_set_assign_val_fu_58_m_axi_dest_AWUSER,
m_axi_dest_WVALID => grp_set_assign_val_fu_58_m_axi_dest_WVALID,
m_axi_dest_WREADY => grp_set_assign_val_fu_58_m_axi_dest_WREADY,
m_axi_dest_WDATA => grp_set_assign_val_fu_58_m_axi_dest_WDATA,
m_axi_dest_WSTRB => grp_set_assign_val_fu_58_m_axi_dest_WSTRB,
m_axi_dest_WLAST => grp_set_assign_val_fu_58_m_axi_dest_WLAST,
m_axi_dest_WID => grp_set_assign_val_fu_58_m_axi_dest_WID,
m_axi_dest_WUSER => grp_set_assign_val_fu_58_m_axi_dest_WUSER,
m_axi_dest_ARVALID => grp_set_assign_val_fu_58_m_axi_dest_ARVALID,
m_axi_dest_ARREADY => grp_set_assign_val_fu_58_m_axi_dest_ARREADY,
m_axi_dest_ARADDR => grp_set_assign_val_fu_58_m_axi_dest_ARADDR,
m_axi_dest_ARID => grp_set_assign_val_fu_58_m_axi_dest_ARID,
m_axi_dest_ARLEN => grp_set_assign_val_fu_58_m_axi_dest_ARLEN,
m_axi_dest_ARSIZE => grp_set_assign_val_fu_58_m_axi_dest_ARSIZE,
m_axi_dest_ARBURST => grp_set_assign_val_fu_58_m_axi_dest_ARBURST,
m_axi_dest_ARLOCK => grp_set_assign_val_fu_58_m_axi_dest_ARLOCK,
m_axi_dest_ARCACHE => grp_set_assign_val_fu_58_m_axi_dest_ARCACHE,
m_axi_dest_ARPROT => grp_set_assign_val_fu_58_m_axi_dest_ARPROT,
m_axi_dest_ARQOS => grp_set_assign_val_fu_58_m_axi_dest_ARQOS,
m_axi_dest_ARREGION => grp_set_assign_val_fu_58_m_axi_dest_ARREGION,
m_axi_dest_ARUSER => grp_set_assign_val_fu_58_m_axi_dest_ARUSER,
m_axi_dest_RVALID => grp_set_assign_val_fu_58_m_axi_dest_RVALID,
m_axi_dest_RREADY => grp_set_assign_val_fu_58_m_axi_dest_RREADY,
m_axi_dest_RDATA => grp_set_assign_val_fu_58_m_axi_dest_RDATA,
m_axi_dest_RLAST => grp_set_assign_val_fu_58_m_axi_dest_RLAST,
m_axi_dest_RID => grp_set_assign_val_fu_58_m_axi_dest_RID,
m_axi_dest_RUSER => grp_set_assign_val_fu_58_m_axi_dest_RUSER,
m_axi_dest_RRESP => grp_set_assign_val_fu_58_m_axi_dest_RRESP,
m_axi_dest_BVALID => grp_set_assign_val_fu_58_m_axi_dest_BVALID,
m_axi_dest_BREADY => grp_set_assign_val_fu_58_m_axi_dest_BREADY,
m_axi_dest_BRESP => grp_set_assign_val_fu_58_m_axi_dest_BRESP,
m_axi_dest_BID => grp_set_assign_val_fu_58_m_axi_dest_BID,
m_axi_dest_BUSER => grp_set_assign_val_fu_58_m_axi_dest_BUSER,
data1 => grp_set_assign_val_fu_58_data1,
tmp => grp_set_assign_val_fu_58_tmp,
src => grp_set_assign_val_fu_58_src);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_set_assign_val_fu_58_ap_start_ap_start_reg assign process. --
grp_set_assign_val_fu_58_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_set_assign_val_fu_58_ap_ready)) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
data1_reg_90 <= data(31 downto 2);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, grp_set_assign_val_fu_58_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
gmem_ARADDR <= ap_const_lv32_0;
gmem_ARBURST <= ap_const_lv2_0;
gmem_ARCACHE <= ap_const_lv4_0;
gmem_ARID <= ap_const_lv1_0;
gmem_ARLEN <= ap_const_lv32_0;
gmem_ARLOCK <= ap_const_lv2_0;
gmem_ARPROT <= ap_const_lv3_0;
gmem_ARQOS <= ap_const_lv4_0;
gmem_ARREGION <= ap_const_lv4_0;
gmem_ARSIZE <= ap_const_lv3_0;
gmem_ARUSER <= ap_const_lv1_0;
gmem_ARVALID <= ap_const_logic_0;
gmem_AWADDR <= grp_set_assign_val_fu_58_m_axi_dest_AWADDR;
gmem_AWBURST <= grp_set_assign_val_fu_58_m_axi_dest_AWBURST;
gmem_AWCACHE <= grp_set_assign_val_fu_58_m_axi_dest_AWCACHE;
gmem_AWID <= grp_set_assign_val_fu_58_m_axi_dest_AWID;
gmem_AWLEN <= grp_set_assign_val_fu_58_m_axi_dest_AWLEN;
gmem_AWLOCK <= grp_set_assign_val_fu_58_m_axi_dest_AWLOCK;
gmem_AWPROT <= grp_set_assign_val_fu_58_m_axi_dest_AWPROT;
gmem_AWQOS <= grp_set_assign_val_fu_58_m_axi_dest_AWQOS;
gmem_AWREGION <= grp_set_assign_val_fu_58_m_axi_dest_AWREGION;
gmem_AWSIZE <= grp_set_assign_val_fu_58_m_axi_dest_AWSIZE;
gmem_AWUSER <= grp_set_assign_val_fu_58_m_axi_dest_AWUSER;
-- gmem_AWVALID assign process. --
gmem_AWVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_AWVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_AWVALID <= grp_set_assign_val_fu_58_m_axi_dest_AWVALID;
else
gmem_AWVALID <= ap_const_logic_0;
end if;
end process;
-- gmem_BREADY assign process. --
gmem_BREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_BREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_BREADY <= grp_set_assign_val_fu_58_m_axi_dest_BREADY;
else
gmem_BREADY <= ap_const_logic_0;
end if;
end process;
gmem_RREADY <= ap_const_logic_0;
gmem_WDATA <= grp_set_assign_val_fu_58_m_axi_dest_WDATA;
gmem_WID <= grp_set_assign_val_fu_58_m_axi_dest_WID;
gmem_WLAST <= grp_set_assign_val_fu_58_m_axi_dest_WLAST;
gmem_WSTRB <= grp_set_assign_val_fu_58_m_axi_dest_WSTRB;
gmem_WUSER <= grp_set_assign_val_fu_58_m_axi_dest_WUSER;
-- gmem_WVALID assign process. --
gmem_WVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_WVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_WVALID <= grp_set_assign_val_fu_58_m_axi_dest_WVALID;
else
gmem_WVALID <= ap_const_logic_0;
end if;
end process;
grp_set_assign_val_fu_58_ap_start <= grp_set_assign_val_fu_58_ap_start_ap_start_reg;
grp_set_assign_val_fu_58_data1 <= data1_reg_90;
grp_set_assign_val_fu_58_m_axi_dest_ARREADY <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_AWREADY <= gmem_AWREADY;
grp_set_assign_val_fu_58_m_axi_dest_BID <= gmem_BID;
grp_set_assign_val_fu_58_m_axi_dest_BRESP <= gmem_BRESP;
grp_set_assign_val_fu_58_m_axi_dest_BUSER <= gmem_BUSER;
grp_set_assign_val_fu_58_m_axi_dest_BVALID <= gmem_BVALID;
grp_set_assign_val_fu_58_m_axi_dest_RDATA <= ap_const_lv32_0;
grp_set_assign_val_fu_58_m_axi_dest_RID <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RLAST <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_RRESP <= ap_const_lv2_0;
grp_set_assign_val_fu_58_m_axi_dest_RUSER <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RVALID <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_WREADY <= gmem_WREADY;
grp_set_assign_val_fu_58_src <= val_r;
grp_set_assign_val_fu_58_tmp <= key;
set_gmem_m_axi_U_ap_dummy_ce <= ap_const_logic_1;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set is
generic (
C_M_AXI_GMEM_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_ID_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_DATA_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_BUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_CACHE_VALUE : INTEGER := 3;
C_M_AXI_GMEM_USER_VALUE : INTEGER := 0;
C_M_AXI_GMEM_PROT_VALUE : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_gmem_AWVALID : OUT STD_LOGIC;
m_axi_gmem_AWREADY : IN STD_LOGIC;
m_axi_gmem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_AWUSER_WIDTH-1 downto 0);
m_axi_gmem_WVALID : OUT STD_LOGIC;
m_axi_gmem_WREADY : IN STD_LOGIC;
m_axi_gmem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH/8-1 downto 0);
m_axi_gmem_WLAST : OUT STD_LOGIC;
m_axi_gmem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_WUSER_WIDTH-1 downto 0);
m_axi_gmem_ARVALID : OUT STD_LOGIC;
m_axi_gmem_ARREADY : IN STD_LOGIC;
m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ARUSER_WIDTH-1 downto 0);
m_axi_gmem_RVALID : IN STD_LOGIC;
m_axi_gmem_RREADY : OUT STD_LOGIC;
m_axi_gmem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_RLAST : IN STD_LOGIC;
m_axi_gmem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_RUSER_WIDTH-1 downto 0);
m_axi_gmem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BVALID : IN STD_LOGIC;
m_axi_gmem_BREADY : OUT STD_LOGIC;
m_axi_gmem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_BUSER_WIDTH-1 downto 0);
data : IN STD_LOGIC_VECTOR (31 downto 0);
key : IN STD_LOGIC_VECTOR (31 downto 0);
val_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"set,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.500000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.437500,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=623,HLS_SYN_LUT=743}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal gmem_AWVALID : STD_LOGIC;
signal gmem_AWREADY : STD_LOGIC;
signal gmem_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WVALID : STD_LOGIC;
signal gmem_WREADY : STD_LOGIC;
signal gmem_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_WLAST : STD_LOGIC;
signal gmem_WID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARVALID : STD_LOGIC;
signal gmem_ARREADY : STD_LOGIC;
signal gmem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RVALID : STD_LOGIC;
signal gmem_RREADY : STD_LOGIC;
signal gmem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_RLAST : STD_LOGIC;
signal gmem_RID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BVALID : STD_LOGIC;
signal gmem_BREADY : STD_LOGIC;
signal gmem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal set_gmem_m_axi_U_ap_dummy_ce : STD_LOGIC;
signal data1_reg_90 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_ap_start : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_done : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_idle : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_ready : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_data1 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_tmp : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_src : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component set_assign_val IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
component set_gmem_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
set_gmem_m_axi_U : component set_gmem_m_axi
generic map (
USER_DW => 32,
USER_AW => 32,
USER_MAXREQS => 5,
C_M_AXI_ID_WIDTH => C_M_AXI_GMEM_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_GMEM_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_GMEM_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_GMEM_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_GMEM_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_GMEM_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_GMEM_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_GMEM_BUSER_WIDTH,
C_USER_VALUE => C_M_AXI_GMEM_USER_VALUE,
C_PROT_VALUE => C_M_AXI_GMEM_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_GMEM_CACHE_VALUE)
port map (
AWVALID => m_axi_gmem_AWVALID,
AWREADY => m_axi_gmem_AWREADY,
AWADDR => m_axi_gmem_AWADDR,
AWID => m_axi_gmem_AWID,
AWLEN => m_axi_gmem_AWLEN,
AWSIZE => m_axi_gmem_AWSIZE,
AWBURST => m_axi_gmem_AWBURST,
AWLOCK => m_axi_gmem_AWLOCK,
AWCACHE => m_axi_gmem_AWCACHE,
AWPROT => m_axi_gmem_AWPROT,
AWQOS => m_axi_gmem_AWQOS,
AWREGION => m_axi_gmem_AWREGION,
AWUSER => m_axi_gmem_AWUSER,
WVALID => m_axi_gmem_WVALID,
WREADY => m_axi_gmem_WREADY,
WDATA => m_axi_gmem_WDATA,
WSTRB => m_axi_gmem_WSTRB,
WLAST => m_axi_gmem_WLAST,
WID => m_axi_gmem_WID,
WUSER => m_axi_gmem_WUSER,
ARVALID => m_axi_gmem_ARVALID,
ARREADY => m_axi_gmem_ARREADY,
ARADDR => m_axi_gmem_ARADDR,
ARID => m_axi_gmem_ARID,
ARLEN => m_axi_gmem_ARLEN,
ARSIZE => m_axi_gmem_ARSIZE,
ARBURST => m_axi_gmem_ARBURST,
ARLOCK => m_axi_gmem_ARLOCK,
ARCACHE => m_axi_gmem_ARCACHE,
ARPROT => m_axi_gmem_ARPROT,
ARQOS => m_axi_gmem_ARQOS,
ARREGION => m_axi_gmem_ARREGION,
ARUSER => m_axi_gmem_ARUSER,
RVALID => m_axi_gmem_RVALID,
RREADY => m_axi_gmem_RREADY,
RDATA => m_axi_gmem_RDATA,
RLAST => m_axi_gmem_RLAST,
RID => m_axi_gmem_RID,
RUSER => m_axi_gmem_RUSER,
RRESP => m_axi_gmem_RRESP,
BVALID => m_axi_gmem_BVALID,
BREADY => m_axi_gmem_BREADY,
BRESP => m_axi_gmem_BRESP,
BID => m_axi_gmem_BID,
BUSER => m_axi_gmem_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => set_gmem_m_axi_U_ap_dummy_ce,
I_ARVALID => gmem_ARVALID,
I_ARREADY => gmem_ARREADY,
I_ARADDR => gmem_ARADDR,
I_ARID => gmem_ARID,
I_ARLEN => gmem_ARLEN,
I_ARSIZE => gmem_ARSIZE,
I_ARLOCK => gmem_ARLOCK,
I_ARCACHE => gmem_ARCACHE,
I_ARQOS => gmem_ARQOS,
I_ARPROT => gmem_ARPROT,
I_ARUSER => gmem_ARUSER,
I_ARBURST => gmem_ARBURST,
I_ARREGION => gmem_ARREGION,
I_RVALID => gmem_RVALID,
I_RREADY => gmem_RREADY,
I_RDATA => gmem_RDATA,
I_RID => gmem_RID,
I_RUSER => gmem_RUSER,
I_RRESP => gmem_RRESP,
I_RLAST => gmem_RLAST,
I_AWVALID => gmem_AWVALID,
I_AWREADY => gmem_AWREADY,
I_AWADDR => gmem_AWADDR,
I_AWID => gmem_AWID,
I_AWLEN => gmem_AWLEN,
I_AWSIZE => gmem_AWSIZE,
I_AWLOCK => gmem_AWLOCK,
I_AWCACHE => gmem_AWCACHE,
I_AWQOS => gmem_AWQOS,
I_AWPROT => gmem_AWPROT,
I_AWUSER => gmem_AWUSER,
I_AWBURST => gmem_AWBURST,
I_AWREGION => gmem_AWREGION,
I_WVALID => gmem_WVALID,
I_WREADY => gmem_WREADY,
I_WDATA => gmem_WDATA,
I_WID => gmem_WID,
I_WUSER => gmem_WUSER,
I_WLAST => gmem_WLAST,
I_WSTRB => gmem_WSTRB,
I_BVALID => gmem_BVALID,
I_BREADY => gmem_BREADY,
I_BRESP => gmem_BRESP,
I_BID => gmem_BID,
I_BUSER => gmem_BUSER);
grp_set_assign_val_fu_58 : component set_assign_val
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_set_assign_val_fu_58_ap_start,
ap_done => grp_set_assign_val_fu_58_ap_done,
ap_idle => grp_set_assign_val_fu_58_ap_idle,
ap_ready => grp_set_assign_val_fu_58_ap_ready,
m_axi_dest_AWVALID => grp_set_assign_val_fu_58_m_axi_dest_AWVALID,
m_axi_dest_AWREADY => grp_set_assign_val_fu_58_m_axi_dest_AWREADY,
m_axi_dest_AWADDR => grp_set_assign_val_fu_58_m_axi_dest_AWADDR,
m_axi_dest_AWID => grp_set_assign_val_fu_58_m_axi_dest_AWID,
m_axi_dest_AWLEN => grp_set_assign_val_fu_58_m_axi_dest_AWLEN,
m_axi_dest_AWSIZE => grp_set_assign_val_fu_58_m_axi_dest_AWSIZE,
m_axi_dest_AWBURST => grp_set_assign_val_fu_58_m_axi_dest_AWBURST,
m_axi_dest_AWLOCK => grp_set_assign_val_fu_58_m_axi_dest_AWLOCK,
m_axi_dest_AWCACHE => grp_set_assign_val_fu_58_m_axi_dest_AWCACHE,
m_axi_dest_AWPROT => grp_set_assign_val_fu_58_m_axi_dest_AWPROT,
m_axi_dest_AWQOS => grp_set_assign_val_fu_58_m_axi_dest_AWQOS,
m_axi_dest_AWREGION => grp_set_assign_val_fu_58_m_axi_dest_AWREGION,
m_axi_dest_AWUSER => grp_set_assign_val_fu_58_m_axi_dest_AWUSER,
m_axi_dest_WVALID => grp_set_assign_val_fu_58_m_axi_dest_WVALID,
m_axi_dest_WREADY => grp_set_assign_val_fu_58_m_axi_dest_WREADY,
m_axi_dest_WDATA => grp_set_assign_val_fu_58_m_axi_dest_WDATA,
m_axi_dest_WSTRB => grp_set_assign_val_fu_58_m_axi_dest_WSTRB,
m_axi_dest_WLAST => grp_set_assign_val_fu_58_m_axi_dest_WLAST,
m_axi_dest_WID => grp_set_assign_val_fu_58_m_axi_dest_WID,
m_axi_dest_WUSER => grp_set_assign_val_fu_58_m_axi_dest_WUSER,
m_axi_dest_ARVALID => grp_set_assign_val_fu_58_m_axi_dest_ARVALID,
m_axi_dest_ARREADY => grp_set_assign_val_fu_58_m_axi_dest_ARREADY,
m_axi_dest_ARADDR => grp_set_assign_val_fu_58_m_axi_dest_ARADDR,
m_axi_dest_ARID => grp_set_assign_val_fu_58_m_axi_dest_ARID,
m_axi_dest_ARLEN => grp_set_assign_val_fu_58_m_axi_dest_ARLEN,
m_axi_dest_ARSIZE => grp_set_assign_val_fu_58_m_axi_dest_ARSIZE,
m_axi_dest_ARBURST => grp_set_assign_val_fu_58_m_axi_dest_ARBURST,
m_axi_dest_ARLOCK => grp_set_assign_val_fu_58_m_axi_dest_ARLOCK,
m_axi_dest_ARCACHE => grp_set_assign_val_fu_58_m_axi_dest_ARCACHE,
m_axi_dest_ARPROT => grp_set_assign_val_fu_58_m_axi_dest_ARPROT,
m_axi_dest_ARQOS => grp_set_assign_val_fu_58_m_axi_dest_ARQOS,
m_axi_dest_ARREGION => grp_set_assign_val_fu_58_m_axi_dest_ARREGION,
m_axi_dest_ARUSER => grp_set_assign_val_fu_58_m_axi_dest_ARUSER,
m_axi_dest_RVALID => grp_set_assign_val_fu_58_m_axi_dest_RVALID,
m_axi_dest_RREADY => grp_set_assign_val_fu_58_m_axi_dest_RREADY,
m_axi_dest_RDATA => grp_set_assign_val_fu_58_m_axi_dest_RDATA,
m_axi_dest_RLAST => grp_set_assign_val_fu_58_m_axi_dest_RLAST,
m_axi_dest_RID => grp_set_assign_val_fu_58_m_axi_dest_RID,
m_axi_dest_RUSER => grp_set_assign_val_fu_58_m_axi_dest_RUSER,
m_axi_dest_RRESP => grp_set_assign_val_fu_58_m_axi_dest_RRESP,
m_axi_dest_BVALID => grp_set_assign_val_fu_58_m_axi_dest_BVALID,
m_axi_dest_BREADY => grp_set_assign_val_fu_58_m_axi_dest_BREADY,
m_axi_dest_BRESP => grp_set_assign_val_fu_58_m_axi_dest_BRESP,
m_axi_dest_BID => grp_set_assign_val_fu_58_m_axi_dest_BID,
m_axi_dest_BUSER => grp_set_assign_val_fu_58_m_axi_dest_BUSER,
data1 => grp_set_assign_val_fu_58_data1,
tmp => grp_set_assign_val_fu_58_tmp,
src => grp_set_assign_val_fu_58_src);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_set_assign_val_fu_58_ap_start_ap_start_reg assign process. --
grp_set_assign_val_fu_58_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_set_assign_val_fu_58_ap_ready)) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
data1_reg_90 <= data(31 downto 2);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, grp_set_assign_val_fu_58_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
gmem_ARADDR <= ap_const_lv32_0;
gmem_ARBURST <= ap_const_lv2_0;
gmem_ARCACHE <= ap_const_lv4_0;
gmem_ARID <= ap_const_lv1_0;
gmem_ARLEN <= ap_const_lv32_0;
gmem_ARLOCK <= ap_const_lv2_0;
gmem_ARPROT <= ap_const_lv3_0;
gmem_ARQOS <= ap_const_lv4_0;
gmem_ARREGION <= ap_const_lv4_0;
gmem_ARSIZE <= ap_const_lv3_0;
gmem_ARUSER <= ap_const_lv1_0;
gmem_ARVALID <= ap_const_logic_0;
gmem_AWADDR <= grp_set_assign_val_fu_58_m_axi_dest_AWADDR;
gmem_AWBURST <= grp_set_assign_val_fu_58_m_axi_dest_AWBURST;
gmem_AWCACHE <= grp_set_assign_val_fu_58_m_axi_dest_AWCACHE;
gmem_AWID <= grp_set_assign_val_fu_58_m_axi_dest_AWID;
gmem_AWLEN <= grp_set_assign_val_fu_58_m_axi_dest_AWLEN;
gmem_AWLOCK <= grp_set_assign_val_fu_58_m_axi_dest_AWLOCK;
gmem_AWPROT <= grp_set_assign_val_fu_58_m_axi_dest_AWPROT;
gmem_AWQOS <= grp_set_assign_val_fu_58_m_axi_dest_AWQOS;
gmem_AWREGION <= grp_set_assign_val_fu_58_m_axi_dest_AWREGION;
gmem_AWSIZE <= grp_set_assign_val_fu_58_m_axi_dest_AWSIZE;
gmem_AWUSER <= grp_set_assign_val_fu_58_m_axi_dest_AWUSER;
-- gmem_AWVALID assign process. --
gmem_AWVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_AWVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_AWVALID <= grp_set_assign_val_fu_58_m_axi_dest_AWVALID;
else
gmem_AWVALID <= ap_const_logic_0;
end if;
end process;
-- gmem_BREADY assign process. --
gmem_BREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_BREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_BREADY <= grp_set_assign_val_fu_58_m_axi_dest_BREADY;
else
gmem_BREADY <= ap_const_logic_0;
end if;
end process;
gmem_RREADY <= ap_const_logic_0;
gmem_WDATA <= grp_set_assign_val_fu_58_m_axi_dest_WDATA;
gmem_WID <= grp_set_assign_val_fu_58_m_axi_dest_WID;
gmem_WLAST <= grp_set_assign_val_fu_58_m_axi_dest_WLAST;
gmem_WSTRB <= grp_set_assign_val_fu_58_m_axi_dest_WSTRB;
gmem_WUSER <= grp_set_assign_val_fu_58_m_axi_dest_WUSER;
-- gmem_WVALID assign process. --
gmem_WVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_WVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_WVALID <= grp_set_assign_val_fu_58_m_axi_dest_WVALID;
else
gmem_WVALID <= ap_const_logic_0;
end if;
end process;
grp_set_assign_val_fu_58_ap_start <= grp_set_assign_val_fu_58_ap_start_ap_start_reg;
grp_set_assign_val_fu_58_data1 <= data1_reg_90;
grp_set_assign_val_fu_58_m_axi_dest_ARREADY <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_AWREADY <= gmem_AWREADY;
grp_set_assign_val_fu_58_m_axi_dest_BID <= gmem_BID;
grp_set_assign_val_fu_58_m_axi_dest_BRESP <= gmem_BRESP;
grp_set_assign_val_fu_58_m_axi_dest_BUSER <= gmem_BUSER;
grp_set_assign_val_fu_58_m_axi_dest_BVALID <= gmem_BVALID;
grp_set_assign_val_fu_58_m_axi_dest_RDATA <= ap_const_lv32_0;
grp_set_assign_val_fu_58_m_axi_dest_RID <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RLAST <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_RRESP <= ap_const_lv2_0;
grp_set_assign_val_fu_58_m_axi_dest_RUSER <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RVALID <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_WREADY <= gmem_WREADY;
grp_set_assign_val_fu_58_src <= val_r;
grp_set_assign_val_fu_58_tmp <= key;
set_gmem_m_axi_U_ap_dummy_ce <= ap_const_logic_1;
end behav;
|
entity tb_case02 is
end tb_case02;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_case02 is
signal sel : unsigned (3 downto 0);
signal det : std_logic_vector (1 downto 0);
begin
dut: entity work.case02
port map (sel, det);
process
begin
sel <= "0000";
wait for 1 ns;
assert det = "00" severity failure;
sel <= "0010";
wait for 1 ns;
assert det = "01" severity failure;
sel <= "0110";
wait for 1 ns;
assert det = "01" severity failure;
sel <= "1010";
wait for 1 ns;
assert det = "10" severity failure;
sel <= "1111";
wait for 1 ns;
assert det = "11" severity failure;
wait;
end process;
end behav;
|
--Copyright 2014 by Emmanuel D. Bello <emabello42@gmail.com>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_5vbn0d
-- /___/ /\ Timestamp : 04/06/2014 00:33:22
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity KeypointReader is
port ( addr : in std_logic_vector (31 downto 0);
enableIn : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (31 downto 0);
request : in std_logic;
rst : in std_logic;
busy : out std_logic;
kptCoordX : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's row possition
kptScale : out std_logic_vector(KPT_SCALE_BW-1 downto 0);
kptOctave : out std_logic_vector(KPT_OCTAVE_BW-1 downto 0);
memAddr : out std_logic_vector (31 downto 0);
read_mem : out std_logic
);
end KeypointReader;
architecture BEHAVIORAL of KeypointReader is
signal addrAux: std_logic_vector(31 downto 0) := (others => '0');
signal enableAux: std_logic := '0';
type reading_mem_states is (INIT, READING, READY);
signal s_readingMemState: reading_mem_states;
type producer_FSM_states is (INIT, REQ);
signal s_producerState: producer_FSM_states;
--signal s_memData: std_logic_vector (31 downto 0);
signal s_offset: natural range 0 to integer'HIGH;
begin
producer_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_producerState <= INIT;
busy <= '0';
else
case s_producerState is
when INIT =>
if request = '1' then
busy <= '1';
s_producerState <= REQ;
end if;
when REQ =>
if s_readingMemState = READY then
busy <= '0';
s_producerState <= INIT;
end if;
end case;
end if;
end if;
end process;
load_kpt_data: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
addrAux <= (others => '0');
elsif enableIn = '1' then
addrAux <= addr;
enableAux <= enableIn;
end if;
end if;
end process;
read_keypoints: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_readingMemState <= INIT;
kptCoordX <= (others => '0');
kptCoordY <= (others => '0');
memAddr <= (others => '0');
s_offset <= 0;
read_mem <= '0';
else
if enableAux = '1' AND s_producerState = REQ then
case s_readingMemState is
when INIT =>
memAddr <= std_logic_vector(resize(unsigned(addrAux) + s_offset,32));
read_mem <= '1';
s_offset <= s_offset + 4;
s_readingMemState <= READING;
when READING =>
read_mem <= '0';
s_readingMemState <= READY;
when READY =>
kptCoordX <= memData(KPT_COORD_BW-1 downto 0);--9 a 0
kptCoordY <= memData(2*KPT_COORD_BW-1 downto KPT_COORD_BW);--19 a 10
kptScale <= memData((2*KPT_COORD_BW+KPT_SCALE_BW)-1 downto 2*KPT_COORD_BW);--25 a 20
kptOctave <= memData((2*KPT_COORD_BW+KPT_SCALE_BW+KPT_OCTAVE_BW)-1 downto (2*KPT_COORD_BW+KPT_SCALE_BW));
s_readingMemState <= INIT;
end case;
end if;
end if;
end if;
end process;
end BEHAVIORAL;
|
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
WHEN choice =>
end generate;
GEN_LABEL : case expression generate
WHEN choice =>
end generate;
end architecture;
|
-- NEED RESULT: ARCH00274: Scope of items in corresponding block extend within corresponding block configuration passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00274
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.3.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00274(ARCH00274)
-- ENT00274_1(ARCH00274_1)
-- CONF00274
-- ENT00274_Test_Bench(ARCH00274_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
entity ENT00274 is
generic ( g10, g11, g12 : integer ) ;
port ( s10, s11, s12 : out integer ) ;
end ENT00274 ;
architecture ARCH00274 of ENT00274 is
component COMP1
end component ;
constant g8 : integer := 8 ;
begin
C1 : COMP1;
B1_1 :
block
begin
B2_2 :
block
begin
CIS1 : COMP1;
end block B2_2 ;
B2_3 :
block
begin
B3_4 :
block
begin
CIS1 : COMP1;
end block B3_4 ;
end block B2_3 ;
end block B1_1 ;
end ARCH00274 ;
entity ENT00274_1 is
generic ( g1 : integer ) ;
port ( s1 : out integer ) ;
begin
end ENT00274_1 ;
architecture ARCH00274_1 of ENT00274_1 is
begin
s1 <= g1 ;
end ARCH00274_1 ;
configuration CONF00274 of WORK.ENT00274 is
-- g8 visible all over the place !!!
for ARCH00274
for C1 : COMP1
use entity WORK.ENT00274_1 ( ARCH00274_1 )
generic map ( g8 )
port map ( s10 ) ;
end for ;
for B1_1
for B2_2
for CIS1 : COMP1
use entity WORK.ENT00274_1 ( ARCH00274_1 )
generic map ( g8 )
port map ( s11 ) ;
end for ;
end for ; -- B2_2 component
for B2_3
for B3_4
for CIS1 : COMP1 -- 3 deep
use entity WORK.ENT00274_1 ( ARCH00274_1 )
generic map ( g8 )
port map ( s12 ) ;
end for ;
end for ; -- B3_4
end for ; -- B2_3
end for ; -- B1_1
end for ;
end CONF00274 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00274_Test_Bench is
end ENT00274_Test_Bench ;
architecture ARCH00274_Test_Bench of ENT00274_Test_Bench is
begin
L1:
block
constant c1 : integer := 1 ;
constant c2 : integer := 2 ;
constant c3 : integer := 3 ;
signal s1, s2, s3 : integer ;
component UUT
end component ;
for CIS1 : UUT use configuration WORK.CONF00274
generic map ( c1, c2, c3 )
port map ( s1, s2, s3 ) ;
begin
CIS1 : UUT ;
P00274 :
process ( s1, s2, s3 )
begin
if s1 = 8 and s2 = 8 and s3 = 8 then
test_report ( "ARCH00274" ,
"Scope of items in corresponding block extend"
& " within corresponding block configuration" ,
true ) ;
end if ;
end process P00274 ;
end block L1 ;
end ARCH00274_Test_Bench ;
|
library verilog;
use verilog.vl_types.all;
entity test1 is
port(
clk : in vl_logic;
reset : in vl_logic;
enabled : in vl_logic;
\in\ : in vl_logic;
Start : in vl_logic;
Stop : in vl_logic;
sda : out vl_logic
);
end test1;
|
-- Generic SPI Slave
-- sets the output data bit on the rising edge of the clock, reads the
-- data input bit on the falling edge.
-- To use, read the data_O output on the rising edge of
-- (data_ready_O and new_data_byte_O), set data_I to something you want to send and
-- wait for a rising edge on data_ack_O before putting another one in.
-- Data sent by the slave will be aligned to 8-bit boundaries, so if you don't
-- have any data ready to send (data_ready_I is set) when a byte starts to be sent,
-- the slave will pull its output low for the duration of the byte. You have between
-- the rising edge of the SPI clock for the last bit of a byte and the next rising
-- edge to provide new data.
-- the spi_clock_I, spi_slave_select_NI and spi_mosi_I signals should be debounced
-- before being fed to this component -- you know better how much noise to expect
-- than I do.
-- Version: 20141019
-- Author: Ronald Landheer-Cieslak
-- Copyright (c) 2014 Vlinder Software
-- License: LGPL-3.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SPISlave is
port(
clock : in std_logic
; resetN : in std_logic
-- bus to the outside
; spi_clock_I : in std_logic
; spi_slave_select_NI : in std_logic
; spi_mosi_I : in std_logic
; spi_miso_O : out std_logic
-- internal bus:
-- signal to this component that data_I contains something
; data_ready_I : in std_logic
-- data to send
; data_I : in std_logic_vector(7 downto 0)
-- acknowledge we've copied the byte, so you can provide another one
; data_ack_O : out std_logic
-- indicate data_O contains valid data from the master
; data_ready_O : out std_logic
-- signal that we've changed the byte (can be used to push into a FIFO or set an SR flip-flop or something)
; new_data_byte_O : out std_logic
-- byte from the master
; data_O : out std_logic_vector(7 downto 0)
);
end entity;
architecture behavior of SPISlave is
type BitCounter is range 0 to 7;
-- driven by a SR flip-flop
signal internal_data_ready_O : std_logic := '0';
signal internal_data_ready_NO : std_logic := '1';
-- driven by p_decoder
signal set_internal_data_ready_O : std_logic := '0';
signal clear_internal_data_ready_O : std_logic := '1';
signal prev_spi_clock_I : std_logic := 'X';
signal prev_spi_slave_select_NI : std_logic := 'X';
signal internal_spi_miso_O : std_logic := 'Z';
signal input_bit_count : BitCounter := 0;
signal output_bit_count : BitCounter := 7;
signal current_input_byte : std_logic_vector(7 downto 0) := (others => 'X');
signal outputting_data : std_logic := '0';
signal current_output_byte : std_logic_vector(7 downto 0) := (others => '0');
signal current_output_byte_valid : std_logic := '0';
signal prev_data_ready_I : std_logic := 'X';
signal data_ack_on_first_seen : std_logic := '0';
signal data_ack_on_byte_change : std_logic := '0';
signal read_select : std_logic := '0';
begin
-- flip-flop for the data-ready output signal
internal_data_ready_O <= not internal_data_ready_NO or set_internal_data_ready_O;
internal_data_ready_NO <= not internal_data_ready_O or clear_internal_data_ready_O;
data_ready_O <= internal_data_ready_O;
-- let the client code know we produced a new byte
new_data_byte_O <= set_internal_data_ready_O;
-- wire-through for the MISO output
spi_miso_O <= internal_spi_miso_O;
-- acknowledge consuming a byte
data_ack_O <= data_ack_on_byte_change or data_ack_on_first_seen;
p_decoder : process(clock, resetN)
begin
if resetN = '0' then
prev_spi_clock_I <= 'X';
prev_spi_slave_select_NI <= 'X';
clear_internal_data_ready_O <= '1';
data_O <= (others => 'X');
internal_spi_miso_O <= 'Z';
set_internal_data_ready_O <= '0';
current_input_byte <= (others => 'X');
input_bit_count <= 0;
output_bit_count <= 7;
outputting_data <= '0';
current_output_byte <= (others => '0');
current_output_byte_valid <= '0';
prev_data_ready_I <= 'X';
data_ack_on_first_seen <= '0';
data_ack_on_byte_change <= '0';
read_select <= '0';
else
if rising_edge(clock) then
-- detect a falling edge of the spi_slave_select_NI input
if prev_spi_slave_select_NI = '1' and spi_slave_select_NI = '0' then
clear_internal_data_ready_O <= '1';
-- counters should already be OK at this point: either because we're coming out of a complete reset or because we have previously been deselected
-- on a rising edge (when we're deselected) reset the counters so we can't get desynchronized if we get deselected in the middle of a byte
elsif prev_spi_slave_select_NI = '0' and spi_slave_select_NI = '1' then
output_bit_count <= 7;
input_bit_count <= 0;
read_select <= '0';
else
clear_internal_data_ready_O <= '0';
end if;
prev_spi_slave_select_NI <= spi_slave_select_NI;
-- detect new output data
if prev_data_ready_I = '0'and data_ready_I = '1' then
current_output_byte <= data_I;
current_output_byte_valid <= '1';
data_ack_on_first_seen <= '1';
else
data_ack_on_first_seen <= '0';
end if;
prev_data_ready_I <= data_ready_I;
-- detect edges of the input clock
if spi_slave_select_NI = '0' then -- we are selected
if prev_spi_clock_I = '0' and spi_clock_I = '1' then -- rising edge of the clock - write a bit if we have any
-- start outputting data if we are at the start of a byte boundary, or if we were already outputting a byte
if current_output_byte_valid = '1' and (outputting_data = '1' or output_bit_count = 7) then
internal_spi_miso_O <= current_output_byte(7);
outputting_data <= '1';
else
internal_spi_miso_O <= '0';
outputting_data <= '0';
end if;
-- if we just decided to output the last bit of the byte, load the next byte if we have one, or invalidate the current byte if we don't.
-- if we do load a new byte, we should acknowledge it.
-- if we're not at the last bit, just shift a bit out of the register
if (output_bit_count = 0) then
-- we should, of course, only take the byte if we've output the current one. Otherwise, we should leave it there until we do.
if outputting_data = '1' then
current_output_byte <= data_I;
current_output_byte_valid <= data_ready_I;
data_ack_on_byte_change <= '1';
else
data_ack_on_byte_change <= '0';
end if;
output_bit_count <= 7;
else
-- shift out a bit
data_ack_on_byte_change <= '0';
output_bit_count <= output_bit_count - 1;
current_output_byte <= current_output_byte(6 downto 0) & '0';
end if;
set_internal_data_ready_O <= '0';
read_select <= '1';
elsif read_select = '1' and prev_spi_clock_I = '1' and spi_clock_I = '0' then -- falling edge of the clock - read a bit
if input_bit_count = 7 then
set_internal_data_ready_O <= '1';
data_O <= current_input_byte(6 downto 0) & spi_mosi_I;
input_bit_count <= 0;
else
set_internal_data_ready_O <= '0';
input_bit_count <= input_bit_count + 1;
end if;
current_input_byte <= current_input_byte(6 downto 0) & spi_mosi_I;
else
set_internal_data_ready_O <= '0';
end if;
else
internal_spi_miso_O <= 'Z';
set_internal_data_ready_O <= '0';
end if;
prev_spi_clock_I <= spi_clock_I;
end if;
end if;
end process;
end architecture;
|
-- Testbench of DDS Frequency Synthesizer
--
-- Copyright (C) 2009 Martin Kumm
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.dds_synthesizer_pkg.all;
use work.sine_lut_pkg.all;
entity dds_synthesizer_tb is
generic(
clk_period : time := 10 ns;
ftw_width : integer := 32
);
end dds_synthesizer_tb;
architecture dds_synthesizer_tb_arch of dds_synthesizer_tb is
signal clk,rst : std_logic := '0';
signal ftw : std_logic_vector(ftw_width-1 downto 0);
signal init_phase : std_logic_vector(phase_width-1 downto 0);
signal phase_out : std_logic_vector(phase_width-1 downto 0);
signal ampl_out : std_logic_vector(ampl_width-1 downto 0);
begin
dds_synth: dds_synthesizer
generic map(
ftw_width => ftw_width
)
port map(
clk_i => clk,
rst_i => rst,
ftw_i => ftw,
phase_i => init_phase,
phase_o => phase_out,
ampl_o => ampl_out
);
init_phase <= (others => '0');
ftw <= conv_std_logic_vector(2147483,ftw_width); --20us period @ 100MHz, ftw_width=32
clk <= not clk after clk_period/2;
rst <= '1','0' after 2*clk_period;
end dds_synthesizer_tb_arch; |
-- Testbench of DDS Frequency Synthesizer
--
-- Copyright (C) 2009 Martin Kumm
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
-- Package Definition
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
use work.dds_synthesizer_pkg.all;
use work.sine_lut_pkg.all;
entity dds_synthesizer_tb is
generic(
clk_period : time := 10 ns;
ftw_width : integer := 32
);
end dds_synthesizer_tb;
architecture dds_synthesizer_tb_arch of dds_synthesizer_tb is
signal clk,rst : std_logic := '0';
signal ftw : std_logic_vector(ftw_width-1 downto 0);
signal init_phase : std_logic_vector(phase_width-1 downto 0);
signal phase_out : std_logic_vector(phase_width-1 downto 0);
signal ampl_out : std_logic_vector(ampl_width-1 downto 0);
begin
dds_synth: dds_synthesizer
generic map(
ftw_width => ftw_width
)
port map(
clk_i => clk,
rst_i => rst,
ftw_i => ftw,
phase_i => init_phase,
phase_o => phase_out,
ampl_o => ampl_out
);
init_phase <= (others => '0');
ftw <= conv_std_logic_vector(2147483,ftw_width); --20us period @ 100MHz, ftw_width=32
clk <= not clk after clk_period/2;
rst <= '1','0' after 2*clk_period;
end dds_synthesizer_tb_arch; |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_3 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_3 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable data : UNSIGNED(7 downto 0);
variable mini : UNSIGNED(7 downto 0);
variable diff : UNSIGNED(7 downto 0);
variable mult : UNSIGNED(23 downto 0);
variable beta : UNSIGNED(15 downto 0);
begin
data := UNSIGNED( INPUT_1(7 downto 0) );
mini := UNSIGNED( INPUT_2(7 downto 0) );
beta := UNSIGNED( INPUT_2(31 downto 16) );
diff := data - mini; -- 8
mult := diff * beta; -- 24
OUTPUT_1(7 downto 0) <= std_logic_vector(mult(15 downto 8));
OUTPUT_1(31 downto 8) <= (others => '0');
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_3 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_3 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable data : UNSIGNED(7 downto 0);
variable mini : UNSIGNED(7 downto 0);
variable diff : UNSIGNED(7 downto 0);
variable mult : UNSIGNED(23 downto 0);
variable beta : UNSIGNED(15 downto 0);
begin
data := UNSIGNED( INPUT_1(7 downto 0) );
mini := UNSIGNED( INPUT_2(7 downto 0) );
beta := UNSIGNED( INPUT_2(31 downto 16) );
diff := data - mini; -- 8
mult := diff * beta; -- 24
OUTPUT_1(7 downto 0) <= std_logic_vector(mult(15 downto 8));
OUTPUT_1(31 downto 8) <= (others => '0');
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_3 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_3 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable data : UNSIGNED(7 downto 0);
variable mini : UNSIGNED(7 downto 0);
variable diff : UNSIGNED(7 downto 0);
variable mult : UNSIGNED(23 downto 0);
variable beta : UNSIGNED(15 downto 0);
begin
data := UNSIGNED( INPUT_1(7 downto 0) );
mini := UNSIGNED( INPUT_2(7 downto 0) );
beta := UNSIGNED( INPUT_2(31 downto 16) );
diff := data - mini; -- 8
mult := diff * beta; -- 24
OUTPUT_1(7 downto 0) <= std_logic_vector(mult(15 downto 8));
OUTPUT_1(31 downto 8) <= (others => '0');
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_3 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_3 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable data : UNSIGNED(7 downto 0);
variable mini : UNSIGNED(7 downto 0);
variable diff : UNSIGNED(7 downto 0);
variable mult : UNSIGNED(23 downto 0);
variable beta : UNSIGNED(15 downto 0);
begin
data := UNSIGNED( INPUT_1(7 downto 0) );
mini := UNSIGNED( INPUT_2(7 downto 0) );
beta := UNSIGNED( INPUT_2(31 downto 16) );
diff := data - mini; -- 8
mult := diff * beta; -- 24
OUTPUT_1(7 downto 0) <= std_logic_vector(mult(15 downto 8));
OUTPUT_1(31 downto 8) <= (others => '0');
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
-- NEED RESULT: ARCH00625: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00625.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00625: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00625: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00625: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00625
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00625(ARCH00625)
-- ENT00625_Test_Bench(ARCH00625_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00625 is
end ENT00625 ;
--
--
architecture ARCH00625 of ENT00625 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
procedure P1
(signal s_st_rec3 : in st_rec3 ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00625" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00625.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00625" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00625" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00625" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00625" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec3_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_rec3 ,
st_rec3_select ,
s_st_rec3_savt ,
chk_st_rec3 ,
s_st_rec3_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f3(lowb,true) <= transport
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when 1,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 2,
--
c_st_rec3_1.f3(lowb,true) after 5 ns when 3 ;
--
end ARCH00625 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00625_Test_Bench is
end ENT00625_Test_Bench ;
--
--
architecture ARCH00625_Test_Bench of ENT00625_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00625 ( ARCH00625 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00625_Test_Bench ;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare10.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare10 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare10;
ARCHITECTURE SYN OF lpm_compare10 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END COMPONENT;
BEGIN
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 24
)
PORT MAP (
dataa => dataa,
datab => datab,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "24"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 24 0 INPUT NODEFVAL "dataa[23..0]"
-- Retrieval info: USED_PORT: datab 0 0 24 0 INPUT NODEFVAL "datab[23..0]"
-- Retrieval info: CONNECT: @dataa 0 0 24 0 dataa 0 0 24 0
-- Retrieval info: CONNECT: @datab 0 0 24 0 datab 0 0 24 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare10_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use IEEE.NUMERIC_bit.all;
package pcie is
type pci_ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(1 downto 0);
end record;
type pci_ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
type data_vector_to_check is array (natural range <>) of std_logic_vector(31 downto 0);
component pciedma is
generic (
fabtech : integer := DEFFABTECH;
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 5; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#A00#;
hmask : integer := 16#FFF#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
pcie_bar_mask : integer := 16#ffe#;
lane_width : integer := 1;
Gen : integer := 1 );
port(
rst : in std_logic;
clk : in std_logic;
sys_clk_p : in std_logic;--check needed
sys_clk_n : in std_logic;--
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic_vector(lane_width-1 downto 0);
pci_exp_txn : out std_logic_vector(lane_width-1 downto 0);
pci_exp_rxp : in std_logic_vector(lane_width-1 downto 0);
pci_exp_rxn : in std_logic_vector(lane_width-1 downto 0);
-- trn_clk : out std_logic;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pcie_master_target_virtex is
generic (
fabtech : integer := DEFFABTECH;
hmstndx : integer := 0;
hslvndx : integer := 0;
abits : integer := 21;
device_id : integer := 9; -- PCIE device ID
vendor_id : integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask : integer := 16#FFE#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr : integer := 0;
hmask : integer := 16#fff#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
Master : integer := 1;
lane_width : integer := 1;
Gen : integer := 1
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic_vector(lane_width-1 downto 0);
pci_exp_txn : out std_logic_vector(lane_width-1 downto 0);
pci_exp_rxp : in std_logic_vector(lane_width-1 downto 0);
pci_exp_rxn : in std_logic_vector(lane_width-1 downto 0);
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pcie_master_fifo_virtex is
generic (
fabtech: integer := DEFFABTECH;
memtech: integer := DEFMEMTECH;
dmamst: integer := NAHBMST;
fifodepth: integer := 5; -- FIFO depth
hslvndx: integer := 0;
abits: integer := 21;
device_id: integer := 9; -- PCIE device ID
vendor_id: integer := 16#10EE#; -- PCIE vendor ID
pcie_bar_mask: integer := 16#FFE#;
nsync: integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
haddr: integer := 16#A00#;
hmask: integer := 16#fff#;
pindex: integer := 0;
paddr: integer := 0;
pmask: integer := 16#fff#;
lane_width: integer := 1;
Gen: integer := 1
);
port(
rst : in std_logic;
clk : in std_logic;
-- System Interface
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_reset_n : in std_logic;
-- PCI Express Fabric Interface
pci_exp_txp : out std_logic_vector(lane_width-1 downto 0);
pci_exp_txn : out std_logic_vector(lane_width-1 downto 0);
pci_exp_rxp : in std_logic_vector(lane_width-1 downto 0);
pci_exp_rxn : in std_logic_vector(lane_width-1 downto 0);
-- AMBA Interface
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
function buffer_available(fabtech : integer;trn_tbuf_av : std_logic_vector(5 downto 0))return std_logic;
function conv_to_bitvector(Gen : in integer;width : in integer)return bit_vector;
function fn_usr_clk_frequency(lane_width : in integer;Gen : in integer) return integer;
function fn_TARGET_LINK_SPEED(lane_width : in integer;Gen : in integer) return bit_vector;
end;
package body pcie is
function buffer_available(fabtech : integer;
trn_tbuf_av : std_logic_vector(5 downto 0))
return std_logic is
variable s: std_logic;
begin
if fabtech = virtex5 then
if trn_tbuf_av(3 downto 0) = "1111" then
s := '0';
else
s := '1';
end if;
elsif fabtech = virtex6 then
if trn_tbuf_av < "000010" then
s := '1';
else
s := '0';
end if;
else
s := '1';
end if;
return s;
end function;
function conv_to_bitvector(Gen : in integer;width : in integer)
return bit_vector is
variable result : bit_vector(width-1 downto 0);
begin
result:=bit_vector(to_unsigned(Gen,width));
return result;
end function;
function fn_usr_clk_frequency(lane_width : in integer;Gen : in integer)
return integer is
variable result : integer;
begin
result := 1;
case lane_width is
when 1 =>
result := 1;
when 2 =>
if Gen = 1 then
result := 1;
else
result := 2;
end if;
when 4 =>
if Gen = 1 then
result := 2;
else
result := 3;
end if;
when 8 =>
result := 3;
when others =>
end case;
return result;
end function;
function fn_TARGET_LINK_SPEED(lane_width : in integer;Gen : in integer)
return bit_vector is
variable result : bit_vector(3 downto 0);
begin
result := x"0";
case lane_width is
when 1 =>
if Gen = 1 then
result := x"0";
else
result := x"2";
end if;
when 2 =>
if Gen = 1 then
result := x"0";
else
result := x"2";
end if;
when 4 =>
if Gen = 1 then
result := x"0";
else
result := x"2";
end if;
when 8 =>
result := x"0";
when others =>
end case;
return result;
end function;
end;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu32 is
port(
ia : in std_logic_vector(31 downto 0);
ib : in std_logic_vector(31 downto 0);
shamt : in std_logic_vector(4 downto 0);
shdir : in std_logic;
C : out std_logic;
control : in std_logic_vector(3 downto 0);
output : out std_logic_vector(31 downto 0);
Z : out std_logic;
S : out std_logic;
V : out std_logic
);
end alu32;
architecture arch of alu32 is
signal temp_c : std_logic_vector(32 downto 0);
signal temp_o : std_logic_vector(31 downto 0);
signal temp_less: std_logic_vector(31 downto 0);
signal temp_out : std_logic_vector(31 downto 0);
signal temp_shift : std_logic_vector(31 downto 0);
signal sh_en : std_logic;
begin
alu: for i in 0 to 30 generate --generate 32 1-bit adders for alu32 entity
alu: entity work.alu1
port map(
ia => ia(i),
ib => ib(i),
less => temp_less(i),
cout=> temp_c(i+1),-- Cin will be previous value temp signal
cin => temp_c(i), -- cout will feed into cin
control => control,
output => temp_o(i)
);
end generate;
alu32: entity work.alu1_last
port map(
ia => ia(31),
ib => ib(31),
less => temp_less(31),
cout=> temp_c(32),-- Cin will be previous value temp signal
cin => temp_c(31), -- cout will feed into cin
control => control,
slt_en => temp_less(0),
output => temp_o(31)
);
shift: entity work.shifter
port map(
ib => ib,
shdir => shdir,
shamt => shamt,
q => temp_shift
);
mux: entity work.mux_gen
generic map(width => 32)
port map(
in0 => temp_o,
in1 => temp_shift,
sel => sh_en,
output => temp_out
);
temp_c(0) <= control(2); -- Set cin to first adder to 0. Leaving it blank will result in an 'X' for sum(0)
C <= temp_c(32);
-- Z flag
Z <= not (temp_out(31) or temp_out(30) or temp_out(29) or temp_out(28) or temp_out(27) or temp_out(26) or
temp_out(25) or temp_out(24) or temp_out(23) or temp_out(22) or temp_out(21) or temp_out(20) or
temp_out(19) or temp_out(18) or temp_out(17) or temp_out(16) or temp_out(15) or temp_out(14) or
temp_out(13) or temp_out(12) or temp_out(11) or temp_out(10) or temp_out(9) or temp_out(8)or
temp_out(7) or temp_out(6) or temp_out(5) or temp_out(4) or temp_out(3) or temp_out(2) or temp_out(1) or
temp_out(0));
-- S flag
S <= temp_out(31);
-- V flag
V <= (temp_c(32) xor temp_c(31));
-- shift enable
sh_en <= (not control(3) and not control(2) and control(1) and control(0));
temp_less(31 downto 1) <= (others => '0');
output <= temp_out;
end arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2644.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02644ent IS
END c13s03b01x00p02n01i02644ent;
ARCHITECTURE c13s03b01x00p02n01i02644arch OF c13s03b01x00p02n01i02644ent IS
-- ERROR: name of the constant contains 2 consecutive underlines
constant te__st: character:='A'; --failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02644 - Consecutive underlines are not allowed in an identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02644arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2644.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02644ent IS
END c13s03b01x00p02n01i02644ent;
ARCHITECTURE c13s03b01x00p02n01i02644arch OF c13s03b01x00p02n01i02644ent IS
-- ERROR: name of the constant contains 2 consecutive underlines
constant te__st: character:='A'; --failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02644 - Consecutive underlines are not allowed in an identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02644arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2644.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02644ent IS
END c13s03b01x00p02n01i02644ent;
ARCHITECTURE c13s03b01x00p02n01i02644arch OF c13s03b01x00p02n01i02644ent IS
-- ERROR: name of the constant contains 2 consecutive underlines
constant te__st: character:='A'; --failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02644 - Consecutive underlines are not allowed in an identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02644arch;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY SimpleUnitReanamedPort0 IS
PORT(
a_in_hdl : IN STD_LOGIC;
b : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleUnitReanamedPort0 IS
BEGIN
b <= a_in_hdl;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Q8_4_ABS is
port (
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
end;
architecture rtl of Q8_4_ABS is
begin
-------------------------------------------------------------------------
PROCESS (INPUT_1)
VARIABLE temp : SIGNED(7 downto 0);
begin
temp := abs( SIGNED( INPUT_1(7 downto 0) ) );
OUTPUT_1 <= STD_LOGIC_VECTOR( RESIZE(temp, 32) );
END PROCESS;
-------------------------------------------------------------------------
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
a_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce1 : OUT STD_LOGIC;
a_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce1 : OUT STD_LOGIC;
b_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
prod_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce0 : OUT STD_LOGIC;
prod_we0 : OUT STD_LOGIC;
prod_d0 : OUT STD_LOGIC_VECTOR (15 downto 0);
prod_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce1 : OUT STD_LOGIC;
prod_we1 : OUT STD_LOGIC;
prod_d1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of matrix_mult is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"matrix_mult,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=5.415000,HLS_SYN_LAT=27,HLS_SYN_TPT=13,HLS_SYN_MEM=0,HLS_SYN_DSP=75,HLS_SYN_FF=9729,HLS_SYN_LUT=5027}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000010";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000100";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (12 downto 0) := "0000000001000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (12 downto 0) := "0000001000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (12 downto 0) := "0000010000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (12 downto 0) := "0000100000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (12 downto 0) := "0001000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (12 downto 0) := "0010000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (12 downto 0) := "0100000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_state13_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_state26_pp0_stage12_iter1 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal reg_764 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state2_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state15_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state28_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state3_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state16_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state5_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state18_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state10_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_state23_pp0_stage9_iter1 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal reg_769 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state4_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state17_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state9_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_state22_pp0_stage8_iter1 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state12_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_state25_pp0_stage11_iter1 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal reg_774 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_779 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state6_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state19_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal reg_784 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_788 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state8_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state21_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state11_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_state24_pp0_stage10_iter1 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal reg_792 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_796 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_800 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state27_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal tmp_0_0_3_fu_805_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_3_reg_1832 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_3_fu_809_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_3_reg_1841 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_3_fu_819_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_3_reg_1850 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_3_fu_829_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_3_reg_1859 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_3_fu_845_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_3_reg_1888 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_3_fu_854_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_3_reg_1897 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_3_fu_873_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_3_reg_1926 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_3_fu_887_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_3_reg_1935 : STD_LOGIC_VECTOR (15 downto 0);
signal b_load_15_reg_1964 : STD_LOGIC_VECTOR (7 downto 0);
signal b_load_20_reg_1969 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_313_0_3_fu_913_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_3_reg_1974 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state7_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state20_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal grp_fu_813_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_0_3_reg_2003 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_4_fu_922_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_4_reg_2008 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_4_fu_926_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_4_reg_2017 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_823_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_1_3_reg_2026 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_4_fu_930_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_4_reg_2031 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_833_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_0_3_reg_2040 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_4_fu_934_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_4_reg_2045 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_839_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_1_3_reg_2054 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_849_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_2_3_reg_2079 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_4_fu_954_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_4_reg_2084 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_858_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_3_3_reg_2093 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_4_fu_958_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_4_reg_2098 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_863_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_2_3_reg_2107 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_868_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_3_3_reg_2112 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_4_fu_962_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_4_reg_2117 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_3_fu_966_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_3_reg_2126 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp75_fu_990_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp75_reg_2155 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_fu_994_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_reg_2164 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1340_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp2_reg_2173 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_fu_1004_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_reg_2178 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1347_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp5_reg_2187 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_fu_1014_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_reg_2192 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_877_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_4_3_reg_2201 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_4_fu_1024_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_4_reg_2206 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1354_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp17_reg_2215 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1361_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp20_reg_2220 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_882_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_4_3_reg_2225 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_891_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_0_3_reg_2230 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_896_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_1_3_reg_2235 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_4_fu_1028_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_4_reg_2240 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_2_fu_1036_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_2_reg_2269 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_2_fu_1040_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_2_reg_2278 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1368_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp8_reg_2287 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_fu_1044_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_reg_2292 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1374_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp11_reg_2301 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_fu_1052_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_reg_2306 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_1060_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_reg_2315 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1380_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp23_reg_2324 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1386_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp26_reg_2329 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1392_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp32_reg_2334 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1398_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp35_reg_2339 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_901_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_2_3_reg_2344 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_905_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_3_3_reg_2349 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_909_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_4_3_reg_2354 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_917_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_0_3_reg_2359 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_2_fu_1074_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_2_reg_2384 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1404_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp14_reg_2393 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_2_fu_1078_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_2_reg_2398 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1410_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp29_reg_2407 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_1094_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_reg_2412 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1416_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp38_reg_2421 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1421_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp41_reg_2426 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1426_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp44_reg_2431 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1432_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp47_reg_2436 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_938_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_1_3_reg_2441 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_942_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_2_3_reg_2446 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_946_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_3_3_reg_2451 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_950_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_4_3_reg_2456 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_4_fu_1103_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_4_reg_2461 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_1_fu_1107_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_1_reg_2490 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_1_fu_1111_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_1_reg_2499 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1438_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp1_reg_2508 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_1_fu_1115_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_1_reg_2513 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_1_fu_1119_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_1_reg_2522 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_2_fu_1123_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_2_reg_2531 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1445_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp50_reg_2540 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1450_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp53_reg_2545 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1455_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp56_reg_2550 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1460_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp59_reg_2555 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_970_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_0_3_reg_2560 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_975_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_1_3_reg_2565 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_980_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_2_3_reg_2570 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_985_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_3_3_reg_2575 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_998_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_reg_2590 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1008_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_1_reg_2595 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1465_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp4_reg_2600 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1018_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_2_reg_2605 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_1_fu_1143_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_1_reg_2610 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_2_fu_1147_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_2_reg_2619 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_1_fu_1151_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_1_reg_2628 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_1_fu_1155_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_1_reg_2637 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1471_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp16_reg_2646 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_fu_1159_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_reg_2651 : STD_LOGIC_VECTOR (15 downto 0);
signal a_load_17_reg_2660 : STD_LOGIC_VECTOR (7 downto 0);
signal a_load_21_reg_2665 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1477_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp62_reg_2670 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1483_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp65_reg_2675 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1489_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp68_reg_2680 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1495_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp71_reg_2685 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1032_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_4_3_reg_2690 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1501_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_reg_2695 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1508_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_reg_2700 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1515_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp6_reg_2705 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1522_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp7_reg_2710 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1047_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_3_reg_2715 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1055_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_4_reg_2720 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_2_fu_1183_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_2_reg_2725 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1064_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_reg_2734 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1069_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_1_reg_2739 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1528_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp19_reg_2744 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_1_fu_1187_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_1_reg_2749 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_fu_1195_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_reg_2758 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1533_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp74_reg_2767 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_0_4_fu_1214_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_3_0_0_4_fu_1214_p2 : signal is "no";
signal tmp_3_0_0_4_reg_2772 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_1_4_fu_1218_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_1_4_fu_1218_p2 : signal is "no";
signal tmp_3_0_1_4_reg_2777 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_2_4_fu_1222_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_2_4_fu_1222_p2 : signal is "no";
signal tmp_3_0_2_4_reg_2782 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1538_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp9_reg_2787 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1544_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp10_reg_2792 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1550_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp12_reg_2797 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1556_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp15_reg_2802 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1562_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp18_reg_2807 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1082_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_2_reg_2812 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1568_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp22_reg_2817 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1086_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_3_reg_2822 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1090_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_4_reg_2827 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1098_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_reg_2832 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_2_fu_1226_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_2_reg_2837 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_3_4_fu_1238_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_3_4_fu_1238_p2 : signal is "no";
signal tmp_3_0_3_4_reg_2846 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1573_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp13_reg_2851 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_0_4_fu_1242_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_0_4_fu_1242_p2 : signal is "no";
signal tmp_3_1_0_4_reg_2856 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_1_4_fu_1246_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_1_4_fu_1246_p2 : signal is "no";
signal tmp_3_1_1_4_reg_2861 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1579_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp21_reg_2866 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1584_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp24_reg_2871 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1589_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp25_reg_2876 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1594_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp27_reg_2881 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1599_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp30_reg_2886 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1127_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_1_reg_2891 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1131_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_2_reg_2896 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1135_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_3_reg_2901 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1139_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_4_reg_2906 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_1_fu_1250_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_1_reg_2911 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_4_4_fu_1254_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_4_4_fu_1254_p2 : signal is "no";
signal tmp_3_0_4_4_reg_2920 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_2_4_fu_1258_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_2_4_fu_1258_p2 : signal is "no";
signal tmp_3_1_2_4_reg_2925 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_3_4_fu_1262_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_3_4_fu_1262_p2 : signal is "no";
signal tmp_3_1_3_4_reg_2930 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1605_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp28_reg_2935 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1610_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp31_reg_2940 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1616_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp33_reg_2945 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1621_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp36_reg_2950 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1626_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp39_reg_2955 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1631_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp42_reg_2960 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1163_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_reg_2965 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1168_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_1_reg_2970 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1173_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_2_reg_2975 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1178_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_3_reg_2980 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_1_fu_1266_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_1_reg_2985 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_4_4_fu_1269_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_4_4_fu_1269_p2 : signal is "no";
signal tmp_3_1_4_4_reg_2994 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_0_4_fu_1273_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_0_4_fu_1273_p2 : signal is "no";
signal tmp_3_2_0_4_reg_2999 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1636_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp34_reg_3004 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1641_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp37_reg_3009 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_2_fu_1277_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_2_reg_3014 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1646_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp45_reg_3023 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1652_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp48_reg_3028 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1658_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp51_reg_3033 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1664_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp54_reg_3038 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1191_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_4_reg_3043 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1199_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_reg_3048 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1204_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_1_reg_3053 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1209_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_2_reg_3058 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_1_4_fu_1280_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_1_4_fu_1280_p2 : signal is "no";
signal tmp_3_2_1_4_reg_3063 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_2_4_fu_1284_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_2_4_fu_1284_p2 : signal is "no";
signal tmp_3_2_2_4_reg_3068 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1670_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp40_reg_3073 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1675_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp43_reg_3078 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1680_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp57_reg_3083 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_2_fu_1288_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1685_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp60_reg_3097 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1691_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp63_reg_3102 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1697_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp66_reg_3107 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1230_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_3_reg_3112 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1234_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_4_reg_3117 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_3_4_fu_1292_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_3_4_fu_1292_p2 : signal is "no";
signal tmp_3_2_3_4_reg_3122 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_4_4_fu_1296_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_4_4_fu_1296_p2 : signal is "no";
signal tmp_3_2_4_4_reg_3127 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1703_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp46_reg_3132 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1709_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp49_reg_3137 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1715_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp52_reg_3142 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1721_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp55_reg_3147 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1727_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp69_reg_3152 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1732_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp72_reg_3157 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_0_4_fu_1300_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_0_4_fu_1300_p2 : signal is "no";
signal tmp_3_3_0_4_reg_3162 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_1_4_fu_1304_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_1_4_fu_1304_p2 : signal is "no";
signal tmp_3_3_1_4_reg_3167 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_2_4_fu_1308_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_2_4_fu_1308_p2 : signal is "no";
signal tmp_3_3_2_4_reg_3172 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_3_4_fu_1312_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_3_4_fu_1312_p2 : signal is "no";
signal tmp_3_3_3_4_reg_3177 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1737_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp58_reg_3182 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1742_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp61_reg_3187 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1748_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp64_reg_3192 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1754_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp67_reg_3197 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1760_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp70_reg_3202 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1766_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp73_reg_3207 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_4_4_fu_1316_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_4_4_fu_1316_p2 : signal is "no";
signal tmp_3_3_4_4_reg_3212 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_0_4_fu_1320_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_0_4_fu_1320_p2 : signal is "no";
signal tmp_3_4_0_4_reg_3217 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_1_4_fu_1324_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_1_4_fu_1324_p2 : signal is "no";
signal tmp_3_4_1_4_reg_3222 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_2_4_fu_1328_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_2_4_fu_1328_p2 : signal is "no";
signal tmp_3_4_2_4_reg_3227 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_3_4_fu_1332_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_3_4_fu_1332_p2 : signal is "no";
signal tmp_3_4_3_4_reg_3232 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_4_4_fu_1336_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_4_4_fu_1336_p2 : signal is "no";
signal tmp_3_4_4_4_reg_3237 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_enable_reg_pp0_iter0_reg : STD_LOGIC := '0';
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal grp_fu_813_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_813_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_823_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_823_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_833_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_833_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_839_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_839_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_849_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_849_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_858_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_858_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_863_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_863_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_868_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_868_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_877_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_877_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_882_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_882_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_891_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_891_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_896_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_896_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_901_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_901_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_905_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_905_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_909_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_909_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_917_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_938_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_938_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_942_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_942_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_946_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_946_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_950_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_950_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_970_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_970_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_975_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_975_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_980_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_980_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_985_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_985_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_998_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1008_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1018_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1032_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1032_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1047_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1055_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1064_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1064_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1069_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1069_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1082_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1082_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1086_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1086_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1090_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1090_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1098_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1127_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1127_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1131_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1131_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1135_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1135_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1139_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1139_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1163_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1163_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1168_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1168_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1173_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1173_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1178_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1178_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1191_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1191_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1199_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1199_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1204_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1204_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1209_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1209_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1230_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1230_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1234_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1234_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1340_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1340_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1347_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1347_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1354_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1354_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1361_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1361_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1368_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1368_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1374_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1374_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1380_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1380_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1386_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1386_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1392_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1392_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1398_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1398_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1404_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1404_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1410_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1410_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1416_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1416_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1421_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1421_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1426_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1426_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1432_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1445_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1445_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1450_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1450_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1455_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1455_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1460_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1460_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1465_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1471_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1477_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1477_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1483_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1483_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1489_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1489_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1495_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1495_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1501_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1508_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1515_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1522_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1528_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1528_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1533_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1533_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1538_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1544_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1550_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1556_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1556_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1562_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1562_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1568_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1568_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1573_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1579_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1579_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1584_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1584_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1589_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1589_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1594_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1594_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1599_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1605_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1605_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1610_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1616_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1616_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1621_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1621_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1626_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1626_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1631_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1631_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1636_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1636_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1641_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1641_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1646_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1646_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1652_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1652_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1658_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1658_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1664_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1664_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1670_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1670_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1675_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1675_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1680_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1680_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1685_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1685_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1691_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1691_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1697_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1697_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1703_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1703_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1709_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1709_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1715_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1715_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1721_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1721_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1727_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1727_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1732_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1732_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1737_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1737_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1742_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1742_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1748_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1748_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1754_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1754_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1760_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1760_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1766_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1766_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (12 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_idle_pp0_1to2 : STD_LOGIC;
signal ap_idle_pp0_0to1 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_enable_pp0 : STD_LOGIC;
component matrix_mult_mul_8bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mdEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
matrix_mult_mul_8bkb_U0 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_813_p0,
din1 => grp_fu_813_p1,
ce => ap_const_logic_1,
dout => grp_fu_813_p2);
matrix_mult_mul_8bkb_U1 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_823_p0,
din1 => grp_fu_823_p1,
ce => ap_const_logic_1,
dout => grp_fu_823_p2);
matrix_mult_mul_8bkb_U2 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_833_p0,
din1 => grp_fu_833_p1,
ce => ap_const_logic_1,
dout => grp_fu_833_p2);
matrix_mult_mul_8bkb_U3 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_839_p0,
din1 => grp_fu_839_p1,
ce => ap_const_logic_1,
dout => grp_fu_839_p2);
matrix_mult_mul_8bkb_U4 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_849_p0,
din1 => grp_fu_849_p1,
ce => ap_const_logic_1,
dout => grp_fu_849_p2);
matrix_mult_mul_8bkb_U5 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_858_p0,
din1 => grp_fu_858_p1,
ce => ap_const_logic_1,
dout => grp_fu_858_p2);
matrix_mult_mul_8bkb_U6 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_863_p0,
din1 => grp_fu_863_p1,
ce => ap_const_logic_1,
dout => grp_fu_863_p2);
matrix_mult_mul_8bkb_U7 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_868_p0,
din1 => grp_fu_868_p1,
ce => ap_const_logic_1,
dout => grp_fu_868_p2);
matrix_mult_mul_8bkb_U8 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_877_p0,
din1 => grp_fu_877_p1,
ce => ap_const_logic_1,
dout => grp_fu_877_p2);
matrix_mult_mul_8bkb_U9 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_882_p0,
din1 => grp_fu_882_p1,
ce => ap_const_logic_1,
dout => grp_fu_882_p2);
matrix_mult_mul_8bkb_U10 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_891_p0,
din1 => grp_fu_891_p1,
ce => ap_const_logic_1,
dout => grp_fu_891_p2);
matrix_mult_mul_8bkb_U11 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_896_p0,
din1 => grp_fu_896_p1,
ce => ap_const_logic_1,
dout => grp_fu_896_p2);
matrix_mult_mul_8bkb_U12 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_901_p0,
din1 => grp_fu_901_p1,
ce => ap_const_logic_1,
dout => grp_fu_901_p2);
matrix_mult_mul_8bkb_U13 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_905_p0,
din1 => grp_fu_905_p1,
ce => ap_const_logic_1,
dout => grp_fu_905_p2);
matrix_mult_mul_8bkb_U14 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_909_p0,
din1 => grp_fu_909_p1,
ce => ap_const_logic_1,
dout => grp_fu_909_p2);
matrix_mult_mul_8bkb_U15 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_917_p0,
din1 => reg_779,
ce => ap_const_logic_1,
dout => grp_fu_917_p2);
matrix_mult_mul_8bkb_U16 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_938_p0,
din1 => grp_fu_938_p1,
ce => ap_const_logic_1,
dout => grp_fu_938_p2);
matrix_mult_mul_8bkb_U17 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_942_p0,
din1 => grp_fu_942_p1,
ce => ap_const_logic_1,
dout => grp_fu_942_p2);
matrix_mult_mul_8bkb_U18 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_946_p0,
din1 => grp_fu_946_p1,
ce => ap_const_logic_1,
dout => grp_fu_946_p2);
matrix_mult_mul_8bkb_U19 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_950_p0,
din1 => grp_fu_950_p1,
ce => ap_const_logic_1,
dout => grp_fu_950_p2);
matrix_mult_mul_8bkb_U20 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_970_p0,
din1 => grp_fu_970_p1,
ce => ap_const_logic_1,
dout => grp_fu_970_p2);
matrix_mult_mul_8bkb_U21 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_975_p0,
din1 => grp_fu_975_p1,
ce => ap_const_logic_1,
dout => grp_fu_975_p2);
matrix_mult_mul_8bkb_U22 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_980_p0,
din1 => grp_fu_980_p1,
ce => ap_const_logic_1,
dout => grp_fu_980_p2);
matrix_mult_mul_8bkb_U23 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_985_p0,
din1 => grp_fu_985_p1,
ce => ap_const_logic_1,
dout => grp_fu_985_p2);
matrix_mult_mul_8bkb_U24 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_769,
din1 => grp_fu_998_p1,
ce => ap_const_logic_1,
dout => grp_fu_998_p2);
matrix_mult_mul_8bkb_U25 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_774,
din1 => grp_fu_1008_p1,
ce => ap_const_logic_1,
dout => grp_fu_1008_p2);
matrix_mult_mul_8bkb_U26 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_792,
din1 => grp_fu_1018_p1,
ce => ap_const_logic_1,
dout => grp_fu_1018_p2);
matrix_mult_mul_8bkb_U27 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1032_p0,
din1 => grp_fu_1032_p1,
ce => ap_const_logic_1,
dout => grp_fu_1032_p2);
matrix_mult_mul_8bkb_U28 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_load_15_reg_1964,
din1 => grp_fu_1047_p1,
ce => ap_const_logic_1,
dout => grp_fu_1047_p2);
matrix_mult_mul_8bkb_U29 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_load_20_reg_1969,
din1 => grp_fu_1055_p1,
ce => ap_const_logic_1,
dout => grp_fu_1055_p2);
matrix_mult_mul_8bkb_U30 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1064_p0,
din1 => grp_fu_1064_p1,
ce => ap_const_logic_1,
dout => grp_fu_1064_p2);
matrix_mult_mul_8bkb_U31 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1069_p0,
din1 => grp_fu_1069_p1,
ce => ap_const_logic_1,
dout => grp_fu_1069_p2);
matrix_mult_mul_8bkb_U32 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1082_p0,
din1 => grp_fu_1082_p1,
ce => ap_const_logic_1,
dout => grp_fu_1082_p2);
matrix_mult_mul_8bkb_U33 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1086_p0,
din1 => grp_fu_1086_p1,
ce => ap_const_logic_1,
dout => grp_fu_1086_p2);
matrix_mult_mul_8bkb_U34 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1090_p0,
din1 => grp_fu_1090_p1,
ce => ap_const_logic_1,
dout => grp_fu_1090_p2);
matrix_mult_mul_8bkb_U35 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1098_p0,
din1 => reg_796,
ce => ap_const_logic_1,
dout => grp_fu_1098_p2);
matrix_mult_mul_8bkb_U36 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1127_p0,
din1 => grp_fu_1127_p1,
ce => ap_const_logic_1,
dout => grp_fu_1127_p2);
matrix_mult_mul_8bkb_U37 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1131_p0,
din1 => grp_fu_1131_p1,
ce => ap_const_logic_1,
dout => grp_fu_1131_p2);
matrix_mult_mul_8bkb_U38 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1135_p0,
din1 => grp_fu_1135_p1,
ce => ap_const_logic_1,
dout => grp_fu_1135_p2);
matrix_mult_mul_8bkb_U39 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1139_p0,
din1 => grp_fu_1139_p1,
ce => ap_const_logic_1,
dout => grp_fu_1139_p2);
matrix_mult_mul_8bkb_U40 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1163_p0,
din1 => grp_fu_1163_p1,
ce => ap_const_logic_1,
dout => grp_fu_1163_p2);
matrix_mult_mul_8bkb_U41 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1168_p0,
din1 => grp_fu_1168_p1,
ce => ap_const_logic_1,
dout => grp_fu_1168_p2);
matrix_mult_mul_8bkb_U42 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1173_p0,
din1 => grp_fu_1173_p1,
ce => ap_const_logic_1,
dout => grp_fu_1173_p2);
matrix_mult_mul_8bkb_U43 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1178_p0,
din1 => grp_fu_1178_p1,
ce => ap_const_logic_1,
dout => grp_fu_1178_p2);
matrix_mult_mul_8bkb_U44 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1191_p0,
din1 => grp_fu_1191_p1,
ce => ap_const_logic_1,
dout => grp_fu_1191_p2);
matrix_mult_mul_8bkb_U45 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1199_p0,
din1 => grp_fu_1199_p1,
ce => ap_const_logic_1,
dout => grp_fu_1199_p2);
matrix_mult_mul_8bkb_U46 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1204_p0,
din1 => grp_fu_1204_p1,
ce => ap_const_logic_1,
dout => grp_fu_1204_p2);
matrix_mult_mul_8bkb_U47 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1209_p0,
din1 => grp_fu_1209_p1,
ce => ap_const_logic_1,
dout => grp_fu_1209_p2);
matrix_mult_mul_8bkb_U48 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1230_p0,
din1 => grp_fu_1230_p1,
ce => ap_const_logic_1,
dout => grp_fu_1230_p2);
matrix_mult_mul_8bkb_U49 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1234_p0,
din1 => grp_fu_1234_p1,
ce => ap_const_logic_1,
dout => grp_fu_1234_p2);
matrix_mult_mac_mcud_U50 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1340_p0,
din1 => grp_fu_1340_p1,
din2 => tmp_2_0_0_3_reg_2003,
ce => ap_const_logic_1,
dout => grp_fu_1340_p3);
matrix_mult_mac_mcud_U51 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1347_p0,
din1 => grp_fu_1347_p1,
din2 => tmp_2_0_1_3_reg_2026,
ce => ap_const_logic_1,
dout => grp_fu_1347_p3);
matrix_mult_mac_mcud_U52 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1354_p0,
din1 => grp_fu_1354_p1,
din2 => tmp_2_1_0_3_reg_2040,
ce => ap_const_logic_1,
dout => grp_fu_1354_p3);
matrix_mult_mac_mcud_U53 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1361_p0,
din1 => grp_fu_1361_p1,
din2 => tmp_2_1_1_3_reg_2054,
ce => ap_const_logic_1,
dout => grp_fu_1361_p3);
matrix_mult_mac_mcud_U54 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1368_p0,
din1 => grp_fu_1368_p1,
din2 => tmp_2_0_2_3_reg_2079,
ce => ap_const_logic_1,
dout => grp_fu_1368_p3);
matrix_mult_mac_mcud_U55 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1374_p0,
din1 => grp_fu_1374_p1,
din2 => tmp_2_0_3_3_reg_2093,
ce => ap_const_logic_1,
dout => grp_fu_1374_p3);
matrix_mult_mac_mcud_U56 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1380_p0,
din1 => grp_fu_1380_p1,
din2 => tmp_2_1_2_3_reg_2107,
ce => ap_const_logic_1,
dout => grp_fu_1380_p3);
matrix_mult_mac_mcud_U57 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1386_p0,
din1 => grp_fu_1386_p1,
din2 => tmp_2_1_3_3_reg_2112,
ce => ap_const_logic_1,
dout => grp_fu_1386_p3);
matrix_mult_mac_mcud_U58 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1392_p0,
din1 => grp_fu_1392_p1,
din2 => tmp_2_2_0_3_reg_2230,
ce => ap_const_logic_1,
dout => grp_fu_1392_p3);
matrix_mult_mac_mcud_U59 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1398_p0,
din1 => grp_fu_1398_p1,
din2 => tmp_2_2_1_3_reg_2235,
ce => ap_const_logic_1,
dout => grp_fu_1398_p3);
matrix_mult_mac_mcud_U60 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1404_p0,
din1 => grp_fu_1404_p1,
din2 => tmp_2_0_4_3_reg_2201,
ce => ap_const_logic_1,
dout => grp_fu_1404_p3);
matrix_mult_mac_mcud_U61 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1410_p0,
din1 => grp_fu_1410_p1,
din2 => tmp_2_1_4_3_reg_2225,
ce => ap_const_logic_1,
dout => grp_fu_1410_p3);
matrix_mult_mac_mcud_U62 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1416_p0,
din1 => grp_fu_1416_p1,
din2 => tmp_2_2_2_3_reg_2344,
ce => ap_const_logic_1,
dout => grp_fu_1416_p3);
matrix_mult_mac_mcud_U63 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1421_p0,
din1 => grp_fu_1421_p1,
din2 => tmp_2_2_3_3_reg_2349,
ce => ap_const_logic_1,
dout => grp_fu_1421_p3);
matrix_mult_mac_mcud_U64 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1426_p0,
din1 => grp_fu_1426_p1,
din2 => tmp_2_2_4_3_reg_2354,
ce => ap_const_logic_1,
dout => grp_fu_1426_p3);
matrix_mult_mac_mcud_U65 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1432_p0,
din1 => reg_788,
din2 => tmp_2_3_0_3_reg_2359,
ce => ap_const_logic_1,
dout => grp_fu_1432_p3);
matrix_mult_mac_mdEe_U66 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => a_q0,
din2 => tmp2_reg_2173,
ce => ap_const_logic_1,
dout => grp_fu_1438_p3);
matrix_mult_mac_mcud_U67 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1445_p0,
din1 => grp_fu_1445_p1,
din2 => tmp_2_3_1_3_reg_2441,
ce => ap_const_logic_1,
dout => grp_fu_1445_p3);
matrix_mult_mac_mcud_U68 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1450_p0,
din1 => grp_fu_1450_p1,
din2 => tmp_2_3_2_3_reg_2446,
ce => ap_const_logic_1,
dout => grp_fu_1450_p3);
matrix_mult_mac_mcud_U69 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1455_p0,
din1 => grp_fu_1455_p1,
din2 => tmp_2_3_3_3_reg_2451,
ce => ap_const_logic_1,
dout => grp_fu_1455_p3);
matrix_mult_mac_mcud_U70 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1460_p0,
din1 => grp_fu_1460_p1,
din2 => tmp_2_3_4_3_reg_2456,
ce => ap_const_logic_1,
dout => grp_fu_1460_p3);
matrix_mult_mac_mdEe_U71 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1465_p1,
din2 => tmp5_reg_2187,
ce => ap_const_logic_1,
dout => grp_fu_1465_p3);
matrix_mult_mac_mdEe_U72 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1471_p0,
din1 => a_q0,
din2 => tmp17_reg_2215,
ce => ap_const_logic_1,
dout => grp_fu_1471_p3);
matrix_mult_mac_mcud_U73 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1477_p0,
din1 => grp_fu_1477_p1,
din2 => tmp_2_4_0_3_reg_2560,
ce => ap_const_logic_1,
dout => grp_fu_1477_p3);
matrix_mult_mac_mcud_U74 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1483_p0,
din1 => grp_fu_1483_p1,
din2 => tmp_2_4_1_3_reg_2565,
ce => ap_const_logic_1,
dout => grp_fu_1483_p3);
matrix_mult_mac_mcud_U75 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1489_p0,
din1 => grp_fu_1489_p1,
din2 => tmp_2_4_2_3_reg_2570,
ce => ap_const_logic_1,
dout => grp_fu_1489_p3);
matrix_mult_mac_mcud_U76 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1495_p0,
din1 => grp_fu_1495_p1,
din2 => tmp_2_4_3_3_reg_2575,
ce => ap_const_logic_1,
dout => grp_fu_1495_p3);
matrix_mult_mac_mcud_U77 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_769,
din1 => grp_fu_1501_p1,
din2 => tmp_2_reg_2590,
ce => ap_const_logic_1,
dout => grp_fu_1501_p3);
matrix_mult_mac_mcud_U78 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_774,
din1 => grp_fu_1508_p1,
din2 => tmp_2_0_1_reg_2595,
ce => ap_const_logic_1,
dout => grp_fu_1508_p3);
matrix_mult_mac_mcud_U79 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_792,
din1 => grp_fu_1515_p1,
din2 => tmp_2_0_2_reg_2605,
ce => ap_const_logic_1,
dout => grp_fu_1515_p3);
matrix_mult_mac_mdEe_U80 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1522_p1,
din2 => tmp8_reg_2287,
ce => ap_const_logic_1,
dout => grp_fu_1522_p3);
matrix_mult_mac_mdEe_U81 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1528_p0,
din1 => grp_fu_1528_p1,
din2 => tmp20_reg_2220,
ce => ap_const_logic_1,
dout => grp_fu_1528_p3);
matrix_mult_mac_mcud_U82 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1533_p0,
din1 => grp_fu_1533_p1,
din2 => tmp_2_4_4_3_reg_2690,
ce => ap_const_logic_1,
dout => grp_fu_1533_p3);
matrix_mult_mac_mcud_U83 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_769,
din1 => grp_fu_1538_p1,
din2 => tmp_2_0_3_reg_2715,
ce => ap_const_logic_1,
dout => grp_fu_1538_p3);
matrix_mult_mac_mdEe_U84 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1544_p1,
din2 => tmp11_reg_2301,
ce => ap_const_logic_1,
dout => grp_fu_1544_p3);
matrix_mult_mac_mcud_U85 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q1,
din1 => grp_fu_1550_p1,
din2 => tmp_2_0_4_reg_2720,
ce => ap_const_logic_1,
dout => grp_fu_1550_p3);
matrix_mult_mac_mcud_U86 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1556_p0,
din1 => grp_fu_1556_p1,
din2 => tmp_2_1_reg_2734,
ce => ap_const_logic_1,
dout => grp_fu_1556_p3);
matrix_mult_mac_mcud_U87 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1562_p0,
din1 => grp_fu_1562_p1,
din2 => tmp_2_1_1_reg_2739,
ce => ap_const_logic_1,
dout => grp_fu_1562_p3);
matrix_mult_mac_mdEe_U88 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1568_p0,
din1 => grp_fu_1568_p1,
din2 => tmp23_reg_2324,
ce => ap_const_logic_1,
dout => grp_fu_1568_p3);
matrix_mult_mac_mdEe_U89 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1573_p1,
din2 => tmp14_reg_2393,
ce => ap_const_logic_1,
dout => grp_fu_1573_p3);
matrix_mult_mac_mcud_U90 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1579_p0,
din1 => grp_fu_1579_p1,
din2 => tmp_2_1_2_reg_2812,
ce => ap_const_logic_1,
dout => grp_fu_1579_p3);
matrix_mult_mac_mcud_U91 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1584_p0,
din1 => grp_fu_1584_p1,
din2 => tmp_2_1_3_reg_2822,
ce => ap_const_logic_1,
dout => grp_fu_1584_p3);
matrix_mult_mac_mdEe_U92 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1589_p0,
din1 => grp_fu_1589_p1,
din2 => tmp26_reg_2329,
ce => ap_const_logic_1,
dout => grp_fu_1589_p3);
matrix_mult_mac_mcud_U93 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1594_p0,
din1 => grp_fu_1594_p1,
din2 => tmp_2_1_4_reg_2827,
ce => ap_const_logic_1,
dout => grp_fu_1594_p3);
matrix_mult_mac_mcud_U94 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1599_p0,
din1 => reg_788,
din2 => tmp_2_2_reg_2832,
ce => ap_const_logic_1,
dout => grp_fu_1599_p3);
matrix_mult_mac_mdEe_U95 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1605_p0,
din1 => grp_fu_1605_p1,
din2 => tmp29_reg_2407,
ce => ap_const_logic_1,
dout => grp_fu_1605_p3);
matrix_mult_mac_mdEe_U96 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1610_p0,
din1 => reg_784,
din2 => tmp32_reg_2334,
ce => ap_const_logic_1,
dout => grp_fu_1610_p3);
matrix_mult_mac_mcud_U97 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1616_p0,
din1 => grp_fu_1616_p1,
din2 => tmp_2_2_1_reg_2891,
ce => ap_const_logic_1,
dout => grp_fu_1616_p3);
matrix_mult_mac_mcud_U98 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1621_p0,
din1 => grp_fu_1621_p1,
din2 => tmp_2_2_2_reg_2896,
ce => ap_const_logic_1,
dout => grp_fu_1621_p3);
matrix_mult_mac_mcud_U99 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1626_p0,
din1 => grp_fu_1626_p1,
din2 => tmp_2_2_3_reg_2901,
ce => ap_const_logic_1,
dout => grp_fu_1626_p3);
matrix_mult_mac_mcud_U100 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1631_p0,
din1 => grp_fu_1631_p1,
din2 => tmp_2_2_4_reg_2906,
ce => ap_const_logic_1,
dout => grp_fu_1631_p3);
matrix_mult_mac_mdEe_U101 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1636_p0,
din1 => grp_fu_1636_p1,
din2 => tmp35_reg_2339,
ce => ap_const_logic_1,
dout => grp_fu_1636_p3);
matrix_mult_mac_mdEe_U102 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1641_p0,
din1 => grp_fu_1641_p1,
din2 => tmp38_reg_2421,
ce => ap_const_logic_1,
dout => grp_fu_1641_p3);
matrix_mult_mac_mcud_U103 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1646_p0,
din1 => grp_fu_1646_p1,
din2 => tmp_2_3_reg_2965,
ce => ap_const_logic_1,
dout => grp_fu_1646_p3);
matrix_mult_mac_mcud_U104 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1652_p0,
din1 => grp_fu_1652_p1,
din2 => tmp_2_3_1_reg_2970,
ce => ap_const_logic_1,
dout => grp_fu_1652_p3);
matrix_mult_mac_mcud_U105 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1658_p0,
din1 => grp_fu_1658_p1,
din2 => tmp_2_3_2_reg_2975,
ce => ap_const_logic_1,
dout => grp_fu_1658_p3);
matrix_mult_mac_mcud_U106 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1664_p0,
din1 => grp_fu_1664_p1,
din2 => tmp_2_3_3_reg_2980,
ce => ap_const_logic_1,
dout => grp_fu_1664_p3);
matrix_mult_mac_mdEe_U107 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1670_p0,
din1 => grp_fu_1670_p1,
din2 => tmp41_reg_2426,
ce => ap_const_logic_1,
dout => grp_fu_1670_p3);
matrix_mult_mac_mdEe_U108 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1675_p0,
din1 => grp_fu_1675_p1,
din2 => tmp44_reg_2431,
ce => ap_const_logic_1,
dout => grp_fu_1675_p3);
matrix_mult_mac_mcud_U109 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1680_p0,
din1 => grp_fu_1680_p1,
din2 => tmp_2_3_4_reg_3043,
ce => ap_const_logic_1,
dout => grp_fu_1680_p3);
matrix_mult_mac_mcud_U110 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1685_p0,
din1 => grp_fu_1685_p1,
din2 => tmp_2_4_reg_3048,
ce => ap_const_logic_1,
dout => grp_fu_1685_p3);
matrix_mult_mac_mcud_U111 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1691_p0,
din1 => grp_fu_1691_p1,
din2 => tmp_2_4_1_reg_3053,
ce => ap_const_logic_1,
dout => grp_fu_1691_p3);
matrix_mult_mac_mcud_U112 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1697_p0,
din1 => grp_fu_1697_p1,
din2 => tmp_2_4_2_reg_3058,
ce => ap_const_logic_1,
dout => grp_fu_1697_p3);
matrix_mult_mac_mdEe_U113 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1703_p0,
din1 => grp_fu_1703_p1,
din2 => tmp47_reg_2436,
ce => ap_const_logic_1,
dout => grp_fu_1703_p3);
matrix_mult_mac_mdEe_U114 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1709_p0,
din1 => grp_fu_1709_p1,
din2 => tmp50_reg_2540,
ce => ap_const_logic_1,
dout => grp_fu_1709_p3);
matrix_mult_mac_mdEe_U115 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1715_p0,
din1 => grp_fu_1715_p1,
din2 => tmp53_reg_2545,
ce => ap_const_logic_1,
dout => grp_fu_1715_p3);
matrix_mult_mac_mdEe_U116 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1721_p0,
din1 => grp_fu_1721_p1,
din2 => tmp56_reg_2550,
ce => ap_const_logic_1,
dout => grp_fu_1721_p3);
matrix_mult_mac_mcud_U117 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1727_p0,
din1 => grp_fu_1727_p1,
din2 => tmp_2_4_3_reg_3112,
ce => ap_const_logic_1,
dout => grp_fu_1727_p3);
matrix_mult_mac_mcud_U118 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1732_p0,
din1 => grp_fu_1732_p1,
din2 => tmp_2_4_4_reg_3117,
ce => ap_const_logic_1,
dout => grp_fu_1732_p3);
matrix_mult_mac_mdEe_U119 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1737_p0,
din1 => grp_fu_1737_p1,
din2 => tmp59_reg_2555,
ce => ap_const_logic_1,
dout => grp_fu_1737_p3);
matrix_mult_mac_mdEe_U120 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1742_p0,
din1 => grp_fu_1742_p1,
din2 => tmp62_reg_2670,
ce => ap_const_logic_1,
dout => grp_fu_1742_p3);
matrix_mult_mac_mdEe_U121 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1748_p0,
din1 => grp_fu_1748_p1,
din2 => tmp65_reg_2675,
ce => ap_const_logic_1,
dout => grp_fu_1748_p3);
matrix_mult_mac_mdEe_U122 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1754_p0,
din1 => grp_fu_1754_p1,
din2 => tmp68_reg_2680,
ce => ap_const_logic_1,
dout => grp_fu_1754_p3);
matrix_mult_mac_mdEe_U123 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1760_p0,
din1 => grp_fu_1760_p1,
din2 => tmp71_reg_2685,
ce => ap_const_logic_1,
dout => grp_fu_1760_p3);
matrix_mult_mac_mdEe_U124 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1766_p0,
din1 => grp_fu_1766_p1,
din2 => tmp74_reg_2767,
ce => ap_const_logic_1,
dout => grp_fu_1766_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0_reg <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
reg_764_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
reg_764 <= a_q1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)))) then
reg_764 <= a_q0;
end if;
end if;
end process;
reg_769_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
reg_769 <= b_q1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)))) then
reg_769 <= b_q0;
end if;
end if;
end process;
reg_774_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
reg_774 <= b_q0;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)))) then
reg_774 <= b_q1;
end if;
end if;
end process;
reg_779_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
reg_779 <= a_q0;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)))) then
reg_779 <= a_q1;
end if;
end if;
end process;
reg_800_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
reg_800 <= a_q0;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
reg_800 <= a_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
a_load_17_reg_2660 <= a_q0;
a_load_21_reg_2665 <= a_q1;
tmp16_reg_2646 <= grp_fu_1471_p3;
tmp4_reg_2600 <= grp_fu_1465_p3;
tmp62_reg_2670 <= grp_fu_1477_p3;
tmp65_reg_2675 <= grp_fu_1483_p3;
tmp68_reg_2680 <= grp_fu_1489_p3;
tmp71_reg_2685 <= grp_fu_1495_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
b_load_15_reg_1964 <= b_q0;
b_load_20_reg_1969 <= b_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)))) then
reg_784 <= a_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)))) then
reg_788 <= a_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)))) then
reg_792 <= b_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)))) then
reg_796 <= a_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp10_reg_2792 <= grp_fu_1544_p3;
tmp12_reg_2797 <= grp_fu_1550_p3;
tmp15_reg_2802 <= grp_fu_1556_p3;
tmp18_reg_2807 <= grp_fu_1562_p3;
tmp22_reg_2817 <= grp_fu_1568_p3;
tmp9_reg_2787 <= grp_fu_1538_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp11_reg_2301 <= grp_fu_1374_p3;
tmp23_reg_2324 <= grp_fu_1380_p3;
tmp26_reg_2329 <= grp_fu_1386_p3;
tmp32_reg_2334 <= grp_fu_1392_p3;
tmp35_reg_2339 <= grp_fu_1398_p3;
tmp8_reg_2287 <= grp_fu_1368_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp13_reg_2851 <= grp_fu_1573_p3;
tmp21_reg_2866 <= grp_fu_1579_p3;
tmp24_reg_2871 <= grp_fu_1584_p3;
tmp25_reg_2876 <= grp_fu_1589_p3;
tmp27_reg_2881 <= grp_fu_1594_p3;
tmp30_reg_2886 <= grp_fu_1599_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp14_reg_2393 <= grp_fu_1404_p3;
tmp29_reg_2407 <= grp_fu_1410_p3;
tmp38_reg_2421 <= grp_fu_1416_p3;
tmp41_reg_2426 <= grp_fu_1421_p3;
tmp44_reg_2431 <= grp_fu_1426_p3;
tmp47_reg_2436 <= grp_fu_1432_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp17_reg_2215 <= grp_fu_1354_p3;
tmp20_reg_2220 <= grp_fu_1361_p3;
tmp2_reg_2173 <= grp_fu_1340_p3;
tmp5_reg_2187 <= grp_fu_1347_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp19_reg_2744 <= grp_fu_1528_p3;
tmp3_reg_2700 <= grp_fu_1508_p3;
tmp6_reg_2705 <= grp_fu_1515_p3;
tmp74_reg_2767 <= grp_fu_1533_p3;
tmp7_reg_2710 <= grp_fu_1522_p3;
tmp_reg_2695 <= grp_fu_1501_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp1_reg_2508 <= grp_fu_1438_p3;
tmp50_reg_2540 <= grp_fu_1445_p3;
tmp53_reg_2545 <= grp_fu_1450_p3;
tmp56_reg_2550 <= grp_fu_1455_p3;
tmp59_reg_2555 <= grp_fu_1460_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp28_reg_2935 <= grp_fu_1605_p3;
tmp31_reg_2940 <= grp_fu_1610_p3;
tmp33_reg_2945 <= grp_fu_1616_p3;
tmp36_reg_2950 <= grp_fu_1621_p3;
tmp39_reg_2955 <= grp_fu_1626_p3;
tmp42_reg_2960 <= grp_fu_1631_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp34_reg_3004 <= grp_fu_1636_p3;
tmp37_reg_3009 <= grp_fu_1641_p3;
tmp45_reg_3023 <= grp_fu_1646_p3;
tmp48_reg_3028 <= grp_fu_1652_p3;
tmp51_reg_3033 <= grp_fu_1658_p3;
tmp54_reg_3038 <= grp_fu_1664_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp40_reg_3073 <= grp_fu_1670_p3;
tmp43_reg_3078 <= grp_fu_1675_p3;
tmp57_reg_3083 <= grp_fu_1680_p3;
tmp60_reg_3097 <= grp_fu_1685_p3;
tmp63_reg_3102 <= grp_fu_1691_p3;
tmp66_reg_3107 <= grp_fu_1697_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp46_reg_3132 <= grp_fu_1703_p3;
tmp49_reg_3137 <= grp_fu_1709_p3;
tmp52_reg_3142 <= grp_fu_1715_p3;
tmp55_reg_3147 <= grp_fu_1721_p3;
tmp69_reg_3152 <= grp_fu_1727_p3;
tmp72_reg_3157 <= grp_fu_1732_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp58_reg_3182 <= grp_fu_1737_p3;
tmp61_reg_3187 <= grp_fu_1742_p3;
tmp64_reg_3192 <= grp_fu_1748_p3;
tmp67_reg_3197 <= grp_fu_1754_p3;
tmp70_reg_3202 <= grp_fu_1760_p3;
tmp73_reg_3207 <= grp_fu_1766_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp75_reg_2155 <= tmp75_fu_990_p1;
tmp_1_0_1_reg_2178 <= tmp_1_0_1_fu_1004_p1;
tmp_1_0_2_reg_2192 <= tmp_1_0_2_fu_1014_p1;
tmp_1_0_4_4_reg_2206 <= tmp_1_0_4_4_fu_1024_p1;
tmp_1_reg_2164 <= tmp_1_fu_994_p1;
tmp_2_0_4_3_reg_2201 <= grp_fu_877_p2;
tmp_2_1_4_3_reg_2225 <= grp_fu_882_p2;
tmp_2_2_0_3_reg_2230 <= grp_fu_891_p2;
tmp_2_2_1_3_reg_2235 <= grp_fu_896_p2;
tmp_313_0_4_reg_2240 <= tmp_313_0_4_fu_1028_p1;
tmp_3_3_4_4_reg_3212 <= tmp_3_3_4_4_fu_1316_p2;
tmp_3_4_0_4_reg_3217 <= tmp_3_4_0_4_fu_1320_p2;
tmp_3_4_1_4_reg_3222 <= tmp_3_4_1_4_fu_1324_p2;
tmp_3_4_2_4_reg_3227 <= tmp_3_4_2_4_fu_1328_p2;
tmp_3_4_3_4_reg_3232 <= tmp_3_4_3_4_fu_1332_p2;
tmp_3_4_4_4_reg_3237 <= tmp_3_4_4_4_fu_1336_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_1_reg_2490 <= tmp_0_0_1_fu_1107_p1;
tmp_1_0_0_1_reg_2499 <= tmp_1_0_0_1_fu_1111_p1;
tmp_1_0_1_1_reg_2513 <= tmp_1_0_1_1_fu_1115_p1;
tmp_1_0_2_1_reg_2522 <= tmp_1_0_2_1_fu_1119_p1;
tmp_1_0_2_2_reg_2531 <= tmp_1_0_2_2_fu_1123_p1;
tmp_2_4_0_3_reg_2560 <= grp_fu_970_p2;
tmp_2_4_1_3_reg_2565 <= grp_fu_975_p2;
tmp_2_4_2_3_reg_2570 <= grp_fu_980_p2;
tmp_2_4_3_3_reg_2575 <= grp_fu_985_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_2_reg_2269 <= tmp_0_0_2_fu_1036_p1;
tmp_1_0_0_2_reg_2278 <= tmp_1_0_0_2_fu_1040_p1;
tmp_1_0_3_reg_2292 <= tmp_1_0_3_fu_1044_p1;
tmp_1_0_4_reg_2306 <= tmp_1_0_4_fu_1052_p1;
tmp_2_2_2_3_reg_2344 <= grp_fu_901_p2;
tmp_2_2_3_3_reg_2349 <= grp_fu_905_p2;
tmp_2_2_4_3_reg_2354 <= grp_fu_909_p2;
tmp_2_3_0_3_reg_2359 <= grp_fu_917_p2;
tmp_s_reg_2315 <= tmp_s_fu_1060_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_3_reg_1832 <= tmp_0_0_3_fu_805_p1;
tmp_111_0_3_reg_1859 <= tmp_111_0_3_fu_829_p1;
tmp_1_0_0_3_reg_1841 <= tmp_1_0_0_3_fu_809_p1;
tmp_1_0_1_3_reg_1850 <= tmp_1_0_1_3_fu_819_p1;
tmp_2_2_1_reg_2891 <= grp_fu_1127_p2;
tmp_2_2_2_reg_2896 <= grp_fu_1131_p2;
tmp_2_2_3_reg_2901 <= grp_fu_1135_p2;
tmp_2_2_4_reg_2906 <= grp_fu_1139_p2;
tmp_313_0_1_reg_2911 <= tmp_313_0_1_fu_1250_p1;
tmp_3_0_3_4_reg_2846 <= tmp_3_0_3_4_fu_1238_p2;
tmp_3_1_0_4_reg_2856 <= tmp_3_1_0_4_fu_1242_p2;
tmp_3_1_1_4_reg_2861 <= tmp_3_1_1_4_fu_1246_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_4_reg_2008 <= tmp_0_0_4_fu_922_p1;
tmp_111_0_4_reg_2045 <= tmp_111_0_4_fu_934_p1;
tmp_1_0_0_4_reg_2017 <= tmp_1_0_0_4_fu_926_p1;
tmp_1_0_1_4_reg_2031 <= tmp_1_0_1_4_fu_930_p1;
tmp_2_0_0_3_reg_2003 <= grp_fu_813_p2;
tmp_2_0_1_3_reg_2026 <= grp_fu_823_p2;
tmp_2_1_0_3_reg_2040 <= grp_fu_833_p2;
tmp_2_1_1_3_reg_2054 <= grp_fu_839_p2;
tmp_3_2_3_4_reg_3122 <= tmp_3_2_3_4_fu_1292_p2;
tmp_3_2_4_4_reg_3127 <= tmp_3_2_4_4_fu_1296_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
tmp_111_0_1_reg_2637 <= tmp_111_0_1_fu_1155_p1;
tmp_1_0_3_1_reg_2610 <= tmp_1_0_3_1_fu_1143_p1;
tmp_1_0_3_2_reg_2619 <= tmp_1_0_3_2_fu_1147_p1;
tmp_1_0_4_1_reg_2628 <= tmp_1_0_4_1_fu_1151_p1;
tmp_2_0_1_reg_2595 <= grp_fu_1008_p2;
tmp_2_0_2_reg_2605 <= grp_fu_1018_p2;
tmp_2_4_4_3_reg_2690 <= grp_fu_1032_p2;
tmp_2_reg_2590 <= grp_fu_998_p2;
tmp_5_reg_2651 <= tmp_5_fu_1159_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp_111_0_2_reg_2398 <= tmp_111_0_2_fu_1078_p1;
tmp_1_0_1_2_reg_2384 <= tmp_1_0_1_2_fu_1074_p1;
tmp_2_3_1_3_reg_2441 <= grp_fu_938_p2;
tmp_2_3_2_3_reg_2446 <= grp_fu_942_p2;
tmp_2_3_3_3_reg_2451 <= grp_fu_946_p2;
tmp_2_3_4_3_reg_2456 <= grp_fu_950_p2;
tmp_3_reg_2412 <= tmp_3_fu_1094_p1;
tmp_4_0_4_reg_2461 <= tmp_4_0_4_fu_1103_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_2_3_reg_1888 <= tmp_1_0_2_3_fu_845_p1;
tmp_1_0_3_3_reg_1897 <= tmp_1_0_3_3_fu_854_p1;
tmp_2_3_1_reg_2970 <= grp_fu_1168_p2;
tmp_2_3_2_reg_2975 <= grp_fu_1173_p2;
tmp_2_3_3_reg_2980 <= grp_fu_1178_p2;
tmp_2_3_reg_2965 <= grp_fu_1163_p2;
tmp_3_0_4_4_reg_2920 <= tmp_3_0_4_4_fu_1254_p2;
tmp_3_1_2_4_reg_2925 <= tmp_3_1_2_4_fu_1258_p2;
tmp_3_1_3_4_reg_2930 <= tmp_3_1_3_4_fu_1262_p2;
tmp_4_0_1_reg_2985 <= tmp_4_0_1_fu_1266_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_2_4_reg_2084 <= tmp_1_0_2_4_fu_954_p1;
tmp_1_0_3_4_reg_2098 <= tmp_1_0_3_4_fu_958_p1;
tmp_212_0_4_reg_2117 <= tmp_212_0_4_fu_962_p1;
tmp_2_0_2_3_reg_2079 <= grp_fu_849_p2;
tmp_2_0_3_3_reg_2093 <= grp_fu_858_p2;
tmp_2_1_2_3_reg_2107 <= grp_fu_863_p2;
tmp_2_1_3_3_reg_2112 <= grp_fu_868_p2;
tmp_3_3_0_4_reg_3162 <= tmp_3_3_0_4_fu_1300_p2;
tmp_3_3_1_4_reg_3167 <= tmp_3_3_1_4_fu_1304_p2;
tmp_3_3_2_4_reg_3172 <= tmp_3_3_2_4_fu_1308_p2;
tmp_3_3_3_4_reg_3177 <= tmp_3_3_3_4_fu_1312_p2;
tmp_4_0_3_reg_2126 <= tmp_4_0_3_fu_966_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_4_2_reg_2725 <= tmp_1_0_4_2_fu_1183_p1;
tmp_212_0_1_reg_2749 <= tmp_212_0_1_fu_1187_p1;
tmp_2_0_3_reg_2715 <= grp_fu_1047_p2;
tmp_2_0_4_reg_2720 <= grp_fu_1055_p2;
tmp_2_1_1_reg_2739 <= grp_fu_1069_p2;
tmp_2_1_reg_2734 <= grp_fu_1064_p2;
tmp_4_reg_2758 <= tmp_4_fu_1195_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_4_3_reg_1926 <= tmp_1_0_4_3_fu_873_p1;
tmp_212_0_3_reg_1935 <= tmp_212_0_3_fu_887_p1;
tmp_2_3_4_reg_3043 <= grp_fu_1191_p2;
tmp_2_4_1_reg_3053 <= grp_fu_1204_p2;
tmp_2_4_2_reg_3058 <= grp_fu_1209_p2;
tmp_2_4_reg_3048 <= grp_fu_1199_p2;
tmp_313_0_2_reg_3014 <= tmp_313_0_2_fu_1277_p1;
tmp_3_1_4_4_reg_2994 <= tmp_3_1_4_4_fu_1269_p2;
tmp_3_2_0_4_reg_2999 <= tmp_3_2_0_4_fu_1273_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_212_0_2_reg_2837 <= tmp_212_0_2_fu_1226_p1;
tmp_2_1_2_reg_2812 <= grp_fu_1082_p2;
tmp_2_1_3_reg_2822 <= grp_fu_1086_p2;
tmp_2_1_4_reg_2827 <= grp_fu_1090_p2;
tmp_2_2_reg_2832 <= grp_fu_1098_p2;
tmp_3_0_0_4_reg_2772 <= tmp_3_0_0_4_fu_1214_p2;
tmp_3_0_1_4_reg_2777 <= tmp_3_0_1_4_fu_1218_p2;
tmp_3_0_2_4_reg_2782 <= tmp_3_0_2_4_fu_1222_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
tmp_2_4_3_reg_3112 <= grp_fu_1230_p2;
tmp_2_4_4_reg_3117 <= grp_fu_1234_p2;
tmp_313_0_3_reg_1974 <= tmp_313_0_3_fu_913_p1;
tmp_3_2_1_4_reg_3063 <= tmp_3_2_1_4_fu_1280_p2;
tmp_3_2_2_4_reg_3068 <= tmp_3_2_2_4_fu_1284_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage0_flag00011011, ap_idle_pp0_1to2, ap_reset_idle_pp0, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_1to2))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if (((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (ap_reset_idle_pp0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
elsif (((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXX";
end case;
end process;
a_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_11(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_7(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_2(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_4(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_F(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_5(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_0(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_3(5 - 1 downto 0);
else
a_address0 <= "XXXXX";
end if;
else
a_address0 <= "XXXXX";
end if;
end process;
a_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_15(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_10(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_6(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_18(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_13(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_9(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_14(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_12(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_8(5 - 1 downto 0);
else
a_address1 <= "XXXXX";
end if;
else
a_address1 <= "XXXXX";
end if;
end process;
a_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
a_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
a_ce1 <= ap_const_logic_1;
else
a_ce1 <= ap_const_logic_0;
end if;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(10);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(9);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0));
end process;
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state20_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0_reg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0 <= ap_start;
else
ap_enable_reg_pp0_iter0 <= ap_enable_reg_pp0_iter0_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0_0to1 <= ap_const_logic_1;
else
ap_idle_pp0_0to1 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_1to2_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0_1to2 <= ap_const_logic_1;
else
ap_idle_pp0_1to2 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to1))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
b_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_5(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_14(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_3(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_0(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_11(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_F(5 - 1 downto 0);
else
b_address0 <= "XXXXX";
end if;
else
b_address0 <= "XXXXX";
end if;
end process;
b_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_9(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_8(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_7(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_6(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_18(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_15(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_4(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_2(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_13(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_12(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_10(5 - 1 downto 0);
else
b_address1 <= "XXXXX";
end if;
else
b_address1 <= "XXXXX";
end if;
end process;
b_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
b_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
b_ce1 <= ap_const_logic_1;
else
b_ce1 <= ap_const_logic_0;
end if;
end process;
grp_fu_1008_p1 <= tmp75_fu_990_p1(8 - 1 downto 0);
grp_fu_1018_p1 <= tmp75_fu_990_p1(8 - 1 downto 0);
grp_fu_1032_p0 <= tmp_1_0_4_3_reg_1926(8 - 1 downto 0);
grp_fu_1032_p1 <= tmp_4_0_3_reg_2126(8 - 1 downto 0);
grp_fu_1047_p1 <= tmp75_reg_2155(8 - 1 downto 0);
grp_fu_1055_p1 <= tmp75_reg_2155(8 - 1 downto 0);
grp_fu_1064_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1064_p1 <= tmp_s_fu_1060_p1(8 - 1 downto 0);
grp_fu_1069_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1069_p1 <= tmp_s_fu_1060_p1(8 - 1 downto 0);
grp_fu_1082_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1082_p1 <= tmp_s_reg_2315(8 - 1 downto 0);
grp_fu_1086_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1086_p1 <= tmp_s_reg_2315(8 - 1 downto 0);
grp_fu_1090_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1090_p1 <= tmp_s_reg_2315(8 - 1 downto 0);
grp_fu_1098_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1127_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1127_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1131_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1131_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1135_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1135_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1139_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1139_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1163_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1163_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1168_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1168_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1173_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1173_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1178_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1178_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1191_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1191_p1 <= tmp_5_reg_2651(8 - 1 downto 0);
grp_fu_1199_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1199_p1 <= tmp_4_fu_1195_p1(8 - 1 downto 0);
grp_fu_1204_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1204_p1 <= tmp_4_fu_1195_p1(8 - 1 downto 0);
grp_fu_1209_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1209_p1 <= tmp_4_fu_1195_p1(8 - 1 downto 0);
grp_fu_1230_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1230_p1 <= tmp_4_reg_2758(8 - 1 downto 0);
grp_fu_1234_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1234_p1 <= tmp_4_reg_2758(8 - 1 downto 0);
grp_fu_1340_p0 <= tmp_1_0_0_4_fu_926_p1(8 - 1 downto 0);
grp_fu_1340_p1 <= tmp_0_0_4_fu_922_p1(8 - 1 downto 0);
grp_fu_1347_p0 <= tmp_1_0_1_4_fu_930_p1(8 - 1 downto 0);
grp_fu_1347_p1 <= tmp_0_0_4_fu_922_p1(8 - 1 downto 0);
grp_fu_1354_p0 <= tmp_1_0_0_4_fu_926_p1(8 - 1 downto 0);
grp_fu_1354_p1 <= tmp_111_0_4_fu_934_p1(8 - 1 downto 0);
grp_fu_1361_p0 <= tmp_1_0_1_4_fu_930_p1(8 - 1 downto 0);
grp_fu_1361_p1 <= tmp_111_0_4_fu_934_p1(8 - 1 downto 0);
grp_fu_1368_p0 <= tmp_1_0_2_4_fu_954_p1(8 - 1 downto 0);
grp_fu_1368_p1 <= tmp_0_0_4_reg_2008(8 - 1 downto 0);
grp_fu_1374_p0 <= tmp_1_0_3_4_fu_958_p1(8 - 1 downto 0);
grp_fu_1374_p1 <= tmp_0_0_4_reg_2008(8 - 1 downto 0);
grp_fu_1380_p0 <= tmp_1_0_2_4_fu_954_p1(8 - 1 downto 0);
grp_fu_1380_p1 <= tmp_111_0_4_reg_2045(8 - 1 downto 0);
grp_fu_1386_p0 <= tmp_1_0_3_4_fu_958_p1(8 - 1 downto 0);
grp_fu_1386_p1 <= tmp_111_0_4_reg_2045(8 - 1 downto 0);
grp_fu_1392_p0 <= tmp_1_0_0_4_reg_2017(8 - 1 downto 0);
grp_fu_1392_p1 <= tmp_212_0_4_fu_962_p1(8 - 1 downto 0);
grp_fu_1398_p0 <= tmp_1_0_1_4_reg_2031(8 - 1 downto 0);
grp_fu_1398_p1 <= tmp_212_0_4_fu_962_p1(8 - 1 downto 0);
grp_fu_1404_p0 <= tmp_1_0_4_4_fu_1024_p1(8 - 1 downto 0);
grp_fu_1404_p1 <= tmp_0_0_4_reg_2008(8 - 1 downto 0);
grp_fu_1410_p0 <= tmp_1_0_4_4_fu_1024_p1(8 - 1 downto 0);
grp_fu_1410_p1 <= tmp_111_0_4_reg_2045(8 - 1 downto 0);
grp_fu_1416_p0 <= tmp_1_0_2_4_reg_2084(8 - 1 downto 0);
grp_fu_1416_p1 <= tmp_212_0_4_reg_2117(8 - 1 downto 0);
grp_fu_1421_p0 <= tmp_1_0_3_4_reg_2098(8 - 1 downto 0);
grp_fu_1421_p1 <= tmp_212_0_4_reg_2117(8 - 1 downto 0);
grp_fu_1426_p0 <= tmp_1_0_4_4_fu_1024_p1(8 - 1 downto 0);
grp_fu_1426_p1 <= tmp_212_0_4_reg_2117(8 - 1 downto 0);
grp_fu_1432_p0 <= tmp_1_0_0_4_reg_2017(8 - 1 downto 0);
grp_fu_1445_p0 <= tmp_1_0_1_4_reg_2031(8 - 1 downto 0);
grp_fu_1445_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1450_p0 <= tmp_1_0_2_4_reg_2084(8 - 1 downto 0);
grp_fu_1450_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1455_p0 <= tmp_1_0_3_4_reg_2098(8 - 1 downto 0);
grp_fu_1455_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1460_p0 <= tmp_1_0_4_4_reg_2206(8 - 1 downto 0);
grp_fu_1460_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1465_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1471_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1477_p0 <= tmp_1_0_0_4_reg_2017(8 - 1 downto 0);
grp_fu_1477_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1483_p0 <= tmp_1_0_1_4_reg_2031(8 - 1 downto 0);
grp_fu_1483_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1489_p0 <= tmp_1_0_2_4_reg_2084(8 - 1 downto 0);
grp_fu_1489_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1495_p0 <= tmp_1_0_3_4_reg_2098(8 - 1 downto 0);
grp_fu_1495_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1501_p1 <= tmp_0_0_1_fu_1107_p1(8 - 1 downto 0);
grp_fu_1508_p1 <= tmp_0_0_1_fu_1107_p1(8 - 1 downto 0);
grp_fu_1515_p1 <= tmp_0_0_1_fu_1107_p1(8 - 1 downto 0);
grp_fu_1522_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1528_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1528_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1533_p0 <= tmp_1_0_4_4_reg_2206(8 - 1 downto 0);
grp_fu_1533_p1 <= tmp_4_0_4_reg_2461(8 - 1 downto 0);
grp_fu_1538_p1 <= tmp_0_0_1_reg_2490(8 - 1 downto 0);
grp_fu_1544_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1550_p1 <= tmp_0_0_1_reg_2490(8 - 1 downto 0);
grp_fu_1556_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1556_p1 <= tmp_111_0_1_fu_1155_p1(8 - 1 downto 0);
grp_fu_1562_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1562_p1 <= tmp_111_0_1_fu_1155_p1(8 - 1 downto 0);
grp_fu_1568_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1568_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1573_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1579_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1579_p1 <= tmp_111_0_1_reg_2637(8 - 1 downto 0);
grp_fu_1584_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1584_p1 <= tmp_111_0_1_reg_2637(8 - 1 downto 0);
grp_fu_1589_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1589_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1594_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1594_p1 <= tmp_111_0_1_reg_2637(8 - 1 downto 0);
grp_fu_1599_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1605_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1605_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1610_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1616_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1616_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1621_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1621_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1626_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1626_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1631_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1631_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1636_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1636_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1641_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1641_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1646_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1646_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1652_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1652_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1658_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1658_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1664_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1664_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1670_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1670_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1675_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1675_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1680_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1680_p1 <= tmp_313_0_1_reg_2911(8 - 1 downto 0);
grp_fu_1685_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1685_p1 <= tmp_4_0_1_fu_1266_p1(8 - 1 downto 0);
grp_fu_1691_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1691_p1 <= tmp_4_0_1_fu_1266_p1(8 - 1 downto 0);
grp_fu_1697_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1697_p1 <= tmp_4_0_1_fu_1266_p1(8 - 1 downto 0);
grp_fu_1703_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1703_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1709_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1709_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1715_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1715_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1721_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1721_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1727_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1727_p1 <= tmp_4_0_1_reg_2985(8 - 1 downto 0);
grp_fu_1732_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1732_p1 <= tmp_4_0_1_reg_2985(8 - 1 downto 0);
grp_fu_1737_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1737_p1 <= tmp_313_0_2_reg_3014(8 - 1 downto 0);
grp_fu_1742_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1742_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1748_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1748_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1754_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1754_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1760_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1760_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1766_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1766_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_813_p0 <= tmp_1_0_0_3_fu_809_p1(8 - 1 downto 0);
grp_fu_813_p1 <= tmp_0_0_3_fu_805_p1(8 - 1 downto 0);
grp_fu_823_p0 <= tmp_1_0_1_3_fu_819_p1(8 - 1 downto 0);
grp_fu_823_p1 <= tmp_0_0_3_fu_805_p1(8 - 1 downto 0);
grp_fu_833_p0 <= tmp_1_0_0_3_fu_809_p1(8 - 1 downto 0);
grp_fu_833_p1 <= tmp_111_0_3_fu_829_p1(8 - 1 downto 0);
grp_fu_839_p0 <= tmp_1_0_1_3_fu_819_p1(8 - 1 downto 0);
grp_fu_839_p1 <= tmp_111_0_3_fu_829_p1(8 - 1 downto 0);
grp_fu_849_p0 <= tmp_1_0_2_3_fu_845_p1(8 - 1 downto 0);
grp_fu_849_p1 <= tmp_0_0_3_reg_1832(8 - 1 downto 0);
grp_fu_858_p0 <= tmp_1_0_3_3_fu_854_p1(8 - 1 downto 0);
grp_fu_858_p1 <= tmp_0_0_3_reg_1832(8 - 1 downto 0);
grp_fu_863_p0 <= tmp_1_0_2_3_fu_845_p1(8 - 1 downto 0);
grp_fu_863_p1 <= tmp_111_0_3_reg_1859(8 - 1 downto 0);
grp_fu_868_p0 <= tmp_1_0_3_3_fu_854_p1(8 - 1 downto 0);
grp_fu_868_p1 <= tmp_111_0_3_reg_1859(8 - 1 downto 0);
grp_fu_877_p0 <= tmp_1_0_4_3_fu_873_p1(8 - 1 downto 0);
grp_fu_877_p1 <= tmp_0_0_3_reg_1832(8 - 1 downto 0);
grp_fu_882_p0 <= tmp_1_0_4_3_fu_873_p1(8 - 1 downto 0);
grp_fu_882_p1 <= tmp_111_0_3_reg_1859(8 - 1 downto 0);
grp_fu_891_p0 <= tmp_1_0_0_3_reg_1841(8 - 1 downto 0);
grp_fu_891_p1 <= tmp_212_0_3_fu_887_p1(8 - 1 downto 0);
grp_fu_896_p0 <= tmp_1_0_1_3_reg_1850(8 - 1 downto 0);
grp_fu_896_p1 <= tmp_212_0_3_fu_887_p1(8 - 1 downto 0);
grp_fu_901_p0 <= tmp_1_0_2_3_reg_1888(8 - 1 downto 0);
grp_fu_901_p1 <= tmp_212_0_3_reg_1935(8 - 1 downto 0);
grp_fu_905_p0 <= tmp_1_0_3_3_reg_1897(8 - 1 downto 0);
grp_fu_905_p1 <= tmp_212_0_3_reg_1935(8 - 1 downto 0);
grp_fu_909_p0 <= tmp_1_0_4_3_reg_1926(8 - 1 downto 0);
grp_fu_909_p1 <= tmp_212_0_3_reg_1935(8 - 1 downto 0);
grp_fu_917_p0 <= tmp_1_0_0_3_reg_1841(8 - 1 downto 0);
grp_fu_938_p0 <= tmp_1_0_1_3_reg_1850(8 - 1 downto 0);
grp_fu_938_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_942_p0 <= tmp_1_0_2_3_reg_1888(8 - 1 downto 0);
grp_fu_942_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_946_p0 <= tmp_1_0_3_3_reg_1897(8 - 1 downto 0);
grp_fu_946_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_950_p0 <= tmp_1_0_4_3_reg_1926(8 - 1 downto 0);
grp_fu_950_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_970_p0 <= tmp_1_0_0_3_reg_1841(8 - 1 downto 0);
grp_fu_970_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_975_p0 <= tmp_1_0_1_3_reg_1850(8 - 1 downto 0);
grp_fu_975_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_980_p0 <= tmp_1_0_2_3_reg_1888(8 - 1 downto 0);
grp_fu_980_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_985_p0 <= tmp_1_0_3_3_reg_1897(8 - 1 downto 0);
grp_fu_985_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_998_p1 <= tmp75_fu_990_p1(8 - 1 downto 0);
prod_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_address0 <= ap_const_lv32_18(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_15(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_13(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_11(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_F(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_9(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_7(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_5(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_3(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_1(5 - 1 downto 0);
else
prod_address0 <= "XXXXX";
end if;
end process;
prod_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_14(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_12(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_10(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_8(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_6(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_4(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_2(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_0(5 - 1 downto 0);
else
prod_address1 <= "XXXXX";
end if;
end process;
prod_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_ce0 <= ap_const_logic_1;
else
prod_ce0 <= ap_const_logic_0;
end if;
end process;
prod_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_ce1 <= ap_const_logic_1;
else
prod_ce1 <= ap_const_logic_0;
end if;
end process;
prod_d0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, tmp_3_0_1_4_reg_2777, tmp_3_0_3_4_reg_2846, tmp_3_1_0_4_reg_2856, tmp_3_1_2_4_reg_2925, tmp_3_1_4_4_reg_2994, tmp_3_2_1_4_reg_3063, tmp_3_2_3_4_reg_3122, tmp_3_3_0_4_reg_3162, tmp_3_3_2_4_reg_3172, tmp_3_3_4_4_reg_3212, tmp_3_4_1_4_reg_3222, tmp_3_4_2_4_reg_3227, tmp_3_4_4_4_reg_3237, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_d0 <= tmp_3_4_4_4_reg_3237;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_d0 <= tmp_3_4_2_4_reg_3227;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_4_1_4_reg_3222;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_3_4_4_reg_3212;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_3_2_4_reg_3172;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_3_0_4_reg_3162;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_2_3_4_reg_3122;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_2_1_4_reg_3063;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_1_4_4_reg_2994;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_1_2_4_reg_2925;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_1_0_4_reg_2856;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_0_3_4_reg_2846;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_0_1_4_reg_2777;
else
prod_d0 <= "XXXXXXXXXXXXXXXX";
end if;
end process;
prod_d1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, tmp_3_0_0_4_reg_2772, tmp_3_0_2_4_reg_2782, tmp_3_1_1_4_reg_2861, tmp_3_0_4_4_reg_2920, tmp_3_1_3_4_reg_2930, tmp_3_2_0_4_reg_2999, tmp_3_2_2_4_reg_3068, tmp_3_2_4_4_reg_3127, tmp_3_3_1_4_reg_3167, tmp_3_3_3_4_reg_3177, tmp_3_4_0_4_reg_3217, tmp_3_4_3_4_reg_3232, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_d1 <= tmp_3_4_3_4_reg_3232;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_4_0_4_reg_3217;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_3_3_4_reg_3177;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_3_1_4_reg_3167;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_2_4_4_reg_3127;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_2_2_4_reg_3068;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_2_0_4_reg_2999;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_1_3_4_reg_2930;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_1_1_4_reg_2861;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_0_4_4_reg_2920;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_0_2_4_reg_2782;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_0_0_4_reg_2772;
else
prod_d1 <= "XXXXXXXXXXXXXXXX";
end if;
end process;
prod_we0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_we0 <= ap_const_logic_1;
else
prod_we0 <= ap_const_logic_0;
end if;
end process;
prod_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_we1 <= ap_const_logic_1;
else
prod_we1 <= ap_const_logic_0;
end if;
end process;
tmp75_fu_990_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_784),16));
tmp_0_0_1_fu_1107_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_784),16));
tmp_0_0_2_fu_1036_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_0_0_3_fu_805_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
tmp_0_0_4_fu_922_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_111_0_1_fu_1155_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
tmp_111_0_2_fu_1078_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_111_0_3_fu_829_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_779),16));
tmp_111_0_4_fu_934_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q1),16));
tmp_1_0_0_1_fu_1111_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_0_2_fu_1040_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_0_3_fu_809_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_0_4_fu_926_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_1_1_fu_1115_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_1_2_fu_1074_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_1_3_fu_819_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_1_4_fu_930_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_1_fu_1004_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_2_1_fu_1119_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_792),16));
tmp_1_0_2_2_fu_1123_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_2_3_fu_845_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_2_4_fu_954_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_2_fu_1014_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_792),16));
tmp_1_0_3_1_fu_1143_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_3_2_fu_1147_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_3_3_fu_854_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_3_4_fu_958_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_3_fu_1044_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_load_15_reg_1964),16));
tmp_1_0_4_1_fu_1151_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_4_2_fu_1183_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_4_3_fu_873_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_4_4_fu_1024_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_4_fu_1052_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_load_20_reg_1969),16));
tmp_1_fu_994_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_212_0_1_fu_1187_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_212_0_2_fu_1226_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_784),16));
tmp_212_0_3_fu_887_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
tmp_212_0_4_fu_962_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_313_0_1_fu_1250_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_796),16));
tmp_313_0_2_fu_1277_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_load_17_reg_2660),16));
tmp_313_0_3_fu_913_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_779),16));
tmp_313_0_4_fu_1028_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_3_0_0_4_fu_1214_p2 <= std_logic_vector(signed(tmp1_reg_2508) + signed(tmp_reg_2695));
tmp_3_0_1_4_fu_1218_p2 <= std_logic_vector(signed(tmp4_reg_2600) + signed(tmp3_reg_2700));
tmp_3_0_2_4_fu_1222_p2 <= std_logic_vector(signed(tmp7_reg_2710) + signed(tmp6_reg_2705));
tmp_3_0_3_4_fu_1238_p2 <= std_logic_vector(signed(tmp10_reg_2792) + signed(tmp9_reg_2787));
tmp_3_0_4_4_fu_1254_p2 <= std_logic_vector(signed(tmp13_reg_2851) + signed(tmp12_reg_2797));
tmp_3_1_0_4_fu_1242_p2 <= std_logic_vector(signed(tmp16_reg_2646) + signed(tmp15_reg_2802));
tmp_3_1_1_4_fu_1246_p2 <= std_logic_vector(signed(tmp19_reg_2744) + signed(tmp18_reg_2807));
tmp_3_1_2_4_fu_1258_p2 <= std_logic_vector(signed(tmp22_reg_2817) + signed(tmp21_reg_2866));
tmp_3_1_3_4_fu_1262_p2 <= std_logic_vector(signed(tmp25_reg_2876) + signed(tmp24_reg_2871));
tmp_3_1_4_4_fu_1269_p2 <= std_logic_vector(signed(tmp28_reg_2935) + signed(tmp27_reg_2881));
tmp_3_2_0_4_fu_1273_p2 <= std_logic_vector(signed(tmp31_reg_2940) + signed(tmp30_reg_2886));
tmp_3_2_1_4_fu_1280_p2 <= std_logic_vector(signed(tmp34_reg_3004) + signed(tmp33_reg_2945));
tmp_3_2_2_4_fu_1284_p2 <= std_logic_vector(signed(tmp37_reg_3009) + signed(tmp36_reg_2950));
tmp_3_2_3_4_fu_1292_p2 <= std_logic_vector(signed(tmp40_reg_3073) + signed(tmp39_reg_2955));
tmp_3_2_4_4_fu_1296_p2 <= std_logic_vector(signed(tmp43_reg_3078) + signed(tmp42_reg_2960));
tmp_3_3_0_4_fu_1300_p2 <= std_logic_vector(signed(tmp46_reg_3132) + signed(tmp45_reg_3023));
tmp_3_3_1_4_fu_1304_p2 <= std_logic_vector(signed(tmp49_reg_3137) + signed(tmp48_reg_3028));
tmp_3_3_2_4_fu_1308_p2 <= std_logic_vector(signed(tmp52_reg_3142) + signed(tmp51_reg_3033));
tmp_3_3_3_4_fu_1312_p2 <= std_logic_vector(signed(tmp55_reg_3147) + signed(tmp54_reg_3038));
tmp_3_3_4_4_fu_1316_p2 <= std_logic_vector(signed(tmp58_reg_3182) + signed(tmp57_reg_3083));
tmp_3_4_0_4_fu_1320_p2 <= std_logic_vector(signed(tmp61_reg_3187) + signed(tmp60_reg_3097));
tmp_3_4_1_4_fu_1324_p2 <= std_logic_vector(signed(tmp64_reg_3192) + signed(tmp63_reg_3102));
tmp_3_4_2_4_fu_1328_p2 <= std_logic_vector(signed(tmp67_reg_3197) + signed(tmp66_reg_3107));
tmp_3_4_3_4_fu_1332_p2 <= std_logic_vector(signed(tmp70_reg_3202) + signed(tmp69_reg_3152));
tmp_3_4_4_4_fu_1336_p2 <= std_logic_vector(signed(tmp73_reg_3207) + signed(tmp72_reg_3157));
tmp_3_fu_1094_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_796),16));
tmp_4_0_1_fu_1266_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_load_21_reg_2665),16));
tmp_4_0_2_fu_1288_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_800),16));
tmp_4_0_3_fu_966_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_4_0_4_fu_1103_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_4_fu_1195_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_800),16));
tmp_5_fu_1159_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_779),16));
tmp_s_fu_1060_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
end behav;
|
library verilog;
use verilog.vl_types.all;
entity ConditionCheck is
port(
Condition : in vl_logic_vector(2 downto 0);
Branch : in vl_logic;
RegWrite : in vl_logic;
Less : in vl_logic;
Zero : in vl_logic;
Overflow : in vl_logic;
BranchValid : out vl_logic;
RegWriteValid : out vl_logic
);
end ConditionCheck;
|
--- Entity Mor
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Mor IS
PORT (
A, B: IN STD_LOGIC;
R: OUT STD_LOGIC
);
END Mor;
ARCHITECTURE pure_logic OF Mor IS
BEGIN
R <= (A OR B);
END pure_logic;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo.vhd when simulating
-- the core, fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END fifo;
ARCHITECTURE fifo_a OF fifo IS
-- synthesis translate_off
COMPONENT wrapped_fifo
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 8,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "artix7",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "1kx18",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1022,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1021,
c_prog_full_type => 3,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh => prog_full_thresh,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full
);
-- synthesis translate_on
END fifo_a;
|
-- NEED RESULT: ARCH00645: The default expression is optional in a constant declaration for a formal generic of an entity passed
-- NEED RESULT: ARCH00645: The default expression is optional in a constant declaration for a formal parameter of a procedure passed
-- NEED RESULT: ARCH00645: The default expression is optional in a constant declaration for a formal generic of a block passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00645
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 4.3.3 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00645(ARCH00645)
-- ENT00645_Test_Bench(ARCH00645_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00645 is
generic ( constant G1 : in integer ;
constant G2, G3, G4 : in integer := 3 ) ;
end ENT00645 ;
--
architecture ARCH00645 of ENT00645 is
procedure Proc ( constant P1 : in integer ;
constant P2, P3, P4 : in integer := 3 ) is
begin
test_report ( "ARCH00645" ,
"The default expression is optional in a "&
"constant declaration for a formal parameter of "&
"a procedure" ,
(P1 = 1) and
(P2 = 2) and
(P3 = 3) and
(P4 = 4) ) ;
end Proc ;
begin
process
begin
test_report ( "ARCH00645" ,
"The default expression is optional in a "&
"constant declaration for a formal generic of "&
"an entity" ,
(G1 = 1) and
(G2 = 2) and
(G3 = 3) and
(G4 = 4) ) ;
Proc (P1 => G1, P2 => G2, P4 => G4) ;
wait ;
end process ;
L1 :
block
generic ( constant BG1 : in integer ;
constant BG2, BG3, BG4 : in integer := 3 ) ;
generic map ( G1, G2, BG4 => G4 ) ;
begin
process
begin
test_report ( "ARCH00645" ,
"The default expression is optional in a "&
"constant declaration for a formal generic of "&
"a block" ,
(BG1 = 1) and
(BG2 = 2) and
(BG3 = 3) and
(BG4 = 4) ) ;
wait ;
end process ;
end block L1 ;
end ARCH00645 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00645_Test_Bench is
end ENT00645_Test_Bench ;
architecture ARCH00645_Test_Bench of ENT00645_Test_Bench is
begin
L1:
block
component UUT
generic ( constant CG1 : in integer ;
constant CG2, CG4 : in integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00645 ( ARCH00645 )
generic map ( G1 => CG1,
G2 => CG2,
G4 => CG4 );
begin
CIS1 : UUT
generic map ( 1, 2, 4 );
end block L1 ;
end ARCH00645_Test_Bench ;
--
|
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